1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 38 #define DRV_NAME "hns_roce" 39 40 /* hip08 is a pci device, it includes two version according pci version id */ 41 #define PCI_REVISION_ID_HIP08_A 0x20 42 #define PCI_REVISION_ID_HIP08_B 0x21 43 44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 45 46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 47 48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 49 50 #define HNS_ROCE_BA_SIZE (32 * 4096) 51 52 #define BA_BYTE_LEN 8 53 54 /* Hardware specification only for v1 engine */ 55 #define HNS_ROCE_MIN_CQE_NUM 0x40 56 #define HNS_ROCE_MIN_WQE_NUM 0x20 57 58 /* Hardware specification only for v1 engine */ 59 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 60 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 61 #define HNS_ROCE_MAX_SGE_NUM 2 62 63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 65 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 67 #define HNS_ROCE_MIN_CQE_CNT 16 68 69 #define HNS_ROCE_RESERVED_SGE 1 70 71 #define HNS_ROCE_MAX_IRQ_NUM 128 72 73 #define HNS_ROCE_SGE_IN_WQE 2 74 #define HNS_ROCE_SGE_SHIFT 4 75 76 #define EQ_ENABLE 1 77 #define EQ_DISABLE 0 78 79 #define HNS_ROCE_CEQ 0 80 #define HNS_ROCE_AEQ 1 81 82 #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4 83 #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10 84 85 #define HNS_ROCE_SL_SHIFT 28 86 #define HNS_ROCE_TCLASS_SHIFT 20 87 #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff 88 89 #define HNS_ROCE_MAX_PORTS 6 90 #define HNS_ROCE_MAX_GID_NUM 16 91 #define HNS_ROCE_GID_SIZE 16 92 #define HNS_ROCE_SGE_SIZE 16 93 94 #define HNS_ROCE_HOP_NUM_0 0xff 95 96 #define BITMAP_NO_RR 0 97 #define BITMAP_RR 1 98 99 #define MR_TYPE_MR 0x00 100 #define MR_TYPE_FRMR 0x01 101 #define MR_TYPE_DMA 0x03 102 103 #define HNS_ROCE_FRMR_MAX_PA 512 104 105 #define PKEY_ID 0xffff 106 #define GUID_LEN 8 107 #define NODE_DESC_SIZE 64 108 #define DB_REG_OFFSET 0x1000 109 110 /* Configure to HW for PAGE_SIZE larger than 4KB */ 111 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 112 113 #define PAGES_SHIFT_8 8 114 #define PAGES_SHIFT_16 16 115 #define PAGES_SHIFT_24 24 116 #define PAGES_SHIFT_32 32 117 118 #define HNS_ROCE_PCI_BAR_NUM 2 119 120 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 121 #define SRQ_DB_REG 0x230 122 123 /* The chip implementation of the consumer index is calculated 124 * according to twice the actual EQ depth 125 */ 126 #define EQ_DEPTH_COEFF 2 127 128 enum { 129 SERV_TYPE_RC, 130 SERV_TYPE_UC, 131 SERV_TYPE_RD, 132 SERV_TYPE_UD, 133 }; 134 135 enum { 136 HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0), 137 HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1), 138 }; 139 140 enum hns_roce_cq_flags { 141 HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0), 142 }; 143 144 enum hns_roce_qp_state { 145 HNS_ROCE_QP_STATE_RST, 146 HNS_ROCE_QP_STATE_INIT, 147 HNS_ROCE_QP_STATE_RTR, 148 HNS_ROCE_QP_STATE_RTS, 149 HNS_ROCE_QP_STATE_SQD, 150 HNS_ROCE_QP_STATE_ERR, 151 HNS_ROCE_QP_NUM_STATE, 152 }; 153 154 enum hns_roce_event { 155 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 156 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 157 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 158 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 159 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 160 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 161 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 162 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 163 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 164 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 165 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 166 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 167 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 168 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 169 /* 0x10 and 0x11 is unused in currently application case */ 170 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 171 HNS_ROCE_EVENT_TYPE_MB = 0x13, 172 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 173 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 174 }; 175 176 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 177 enum { 178 HNS_ROCE_LWQCE_QPC_ERROR = 1, 179 HNS_ROCE_LWQCE_MTU_ERROR = 2, 180 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 181 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 182 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 183 HNS_ROCE_LWQCE_SL_ERROR = 6, 184 HNS_ROCE_LWQCE_PORT_ERROR = 7, 185 }; 186 187 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 188 enum { 189 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 190 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 191 HNS_ROCE_LAVWQE_VA_ERROR = 3, 192 HNS_ROCE_LAVWQE_PD_ERROR = 4, 193 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 194 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 195 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 196 }; 197 198 /* DOORBELL overflow subtype */ 199 enum { 200 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 201 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 202 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 203 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 204 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 205 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 206 }; 207 208 enum { 209 /* RQ&SRQ related operations */ 210 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 211 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 212 }; 213 214 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 215 216 enum { 217 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 218 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 219 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 220 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 221 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 222 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 223 HNS_ROCE_CAP_FLAG_MW = BIT(7), 224 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 225 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 226 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 227 }; 228 229 #define HNS_ROCE_DB_TYPE_COUNT 2 230 #define HNS_ROCE_DB_UNIT_SIZE 4 231 232 enum { 233 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 234 }; 235 236 enum hns_roce_reset_stage { 237 HNS_ROCE_STATE_NON_RST, 238 HNS_ROCE_STATE_RST_BEF_DOWN, 239 HNS_ROCE_STATE_RST_DOWN, 240 HNS_ROCE_STATE_RST_UNINIT, 241 HNS_ROCE_STATE_RST_INIT, 242 HNS_ROCE_STATE_RST_INITED, 243 }; 244 245 enum hns_roce_instance_state { 246 HNS_ROCE_STATE_NON_INIT, 247 HNS_ROCE_STATE_INIT, 248 HNS_ROCE_STATE_INITED, 249 HNS_ROCE_STATE_UNINIT, 250 }; 251 252 enum { 253 HNS_ROCE_RST_DIRECT_RETURN = 0, 254 }; 255 256 enum { 257 CMD_RST_PRC_OTHERS, 258 CMD_RST_PRC_SUCCESS, 259 CMD_RST_PRC_EBUSY, 260 }; 261 262 #define HNS_ROCE_CMD_SUCCESS 1 263 264 #define HNS_ROCE_PORT_DOWN 0 265 #define HNS_ROCE_PORT_UP 1 266 267 /* The minimum page size is 4K for hardware */ 268 #define HNS_HW_PAGE_SHIFT 12 269 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 270 271 /* The minimum page count for hardware access page directly. */ 272 #define HNS_HW_DIRECT_PAGE_COUNT 2 273 274 struct hns_roce_uar { 275 u64 pfn; 276 unsigned long index; 277 unsigned long logic_idx; 278 }; 279 280 struct hns_roce_ucontext { 281 struct ib_ucontext ibucontext; 282 struct hns_roce_uar uar; 283 struct list_head page_list; 284 struct mutex page_mutex; 285 }; 286 287 struct hns_roce_pd { 288 struct ib_pd ibpd; 289 unsigned long pdn; 290 }; 291 292 struct hns_roce_bitmap { 293 /* Bitmap Traversal last a bit which is 1 */ 294 unsigned long last; 295 unsigned long top; 296 unsigned long max; 297 unsigned long reserved_top; 298 unsigned long mask; 299 spinlock_t lock; 300 unsigned long *table; 301 }; 302 303 /* For Hardware Entry Memory */ 304 struct hns_roce_hem_table { 305 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 306 u32 type; 307 /* HEM array elment num */ 308 unsigned long num_hem; 309 /* HEM entry record obj total num */ 310 unsigned long num_obj; 311 /* Single obj size */ 312 unsigned long obj_size; 313 unsigned long table_chunk_size; 314 int lowmem; 315 struct mutex mutex; 316 struct hns_roce_hem **hem; 317 u64 **bt_l1; 318 dma_addr_t *bt_l1_dma_addr; 319 u64 **bt_l0; 320 dma_addr_t *bt_l0_dma_addr; 321 }; 322 323 struct hns_roce_buf_region { 324 int offset; /* page offset */ 325 u32 count; /* page count */ 326 int hopnum; /* addressing hop num */ 327 }; 328 329 #define HNS_ROCE_MAX_BT_REGION 3 330 #define HNS_ROCE_MAX_BT_LEVEL 3 331 struct hns_roce_hem_list { 332 struct list_head root_bt; 333 /* link all bt dma mem by hop config */ 334 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 335 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 336 dma_addr_t root_ba; /* pointer to the root ba table */ 337 }; 338 339 struct hns_roce_buf_attr { 340 struct { 341 size_t size; /* region size */ 342 int hopnum; /* multi-hop addressing hop num */ 343 } region[HNS_ROCE_MAX_BT_REGION]; 344 int region_count; /* valid region count */ 345 unsigned int page_shift; /* buffer page shift */ 346 bool fixed_page; /* decide page shift is fixed-size or maximum size */ 347 int user_access; /* umem access flag */ 348 bool mtt_only; /* only alloc buffer-required MTT memory */ 349 }; 350 351 /* memory translate region */ 352 struct hns_roce_mtr { 353 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 354 struct ib_umem *umem; /* user space buffer */ 355 struct hns_roce_buf *kmem; /* kernel space buffer */ 356 struct { 357 dma_addr_t root_ba; /* root BA table's address */ 358 bool is_direct; /* addressing without BA table */ 359 unsigned int ba_pg_shift; /* BA table page shift */ 360 unsigned int buf_pg_shift; /* buffer page shift */ 361 int buf_pg_count; /* buffer page count */ 362 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 363 unsigned int region_count; 364 } hem_cfg; /* config for hardware addressing */ 365 }; 366 367 struct hns_roce_mw { 368 struct ib_mw ibmw; 369 u32 pdn; 370 u32 rkey; 371 int enabled; /* MW's active status */ 372 u32 pbl_hop_num; 373 u32 pbl_ba_pg_sz; 374 u32 pbl_buf_pg_sz; 375 }; 376 377 /* Only support 4K page size for mr register */ 378 #define MR_SIZE_4K 0 379 380 struct hns_roce_mr { 381 struct ib_mr ibmr; 382 u64 iova; /* MR's virtual orignal addr */ 383 u64 size; /* Address range of MR */ 384 u32 key; /* Key of MR */ 385 u32 pd; /* PD num of MR */ 386 u32 access; /* Access permission of MR */ 387 int enabled; /* MR's active status */ 388 int type; /* MR's register type */ 389 u32 pbl_hop_num; /* multi-hop number */ 390 struct hns_roce_mtr pbl_mtr; 391 u32 npages; 392 dma_addr_t *page_list; 393 }; 394 395 struct hns_roce_mr_table { 396 struct hns_roce_bitmap mtpt_bitmap; 397 struct hns_roce_hem_table mtpt_table; 398 }; 399 400 struct hns_roce_wq { 401 u64 *wrid; /* Work request ID */ 402 spinlock_t lock; 403 u32 wqe_cnt; /* WQE num */ 404 int max_gs; 405 int offset; 406 int wqe_shift; /* WQE size */ 407 u32 head; 408 u32 tail; 409 void __iomem *db_reg_l; 410 }; 411 412 struct hns_roce_sge { 413 unsigned int sge_cnt; /* SGE num */ 414 int offset; 415 int sge_shift; /* SGE size */ 416 }; 417 418 struct hns_roce_buf_list { 419 void *buf; 420 dma_addr_t map; 421 }; 422 423 struct hns_roce_buf { 424 struct hns_roce_buf_list direct; 425 struct hns_roce_buf_list *page_list; 426 u32 npages; 427 u32 size; 428 unsigned int page_shift; 429 }; 430 431 struct hns_roce_db_pgdir { 432 struct list_head list; 433 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 434 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 435 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 436 u32 *page; 437 dma_addr_t db_dma; 438 }; 439 440 struct hns_roce_user_db_page { 441 struct list_head list; 442 struct ib_umem *umem; 443 unsigned long user_virt; 444 refcount_t refcount; 445 }; 446 447 struct hns_roce_db { 448 u32 *db_record; 449 union { 450 struct hns_roce_db_pgdir *pgdir; 451 struct hns_roce_user_db_page *user_page; 452 } u; 453 dma_addr_t dma; 454 void *virt_addr; 455 int index; 456 int order; 457 }; 458 459 struct hns_roce_cq { 460 struct ib_cq ib_cq; 461 struct hns_roce_mtr mtr; 462 struct hns_roce_db db; 463 u32 flags; 464 spinlock_t lock; 465 u32 cq_depth; 466 u32 cons_index; 467 u32 *set_ci_db; 468 void __iomem *cq_db_l; 469 u16 *tptr_addr; 470 int arm_sn; 471 unsigned long cqn; 472 u32 vector; 473 atomic_t refcount; 474 struct completion free; 475 struct list_head sq_list; /* all qps on this send cq */ 476 struct list_head rq_list; /* all qps on this recv cq */ 477 int is_armed; /* cq is armed */ 478 struct list_head node; /* all armed cqs are on a list */ 479 }; 480 481 struct hns_roce_idx_que { 482 struct hns_roce_mtr mtr; 483 int entry_shift; 484 unsigned long *bitmap; 485 }; 486 487 struct hns_roce_srq { 488 struct ib_srq ibsrq; 489 unsigned long srqn; 490 u32 wqe_cnt; 491 int max_gs; 492 int wqe_shift; 493 void __iomem *db_reg_l; 494 495 atomic_t refcount; 496 struct completion free; 497 498 struct hns_roce_mtr buf_mtr; 499 500 u64 *wrid; 501 struct hns_roce_idx_que idx_que; 502 spinlock_t lock; 503 int head; 504 int tail; 505 struct mutex mutex; 506 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 507 }; 508 509 struct hns_roce_uar_table { 510 struct hns_roce_bitmap bitmap; 511 }; 512 513 struct hns_roce_qp_table { 514 struct hns_roce_bitmap bitmap; 515 struct hns_roce_hem_table qp_table; 516 struct hns_roce_hem_table irrl_table; 517 struct hns_roce_hem_table trrl_table; 518 struct hns_roce_hem_table sccc_table; 519 struct mutex scc_mutex; 520 }; 521 522 struct hns_roce_cq_table { 523 struct hns_roce_bitmap bitmap; 524 struct xarray array; 525 struct hns_roce_hem_table table; 526 }; 527 528 struct hns_roce_srq_table { 529 struct hns_roce_bitmap bitmap; 530 struct xarray xa; 531 struct hns_roce_hem_table table; 532 }; 533 534 struct hns_roce_raq_table { 535 struct hns_roce_buf_list *e_raq_buf; 536 }; 537 538 struct hns_roce_av { 539 u8 port; 540 u8 gid_index; 541 u8 stat_rate; 542 u8 hop_limit; 543 u32 flowlabel; 544 u8 sl; 545 u8 tclass; 546 u8 dgid[HNS_ROCE_GID_SIZE]; 547 u8 mac[ETH_ALEN]; 548 u16 vlan_id; 549 bool vlan_en; 550 }; 551 552 struct hns_roce_ah { 553 struct ib_ah ibah; 554 struct hns_roce_av av; 555 }; 556 557 struct hns_roce_cmd_context { 558 struct completion done; 559 int result; 560 int next; 561 u64 out_param; 562 u16 token; 563 }; 564 565 struct hns_roce_cmdq { 566 struct dma_pool *pool; 567 struct mutex hcr_mutex; 568 struct semaphore poll_sem; 569 /* 570 * Event mode: cmd register mutex protection, 571 * ensure to not exceed max_cmds and user use limit region 572 */ 573 struct semaphore event_sem; 574 int max_cmds; 575 spinlock_t context_lock; 576 int free_head; 577 struct hns_roce_cmd_context *context; 578 /* 579 * Result of get integer part 580 * which max_comds compute according a power of 2 581 */ 582 u16 token_mask; 583 /* 584 * Process whether use event mode, init default non-zero 585 * After the event queue of cmd event ready, 586 * can switch into event mode 587 * close device, switch into poll mode(non event mode) 588 */ 589 u8 use_events; 590 }; 591 592 struct hns_roce_cmd_mailbox { 593 void *buf; 594 dma_addr_t dma; 595 }; 596 597 struct hns_roce_dev; 598 599 struct hns_roce_rinl_sge { 600 void *addr; 601 u32 len; 602 }; 603 604 struct hns_roce_rinl_wqe { 605 struct hns_roce_rinl_sge *sg_list; 606 u32 sge_cnt; 607 }; 608 609 struct hns_roce_rinl_buf { 610 struct hns_roce_rinl_wqe *wqe_list; 611 u32 wqe_cnt; 612 }; 613 614 enum { 615 HNS_ROCE_FLUSH_FLAG = 0, 616 }; 617 618 struct hns_roce_work { 619 struct hns_roce_dev *hr_dev; 620 struct work_struct work; 621 u32 qpn; 622 u32 cqn; 623 int event_type; 624 int sub_type; 625 }; 626 627 struct hns_roce_qp { 628 struct ib_qp ibqp; 629 struct hns_roce_wq rq; 630 struct hns_roce_db rdb; 631 struct hns_roce_db sdb; 632 unsigned long en_flags; 633 u32 doorbell_qpn; 634 u32 sq_signal_bits; 635 struct hns_roce_wq sq; 636 637 struct hns_roce_mtr mtr; 638 639 u32 buff_size; 640 struct mutex mutex; 641 u8 port; 642 u8 phy_port; 643 u8 sl; 644 u8 resp_depth; 645 u8 state; 646 u32 access_flags; 647 u32 atomic_rd_en; 648 u32 pkey_index; 649 u32 qkey; 650 void (*event)(struct hns_roce_qp *qp, 651 enum hns_roce_event event_type); 652 unsigned long qpn; 653 654 atomic_t refcount; 655 struct completion free; 656 657 struct hns_roce_sge sge; 658 u32 next_sge; 659 660 /* 0: flush needed, 1: unneeded */ 661 unsigned long flush_flag; 662 struct hns_roce_work flush_work; 663 struct hns_roce_rinl_buf rq_inl_buf; 664 struct list_head node; /* all qps are on a list */ 665 struct list_head rq_node; /* all recv qps are on a list */ 666 struct list_head sq_node; /* all send qps are on a list */ 667 }; 668 669 struct hns_roce_ib_iboe { 670 spinlock_t lock; 671 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 672 struct notifier_block nb; 673 u8 phy_port[HNS_ROCE_MAX_PORTS]; 674 }; 675 676 enum { 677 HNS_ROCE_EQ_STAT_INVALID = 0, 678 HNS_ROCE_EQ_STAT_VALID = 2, 679 }; 680 681 struct hns_roce_ceqe { 682 __le32 comp; 683 }; 684 685 struct hns_roce_aeqe { 686 __le32 asyn; 687 union { 688 struct { 689 __le32 qp; 690 u32 rsv0; 691 u32 rsv1; 692 } qp_event; 693 694 struct { 695 __le32 srq; 696 u32 rsv0; 697 u32 rsv1; 698 } srq_event; 699 700 struct { 701 __le32 cq; 702 u32 rsv0; 703 u32 rsv1; 704 } cq_event; 705 706 struct { 707 __le32 ceqe; 708 u32 rsv0; 709 u32 rsv1; 710 } ce_event; 711 712 struct { 713 __le64 out_param; 714 __le16 token; 715 u8 status; 716 u8 rsv0; 717 } __packed cmd; 718 } event; 719 }; 720 721 struct hns_roce_eq { 722 struct hns_roce_dev *hr_dev; 723 void __iomem *doorbell; 724 725 int type_flag; /* Aeq:1 ceq:0 */ 726 int eqn; 727 u32 entries; 728 int log_entries; 729 int eqe_size; 730 int irq; 731 int log_page_size; 732 int cons_index; 733 struct hns_roce_buf_list *buf_list; 734 int over_ignore; 735 int coalesce; 736 int arm_st; 737 int hop_num; 738 struct hns_roce_mtr mtr; 739 u16 eq_max_cnt; 740 int eq_period; 741 int shift; 742 int event_type; 743 int sub_type; 744 }; 745 746 struct hns_roce_eq_table { 747 struct hns_roce_eq *eq; 748 void __iomem **eqc_base; /* only for hw v1 */ 749 }; 750 751 struct hns_roce_caps { 752 u64 fw_ver; 753 u8 num_ports; 754 int gid_table_len[HNS_ROCE_MAX_PORTS]; 755 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 756 int local_ca_ack_delay; 757 int num_uars; 758 u32 phy_num_uars; 759 u32 max_sq_sg; 760 u32 max_sq_inline; 761 u32 max_rq_sg; 762 u32 max_extend_sg; 763 int num_qps; 764 int reserved_qps; 765 int num_qpc_timer; 766 int num_cqc_timer; 767 int num_srqs; 768 u32 max_wqes; 769 u32 max_srq_wrs; 770 u32 max_srq_sges; 771 u32 max_sq_desc_sz; 772 u32 max_rq_desc_sz; 773 u32 max_srq_desc_sz; 774 int max_qp_init_rdma; 775 int max_qp_dest_rdma; 776 int num_cqs; 777 u32 max_cqes; 778 u32 min_cqes; 779 u32 min_wqes; 780 int reserved_cqs; 781 int reserved_srqs; 782 int num_aeq_vectors; 783 int num_comp_vectors; 784 int num_other_vectors; 785 int num_mtpts; 786 u32 num_mtt_segs; 787 u32 num_cqe_segs; 788 u32 num_srqwqe_segs; 789 u32 num_idx_segs; 790 int reserved_mrws; 791 int reserved_uars; 792 int num_pds; 793 int reserved_pds; 794 u32 mtt_entry_sz; 795 u32 cq_entry_sz; 796 u32 page_size_cap; 797 u32 reserved_lkey; 798 int mtpt_entry_sz; 799 int qpc_entry_sz; 800 int irrl_entry_sz; 801 int trrl_entry_sz; 802 int cqc_entry_sz; 803 int sccc_entry_sz; 804 int qpc_timer_entry_sz; 805 int cqc_timer_entry_sz; 806 int srqc_entry_sz; 807 int idx_entry_sz; 808 u32 pbl_ba_pg_sz; 809 u32 pbl_buf_pg_sz; 810 u32 pbl_hop_num; 811 int aeqe_depth; 812 int ceqe_depth; 813 enum ib_mtu max_mtu; 814 u32 qpc_bt_num; 815 u32 qpc_timer_bt_num; 816 u32 srqc_bt_num; 817 u32 cqc_bt_num; 818 u32 cqc_timer_bt_num; 819 u32 mpt_bt_num; 820 u32 sccc_bt_num; 821 u32 qpc_ba_pg_sz; 822 u32 qpc_buf_pg_sz; 823 u32 qpc_hop_num; 824 u32 srqc_ba_pg_sz; 825 u32 srqc_buf_pg_sz; 826 u32 srqc_hop_num; 827 u32 cqc_ba_pg_sz; 828 u32 cqc_buf_pg_sz; 829 u32 cqc_hop_num; 830 u32 mpt_ba_pg_sz; 831 u32 mpt_buf_pg_sz; 832 u32 mpt_hop_num; 833 u32 mtt_ba_pg_sz; 834 u32 mtt_buf_pg_sz; 835 u32 mtt_hop_num; 836 u32 wqe_sq_hop_num; 837 u32 wqe_sge_hop_num; 838 u32 wqe_rq_hop_num; 839 u32 sccc_ba_pg_sz; 840 u32 sccc_buf_pg_sz; 841 u32 sccc_hop_num; 842 u32 qpc_timer_ba_pg_sz; 843 u32 qpc_timer_buf_pg_sz; 844 u32 qpc_timer_hop_num; 845 u32 cqc_timer_ba_pg_sz; 846 u32 cqc_timer_buf_pg_sz; 847 u32 cqc_timer_hop_num; 848 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 849 u32 cqe_buf_pg_sz; 850 u32 cqe_hop_num; 851 u32 srqwqe_ba_pg_sz; 852 u32 srqwqe_buf_pg_sz; 853 u32 srqwqe_hop_num; 854 u32 idx_ba_pg_sz; 855 u32 idx_buf_pg_sz; 856 u32 idx_hop_num; 857 u32 eqe_ba_pg_sz; 858 u32 eqe_buf_pg_sz; 859 u32 eqe_hop_num; 860 u32 sl_num; 861 u32 tsq_buf_pg_sz; 862 u32 tpq_buf_pg_sz; 863 u32 chunk_sz; /* chunk size in non multihop mode */ 864 u64 flags; 865 u16 default_ceq_max_cnt; 866 u16 default_ceq_period; 867 u16 default_aeq_max_cnt; 868 u16 default_aeq_period; 869 u16 default_aeq_arm_st; 870 u16 default_ceq_arm_st; 871 }; 872 873 struct hns_roce_dfx_hw { 874 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 875 int *buffer); 876 }; 877 878 enum hns_roce_device_state { 879 HNS_ROCE_DEVICE_STATE_INITED, 880 HNS_ROCE_DEVICE_STATE_RST_DOWN, 881 HNS_ROCE_DEVICE_STATE_UNINIT, 882 }; 883 884 struct hns_roce_hw { 885 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 886 int (*cmq_init)(struct hns_roce_dev *hr_dev); 887 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 888 int (*hw_profile)(struct hns_roce_dev *hr_dev); 889 int (*hw_init)(struct hns_roce_dev *hr_dev); 890 void (*hw_exit)(struct hns_roce_dev *hr_dev); 891 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 892 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 893 u16 token, int event); 894 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); 895 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); 896 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 897 const union ib_gid *gid, const struct ib_gid_attr *attr); 898 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 899 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 900 enum ib_mtu mtu); 901 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, 902 unsigned long mtpt_idx); 903 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 904 struct hns_roce_mr *mr, int flags, u32 pdn, 905 int mr_access_flags, u64 iova, u64 size, 906 void *mb_buf); 907 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 908 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 909 void (*write_cqc)(struct hns_roce_dev *hr_dev, 910 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 911 dma_addr_t dma_handle); 912 int (*set_hem)(struct hns_roce_dev *hr_dev, 913 struct hns_roce_hem_table *table, int obj, int step_idx); 914 int (*clear_hem)(struct hns_roce_dev *hr_dev, 915 struct hns_roce_hem_table *table, int obj, 916 int step_idx); 917 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 918 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 919 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 920 int attr_mask, enum ib_qp_state cur_state, 921 enum ib_qp_state new_state); 922 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); 923 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 924 struct hns_roce_qp *hr_qp); 925 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 926 const struct ib_send_wr **bad_wr); 927 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 928 const struct ib_recv_wr **bad_recv_wr); 929 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 930 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 931 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 932 struct ib_udata *udata); 933 void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 934 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 935 int (*init_eq)(struct hns_roce_dev *hr_dev); 936 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 937 void (*write_srqc)(struct hns_roce_dev *hr_dev, 938 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, 939 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, 940 dma_addr_t dma_handle_wqe, 941 dma_addr_t dma_handle_idx); 942 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 943 enum ib_srq_attr_mask srq_attr_mask, 944 struct ib_udata *udata); 945 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); 946 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 947 const struct ib_recv_wr **bad_wr); 948 const struct ib_device_ops *hns_roce_dev_ops; 949 const struct ib_device_ops *hns_roce_dev_srq_ops; 950 }; 951 952 struct hns_roce_dev { 953 struct ib_device ib_dev; 954 struct platform_device *pdev; 955 struct pci_dev *pci_dev; 956 struct device *dev; 957 struct hns_roce_uar priv_uar; 958 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 959 spinlock_t sm_lock; 960 spinlock_t bt_cmd_lock; 961 bool active; 962 bool is_reset; 963 bool dis_db; 964 unsigned long reset_cnt; 965 struct hns_roce_ib_iboe iboe; 966 enum hns_roce_device_state state; 967 struct list_head qp_list; /* list of all qps on this dev */ 968 spinlock_t qp_list_lock; /* protect qp_list */ 969 970 struct list_head pgdir_list; 971 struct mutex pgdir_mutex; 972 int irq[HNS_ROCE_MAX_IRQ_NUM]; 973 u8 __iomem *reg_base; 974 struct hns_roce_caps caps; 975 struct xarray qp_table_xa; 976 977 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 978 u64 sys_image_guid; 979 u32 vendor_id; 980 u32 vendor_part_id; 981 u32 hw_rev; 982 void __iomem *priv_addr; 983 984 struct hns_roce_cmdq cmd; 985 struct hns_roce_bitmap pd_bitmap; 986 struct hns_roce_uar_table uar_table; 987 struct hns_roce_mr_table mr_table; 988 struct hns_roce_cq_table cq_table; 989 struct hns_roce_srq_table srq_table; 990 struct hns_roce_qp_table qp_table; 991 struct hns_roce_eq_table eq_table; 992 struct hns_roce_hem_table qpc_timer_table; 993 struct hns_roce_hem_table cqc_timer_table; 994 995 int cmd_mod; 996 int loop_idc; 997 u32 sdb_offset; 998 u32 odb_offset; 999 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 1000 u32 tptr_size; /* only for hw v1 */ 1001 const struct hns_roce_hw *hw; 1002 void *priv; 1003 struct workqueue_struct *irq_workq; 1004 const struct hns_roce_dfx_hw *dfx; 1005 }; 1006 1007 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1008 { 1009 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1010 } 1011 1012 static inline struct hns_roce_ucontext 1013 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1014 { 1015 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1016 } 1017 1018 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1019 { 1020 return container_of(ibpd, struct hns_roce_pd, ibpd); 1021 } 1022 1023 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1024 { 1025 return container_of(ibah, struct hns_roce_ah, ibah); 1026 } 1027 1028 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1029 { 1030 return container_of(ibmr, struct hns_roce_mr, ibmr); 1031 } 1032 1033 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1034 { 1035 return container_of(ibmw, struct hns_roce_mw, ibmw); 1036 } 1037 1038 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1039 { 1040 return container_of(ibqp, struct hns_roce_qp, ibqp); 1041 } 1042 1043 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1044 { 1045 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1046 } 1047 1048 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1049 { 1050 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1051 } 1052 1053 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1054 { 1055 __raw_writeq(*(u64 *) val, dest); 1056 } 1057 1058 static inline struct hns_roce_qp 1059 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1060 { 1061 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1062 } 1063 1064 static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf) 1065 { 1066 if (buf->page_list) 1067 return false; 1068 1069 return true; 1070 } 1071 1072 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 1073 { 1074 if (hns_roce_buf_is_direct(buf)) 1075 return (char *)(buf->direct.buf) + (offset & (buf->size - 1)); 1076 1077 return (char *)(buf->page_list[offset >> buf->page_shift].buf) + 1078 (offset & ((1 << buf->page_shift) - 1)); 1079 } 1080 1081 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx) 1082 { 1083 if (hns_roce_buf_is_direct(buf)) 1084 return buf->direct.map + ((dma_addr_t)idx << buf->page_shift); 1085 else 1086 return buf->page_list[idx].map; 1087 } 1088 1089 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1090 1091 static inline u64 to_hr_hw_page_addr(u64 addr) 1092 { 1093 return addr >> HNS_HW_PAGE_SHIFT; 1094 } 1095 1096 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1097 { 1098 return page_shift - HNS_HW_PAGE_SHIFT; 1099 } 1100 1101 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1102 { 1103 if (count > 0) 1104 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1105 1106 return 0; 1107 } 1108 1109 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1110 { 1111 return hr_hw_page_align(count << buf_shift); 1112 } 1113 1114 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1115 { 1116 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1117 } 1118 1119 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1120 { 1121 if (!count) 1122 return 0; 1123 1124 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1125 } 1126 1127 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1128 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1129 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1130 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1131 1132 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1133 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1134 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1135 u64 out_param); 1136 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1137 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1138 1139 /* hns roce hw need current block and next block addr from mtt */ 1140 #define MTT_MIN_COUNT 2 1141 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1142 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1143 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1144 struct hns_roce_buf_attr *buf_attr, 1145 unsigned int page_shift, struct ib_udata *udata, 1146 unsigned long user_addr); 1147 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1148 struct hns_roce_mtr *mtr); 1149 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1150 dma_addr_t *pages, int page_cnt); 1151 1152 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1153 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1154 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1155 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1156 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1157 1158 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1159 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1160 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1161 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1162 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1163 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1164 1165 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1166 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1167 int rr); 1168 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1169 u32 reserved_bot, u32 resetrved_top); 1170 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1171 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1172 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1173 int align, unsigned long *obj); 1174 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1175 unsigned long obj, int cnt, 1176 int rr); 1177 1178 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1179 struct ib_udata *udata); 1180 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1181 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags); 1182 1183 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1184 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1185 1186 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1187 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1188 u64 virt_addr, int access_flags, 1189 struct ib_udata *udata); 1190 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, 1191 u64 virt_addr, int mr_access_flags, struct ib_pd *pd, 1192 struct ib_udata *udata); 1193 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1194 u32 max_num_sg, struct ib_udata *udata); 1195 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1196 unsigned int *sg_offset); 1197 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1198 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1199 struct hns_roce_cmd_mailbox *mailbox, 1200 unsigned long mpt_index); 1201 unsigned long key_to_hw_index(u32 key); 1202 1203 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type, 1204 struct ib_udata *udata); 1205 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1206 1207 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1208 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 1209 struct hns_roce_buf *buf, u32 page_shift); 1210 1211 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1212 int buf_cnt, int start, struct hns_roce_buf *buf); 1213 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1214 int buf_cnt, int start, struct ib_umem *umem, 1215 unsigned int page_shift); 1216 1217 int hns_roce_create_srq(struct ib_srq *srq, 1218 struct ib_srq_init_attr *srq_init_attr, 1219 struct ib_udata *udata); 1220 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1221 enum ib_srq_attr_mask srq_attr_mask, 1222 struct ib_udata *udata); 1223 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1224 1225 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1226 struct ib_qp_init_attr *init_attr, 1227 struct ib_udata *udata); 1228 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1229 int attr_mask, struct ib_udata *udata); 1230 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1231 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 1232 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n); 1233 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n); 1234 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1235 struct ib_cq *ib_cq); 1236 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1237 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1238 struct hns_roce_cq *recv_cq); 1239 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1240 struct hns_roce_cq *recv_cq); 1241 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1242 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1243 struct ib_udata *udata); 1244 __be32 send_ieth(const struct ib_send_wr *wr); 1245 int to_hr_qp_type(int qp_type); 1246 1247 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1248 struct ib_udata *udata); 1249 1250 void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1251 int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1252 struct ib_udata *udata, unsigned long virt, 1253 struct hns_roce_db *db); 1254 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1255 struct hns_roce_db *db); 1256 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1257 int order); 1258 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1259 1260 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1261 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1262 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1263 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1264 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1265 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1266 int hns_roce_init(struct hns_roce_dev *hr_dev); 1267 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1268 1269 int hns_roce_fill_res_entry(struct sk_buff *msg, 1270 struct rdma_restrack_entry *res); 1271 #endif /* _HNS_ROCE_DEVICE_H */ 1272