1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 38 #define DRV_NAME "hns_roce" 39 40 #define PCI_REVISION_ID_HIP08 0x21 41 #define PCI_REVISION_ID_HIP09 0x30 42 43 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 44 45 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 46 47 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 48 49 #define HNS_ROCE_BA_SIZE (32 * 4096) 50 51 #define BA_BYTE_LEN 8 52 53 /* Hardware specification only for v1 engine */ 54 #define HNS_ROCE_MIN_CQE_NUM 0x40 55 #define HNS_ROCE_MIN_WQE_NUM 0x20 56 57 /* Hardware specification only for v1 engine */ 58 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 59 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 60 61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 63 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 65 #define HNS_ROCE_MIN_CQE_CNT 16 66 67 #define HNS_ROCE_MAX_IRQ_NUM 128 68 69 #define HNS_ROCE_SGE_IN_WQE 2 70 #define HNS_ROCE_SGE_SHIFT 4 71 72 #define EQ_ENABLE 1 73 #define EQ_DISABLE 0 74 75 #define HNS_ROCE_CEQ 0 76 #define HNS_ROCE_AEQ 1 77 78 #define HNS_ROCE_CEQE_SIZE 0x4 79 #define HNS_ROCE_AEQE_SIZE 0x10 80 81 #define HNS_ROCE_V3_EQE_SIZE 0x40 82 83 #define HNS_ROCE_V2_CQE_SIZE 32 84 #define HNS_ROCE_V3_CQE_SIZE 64 85 86 #define HNS_ROCE_V2_QPC_SZ 256 87 #define HNS_ROCE_V3_QPC_SZ 512 88 89 #define HNS_ROCE_MAX_PORTS 6 90 #define HNS_ROCE_GID_SIZE 16 91 #define HNS_ROCE_SGE_SIZE 16 92 93 #define HNS_ROCE_HOP_NUM_0 0xff 94 95 #define BITMAP_NO_RR 0 96 #define BITMAP_RR 1 97 98 #define MR_TYPE_MR 0x00 99 #define MR_TYPE_FRMR 0x01 100 #define MR_TYPE_DMA 0x03 101 102 #define HNS_ROCE_FRMR_MAX_PA 512 103 104 #define PKEY_ID 0xffff 105 #define GUID_LEN 8 106 #define NODE_DESC_SIZE 64 107 #define DB_REG_OFFSET 0x1000 108 109 /* Configure to HW for PAGE_SIZE larger than 4KB */ 110 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 111 112 #define PAGES_SHIFT_8 8 113 #define PAGES_SHIFT_16 16 114 #define PAGES_SHIFT_24 24 115 #define PAGES_SHIFT_32 32 116 117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 118 #define SRQ_DB_REG 0x230 119 120 /* The chip implementation of the consumer index is calculated 121 * according to twice the actual EQ depth 122 */ 123 #define EQ_DEPTH_COEFF 2 124 125 enum { 126 SERV_TYPE_RC, 127 SERV_TYPE_UC, 128 SERV_TYPE_RD, 129 SERV_TYPE_UD, 130 }; 131 132 enum { 133 HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0), 134 HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1), 135 }; 136 137 enum hns_roce_cq_flags { 138 HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0), 139 }; 140 141 enum hns_roce_qp_state { 142 HNS_ROCE_QP_STATE_RST, 143 HNS_ROCE_QP_STATE_INIT, 144 HNS_ROCE_QP_STATE_RTR, 145 HNS_ROCE_QP_STATE_RTS, 146 HNS_ROCE_QP_STATE_SQD, 147 HNS_ROCE_QP_STATE_ERR, 148 HNS_ROCE_QP_NUM_STATE, 149 }; 150 151 enum hns_roce_event { 152 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 153 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 154 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 155 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 156 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 157 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 158 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 159 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 160 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 161 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 162 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 163 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 164 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 165 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 166 /* 0x10 and 0x11 is unused in currently application case */ 167 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 168 HNS_ROCE_EVENT_TYPE_MB = 0x13, 169 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 170 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 171 }; 172 173 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 174 enum { 175 HNS_ROCE_LWQCE_QPC_ERROR = 1, 176 HNS_ROCE_LWQCE_MTU_ERROR = 2, 177 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 178 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 179 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 180 HNS_ROCE_LWQCE_SL_ERROR = 6, 181 HNS_ROCE_LWQCE_PORT_ERROR = 7, 182 }; 183 184 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 185 enum { 186 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 187 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 188 HNS_ROCE_LAVWQE_VA_ERROR = 3, 189 HNS_ROCE_LAVWQE_PD_ERROR = 4, 190 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 191 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 192 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 193 }; 194 195 /* DOORBELL overflow subtype */ 196 enum { 197 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 198 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 199 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 200 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 201 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 202 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 203 }; 204 205 enum { 206 /* RQ&SRQ related operations */ 207 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 208 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 209 }; 210 211 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 212 213 enum { 214 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 215 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 216 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 217 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 218 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 219 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 220 HNS_ROCE_CAP_FLAG_MW = BIT(7), 221 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 222 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 223 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 224 }; 225 226 #define HNS_ROCE_DB_TYPE_COUNT 2 227 #define HNS_ROCE_DB_UNIT_SIZE 4 228 229 enum { 230 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 231 }; 232 233 enum hns_roce_reset_stage { 234 HNS_ROCE_STATE_NON_RST, 235 HNS_ROCE_STATE_RST_BEF_DOWN, 236 HNS_ROCE_STATE_RST_DOWN, 237 HNS_ROCE_STATE_RST_UNINIT, 238 HNS_ROCE_STATE_RST_INIT, 239 HNS_ROCE_STATE_RST_INITED, 240 }; 241 242 enum hns_roce_instance_state { 243 HNS_ROCE_STATE_NON_INIT, 244 HNS_ROCE_STATE_INIT, 245 HNS_ROCE_STATE_INITED, 246 HNS_ROCE_STATE_UNINIT, 247 }; 248 249 enum { 250 HNS_ROCE_RST_DIRECT_RETURN = 0, 251 }; 252 253 enum { 254 CMD_RST_PRC_OTHERS, 255 CMD_RST_PRC_SUCCESS, 256 CMD_RST_PRC_EBUSY, 257 }; 258 259 #define HNS_ROCE_CMD_SUCCESS 1 260 261 #define HNS_ROCE_PORT_DOWN 0 262 #define HNS_ROCE_PORT_UP 1 263 264 /* The minimum page size is 4K for hardware */ 265 #define HNS_HW_PAGE_SHIFT 12 266 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 267 268 /* The minimum page count for hardware access page directly. */ 269 #define HNS_HW_DIRECT_PAGE_COUNT 2 270 271 struct hns_roce_uar { 272 u64 pfn; 273 unsigned long index; 274 unsigned long logic_idx; 275 }; 276 277 struct hns_roce_ucontext { 278 struct ib_ucontext ibucontext; 279 struct hns_roce_uar uar; 280 struct list_head page_list; 281 struct mutex page_mutex; 282 }; 283 284 struct hns_roce_pd { 285 struct ib_pd ibpd; 286 unsigned long pdn; 287 }; 288 289 struct hns_roce_bitmap { 290 /* Bitmap Traversal last a bit which is 1 */ 291 unsigned long last; 292 unsigned long top; 293 unsigned long max; 294 unsigned long reserved_top; 295 unsigned long mask; 296 spinlock_t lock; 297 unsigned long *table; 298 }; 299 300 /* For Hardware Entry Memory */ 301 struct hns_roce_hem_table { 302 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 303 u32 type; 304 /* HEM array elment num */ 305 unsigned long num_hem; 306 /* HEM entry record obj total num */ 307 unsigned long num_obj; 308 /* Single obj size */ 309 unsigned long obj_size; 310 unsigned long table_chunk_size; 311 int lowmem; 312 struct mutex mutex; 313 struct hns_roce_hem **hem; 314 u64 **bt_l1; 315 dma_addr_t *bt_l1_dma_addr; 316 u64 **bt_l0; 317 dma_addr_t *bt_l0_dma_addr; 318 }; 319 320 struct hns_roce_buf_region { 321 int offset; /* page offset */ 322 u32 count; /* page count */ 323 int hopnum; /* addressing hop num */ 324 }; 325 326 #define HNS_ROCE_MAX_BT_REGION 3 327 #define HNS_ROCE_MAX_BT_LEVEL 3 328 struct hns_roce_hem_list { 329 struct list_head root_bt; 330 /* link all bt dma mem by hop config */ 331 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 332 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 333 dma_addr_t root_ba; /* pointer to the root ba table */ 334 }; 335 336 struct hns_roce_buf_attr { 337 struct { 338 size_t size; /* region size */ 339 int hopnum; /* multi-hop addressing hop num */ 340 } region[HNS_ROCE_MAX_BT_REGION]; 341 int region_count; /* valid region count */ 342 unsigned int page_shift; /* buffer page shift */ 343 bool fixed_page; /* decide page shift is fixed-size or maximum size */ 344 int user_access; /* umem access flag */ 345 bool mtt_only; /* only alloc buffer-required MTT memory */ 346 }; 347 348 struct hns_roce_hem_cfg { 349 dma_addr_t root_ba; /* root BA table's address */ 350 bool is_direct; /* addressing without BA table */ 351 unsigned int ba_pg_shift; /* BA table page shift */ 352 unsigned int buf_pg_shift; /* buffer page shift */ 353 unsigned int buf_pg_count; /* buffer page count */ 354 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 355 int region_count; 356 }; 357 358 /* memory translate region */ 359 struct hns_roce_mtr { 360 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 361 struct ib_umem *umem; /* user space buffer */ 362 struct hns_roce_buf *kmem; /* kernel space buffer */ 363 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 364 }; 365 366 struct hns_roce_mw { 367 struct ib_mw ibmw; 368 u32 pdn; 369 u32 rkey; 370 int enabled; /* MW's active status */ 371 u32 pbl_hop_num; 372 u32 pbl_ba_pg_sz; 373 u32 pbl_buf_pg_sz; 374 }; 375 376 /* Only support 4K page size for mr register */ 377 #define MR_SIZE_4K 0 378 379 struct hns_roce_mr { 380 struct ib_mr ibmr; 381 u64 iova; /* MR's virtual orignal addr */ 382 u64 size; /* Address range of MR */ 383 u32 key; /* Key of MR */ 384 u32 pd; /* PD num of MR */ 385 u32 access; /* Access permission of MR */ 386 int enabled; /* MR's active status */ 387 int type; /* MR's register type */ 388 u32 pbl_hop_num; /* multi-hop number */ 389 struct hns_roce_mtr pbl_mtr; 390 u32 npages; 391 dma_addr_t *page_list; 392 }; 393 394 struct hns_roce_mr_table { 395 struct hns_roce_bitmap mtpt_bitmap; 396 struct hns_roce_hem_table mtpt_table; 397 }; 398 399 struct hns_roce_wq { 400 u64 *wrid; /* Work request ID */ 401 spinlock_t lock; 402 u32 wqe_cnt; /* WQE num */ 403 int max_gs; 404 int offset; 405 int wqe_shift; /* WQE size */ 406 u32 head; 407 u32 tail; 408 void __iomem *db_reg_l; 409 }; 410 411 struct hns_roce_sge { 412 unsigned int sge_cnt; /* SGE num */ 413 int offset; 414 int sge_shift; /* SGE size */ 415 }; 416 417 struct hns_roce_buf_list { 418 void *buf; 419 dma_addr_t map; 420 }; 421 422 struct hns_roce_buf { 423 struct hns_roce_buf_list direct; 424 struct hns_roce_buf_list *page_list; 425 u32 npages; 426 u32 size; 427 unsigned int page_shift; 428 }; 429 430 struct hns_roce_db_pgdir { 431 struct list_head list; 432 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 433 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 434 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 435 u32 *page; 436 dma_addr_t db_dma; 437 }; 438 439 struct hns_roce_user_db_page { 440 struct list_head list; 441 struct ib_umem *umem; 442 unsigned long user_virt; 443 refcount_t refcount; 444 }; 445 446 struct hns_roce_db { 447 u32 *db_record; 448 union { 449 struct hns_roce_db_pgdir *pgdir; 450 struct hns_roce_user_db_page *user_page; 451 } u; 452 dma_addr_t dma; 453 void *virt_addr; 454 int index; 455 int order; 456 }; 457 458 struct hns_roce_cq { 459 struct ib_cq ib_cq; 460 struct hns_roce_mtr mtr; 461 struct hns_roce_db db; 462 u32 flags; 463 spinlock_t lock; 464 u32 cq_depth; 465 u32 cons_index; 466 u32 *set_ci_db; 467 void __iomem *cq_db_l; 468 u16 *tptr_addr; 469 int arm_sn; 470 int cqe_size; 471 unsigned long cqn; 472 u32 vector; 473 atomic_t refcount; 474 struct completion free; 475 struct list_head sq_list; /* all qps on this send cq */ 476 struct list_head rq_list; /* all qps on this recv cq */ 477 int is_armed; /* cq is armed */ 478 struct list_head node; /* all armed cqs are on a list */ 479 }; 480 481 struct hns_roce_idx_que { 482 struct hns_roce_mtr mtr; 483 int entry_shift; 484 unsigned long *bitmap; 485 }; 486 487 struct hns_roce_srq { 488 struct ib_srq ibsrq; 489 unsigned long srqn; 490 u32 wqe_cnt; 491 int max_gs; 492 int wqe_shift; 493 void __iomem *db_reg_l; 494 495 atomic_t refcount; 496 struct completion free; 497 498 struct hns_roce_mtr buf_mtr; 499 500 u64 *wrid; 501 struct hns_roce_idx_que idx_que; 502 spinlock_t lock; 503 int head; 504 int tail; 505 struct mutex mutex; 506 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 507 }; 508 509 struct hns_roce_uar_table { 510 struct hns_roce_bitmap bitmap; 511 }; 512 513 struct hns_roce_qp_table { 514 struct hns_roce_bitmap bitmap; 515 struct hns_roce_hem_table qp_table; 516 struct hns_roce_hem_table irrl_table; 517 struct hns_roce_hem_table trrl_table; 518 struct hns_roce_hem_table sccc_table; 519 struct mutex scc_mutex; 520 }; 521 522 struct hns_roce_cq_table { 523 struct hns_roce_bitmap bitmap; 524 struct xarray array; 525 struct hns_roce_hem_table table; 526 }; 527 528 struct hns_roce_srq_table { 529 struct hns_roce_bitmap bitmap; 530 struct xarray xa; 531 struct hns_roce_hem_table table; 532 }; 533 534 struct hns_roce_raq_table { 535 struct hns_roce_buf_list *e_raq_buf; 536 }; 537 538 struct hns_roce_av { 539 u8 port; 540 u8 gid_index; 541 u8 stat_rate; 542 u8 hop_limit; 543 u32 flowlabel; 544 u16 udp_sport; 545 u8 sl; 546 u8 tclass; 547 u8 dgid[HNS_ROCE_GID_SIZE]; 548 u8 mac[ETH_ALEN]; 549 u16 vlan_id; 550 bool vlan_en; 551 }; 552 553 struct hns_roce_ah { 554 struct ib_ah ibah; 555 struct hns_roce_av av; 556 }; 557 558 struct hns_roce_cmd_context { 559 struct completion done; 560 int result; 561 int next; 562 u64 out_param; 563 u16 token; 564 }; 565 566 struct hns_roce_cmdq { 567 struct dma_pool *pool; 568 struct mutex hcr_mutex; 569 struct semaphore poll_sem; 570 /* 571 * Event mode: cmd register mutex protection, 572 * ensure to not exceed max_cmds and user use limit region 573 */ 574 struct semaphore event_sem; 575 int max_cmds; 576 spinlock_t context_lock; 577 int free_head; 578 struct hns_roce_cmd_context *context; 579 /* 580 * Result of get integer part 581 * which max_comds compute according a power of 2 582 */ 583 u16 token_mask; 584 /* 585 * Process whether use event mode, init default non-zero 586 * After the event queue of cmd event ready, 587 * can switch into event mode 588 * close device, switch into poll mode(non event mode) 589 */ 590 u8 use_events; 591 }; 592 593 struct hns_roce_cmd_mailbox { 594 void *buf; 595 dma_addr_t dma; 596 }; 597 598 struct hns_roce_dev; 599 600 struct hns_roce_rinl_sge { 601 void *addr; 602 u32 len; 603 }; 604 605 struct hns_roce_rinl_wqe { 606 struct hns_roce_rinl_sge *sg_list; 607 u32 sge_cnt; 608 }; 609 610 struct hns_roce_rinl_buf { 611 struct hns_roce_rinl_wqe *wqe_list; 612 u32 wqe_cnt; 613 }; 614 615 enum { 616 HNS_ROCE_FLUSH_FLAG = 0, 617 }; 618 619 struct hns_roce_work { 620 struct hns_roce_dev *hr_dev; 621 struct work_struct work; 622 u32 qpn; 623 u32 cqn; 624 int event_type; 625 int sub_type; 626 }; 627 628 struct hns_roce_qp { 629 struct ib_qp ibqp; 630 struct hns_roce_wq rq; 631 struct hns_roce_db rdb; 632 struct hns_roce_db sdb; 633 unsigned long en_flags; 634 u32 doorbell_qpn; 635 u32 sq_signal_bits; 636 struct hns_roce_wq sq; 637 638 struct hns_roce_mtr mtr; 639 640 u32 buff_size; 641 struct mutex mutex; 642 u8 port; 643 u8 phy_port; 644 u8 sl; 645 u8 resp_depth; 646 u8 state; 647 u32 access_flags; 648 u32 atomic_rd_en; 649 u32 pkey_index; 650 u32 qkey; 651 void (*event)(struct hns_roce_qp *qp, 652 enum hns_roce_event event_type); 653 unsigned long qpn; 654 655 atomic_t refcount; 656 struct completion free; 657 658 struct hns_roce_sge sge; 659 u32 next_sge; 660 enum ib_mtu path_mtu; 661 u32 max_inline_data; 662 663 /* 0: flush needed, 1: unneeded */ 664 unsigned long flush_flag; 665 struct hns_roce_work flush_work; 666 struct hns_roce_rinl_buf rq_inl_buf; 667 struct list_head node; /* all qps are on a list */ 668 struct list_head rq_node; /* all recv qps are on a list */ 669 struct list_head sq_node; /* all send qps are on a list */ 670 }; 671 672 struct hns_roce_ib_iboe { 673 spinlock_t lock; 674 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 675 struct notifier_block nb; 676 u8 phy_port[HNS_ROCE_MAX_PORTS]; 677 }; 678 679 enum { 680 HNS_ROCE_EQ_STAT_INVALID = 0, 681 HNS_ROCE_EQ_STAT_VALID = 2, 682 }; 683 684 struct hns_roce_ceqe { 685 __le32 comp; 686 __le32 rsv[15]; 687 }; 688 689 struct hns_roce_aeqe { 690 __le32 asyn; 691 union { 692 struct { 693 __le32 qp; 694 u32 rsv0; 695 u32 rsv1; 696 } qp_event; 697 698 struct { 699 __le32 srq; 700 u32 rsv0; 701 u32 rsv1; 702 } srq_event; 703 704 struct { 705 __le32 cq; 706 u32 rsv0; 707 u32 rsv1; 708 } cq_event; 709 710 struct { 711 __le32 ceqe; 712 u32 rsv0; 713 u32 rsv1; 714 } ce_event; 715 716 struct { 717 __le64 out_param; 718 __le16 token; 719 u8 status; 720 u8 rsv0; 721 } __packed cmd; 722 } event; 723 __le32 rsv[12]; 724 }; 725 726 struct hns_roce_eq { 727 struct hns_roce_dev *hr_dev; 728 void __iomem *doorbell; 729 730 int type_flag; /* Aeq:1 ceq:0 */ 731 int eqn; 732 u32 entries; 733 int log_entries; 734 int eqe_size; 735 int irq; 736 int log_page_size; 737 int cons_index; 738 struct hns_roce_buf_list *buf_list; 739 int over_ignore; 740 int coalesce; 741 int arm_st; 742 int hop_num; 743 struct hns_roce_mtr mtr; 744 u16 eq_max_cnt; 745 int eq_period; 746 int shift; 747 int event_type; 748 int sub_type; 749 }; 750 751 struct hns_roce_eq_table { 752 struct hns_roce_eq *eq; 753 void __iomem **eqc_base; /* only for hw v1 */ 754 }; 755 756 struct hns_roce_caps { 757 u64 fw_ver; 758 u8 num_ports; 759 int gid_table_len[HNS_ROCE_MAX_PORTS]; 760 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 761 int local_ca_ack_delay; 762 int num_uars; 763 u32 phy_num_uars; 764 u32 max_sq_sg; 765 u32 max_sq_inline; 766 u32 max_rq_sg; 767 u32 max_extend_sg; 768 int num_qps; 769 int reserved_qps; 770 int num_qpc_timer; 771 int num_cqc_timer; 772 int num_srqs; 773 u32 max_wqes; 774 u32 max_srq_wrs; 775 u32 max_srq_sges; 776 u32 max_sq_desc_sz; 777 u32 max_rq_desc_sz; 778 u32 max_srq_desc_sz; 779 int max_qp_init_rdma; 780 int max_qp_dest_rdma; 781 int num_cqs; 782 u32 max_cqes; 783 u32 min_cqes; 784 u32 min_wqes; 785 int reserved_cqs; 786 int reserved_srqs; 787 int num_aeq_vectors; 788 int num_comp_vectors; 789 int num_other_vectors; 790 int num_mtpts; 791 u32 num_mtt_segs; 792 u32 num_cqe_segs; 793 u32 num_srqwqe_segs; 794 u32 num_idx_segs; 795 int reserved_mrws; 796 int reserved_uars; 797 int num_pds; 798 int reserved_pds; 799 u32 mtt_entry_sz; 800 u32 cqe_sz; 801 u32 page_size_cap; 802 u32 reserved_lkey; 803 int mtpt_entry_sz; 804 int qpc_sz; 805 int irrl_entry_sz; 806 int trrl_entry_sz; 807 int cqc_entry_sz; 808 int sccc_sz; 809 int qpc_timer_entry_sz; 810 int cqc_timer_entry_sz; 811 int srqc_entry_sz; 812 int idx_entry_sz; 813 u32 pbl_ba_pg_sz; 814 u32 pbl_buf_pg_sz; 815 u32 pbl_hop_num; 816 int aeqe_depth; 817 int ceqe_depth; 818 u32 aeqe_size; 819 u32 ceqe_size; 820 enum ib_mtu max_mtu; 821 u32 qpc_bt_num; 822 u32 qpc_timer_bt_num; 823 u32 srqc_bt_num; 824 u32 cqc_bt_num; 825 u32 cqc_timer_bt_num; 826 u32 mpt_bt_num; 827 u32 sccc_bt_num; 828 u32 qpc_ba_pg_sz; 829 u32 qpc_buf_pg_sz; 830 u32 qpc_hop_num; 831 u32 srqc_ba_pg_sz; 832 u32 srqc_buf_pg_sz; 833 u32 srqc_hop_num; 834 u32 cqc_ba_pg_sz; 835 u32 cqc_buf_pg_sz; 836 u32 cqc_hop_num; 837 u32 mpt_ba_pg_sz; 838 u32 mpt_buf_pg_sz; 839 u32 mpt_hop_num; 840 u32 mtt_ba_pg_sz; 841 u32 mtt_buf_pg_sz; 842 u32 mtt_hop_num; 843 u32 wqe_sq_hop_num; 844 u32 wqe_sge_hop_num; 845 u32 wqe_rq_hop_num; 846 u32 sccc_ba_pg_sz; 847 u32 sccc_buf_pg_sz; 848 u32 sccc_hop_num; 849 u32 qpc_timer_ba_pg_sz; 850 u32 qpc_timer_buf_pg_sz; 851 u32 qpc_timer_hop_num; 852 u32 cqc_timer_ba_pg_sz; 853 u32 cqc_timer_buf_pg_sz; 854 u32 cqc_timer_hop_num; 855 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 856 u32 cqe_buf_pg_sz; 857 u32 cqe_hop_num; 858 u32 srqwqe_ba_pg_sz; 859 u32 srqwqe_buf_pg_sz; 860 u32 srqwqe_hop_num; 861 u32 idx_ba_pg_sz; 862 u32 idx_buf_pg_sz; 863 u32 idx_hop_num; 864 u32 eqe_ba_pg_sz; 865 u32 eqe_buf_pg_sz; 866 u32 eqe_hop_num; 867 u32 sl_num; 868 u32 tsq_buf_pg_sz; 869 u32 tpq_buf_pg_sz; 870 u32 chunk_sz; /* chunk size in non multihop mode */ 871 u64 flags; 872 u16 default_ceq_max_cnt; 873 u16 default_ceq_period; 874 u16 default_aeq_max_cnt; 875 u16 default_aeq_period; 876 u16 default_aeq_arm_st; 877 u16 default_ceq_arm_st; 878 }; 879 880 struct hns_roce_dfx_hw { 881 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 882 int *buffer); 883 }; 884 885 enum hns_roce_device_state { 886 HNS_ROCE_DEVICE_STATE_INITED, 887 HNS_ROCE_DEVICE_STATE_RST_DOWN, 888 HNS_ROCE_DEVICE_STATE_UNINIT, 889 }; 890 891 struct hns_roce_hw { 892 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 893 int (*cmq_init)(struct hns_roce_dev *hr_dev); 894 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 895 int (*hw_profile)(struct hns_roce_dev *hr_dev); 896 int (*hw_init)(struct hns_roce_dev *hr_dev); 897 void (*hw_exit)(struct hns_roce_dev *hr_dev); 898 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 899 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 900 u16 token, int event); 901 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); 902 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); 903 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 904 const union ib_gid *gid, const struct ib_gid_attr *attr); 905 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 906 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 907 enum ib_mtu mtu); 908 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 909 struct hns_roce_mr *mr, unsigned long mtpt_idx); 910 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 911 struct hns_roce_mr *mr, int flags, u32 pdn, 912 int mr_access_flags, u64 iova, u64 size, 913 void *mb_buf); 914 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 915 struct hns_roce_mr *mr); 916 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 917 void (*write_cqc)(struct hns_roce_dev *hr_dev, 918 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 919 dma_addr_t dma_handle); 920 int (*set_hem)(struct hns_roce_dev *hr_dev, 921 struct hns_roce_hem_table *table, int obj, int step_idx); 922 int (*clear_hem)(struct hns_roce_dev *hr_dev, 923 struct hns_roce_hem_table *table, int obj, 924 int step_idx); 925 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 926 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 927 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 928 int attr_mask, enum ib_qp_state cur_state, 929 enum ib_qp_state new_state); 930 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); 931 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 932 struct hns_roce_qp *hr_qp); 933 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 934 const struct ib_send_wr **bad_wr); 935 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 936 const struct ib_recv_wr **bad_recv_wr); 937 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 938 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 939 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 940 struct ib_udata *udata); 941 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 942 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 943 int (*init_eq)(struct hns_roce_dev *hr_dev); 944 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 945 void (*write_srqc)(struct hns_roce_dev *hr_dev, 946 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, 947 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, 948 dma_addr_t dma_handle_wqe, 949 dma_addr_t dma_handle_idx); 950 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 951 enum ib_srq_attr_mask srq_attr_mask, 952 struct ib_udata *udata); 953 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); 954 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 955 const struct ib_recv_wr **bad_wr); 956 const struct ib_device_ops *hns_roce_dev_ops; 957 const struct ib_device_ops *hns_roce_dev_srq_ops; 958 }; 959 960 struct hns_roce_dev { 961 struct ib_device ib_dev; 962 struct platform_device *pdev; 963 struct pci_dev *pci_dev; 964 struct device *dev; 965 struct hns_roce_uar priv_uar; 966 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 967 spinlock_t sm_lock; 968 spinlock_t bt_cmd_lock; 969 bool active; 970 bool is_reset; 971 bool dis_db; 972 unsigned long reset_cnt; 973 struct hns_roce_ib_iboe iboe; 974 enum hns_roce_device_state state; 975 struct list_head qp_list; /* list of all qps on this dev */ 976 spinlock_t qp_list_lock; /* protect qp_list */ 977 978 struct list_head pgdir_list; 979 struct mutex pgdir_mutex; 980 int irq[HNS_ROCE_MAX_IRQ_NUM]; 981 u8 __iomem *reg_base; 982 struct hns_roce_caps caps; 983 struct xarray qp_table_xa; 984 985 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 986 u64 sys_image_guid; 987 u32 vendor_id; 988 u32 vendor_part_id; 989 u32 hw_rev; 990 void __iomem *priv_addr; 991 992 struct hns_roce_cmdq cmd; 993 struct hns_roce_bitmap pd_bitmap; 994 struct hns_roce_uar_table uar_table; 995 struct hns_roce_mr_table mr_table; 996 struct hns_roce_cq_table cq_table; 997 struct hns_roce_srq_table srq_table; 998 struct hns_roce_qp_table qp_table; 999 struct hns_roce_eq_table eq_table; 1000 struct hns_roce_hem_table qpc_timer_table; 1001 struct hns_roce_hem_table cqc_timer_table; 1002 1003 int cmd_mod; 1004 int loop_idc; 1005 u32 sdb_offset; 1006 u32 odb_offset; 1007 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 1008 u32 tptr_size; /* only for hw v1 */ 1009 const struct hns_roce_hw *hw; 1010 void *priv; 1011 struct workqueue_struct *irq_workq; 1012 const struct hns_roce_dfx_hw *dfx; 1013 }; 1014 1015 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1016 { 1017 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1018 } 1019 1020 static inline struct hns_roce_ucontext 1021 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1022 { 1023 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1024 } 1025 1026 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1027 { 1028 return container_of(ibpd, struct hns_roce_pd, ibpd); 1029 } 1030 1031 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1032 { 1033 return container_of(ibah, struct hns_roce_ah, ibah); 1034 } 1035 1036 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1037 { 1038 return container_of(ibmr, struct hns_roce_mr, ibmr); 1039 } 1040 1041 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1042 { 1043 return container_of(ibmw, struct hns_roce_mw, ibmw); 1044 } 1045 1046 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1047 { 1048 return container_of(ibqp, struct hns_roce_qp, ibqp); 1049 } 1050 1051 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1052 { 1053 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1054 } 1055 1056 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1057 { 1058 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1059 } 1060 1061 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1062 { 1063 __raw_writeq(*(u64 *) val, dest); 1064 } 1065 1066 static inline struct hns_roce_qp 1067 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1068 { 1069 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1070 } 1071 1072 static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf) 1073 { 1074 if (buf->page_list) 1075 return false; 1076 1077 return true; 1078 } 1079 1080 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 1081 { 1082 if (hns_roce_buf_is_direct(buf)) 1083 return (char *)(buf->direct.buf) + (offset & (buf->size - 1)); 1084 1085 return (char *)(buf->page_list[offset >> buf->page_shift].buf) + 1086 (offset & ((1 << buf->page_shift) - 1)); 1087 } 1088 1089 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx) 1090 { 1091 if (hns_roce_buf_is_direct(buf)) 1092 return buf->direct.map + ((dma_addr_t)idx << buf->page_shift); 1093 else 1094 return buf->page_list[idx].map; 1095 } 1096 1097 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1098 1099 static inline u64 to_hr_hw_page_addr(u64 addr) 1100 { 1101 return addr >> HNS_HW_PAGE_SHIFT; 1102 } 1103 1104 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1105 { 1106 return page_shift - HNS_HW_PAGE_SHIFT; 1107 } 1108 1109 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1110 { 1111 if (count > 0) 1112 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1113 1114 return 0; 1115 } 1116 1117 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1118 { 1119 return hr_hw_page_align(count << buf_shift); 1120 } 1121 1122 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1123 { 1124 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1125 } 1126 1127 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1128 { 1129 if (!count) 1130 return 0; 1131 1132 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1133 } 1134 1135 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1136 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1137 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1138 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1139 1140 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1141 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1142 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1143 u64 out_param); 1144 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1145 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1146 1147 /* hns roce hw need current block and next block addr from mtt */ 1148 #define MTT_MIN_COUNT 2 1149 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1150 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1151 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1152 struct hns_roce_buf_attr *buf_attr, 1153 unsigned int page_shift, struct ib_udata *udata, 1154 unsigned long user_addr); 1155 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1156 struct hns_roce_mtr *mtr); 1157 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1158 dma_addr_t *pages, int page_cnt); 1159 1160 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1161 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1162 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1163 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1164 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1165 1166 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1167 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1168 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1169 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1170 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1171 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1172 1173 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1174 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1175 int rr); 1176 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1177 u32 reserved_bot, u32 resetrved_top); 1178 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1179 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1180 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1181 int align, unsigned long *obj); 1182 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1183 unsigned long obj, int cnt, 1184 int rr); 1185 1186 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1187 struct ib_udata *udata); 1188 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1189 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1190 { 1191 return 0; 1192 } 1193 1194 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1195 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1196 1197 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1198 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1199 u64 virt_addr, int access_flags, 1200 struct ib_udata *udata); 1201 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, 1202 u64 virt_addr, int mr_access_flags, struct ib_pd *pd, 1203 struct ib_udata *udata); 1204 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1205 u32 max_num_sg); 1206 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1207 unsigned int *sg_offset); 1208 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1209 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1210 struct hns_roce_cmd_mailbox *mailbox, 1211 unsigned long mpt_index); 1212 unsigned long key_to_hw_index(u32 key); 1213 1214 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1215 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1216 1217 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1218 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 1219 struct hns_roce_buf *buf, u32 page_shift); 1220 1221 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1222 int buf_cnt, int start, struct hns_roce_buf *buf); 1223 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1224 int buf_cnt, int start, struct ib_umem *umem, 1225 unsigned int page_shift); 1226 1227 int hns_roce_create_srq(struct ib_srq *srq, 1228 struct ib_srq_init_attr *srq_init_attr, 1229 struct ib_udata *udata); 1230 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1231 enum ib_srq_attr_mask srq_attr_mask, 1232 struct ib_udata *udata); 1233 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1234 1235 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1236 struct ib_qp_init_attr *init_attr, 1237 struct ib_udata *udata); 1238 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1239 int attr_mask, struct ib_udata *udata); 1240 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1241 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 1242 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n); 1243 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n); 1244 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1245 struct ib_cq *ib_cq); 1246 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1247 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1248 struct hns_roce_cq *recv_cq); 1249 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1250 struct hns_roce_cq *recv_cq); 1251 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1252 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1253 struct ib_udata *udata); 1254 __be32 send_ieth(const struct ib_send_wr *wr); 1255 int to_hr_qp_type(int qp_type); 1256 1257 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1258 struct ib_udata *udata); 1259 1260 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1261 int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1262 struct ib_udata *udata, unsigned long virt, 1263 struct hns_roce_db *db); 1264 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1265 struct hns_roce_db *db); 1266 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1267 int order); 1268 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1269 1270 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1271 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1272 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1273 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1274 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1275 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1276 int hns_roce_init(struct hns_roce_dev *hr_dev); 1277 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1278 1279 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, 1280 struct ib_cq *ib_cq); 1281 #endif /* _HNS_ROCE_DEVICE_H */ 1282