1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/platform_device.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/uverbs_ioctl.h> 36 #include "hns_roce_device.h" 37 #include "hns_roce_cmd.h" 38 #include "hns_roce_hem.h" 39 #include <rdma/hns-abi.h> 40 #include "hns_roce_common.h" 41 42 static void hns_roce_ib_cq_comp(struct hns_roce_cq *hr_cq) 43 { 44 struct ib_cq *ibcq = &hr_cq->ib_cq; 45 46 ibcq->comp_handler(ibcq, ibcq->cq_context); 47 } 48 49 static void hns_roce_ib_cq_event(struct hns_roce_cq *hr_cq, 50 enum hns_roce_event event_type) 51 { 52 struct hns_roce_dev *hr_dev; 53 struct ib_event event; 54 struct ib_cq *ibcq; 55 56 ibcq = &hr_cq->ib_cq; 57 hr_dev = to_hr_dev(ibcq->device); 58 59 if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID && 60 event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR && 61 event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) { 62 dev_err(hr_dev->dev, 63 "hns_roce_ib: Unexpected event type 0x%x on CQ %06lx\n", 64 event_type, hr_cq->cqn); 65 return; 66 } 67 68 if (ibcq->event_handler) { 69 event.device = ibcq->device; 70 event.event = IB_EVENT_CQ_ERR; 71 event.element.cq = ibcq; 72 ibcq->event_handler(&event, ibcq->cq_context); 73 } 74 } 75 76 static int hns_roce_sw2hw_cq(struct hns_roce_dev *dev, 77 struct hns_roce_cmd_mailbox *mailbox, 78 unsigned long cq_num) 79 { 80 return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cq_num, 0, 81 HNS_ROCE_CMD_SW2HW_CQ, HNS_ROCE_CMD_TIMEOUT_MSECS); 82 } 83 84 static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent, 85 struct hns_roce_mtt *hr_mtt, 86 struct hns_roce_uar *hr_uar, 87 struct hns_roce_cq *hr_cq, int vector) 88 { 89 struct hns_roce_cmd_mailbox *mailbox; 90 struct hns_roce_hem_table *mtt_table; 91 struct hns_roce_cq_table *cq_table; 92 struct device *dev = hr_dev->dev; 93 dma_addr_t dma_handle; 94 u64 *mtts; 95 int ret; 96 97 cq_table = &hr_dev->cq_table; 98 99 /* Get the physical address of cq buf */ 100 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 101 mtt_table = &hr_dev->mr_table.mtt_cqe_table; 102 else 103 mtt_table = &hr_dev->mr_table.mtt_table; 104 105 mtts = hns_roce_table_find(hr_dev, mtt_table, 106 hr_mtt->first_seg, &dma_handle); 107 if (!mtts) { 108 dev_err(dev, "CQ alloc.Failed to find cq buf addr.\n"); 109 return -EINVAL; 110 } 111 112 if (vector >= hr_dev->caps.num_comp_vectors) { 113 dev_err(dev, "CQ alloc.Invalid vector.\n"); 114 return -EINVAL; 115 } 116 hr_cq->vector = vector; 117 118 ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn); 119 if (ret == -1) { 120 dev_err(dev, "CQ alloc.Failed to alloc index.\n"); 121 return -ENOMEM; 122 } 123 124 /* Get CQC memory HEM(Hardware Entry Memory) table */ 125 ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn); 126 if (ret) { 127 dev_err(dev, "CQ alloc.Failed to get context mem.\n"); 128 goto err_out; 129 } 130 131 ret = xa_err(xa_store(&cq_table->array, hr_cq->cqn, hr_cq, GFP_KERNEL)); 132 if (ret) { 133 dev_err(dev, "CQ alloc failed xa_store.\n"); 134 goto err_put; 135 } 136 137 /* Allocate mailbox memory */ 138 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 139 if (IS_ERR(mailbox)) { 140 ret = PTR_ERR(mailbox); 141 goto err_xa; 142 } 143 144 hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle, 145 nent, vector); 146 147 /* Send mailbox to hw */ 148 ret = hns_roce_sw2hw_cq(hr_dev, mailbox, hr_cq->cqn); 149 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 150 if (ret) { 151 dev_err(dev, "CQ alloc.Failed to cmd mailbox.\n"); 152 goto err_xa; 153 } 154 155 hr_cq->cons_index = 0; 156 hr_cq->arm_sn = 1; 157 hr_cq->uar = hr_uar; 158 159 atomic_set(&hr_cq->refcount, 1); 160 init_completion(&hr_cq->free); 161 162 return 0; 163 164 err_xa: 165 xa_erase(&cq_table->array, hr_cq->cqn); 166 167 err_put: 168 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 169 170 err_out: 171 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); 172 return ret; 173 } 174 175 static int hns_roce_hw2sw_cq(struct hns_roce_dev *dev, 176 struct hns_roce_cmd_mailbox *mailbox, 177 unsigned long cq_num) 178 { 179 return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, cq_num, 180 mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_CQ, 181 HNS_ROCE_CMD_TIMEOUT_MSECS); 182 } 183 184 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 185 { 186 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 187 struct device *dev = hr_dev->dev; 188 int ret; 189 190 ret = hns_roce_hw2sw_cq(hr_dev, NULL, hr_cq->cqn); 191 if (ret) 192 dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret, 193 hr_cq->cqn); 194 195 xa_erase(&cq_table->array, hr_cq->cqn); 196 197 /* Waiting interrupt process procedure carried out */ 198 synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq); 199 200 /* wait for all interrupt processed */ 201 if (atomic_dec_and_test(&hr_cq->refcount)) 202 complete(&hr_cq->free); 203 wait_for_completion(&hr_cq->free); 204 205 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 206 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); 207 } 208 209 static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev, 210 struct ib_udata *udata, 211 struct hns_roce_cq_buf *buf, 212 struct ib_umem **umem, u64 buf_addr, int cqe) 213 { 214 int ret; 215 u32 page_shift; 216 u32 npages; 217 218 *umem = ib_umem_get(udata, buf_addr, cqe * hr_dev->caps.cq_entry_sz, 219 IB_ACCESS_LOCAL_WRITE, 1); 220 if (IS_ERR(*umem)) 221 return PTR_ERR(*umem); 222 223 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 224 buf->hr_mtt.mtt_type = MTT_TYPE_CQE; 225 else 226 buf->hr_mtt.mtt_type = MTT_TYPE_WQE; 227 228 if (hr_dev->caps.cqe_buf_pg_sz) { 229 npages = (ib_umem_page_count(*umem) + 230 (1 << hr_dev->caps.cqe_buf_pg_sz) - 1) / 231 (1 << hr_dev->caps.cqe_buf_pg_sz); 232 page_shift = PAGE_SHIFT + hr_dev->caps.cqe_buf_pg_sz; 233 ret = hns_roce_mtt_init(hr_dev, npages, page_shift, 234 &buf->hr_mtt); 235 } else { 236 ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(*umem), 237 PAGE_SHIFT, &buf->hr_mtt); 238 } 239 if (ret) 240 goto err_buf; 241 242 ret = hns_roce_ib_umem_write_mtt(hr_dev, &buf->hr_mtt, *umem); 243 if (ret) 244 goto err_mtt; 245 246 return 0; 247 248 err_mtt: 249 hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt); 250 251 err_buf: 252 ib_umem_release(*umem); 253 return ret; 254 } 255 256 static int hns_roce_ib_alloc_cq_buf(struct hns_roce_dev *hr_dev, 257 struct hns_roce_cq_buf *buf, u32 nent) 258 { 259 int ret; 260 u32 page_shift = PAGE_SHIFT + hr_dev->caps.cqe_buf_pg_sz; 261 262 ret = hns_roce_buf_alloc(hr_dev, nent * hr_dev->caps.cq_entry_sz, 263 (1 << page_shift) * 2, &buf->hr_buf, 264 page_shift); 265 if (ret) 266 goto out; 267 268 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 269 buf->hr_mtt.mtt_type = MTT_TYPE_CQE; 270 else 271 buf->hr_mtt.mtt_type = MTT_TYPE_WQE; 272 273 ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages, 274 buf->hr_buf.page_shift, &buf->hr_mtt); 275 if (ret) 276 goto err_buf; 277 278 ret = hns_roce_buf_write_mtt(hr_dev, &buf->hr_mtt, &buf->hr_buf); 279 if (ret) 280 goto err_mtt; 281 282 return 0; 283 284 err_mtt: 285 hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt); 286 287 err_buf: 288 hns_roce_buf_free(hr_dev, nent * hr_dev->caps.cq_entry_sz, 289 &buf->hr_buf); 290 out: 291 return ret; 292 } 293 294 static void hns_roce_ib_free_cq_buf(struct hns_roce_dev *hr_dev, 295 struct hns_roce_cq_buf *buf, int cqe) 296 { 297 hns_roce_buf_free(hr_dev, (cqe + 1) * hr_dev->caps.cq_entry_sz, 298 &buf->hr_buf); 299 } 300 301 int hns_roce_ib_create_cq(struct ib_cq *ib_cq, 302 const struct ib_cq_init_attr *attr, 303 struct ib_udata *udata) 304 { 305 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device); 306 struct device *dev = hr_dev->dev; 307 struct hns_roce_ib_create_cq ucmd; 308 struct hns_roce_ib_create_cq_resp resp = {}; 309 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq); 310 struct hns_roce_uar *uar = NULL; 311 int vector = attr->comp_vector; 312 int cq_entries = attr->cqe; 313 int ret; 314 struct hns_roce_ucontext *context = rdma_udata_to_drv_context( 315 udata, struct hns_roce_ucontext, ibucontext); 316 317 if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) { 318 dev_err(dev, "Creat CQ failed. entries=%d, max=%d\n", 319 cq_entries, hr_dev->caps.max_cqes); 320 return -EINVAL; 321 } 322 323 if (hr_dev->caps.min_cqes) 324 cq_entries = max(cq_entries, hr_dev->caps.min_cqes); 325 326 cq_entries = roundup_pow_of_two((unsigned int)cq_entries); 327 hr_cq->ib_cq.cqe = cq_entries - 1; 328 spin_lock_init(&hr_cq->lock); 329 330 if (udata) { 331 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 332 dev_err(dev, "Failed to copy_from_udata.\n"); 333 ret = -EFAULT; 334 goto err_cq; 335 } 336 337 /* Get user space address, write it into mtt table */ 338 ret = hns_roce_ib_get_cq_umem(hr_dev, udata, &hr_cq->hr_buf, 339 &hr_cq->umem, ucmd.buf_addr, 340 cq_entries); 341 if (ret) { 342 dev_err(dev, "Failed to get_cq_umem.\n"); 343 goto err_cq; 344 } 345 346 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 347 (udata->outlen >= sizeof(resp))) { 348 ret = hns_roce_db_map_user(context, udata, ucmd.db_addr, 349 &hr_cq->db); 350 if (ret) { 351 dev_err(dev, "cq record doorbell map failed!\n"); 352 goto err_mtt; 353 } 354 hr_cq->db_en = 1; 355 resp.cap_flags |= HNS_ROCE_SUPPORT_CQ_RECORD_DB; 356 } 357 358 /* Get user space parameters */ 359 uar = &context->uar; 360 } else { 361 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 362 ret = hns_roce_alloc_db(hr_dev, &hr_cq->db, 1); 363 if (ret) 364 goto err_cq; 365 366 hr_cq->set_ci_db = hr_cq->db.db_record; 367 *hr_cq->set_ci_db = 0; 368 hr_cq->db_en = 1; 369 } 370 371 /* Init mmt table and write buff address to mtt table */ 372 ret = hns_roce_ib_alloc_cq_buf(hr_dev, &hr_cq->hr_buf, 373 cq_entries); 374 if (ret) { 375 dev_err(dev, "Failed to alloc_cq_buf.\n"); 376 goto err_db; 377 } 378 379 uar = &hr_dev->priv_uar; 380 hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset + 381 DB_REG_OFFSET * uar->index; 382 } 383 384 /* Allocate cq index, fill cq_context */ 385 ret = hns_roce_cq_alloc(hr_dev, cq_entries, &hr_cq->hr_buf.hr_mtt, uar, 386 hr_cq, vector); 387 if (ret) { 388 dev_err(dev, "Creat CQ .Failed to cq_alloc.\n"); 389 goto err_dbmap; 390 } 391 392 /* 393 * For the QP created by kernel space, tptr value should be initialized 394 * to zero; For the QP created by user space, it will cause synchronous 395 * problems if tptr is set to zero here, so we initialze it in user 396 * space. 397 */ 398 if (!udata && hr_cq->tptr_addr) 399 *hr_cq->tptr_addr = 0; 400 401 /* Get created cq handler and carry out event */ 402 hr_cq->comp = hns_roce_ib_cq_comp; 403 hr_cq->event = hns_roce_ib_cq_event; 404 hr_cq->cq_depth = cq_entries; 405 406 if (udata) { 407 resp.cqn = hr_cq->cqn; 408 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 409 if (ret) 410 goto err_cqc; 411 } 412 413 return 0; 414 415 err_cqc: 416 hns_roce_free_cq(hr_dev, hr_cq); 417 418 err_dbmap: 419 if (udata && (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 420 (udata->outlen >= sizeof(resp))) 421 hns_roce_db_unmap_user(context, &hr_cq->db); 422 423 err_mtt: 424 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt); 425 ib_umem_release(hr_cq->umem); 426 if (!udata) 427 hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf, 428 hr_cq->ib_cq.cqe); 429 430 err_db: 431 if (!udata && (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) 432 hns_roce_free_db(hr_dev, &hr_cq->db); 433 434 err_cq: 435 return ret; 436 } 437 438 void hns_roce_ib_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 439 { 440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device); 441 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq); 442 443 if (hr_dev->hw->destroy_cq) { 444 hr_dev->hw->destroy_cq(ib_cq, udata); 445 return; 446 } 447 448 hns_roce_free_cq(hr_dev, hr_cq); 449 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt); 450 451 ib_umem_release(hr_cq->umem); 452 if (udata) { 453 if (hr_cq->db_en == 1) 454 hns_roce_db_unmap_user(rdma_udata_to_drv_context( 455 udata, 456 struct hns_roce_ucontext, 457 ibucontext), 458 &hr_cq->db); 459 } else { 460 /* Free the buff of stored cq */ 461 hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf, ib_cq->cqe); 462 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) 463 hns_roce_free_db(hr_dev, &hr_cq->db); 464 } 465 } 466 467 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn) 468 { 469 struct device *dev = hr_dev->dev; 470 struct hns_roce_cq *cq; 471 472 cq = xa_load(&hr_dev->cq_table.array, cqn & (hr_dev->caps.num_cqs - 1)); 473 if (!cq) { 474 dev_warn(dev, "Completion event for bogus CQ 0x%08x\n", cqn); 475 return; 476 } 477 478 ++cq->arm_sn; 479 cq->comp(cq); 480 } 481 482 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) 483 { 484 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 485 struct device *dev = hr_dev->dev; 486 struct hns_roce_cq *cq; 487 488 cq = xa_load(&cq_table->array, cqn & (hr_dev->caps.num_cqs - 1)); 489 if (cq) 490 atomic_inc(&cq->refcount); 491 492 if (!cq) { 493 dev_warn(dev, "Async event for bogus CQ %08x\n", cqn); 494 return; 495 } 496 497 cq->event(cq, (enum hns_roce_event)event_type); 498 499 if (atomic_dec_and_test(&cq->refcount)) 500 complete(&cq->free); 501 } 502 503 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) 504 { 505 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 506 507 xa_init(&cq_table->array); 508 509 return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs, 510 hr_dev->caps.num_cqs - 1, 511 hr_dev->caps.reserved_cqs, 0); 512 } 513 514 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev) 515 { 516 hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap); 517 } 518