1 /*
2  * Copyright (c) 2016 Hisilicon Limited.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/platform_device.h>
34 #include <rdma/ib_umem.h>
35 #include "hns_roce_device.h"
36 #include "hns_roce_cmd.h"
37 #include "hns_roce_hem.h"
38 #include <rdma/hns-abi.h>
39 #include "hns_roce_common.h"
40 
41 static void hns_roce_ib_cq_comp(struct hns_roce_cq *hr_cq)
42 {
43 	struct ib_cq *ibcq = &hr_cq->ib_cq;
44 
45 	ibcq->comp_handler(ibcq, ibcq->cq_context);
46 }
47 
48 static void hns_roce_ib_cq_event(struct hns_roce_cq *hr_cq,
49 				 enum hns_roce_event event_type)
50 {
51 	struct hns_roce_dev *hr_dev;
52 	struct ib_event event;
53 	struct ib_cq *ibcq;
54 
55 	ibcq = &hr_cq->ib_cq;
56 	hr_dev = to_hr_dev(ibcq->device);
57 
58 	if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID &&
59 	    event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR &&
60 	    event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) {
61 		dev_err(&hr_dev->pdev->dev,
62 			"hns_roce_ib: Unexpected event type 0x%x on CQ %06lx\n",
63 			event_type, hr_cq->cqn);
64 		return;
65 	}
66 
67 	if (ibcq->event_handler) {
68 		event.device = ibcq->device;
69 		event.event = IB_EVENT_CQ_ERR;
70 		event.element.cq = ibcq;
71 		ibcq->event_handler(&event, ibcq->cq_context);
72 	}
73 }
74 
75 static int hns_roce_sw2hw_cq(struct hns_roce_dev *dev,
76 			     struct hns_roce_cmd_mailbox *mailbox,
77 			     unsigned long cq_num)
78 {
79 	return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cq_num, 0,
80 			    HNS_ROCE_CMD_SW2HW_CQ, HNS_ROCE_CMD_TIMEOUT_MSECS);
81 }
82 
83 static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
84 			     struct hns_roce_mtt *hr_mtt,
85 			     struct hns_roce_uar *hr_uar,
86 			     struct hns_roce_cq *hr_cq, int vector)
87 {
88 	struct hns_roce_cmd_mailbox *mailbox = NULL;
89 	struct hns_roce_cq_table *cq_table = NULL;
90 	struct device *dev = &hr_dev->pdev->dev;
91 	dma_addr_t dma_handle;
92 	u64 *mtts = NULL;
93 	int ret = 0;
94 
95 	cq_table = &hr_dev->cq_table;
96 
97 	/* Get the physical address of cq buf */
98 	mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
99 				   hr_mtt->first_seg, &dma_handle);
100 	if (!mtts) {
101 		dev_err(dev, "CQ alloc.Failed to find cq buf addr.\n");
102 		return -EINVAL;
103 	}
104 
105 	if (vector >= hr_dev->caps.num_comp_vectors) {
106 		dev_err(dev, "CQ alloc.Invalid vector.\n");
107 		return -EINVAL;
108 	}
109 	hr_cq->vector = vector;
110 
111 	ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn);
112 	if (ret == -1) {
113 		dev_err(dev, "CQ alloc.Failed to alloc index.\n");
114 		return -ENOMEM;
115 	}
116 
117 	/* Get CQC memory HEM(Hardware Entry Memory) table */
118 	ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn);
119 	if (ret) {
120 		dev_err(dev, "CQ alloc.Failed to get context mem.\n");
121 		goto err_out;
122 	}
123 
124 	/* The cq insert radix tree */
125 	spin_lock_irq(&cq_table->lock);
126 	/* Radix_tree: The associated pointer and long integer key value like */
127 	ret = radix_tree_insert(&cq_table->tree, hr_cq->cqn, hr_cq);
128 	spin_unlock_irq(&cq_table->lock);
129 	if (ret) {
130 		dev_err(dev, "CQ alloc.Failed to radix_tree_insert.\n");
131 		goto err_put;
132 	}
133 
134 	/* Allocate mailbox memory */
135 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
136 	if (IS_ERR(mailbox)) {
137 		ret = PTR_ERR(mailbox);
138 		goto err_radix;
139 	}
140 
141 	hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle,
142 			      nent, vector);
143 
144 	/* Send mailbox to hw */
145 	ret = hns_roce_sw2hw_cq(hr_dev, mailbox, hr_cq->cqn);
146 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
147 	if (ret) {
148 		dev_err(dev, "CQ alloc.Failed to cmd mailbox.\n");
149 		goto err_radix;
150 	}
151 
152 	hr_cq->cons_index = 0;
153 	hr_cq->uar = hr_uar;
154 
155 	atomic_set(&hr_cq->refcount, 1);
156 	init_completion(&hr_cq->free);
157 
158 	return 0;
159 
160 err_radix:
161 	spin_lock_irq(&cq_table->lock);
162 	radix_tree_delete(&cq_table->tree, hr_cq->cqn);
163 	spin_unlock_irq(&cq_table->lock);
164 
165 err_put:
166 	hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
167 
168 err_out:
169 	hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
170 	return ret;
171 }
172 
173 static int hns_roce_hw2sw_cq(struct hns_roce_dev *dev,
174 			     struct hns_roce_cmd_mailbox *mailbox,
175 			     unsigned long cq_num)
176 {
177 	return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
178 				 mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_CQ,
179 				 HNS_ROCE_CMD_TIMEOUT_MSECS);
180 }
181 
182 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
183 {
184 	struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
185 	struct device *dev = &hr_dev->pdev->dev;
186 	int ret;
187 
188 	ret = hns_roce_hw2sw_cq(hr_dev, NULL, hr_cq->cqn);
189 	if (ret)
190 		dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret,
191 			hr_cq->cqn);
192 
193 	/* Waiting interrupt process procedure carried out */
194 	synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
195 
196 	/* wait for all interrupt processed */
197 	if (atomic_dec_and_test(&hr_cq->refcount))
198 		complete(&hr_cq->free);
199 	wait_for_completion(&hr_cq->free);
200 
201 	spin_lock_irq(&cq_table->lock);
202 	radix_tree_delete(&cq_table->tree, hr_cq->cqn);
203 	spin_unlock_irq(&cq_table->lock);
204 
205 	hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
206 	hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
207 }
208 
209 static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
210 				   struct ib_ucontext *context,
211 				   struct hns_roce_cq_buf *buf,
212 				   struct ib_umem **umem, u64 buf_addr, int cqe)
213 {
214 	int ret;
215 
216 	*umem = ib_umem_get(context, buf_addr, cqe * hr_dev->caps.cq_entry_sz,
217 			    IB_ACCESS_LOCAL_WRITE, 1);
218 	if (IS_ERR(*umem))
219 		return PTR_ERR(*umem);
220 
221 	ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(*umem),
222 				ilog2((unsigned int)(*umem)->page_size),
223 				&buf->hr_mtt);
224 	if (ret)
225 		goto err_buf;
226 
227 	ret = hns_roce_ib_umem_write_mtt(hr_dev, &buf->hr_mtt, *umem);
228 	if (ret)
229 		goto err_mtt;
230 
231 	return 0;
232 
233 err_mtt:
234 	hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt);
235 
236 err_buf:
237 	ib_umem_release(*umem);
238 	return ret;
239 }
240 
241 static int hns_roce_ib_alloc_cq_buf(struct hns_roce_dev *hr_dev,
242 				    struct hns_roce_cq_buf *buf, u32 nent)
243 {
244 	int ret;
245 
246 	ret = hns_roce_buf_alloc(hr_dev, nent * hr_dev->caps.cq_entry_sz,
247 				 PAGE_SIZE * 2, &buf->hr_buf);
248 	if (ret)
249 		goto out;
250 
251 	ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages,
252 				buf->hr_buf.page_shift, &buf->hr_mtt);
253 	if (ret)
254 		goto err_buf;
255 
256 	ret = hns_roce_buf_write_mtt(hr_dev, &buf->hr_mtt, &buf->hr_buf);
257 	if (ret)
258 		goto err_mtt;
259 
260 	return 0;
261 
262 err_mtt:
263 	hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt);
264 
265 err_buf:
266 	hns_roce_buf_free(hr_dev, nent * hr_dev->caps.cq_entry_sz,
267 			  &buf->hr_buf);
268 out:
269 	return ret;
270 }
271 
272 static void hns_roce_ib_free_cq_buf(struct hns_roce_dev *hr_dev,
273 				    struct hns_roce_cq_buf *buf, int cqe)
274 {
275 	hns_roce_buf_free(hr_dev, (cqe + 1) * hr_dev->caps.cq_entry_sz,
276 			  &buf->hr_buf);
277 }
278 
279 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
280 				    const struct ib_cq_init_attr *attr,
281 				    struct ib_ucontext *context,
282 				    struct ib_udata *udata)
283 {
284 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
285 	struct device *dev = &hr_dev->pdev->dev;
286 	struct hns_roce_ib_create_cq ucmd;
287 	struct hns_roce_cq *hr_cq = NULL;
288 	struct hns_roce_uar *uar = NULL;
289 	int vector = attr->comp_vector;
290 	int cq_entries = attr->cqe;
291 	int ret = 0;
292 
293 	if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) {
294 		dev_err(dev, "Creat CQ failed. entries=%d, max=%d\n",
295 			cq_entries, hr_dev->caps.max_cqes);
296 		return ERR_PTR(-EINVAL);
297 	}
298 
299 	hr_cq = kmalloc(sizeof(*hr_cq), GFP_KERNEL);
300 	if (!hr_cq)
301 		return ERR_PTR(-ENOMEM);
302 
303 	/* In v1 engine, parameter verification */
304 	if (cq_entries < HNS_ROCE_MIN_CQE_NUM)
305 		cq_entries = HNS_ROCE_MIN_CQE_NUM;
306 
307 	cq_entries = roundup_pow_of_two((unsigned int)cq_entries);
308 	hr_cq->ib_cq.cqe = cq_entries - 1;
309 	spin_lock_init(&hr_cq->lock);
310 
311 	if (context) {
312 		if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
313 			dev_err(dev, "Failed to copy_from_udata.\n");
314 			ret = -EFAULT;
315 			goto err_cq;
316 		}
317 
318 		/* Get user space address, write it into mtt table */
319 		ret = hns_roce_ib_get_cq_umem(hr_dev, context, &hr_cq->hr_buf,
320 					      &hr_cq->umem, ucmd.buf_addr,
321 					      cq_entries);
322 		if (ret) {
323 			dev_err(dev, "Failed to get_cq_umem.\n");
324 			goto err_cq;
325 		}
326 
327 		/* Get user space parameters */
328 		uar = &to_hr_ucontext(context)->uar;
329 	} else {
330 		/* Init mmt table and write buff address to mtt table */
331 		ret = hns_roce_ib_alloc_cq_buf(hr_dev, &hr_cq->hr_buf,
332 					       cq_entries);
333 		if (ret) {
334 			dev_err(dev, "Failed to alloc_cq_buf.\n");
335 			goto err_cq;
336 		}
337 
338 		uar = &hr_dev->priv_uar;
339 		hr_cq->cq_db_l = hr_dev->reg_base + ROCEE_DB_OTHERS_L_0_REG +
340 				 0x1000 * uar->index;
341 	}
342 
343 	/* Allocate cq index, fill cq_context */
344 	ret = hns_roce_cq_alloc(hr_dev, cq_entries, &hr_cq->hr_buf.hr_mtt, uar,
345 				hr_cq, vector);
346 	if (ret) {
347 		dev_err(dev, "Creat CQ .Failed to cq_alloc.\n");
348 		goto err_mtt;
349 	}
350 
351 	/*
352 	 * For the QP created by kernel space, tptr value should be initialized
353 	 * to zero; For the QP created by user space, it will cause synchronous
354 	 * problems if tptr is set to zero here, so we initialze it in user
355 	 * space.
356 	 */
357 	if (!context)
358 		*hr_cq->tptr_addr = 0;
359 
360 	/* Get created cq handler and carry out event */
361 	hr_cq->comp = hns_roce_ib_cq_comp;
362 	hr_cq->event = hns_roce_ib_cq_event;
363 	hr_cq->cq_depth = cq_entries;
364 
365 	if (context) {
366 		if (ib_copy_to_udata(udata, &hr_cq->cqn, sizeof(u64))) {
367 			ret = -EFAULT;
368 			goto err_cqc;
369 		}
370 	}
371 
372 	return &hr_cq->ib_cq;
373 
374 err_cqc:
375 	hns_roce_free_cq(hr_dev, hr_cq);
376 
377 err_mtt:
378 	hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
379 	if (context)
380 		ib_umem_release(hr_cq->umem);
381 	else
382 		hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
383 					hr_cq->ib_cq.cqe);
384 
385 err_cq:
386 	kfree(hr_cq);
387 	return ERR_PTR(ret);
388 }
389 
390 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
391 {
392 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
393 	struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
394 	int ret = 0;
395 
396 	if (hr_dev->hw->destroy_cq) {
397 		ret = hr_dev->hw->destroy_cq(ib_cq);
398 	} else {
399 		hns_roce_free_cq(hr_dev, hr_cq);
400 		hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
401 
402 		if (ib_cq->uobject)
403 			ib_umem_release(hr_cq->umem);
404 		else
405 			/* Free the buff of stored cq */
406 			hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
407 						ib_cq->cqe);
408 
409 		kfree(hr_cq);
410 	}
411 
412 	return ret;
413 }
414 
415 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
416 {
417 	struct device *dev = &hr_dev->pdev->dev;
418 	struct hns_roce_cq *cq;
419 
420 	cq = radix_tree_lookup(&hr_dev->cq_table.tree,
421 			       cqn & (hr_dev->caps.num_cqs - 1));
422 	if (!cq) {
423 		dev_warn(dev, "Completion event for bogus CQ 0x%08x\n", cqn);
424 		return;
425 	}
426 
427 	cq->comp(cq);
428 }
429 
430 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
431 {
432 	struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
433 	struct device *dev = &hr_dev->pdev->dev;
434 	struct hns_roce_cq *cq;
435 
436 	cq = radix_tree_lookup(&cq_table->tree,
437 			       cqn & (hr_dev->caps.num_cqs - 1));
438 	if (cq)
439 		atomic_inc(&cq->refcount);
440 
441 	if (!cq) {
442 		dev_warn(dev, "Async event for bogus CQ %08x\n", cqn);
443 		return;
444 	}
445 
446 	cq->event(cq, (enum hns_roce_event)event_type);
447 
448 	if (atomic_dec_and_test(&cq->refcount))
449 		complete(&cq->free);
450 }
451 
452 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev)
453 {
454 	struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
455 
456 	spin_lock_init(&cq_table->lock);
457 	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
458 
459 	return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs,
460 				    hr_dev->caps.num_cqs - 1,
461 				    hr_dev->caps.reserved_cqs, 0);
462 }
463 
464 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev)
465 {
466 	hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap);
467 }
468