1 /*
2  * Copyright (c) 2016 Hisilicon Limited.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef _HNS_ROCE_COMMON_H
34 #define _HNS_ROCE_COMMON_H
35 
36 #ifndef assert
37 #define assert(cond)
38 #endif
39 
40 #define roce_write(dev, reg, val)	writel((val), (dev)->reg_base + (reg))
41 #define roce_read(dev, reg)		readl((dev)->reg_base + (reg))
42 #define roce_raw_write(value, addr) \
43 	__raw_writel((__force u32)cpu_to_le32(value), (addr))
44 
45 #define roce_get_field(origin, mask, shift) \
46 	(((le32_to_cpu(origin)) & (mask)) >> (shift))
47 
48 #define roce_get_bit(origin, shift) \
49 	roce_get_field((origin), (1ul << (shift)), (shift))
50 
51 #define roce_set_field(origin, mask, shift, val) \
52 	do { \
53 		(origin) &= ~cpu_to_le32(mask); \
54 		(origin) |= cpu_to_le32(((u32)(val) << (shift)) & (mask)); \
55 	} while (0)
56 
57 #define roce_set_bit(origin, shift, val) \
58 	roce_set_field((origin), (1ul << (shift)), (shift), (val))
59 
60 /*
61  * roce_hw_index_cmp_lt - Compare two hardware index values in hisilicon
62  *                        SOC, check if a is less than b.
63  * @a: hardware index value
64  * @b: hardware index value
65  * @bits: the number of bits of a and b, range: 0~31.
66  *
67  * Hardware index increases continuously till max value, and then restart
68  * from zero, again and again. Because the bits of reg field is often
69  * limited, the reg field can only hold the low bits of the hardware index
70  * in hisilicon SOC.
71  * In some scenes we need to compare two values(a,b) getted from two reg
72  * fields in this driver, for example:
73  * If a equals 0xfffe, b equals 0x1 and bits equals 16, we think b has
74  * incresed from 0xffff to 0x1 and a is less than b.
75  * If a equals 0xfffe, b equals 0x0xf001 and bits equals 16, we think a
76  * is bigger than b.
77  *
78  * Return true on a less than b, otherwise false.
79  */
80 #define roce_hw_index_mask(bits)	((1ul << (bits)) - 1)
81 #define roce_hw_index_shift(bits)	(32 - (bits))
82 #define roce_hw_index_cmp_lt(a, b, bits) \
83 	((int)((((a) - (b)) & roce_hw_index_mask(bits)) << \
84 		roce_hw_index_shift(bits)) < 0)
85 
86 #define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3
87 #define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4
88 
89 #define ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S 5
90 
91 #define ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S 6
92 
93 #define ROCEE_GLB_CFG_ROCEE_PORT_ST_S 10
94 #define ROCEE_GLB_CFG_ROCEE_PORT_ST_M  \
95 	(((1UL << 6) - 1) << ROCEE_GLB_CFG_ROCEE_PORT_ST_S)
96 
97 #define ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S 16
98 
99 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0
100 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M  \
101 	(((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S)
102 
103 #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S 24
104 #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M  \
105 	(((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S)
106 
107 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0
108 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M   \
109 	(((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S)
110 
111 #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S 24
112 #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M   \
113 	(((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S)
114 
115 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0
116 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M   \
117 	(((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S)
118 
119 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S 16
120 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M   \
121 	(((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S)
122 
123 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0
124 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M   \
125 	(((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S)
126 
127 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S 16
128 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M   \
129 	(((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S)
130 
131 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0
132 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_M   \
133 	(((1UL << 8) - 1) << ROCEE_RAQ_WL_ROCEE_RAQ_WL_S)
134 
135 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0
136 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M   \
137 	(((1UL << 15) - 1) << \
138 	ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S)
139 
140 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S 16
141 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M   \
142 	(((1UL << 4) - 1) << \
143 	ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S)
144 
145 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S 20
146 
147 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE 21
148 
149 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0
150 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M   \
151 	(((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S)
152 
153 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S 5
154 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M   \
155 	(((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S)
156 
157 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0
158 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M   \
159 	(((1UL << 5) - 1) << ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S)
160 
161 #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S 5
162 #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M   \
163 	(((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S)
164 
165 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0
166 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M   \
167 	(((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S)
168 
169 #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S 8
170 #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M   \
171 	(((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S)
172 
173 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S 0
174 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M   \
175 	(((1UL << 19) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S)
176 
177 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_S 19
178 
179 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S 20
180 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M   \
181 	(((1UL << 2) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S)
182 
183 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S 22
184 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M   \
185 	(((1UL << 5) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S)
186 
187 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S 31
188 
189 #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S 0
190 #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M   \
191 	(((1UL << 3) - 1) << ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S)
192 
193 #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S 0
194 #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M   \
195 	(((1UL << 15) - 1) << ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S)
196 
197 #define ROCEE_MB6_ROCEE_MB_CMD_S 0
198 #define ROCEE_MB6_ROCEE_MB_CMD_M   \
199 	(((1UL << 8) - 1) << ROCEE_MB6_ROCEE_MB_CMD_S)
200 
201 #define ROCEE_MB6_ROCEE_MB_CMD_MDF_S 8
202 #define ROCEE_MB6_ROCEE_MB_CMD_MDF_M   \
203 	(((1UL << 4) - 1) << ROCEE_MB6_ROCEE_MB_CMD_MDF_S)
204 
205 #define ROCEE_MB6_ROCEE_MB_EVENT_S 14
206 
207 #define ROCEE_MB6_ROCEE_MB_HW_RUN_S 15
208 
209 #define ROCEE_MB6_ROCEE_MB_TOKEN_S 16
210 #define ROCEE_MB6_ROCEE_MB_TOKEN_M   \
211 	(((1UL << 16) - 1) << ROCEE_MB6_ROCEE_MB_TOKEN_S)
212 
213 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S 0
214 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M   \
215 	(((1UL << 24) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S)
216 
217 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S 24
218 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M   \
219 	(((1UL << 4) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S)
220 
221 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S 28
222 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M   \
223 	(((1UL << 3) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S)
224 
225 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S 31
226 
227 #define ROCEE_SMAC_H_ROCEE_SMAC_H_S 0
228 #define ROCEE_SMAC_H_ROCEE_SMAC_H_M   \
229 	(((1UL << 16) - 1) << ROCEE_SMAC_H_ROCEE_SMAC_H_S)
230 
231 #define ROCEE_SMAC_H_ROCEE_PORT_MTU_S 16
232 #define ROCEE_SMAC_H_ROCEE_PORT_MTU_M   \
233 	(((1UL << 4) - 1) << ROCEE_SMAC_H_ROCEE_PORT_MTU_S)
234 
235 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S 0
236 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M   \
237 	(((1UL << 2) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S)
238 
239 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S 8
240 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M   \
241 	(((1UL << 4) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S)
242 
243 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S 17
244 
245 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S 0
246 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M   \
247 	(((1UL << 5) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S)
248 
249 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S 16
250 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M   \
251 	(((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S)
252 
253 #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S 0
254 #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M   \
255 	(((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S)
256 
257 #define ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S 16
258 #define ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S 1
259 #define ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S 0
260 
261 #define ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S 0
262 #define ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S 1
263 
264 #define ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S 0
265 
266 #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S 0
267 #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M   \
268 	(((1UL << 28) - 1) << ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S)
269 
270 #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S 0
271 #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M   \
272 	(((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)
273 
274 #define ROCEE_SDB_PTR_CMP_BITS 28
275 
276 #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0
277 #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M   \
278 	(((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S)
279 
280 #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S	0
281 #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M	\
282 	(((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S)
283 
284 #define ROCEE_SDB_CNT_CMP_BITS 16
285 
286 #define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S	20
287 
288 #define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0
289 
290 /*************ROCEE_REG DEFINITION****************/
291 #define ROCEE_VENDOR_ID_REG			0x0
292 #define ROCEE_VENDOR_PART_ID_REG		0x4
293 
294 #define ROCEE_SYS_IMAGE_GUID_L_REG		0xC
295 #define ROCEE_SYS_IMAGE_GUID_H_REG		0x10
296 
297 #define ROCEE_PORT_GID_L_0_REG			0x50
298 #define ROCEE_PORT_GID_ML_0_REG			0x54
299 #define ROCEE_PORT_GID_MH_0_REG			0x58
300 #define ROCEE_PORT_GID_H_0_REG			0x5C
301 
302 #define ROCEE_BT_CMD_H_REG			0x204
303 
304 #define ROCEE_SMAC_L_0_REG			0x240
305 #define ROCEE_SMAC_H_0_REG			0x244
306 
307 #define ROCEE_QP1C_CFG3_0_REG			0x27C
308 
309 #define ROCEE_CAEP_AEQE_CONS_IDX_REG		0x3AC
310 #define ROCEE_CAEP_CEQC_CONS_IDX_0_REG		0x3BC
311 
312 #define ROCEE_ECC_UCERR_ALM1_REG		0xB38
313 #define ROCEE_ECC_UCERR_ALM2_REG		0xB3C
314 #define ROCEE_ECC_CERR_ALM1_REG			0xB44
315 #define ROCEE_ECC_CERR_ALM2_REG			0xB48
316 
317 #define ROCEE_ACK_DELAY_REG			0x14
318 #define ROCEE_GLB_CFG_REG			0x18
319 
320 #define ROCEE_DMAE_USER_CFG1_REG		0x40
321 #define ROCEE_DMAE_USER_CFG2_REG		0x44
322 
323 #define ROCEE_DB_SQ_WL_REG			0x154
324 #define ROCEE_DB_OTHERS_WL_REG			0x158
325 #define ROCEE_RAQ_WL_REG			0x15C
326 #define ROCEE_WRMS_POL_TIME_INTERVAL_REG	0x160
327 #define ROCEE_EXT_DB_SQ_REG			0x164
328 #define ROCEE_EXT_DB_SQ_H_REG			0x168
329 #define ROCEE_EXT_DB_OTH_REG			0x16C
330 
331 #define ROCEE_EXT_DB_OTH_H_REG			0x170
332 #define ROCEE_EXT_DB_SQ_WL_EMPTY_REG		0x174
333 #define ROCEE_EXT_DB_SQ_WL_REG			0x178
334 #define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG	0x17C
335 #define ROCEE_EXT_DB_OTHERS_WL_REG		0x180
336 #define ROCEE_EXT_RAQ_REG			0x184
337 #define ROCEE_EXT_RAQ_H_REG			0x188
338 
339 #define ROCEE_CAEP_CE_INTERVAL_CFG_REG		0x190
340 #define ROCEE_CAEP_CE_BURST_NUM_CFG_REG		0x194
341 #define ROCEE_BT_CMD_L_REG			0x200
342 
343 #define ROCEE_MB1_REG				0x210
344 #define ROCEE_MB6_REG				0x224
345 #define ROCEE_DB_SQ_L_0_REG			0x230
346 #define ROCEE_DB_OTHERS_L_0_REG			0x238
347 #define ROCEE_QP1C_CFG0_0_REG			0x270
348 
349 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG		0x3A0
350 #define ROCEE_CAEP_CEQC_SHIFT_0_REG		0x3B0
351 #define ROCEE_CAEP_CE_IRQ_MASK_0_REG		0x3C0
352 #define ROCEE_CAEP_CEQ_ALM_OVF_0_REG		0x3C4
353 #define ROCEE_CAEP_AE_MASK_REG			0x6C8
354 #define ROCEE_CAEP_AE_ST_REG			0x6CC
355 
356 #define ROCEE_SDB_ISSUE_PTR_REG			0x758
357 #define ROCEE_SDB_SEND_PTR_REG			0x75C
358 #define ROCEE_CAEP_CQE_WCMD_EMPTY		0x850
359 #define ROCEE_SCAEP_WR_CQE_CNT			0x8D0
360 #define ROCEE_SDB_INV_CNT_REG			0x9A4
361 #define ROCEE_SDB_RETRY_CNT_REG			0x9AC
362 #define ROCEE_TSP_BP_ST_REG			0x9EC
363 #define ROCEE_ECC_UCERR_ALM0_REG		0xB34
364 #define ROCEE_ECC_CERR_ALM0_REG			0xB40
365 
366 /* V2 ROCEE REG */
367 #define ROCEE_TX_CMQ_BASEADDR_L_REG		0x07000
368 #define ROCEE_TX_CMQ_BASEADDR_H_REG		0x07004
369 #define ROCEE_TX_CMQ_DEPTH_REG			0x07008
370 #define ROCEE_TX_CMQ_TAIL_REG			0x07010
371 #define ROCEE_TX_CMQ_HEAD_REG			0x07014
372 
373 #define ROCEE_RX_CMQ_BASEADDR_L_REG		0x07018
374 #define ROCEE_RX_CMQ_BASEADDR_H_REG		0x0701c
375 #define ROCEE_RX_CMQ_DEPTH_REG			0x07020
376 #define ROCEE_RX_CMQ_TAIL_REG			0x07024
377 #define ROCEE_RX_CMQ_HEAD_REG			0x07028
378 
379 #define ROCEE_VF_MB_CFG0_REG			0x40
380 #define ROCEE_VF_MB_STATUS_REG			0x58
381 
382 #define ROCEE_VF_EQ_DB_CFG0_REG			0x238
383 #define ROCEE_VF_EQ_DB_CFG1_REG			0x23C
384 
385 #define ROCEE_VF_ABN_INT_CFG_REG		0x13000
386 #define ROCEE_VF_ABN_INT_ST_REG			0x13004
387 #define ROCEE_VF_ABN_INT_EN_REG			0x13008
388 #define ROCEE_VF_EVENT_INT_EN_REG		0x1300c
389 
390 #endif /* _HNS_ROCE_COMMON_H */
391