1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_COMMON_H 34 #define _HNS_ROCE_COMMON_H 35 36 #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) 37 #define roce_read(dev, reg) readl((dev)->reg_base + (reg)) 38 #define roce_raw_write(value, addr) \ 39 __raw_writel((__force u32)cpu_to_le32(value), (addr)) 40 41 #define roce_get_field(origin, mask, shift) \ 42 ((le32_to_cpu(origin) & (mask)) >> (u32)(shift)) 43 44 #define roce_get_bit(origin, shift) \ 45 roce_get_field((origin), (1ul << (shift)), (shift)) 46 47 #define roce_set_field(origin, mask, shift, val) \ 48 do { \ 49 (origin) &= ~cpu_to_le32(mask); \ 50 (origin) |= cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask)); \ 51 } while (0) 52 53 #define roce_set_bit(origin, shift, val) \ 54 roce_set_field((origin), (1ul << (shift)), (shift), (val)) 55 56 #define FIELD_LOC(field_type, field_h, field_l) field_type, field_h, field_l 57 58 #define _hr_reg_enable(ptr, field_type, field_h, field_l) \ 59 ({ \ 60 const field_type *_ptr = ptr; \ 61 *((__le32 *)_ptr + (field_h) / 32) |= \ 62 cpu_to_le32(BIT((field_l) % 32)) + \ 63 BUILD_BUG_ON_ZERO((field_h) != (field_l)); \ 64 }) 65 66 #define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field) 67 68 #define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3 69 #define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4 70 71 #define ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S 5 72 73 #define ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S 6 74 75 #define ROCEE_GLB_CFG_ROCEE_PORT_ST_S 10 76 #define ROCEE_GLB_CFG_ROCEE_PORT_ST_M \ 77 (((1UL << 6) - 1) << ROCEE_GLB_CFG_ROCEE_PORT_ST_S) 78 79 #define ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S 16 80 81 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0 82 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M \ 83 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S) 84 85 #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S 24 86 #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M \ 87 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S) 88 89 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0 90 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M \ 91 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S) 92 93 #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S 24 94 #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M \ 95 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S) 96 97 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0 98 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M \ 99 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S) 100 101 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S 16 102 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M \ 103 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S) 104 105 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0 106 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M \ 107 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S) 108 109 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S 16 110 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M \ 111 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S) 112 113 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0 114 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_M \ 115 (((1UL << 8) - 1) << ROCEE_RAQ_WL_ROCEE_RAQ_WL_S) 116 117 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0 118 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M \ 119 (((1UL << 15) - 1) << \ 120 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S) 121 122 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S 16 123 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M \ 124 (((1UL << 4) - 1) << \ 125 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S) 126 127 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S 20 128 129 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE 21 130 131 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0 132 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M \ 133 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S) 134 135 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S 5 136 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M \ 137 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S) 138 139 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0 140 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M \ 141 (((1UL << 5) - 1) << ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S) 142 143 #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S 5 144 #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M \ 145 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S) 146 147 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0 148 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M \ 149 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S) 150 151 #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S 8 152 #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M \ 153 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S) 154 155 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S 0 156 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M \ 157 (((1UL << 19) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S) 158 159 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_S 19 160 161 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S 20 162 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M \ 163 (((1UL << 2) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S) 164 165 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S 22 166 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M \ 167 (((1UL << 5) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S) 168 169 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S 31 170 171 #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S 0 172 #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M \ 173 (((1UL << 3) - 1) << ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S) 174 175 #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S 0 176 #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M \ 177 (((1UL << 15) - 1) << ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S) 178 179 #define ROCEE_MB6_ROCEE_MB_CMD_S 0 180 #define ROCEE_MB6_ROCEE_MB_CMD_M \ 181 (((1UL << 8) - 1) << ROCEE_MB6_ROCEE_MB_CMD_S) 182 183 #define ROCEE_MB6_ROCEE_MB_CMD_MDF_S 8 184 #define ROCEE_MB6_ROCEE_MB_CMD_MDF_M \ 185 (((1UL << 4) - 1) << ROCEE_MB6_ROCEE_MB_CMD_MDF_S) 186 187 #define ROCEE_MB6_ROCEE_MB_EVENT_S 14 188 189 #define ROCEE_MB6_ROCEE_MB_HW_RUN_S 15 190 191 #define ROCEE_MB6_ROCEE_MB_TOKEN_S 16 192 #define ROCEE_MB6_ROCEE_MB_TOKEN_M \ 193 (((1UL << 16) - 1) << ROCEE_MB6_ROCEE_MB_TOKEN_S) 194 195 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S 0 196 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M \ 197 (((1UL << 24) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S) 198 199 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S 24 200 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M \ 201 (((1UL << 4) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S) 202 203 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S 28 204 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M \ 205 (((1UL << 3) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S) 206 207 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S 31 208 209 #define ROCEE_SMAC_H_ROCEE_SMAC_H_S 0 210 #define ROCEE_SMAC_H_ROCEE_SMAC_H_M \ 211 (((1UL << 16) - 1) << ROCEE_SMAC_H_ROCEE_SMAC_H_S) 212 213 #define ROCEE_SMAC_H_ROCEE_PORT_MTU_S 16 214 #define ROCEE_SMAC_H_ROCEE_PORT_MTU_M \ 215 (((1UL << 4) - 1) << ROCEE_SMAC_H_ROCEE_PORT_MTU_S) 216 217 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S 0 218 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M \ 219 (((1UL << 2) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S) 220 221 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S 8 222 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M \ 223 (((1UL << 4) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S) 224 225 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S 17 226 227 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S 0 228 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M \ 229 (((1UL << 5) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S) 230 231 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S 16 232 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M \ 233 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S) 234 235 #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S 0 236 #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M \ 237 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S) 238 239 #define ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S 16 240 #define ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S 1 241 #define ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S 0 242 243 #define ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S 0 244 #define ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S 1 245 246 #define ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S 0 247 248 #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S 0 249 #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M \ 250 (((1UL << 28) - 1) << ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) 251 252 #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S 0 253 #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \ 254 (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) 255 256 #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0 257 #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \ 258 (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S) 259 260 #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S 0 261 #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M \ 262 (((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S) 263 264 #define ROCEE_SDB_CNT_CMP_BITS 16 265 266 #define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S 20 267 268 #define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0 269 270 /*************ROCEE_REG DEFINITION****************/ 271 #define ROCEE_VENDOR_ID_REG 0x0 272 #define ROCEE_VENDOR_PART_ID_REG 0x4 273 274 #define ROCEE_SYS_IMAGE_GUID_L_REG 0xC 275 #define ROCEE_SYS_IMAGE_GUID_H_REG 0x10 276 277 #define ROCEE_PORT_GID_L_0_REG 0x50 278 #define ROCEE_PORT_GID_ML_0_REG 0x54 279 #define ROCEE_PORT_GID_MH_0_REG 0x58 280 #define ROCEE_PORT_GID_H_0_REG 0x5C 281 282 #define ROCEE_BT_CMD_H_REG 0x204 283 284 #define ROCEE_SMAC_L_0_REG 0x240 285 #define ROCEE_SMAC_H_0_REG 0x244 286 287 #define ROCEE_QP1C_CFG3_0_REG 0x27C 288 289 #define ROCEE_CAEP_AEQE_CONS_IDX_REG 0x3AC 290 #define ROCEE_CAEP_CEQC_CONS_IDX_0_REG 0x3BC 291 292 #define ROCEE_ECC_UCERR_ALM1_REG 0xB38 293 #define ROCEE_ECC_UCERR_ALM2_REG 0xB3C 294 #define ROCEE_ECC_CERR_ALM1_REG 0xB44 295 #define ROCEE_ECC_CERR_ALM2_REG 0xB48 296 297 #define ROCEE_ACK_DELAY_REG 0x14 298 #define ROCEE_GLB_CFG_REG 0x18 299 300 #define ROCEE_DMAE_USER_CFG1_REG 0x40 301 #define ROCEE_DMAE_USER_CFG2_REG 0x44 302 303 #define ROCEE_DB_SQ_WL_REG 0x154 304 #define ROCEE_DB_OTHERS_WL_REG 0x158 305 #define ROCEE_RAQ_WL_REG 0x15C 306 #define ROCEE_WRMS_POL_TIME_INTERVAL_REG 0x160 307 #define ROCEE_EXT_DB_SQ_REG 0x164 308 #define ROCEE_EXT_DB_SQ_H_REG 0x168 309 #define ROCEE_EXT_DB_OTH_REG 0x16C 310 311 #define ROCEE_EXT_DB_OTH_H_REG 0x170 312 #define ROCEE_EXT_DB_SQ_WL_EMPTY_REG 0x174 313 #define ROCEE_EXT_DB_SQ_WL_REG 0x178 314 #define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG 0x17C 315 #define ROCEE_EXT_DB_OTHERS_WL_REG 0x180 316 #define ROCEE_EXT_RAQ_REG 0x184 317 #define ROCEE_EXT_RAQ_H_REG 0x188 318 319 #define ROCEE_CAEP_CE_INTERVAL_CFG_REG 0x190 320 #define ROCEE_CAEP_CE_BURST_NUM_CFG_REG 0x194 321 #define ROCEE_BT_CMD_L_REG 0x200 322 323 #define ROCEE_MB1_REG 0x210 324 #define ROCEE_MB6_REG 0x224 325 #define ROCEE_DB_SQ_L_0_REG 0x230 326 #define ROCEE_DB_OTHERS_L_0_REG 0x238 327 #define ROCEE_QP1C_CFG0_0_REG 0x270 328 329 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG 0x3A0 330 #define ROCEE_CAEP_CEQC_SHIFT_0_REG 0x3B0 331 #define ROCEE_CAEP_CE_IRQ_MASK_0_REG 0x3C0 332 #define ROCEE_CAEP_CEQ_ALM_OVF_0_REG 0x3C4 333 #define ROCEE_CAEP_AE_MASK_REG 0x6C8 334 #define ROCEE_CAEP_AE_ST_REG 0x6CC 335 336 #define ROCEE_CAEP_CQE_WCMD_EMPTY 0x850 337 #define ROCEE_SCAEP_WR_CQE_CNT 0x8D0 338 #define ROCEE_ECC_UCERR_ALM0_REG 0xB34 339 #define ROCEE_ECC_CERR_ALM0_REG 0xB40 340 341 /* V2 ROCEE REG */ 342 #define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000 343 #define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004 344 #define ROCEE_TX_CMQ_DEPTH_REG 0x07008 345 #define ROCEE_TX_CMQ_TAIL_REG 0x07010 346 #define ROCEE_TX_CMQ_HEAD_REG 0x07014 347 348 #define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018 349 #define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c 350 #define ROCEE_RX_CMQ_DEPTH_REG 0x07020 351 #define ROCEE_RX_CMQ_TAIL_REG 0x07024 352 #define ROCEE_RX_CMQ_HEAD_REG 0x07028 353 354 #define ROCEE_VF_EQ_DB_CFG0_REG 0x238 355 #define ROCEE_VF_EQ_DB_CFG1_REG 0x23C 356 357 #define ROCEE_VF_ABN_INT_CFG_REG 0x13000 358 #define ROCEE_VF_ABN_INT_ST_REG 0x13004 359 #define ROCEE_VF_ABN_INT_EN_REG 0x13008 360 #define ROCEE_VF_EVENT_INT_EN_REG 0x1300c 361 362 #endif /* _HNS_ROCE_COMMON_H */ 363