1 /* 2 * Copyright(c) 2015 - 2018 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <rdma/ib_mad.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <linux/io.h> 51 #include <linux/module.h> 52 #include <linux/utsname.h> 53 #include <linux/rculist.h> 54 #include <linux/mm.h> 55 #include <linux/vmalloc.h> 56 #include <rdma/opa_addr.h> 57 58 #include "hfi.h" 59 #include "common.h" 60 #include "device.h" 61 #include "trace.h" 62 #include "qp.h" 63 #include "verbs_txreq.h" 64 #include "debugfs.h" 65 #include "vnic.h" 66 #include "fault.h" 67 #include "affinity.h" 68 69 static unsigned int hfi1_lkey_table_size = 16; 70 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint, 71 S_IRUGO); 72 MODULE_PARM_DESC(lkey_table_size, 73 "LKEY table size in bits (2^n, 1 <= n <= 23)"); 74 75 static unsigned int hfi1_max_pds = 0xFFFF; 76 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO); 77 MODULE_PARM_DESC(max_pds, 78 "Maximum number of protection domains to support"); 79 80 static unsigned int hfi1_max_ahs = 0xFFFF; 81 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO); 82 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support"); 83 84 unsigned int hfi1_max_cqes = 0x2FFFFF; 85 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO); 86 MODULE_PARM_DESC(max_cqes, 87 "Maximum number of completion queue entries to support"); 88 89 unsigned int hfi1_max_cqs = 0x1FFFF; 90 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO); 91 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support"); 92 93 unsigned int hfi1_max_qp_wrs = 0x3FFF; 94 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO); 95 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support"); 96 97 unsigned int hfi1_max_qps = 32768; 98 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO); 99 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support"); 100 101 unsigned int hfi1_max_sges = 0x60; 102 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO); 103 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support"); 104 105 unsigned int hfi1_max_mcast_grps = 16384; 106 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO); 107 MODULE_PARM_DESC(max_mcast_grps, 108 "Maximum number of multicast groups to support"); 109 110 unsigned int hfi1_max_mcast_qp_attached = 16; 111 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached, 112 uint, S_IRUGO); 113 MODULE_PARM_DESC(max_mcast_qp_attached, 114 "Maximum number of attached QPs to support"); 115 116 unsigned int hfi1_max_srqs = 1024; 117 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO); 118 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support"); 119 120 unsigned int hfi1_max_srq_sges = 128; 121 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO); 122 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support"); 123 124 unsigned int hfi1_max_srq_wrs = 0x1FFFF; 125 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO); 126 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support"); 127 128 unsigned short piothreshold = 256; 129 module_param(piothreshold, ushort, S_IRUGO); 130 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio"); 131 132 static unsigned int sge_copy_mode; 133 module_param(sge_copy_mode, uint, S_IRUGO); 134 MODULE_PARM_DESC(sge_copy_mode, 135 "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS"); 136 137 static void verbs_sdma_complete( 138 struct sdma_txreq *cookie, 139 int status); 140 141 static int pio_wait(struct rvt_qp *qp, 142 struct send_context *sc, 143 struct hfi1_pkt_state *ps, 144 u32 flag); 145 146 /* Length of buffer to create verbs txreq cache name */ 147 #define TXREQ_NAME_LEN 24 148 149 /* 16B trailing buffer */ 150 static const u8 trail_buf[MAX_16B_PADDING]; 151 152 static uint wss_threshold = 80; 153 module_param(wss_threshold, uint, S_IRUGO); 154 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy"); 155 static uint wss_clean_period = 256; 156 module_param(wss_clean_period, uint, S_IRUGO); 157 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned"); 158 159 /* 160 * Translate ib_wr_opcode into ib_wc_opcode. 161 */ 162 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = { 163 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE, 164 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE, 165 [IB_WR_SEND] = IB_WC_SEND, 166 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND, 167 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ, 168 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP, 169 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD, 170 [IB_WR_SEND_WITH_INV] = IB_WC_SEND, 171 [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV, 172 [IB_WR_REG_MR] = IB_WC_REG_MR 173 }; 174 175 /* 176 * Length of header by opcode, 0 --> not supported 177 */ 178 const u8 hdr_len_by_opcode[256] = { 179 /* RC */ 180 [IB_OPCODE_RC_SEND_FIRST] = 12 + 8, 181 [IB_OPCODE_RC_SEND_MIDDLE] = 12 + 8, 182 [IB_OPCODE_RC_SEND_LAST] = 12 + 8, 183 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 184 [IB_OPCODE_RC_SEND_ONLY] = 12 + 8, 185 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4, 186 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = 12 + 8 + 16, 187 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = 12 + 8, 188 [IB_OPCODE_RC_RDMA_WRITE_LAST] = 12 + 8, 189 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 190 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = 12 + 8 + 16, 191 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20, 192 [IB_OPCODE_RC_RDMA_READ_REQUEST] = 12 + 8 + 16, 193 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = 12 + 8 + 4, 194 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = 12 + 8, 195 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = 12 + 8 + 4, 196 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = 12 + 8 + 4, 197 [IB_OPCODE_RC_ACKNOWLEDGE] = 12 + 8 + 4, 198 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = 12 + 8 + 4 + 8, 199 [IB_OPCODE_RC_COMPARE_SWAP] = 12 + 8 + 28, 200 [IB_OPCODE_RC_FETCH_ADD] = 12 + 8 + 28, 201 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = 12 + 8 + 4, 202 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = 12 + 8 + 4, 203 /* UC */ 204 [IB_OPCODE_UC_SEND_FIRST] = 12 + 8, 205 [IB_OPCODE_UC_SEND_MIDDLE] = 12 + 8, 206 [IB_OPCODE_UC_SEND_LAST] = 12 + 8, 207 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 208 [IB_OPCODE_UC_SEND_ONLY] = 12 + 8, 209 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4, 210 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = 12 + 8 + 16, 211 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = 12 + 8, 212 [IB_OPCODE_UC_RDMA_WRITE_LAST] = 12 + 8, 213 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 214 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = 12 + 8 + 16, 215 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20, 216 /* UD */ 217 [IB_OPCODE_UD_SEND_ONLY] = 12 + 8 + 8, 218 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 12 219 }; 220 221 static const opcode_handler opcode_handler_tbl[256] = { 222 /* RC */ 223 [IB_OPCODE_RC_SEND_FIRST] = &hfi1_rc_rcv, 224 [IB_OPCODE_RC_SEND_MIDDLE] = &hfi1_rc_rcv, 225 [IB_OPCODE_RC_SEND_LAST] = &hfi1_rc_rcv, 226 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv, 227 [IB_OPCODE_RC_SEND_ONLY] = &hfi1_rc_rcv, 228 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv, 229 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = &hfi1_rc_rcv, 230 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = &hfi1_rc_rcv, 231 [IB_OPCODE_RC_RDMA_WRITE_LAST] = &hfi1_rc_rcv, 232 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv, 233 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = &hfi1_rc_rcv, 234 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv, 235 [IB_OPCODE_RC_RDMA_READ_REQUEST] = &hfi1_rc_rcv, 236 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = &hfi1_rc_rcv, 237 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = &hfi1_rc_rcv, 238 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = &hfi1_rc_rcv, 239 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = &hfi1_rc_rcv, 240 [IB_OPCODE_RC_ACKNOWLEDGE] = &hfi1_rc_rcv, 241 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = &hfi1_rc_rcv, 242 [IB_OPCODE_RC_COMPARE_SWAP] = &hfi1_rc_rcv, 243 [IB_OPCODE_RC_FETCH_ADD] = &hfi1_rc_rcv, 244 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = &hfi1_rc_rcv, 245 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = &hfi1_rc_rcv, 246 /* UC */ 247 [IB_OPCODE_UC_SEND_FIRST] = &hfi1_uc_rcv, 248 [IB_OPCODE_UC_SEND_MIDDLE] = &hfi1_uc_rcv, 249 [IB_OPCODE_UC_SEND_LAST] = &hfi1_uc_rcv, 250 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv, 251 [IB_OPCODE_UC_SEND_ONLY] = &hfi1_uc_rcv, 252 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv, 253 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = &hfi1_uc_rcv, 254 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = &hfi1_uc_rcv, 255 [IB_OPCODE_UC_RDMA_WRITE_LAST] = &hfi1_uc_rcv, 256 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv, 257 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = &hfi1_uc_rcv, 258 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv, 259 /* UD */ 260 [IB_OPCODE_UD_SEND_ONLY] = &hfi1_ud_rcv, 261 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_ud_rcv, 262 /* CNP */ 263 [IB_OPCODE_CNP] = &hfi1_cnp_rcv 264 }; 265 266 #define OPMASK 0x1f 267 268 static const u32 pio_opmask[BIT(3)] = { 269 /* RC */ 270 [IB_OPCODE_RC >> 5] = 271 BIT(RC_OP(SEND_ONLY) & OPMASK) | 272 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) | 273 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) | 274 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) | 275 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) | 276 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) | 277 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) | 278 BIT(RC_OP(COMPARE_SWAP) & OPMASK) | 279 BIT(RC_OP(FETCH_ADD) & OPMASK), 280 /* UC */ 281 [IB_OPCODE_UC >> 5] = 282 BIT(UC_OP(SEND_ONLY) & OPMASK) | 283 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) | 284 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) | 285 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK), 286 }; 287 288 /* 289 * System image GUID. 290 */ 291 __be64 ib_hfi1_sys_image_guid; 292 293 /* 294 * Make sure the QP is ready and able to accept the given opcode. 295 */ 296 static inline opcode_handler qp_ok(struct hfi1_packet *packet) 297 { 298 if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK)) 299 return NULL; 300 if (((packet->opcode & RVT_OPCODE_QP_MASK) == 301 packet->qp->allowed_ops) || 302 (packet->opcode == IB_OPCODE_CNP)) 303 return opcode_handler_tbl[packet->opcode]; 304 305 return NULL; 306 } 307 308 static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc) 309 { 310 #ifdef CONFIG_FAULT_INJECTION 311 if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP) 312 /* 313 * In order to drop non-IB traffic we 314 * set PbcInsertHrc to NONE (0x2). 315 * The packet will still be delivered 316 * to the receiving node but a 317 * KHdrHCRCErr (KDETH packet with a bad 318 * HCRC) will be triggered and the 319 * packet will not be delivered to the 320 * correct context. 321 */ 322 pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT; 323 else 324 /* 325 * In order to drop regular verbs 326 * traffic we set the PbcTestEbp 327 * flag. The packet will still be 328 * delivered to the receiving node but 329 * a 'late ebp error' will be 330 * triggered and will be dropped. 331 */ 332 pbc |= PBC_TEST_EBP; 333 #endif 334 return pbc; 335 } 336 337 static int hfi1_do_pkey_check(struct hfi1_packet *packet) 338 { 339 struct hfi1_ctxtdata *rcd = packet->rcd; 340 struct hfi1_pportdata *ppd = rcd->ppd; 341 struct hfi1_16b_header *hdr = packet->hdr; 342 u16 pkey; 343 344 /* Pkey check needed only for bypass packets */ 345 if (packet->etype != RHF_RCV_TYPE_BYPASS) 346 return 0; 347 348 /* Perform pkey check */ 349 pkey = hfi1_16B_get_pkey(hdr); 350 return ingress_pkey_check(ppd, pkey, packet->sc, 351 packet->qp->s_pkey_index, 352 packet->slid, true); 353 } 354 355 static inline void hfi1_handle_packet(struct hfi1_packet *packet, 356 bool is_mcast) 357 { 358 u32 qp_num; 359 struct hfi1_ctxtdata *rcd = packet->rcd; 360 struct hfi1_pportdata *ppd = rcd->ppd; 361 struct hfi1_ibport *ibp = rcd_to_iport(rcd); 362 struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi; 363 opcode_handler packet_handler; 364 unsigned long flags; 365 366 inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]); 367 368 if (unlikely(is_mcast)) { 369 struct rvt_mcast *mcast; 370 struct rvt_mcast_qp *p; 371 372 if (!packet->grh) 373 goto drop; 374 mcast = rvt_mcast_find(&ibp->rvp, 375 &packet->grh->dgid, 376 opa_get_lid(packet->dlid, 9B)); 377 if (!mcast) 378 goto drop; 379 list_for_each_entry_rcu(p, &mcast->qp_list, list) { 380 packet->qp = p->qp; 381 if (hfi1_do_pkey_check(packet)) 382 goto drop; 383 spin_lock_irqsave(&packet->qp->r_lock, flags); 384 packet_handler = qp_ok(packet); 385 if (likely(packet_handler)) 386 packet_handler(packet); 387 else 388 ibp->rvp.n_pkt_drops++; 389 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 390 } 391 /* 392 * Notify rvt_multicast_detach() if it is waiting for us 393 * to finish. 394 */ 395 if (atomic_dec_return(&mcast->refcount) <= 1) 396 wake_up(&mcast->wait); 397 } else { 398 /* Get the destination QP number. */ 399 if (packet->etype == RHF_RCV_TYPE_BYPASS && 400 hfi1_16B_get_l4(packet->hdr) == OPA_16B_L4_FM) 401 qp_num = hfi1_16B_get_dest_qpn(packet->mgmt); 402 else 403 qp_num = ib_bth_get_qpn(packet->ohdr); 404 405 rcu_read_lock(); 406 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num); 407 if (!packet->qp) 408 goto unlock_drop; 409 410 if (hfi1_do_pkey_check(packet)) 411 goto unlock_drop; 412 413 spin_lock_irqsave(&packet->qp->r_lock, flags); 414 packet_handler = qp_ok(packet); 415 if (likely(packet_handler)) 416 packet_handler(packet); 417 else 418 ibp->rvp.n_pkt_drops++; 419 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 420 rcu_read_unlock(); 421 } 422 return; 423 unlock_drop: 424 rcu_read_unlock(); 425 drop: 426 ibp->rvp.n_pkt_drops++; 427 } 428 429 /** 430 * hfi1_ib_rcv - process an incoming packet 431 * @packet: data packet information 432 * 433 * This is called to process an incoming packet at interrupt level. 434 */ 435 void hfi1_ib_rcv(struct hfi1_packet *packet) 436 { 437 struct hfi1_ctxtdata *rcd = packet->rcd; 438 439 trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf))); 440 hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid)); 441 } 442 443 void hfi1_16B_rcv(struct hfi1_packet *packet) 444 { 445 struct hfi1_ctxtdata *rcd = packet->rcd; 446 447 trace_input_ibhdr(rcd->dd, packet, false); 448 hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid)); 449 } 450 451 /* 452 * This is called from a timer to check for QPs 453 * which need kernel memory in order to send a packet. 454 */ 455 static void mem_timer(struct timer_list *t) 456 { 457 struct hfi1_ibdev *dev = from_timer(dev, t, mem_timer); 458 struct list_head *list = &dev->memwait; 459 struct rvt_qp *qp = NULL; 460 struct iowait *wait; 461 unsigned long flags; 462 struct hfi1_qp_priv *priv; 463 464 write_seqlock_irqsave(&dev->iowait_lock, flags); 465 if (!list_empty(list)) { 466 wait = list_first_entry(list, struct iowait, list); 467 qp = iowait_to_qp(wait); 468 priv = qp->priv; 469 list_del_init(&priv->s_iowait.list); 470 priv->s_iowait.lock = NULL; 471 /* refcount held until actual wake up */ 472 if (!list_empty(list)) 473 mod_timer(&dev->mem_timer, jiffies + 1); 474 } 475 write_sequnlock_irqrestore(&dev->iowait_lock, flags); 476 477 if (qp) 478 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM); 479 } 480 481 /* 482 * This is called with progress side lock held. 483 */ 484 /* New API */ 485 static void verbs_sdma_complete( 486 struct sdma_txreq *cookie, 487 int status) 488 { 489 struct verbs_txreq *tx = 490 container_of(cookie, struct verbs_txreq, txreq); 491 struct rvt_qp *qp = tx->qp; 492 493 spin_lock(&qp->s_lock); 494 if (tx->wqe) { 495 rvt_send_complete(qp, tx->wqe, IB_WC_SUCCESS); 496 } else if (qp->ibqp.qp_type == IB_QPT_RC) { 497 struct hfi1_opa_header *hdr; 498 499 hdr = &tx->phdr.hdr; 500 hfi1_rc_send_complete(qp, hdr); 501 } 502 spin_unlock(&qp->s_lock); 503 504 hfi1_put_txreq(tx); 505 } 506 507 static int wait_kmem(struct hfi1_ibdev *dev, 508 struct rvt_qp *qp, 509 struct hfi1_pkt_state *ps) 510 { 511 struct hfi1_qp_priv *priv = qp->priv; 512 unsigned long flags; 513 int ret = 0; 514 515 spin_lock_irqsave(&qp->s_lock, flags); 516 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { 517 write_seqlock(&dev->iowait_lock); 518 list_add_tail(&ps->s_txreq->txreq.list, 519 &ps->wait->tx_head); 520 if (list_empty(&priv->s_iowait.list)) { 521 if (list_empty(&dev->memwait)) 522 mod_timer(&dev->mem_timer, jiffies + 1); 523 qp->s_flags |= RVT_S_WAIT_KMEM; 524 list_add_tail(&priv->s_iowait.list, &dev->memwait); 525 priv->s_iowait.lock = &dev->iowait_lock; 526 trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM); 527 rvt_get_qp(qp); 528 } 529 write_sequnlock(&dev->iowait_lock); 530 hfi1_qp_unbusy(qp, ps->wait); 531 ret = -EBUSY; 532 } 533 spin_unlock_irqrestore(&qp->s_lock, flags); 534 535 return ret; 536 } 537 538 /* 539 * This routine calls txadds for each sg entry. 540 * 541 * Add failures will revert the sge cursor 542 */ 543 static noinline int build_verbs_ulp_payload( 544 struct sdma_engine *sde, 545 u32 length, 546 struct verbs_txreq *tx) 547 { 548 struct rvt_sge_state *ss = tx->ss; 549 struct rvt_sge *sg_list = ss->sg_list; 550 struct rvt_sge sge = ss->sge; 551 u8 num_sge = ss->num_sge; 552 u32 len; 553 int ret = 0; 554 555 while (length) { 556 len = ss->sge.length; 557 if (len > length) 558 len = length; 559 if (len > ss->sge.sge_length) 560 len = ss->sge.sge_length; 561 WARN_ON_ONCE(len == 0); 562 ret = sdma_txadd_kvaddr( 563 sde->dd, 564 &tx->txreq, 565 ss->sge.vaddr, 566 len); 567 if (ret) 568 goto bail_txadd; 569 rvt_update_sge(ss, len, false); 570 length -= len; 571 } 572 return ret; 573 bail_txadd: 574 /* unwind cursor */ 575 ss->sge = sge; 576 ss->num_sge = num_sge; 577 ss->sg_list = sg_list; 578 return ret; 579 } 580 581 /** 582 * update_tx_opstats - record stats by opcode 583 * @qp; the qp 584 * @ps: transmit packet state 585 * @plen: the plen in dwords 586 * 587 * This is a routine to record the tx opstats after a 588 * packet has been presented to the egress mechanism. 589 */ 590 static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 591 u32 plen) 592 { 593 #ifdef CONFIG_DEBUG_FS 594 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 595 struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats); 596 597 inc_opstats(plen * 4, &s->stats[ps->opcode]); 598 put_cpu_ptr(s); 599 #endif 600 } 601 602 /* 603 * Build the number of DMA descriptors needed to send length bytes of data. 604 * 605 * NOTE: DMA mapping is held in the tx until completed in the ring or 606 * the tx desc is freed without having been submitted to the ring 607 * 608 * This routine ensures all the helper routine calls succeed. 609 */ 610 /* New API */ 611 static int build_verbs_tx_desc( 612 struct sdma_engine *sde, 613 u32 length, 614 struct verbs_txreq *tx, 615 struct hfi1_ahg_info *ahg_info, 616 u64 pbc) 617 { 618 int ret = 0; 619 struct hfi1_sdma_header *phdr = &tx->phdr; 620 u16 hdrbytes = (tx->hdr_dwords + sizeof(pbc) / 4) << 2; 621 u8 extra_bytes = 0; 622 623 if (tx->phdr.hdr.hdr_type) { 624 /* 625 * hdrbytes accounts for PBC. Need to subtract 8 bytes 626 * before calculating padding. 627 */ 628 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) + 629 (SIZE_OF_CRC << 2) + SIZE_OF_LT; 630 } 631 if (!ahg_info->ahgcount) { 632 ret = sdma_txinit_ahg( 633 &tx->txreq, 634 ahg_info->tx_flags, 635 hdrbytes + length + 636 extra_bytes, 637 ahg_info->ahgidx, 638 0, 639 NULL, 640 0, 641 verbs_sdma_complete); 642 if (ret) 643 goto bail_txadd; 644 phdr->pbc = cpu_to_le64(pbc); 645 ret = sdma_txadd_kvaddr( 646 sde->dd, 647 &tx->txreq, 648 phdr, 649 hdrbytes); 650 if (ret) 651 goto bail_txadd; 652 } else { 653 ret = sdma_txinit_ahg( 654 &tx->txreq, 655 ahg_info->tx_flags, 656 length, 657 ahg_info->ahgidx, 658 ahg_info->ahgcount, 659 ahg_info->ahgdesc, 660 hdrbytes, 661 verbs_sdma_complete); 662 if (ret) 663 goto bail_txadd; 664 } 665 /* add the ulp payload - if any. tx->ss can be NULL for acks */ 666 if (tx->ss) { 667 ret = build_verbs_ulp_payload(sde, length, tx); 668 if (ret) 669 goto bail_txadd; 670 } 671 672 /* add icrc, lt byte, and padding to flit */ 673 if (extra_bytes) 674 ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq, 675 (void *)trail_buf, extra_bytes); 676 677 bail_txadd: 678 return ret; 679 } 680 681 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 682 u64 pbc) 683 { 684 struct hfi1_qp_priv *priv = qp->priv; 685 struct hfi1_ahg_info *ahg_info = priv->s_ahg; 686 u32 hdrwords = ps->s_txreq->hdr_dwords; 687 u32 len = ps->s_txreq->s_cur_size; 688 u32 plen; 689 struct hfi1_ibdev *dev = ps->dev; 690 struct hfi1_pportdata *ppd = ps->ppd; 691 struct verbs_txreq *tx; 692 u8 sc5 = priv->s_sc; 693 int ret; 694 u32 dwords; 695 696 if (ps->s_txreq->phdr.hdr.hdr_type) { 697 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len); 698 699 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) + 700 SIZE_OF_LT) >> 2; 701 } else { 702 dwords = (len + 3) >> 2; 703 } 704 plen = hdrwords + dwords + sizeof(pbc) / 4; 705 706 tx = ps->s_txreq; 707 if (!sdma_txreq_built(&tx->txreq)) { 708 if (likely(pbc == 0)) { 709 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5); 710 711 /* No vl15 here */ 712 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */ 713 if (ps->s_txreq->phdr.hdr.hdr_type) 714 pbc |= PBC_PACKET_BYPASS | 715 PBC_INSERT_BYPASS_ICRC; 716 else 717 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT); 718 719 if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode))) 720 pbc = hfi1_fault_tx(qp, ps->opcode, pbc); 721 pbc = create_pbc(ppd, 722 pbc, 723 qp->srate_mbps, 724 vl, 725 plen); 726 } 727 tx->wqe = qp->s_wqe; 728 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc); 729 if (unlikely(ret)) 730 goto bail_build; 731 } 732 ret = sdma_send_txreq(tx->sde, ps->wait, &tx->txreq, ps->pkts_sent); 733 if (unlikely(ret < 0)) { 734 if (ret == -ECOMM) 735 goto bail_ecomm; 736 return ret; 737 } 738 739 update_tx_opstats(qp, ps, plen); 740 trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device), 741 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5)); 742 return ret; 743 744 bail_ecomm: 745 /* The current one got "sent" */ 746 return 0; 747 bail_build: 748 ret = wait_kmem(dev, qp, ps); 749 if (!ret) { 750 /* free txreq - bad state */ 751 hfi1_put_txreq(ps->s_txreq); 752 ps->s_txreq = NULL; 753 } 754 return ret; 755 } 756 757 /* 758 * If we are now in the error state, return zero to flush the 759 * send work request. 760 */ 761 static int pio_wait(struct rvt_qp *qp, 762 struct send_context *sc, 763 struct hfi1_pkt_state *ps, 764 u32 flag) 765 { 766 struct hfi1_qp_priv *priv = qp->priv; 767 struct hfi1_devdata *dd = sc->dd; 768 unsigned long flags; 769 int ret = 0; 770 771 /* 772 * Note that as soon as want_buffer() is called and 773 * possibly before it returns, sc_piobufavail() 774 * could be called. Therefore, put QP on the I/O wait list before 775 * enabling the PIO avail interrupt. 776 */ 777 spin_lock_irqsave(&qp->s_lock, flags); 778 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { 779 write_seqlock(&sc->waitlock); 780 list_add_tail(&ps->s_txreq->txreq.list, 781 &ps->wait->tx_head); 782 if (list_empty(&priv->s_iowait.list)) { 783 struct hfi1_ibdev *dev = &dd->verbs_dev; 784 int was_empty; 785 786 dev->n_piowait += !!(flag & RVT_S_WAIT_PIO); 787 dev->n_piodrain += !!(flag & HFI1_S_WAIT_PIO_DRAIN); 788 qp->s_flags |= flag; 789 was_empty = list_empty(&sc->piowait); 790 iowait_queue(ps->pkts_sent, &priv->s_iowait, 791 &sc->piowait); 792 priv->s_iowait.lock = &sc->waitlock; 793 trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO); 794 rvt_get_qp(qp); 795 /* counting: only call wantpiobuf_intr if first user */ 796 if (was_empty) 797 hfi1_sc_wantpiobuf_intr(sc, 1); 798 } 799 write_sequnlock(&sc->waitlock); 800 hfi1_qp_unbusy(qp, ps->wait); 801 ret = -EBUSY; 802 } 803 spin_unlock_irqrestore(&qp->s_lock, flags); 804 return ret; 805 } 806 807 static void verbs_pio_complete(void *arg, int code) 808 { 809 struct rvt_qp *qp = (struct rvt_qp *)arg; 810 struct hfi1_qp_priv *priv = qp->priv; 811 812 if (iowait_pio_dec(&priv->s_iowait)) 813 iowait_drain_wakeup(&priv->s_iowait); 814 } 815 816 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 817 u64 pbc) 818 { 819 struct hfi1_qp_priv *priv = qp->priv; 820 u32 hdrwords = ps->s_txreq->hdr_dwords; 821 struct rvt_sge_state *ss = ps->s_txreq->ss; 822 u32 len = ps->s_txreq->s_cur_size; 823 u32 dwords; 824 u32 plen; 825 struct hfi1_pportdata *ppd = ps->ppd; 826 u32 *hdr; 827 u8 sc5; 828 unsigned long flags = 0; 829 struct send_context *sc; 830 struct pio_buf *pbuf; 831 int wc_status = IB_WC_SUCCESS; 832 int ret = 0; 833 pio_release_cb cb = NULL; 834 u8 extra_bytes = 0; 835 836 if (ps->s_txreq->phdr.hdr.hdr_type) { 837 u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len); 838 839 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT; 840 dwords = (len + extra_bytes) >> 2; 841 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah; 842 } else { 843 dwords = (len + 3) >> 2; 844 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh; 845 } 846 plen = hdrwords + dwords + sizeof(pbc) / 4; 847 848 /* only RC/UC use complete */ 849 switch (qp->ibqp.qp_type) { 850 case IB_QPT_RC: 851 case IB_QPT_UC: 852 cb = verbs_pio_complete; 853 break; 854 default: 855 break; 856 } 857 858 /* vl15 special case taken care of in ud.c */ 859 sc5 = priv->s_sc; 860 sc = ps->s_txreq->psc; 861 862 if (likely(pbc == 0)) { 863 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5); 864 865 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */ 866 if (ps->s_txreq->phdr.hdr.hdr_type) 867 pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC; 868 else 869 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT); 870 871 if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode))) 872 pbc = hfi1_fault_tx(qp, ps->opcode, pbc); 873 pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen); 874 } 875 if (cb) 876 iowait_pio_inc(&priv->s_iowait); 877 pbuf = sc_buffer_alloc(sc, plen, cb, qp); 878 if (unlikely(!pbuf)) { 879 if (cb) 880 verbs_pio_complete(qp, 0); 881 if (ppd->host_link_state != HLS_UP_ACTIVE) { 882 /* 883 * If we have filled the PIO buffers to capacity and are 884 * not in an active state this request is not going to 885 * go out to so just complete it with an error or else a 886 * ULP or the core may be stuck waiting. 887 */ 888 hfi1_cdbg( 889 PIO, 890 "alloc failed. state not active, completing"); 891 wc_status = IB_WC_GENERAL_ERR; 892 goto pio_bail; 893 } else { 894 /* 895 * This is a normal occurrence. The PIO buffs are full 896 * up but we are still happily sending, well we could be 897 * so lets continue to queue the request. 898 */ 899 hfi1_cdbg(PIO, "alloc failed. state active, queuing"); 900 ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO); 901 if (!ret) 902 /* txreq not queued - free */ 903 goto bail; 904 /* tx consumed in wait */ 905 return ret; 906 } 907 } 908 909 if (dwords == 0) { 910 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords); 911 } else { 912 seg_pio_copy_start(pbuf, pbc, 913 hdr, hdrwords * 4); 914 if (ss) { 915 while (len) { 916 void *addr = ss->sge.vaddr; 917 u32 slen = ss->sge.length; 918 919 if (slen > len) 920 slen = len; 921 if (slen > ss->sge.sge_length) 922 slen = ss->sge.sge_length; 923 rvt_update_sge(ss, slen, false); 924 seg_pio_copy_mid(pbuf, addr, slen); 925 len -= slen; 926 } 927 } 928 /* add icrc, lt byte, and padding to flit */ 929 if (extra_bytes) 930 seg_pio_copy_mid(pbuf, trail_buf, extra_bytes); 931 932 seg_pio_copy_end(pbuf); 933 } 934 935 update_tx_opstats(qp, ps, plen); 936 trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device), 937 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5)); 938 939 pio_bail: 940 if (qp->s_wqe) { 941 spin_lock_irqsave(&qp->s_lock, flags); 942 rvt_send_complete(qp, qp->s_wqe, wc_status); 943 spin_unlock_irqrestore(&qp->s_lock, flags); 944 } else if (qp->ibqp.qp_type == IB_QPT_RC) { 945 spin_lock_irqsave(&qp->s_lock, flags); 946 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr); 947 spin_unlock_irqrestore(&qp->s_lock, flags); 948 } 949 950 ret = 0; 951 952 bail: 953 hfi1_put_txreq(ps->s_txreq); 954 return ret; 955 } 956 957 /* 958 * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent 959 * being an entry from the partition key table), return 0 960 * otherwise. Use the matching criteria for egress partition keys 961 * specified in the OPAv1 spec., section 9.1l.7. 962 */ 963 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent) 964 { 965 u16 mkey = pkey & PKEY_LOW_15_MASK; 966 u16 mentry = ent & PKEY_LOW_15_MASK; 967 968 if (mkey == mentry) { 969 /* 970 * If pkey[15] is set (full partition member), 971 * is bit 15 in the corresponding table element 972 * clear (limited member)? 973 */ 974 if (pkey & PKEY_MEMBER_MASK) 975 return !!(ent & PKEY_MEMBER_MASK); 976 return 1; 977 } 978 return 0; 979 } 980 981 /** 982 * egress_pkey_check - check P_KEY of a packet 983 * @ppd: Physical IB port data 984 * @slid: SLID for packet 985 * @bkey: PKEY for header 986 * @sc5: SC for packet 987 * @s_pkey_index: It will be used for look up optimization for kernel contexts 988 * only. If it is negative value, then it means user contexts is calling this 989 * function. 990 * 991 * It checks if hdr's pkey is valid. 992 * 993 * Return: 0 on success, otherwise, 1 994 */ 995 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey, 996 u8 sc5, int8_t s_pkey_index) 997 { 998 struct hfi1_devdata *dd; 999 int i; 1000 int is_user_ctxt_mechanism = (s_pkey_index < 0); 1001 1002 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT)) 1003 return 0; 1004 1005 /* If SC15, pkey[0:14] must be 0x7fff */ 1006 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1007 goto bad; 1008 1009 /* Is the pkey = 0x0, or 0x8000? */ 1010 if ((pkey & PKEY_LOW_15_MASK) == 0) 1011 goto bad; 1012 1013 /* 1014 * For the kernel contexts only, if a qp is passed into the function, 1015 * the most likely matching pkey has index qp->s_pkey_index 1016 */ 1017 if (!is_user_ctxt_mechanism && 1018 egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) { 1019 return 0; 1020 } 1021 1022 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1023 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1024 return 0; 1025 } 1026 bad: 1027 /* 1028 * For the user-context mechanism, the P_KEY check would only happen 1029 * once per SDMA request, not once per packet. Therefore, there's no 1030 * need to increment the counter for the user-context mechanism. 1031 */ 1032 if (!is_user_ctxt_mechanism) { 1033 incr_cntr64(&ppd->port_xmit_constraint_errors); 1034 dd = ppd->dd; 1035 if (!(dd->err_info_xmit_constraint.status & 1036 OPA_EI_STATUS_SMASK)) { 1037 dd->err_info_xmit_constraint.status |= 1038 OPA_EI_STATUS_SMASK; 1039 dd->err_info_xmit_constraint.slid = slid; 1040 dd->err_info_xmit_constraint.pkey = pkey; 1041 } 1042 } 1043 return 1; 1044 } 1045 1046 /** 1047 * get_send_routine - choose an egress routine 1048 * 1049 * Choose an egress routine based on QP type 1050 * and size 1051 */ 1052 static inline send_routine get_send_routine(struct rvt_qp *qp, 1053 struct hfi1_pkt_state *ps) 1054 { 1055 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 1056 struct hfi1_qp_priv *priv = qp->priv; 1057 struct verbs_txreq *tx = ps->s_txreq; 1058 1059 if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA))) 1060 return dd->process_pio_send; 1061 switch (qp->ibqp.qp_type) { 1062 case IB_QPT_SMI: 1063 return dd->process_pio_send; 1064 case IB_QPT_GSI: 1065 case IB_QPT_UD: 1066 break; 1067 case IB_QPT_UC: 1068 case IB_QPT_RC: { 1069 if (piothreshold && 1070 tx->s_cur_size <= min(piothreshold, qp->pmtu) && 1071 (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) && 1072 iowait_sdma_pending(&priv->s_iowait) == 0 && 1073 !sdma_txreq_built(&tx->txreq)) 1074 return dd->process_pio_send; 1075 break; 1076 } 1077 default: 1078 break; 1079 } 1080 return dd->process_dma_send; 1081 } 1082 1083 /** 1084 * hfi1_verbs_send - send a packet 1085 * @qp: the QP to send on 1086 * @ps: the state of the packet to send 1087 * 1088 * Return zero if packet is sent or queued OK. 1089 * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise. 1090 */ 1091 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps) 1092 { 1093 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 1094 struct hfi1_qp_priv *priv = qp->priv; 1095 struct ib_other_headers *ohdr = NULL; 1096 send_routine sr; 1097 int ret; 1098 u16 pkey; 1099 u32 slid; 1100 u8 l4 = 0; 1101 1102 /* locate the pkey within the headers */ 1103 if (ps->s_txreq->phdr.hdr.hdr_type) { 1104 struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah; 1105 1106 l4 = hfi1_16B_get_l4(hdr); 1107 if (l4 == OPA_16B_L4_IB_LOCAL) 1108 ohdr = &hdr->u.oth; 1109 else if (l4 == OPA_16B_L4_IB_GLOBAL) 1110 ohdr = &hdr->u.l.oth; 1111 1112 slid = hfi1_16B_get_slid(hdr); 1113 pkey = hfi1_16B_get_pkey(hdr); 1114 } else { 1115 struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh; 1116 u8 lnh = ib_get_lnh(hdr); 1117 1118 if (lnh == HFI1_LRH_GRH) 1119 ohdr = &hdr->u.l.oth; 1120 else 1121 ohdr = &hdr->u.oth; 1122 slid = ib_get_slid(hdr); 1123 pkey = ib_bth_get_pkey(ohdr); 1124 } 1125 1126 if (likely(l4 != OPA_16B_L4_FM)) 1127 ps->opcode = ib_bth_get_opcode(ohdr); 1128 else 1129 ps->opcode = IB_OPCODE_UD_SEND_ONLY; 1130 1131 sr = get_send_routine(qp, ps); 1132 ret = egress_pkey_check(dd->pport, slid, pkey, 1133 priv->s_sc, qp->s_pkey_index); 1134 if (unlikely(ret)) { 1135 /* 1136 * The value we are returning here does not get propagated to 1137 * the verbs caller. Thus we need to complete the request with 1138 * error otherwise the caller could be sitting waiting on the 1139 * completion event. Only do this for PIO. SDMA has its own 1140 * mechanism for handling the errors. So for SDMA we can just 1141 * return. 1142 */ 1143 if (sr == dd->process_pio_send) { 1144 unsigned long flags; 1145 1146 hfi1_cdbg(PIO, "%s() Failed. Completing with err", 1147 __func__); 1148 spin_lock_irqsave(&qp->s_lock, flags); 1149 rvt_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR); 1150 spin_unlock_irqrestore(&qp->s_lock, flags); 1151 } 1152 return -EINVAL; 1153 } 1154 if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait)) 1155 return pio_wait(qp, 1156 ps->s_txreq->psc, 1157 ps, 1158 HFI1_S_WAIT_PIO_DRAIN); 1159 return sr(qp, ps, 0); 1160 } 1161 1162 /** 1163 * hfi1_fill_device_attr - Fill in rvt dev info device attributes. 1164 * @dd: the device data structure 1165 */ 1166 static void hfi1_fill_device_attr(struct hfi1_devdata *dd) 1167 { 1168 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi; 1169 u32 ver = dd->dc8051_ver; 1170 1171 memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props)); 1172 1173 rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) | 1174 ((u64)(dc8051_ver_min(ver)) << 16) | 1175 (u64)dc8051_ver_patch(ver); 1176 1177 rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR | 1178 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT | 1179 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN | 1180 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE | 1181 IB_DEVICE_MEM_MGT_EXTENSIONS | 1182 IB_DEVICE_RDMA_NETDEV_OPA_VNIC; 1183 rdi->dparms.props.page_size_cap = PAGE_SIZE; 1184 rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3; 1185 rdi->dparms.props.vendor_part_id = dd->pcidev->device; 1186 rdi->dparms.props.hw_ver = dd->minrev; 1187 rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid; 1188 rdi->dparms.props.max_mr_size = U64_MAX; 1189 rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX; 1190 rdi->dparms.props.max_qp = hfi1_max_qps; 1191 rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs; 1192 rdi->dparms.props.max_send_sge = hfi1_max_sges; 1193 rdi->dparms.props.max_recv_sge = hfi1_max_sges; 1194 rdi->dparms.props.max_sge_rd = hfi1_max_sges; 1195 rdi->dparms.props.max_cq = hfi1_max_cqs; 1196 rdi->dparms.props.max_ah = hfi1_max_ahs; 1197 rdi->dparms.props.max_cqe = hfi1_max_cqes; 1198 rdi->dparms.props.max_mr = rdi->lkey_table.max; 1199 rdi->dparms.props.max_fmr = rdi->lkey_table.max; 1200 rdi->dparms.props.max_map_per_fmr = 32767; 1201 rdi->dparms.props.max_pd = hfi1_max_pds; 1202 rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC; 1203 rdi->dparms.props.max_qp_init_rd_atom = 255; 1204 rdi->dparms.props.max_srq = hfi1_max_srqs; 1205 rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs; 1206 rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges; 1207 rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB; 1208 rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd); 1209 rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps; 1210 rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached; 1211 rdi->dparms.props.max_total_mcast_qp_attach = 1212 rdi->dparms.props.max_mcast_qp_attach * 1213 rdi->dparms.props.max_mcast_grp; 1214 } 1215 1216 static inline u16 opa_speed_to_ib(u16 in) 1217 { 1218 u16 out = 0; 1219 1220 if (in & OPA_LINK_SPEED_25G) 1221 out |= IB_SPEED_EDR; 1222 if (in & OPA_LINK_SPEED_12_5G) 1223 out |= IB_SPEED_FDR; 1224 1225 return out; 1226 } 1227 1228 /* 1229 * Convert a single OPA link width (no multiple flags) to an IB value. 1230 * A zero OPA link width means link down, which means the IB width value 1231 * is a don't care. 1232 */ 1233 static inline u16 opa_width_to_ib(u16 in) 1234 { 1235 switch (in) { 1236 case OPA_LINK_WIDTH_1X: 1237 /* map 2x and 3x to 1x as they don't exist in IB */ 1238 case OPA_LINK_WIDTH_2X: 1239 case OPA_LINK_WIDTH_3X: 1240 return IB_WIDTH_1X; 1241 default: /* link down or unknown, return our largest width */ 1242 case OPA_LINK_WIDTH_4X: 1243 return IB_WIDTH_4X; 1244 } 1245 } 1246 1247 static int query_port(struct rvt_dev_info *rdi, u8 port_num, 1248 struct ib_port_attr *props) 1249 { 1250 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi); 1251 struct hfi1_devdata *dd = dd_from_dev(verbs_dev); 1252 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1]; 1253 u32 lid = ppd->lid; 1254 1255 /* props being zeroed by the caller, avoid zeroing it here */ 1256 props->lid = lid ? lid : 0; 1257 props->lmc = ppd->lmc; 1258 /* OPA logical states match IB logical states */ 1259 props->state = driver_lstate(ppd); 1260 props->phys_state = driver_pstate(ppd); 1261 props->gid_tbl_len = HFI1_GUIDS_PER_PORT; 1262 props->active_width = (u8)opa_width_to_ib(ppd->link_width_active); 1263 /* see rate_show() in ib core/sysfs.c */ 1264 props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active); 1265 props->max_vl_num = ppd->vls_supported; 1266 1267 /* Once we are a "first class" citizen and have added the OPA MTUs to 1268 * the core we can advertise the larger MTU enum to the ULPs, for now 1269 * advertise only 4K. 1270 * 1271 * Those applications which are either OPA aware or pass the MTU enum 1272 * from the Path Records to us will get the new 8k MTU. Those that 1273 * attempt to process the MTU enum may fail in various ways. 1274 */ 1275 props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ? 1276 4096 : hfi1_max_mtu), IB_MTU_4096); 1277 props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu : 1278 mtu_to_enum(ppd->ibmtu, IB_MTU_4096); 1279 1280 return 0; 1281 } 1282 1283 static int modify_device(struct ib_device *device, 1284 int device_modify_mask, 1285 struct ib_device_modify *device_modify) 1286 { 1287 struct hfi1_devdata *dd = dd_from_ibdev(device); 1288 unsigned i; 1289 int ret; 1290 1291 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID | 1292 IB_DEVICE_MODIFY_NODE_DESC)) { 1293 ret = -EOPNOTSUPP; 1294 goto bail; 1295 } 1296 1297 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) { 1298 memcpy(device->node_desc, device_modify->node_desc, 1299 IB_DEVICE_NODE_DESC_MAX); 1300 for (i = 0; i < dd->num_pports; i++) { 1301 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data; 1302 1303 hfi1_node_desc_chg(ibp); 1304 } 1305 } 1306 1307 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) { 1308 ib_hfi1_sys_image_guid = 1309 cpu_to_be64(device_modify->sys_image_guid); 1310 for (i = 0; i < dd->num_pports; i++) { 1311 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data; 1312 1313 hfi1_sys_guid_chg(ibp); 1314 } 1315 } 1316 1317 ret = 0; 1318 1319 bail: 1320 return ret; 1321 } 1322 1323 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num) 1324 { 1325 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi); 1326 struct hfi1_devdata *dd = dd_from_dev(verbs_dev); 1327 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1]; 1328 int ret; 1329 1330 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0, 1331 OPA_LINKDOWN_REASON_UNKNOWN); 1332 ret = set_link_state(ppd, HLS_DN_DOWNDEF); 1333 return ret; 1334 } 1335 1336 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp, 1337 int guid_index, __be64 *guid) 1338 { 1339 struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp); 1340 1341 if (guid_index >= HFI1_GUIDS_PER_PORT) 1342 return -EINVAL; 1343 1344 *guid = get_sguid(ibp, guid_index); 1345 return 0; 1346 } 1347 1348 /* 1349 * convert ah port,sl to sc 1350 */ 1351 u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah) 1352 { 1353 struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah)); 1354 1355 return ibp->sl_to_sc[rdma_ah_get_sl(ah)]; 1356 } 1357 1358 static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr) 1359 { 1360 struct hfi1_ibport *ibp; 1361 struct hfi1_pportdata *ppd; 1362 struct hfi1_devdata *dd; 1363 u8 sc5; 1364 u8 sl; 1365 1366 if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) && 1367 !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) 1368 return -EINVAL; 1369 1370 /* test the mapping for validity */ 1371 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr)); 1372 ppd = ppd_from_ibp(ibp); 1373 dd = dd_from_ppd(ppd); 1374 1375 sl = rdma_ah_get_sl(ah_attr); 1376 if (sl >= ARRAY_SIZE(ibp->sl_to_sc)) 1377 return -EINVAL; 1378 1379 sc5 = ibp->sl_to_sc[sl]; 1380 if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf) 1381 return -EINVAL; 1382 return 0; 1383 } 1384 1385 static void hfi1_notify_new_ah(struct ib_device *ibdev, 1386 struct rdma_ah_attr *ah_attr, 1387 struct rvt_ah *ah) 1388 { 1389 struct hfi1_ibport *ibp; 1390 struct hfi1_pportdata *ppd; 1391 struct hfi1_devdata *dd; 1392 u8 sc5; 1393 struct rdma_ah_attr *attr = &ah->attr; 1394 1395 /* 1396 * Do not trust reading anything from rvt_ah at this point as it is not 1397 * done being setup. We can however modify things which we need to set. 1398 */ 1399 1400 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr)); 1401 ppd = ppd_from_ibp(ibp); 1402 sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)]; 1403 hfi1_update_ah_attr(ibdev, attr); 1404 hfi1_make_opa_lid(attr); 1405 dd = dd_from_ppd(ppd); 1406 ah->vl = sc_to_vlt(dd, sc5); 1407 if (ah->vl < num_vls || ah->vl == 15) 1408 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu); 1409 } 1410 1411 /** 1412 * hfi1_get_npkeys - return the size of the PKEY table for context 0 1413 * @dd: the hfi1_ib device 1414 */ 1415 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd) 1416 { 1417 return ARRAY_SIZE(dd->pport[0].pkeys); 1418 } 1419 1420 static void init_ibport(struct hfi1_pportdata *ppd) 1421 { 1422 struct hfi1_ibport *ibp = &ppd->ibport_data; 1423 size_t sz = ARRAY_SIZE(ibp->sl_to_sc); 1424 int i; 1425 1426 for (i = 0; i < sz; i++) { 1427 ibp->sl_to_sc[i] = i; 1428 ibp->sc_to_sl[i] = i; 1429 } 1430 1431 for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++) 1432 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list); 1433 timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0); 1434 1435 spin_lock_init(&ibp->rvp.lock); 1436 /* Set the prefix to the default value (see ch. 4.1.1) */ 1437 ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX; 1438 ibp->rvp.sm_lid = 0; 1439 /* 1440 * Below should only set bits defined in OPA PortInfo.CapabilityMask 1441 * and PortInfo.CapabilityMask3 1442 */ 1443 ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP | 1444 IB_PORT_CAP_MASK_NOTICE_SUP; 1445 ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported; 1446 ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA; 1447 ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA; 1448 ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS; 1449 ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS; 1450 ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT; 1451 1452 RCU_INIT_POINTER(ibp->rvp.qp[0], NULL); 1453 RCU_INIT_POINTER(ibp->rvp.qp[1], NULL); 1454 } 1455 1456 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str) 1457 { 1458 struct rvt_dev_info *rdi = ib_to_rvt(ibdev); 1459 struct hfi1_ibdev *dev = dev_from_rdi(rdi); 1460 u32 ver = dd_from_dev(dev)->dc8051_ver; 1461 1462 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver), 1463 dc8051_ver_min(ver), dc8051_ver_patch(ver)); 1464 } 1465 1466 static const char * const driver_cntr_names[] = { 1467 /* must be element 0*/ 1468 "DRIVER_KernIntr", 1469 "DRIVER_ErrorIntr", 1470 "DRIVER_Tx_Errs", 1471 "DRIVER_Rcv_Errs", 1472 "DRIVER_HW_Errs", 1473 "DRIVER_NoPIOBufs", 1474 "DRIVER_CtxtsOpen", 1475 "DRIVER_RcvLen_Errs", 1476 "DRIVER_EgrBufFull", 1477 "DRIVER_EgrHdrFull" 1478 }; 1479 1480 static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */ 1481 static const char **dev_cntr_names; 1482 static const char **port_cntr_names; 1483 int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names); 1484 static int num_dev_cntrs; 1485 static int num_port_cntrs; 1486 static int cntr_names_initialized; 1487 1488 /* 1489 * Convert a list of names separated by '\n' into an array of NULL terminated 1490 * strings. Optionally some entries can be reserved in the array to hold extra 1491 * external strings. 1492 */ 1493 static int init_cntr_names(const char *names_in, 1494 const size_t names_len, 1495 int num_extra_names, 1496 int *num_cntrs, 1497 const char ***cntr_names) 1498 { 1499 char *names_out, *p, **q; 1500 int i, n; 1501 1502 n = 0; 1503 for (i = 0; i < names_len; i++) 1504 if (names_in[i] == '\n') 1505 n++; 1506 1507 names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len, 1508 GFP_KERNEL); 1509 if (!names_out) { 1510 *num_cntrs = 0; 1511 *cntr_names = NULL; 1512 return -ENOMEM; 1513 } 1514 1515 p = names_out + (n + num_extra_names) * sizeof(char *); 1516 memcpy(p, names_in, names_len); 1517 1518 q = (char **)names_out; 1519 for (i = 0; i < n; i++) { 1520 q[i] = p; 1521 p = strchr(p, '\n'); 1522 *p++ = '\0'; 1523 } 1524 1525 *num_cntrs = n; 1526 *cntr_names = (const char **)names_out; 1527 return 0; 1528 } 1529 1530 static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev, 1531 u8 port_num) 1532 { 1533 int i, err; 1534 1535 mutex_lock(&cntr_names_lock); 1536 if (!cntr_names_initialized) { 1537 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1538 1539 err = init_cntr_names(dd->cntrnames, 1540 dd->cntrnameslen, 1541 num_driver_cntrs, 1542 &num_dev_cntrs, 1543 &dev_cntr_names); 1544 if (err) { 1545 mutex_unlock(&cntr_names_lock); 1546 return NULL; 1547 } 1548 1549 for (i = 0; i < num_driver_cntrs; i++) 1550 dev_cntr_names[num_dev_cntrs + i] = 1551 driver_cntr_names[i]; 1552 1553 err = init_cntr_names(dd->portcntrnames, 1554 dd->portcntrnameslen, 1555 0, 1556 &num_port_cntrs, 1557 &port_cntr_names); 1558 if (err) { 1559 kfree(dev_cntr_names); 1560 dev_cntr_names = NULL; 1561 mutex_unlock(&cntr_names_lock); 1562 return NULL; 1563 } 1564 cntr_names_initialized = 1; 1565 } 1566 mutex_unlock(&cntr_names_lock); 1567 1568 if (!port_num) 1569 return rdma_alloc_hw_stats_struct( 1570 dev_cntr_names, 1571 num_dev_cntrs + num_driver_cntrs, 1572 RDMA_HW_STATS_DEFAULT_LIFESPAN); 1573 else 1574 return rdma_alloc_hw_stats_struct( 1575 port_cntr_names, 1576 num_port_cntrs, 1577 RDMA_HW_STATS_DEFAULT_LIFESPAN); 1578 } 1579 1580 static u64 hfi1_sps_ints(void) 1581 { 1582 unsigned long flags; 1583 struct hfi1_devdata *dd; 1584 u64 sps_ints = 0; 1585 1586 spin_lock_irqsave(&hfi1_devs_lock, flags); 1587 list_for_each_entry(dd, &hfi1_dev_list, list) { 1588 sps_ints += get_all_cpu_total(dd->int_counter); 1589 } 1590 spin_unlock_irqrestore(&hfi1_devs_lock, flags); 1591 return sps_ints; 1592 } 1593 1594 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats, 1595 u8 port, int index) 1596 { 1597 u64 *values; 1598 int count; 1599 1600 if (!port) { 1601 u64 *stats = (u64 *)&hfi1_stats; 1602 int i; 1603 1604 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values); 1605 values[num_dev_cntrs] = hfi1_sps_ints(); 1606 for (i = 1; i < num_driver_cntrs; i++) 1607 values[num_dev_cntrs + i] = stats[i]; 1608 count = num_dev_cntrs + num_driver_cntrs; 1609 } else { 1610 struct hfi1_ibport *ibp = to_iport(ibdev, port); 1611 1612 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values); 1613 count = num_port_cntrs; 1614 } 1615 1616 memcpy(stats->value, values, count * sizeof(u64)); 1617 return count; 1618 } 1619 1620 static const struct ib_device_ops hfi1_dev_ops = { 1621 .alloc_hw_stats = alloc_hw_stats, 1622 .alloc_rdma_netdev = hfi1_vnic_alloc_rn, 1623 .get_dev_fw_str = hfi1_get_dev_fw_str, 1624 .get_hw_stats = get_hw_stats, 1625 .modify_device = modify_device, 1626 /* keep process mad in the driver */ 1627 .process_mad = hfi1_process_mad, 1628 }; 1629 1630 /** 1631 * hfi1_register_ib_device - register our device with the infiniband core 1632 * @dd: the device data structure 1633 * Return 0 if successful, errno if unsuccessful. 1634 */ 1635 int hfi1_register_ib_device(struct hfi1_devdata *dd) 1636 { 1637 struct hfi1_ibdev *dev = &dd->verbs_dev; 1638 struct ib_device *ibdev = &dev->rdi.ibdev; 1639 struct hfi1_pportdata *ppd = dd->pport; 1640 struct hfi1_ibport *ibp = &ppd->ibport_data; 1641 unsigned i; 1642 int ret; 1643 1644 for (i = 0; i < dd->num_pports; i++) 1645 init_ibport(ppd + i); 1646 1647 /* Only need to initialize non-zero fields. */ 1648 1649 timer_setup(&dev->mem_timer, mem_timer, 0); 1650 1651 seqlock_init(&dev->iowait_lock); 1652 seqlock_init(&dev->txwait_lock); 1653 INIT_LIST_HEAD(&dev->txwait); 1654 INIT_LIST_HEAD(&dev->memwait); 1655 1656 ret = verbs_txreq_init(dev); 1657 if (ret) 1658 goto err_verbs_txreq; 1659 1660 /* Use first-port GUID as node guid */ 1661 ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX); 1662 1663 /* 1664 * The system image GUID is supposed to be the same for all 1665 * HFIs in a single system but since there can be other 1666 * device types in the system, we can't be sure this is unique. 1667 */ 1668 if (!ib_hfi1_sys_image_guid) 1669 ib_hfi1_sys_image_guid = ibdev->node_guid; 1670 ibdev->owner = THIS_MODULE; 1671 ibdev->phys_port_cnt = dd->num_pports; 1672 ibdev->dev.parent = &dd->pcidev->dev; 1673 1674 ib_set_device_ops(ibdev, &hfi1_dev_ops); 1675 1676 strlcpy(ibdev->node_desc, init_utsname()->nodename, 1677 sizeof(ibdev->node_desc)); 1678 1679 /* 1680 * Fill in rvt info object. 1681 */ 1682 dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files; 1683 dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev; 1684 dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah; 1685 dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah; 1686 dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be; 1687 dd->verbs_dev.rdi.driver_f.query_port_state = query_port; 1688 dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port; 1689 dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg; 1690 /* 1691 * Fill in rvt info device attributes. 1692 */ 1693 hfi1_fill_device_attr(dd); 1694 1695 /* queue pair */ 1696 dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size; 1697 dd->verbs_dev.rdi.dparms.qpn_start = 0; 1698 dd->verbs_dev.rdi.dparms.qpn_inc = 1; 1699 dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift; 1700 dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16; 1701 dd->verbs_dev.rdi.dparms.qpn_res_end = 1702 dd->verbs_dev.rdi.dparms.qpn_res_start + 65535; 1703 dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC; 1704 dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK; 1705 dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT; 1706 dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK; 1707 dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA | 1708 RDMA_CORE_CAP_OPA_AH; 1709 dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE; 1710 1711 dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc; 1712 dd->verbs_dev.rdi.driver_f.qp_priv_init = hfi1_qp_priv_init; 1713 dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free; 1714 dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps; 1715 dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset; 1716 dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt; 1717 dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send; 1718 dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send; 1719 dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr; 1720 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp; 1721 dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters; 1722 dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue; 1723 dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp; 1724 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp; 1725 dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp; 1726 dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu; 1727 dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp; 1728 dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp; 1729 dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc; 1730 dd->verbs_dev.rdi.driver_f.setup_wqe = hfi1_setup_wqe; 1731 dd->verbs_dev.rdi.driver_f.comp_vect_cpu_lookup = 1732 hfi1_comp_vect_mappings_lookup; 1733 1734 /* completeion queue */ 1735 dd->verbs_dev.rdi.ibdev.num_comp_vectors = dd->comp_vect_possible_cpus; 1736 dd->verbs_dev.rdi.dparms.node = dd->node; 1737 1738 /* misc settings */ 1739 dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */ 1740 dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size; 1741 dd->verbs_dev.rdi.dparms.nports = dd->num_pports; 1742 dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd); 1743 dd->verbs_dev.rdi.dparms.sge_copy_mode = sge_copy_mode; 1744 dd->verbs_dev.rdi.dparms.wss_threshold = wss_threshold; 1745 dd->verbs_dev.rdi.dparms.wss_clean_period = wss_clean_period; 1746 1747 /* post send table */ 1748 dd->verbs_dev.rdi.post_parms = hfi1_post_parms; 1749 1750 /* opcode translation table */ 1751 dd->verbs_dev.rdi.wc_opcode = ib_hfi1_wc_opcode; 1752 1753 ppd = dd->pport; 1754 for (i = 0; i < dd->num_pports; i++, ppd++) 1755 rvt_init_port(&dd->verbs_dev.rdi, 1756 &ppd->ibport_data.rvp, 1757 i, 1758 ppd->pkeys); 1759 1760 rdma_set_device_sysfs_group(&dd->verbs_dev.rdi.ibdev, 1761 &ib_hfi1_attr_group); 1762 1763 ret = rvt_register_device(&dd->verbs_dev.rdi, RDMA_DRIVER_HFI1); 1764 if (ret) 1765 goto err_verbs_txreq; 1766 1767 ret = hfi1_verbs_register_sysfs(dd); 1768 if (ret) 1769 goto err_class; 1770 1771 return ret; 1772 1773 err_class: 1774 rvt_unregister_device(&dd->verbs_dev.rdi); 1775 err_verbs_txreq: 1776 verbs_txreq_exit(dev); 1777 dd_dev_err(dd, "cannot register verbs: %d!\n", -ret); 1778 return ret; 1779 } 1780 1781 void hfi1_unregister_ib_device(struct hfi1_devdata *dd) 1782 { 1783 struct hfi1_ibdev *dev = &dd->verbs_dev; 1784 1785 hfi1_verbs_unregister_sysfs(dd); 1786 1787 rvt_unregister_device(&dd->verbs_dev.rdi); 1788 1789 if (!list_empty(&dev->txwait)) 1790 dd_dev_err(dd, "txwait list not empty!\n"); 1791 if (!list_empty(&dev->memwait)) 1792 dd_dev_err(dd, "memwait list not empty!\n"); 1793 1794 del_timer_sync(&dev->mem_timer); 1795 verbs_txreq_exit(dev); 1796 1797 mutex_lock(&cntr_names_lock); 1798 kfree(dev_cntr_names); 1799 kfree(port_cntr_names); 1800 dev_cntr_names = NULL; 1801 port_cntr_names = NULL; 1802 cntr_names_initialized = 0; 1803 mutex_unlock(&cntr_names_lock); 1804 } 1805 1806 void hfi1_cnp_rcv(struct hfi1_packet *packet) 1807 { 1808 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd); 1809 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1810 struct ib_header *hdr = packet->hdr; 1811 struct rvt_qp *qp = packet->qp; 1812 u32 lqpn, rqpn = 0; 1813 u16 rlid = 0; 1814 u8 sl, sc5, svc_type; 1815 1816 switch (packet->qp->ibqp.qp_type) { 1817 case IB_QPT_UC: 1818 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr); 1819 rqpn = qp->remote_qpn; 1820 svc_type = IB_CC_SVCTYPE_UC; 1821 break; 1822 case IB_QPT_RC: 1823 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr); 1824 rqpn = qp->remote_qpn; 1825 svc_type = IB_CC_SVCTYPE_RC; 1826 break; 1827 case IB_QPT_SMI: 1828 case IB_QPT_GSI: 1829 case IB_QPT_UD: 1830 svc_type = IB_CC_SVCTYPE_UD; 1831 break; 1832 default: 1833 ibp->rvp.n_pkt_drops++; 1834 return; 1835 } 1836 1837 sc5 = hfi1_9B_get_sc5(hdr, packet->rhf); 1838 sl = ibp->sc_to_sl[sc5]; 1839 lqpn = qp->ibqp.qp_num; 1840 1841 process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type); 1842 } 1843