1145eba1aSCai Huoqing // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2f48ad614SDennis Dalessandro /*
384e3b19aSGary Leshner * Copyright(c) 2015 - 2020 Intel Corporation.
4f48ad614SDennis Dalessandro */
5f48ad614SDennis Dalessandro
6f48ad614SDennis Dalessandro #include <rdma/ib_mad.h>
7f48ad614SDennis Dalessandro #include <rdma/ib_user_verbs.h>
8f48ad614SDennis Dalessandro #include <linux/io.h>
9f48ad614SDennis Dalessandro #include <linux/module.h>
10f48ad614SDennis Dalessandro #include <linux/utsname.h>
11f48ad614SDennis Dalessandro #include <linux/rculist.h>
12f48ad614SDennis Dalessandro #include <linux/mm.h>
13f48ad614SDennis Dalessandro #include <linux/vmalloc.h>
1413c19222SDon Hiatt #include <rdma/opa_addr.h>
156497d0a9SGustavo A. R. Silva #include <linux/nospec.h>
16f48ad614SDennis Dalessandro
17f48ad614SDennis Dalessandro #include "hfi.h"
18f48ad614SDennis Dalessandro #include "common.h"
19f48ad614SDennis Dalessandro #include "device.h"
20f48ad614SDennis Dalessandro #include "trace.h"
21f48ad614SDennis Dalessandro #include "qp.h"
22f48ad614SDennis Dalessandro #include "verbs_txreq.h"
230181ce31SDon Hiatt #include "debugfs.h"
242280740fSVishwanathapura, Niranjana #include "vnic.h"
25a74d5307SMitko Haralanov #include "fault.h"
265d18ee67SSebastian Sanchez #include "affinity.h"
270ad45e5fSPiotr Stankiewicz #include "ipoib.h"
28f48ad614SDennis Dalessandro
29f48ad614SDennis Dalessandro static unsigned int hfi1_lkey_table_size = 16;
30f48ad614SDennis Dalessandro module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
31f48ad614SDennis Dalessandro S_IRUGO);
32f48ad614SDennis Dalessandro MODULE_PARM_DESC(lkey_table_size,
33f48ad614SDennis Dalessandro "LKEY table size in bits (2^n, 1 <= n <= 23)");
34f48ad614SDennis Dalessandro
35f48ad614SDennis Dalessandro static unsigned int hfi1_max_pds = 0xFFFF;
36f48ad614SDennis Dalessandro module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
37f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_pds,
38f48ad614SDennis Dalessandro "Maximum number of protection domains to support");
39f48ad614SDennis Dalessandro
40f48ad614SDennis Dalessandro static unsigned int hfi1_max_ahs = 0xFFFF;
41f48ad614SDennis Dalessandro module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
42f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
43f48ad614SDennis Dalessandro
44f6aa7835SJianxin Xiong unsigned int hfi1_max_cqes = 0x2FFFFF;
45f48ad614SDennis Dalessandro module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
46f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_cqes,
47f48ad614SDennis Dalessandro "Maximum number of completion queue entries to support");
48f48ad614SDennis Dalessandro
49f48ad614SDennis Dalessandro unsigned int hfi1_max_cqs = 0x1FFFF;
50f48ad614SDennis Dalessandro module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
51f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
52f48ad614SDennis Dalessandro
53f48ad614SDennis Dalessandro unsigned int hfi1_max_qp_wrs = 0x3FFF;
54f48ad614SDennis Dalessandro module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
55f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
56f48ad614SDennis Dalessandro
57f6aa7835SJianxin Xiong unsigned int hfi1_max_qps = 32768;
58f48ad614SDennis Dalessandro module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
59f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
60f48ad614SDennis Dalessandro
61f48ad614SDennis Dalessandro unsigned int hfi1_max_sges = 0x60;
62f48ad614SDennis Dalessandro module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
63f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
64f48ad614SDennis Dalessandro
65f48ad614SDennis Dalessandro unsigned int hfi1_max_mcast_grps = 16384;
66f48ad614SDennis Dalessandro module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
67f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_mcast_grps,
68f48ad614SDennis Dalessandro "Maximum number of multicast groups to support");
69f48ad614SDennis Dalessandro
70f48ad614SDennis Dalessandro unsigned int hfi1_max_mcast_qp_attached = 16;
71f48ad614SDennis Dalessandro module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
72f48ad614SDennis Dalessandro uint, S_IRUGO);
73f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_mcast_qp_attached,
74f48ad614SDennis Dalessandro "Maximum number of attached QPs to support");
75f48ad614SDennis Dalessandro
76f48ad614SDennis Dalessandro unsigned int hfi1_max_srqs = 1024;
77f48ad614SDennis Dalessandro module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
78f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
79f48ad614SDennis Dalessandro
80f48ad614SDennis Dalessandro unsigned int hfi1_max_srq_sges = 128;
81f48ad614SDennis Dalessandro module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
82f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
83f48ad614SDennis Dalessandro
84f48ad614SDennis Dalessandro unsigned int hfi1_max_srq_wrs = 0x1FFFF;
85f48ad614SDennis Dalessandro module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
86f48ad614SDennis Dalessandro MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
87f48ad614SDennis Dalessandro
88f48ad614SDennis Dalessandro unsigned short piothreshold = 256;
89f48ad614SDennis Dalessandro module_param(piothreshold, ushort, S_IRUGO);
90f48ad614SDennis Dalessandro MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
91f48ad614SDennis Dalessandro
92f48ad614SDennis Dalessandro static unsigned int sge_copy_mode;
93f48ad614SDennis Dalessandro module_param(sge_copy_mode, uint, S_IRUGO);
94f48ad614SDennis Dalessandro MODULE_PARM_DESC(sge_copy_mode,
95f48ad614SDennis Dalessandro "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
96f48ad614SDennis Dalessandro
97f48ad614SDennis Dalessandro static void verbs_sdma_complete(
98f48ad614SDennis Dalessandro struct sdma_txreq *cookie,
99f48ad614SDennis Dalessandro int status);
100f48ad614SDennis Dalessandro
101f48ad614SDennis Dalessandro static int pio_wait(struct rvt_qp *qp,
102f48ad614SDennis Dalessandro struct send_context *sc,
103f48ad614SDennis Dalessandro struct hfi1_pkt_state *ps,
104f48ad614SDennis Dalessandro u32 flag);
105f48ad614SDennis Dalessandro
106f48ad614SDennis Dalessandro /* Length of buffer to create verbs txreq cache name */
107f48ad614SDennis Dalessandro #define TXREQ_NAME_LEN 24
108f48ad614SDennis Dalessandro
109019f118bSBrian Welty static uint wss_threshold = 80;
110f48ad614SDennis Dalessandro module_param(wss_threshold, uint, S_IRUGO);
111f48ad614SDennis Dalessandro MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
112f48ad614SDennis Dalessandro static uint wss_clean_period = 256;
113f48ad614SDennis Dalessandro module_param(wss_clean_period, uint, S_IRUGO);
114f48ad614SDennis Dalessandro MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
115f48ad614SDennis Dalessandro
116f48ad614SDennis Dalessandro /*
11743a474aaSMike Marciniszyn * Translate ib_wr_opcode into ib_wc_opcode.
11843a474aaSMike Marciniszyn */
11943a474aaSMike Marciniszyn const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
12043a474aaSMike Marciniszyn [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
1213c6cb20aSKaike Wan [IB_WR_TID_RDMA_WRITE] = IB_WC_RDMA_WRITE,
12243a474aaSMike Marciniszyn [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
12343a474aaSMike Marciniszyn [IB_WR_SEND] = IB_WC_SEND,
12443a474aaSMike Marciniszyn [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
12543a474aaSMike Marciniszyn [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
12624b11923SKaike Wan [IB_WR_TID_RDMA_READ] = IB_WC_RDMA_READ,
12743a474aaSMike Marciniszyn [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
12843a474aaSMike Marciniszyn [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
12943a474aaSMike Marciniszyn [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
13043a474aaSMike Marciniszyn [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
13143a474aaSMike Marciniszyn [IB_WR_REG_MR] = IB_WC_REG_MR
13243a474aaSMike Marciniszyn };
13343a474aaSMike Marciniszyn
13443a474aaSMike Marciniszyn /*
135f48ad614SDennis Dalessandro * Length of header by opcode, 0 --> not supported
136f48ad614SDennis Dalessandro */
137f48ad614SDennis Dalessandro const u8 hdr_len_by_opcode[256] = {
138f48ad614SDennis Dalessandro /* RC */
139f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_FIRST] = 12 + 8,
140f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_MIDDLE] = 12 + 8,
141f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_LAST] = 12 + 8,
142f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
143f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_ONLY] = 12 + 8,
144f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
145f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
146f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = 12 + 8,
147f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_LAST] = 12 + 8,
148f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
149f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
150f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
151f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_REQUEST] = 12 + 8 + 16,
152f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = 12 + 8 + 4,
153f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = 12 + 8,
154f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = 12 + 8 + 4,
155f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = 12 + 8 + 4,
156f48ad614SDennis Dalessandro [IB_OPCODE_RC_ACKNOWLEDGE] = 12 + 8 + 4,
15737aab620SMike Marciniszyn [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = 12 + 8 + 4 + 8,
158f48ad614SDennis Dalessandro [IB_OPCODE_RC_COMPARE_SWAP] = 12 + 8 + 28,
159f48ad614SDennis Dalessandro [IB_OPCODE_RC_FETCH_ADD] = 12 + 8 + 28,
160bdd8a98cSJianxin Xiong [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = 12 + 8 + 4,
161bdd8a98cSJianxin Xiong [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = 12 + 8 + 4,
16222d136d7SKaike Wan [IB_OPCODE_TID_RDMA_READ_REQ] = 12 + 8 + 36,
16322d136d7SKaike Wan [IB_OPCODE_TID_RDMA_READ_RESP] = 12 + 8 + 36,
1643c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_REQ] = 12 + 8 + 36,
1653c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_RESP] = 12 + 8 + 36,
1663c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_DATA] = 12 + 8 + 36,
1673c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_DATA_LAST] = 12 + 8 + 36,
1683c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_ACK] = 12 + 8 + 36,
1693c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_RESYNC] = 12 + 8 + 36,
170f48ad614SDennis Dalessandro /* UC */
171f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_FIRST] = 12 + 8,
172f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_MIDDLE] = 12 + 8,
173f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_LAST] = 12 + 8,
174f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
175f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_ONLY] = 12 + 8,
176f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
177f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
178f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = 12 + 8,
179f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_LAST] = 12 + 8,
180f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
181f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
182f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
183f48ad614SDennis Dalessandro /* UD */
184f48ad614SDennis Dalessandro [IB_OPCODE_UD_SEND_ONLY] = 12 + 8 + 8,
185f48ad614SDennis Dalessandro [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 12
186f48ad614SDennis Dalessandro };
187f48ad614SDennis Dalessandro
188f48ad614SDennis Dalessandro static const opcode_handler opcode_handler_tbl[256] = {
189f48ad614SDennis Dalessandro /* RC */
190f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_FIRST] = &hfi1_rc_rcv,
191f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_MIDDLE] = &hfi1_rc_rcv,
192f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_LAST] = &hfi1_rc_rcv,
193f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
194f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_ONLY] = &hfi1_rc_rcv,
195f48ad614SDennis Dalessandro [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
196f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_FIRST] = &hfi1_rc_rcv,
197f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = &hfi1_rc_rcv,
198f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_LAST] = &hfi1_rc_rcv,
199f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
200f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_ONLY] = &hfi1_rc_rcv,
201f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
202f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_REQUEST] = &hfi1_rc_rcv,
203f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = &hfi1_rc_rcv,
204f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = &hfi1_rc_rcv,
205f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = &hfi1_rc_rcv,
206f48ad614SDennis Dalessandro [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = &hfi1_rc_rcv,
207f48ad614SDennis Dalessandro [IB_OPCODE_RC_ACKNOWLEDGE] = &hfi1_rc_rcv,
208f48ad614SDennis Dalessandro [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = &hfi1_rc_rcv,
209f48ad614SDennis Dalessandro [IB_OPCODE_RC_COMPARE_SWAP] = &hfi1_rc_rcv,
210f48ad614SDennis Dalessandro [IB_OPCODE_RC_FETCH_ADD] = &hfi1_rc_rcv,
211a2df0c83SJianxin Xiong [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = &hfi1_rc_rcv,
212a2df0c83SJianxin Xiong [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = &hfi1_rc_rcv,
21322d136d7SKaike Wan
21422d136d7SKaike Wan /* TID RDMA has separate handlers for different opcodes.*/
2153c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_REQ] = &hfi1_rc_rcv_tid_rdma_write_req,
2163c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_RESP] = &hfi1_rc_rcv_tid_rdma_write_resp,
2173c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_DATA] = &hfi1_rc_rcv_tid_rdma_write_data,
2183c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_WRITE_DATA_LAST] = &hfi1_rc_rcv_tid_rdma_write_data,
21922d136d7SKaike Wan [IB_OPCODE_TID_RDMA_READ_REQ] = &hfi1_rc_rcv_tid_rdma_read_req,
22022d136d7SKaike Wan [IB_OPCODE_TID_RDMA_READ_RESP] = &hfi1_rc_rcv_tid_rdma_read_resp,
2213c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_RESYNC] = &hfi1_rc_rcv_tid_rdma_resync,
2223c6cb20aSKaike Wan [IB_OPCODE_TID_RDMA_ACK] = &hfi1_rc_rcv_tid_rdma_ack,
22322d136d7SKaike Wan
224f48ad614SDennis Dalessandro /* UC */
225f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_FIRST] = &hfi1_uc_rcv,
226f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_MIDDLE] = &hfi1_uc_rcv,
227f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_LAST] = &hfi1_uc_rcv,
228f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
229f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_ONLY] = &hfi1_uc_rcv,
230f48ad614SDennis Dalessandro [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
231f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_FIRST] = &hfi1_uc_rcv,
232f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = &hfi1_uc_rcv,
233f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_LAST] = &hfi1_uc_rcv,
234f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
235f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_ONLY] = &hfi1_uc_rcv,
236f48ad614SDennis Dalessandro [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
237f48ad614SDennis Dalessandro /* UD */
238f48ad614SDennis Dalessandro [IB_OPCODE_UD_SEND_ONLY] = &hfi1_ud_rcv,
239f48ad614SDennis Dalessandro [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_ud_rcv,
240f48ad614SDennis Dalessandro /* CNP */
241f48ad614SDennis Dalessandro [IB_OPCODE_CNP] = &hfi1_cnp_rcv
242f48ad614SDennis Dalessandro };
243f48ad614SDennis Dalessandro
244b374e060SMike Marciniszyn #define OPMASK 0x1f
245b374e060SMike Marciniszyn
246b374e060SMike Marciniszyn static const u32 pio_opmask[BIT(3)] = {
247b374e060SMike Marciniszyn /* RC */
248b374e060SMike Marciniszyn [IB_OPCODE_RC >> 5] =
249b374e060SMike Marciniszyn BIT(RC_OP(SEND_ONLY) & OPMASK) |
250b374e060SMike Marciniszyn BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
251b374e060SMike Marciniszyn BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
252b374e060SMike Marciniszyn BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
253b374e060SMike Marciniszyn BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
254b374e060SMike Marciniszyn BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
255b374e060SMike Marciniszyn BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
256b374e060SMike Marciniszyn BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
257b374e060SMike Marciniszyn BIT(RC_OP(FETCH_ADD) & OPMASK),
258b374e060SMike Marciniszyn /* UC */
259b374e060SMike Marciniszyn [IB_OPCODE_UC >> 5] =
260b374e060SMike Marciniszyn BIT(UC_OP(SEND_ONLY) & OPMASK) |
261b374e060SMike Marciniszyn BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
262b374e060SMike Marciniszyn BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
263b374e060SMike Marciniszyn BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
264b374e060SMike Marciniszyn };
265b374e060SMike Marciniszyn
266f48ad614SDennis Dalessandro /*
267f48ad614SDennis Dalessandro * System image GUID.
268f48ad614SDennis Dalessandro */
269f48ad614SDennis Dalessandro __be64 ib_hfi1_sys_image_guid;
270f48ad614SDennis Dalessandro
271f48ad614SDennis Dalessandro /*
272f48ad614SDennis Dalessandro * Make sure the QP is ready and able to accept the given opcode.
273f48ad614SDennis Dalessandro */
qp_ok(struct hfi1_packet * packet)2749039746cSDon Hiatt static inline opcode_handler qp_ok(struct hfi1_packet *packet)
275f48ad614SDennis Dalessandro {
276f48ad614SDennis Dalessandro if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
27771e68e3dSJakub Pawlak return NULL;
2789039746cSDon Hiatt if (((packet->opcode & RVT_OPCODE_QP_MASK) ==
2799039746cSDon Hiatt packet->qp->allowed_ops) ||
2809039746cSDon Hiatt (packet->opcode == IB_OPCODE_CNP))
2819039746cSDon Hiatt return opcode_handler_tbl[packet->opcode];
28271e68e3dSJakub Pawlak
28371e68e3dSJakub Pawlak return NULL;
284f48ad614SDennis Dalessandro }
285f48ad614SDennis Dalessandro
hfi1_fault_tx(struct rvt_qp * qp,u8 opcode,u64 pbc)286243d9f43SDon Hiatt static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc)
287243d9f43SDon Hiatt {
288243d9f43SDon Hiatt #ifdef CONFIG_FAULT_INJECTION
2896b6cf935SKaike Wan if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP) {
290243d9f43SDon Hiatt /*
291243d9f43SDon Hiatt * In order to drop non-IB traffic we
292243d9f43SDon Hiatt * set PbcInsertHrc to NONE (0x2).
293243d9f43SDon Hiatt * The packet will still be delivered
294243d9f43SDon Hiatt * to the receiving node but a
295243d9f43SDon Hiatt * KHdrHCRCErr (KDETH packet with a bad
296243d9f43SDon Hiatt * HCRC) will be triggered and the
297243d9f43SDon Hiatt * packet will not be delivered to the
298243d9f43SDon Hiatt * correct context.
299243d9f43SDon Hiatt */
3006b6cf935SKaike Wan pbc &= ~PBC_INSERT_HCRC_SMASK;
301243d9f43SDon Hiatt pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT;
3026b6cf935SKaike Wan } else {
303243d9f43SDon Hiatt /*
304243d9f43SDon Hiatt * In order to drop regular verbs
305243d9f43SDon Hiatt * traffic we set the PbcTestEbp
306243d9f43SDon Hiatt * flag. The packet will still be
307243d9f43SDon Hiatt * delivered to the receiving node but
308243d9f43SDon Hiatt * a 'late ebp error' will be
309243d9f43SDon Hiatt * triggered and will be dropped.
310243d9f43SDon Hiatt */
311243d9f43SDon Hiatt pbc |= PBC_TEST_EBP;
3126b6cf935SKaike Wan }
313243d9f43SDon Hiatt #endif
314243d9f43SDon Hiatt return pbc;
315243d9f43SDon Hiatt }
316243d9f43SDon Hiatt
tid_qp_ok(int opcode,struct hfi1_packet * packet)31722d136d7SKaike Wan static opcode_handler tid_qp_ok(int opcode, struct hfi1_packet *packet)
31822d136d7SKaike Wan {
31922d136d7SKaike Wan if (packet->qp->ibqp.qp_type != IB_QPT_RC ||
32022d136d7SKaike Wan !(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
32122d136d7SKaike Wan return NULL;
32222d136d7SKaike Wan if ((opcode & RVT_OPCODE_QP_MASK) == IB_OPCODE_TID_RDMA)
32322d136d7SKaike Wan return opcode_handler_tbl[opcode];
32422d136d7SKaike Wan return NULL;
32522d136d7SKaike Wan }
32622d136d7SKaike Wan
hfi1_kdeth_eager_rcv(struct hfi1_packet * packet)32722d136d7SKaike Wan void hfi1_kdeth_eager_rcv(struct hfi1_packet *packet)
32822d136d7SKaike Wan {
32922d136d7SKaike Wan struct hfi1_ctxtdata *rcd = packet->rcd;
33022d136d7SKaike Wan struct ib_header *hdr = packet->hdr;
33122d136d7SKaike Wan u32 tlen = packet->tlen;
33222d136d7SKaike Wan struct hfi1_pportdata *ppd = rcd->ppd;
33322d136d7SKaike Wan struct hfi1_ibport *ibp = &ppd->ibport_data;
33422d136d7SKaike Wan struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
33522d136d7SKaike Wan opcode_handler opcode_handler;
33622d136d7SKaike Wan unsigned long flags;
33722d136d7SKaike Wan u32 qp_num;
33822d136d7SKaike Wan int lnh;
33922d136d7SKaike Wan u8 opcode;
34022d136d7SKaike Wan
34122d136d7SKaike Wan /* DW == LRH (2) + BTH (3) + KDETH (9) + CRC (1) */
34222d136d7SKaike Wan if (unlikely(tlen < 15 * sizeof(u32)))
34322d136d7SKaike Wan goto drop;
34422d136d7SKaike Wan
34522d136d7SKaike Wan lnh = be16_to_cpu(hdr->lrh[0]) & 3;
34622d136d7SKaike Wan if (lnh != HFI1_LRH_BTH)
34722d136d7SKaike Wan goto drop;
34822d136d7SKaike Wan
34922d136d7SKaike Wan packet->ohdr = &hdr->u.oth;
35022d136d7SKaike Wan trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
35122d136d7SKaike Wan
35222d136d7SKaike Wan opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
35322d136d7SKaike Wan inc_opstats(tlen, &rcd->opstats->stats[opcode]);
35422d136d7SKaike Wan
35522d136d7SKaike Wan /* verbs_qp can be picked up from any tid_rdma header struct */
35622d136d7SKaike Wan qp_num = be32_to_cpu(packet->ohdr->u.tid_rdma.r_req.verbs_qp) &
35722d136d7SKaike Wan RVT_QPN_MASK;
35822d136d7SKaike Wan
35922d136d7SKaike Wan rcu_read_lock();
36022d136d7SKaike Wan packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
36122d136d7SKaike Wan if (!packet->qp)
36222d136d7SKaike Wan goto drop_rcu;
36322d136d7SKaike Wan spin_lock_irqsave(&packet->qp->r_lock, flags);
36422d136d7SKaike Wan opcode_handler = tid_qp_ok(opcode, packet);
36522d136d7SKaike Wan if (likely(opcode_handler))
36622d136d7SKaike Wan opcode_handler(packet);
36722d136d7SKaike Wan else
36822d136d7SKaike Wan goto drop_unlock;
36922d136d7SKaike Wan spin_unlock_irqrestore(&packet->qp->r_lock, flags);
37022d136d7SKaike Wan rcu_read_unlock();
37122d136d7SKaike Wan
37222d136d7SKaike Wan return;
37322d136d7SKaike Wan drop_unlock:
37422d136d7SKaike Wan spin_unlock_irqrestore(&packet->qp->r_lock, flags);
37522d136d7SKaike Wan drop_rcu:
37622d136d7SKaike Wan rcu_read_unlock();
37722d136d7SKaike Wan drop:
37822d136d7SKaike Wan ibp->rvp.n_pkt_drops++;
37922d136d7SKaike Wan }
38022d136d7SKaike Wan
hfi1_kdeth_expected_rcv(struct hfi1_packet * packet)38122d136d7SKaike Wan void hfi1_kdeth_expected_rcv(struct hfi1_packet *packet)
38222d136d7SKaike Wan {
38322d136d7SKaike Wan struct hfi1_ctxtdata *rcd = packet->rcd;
38422d136d7SKaike Wan struct ib_header *hdr = packet->hdr;
38522d136d7SKaike Wan u32 tlen = packet->tlen;
38622d136d7SKaike Wan struct hfi1_pportdata *ppd = rcd->ppd;
38722d136d7SKaike Wan struct hfi1_ibport *ibp = &ppd->ibport_data;
38822d136d7SKaike Wan struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
38922d136d7SKaike Wan opcode_handler opcode_handler;
39022d136d7SKaike Wan unsigned long flags;
39122d136d7SKaike Wan u32 qp_num;
39222d136d7SKaike Wan int lnh;
39322d136d7SKaike Wan u8 opcode;
39422d136d7SKaike Wan
39522d136d7SKaike Wan /* DW == LRH (2) + BTH (3) + KDETH (9) + CRC (1) */
39622d136d7SKaike Wan if (unlikely(tlen < 15 * sizeof(u32)))
39722d136d7SKaike Wan goto drop;
39822d136d7SKaike Wan
39922d136d7SKaike Wan lnh = be16_to_cpu(hdr->lrh[0]) & 3;
40022d136d7SKaike Wan if (lnh != HFI1_LRH_BTH)
40122d136d7SKaike Wan goto drop;
40222d136d7SKaike Wan
40322d136d7SKaike Wan packet->ohdr = &hdr->u.oth;
40422d136d7SKaike Wan trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
40522d136d7SKaike Wan
40622d136d7SKaike Wan opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
40722d136d7SKaike Wan inc_opstats(tlen, &rcd->opstats->stats[opcode]);
40822d136d7SKaike Wan
40922d136d7SKaike Wan /* verbs_qp can be picked up from any tid_rdma header struct */
41022d136d7SKaike Wan qp_num = be32_to_cpu(packet->ohdr->u.tid_rdma.r_rsp.verbs_qp) &
41122d136d7SKaike Wan RVT_QPN_MASK;
41222d136d7SKaike Wan
41322d136d7SKaike Wan rcu_read_lock();
41422d136d7SKaike Wan packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
41522d136d7SKaike Wan if (!packet->qp)
41622d136d7SKaike Wan goto drop_rcu;
41722d136d7SKaike Wan spin_lock_irqsave(&packet->qp->r_lock, flags);
41822d136d7SKaike Wan opcode_handler = tid_qp_ok(opcode, packet);
41922d136d7SKaike Wan if (likely(opcode_handler))
42022d136d7SKaike Wan opcode_handler(packet);
42122d136d7SKaike Wan else
42222d136d7SKaike Wan goto drop_unlock;
42322d136d7SKaike Wan spin_unlock_irqrestore(&packet->qp->r_lock, flags);
42422d136d7SKaike Wan rcu_read_unlock();
42522d136d7SKaike Wan
42622d136d7SKaike Wan return;
42722d136d7SKaike Wan drop_unlock:
42822d136d7SKaike Wan spin_unlock_irqrestore(&packet->qp->r_lock, flags);
42922d136d7SKaike Wan drop_rcu:
43022d136d7SKaike Wan rcu_read_unlock();
43122d136d7SKaike Wan drop:
43222d136d7SKaike Wan ibp->rvp.n_pkt_drops++;
43322d136d7SKaike Wan }
43422d136d7SKaike Wan
hfi1_do_pkey_check(struct hfi1_packet * packet)4355786adf3SDon Hiatt static int hfi1_do_pkey_check(struct hfi1_packet *packet)
4365786adf3SDon Hiatt {
4375786adf3SDon Hiatt struct hfi1_ctxtdata *rcd = packet->rcd;
4385786adf3SDon Hiatt struct hfi1_pportdata *ppd = rcd->ppd;
4395786adf3SDon Hiatt struct hfi1_16b_header *hdr = packet->hdr;
4405786adf3SDon Hiatt u16 pkey;
4415786adf3SDon Hiatt
4425786adf3SDon Hiatt /* Pkey check needed only for bypass packets */
4435786adf3SDon Hiatt if (packet->etype != RHF_RCV_TYPE_BYPASS)
4445786adf3SDon Hiatt return 0;
4455786adf3SDon Hiatt
4465786adf3SDon Hiatt /* Perform pkey check */
4475786adf3SDon Hiatt pkey = hfi1_16B_get_pkey(hdr);
4485786adf3SDon Hiatt return ingress_pkey_check(ppd, pkey, packet->sc,
4495786adf3SDon Hiatt packet->qp->s_pkey_index,
4505786adf3SDon Hiatt packet->slid, true);
4515786adf3SDon Hiatt }
4525786adf3SDon Hiatt
hfi1_handle_packet(struct hfi1_packet * packet,bool is_mcast)4539039746cSDon Hiatt static inline void hfi1_handle_packet(struct hfi1_packet *packet,
4549039746cSDon Hiatt bool is_mcast)
455f48ad614SDennis Dalessandro {
4569039746cSDon Hiatt u32 qp_num;
457f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd = packet->rcd;
458f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = rcd->ppd;
459f3e862cbSSebastian Sanchez struct hfi1_ibport *ibp = rcd_to_iport(rcd);
460f48ad614SDennis Dalessandro struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
46171e68e3dSJakub Pawlak opcode_handler packet_handler;
462f48ad614SDennis Dalessandro unsigned long flags;
463f48ad614SDennis Dalessandro
4649039746cSDon Hiatt inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]);
465f48ad614SDennis Dalessandro
4669039746cSDon Hiatt if (unlikely(is_mcast)) {
467f48ad614SDennis Dalessandro struct rvt_mcast *mcast;
468f48ad614SDennis Dalessandro struct rvt_mcast_qp *p;
469f48ad614SDennis Dalessandro
4709039746cSDon Hiatt if (!packet->grh)
471f48ad614SDennis Dalessandro goto drop;
4729039746cSDon Hiatt mcast = rvt_mcast_find(&ibp->rvp,
4739039746cSDon Hiatt &packet->grh->dgid,
47472c07e2bSDon Hiatt opa_get_lid(packet->dlid, 9B));
475f48ad614SDennis Dalessandro if (!mcast)
476f48ad614SDennis Dalessandro goto drop;
477817a68a6SDennis Dalessandro rcu_read_lock();
478f48ad614SDennis Dalessandro list_for_each_entry_rcu(p, &mcast->qp_list, list) {
479f48ad614SDennis Dalessandro packet->qp = p->qp;
4805786adf3SDon Hiatt if (hfi1_do_pkey_check(packet))
481817a68a6SDennis Dalessandro goto unlock_drop;
482f48ad614SDennis Dalessandro spin_lock_irqsave(&packet->qp->r_lock, flags);
4839039746cSDon Hiatt packet_handler = qp_ok(packet);
48471e68e3dSJakub Pawlak if (likely(packet_handler))
48571e68e3dSJakub Pawlak packet_handler(packet);
48671e68e3dSJakub Pawlak else
48771e68e3dSJakub Pawlak ibp->rvp.n_pkt_drops++;
488f48ad614SDennis Dalessandro spin_unlock_irqrestore(&packet->qp->r_lock, flags);
489f48ad614SDennis Dalessandro }
490817a68a6SDennis Dalessandro rcu_read_unlock();
491f48ad614SDennis Dalessandro /*
492f48ad614SDennis Dalessandro * Notify rvt_multicast_detach() if it is waiting for us
493f48ad614SDennis Dalessandro * to finish.
494f48ad614SDennis Dalessandro */
495f48ad614SDennis Dalessandro if (atomic_dec_return(&mcast->refcount) <= 1)
496f48ad614SDennis Dalessandro wake_up(&mcast->wait);
497f48ad614SDennis Dalessandro } else {
4989039746cSDon Hiatt /* Get the destination QP number. */
49981cd3891SDon Hiatt if (packet->etype == RHF_RCV_TYPE_BYPASS &&
50081cd3891SDon Hiatt hfi1_16B_get_l4(packet->hdr) == OPA_16B_L4_FM)
50181cd3891SDon Hiatt qp_num = hfi1_16B_get_dest_qpn(packet->mgmt);
50281cd3891SDon Hiatt else
5039039746cSDon Hiatt qp_num = ib_bth_get_qpn(packet->ohdr);
50481cd3891SDon Hiatt
505f48ad614SDennis Dalessandro rcu_read_lock();
506f48ad614SDennis Dalessandro packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
5075786adf3SDon Hiatt if (!packet->qp)
5085786adf3SDon Hiatt goto unlock_drop;
5095786adf3SDon Hiatt
5105786adf3SDon Hiatt if (hfi1_do_pkey_check(packet))
5115786adf3SDon Hiatt goto unlock_drop;
5125786adf3SDon Hiatt
513f48ad614SDennis Dalessandro spin_lock_irqsave(&packet->qp->r_lock, flags);
5149039746cSDon Hiatt packet_handler = qp_ok(packet);
51571e68e3dSJakub Pawlak if (likely(packet_handler))
51671e68e3dSJakub Pawlak packet_handler(packet);
51771e68e3dSJakub Pawlak else
51871e68e3dSJakub Pawlak ibp->rvp.n_pkt_drops++;
519f48ad614SDennis Dalessandro spin_unlock_irqrestore(&packet->qp->r_lock, flags);
520f48ad614SDennis Dalessandro rcu_read_unlock();
521f48ad614SDennis Dalessandro }
522f48ad614SDennis Dalessandro return;
5235786adf3SDon Hiatt unlock_drop:
5245786adf3SDon Hiatt rcu_read_unlock();
525f48ad614SDennis Dalessandro drop:
526f48ad614SDennis Dalessandro ibp->rvp.n_pkt_drops++;
527f48ad614SDennis Dalessandro }
528f48ad614SDennis Dalessandro
5299039746cSDon Hiatt /**
5309039746cSDon Hiatt * hfi1_ib_rcv - process an incoming packet
5319039746cSDon Hiatt * @packet: data packet information
5329039746cSDon Hiatt *
5339039746cSDon Hiatt * This is called to process an incoming packet at interrupt level.
5349039746cSDon Hiatt */
hfi1_ib_rcv(struct hfi1_packet * packet)5359039746cSDon Hiatt void hfi1_ib_rcv(struct hfi1_packet *packet)
5369039746cSDon Hiatt {
5379039746cSDon Hiatt struct hfi1_ctxtdata *rcd = packet->rcd;
5389039746cSDon Hiatt
53972c07e2bSDon Hiatt trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
54072c07e2bSDon Hiatt hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
54172c07e2bSDon Hiatt }
5429039746cSDon Hiatt
hfi1_16B_rcv(struct hfi1_packet * packet)54372c07e2bSDon Hiatt void hfi1_16B_rcv(struct hfi1_packet *packet)
54472c07e2bSDon Hiatt {
54572c07e2bSDon Hiatt struct hfi1_ctxtdata *rcd = packet->rcd;
54672c07e2bSDon Hiatt
54772c07e2bSDon Hiatt trace_input_ibhdr(rcd->dd, packet, false);
54872c07e2bSDon Hiatt hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
5499039746cSDon Hiatt }
5509039746cSDon Hiatt
551f48ad614SDennis Dalessandro /*
552f48ad614SDennis Dalessandro * This is called from a timer to check for QPs
553f48ad614SDennis Dalessandro * which need kernel memory in order to send a packet.
554f48ad614SDennis Dalessandro */
mem_timer(struct timer_list * t)5558064135eSKees Cook static void mem_timer(struct timer_list *t)
556f48ad614SDennis Dalessandro {
5578064135eSKees Cook struct hfi1_ibdev *dev = from_timer(dev, t, mem_timer);
558f48ad614SDennis Dalessandro struct list_head *list = &dev->memwait;
559f48ad614SDennis Dalessandro struct rvt_qp *qp = NULL;
560f48ad614SDennis Dalessandro struct iowait *wait;
561f48ad614SDennis Dalessandro unsigned long flags;
562f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv;
563f48ad614SDennis Dalessandro
564f48ad614SDennis Dalessandro write_seqlock_irqsave(&dev->iowait_lock, flags);
565f48ad614SDennis Dalessandro if (!list_empty(list)) {
566f48ad614SDennis Dalessandro wait = list_first_entry(list, struct iowait, list);
567f48ad614SDennis Dalessandro qp = iowait_to_qp(wait);
568f48ad614SDennis Dalessandro priv = qp->priv;
569f48ad614SDennis Dalessandro list_del_init(&priv->s_iowait.list);
5704e045572SMike Marciniszyn priv->s_iowait.lock = NULL;
571f48ad614SDennis Dalessandro /* refcount held until actual wake up */
572f48ad614SDennis Dalessandro if (!list_empty(list))
573f48ad614SDennis Dalessandro mod_timer(&dev->mem_timer, jiffies + 1);
574f48ad614SDennis Dalessandro }
575f48ad614SDennis Dalessandro write_sequnlock_irqrestore(&dev->iowait_lock, flags);
576f48ad614SDennis Dalessandro
577f48ad614SDennis Dalessandro if (qp)
578f48ad614SDennis Dalessandro hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
579f48ad614SDennis Dalessandro }
580f48ad614SDennis Dalessandro
581f48ad614SDennis Dalessandro /*
582f48ad614SDennis Dalessandro * This is called with progress side lock held.
583f48ad614SDennis Dalessandro */
584f48ad614SDennis Dalessandro /* New API */
verbs_sdma_complete(struct sdma_txreq * cookie,int status)585f48ad614SDennis Dalessandro static void verbs_sdma_complete(
586f48ad614SDennis Dalessandro struct sdma_txreq *cookie,
587f48ad614SDennis Dalessandro int status)
588f48ad614SDennis Dalessandro {
589f48ad614SDennis Dalessandro struct verbs_txreq *tx =
590f48ad614SDennis Dalessandro container_of(cookie, struct verbs_txreq, txreq);
591f48ad614SDennis Dalessandro struct rvt_qp *qp = tx->qp;
592f48ad614SDennis Dalessandro
593f48ad614SDennis Dalessandro spin_lock(&qp->s_lock);
594f48ad614SDennis Dalessandro if (tx->wqe) {
595116aa033SVenkata Sandeep Dhanalakota rvt_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
596f48ad614SDennis Dalessandro } else if (qp->ibqp.qp_type == IB_QPT_RC) {
59730e07416SDon Hiatt struct hfi1_opa_header *hdr;
598f48ad614SDennis Dalessandro
599f48ad614SDennis Dalessandro hdr = &tx->phdr.hdr;
6004bb02e95SMike Marciniszyn if (unlikely(status == SDMA_TXREQ_S_ABORTED))
6014bb02e95SMike Marciniszyn hfi1_rc_verbs_aborted(qp, hdr);
602f48ad614SDennis Dalessandro hfi1_rc_send_complete(qp, hdr);
603f48ad614SDennis Dalessandro }
604f48ad614SDennis Dalessandro spin_unlock(&qp->s_lock);
605f48ad614SDennis Dalessandro
606f48ad614SDennis Dalessandro hfi1_put_txreq(tx);
607f48ad614SDennis Dalessandro }
608f48ad614SDennis Dalessandro
hfi1_wait_kmem(struct rvt_qp * qp)609838b6fd2SKaike Wan void hfi1_wait_kmem(struct rvt_qp *qp)
610f48ad614SDennis Dalessandro {
611f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
612838b6fd2SKaike Wan struct ib_qp *ibqp = &qp->ibqp;
613838b6fd2SKaike Wan struct ib_device *ibdev = ibqp->device;
614838b6fd2SKaike Wan struct hfi1_ibdev *dev = to_idev(ibdev);
615f48ad614SDennis Dalessandro
616f48ad614SDennis Dalessandro if (list_empty(&priv->s_iowait.list)) {
617f48ad614SDennis Dalessandro if (list_empty(&dev->memwait))
618f48ad614SDennis Dalessandro mod_timer(&dev->mem_timer, jiffies + 1);
619f48ad614SDennis Dalessandro qp->s_flags |= RVT_S_WAIT_KMEM;
620f48ad614SDennis Dalessandro list_add_tail(&priv->s_iowait.list, &dev->memwait);
6214e045572SMike Marciniszyn priv->s_iowait.lock = &dev->iowait_lock;
622f48ad614SDennis Dalessandro trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
6234d6f85c3SMike Marciniszyn rvt_get_qp(qp);
624f48ad614SDennis Dalessandro }
625838b6fd2SKaike Wan }
626838b6fd2SKaike Wan
wait_kmem(struct hfi1_ibdev * dev,struct rvt_qp * qp,struct hfi1_pkt_state * ps)627838b6fd2SKaike Wan static int wait_kmem(struct hfi1_ibdev *dev,
628838b6fd2SKaike Wan struct rvt_qp *qp,
629838b6fd2SKaike Wan struct hfi1_pkt_state *ps)
630838b6fd2SKaike Wan {
631838b6fd2SKaike Wan unsigned long flags;
632838b6fd2SKaike Wan int ret = 0;
633838b6fd2SKaike Wan
634838b6fd2SKaike Wan spin_lock_irqsave(&qp->s_lock, flags);
635838b6fd2SKaike Wan if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
636838b6fd2SKaike Wan write_seqlock(&dev->iowait_lock);
637838b6fd2SKaike Wan list_add_tail(&ps->s_txreq->txreq.list,
638838b6fd2SKaike Wan &ps->wait->tx_head);
639838b6fd2SKaike Wan hfi1_wait_kmem(qp);
640f48ad614SDennis Dalessandro write_sequnlock(&dev->iowait_lock);
6415da0fc9dSDennis Dalessandro hfi1_qp_unbusy(qp, ps->wait);
642f48ad614SDennis Dalessandro ret = -EBUSY;
643f48ad614SDennis Dalessandro }
644f48ad614SDennis Dalessandro spin_unlock_irqrestore(&qp->s_lock, flags);
645f48ad614SDennis Dalessandro
646f48ad614SDennis Dalessandro return ret;
647f48ad614SDennis Dalessandro }
648f48ad614SDennis Dalessandro
649f48ad614SDennis Dalessandro /*
650f48ad614SDennis Dalessandro * This routine calls txadds for each sg entry.
651f48ad614SDennis Dalessandro *
652f48ad614SDennis Dalessandro * Add failures will revert the sge cursor
653f48ad614SDennis Dalessandro */
build_verbs_ulp_payload(struct sdma_engine * sde,u32 length,struct verbs_txreq * tx)654f48ad614SDennis Dalessandro static noinline int build_verbs_ulp_payload(
655f48ad614SDennis Dalessandro struct sdma_engine *sde,
656f48ad614SDennis Dalessandro u32 length,
657f48ad614SDennis Dalessandro struct verbs_txreq *tx)
658f48ad614SDennis Dalessandro {
659b777f154SMitko Haralanov struct rvt_sge_state *ss = tx->ss;
660f48ad614SDennis Dalessandro struct rvt_sge *sg_list = ss->sg_list;
661f48ad614SDennis Dalessandro struct rvt_sge sge = ss->sge;
662f48ad614SDennis Dalessandro u8 num_sge = ss->num_sge;
663f48ad614SDennis Dalessandro u32 len;
664f48ad614SDennis Dalessandro int ret = 0;
665f48ad614SDennis Dalessandro
666f48ad614SDennis Dalessandro while (length) {
66787fc34b5SMichael J. Ruhl len = rvt_get_sge_length(&ss->sge, length);
668f48ad614SDennis Dalessandro WARN_ON_ONCE(len == 0);
669f48ad614SDennis Dalessandro ret = sdma_txadd_kvaddr(
670f48ad614SDennis Dalessandro sde->dd,
671f48ad614SDennis Dalessandro &tx->txreq,
672f48ad614SDennis Dalessandro ss->sge.vaddr,
673f48ad614SDennis Dalessandro len);
674f48ad614SDennis Dalessandro if (ret)
675f48ad614SDennis Dalessandro goto bail_txadd;
6761198fceaSBrian Welty rvt_update_sge(ss, len, false);
677f48ad614SDennis Dalessandro length -= len;
678f48ad614SDennis Dalessandro }
679f48ad614SDennis Dalessandro return ret;
680f48ad614SDennis Dalessandro bail_txadd:
681f48ad614SDennis Dalessandro /* unwind cursor */
682f48ad614SDennis Dalessandro ss->sge = sge;
683f48ad614SDennis Dalessandro ss->num_sge = num_sge;
684f48ad614SDennis Dalessandro ss->sg_list = sg_list;
685f48ad614SDennis Dalessandro return ret;
686f48ad614SDennis Dalessandro }
687f48ad614SDennis Dalessandro
6881b311f89SMike Marciniszyn /**
6891b311f89SMike Marciniszyn * update_tx_opstats - record stats by opcode
690cd5962d4SLee Jones * @qp: the qp
6911b311f89SMike Marciniszyn * @ps: transmit packet state
6921b311f89SMike Marciniszyn * @plen: the plen in dwords
6931b311f89SMike Marciniszyn *
6941b311f89SMike Marciniszyn * This is a routine to record the tx opstats after a
6951b311f89SMike Marciniszyn * packet has been presented to the egress mechanism.
6961b311f89SMike Marciniszyn */
update_tx_opstats(struct rvt_qp * qp,struct hfi1_pkt_state * ps,u32 plen)6971b311f89SMike Marciniszyn static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
6981b311f89SMike Marciniszyn u32 plen)
6991b311f89SMike Marciniszyn {
7001b311f89SMike Marciniszyn #ifdef CONFIG_DEBUG_FS
7011b311f89SMike Marciniszyn struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
7021b311f89SMike Marciniszyn struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats);
7031b311f89SMike Marciniszyn
7041b311f89SMike Marciniszyn inc_opstats(plen * 4, &s->stats[ps->opcode]);
7051b311f89SMike Marciniszyn put_cpu_ptr(s);
7061b311f89SMike Marciniszyn #endif
7071b311f89SMike Marciniszyn }
7081b311f89SMike Marciniszyn
709f48ad614SDennis Dalessandro /*
710f48ad614SDennis Dalessandro * Build the number of DMA descriptors needed to send length bytes of data.
711f48ad614SDennis Dalessandro *
712f48ad614SDennis Dalessandro * NOTE: DMA mapping is held in the tx until completed in the ring or
713f48ad614SDennis Dalessandro * the tx desc is freed without having been submitted to the ring
714f48ad614SDennis Dalessandro *
715f48ad614SDennis Dalessandro * This routine ensures all the helper routine calls succeed.
716f48ad614SDennis Dalessandro */
717f48ad614SDennis Dalessandro /* New API */
build_verbs_tx_desc(struct sdma_engine * sde,u32 length,struct verbs_txreq * tx,struct hfi1_ahg_info * ahg_info,u64 pbc)718f48ad614SDennis Dalessandro static int build_verbs_tx_desc(
719f48ad614SDennis Dalessandro struct sdma_engine *sde,
720f48ad614SDennis Dalessandro u32 length,
721f48ad614SDennis Dalessandro struct verbs_txreq *tx,
722a9b6b3bcSDasaratharaman Chandramouli struct hfi1_ahg_info *ahg_info,
723f48ad614SDennis Dalessandro u64 pbc)
724f48ad614SDennis Dalessandro {
725f48ad614SDennis Dalessandro int ret = 0;
726d4d602e9SDon Hiatt struct hfi1_sdma_header *phdr = &tx->phdr;
7279636258fSMitko Haralanov u16 hdrbytes = (tx->hdr_dwords + sizeof(pbc) / 4) << 2;
728566d53a8SDon Hiatt u8 extra_bytes = 0;
729f48ad614SDennis Dalessandro
730566d53a8SDon Hiatt if (tx->phdr.hdr.hdr_type) {
731566d53a8SDon Hiatt /*
732566d53a8SDon Hiatt * hdrbytes accounts for PBC. Need to subtract 8 bytes
733566d53a8SDon Hiatt * before calculating padding.
734566d53a8SDon Hiatt */
735566d53a8SDon Hiatt extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) +
736566d53a8SDon Hiatt (SIZE_OF_CRC << 2) + SIZE_OF_LT;
737566d53a8SDon Hiatt }
738a9b6b3bcSDasaratharaman Chandramouli if (!ahg_info->ahgcount) {
739f48ad614SDennis Dalessandro ret = sdma_txinit_ahg(
740f48ad614SDennis Dalessandro &tx->txreq,
741a9b6b3bcSDasaratharaman Chandramouli ahg_info->tx_flags,
742566d53a8SDon Hiatt hdrbytes + length +
743566d53a8SDon Hiatt extra_bytes,
744a9b6b3bcSDasaratharaman Chandramouli ahg_info->ahgidx,
745f48ad614SDennis Dalessandro 0,
746f48ad614SDennis Dalessandro NULL,
747f48ad614SDennis Dalessandro 0,
748f48ad614SDennis Dalessandro verbs_sdma_complete);
749f48ad614SDennis Dalessandro if (ret)
750f48ad614SDennis Dalessandro goto bail_txadd;
751f48ad614SDennis Dalessandro phdr->pbc = cpu_to_le64(pbc);
752f48ad614SDennis Dalessandro ret = sdma_txadd_kvaddr(
753f48ad614SDennis Dalessandro sde->dd,
754f48ad614SDennis Dalessandro &tx->txreq,
755f48ad614SDennis Dalessandro phdr,
756f48ad614SDennis Dalessandro hdrbytes);
757f48ad614SDennis Dalessandro if (ret)
758f48ad614SDennis Dalessandro goto bail_txadd;
759f48ad614SDennis Dalessandro } else {
760f48ad614SDennis Dalessandro ret = sdma_txinit_ahg(
761f48ad614SDennis Dalessandro &tx->txreq,
762a9b6b3bcSDasaratharaman Chandramouli ahg_info->tx_flags,
763f48ad614SDennis Dalessandro length,
764a9b6b3bcSDasaratharaman Chandramouli ahg_info->ahgidx,
765a9b6b3bcSDasaratharaman Chandramouli ahg_info->ahgcount,
766a9b6b3bcSDasaratharaman Chandramouli ahg_info->ahgdesc,
767f48ad614SDennis Dalessandro hdrbytes,
768f48ad614SDennis Dalessandro verbs_sdma_complete);
769f48ad614SDennis Dalessandro if (ret)
770f48ad614SDennis Dalessandro goto bail_txadd;
771f48ad614SDennis Dalessandro }
772b777f154SMitko Haralanov /* add the ulp payload - if any. tx->ss can be NULL for acks */
773566d53a8SDon Hiatt if (tx->ss) {
774b777f154SMitko Haralanov ret = build_verbs_ulp_payload(sde, length, tx);
775566d53a8SDon Hiatt if (ret)
776566d53a8SDon Hiatt goto bail_txadd;
777566d53a8SDon Hiatt }
778566d53a8SDon Hiatt
779566d53a8SDon Hiatt /* add icrc, lt byte, and padding to flit */
780f8195f3bSDon Hiatt if (extra_bytes)
781*00cbce5cSPatrick Kelsey ret = sdma_txadd_daddr(sde->dd, &tx->txreq, sde->dd->sdma_pad_phys,
782*00cbce5cSPatrick Kelsey extra_bytes);
783566d53a8SDon Hiatt
784f48ad614SDennis Dalessandro bail_txadd:
785f48ad614SDennis Dalessandro return ret;
786f48ad614SDennis Dalessandro }
787f48ad614SDennis Dalessandro
update_hcrc(u8 opcode,u64 pbc)7886b6cf935SKaike Wan static u64 update_hcrc(u8 opcode, u64 pbc)
7896b6cf935SKaike Wan {
7906b6cf935SKaike Wan if ((opcode & IB_OPCODE_TID_RDMA) == IB_OPCODE_TID_RDMA) {
7916b6cf935SKaike Wan pbc &= ~PBC_INSERT_HCRC_SMASK;
7926b6cf935SKaike Wan pbc |= (u64)PBC_IHCRC_LKDETH << PBC_INSERT_HCRC_SHIFT;
7936b6cf935SKaike Wan }
7946b6cf935SKaike Wan return pbc;
7956b6cf935SKaike Wan }
7966b6cf935SKaike Wan
hfi1_verbs_send_dma(struct rvt_qp * qp,struct hfi1_pkt_state * ps,u64 pbc)797f48ad614SDennis Dalessandro int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
798f48ad614SDennis Dalessandro u64 pbc)
799f48ad614SDennis Dalessandro {
800f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
801a9b6b3bcSDasaratharaman Chandramouli struct hfi1_ahg_info *ahg_info = priv->s_ahg;
8029636258fSMitko Haralanov u32 hdrwords = ps->s_txreq->hdr_dwords;
803e922ae06SDon Hiatt u32 len = ps->s_txreq->s_cur_size;
804566d53a8SDon Hiatt u32 plen;
805f48ad614SDennis Dalessandro struct hfi1_ibdev *dev = ps->dev;
806f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = ps->ppd;
807f48ad614SDennis Dalessandro struct verbs_txreq *tx;
808f48ad614SDennis Dalessandro u8 sc5 = priv->s_sc;
809f48ad614SDennis Dalessandro int ret;
810566d53a8SDon Hiatt u32 dwords;
811566d53a8SDon Hiatt
812566d53a8SDon Hiatt if (ps->s_txreq->phdr.hdr.hdr_type) {
813566d53a8SDon Hiatt u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len);
814566d53a8SDon Hiatt
815566d53a8SDon Hiatt dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) +
816566d53a8SDon Hiatt SIZE_OF_LT) >> 2;
817566d53a8SDon Hiatt } else {
818566d53a8SDon Hiatt dwords = (len + 3) >> 2;
819566d53a8SDon Hiatt }
8209636258fSMitko Haralanov plen = hdrwords + dwords + sizeof(pbc) / 4;
821f48ad614SDennis Dalessandro
822f48ad614SDennis Dalessandro tx = ps->s_txreq;
823f48ad614SDennis Dalessandro if (!sdma_txreq_built(&tx->txreq)) {
824f48ad614SDennis Dalessandro if (likely(pbc == 0)) {
825f48ad614SDennis Dalessandro u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
826243d9f43SDon Hiatt
827f48ad614SDennis Dalessandro /* No vl15 here */
828566d53a8SDon Hiatt /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
829566d53a8SDon Hiatt if (ps->s_txreq->phdr.hdr.hdr_type)
830566d53a8SDon Hiatt pbc |= PBC_PACKET_BYPASS |
831566d53a8SDon Hiatt PBC_INSERT_BYPASS_ICRC;
832566d53a8SDon Hiatt else
8337dafbab3SDon Hiatt pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
834f48ad614SDennis Dalessandro
835f48ad614SDennis Dalessandro pbc = create_pbc(ppd,
836243d9f43SDon Hiatt pbc,
837f48ad614SDennis Dalessandro qp->srate_mbps,
838f48ad614SDennis Dalessandro vl,
839f48ad614SDennis Dalessandro plen);
8406b6cf935SKaike Wan
841b2590bddSKaike Wan if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
842b2590bddSKaike Wan pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
843b2590bddSKaike Wan else
8446b6cf935SKaike Wan /* Update HCRC based on packet opcode */
8456b6cf935SKaike Wan pbc = update_hcrc(ps->opcode, pbc);
846f48ad614SDennis Dalessandro }
847f48ad614SDennis Dalessandro tx->wqe = qp->s_wqe;
848b777f154SMitko Haralanov ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
849f48ad614SDennis Dalessandro if (unlikely(ret))
850f48ad614SDennis Dalessandro goto bail_build;
851f48ad614SDennis Dalessandro }
8525da0fc9dSDennis Dalessandro ret = sdma_send_txreq(tx->sde, ps->wait, &tx->txreq, ps->pkts_sent);
853f48ad614SDennis Dalessandro if (unlikely(ret < 0)) {
854f48ad614SDennis Dalessandro if (ret == -ECOMM)
855f48ad614SDennis Dalessandro goto bail_ecomm;
856f48ad614SDennis Dalessandro return ret;
857f48ad614SDennis Dalessandro }
8581b311f89SMike Marciniszyn
8591b311f89SMike Marciniszyn update_tx_opstats(qp, ps, plen);
860f48ad614SDennis Dalessandro trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
861228d2af1SDon Hiatt &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
862f48ad614SDennis Dalessandro return ret;
863f48ad614SDennis Dalessandro
864f48ad614SDennis Dalessandro bail_ecomm:
865f48ad614SDennis Dalessandro /* The current one got "sent" */
866f48ad614SDennis Dalessandro return 0;
867f48ad614SDennis Dalessandro bail_build:
868f48ad614SDennis Dalessandro ret = wait_kmem(dev, qp, ps);
869f48ad614SDennis Dalessandro if (!ret) {
870f48ad614SDennis Dalessandro /* free txreq - bad state */
871f48ad614SDennis Dalessandro hfi1_put_txreq(ps->s_txreq);
872f48ad614SDennis Dalessandro ps->s_txreq = NULL;
873f48ad614SDennis Dalessandro }
874f48ad614SDennis Dalessandro return ret;
875f48ad614SDennis Dalessandro }
876f48ad614SDennis Dalessandro
877f48ad614SDennis Dalessandro /*
878f48ad614SDennis Dalessandro * If we are now in the error state, return zero to flush the
879f48ad614SDennis Dalessandro * send work request.
880f48ad614SDennis Dalessandro */
pio_wait(struct rvt_qp * qp,struct send_context * sc,struct hfi1_pkt_state * ps,u32 flag)881f48ad614SDennis Dalessandro static int pio_wait(struct rvt_qp *qp,
882f48ad614SDennis Dalessandro struct send_context *sc,
883f48ad614SDennis Dalessandro struct hfi1_pkt_state *ps,
884f48ad614SDennis Dalessandro u32 flag)
885f48ad614SDennis Dalessandro {
886f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
887f48ad614SDennis Dalessandro struct hfi1_devdata *dd = sc->dd;
888f48ad614SDennis Dalessandro unsigned long flags;
889f48ad614SDennis Dalessandro int ret = 0;
890f48ad614SDennis Dalessandro
891f48ad614SDennis Dalessandro /*
892f48ad614SDennis Dalessandro * Note that as soon as want_buffer() is called and
893f48ad614SDennis Dalessandro * possibly before it returns, sc_piobufavail()
894f48ad614SDennis Dalessandro * could be called. Therefore, put QP on the I/O wait list before
895f48ad614SDennis Dalessandro * enabling the PIO avail interrupt.
896f48ad614SDennis Dalessandro */
897f48ad614SDennis Dalessandro spin_lock_irqsave(&qp->s_lock, flags);
898f48ad614SDennis Dalessandro if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
8999aefcabeSMike Marciniszyn write_seqlock(&sc->waitlock);
900f48ad614SDennis Dalessandro list_add_tail(&ps->s_txreq->txreq.list,
9015da0fc9dSDennis Dalessandro &ps->wait->tx_head);
902f48ad614SDennis Dalessandro if (list_empty(&priv->s_iowait.list)) {
903f48ad614SDennis Dalessandro struct hfi1_ibdev *dev = &dd->verbs_dev;
904f48ad614SDennis Dalessandro int was_empty;
905f48ad614SDennis Dalessandro
906f48ad614SDennis Dalessandro dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
9072e2ba09eSMike Marciniszyn dev->n_piodrain += !!(flag & HFI1_S_WAIT_PIO_DRAIN);
908f48ad614SDennis Dalessandro qp->s_flags |= flag;
909f48ad614SDennis Dalessandro was_empty = list_empty(&sc->piowait);
91034025fb0SKaike Wan iowait_get_priority(&priv->s_iowait);
911bcad2913SKaike Wan iowait_queue(ps->pkts_sent, &priv->s_iowait,
912bcad2913SKaike Wan &sc->piowait);
9139aefcabeSMike Marciniszyn priv->s_iowait.lock = &sc->waitlock;
914f48ad614SDennis Dalessandro trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
9154d6f85c3SMike Marciniszyn rvt_get_qp(qp);
916f48ad614SDennis Dalessandro /* counting: only call wantpiobuf_intr if first user */
917f48ad614SDennis Dalessandro if (was_empty)
918f48ad614SDennis Dalessandro hfi1_sc_wantpiobuf_intr(sc, 1);
919f48ad614SDennis Dalessandro }
9209aefcabeSMike Marciniszyn write_sequnlock(&sc->waitlock);
9215da0fc9dSDennis Dalessandro hfi1_qp_unbusy(qp, ps->wait);
922f48ad614SDennis Dalessandro ret = -EBUSY;
923f48ad614SDennis Dalessandro }
924f48ad614SDennis Dalessandro spin_unlock_irqrestore(&qp->s_lock, flags);
925f48ad614SDennis Dalessandro return ret;
926f48ad614SDennis Dalessandro }
927f48ad614SDennis Dalessandro
verbs_pio_complete(void * arg,int code)928f48ad614SDennis Dalessandro static void verbs_pio_complete(void *arg, int code)
929f48ad614SDennis Dalessandro {
930f48ad614SDennis Dalessandro struct rvt_qp *qp = (struct rvt_qp *)arg;
931f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
932f48ad614SDennis Dalessandro
933f48ad614SDennis Dalessandro if (iowait_pio_dec(&priv->s_iowait))
934f48ad614SDennis Dalessandro iowait_drain_wakeup(&priv->s_iowait);
935f48ad614SDennis Dalessandro }
936f48ad614SDennis Dalessandro
hfi1_verbs_send_pio(struct rvt_qp * qp,struct hfi1_pkt_state * ps,u64 pbc)937f48ad614SDennis Dalessandro int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
938f48ad614SDennis Dalessandro u64 pbc)
939f48ad614SDennis Dalessandro {
940f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
9419636258fSMitko Haralanov u32 hdrwords = ps->s_txreq->hdr_dwords;
942b777f154SMitko Haralanov struct rvt_sge_state *ss = ps->s_txreq->ss;
943e922ae06SDon Hiatt u32 len = ps->s_txreq->s_cur_size;
944566d53a8SDon Hiatt u32 dwords;
945566d53a8SDon Hiatt u32 plen;
946f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = ps->ppd;
947566d53a8SDon Hiatt u32 *hdr;
948f48ad614SDennis Dalessandro u8 sc5;
949f48ad614SDennis Dalessandro unsigned long flags = 0;
950f48ad614SDennis Dalessandro struct send_context *sc;
951f48ad614SDennis Dalessandro struct pio_buf *pbuf;
952f48ad614SDennis Dalessandro int wc_status = IB_WC_SUCCESS;
953f48ad614SDennis Dalessandro int ret = 0;
954f48ad614SDennis Dalessandro pio_release_cb cb = NULL;
955566d53a8SDon Hiatt u8 extra_bytes = 0;
956566d53a8SDon Hiatt
957566d53a8SDon Hiatt if (ps->s_txreq->phdr.hdr.hdr_type) {
958566d53a8SDon Hiatt u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len);
959566d53a8SDon Hiatt
960566d53a8SDon Hiatt extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT;
961566d53a8SDon Hiatt dwords = (len + extra_bytes) >> 2;
962566d53a8SDon Hiatt hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah;
963566d53a8SDon Hiatt } else {
964566d53a8SDon Hiatt dwords = (len + 3) >> 2;
965566d53a8SDon Hiatt hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh;
966566d53a8SDon Hiatt }
9679636258fSMitko Haralanov plen = hdrwords + dwords + sizeof(pbc) / 4;
968f48ad614SDennis Dalessandro
969f48ad614SDennis Dalessandro /* only RC/UC use complete */
970f48ad614SDennis Dalessandro switch (qp->ibqp.qp_type) {
971f48ad614SDennis Dalessandro case IB_QPT_RC:
972f48ad614SDennis Dalessandro case IB_QPT_UC:
973f48ad614SDennis Dalessandro cb = verbs_pio_complete;
974f48ad614SDennis Dalessandro break;
975f48ad614SDennis Dalessandro default:
976f48ad614SDennis Dalessandro break;
977f48ad614SDennis Dalessandro }
978f48ad614SDennis Dalessandro
979f48ad614SDennis Dalessandro /* vl15 special case taken care of in ud.c */
980f48ad614SDennis Dalessandro sc5 = priv->s_sc;
981f48ad614SDennis Dalessandro sc = ps->s_txreq->psc;
982f48ad614SDennis Dalessandro
983f48ad614SDennis Dalessandro if (likely(pbc == 0)) {
984f48ad614SDennis Dalessandro u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
985243d9f43SDon Hiatt
986566d53a8SDon Hiatt /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
987566d53a8SDon Hiatt if (ps->s_txreq->phdr.hdr.hdr_type)
988566d53a8SDon Hiatt pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
989566d53a8SDon Hiatt else
9907dafbab3SDon Hiatt pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
991a74d5307SMitko Haralanov
992b2590bddSKaike Wan pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen);
993a74d5307SMitko Haralanov if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
994566d53a8SDon Hiatt pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
995b2590bddSKaike Wan else
9966b6cf935SKaike Wan /* Update HCRC based on packet opcode */
9976b6cf935SKaike Wan pbc = update_hcrc(ps->opcode, pbc);
998f48ad614SDennis Dalessandro }
999f48ad614SDennis Dalessandro if (cb)
1000f48ad614SDennis Dalessandro iowait_pio_inc(&priv->s_iowait);
1001f48ad614SDennis Dalessandro pbuf = sc_buffer_alloc(sc, plen, cb, qp);
10027b0b6925SDenis Efremov if (IS_ERR_OR_NULL(pbuf)) {
1003f48ad614SDennis Dalessandro if (cb)
1004f48ad614SDennis Dalessandro verbs_pio_complete(qp, 0);
1005942a8993SMike Marciniszyn if (IS_ERR(pbuf)) {
1006f48ad614SDennis Dalessandro /*
1007f48ad614SDennis Dalessandro * If we have filled the PIO buffers to capacity and are
1008f48ad614SDennis Dalessandro * not in an active state this request is not going to
1009f48ad614SDennis Dalessandro * go out to so just complete it with an error or else a
1010f48ad614SDennis Dalessandro * ULP or the core may be stuck waiting.
1011f48ad614SDennis Dalessandro */
1012f48ad614SDennis Dalessandro hfi1_cdbg(
1013f48ad614SDennis Dalessandro PIO,
1014f48ad614SDennis Dalessandro "alloc failed. state not active, completing");
1015f48ad614SDennis Dalessandro wc_status = IB_WC_GENERAL_ERR;
1016f48ad614SDennis Dalessandro goto pio_bail;
1017f48ad614SDennis Dalessandro } else {
1018f48ad614SDennis Dalessandro /*
1019f48ad614SDennis Dalessandro * This is a normal occurrence. The PIO buffs are full
1020f48ad614SDennis Dalessandro * up but we are still happily sending, well we could be
1021f48ad614SDennis Dalessandro * so lets continue to queue the request.
1022f48ad614SDennis Dalessandro */
1023f48ad614SDennis Dalessandro hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1024f48ad614SDennis Dalessandro ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1025f48ad614SDennis Dalessandro if (!ret)
1026f48ad614SDennis Dalessandro /* txreq not queued - free */
1027f48ad614SDennis Dalessandro goto bail;
1028f48ad614SDennis Dalessandro /* tx consumed in wait */
1029f48ad614SDennis Dalessandro return ret;
1030f48ad614SDennis Dalessandro }
1031f48ad614SDennis Dalessandro }
1032f48ad614SDennis Dalessandro
1033566d53a8SDon Hiatt if (dwords == 0) {
1034f48ad614SDennis Dalessandro pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1035f48ad614SDennis Dalessandro } else {
1036566d53a8SDon Hiatt seg_pio_copy_start(pbuf, pbc,
1037566d53a8SDon Hiatt hdr, hdrwords * 4);
1038f48ad614SDennis Dalessandro if (ss) {
1039f48ad614SDennis Dalessandro while (len) {
1040f48ad614SDennis Dalessandro void *addr = ss->sge.vaddr;
104187fc34b5SMichael J. Ruhl u32 slen = rvt_get_sge_length(&ss->sge, len);
1042f48ad614SDennis Dalessandro
10431198fceaSBrian Welty rvt_update_sge(ss, slen, false);
1044f48ad614SDennis Dalessandro seg_pio_copy_mid(pbuf, addr, slen);
1045f48ad614SDennis Dalessandro len -= slen;
1046f48ad614SDennis Dalessandro }
1047f48ad614SDennis Dalessandro }
1048f8195f3bSDon Hiatt /* add icrc, lt byte, and padding to flit */
1049f8195f3bSDon Hiatt if (extra_bytes)
105022bb1365SMike Marciniszyn seg_pio_copy_mid(pbuf, ppd->dd->sdma_pad_dma,
105122bb1365SMike Marciniszyn extra_bytes);
1052566d53a8SDon Hiatt
1053566d53a8SDon Hiatt seg_pio_copy_end(pbuf);
1054f48ad614SDennis Dalessandro }
1055f48ad614SDennis Dalessandro
10561b311f89SMike Marciniszyn update_tx_opstats(qp, ps, plen);
1057f48ad614SDennis Dalessandro trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1058228d2af1SDon Hiatt &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
1059f48ad614SDennis Dalessandro
1060f48ad614SDennis Dalessandro pio_bail:
10614bb02e95SMike Marciniszyn spin_lock_irqsave(&qp->s_lock, flags);
1062f48ad614SDennis Dalessandro if (qp->s_wqe) {
1063116aa033SVenkata Sandeep Dhanalakota rvt_send_complete(qp, qp->s_wqe, wc_status);
1064f48ad614SDennis Dalessandro } else if (qp->ibqp.qp_type == IB_QPT_RC) {
10654bb02e95SMike Marciniszyn if (unlikely(wc_status == IB_WC_GENERAL_ERR))
10664bb02e95SMike Marciniszyn hfi1_rc_verbs_aborted(qp, &ps->s_txreq->phdr.hdr);
1067f48ad614SDennis Dalessandro hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1068f48ad614SDennis Dalessandro }
10694bb02e95SMike Marciniszyn spin_unlock_irqrestore(&qp->s_lock, flags);
1070f48ad614SDennis Dalessandro
1071f48ad614SDennis Dalessandro ret = 0;
1072f48ad614SDennis Dalessandro
1073f48ad614SDennis Dalessandro bail:
1074f48ad614SDennis Dalessandro hfi1_put_txreq(ps->s_txreq);
1075f48ad614SDennis Dalessandro return ret;
1076f48ad614SDennis Dalessandro }
1077f48ad614SDennis Dalessandro
1078f48ad614SDennis Dalessandro /*
1079f48ad614SDennis Dalessandro * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1080f48ad614SDennis Dalessandro * being an entry from the partition key table), return 0
1081f48ad614SDennis Dalessandro * otherwise. Use the matching criteria for egress partition keys
1082f48ad614SDennis Dalessandro * specified in the OPAv1 spec., section 9.1l.7.
1083f48ad614SDennis Dalessandro */
egress_pkey_matches_entry(u16 pkey,u16 ent)1084f48ad614SDennis Dalessandro static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1085f48ad614SDennis Dalessandro {
1086f48ad614SDennis Dalessandro u16 mkey = pkey & PKEY_LOW_15_MASK;
1087f48ad614SDennis Dalessandro u16 mentry = ent & PKEY_LOW_15_MASK;
1088f48ad614SDennis Dalessandro
1089f48ad614SDennis Dalessandro if (mkey == mentry) {
1090f48ad614SDennis Dalessandro /*
1091f48ad614SDennis Dalessandro * If pkey[15] is set (full partition member),
1092f48ad614SDennis Dalessandro * is bit 15 in the corresponding table element
1093f48ad614SDennis Dalessandro * clear (limited member)?
1094f48ad614SDennis Dalessandro */
1095f48ad614SDennis Dalessandro if (pkey & PKEY_MEMBER_MASK)
1096f48ad614SDennis Dalessandro return !!(ent & PKEY_MEMBER_MASK);
1097f48ad614SDennis Dalessandro return 1;
1098f48ad614SDennis Dalessandro }
1099f48ad614SDennis Dalessandro return 0;
1100f48ad614SDennis Dalessandro }
1101f48ad614SDennis Dalessandro
1102f48ad614SDennis Dalessandro /**
1103f48ad614SDennis Dalessandro * egress_pkey_check - check P_KEY of a packet
1104f48ad614SDennis Dalessandro * @ppd: Physical IB port data
1105566d53a8SDon Hiatt * @slid: SLID for packet
1106cd5962d4SLee Jones * @pkey: PKEY for header
1107f48ad614SDennis Dalessandro * @sc5: SC for packet
1108f48ad614SDennis Dalessandro * @s_pkey_index: It will be used for look up optimization for kernel contexts
1109f48ad614SDennis Dalessandro * only. If it is negative value, then it means user contexts is calling this
1110f48ad614SDennis Dalessandro * function.
1111f48ad614SDennis Dalessandro *
1112f48ad614SDennis Dalessandro * It checks if hdr's pkey is valid.
1113f48ad614SDennis Dalessandro *
1114f48ad614SDennis Dalessandro * Return: 0 on success, otherwise, 1
1115f48ad614SDennis Dalessandro */
egress_pkey_check(struct hfi1_pportdata * ppd,u32 slid,u16 pkey,u8 sc5,int8_t s_pkey_index)1116566d53a8SDon Hiatt int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1117f48ad614SDennis Dalessandro u8 sc5, int8_t s_pkey_index)
1118f48ad614SDennis Dalessandro {
1119f48ad614SDennis Dalessandro struct hfi1_devdata *dd;
1120f48ad614SDennis Dalessandro int i;
1121f48ad614SDennis Dalessandro int is_user_ctxt_mechanism = (s_pkey_index < 0);
1122f48ad614SDennis Dalessandro
1123f48ad614SDennis Dalessandro if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1124f48ad614SDennis Dalessandro return 0;
1125f48ad614SDennis Dalessandro
1126f48ad614SDennis Dalessandro /* If SC15, pkey[0:14] must be 0x7fff */
1127f48ad614SDennis Dalessandro if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1128f48ad614SDennis Dalessandro goto bad;
1129f48ad614SDennis Dalessandro
1130f48ad614SDennis Dalessandro /* Is the pkey = 0x0, or 0x8000? */
1131f48ad614SDennis Dalessandro if ((pkey & PKEY_LOW_15_MASK) == 0)
1132f48ad614SDennis Dalessandro goto bad;
1133f48ad614SDennis Dalessandro
1134f48ad614SDennis Dalessandro /*
1135f48ad614SDennis Dalessandro * For the kernel contexts only, if a qp is passed into the function,
1136f48ad614SDennis Dalessandro * the most likely matching pkey has index qp->s_pkey_index
1137f48ad614SDennis Dalessandro */
1138f48ad614SDennis Dalessandro if (!is_user_ctxt_mechanism &&
1139f48ad614SDennis Dalessandro egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1140f48ad614SDennis Dalessandro return 0;
1141f48ad614SDennis Dalessandro }
1142f48ad614SDennis Dalessandro
1143f48ad614SDennis Dalessandro for (i = 0; i < MAX_PKEY_VALUES; i++) {
1144f48ad614SDennis Dalessandro if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1145f48ad614SDennis Dalessandro return 0;
1146f48ad614SDennis Dalessandro }
1147f48ad614SDennis Dalessandro bad:
1148f48ad614SDennis Dalessandro /*
1149f48ad614SDennis Dalessandro * For the user-context mechanism, the P_KEY check would only happen
1150f48ad614SDennis Dalessandro * once per SDMA request, not once per packet. Therefore, there's no
1151f48ad614SDennis Dalessandro * need to increment the counter for the user-context mechanism.
1152f48ad614SDennis Dalessandro */
1153f48ad614SDennis Dalessandro if (!is_user_ctxt_mechanism) {
1154f48ad614SDennis Dalessandro incr_cntr64(&ppd->port_xmit_constraint_errors);
1155f48ad614SDennis Dalessandro dd = ppd->dd;
1156f48ad614SDennis Dalessandro if (!(dd->err_info_xmit_constraint.status &
1157f48ad614SDennis Dalessandro OPA_EI_STATUS_SMASK)) {
1158f48ad614SDennis Dalessandro dd->err_info_xmit_constraint.status |=
1159f48ad614SDennis Dalessandro OPA_EI_STATUS_SMASK;
1160f48ad614SDennis Dalessandro dd->err_info_xmit_constraint.slid = slid;
1161f48ad614SDennis Dalessandro dd->err_info_xmit_constraint.pkey = pkey;
1162f48ad614SDennis Dalessandro }
1163f48ad614SDennis Dalessandro }
1164f48ad614SDennis Dalessandro return 1;
1165f48ad614SDennis Dalessandro }
1166f48ad614SDennis Dalessandro
1167cd5962d4SLee Jones /*
1168f48ad614SDennis Dalessandro * get_send_routine - choose an egress routine
1169f48ad614SDennis Dalessandro *
1170f48ad614SDennis Dalessandro * Choose an egress routine based on QP type
1171f48ad614SDennis Dalessandro * and size
1172f48ad614SDennis Dalessandro */
get_send_routine(struct rvt_qp * qp,struct hfi1_pkt_state * ps)1173f48ad614SDennis Dalessandro static inline send_routine get_send_routine(struct rvt_qp *qp,
1174566d53a8SDon Hiatt struct hfi1_pkt_state *ps)
1175f48ad614SDennis Dalessandro {
1176f48ad614SDennis Dalessandro struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1177f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
1178566d53a8SDon Hiatt struct verbs_txreq *tx = ps->s_txreq;
1179f48ad614SDennis Dalessandro
1180f48ad614SDennis Dalessandro if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1181f48ad614SDennis Dalessandro return dd->process_pio_send;
1182f48ad614SDennis Dalessandro switch (qp->ibqp.qp_type) {
1183f48ad614SDennis Dalessandro case IB_QPT_SMI:
1184f48ad614SDennis Dalessandro return dd->process_pio_send;
1185f48ad614SDennis Dalessandro case IB_QPT_GSI:
1186f48ad614SDennis Dalessandro case IB_QPT_UD:
1187f48ad614SDennis Dalessandro break;
1188f48ad614SDennis Dalessandro case IB_QPT_UC:
1189270a9833SMike Marciniszyn case IB_QPT_RC:
1190270a9833SMike Marciniszyn priv->s_running_pkt_size =
1191270a9833SMike Marciniszyn (tx->s_cur_size + priv->s_running_pkt_size) / 2;
1192f48ad614SDennis Dalessandro if (piothreshold &&
1193270a9833SMike Marciniszyn priv->s_running_pkt_size <= min(piothreshold, qp->pmtu) &&
1194566d53a8SDon Hiatt (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) &&
1195f48ad614SDennis Dalessandro iowait_sdma_pending(&priv->s_iowait) == 0 &&
1196f48ad614SDennis Dalessandro !sdma_txreq_built(&tx->txreq))
1197f48ad614SDennis Dalessandro return dd->process_pio_send;
1198f48ad614SDennis Dalessandro break;
1199f48ad614SDennis Dalessandro default:
1200f48ad614SDennis Dalessandro break;
1201f48ad614SDennis Dalessandro }
1202f48ad614SDennis Dalessandro return dd->process_dma_send;
1203f48ad614SDennis Dalessandro }
1204f48ad614SDennis Dalessandro
1205f48ad614SDennis Dalessandro /**
1206f48ad614SDennis Dalessandro * hfi1_verbs_send - send a packet
1207f48ad614SDennis Dalessandro * @qp: the QP to send on
1208f48ad614SDennis Dalessandro * @ps: the state of the packet to send
1209f48ad614SDennis Dalessandro *
1210f48ad614SDennis Dalessandro * Return zero if packet is sent or queued OK.
1211f48ad614SDennis Dalessandro * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1212f48ad614SDennis Dalessandro */
hfi1_verbs_send(struct rvt_qp * qp,struct hfi1_pkt_state * ps)1213f48ad614SDennis Dalessandro int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1214f48ad614SDennis Dalessandro {
1215f48ad614SDennis Dalessandro struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1216f48ad614SDennis Dalessandro struct hfi1_qp_priv *priv = qp->priv;
121781cd3891SDon Hiatt struct ib_other_headers *ohdr = NULL;
1218f48ad614SDennis Dalessandro send_routine sr;
1219f48ad614SDennis Dalessandro int ret;
1220566d53a8SDon Hiatt u16 pkey;
1221566d53a8SDon Hiatt u32 slid;
122281cd3891SDon Hiatt u8 l4 = 0;
1223f48ad614SDennis Dalessandro
1224f48ad614SDennis Dalessandro /* locate the pkey within the headers */
1225566d53a8SDon Hiatt if (ps->s_txreq->phdr.hdr.hdr_type) {
1226566d53a8SDon Hiatt struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah;
1227566d53a8SDon Hiatt
122881cd3891SDon Hiatt l4 = hfi1_16B_get_l4(hdr);
122981cd3891SDon Hiatt if (l4 == OPA_16B_L4_IB_LOCAL)
1230566d53a8SDon Hiatt ohdr = &hdr->u.oth;
123181cd3891SDon Hiatt else if (l4 == OPA_16B_L4_IB_GLOBAL)
123281cd3891SDon Hiatt ohdr = &hdr->u.l.oth;
123381cd3891SDon Hiatt
1234566d53a8SDon Hiatt slid = hfi1_16B_get_slid(hdr);
1235566d53a8SDon Hiatt pkey = hfi1_16B_get_pkey(hdr);
1236566d53a8SDon Hiatt } else {
1237566d53a8SDon Hiatt struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh;
1238566d53a8SDon Hiatt u8 lnh = ib_get_lnh(hdr);
1239566d53a8SDon Hiatt
1240f48ad614SDennis Dalessandro if (lnh == HFI1_LRH_GRH)
1241f48ad614SDennis Dalessandro ohdr = &hdr->u.l.oth;
1242f48ad614SDennis Dalessandro else
1243f48ad614SDennis Dalessandro ohdr = &hdr->u.oth;
1244566d53a8SDon Hiatt slid = ib_get_slid(hdr);
1245566d53a8SDon Hiatt pkey = ib_bth_get_pkey(ohdr);
1246566d53a8SDon Hiatt }
1247f48ad614SDennis Dalessandro
124881cd3891SDon Hiatt if (likely(l4 != OPA_16B_L4_FM))
1249566d53a8SDon Hiatt ps->opcode = ib_bth_get_opcode(ohdr);
125081cd3891SDon Hiatt else
125181cd3891SDon Hiatt ps->opcode = IB_OPCODE_UD_SEND_ONLY;
125281cd3891SDon Hiatt
1253566d53a8SDon Hiatt sr = get_send_routine(qp, ps);
1254566d53a8SDon Hiatt ret = egress_pkey_check(dd->pport, slid, pkey,
1255566d53a8SDon Hiatt priv->s_sc, qp->s_pkey_index);
1256f48ad614SDennis Dalessandro if (unlikely(ret)) {
1257f48ad614SDennis Dalessandro /*
1258f48ad614SDennis Dalessandro * The value we are returning here does not get propagated to
1259f48ad614SDennis Dalessandro * the verbs caller. Thus we need to complete the request with
1260f48ad614SDennis Dalessandro * error otherwise the caller could be sitting waiting on the
1261f48ad614SDennis Dalessandro * completion event. Only do this for PIO. SDMA has its own
1262f48ad614SDennis Dalessandro * mechanism for handling the errors. So for SDMA we can just
1263f48ad614SDennis Dalessandro * return.
1264f48ad614SDennis Dalessandro */
1265f48ad614SDennis Dalessandro if (sr == dd->process_pio_send) {
1266f48ad614SDennis Dalessandro unsigned long flags;
1267f48ad614SDennis Dalessandro
1268f48ad614SDennis Dalessandro hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1269f48ad614SDennis Dalessandro __func__);
1270f48ad614SDennis Dalessandro spin_lock_irqsave(&qp->s_lock, flags);
1271116aa033SVenkata Sandeep Dhanalakota rvt_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1272f48ad614SDennis Dalessandro spin_unlock_irqrestore(&qp->s_lock, flags);
1273f48ad614SDennis Dalessandro }
1274f48ad614SDennis Dalessandro return -EINVAL;
1275f48ad614SDennis Dalessandro }
1276f48ad614SDennis Dalessandro if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1277f48ad614SDennis Dalessandro return pio_wait(qp,
1278f48ad614SDennis Dalessandro ps->s_txreq->psc,
1279f48ad614SDennis Dalessandro ps,
12802e2ba09eSMike Marciniszyn HFI1_S_WAIT_PIO_DRAIN);
1281f48ad614SDennis Dalessandro return sr(qp, ps, 0);
1282f48ad614SDennis Dalessandro }
1283f48ad614SDennis Dalessandro
1284f48ad614SDennis Dalessandro /**
1285f48ad614SDennis Dalessandro * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1286f48ad614SDennis Dalessandro * @dd: the device data structure
1287f48ad614SDennis Dalessandro */
hfi1_fill_device_attr(struct hfi1_devdata * dd)1288f48ad614SDennis Dalessandro static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1289f48ad614SDennis Dalessandro {
1290f48ad614SDennis Dalessandro struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
12915e6e9424SMichael J. Ruhl u32 ver = dd->dc8051_ver;
1292f48ad614SDennis Dalessandro
1293f48ad614SDennis Dalessandro memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1294f48ad614SDennis Dalessandro
12955e6e9424SMichael J. Ruhl rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) |
12965e6e9424SMichael J. Ruhl ((u64)(dc8051_ver_min(ver)) << 16) |
12975e6e9424SMichael J. Ruhl (u64)dc8051_ver_patch(ver);
12985e6e9424SMichael J. Ruhl
1299f48ad614SDennis Dalessandro rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1300f48ad614SDennis Dalessandro IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1301f48ad614SDennis Dalessandro IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1302c72cfe3eSJianxin Xiong IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1303e945c653SJason Gunthorpe IB_DEVICE_MEM_MGT_EXTENSIONS;
1304e945c653SJason Gunthorpe rdi->dparms.props.kernel_cap_flags = IBK_RDMA_NETDEV_OPA;
1305f48ad614SDennis Dalessandro rdi->dparms.props.page_size_cap = PAGE_SIZE;
1306f48ad614SDennis Dalessandro rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1307f48ad614SDennis Dalessandro rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1308f48ad614SDennis Dalessandro rdi->dparms.props.hw_ver = dd->minrev;
1309f48ad614SDennis Dalessandro rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1310c72cfe3eSJianxin Xiong rdi->dparms.props.max_mr_size = U64_MAX;
1311c72cfe3eSJianxin Xiong rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1312f48ad614SDennis Dalessandro rdi->dparms.props.max_qp = hfi1_max_qps;
13133c6cb20aSKaike Wan rdi->dparms.props.max_qp_wr =
13143c6cb20aSKaike Wan (hfi1_max_qp_wrs >= HFI1_QP_WQE_INVALID ?
13153c6cb20aSKaike Wan HFI1_QP_WQE_INVALID - 1 : hfi1_max_qp_wrs);
131633023fb8SSteve Wise rdi->dparms.props.max_send_sge = hfi1_max_sges;
131733023fb8SSteve Wise rdi->dparms.props.max_recv_sge = hfi1_max_sges;
1318f48ad614SDennis Dalessandro rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1319f48ad614SDennis Dalessandro rdi->dparms.props.max_cq = hfi1_max_cqs;
1320f48ad614SDennis Dalessandro rdi->dparms.props.max_ah = hfi1_max_ahs;
1321f48ad614SDennis Dalessandro rdi->dparms.props.max_cqe = hfi1_max_cqes;
1322f48ad614SDennis Dalessandro rdi->dparms.props.max_pd = hfi1_max_pds;
1323f48ad614SDennis Dalessandro rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1324f48ad614SDennis Dalessandro rdi->dparms.props.max_qp_init_rd_atom = 255;
1325f48ad614SDennis Dalessandro rdi->dparms.props.max_srq = hfi1_max_srqs;
1326f48ad614SDennis Dalessandro rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1327f48ad614SDennis Dalessandro rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1328f48ad614SDennis Dalessandro rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1329f48ad614SDennis Dalessandro rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1330f48ad614SDennis Dalessandro rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1331f48ad614SDennis Dalessandro rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1332f48ad614SDennis Dalessandro rdi->dparms.props.max_total_mcast_qp_attach =
1333f48ad614SDennis Dalessandro rdi->dparms.props.max_mcast_qp_attach *
1334f48ad614SDennis Dalessandro rdi->dparms.props.max_mcast_grp;
1335f48ad614SDennis Dalessandro }
1336f48ad614SDennis Dalessandro
opa_speed_to_ib(u16 in)1337f48ad614SDennis Dalessandro static inline u16 opa_speed_to_ib(u16 in)
1338f48ad614SDennis Dalessandro {
1339f48ad614SDennis Dalessandro u16 out = 0;
1340f48ad614SDennis Dalessandro
1341f48ad614SDennis Dalessandro if (in & OPA_LINK_SPEED_25G)
1342f48ad614SDennis Dalessandro out |= IB_SPEED_EDR;
1343f48ad614SDennis Dalessandro if (in & OPA_LINK_SPEED_12_5G)
1344f48ad614SDennis Dalessandro out |= IB_SPEED_FDR;
1345f48ad614SDennis Dalessandro
1346f48ad614SDennis Dalessandro return out;
1347f48ad614SDennis Dalessandro }
1348f48ad614SDennis Dalessandro
1349f48ad614SDennis Dalessandro /*
1350f48ad614SDennis Dalessandro * Convert a single OPA link width (no multiple flags) to an IB value.
1351f48ad614SDennis Dalessandro * A zero OPA link width means link down, which means the IB width value
1352f48ad614SDennis Dalessandro * is a don't care.
1353f48ad614SDennis Dalessandro */
opa_width_to_ib(u16 in)1354f48ad614SDennis Dalessandro static inline u16 opa_width_to_ib(u16 in)
1355f48ad614SDennis Dalessandro {
1356f48ad614SDennis Dalessandro switch (in) {
1357f48ad614SDennis Dalessandro case OPA_LINK_WIDTH_1X:
1358f48ad614SDennis Dalessandro /* map 2x and 3x to 1x as they don't exist in IB */
1359f48ad614SDennis Dalessandro case OPA_LINK_WIDTH_2X:
1360f48ad614SDennis Dalessandro case OPA_LINK_WIDTH_3X:
1361f48ad614SDennis Dalessandro return IB_WIDTH_1X;
1362f48ad614SDennis Dalessandro default: /* link down or unknown, return our largest width */
1363f48ad614SDennis Dalessandro case OPA_LINK_WIDTH_4X:
1364f48ad614SDennis Dalessandro return IB_WIDTH_4X;
1365f48ad614SDennis Dalessandro }
1366f48ad614SDennis Dalessandro }
1367f48ad614SDennis Dalessandro
query_port(struct rvt_dev_info * rdi,u32 port_num,struct ib_port_attr * props)13681fb7f897SMark Bloch static int query_port(struct rvt_dev_info *rdi, u32 port_num,
1369f48ad614SDennis Dalessandro struct ib_port_attr *props)
1370f48ad614SDennis Dalessandro {
1371f48ad614SDennis Dalessandro struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1372f48ad614SDennis Dalessandro struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1373f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
137451e658f5SDasaratharaman Chandramouli u32 lid = ppd->lid;
1375f48ad614SDennis Dalessandro
1376c4550c63SOr Gerlitz /* props being zeroed by the caller, avoid zeroing it here */
1377f48ad614SDennis Dalessandro props->lid = lid ? lid : 0;
1378f48ad614SDennis Dalessandro props->lmc = ppd->lmc;
1379f48ad614SDennis Dalessandro /* OPA logical states match IB logical states */
1380f48ad614SDennis Dalessandro props->state = driver_lstate(ppd);
1381bec7c79cSByczkowski, Jakub props->phys_state = driver_pstate(ppd);
1382f48ad614SDennis Dalessandro props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1383f48ad614SDennis Dalessandro props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1384f48ad614SDennis Dalessandro /* see rate_show() in ib core/sysfs.c */
1385376ceb31SAharon Landau props->active_speed = opa_speed_to_ib(ppd->link_speed_active);
1386f48ad614SDennis Dalessandro props->max_vl_num = ppd->vls_supported;
1387f48ad614SDennis Dalessandro
1388f48ad614SDennis Dalessandro /* Once we are a "first class" citizen and have added the OPA MTUs to
1389f48ad614SDennis Dalessandro * the core we can advertise the larger MTU enum to the ULPs, for now
1390f48ad614SDennis Dalessandro * advertise only 4K.
1391f48ad614SDennis Dalessandro *
1392f48ad614SDennis Dalessandro * Those applications which are either OPA aware or pass the MTU enum
1393f48ad614SDennis Dalessandro * from the Path Records to us will get the new 8k MTU. Those that
1394f48ad614SDennis Dalessandro * attempt to process the MTU enum may fail in various ways.
1395f48ad614SDennis Dalessandro */
1396f48ad614SDennis Dalessandro props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1397f48ad614SDennis Dalessandro 4096 : hfi1_max_mtu), IB_MTU_4096);
1398f48ad614SDennis Dalessandro props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
139969a3ffaaSJan Sokolowski mtu_to_enum(ppd->ibmtu, IB_MTU_4096);
1400b135e324SMike Marciniszyn props->phys_mtu = hfi1_max_mtu;
1401f48ad614SDennis Dalessandro
1402f48ad614SDennis Dalessandro return 0;
1403f48ad614SDennis Dalessandro }
1404f48ad614SDennis Dalessandro
modify_device(struct ib_device * device,int device_modify_mask,struct ib_device_modify * device_modify)1405f48ad614SDennis Dalessandro static int modify_device(struct ib_device *device,
1406f48ad614SDennis Dalessandro int device_modify_mask,
1407f48ad614SDennis Dalessandro struct ib_device_modify *device_modify)
1408f48ad614SDennis Dalessandro {
1409f48ad614SDennis Dalessandro struct hfi1_devdata *dd = dd_from_ibdev(device);
1410f48ad614SDennis Dalessandro unsigned i;
1411f48ad614SDennis Dalessandro int ret;
1412f48ad614SDennis Dalessandro
1413f48ad614SDennis Dalessandro if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1414f48ad614SDennis Dalessandro IB_DEVICE_MODIFY_NODE_DESC)) {
1415f48ad614SDennis Dalessandro ret = -EOPNOTSUPP;
1416f48ad614SDennis Dalessandro goto bail;
1417f48ad614SDennis Dalessandro }
1418f48ad614SDennis Dalessandro
1419f48ad614SDennis Dalessandro if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1420bd99fdeaSYuval Shaia memcpy(device->node_desc, device_modify->node_desc,
1421bd99fdeaSYuval Shaia IB_DEVICE_NODE_DESC_MAX);
1422f48ad614SDennis Dalessandro for (i = 0; i < dd->num_pports; i++) {
1423f48ad614SDennis Dalessandro struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1424f48ad614SDennis Dalessandro
1425f48ad614SDennis Dalessandro hfi1_node_desc_chg(ibp);
1426f48ad614SDennis Dalessandro }
1427f48ad614SDennis Dalessandro }
1428f48ad614SDennis Dalessandro
1429f48ad614SDennis Dalessandro if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1430f48ad614SDennis Dalessandro ib_hfi1_sys_image_guid =
1431f48ad614SDennis Dalessandro cpu_to_be64(device_modify->sys_image_guid);
1432f48ad614SDennis Dalessandro for (i = 0; i < dd->num_pports; i++) {
1433f48ad614SDennis Dalessandro struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1434f48ad614SDennis Dalessandro
1435f48ad614SDennis Dalessandro hfi1_sys_guid_chg(ibp);
1436f48ad614SDennis Dalessandro }
1437f48ad614SDennis Dalessandro }
1438f48ad614SDennis Dalessandro
1439f48ad614SDennis Dalessandro ret = 0;
1440f48ad614SDennis Dalessandro
1441f48ad614SDennis Dalessandro bail:
1442f48ad614SDennis Dalessandro return ret;
1443f48ad614SDennis Dalessandro }
1444f48ad614SDennis Dalessandro
shut_down_port(struct rvt_dev_info * rdi,u32 port_num)14451fb7f897SMark Bloch static int shut_down_port(struct rvt_dev_info *rdi, u32 port_num)
1446f48ad614SDennis Dalessandro {
1447f48ad614SDennis Dalessandro struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1448f48ad614SDennis Dalessandro struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1449f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1450f48ad614SDennis Dalessandro
1451f48ad614SDennis Dalessandro set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1452f48ad614SDennis Dalessandro OPA_LINKDOWN_REASON_UNKNOWN);
1453e58f889eSye xingchen return set_link_state(ppd, HLS_DN_DOWNDEF);
1454f48ad614SDennis Dalessandro }
1455f48ad614SDennis Dalessandro
hfi1_get_guid_be(struct rvt_dev_info * rdi,struct rvt_ibport * rvp,int guid_index,__be64 * guid)1456f48ad614SDennis Dalessandro static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1457f48ad614SDennis Dalessandro int guid_index, __be64 *guid)
1458f48ad614SDennis Dalessandro {
1459f48ad614SDennis Dalessandro struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1460f48ad614SDennis Dalessandro
1461a6cd5f08SJakub Pawlak if (guid_index >= HFI1_GUIDS_PER_PORT)
1462f48ad614SDennis Dalessandro return -EINVAL;
1463f48ad614SDennis Dalessandro
1464a6cd5f08SJakub Pawlak *guid = get_sguid(ibp, guid_index);
1465f48ad614SDennis Dalessandro return 0;
1466f48ad614SDennis Dalessandro }
1467f48ad614SDennis Dalessandro
1468f48ad614SDennis Dalessandro /*
1469f48ad614SDennis Dalessandro * convert ah port,sl to sc
1470f48ad614SDennis Dalessandro */
ah_to_sc(struct ib_device * ibdev,struct rdma_ah_attr * ah)147190898850SDasaratharaman Chandramouli u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah)
1472f48ad614SDennis Dalessandro {
1473d8966fcdSDasaratharaman Chandramouli struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah));
1474f48ad614SDennis Dalessandro
1475d8966fcdSDasaratharaman Chandramouli return ibp->sl_to_sc[rdma_ah_get_sl(ah)];
1476f48ad614SDennis Dalessandro }
1477f48ad614SDennis Dalessandro
hfi1_check_ah(struct ib_device * ibdev,struct rdma_ah_attr * ah_attr)147890898850SDasaratharaman Chandramouli static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1479f48ad614SDennis Dalessandro {
1480f48ad614SDennis Dalessandro struct hfi1_ibport *ibp;
1481f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd;
1482f48ad614SDennis Dalessandro struct hfi1_devdata *dd;
1483f48ad614SDennis Dalessandro u8 sc5;
14840dbfaa9fSIra Weiny u8 sl;
1485f48ad614SDennis Dalessandro
148613c19222SDon Hiatt if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) &&
148713c19222SDon Hiatt !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
148813c19222SDon Hiatt return -EINVAL;
148913c19222SDon Hiatt
1490f48ad614SDennis Dalessandro /* test the mapping for validity */
1491d8966fcdSDasaratharaman Chandramouli ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1492f48ad614SDennis Dalessandro ppd = ppd_from_ibp(ibp);
1493f48ad614SDennis Dalessandro dd = dd_from_ppd(ppd);
14940dbfaa9fSIra Weiny
14950dbfaa9fSIra Weiny sl = rdma_ah_get_sl(ah_attr);
14960dbfaa9fSIra Weiny if (sl >= ARRAY_SIZE(ibp->sl_to_sc))
14970dbfaa9fSIra Weiny return -EINVAL;
14986497d0a9SGustavo A. R. Silva sl = array_index_nospec(sl, ARRAY_SIZE(ibp->sl_to_sc));
14990dbfaa9fSIra Weiny
15000dbfaa9fSIra Weiny sc5 = ibp->sl_to_sc[sl];
1501f48ad614SDennis Dalessandro if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1502f48ad614SDennis Dalessandro return -EINVAL;
1503f48ad614SDennis Dalessandro return 0;
1504f48ad614SDennis Dalessandro }
1505f48ad614SDennis Dalessandro
hfi1_notify_new_ah(struct ib_device * ibdev,struct rdma_ah_attr * ah_attr,struct rvt_ah * ah)1506f48ad614SDennis Dalessandro static void hfi1_notify_new_ah(struct ib_device *ibdev,
150790898850SDasaratharaman Chandramouli struct rdma_ah_attr *ah_attr,
1508f48ad614SDennis Dalessandro struct rvt_ah *ah)
1509f48ad614SDennis Dalessandro {
1510f48ad614SDennis Dalessandro struct hfi1_ibport *ibp;
1511f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd;
1512f48ad614SDennis Dalessandro struct hfi1_devdata *dd;
1513f48ad614SDennis Dalessandro u8 sc5;
1514d98bb7f7SDon Hiatt struct rdma_ah_attr *attr = &ah->attr;
1515f48ad614SDennis Dalessandro
1516f48ad614SDennis Dalessandro /*
1517f48ad614SDennis Dalessandro * Do not trust reading anything from rvt_ah at this point as it is not
1518f48ad614SDennis Dalessandro * done being setup. We can however modify things which we need to set.
1519f48ad614SDennis Dalessandro */
1520f48ad614SDennis Dalessandro
1521d8966fcdSDasaratharaman Chandramouli ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1522f48ad614SDennis Dalessandro ppd = ppd_from_ibp(ibp);
1523d8966fcdSDasaratharaman Chandramouli sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)];
1524d98bb7f7SDon Hiatt hfi1_update_ah_attr(ibdev, attr);
1525d98bb7f7SDon Hiatt hfi1_make_opa_lid(attr);
1526f48ad614SDennis Dalessandro dd = dd_from_ppd(ppd);
1527f48ad614SDennis Dalessandro ah->vl = sc_to_vlt(dd, sc5);
1528f48ad614SDennis Dalessandro if (ah->vl < num_vls || ah->vl == 15)
1529f48ad614SDennis Dalessandro ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1530f48ad614SDennis Dalessandro }
1531f48ad614SDennis Dalessandro
1532f48ad614SDennis Dalessandro /**
1533f48ad614SDennis Dalessandro * hfi1_get_npkeys - return the size of the PKEY table for context 0
1534f48ad614SDennis Dalessandro * @dd: the hfi1_ib device
1535f48ad614SDennis Dalessandro */
hfi1_get_npkeys(struct hfi1_devdata * dd)1536f48ad614SDennis Dalessandro unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1537f48ad614SDennis Dalessandro {
1538f48ad614SDennis Dalessandro return ARRAY_SIZE(dd->pport[0].pkeys);
1539f48ad614SDennis Dalessandro }
1540f48ad614SDennis Dalessandro
init_ibport(struct hfi1_pportdata * ppd)1541f48ad614SDennis Dalessandro static void init_ibport(struct hfi1_pportdata *ppd)
1542f48ad614SDennis Dalessandro {
1543f48ad614SDennis Dalessandro struct hfi1_ibport *ibp = &ppd->ibport_data;
1544f48ad614SDennis Dalessandro size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1545f48ad614SDennis Dalessandro int i;
1546f48ad614SDennis Dalessandro
1547f48ad614SDennis Dalessandro for (i = 0; i < sz; i++) {
1548f48ad614SDennis Dalessandro ibp->sl_to_sc[i] = i;
1549f48ad614SDennis Dalessandro ibp->sc_to_sl[i] = i;
1550f48ad614SDennis Dalessandro }
1551f48ad614SDennis Dalessandro
1552bf90aaddSMichael J. Ruhl for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++)
1553bf90aaddSMichael J. Ruhl INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list);
15548064135eSKees Cook timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0);
1555bf90aaddSMichael J. Ruhl
1556f48ad614SDennis Dalessandro spin_lock_init(&ibp->rvp.lock);
1557f48ad614SDennis Dalessandro /* Set the prefix to the default value (see ch. 4.1.1) */
1558f48ad614SDennis Dalessandro ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1559f48ad614SDennis Dalessandro ibp->rvp.sm_lid = 0;
1560cb49366fSVishwanathapura, Niranjana /*
1561cb49366fSVishwanathapura, Niranjana * Below should only set bits defined in OPA PortInfo.CapabilityMask
1562cb49366fSVishwanathapura, Niranjana * and PortInfo.CapabilityMask3
1563cb49366fSVishwanathapura, Niranjana */
1564f48ad614SDennis Dalessandro ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1565f48ad614SDennis Dalessandro IB_PORT_CAP_MASK_NOTICE_SUP;
1566cb49366fSVishwanathapura, Niranjana ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported;
1567f48ad614SDennis Dalessandro ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1568f48ad614SDennis Dalessandro ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1569f48ad614SDennis Dalessandro ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1570f48ad614SDennis Dalessandro ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1571f48ad614SDennis Dalessandro ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1572f48ad614SDennis Dalessandro
1573f48ad614SDennis Dalessandro RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1574f48ad614SDennis Dalessandro RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1575f48ad614SDennis Dalessandro }
1576f48ad614SDennis Dalessandro
hfi1_get_dev_fw_str(struct ib_device * ibdev,char * str)15779abb0d1bSLeon Romanovsky static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str)
1578939b6ca8SIra Weiny {
1579939b6ca8SIra Weiny struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1580939b6ca8SIra Weiny struct hfi1_ibdev *dev = dev_from_rdi(rdi);
15815e6e9424SMichael J. Ruhl u32 ver = dd_from_dev(dev)->dc8051_ver;
1582939b6ca8SIra Weiny
15839abb0d1bSLeon Romanovsky snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver),
15845e6e9424SMichael J. Ruhl dc8051_ver_min(ver), dc8051_ver_patch(ver));
1585939b6ca8SIra Weiny }
1586939b6ca8SIra Weiny
1587b7481944SJianxin Xiong static const char * const driver_cntr_names[] = {
1588b7481944SJianxin Xiong /* must be element 0*/
1589b7481944SJianxin Xiong "DRIVER_KernIntr",
1590b7481944SJianxin Xiong "DRIVER_ErrorIntr",
1591b7481944SJianxin Xiong "DRIVER_Tx_Errs",
1592b7481944SJianxin Xiong "DRIVER_Rcv_Errs",
1593b7481944SJianxin Xiong "DRIVER_HW_Errs",
1594b7481944SJianxin Xiong "DRIVER_NoPIOBufs",
1595b7481944SJianxin Xiong "DRIVER_CtxtsOpen",
1596b7481944SJianxin Xiong "DRIVER_RcvLen_Errs",
1597b7481944SJianxin Xiong "DRIVER_EgrBufFull",
1598b7481944SJianxin Xiong "DRIVER_EgrHdrFull"
1599b7481944SJianxin Xiong };
1600b7481944SJianxin Xiong
160113f30b0fSAharon Landau static struct rdma_stat_desc *dev_cntr_descs;
160213f30b0fSAharon Landau static struct rdma_stat_desc *port_cntr_descs;
160336d84219SPiotr Stankiewicz int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1604b7481944SJianxin Xiong static int num_dev_cntrs;
1605b7481944SJianxin Xiong static int num_port_cntrs;
1606b7481944SJianxin Xiong
1607b7481944SJianxin Xiong /*
1608b7481944SJianxin Xiong * Convert a list of names separated by '\n' into an array of NULL terminated
1609b7481944SJianxin Xiong * strings. Optionally some entries can be reserved in the array to hold extra
1610b7481944SJianxin Xiong * external strings.
1611b7481944SJianxin Xiong */
init_cntr_names(const char * names_in,const size_t names_len,int num_extra_names,int * num_cntrs,struct rdma_stat_desc ** cntr_descs)161213f30b0fSAharon Landau static int init_cntr_names(const char *names_in, const size_t names_len,
161313f30b0fSAharon Landau int num_extra_names, int *num_cntrs,
161413f30b0fSAharon Landau struct rdma_stat_desc **cntr_descs)
1615b7481944SJianxin Xiong {
1616ef90f0a1SDean Luick struct rdma_stat_desc *names_out;
1617ef90f0a1SDean Luick char *p;
1618b7481944SJianxin Xiong int i, n;
1619b7481944SJianxin Xiong
1620b7481944SJianxin Xiong n = 0;
1621b7481944SJianxin Xiong for (i = 0; i < names_len; i++)
1622b7481944SJianxin Xiong if (names_in[i] == '\n')
1623b7481944SJianxin Xiong n++;
1624b7481944SJianxin Xiong
1625ef90f0a1SDean Luick names_out = kzalloc((n + num_extra_names) * sizeof(*names_out)
1626ef90f0a1SDean Luick + names_len,
1627b7481944SJianxin Xiong GFP_KERNEL);
1628b7481944SJianxin Xiong if (!names_out) {
1629b7481944SJianxin Xiong *num_cntrs = 0;
163013f30b0fSAharon Landau *cntr_descs = NULL;
1631b7481944SJianxin Xiong return -ENOMEM;
1632b7481944SJianxin Xiong }
1633b7481944SJianxin Xiong
1634ef90f0a1SDean Luick p = (char *)&names_out[n + num_extra_names];
1635b7481944SJianxin Xiong memcpy(p, names_in, names_len);
1636b7481944SJianxin Xiong
1637b7481944SJianxin Xiong for (i = 0; i < n; i++) {
1638ef90f0a1SDean Luick names_out[i].name = p;
1639b7481944SJianxin Xiong p = strchr(p, '\n');
1640b7481944SJianxin Xiong *p++ = '\0';
1641b7481944SJianxin Xiong }
1642b7481944SJianxin Xiong
1643b7481944SJianxin Xiong *num_cntrs = n;
1644ef90f0a1SDean Luick *cntr_descs = names_out;
1645b7481944SJianxin Xiong return 0;
1646b7481944SJianxin Xiong }
1647b7481944SJianxin Xiong
hfi1_alloc_hw_device_stats(struct ib_device * ibdev)16484b5f4d3fSJason Gunthorpe static struct rdma_hw_stats *hfi1_alloc_hw_device_stats(struct ib_device *ibdev)
16494b5f4d3fSJason Gunthorpe {
1650ef90f0a1SDean Luick if (!dev_cntr_descs) {
1651ef90f0a1SDean Luick struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1652ef90f0a1SDean Luick int i, err;
1653ef90f0a1SDean Luick
1654ef90f0a1SDean Luick err = init_cntr_names(dd->cntrnames, dd->cntrnameslen,
1655ef90f0a1SDean Luick num_driver_cntrs,
1656ef90f0a1SDean Luick &num_dev_cntrs, &dev_cntr_descs);
1657ef90f0a1SDean Luick if (err)
16584b5f4d3fSJason Gunthorpe return NULL;
1659ef90f0a1SDean Luick
1660ef90f0a1SDean Luick for (i = 0; i < num_driver_cntrs; i++)
1661ef90f0a1SDean Luick dev_cntr_descs[num_dev_cntrs + i].name =
1662ef90f0a1SDean Luick driver_cntr_names[i];
1663ef90f0a1SDean Luick }
166413f30b0fSAharon Landau return rdma_alloc_hw_stats_struct(dev_cntr_descs,
1665b7481944SJianxin Xiong num_dev_cntrs + num_driver_cntrs,
1666b7481944SJianxin Xiong RDMA_HW_STATS_DEFAULT_LIFESPAN);
16674b5f4d3fSJason Gunthorpe }
16684b5f4d3fSJason Gunthorpe
hfi_alloc_hw_port_stats(struct ib_device * ibdev,u32 port_num)16694b5f4d3fSJason Gunthorpe static struct rdma_hw_stats *hfi_alloc_hw_port_stats(struct ib_device *ibdev,
16704b5f4d3fSJason Gunthorpe u32 port_num)
16714b5f4d3fSJason Gunthorpe {
1672ef90f0a1SDean Luick if (!port_cntr_descs) {
1673ef90f0a1SDean Luick struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1674ef90f0a1SDean Luick int err;
1675ef90f0a1SDean Luick
1676ef90f0a1SDean Luick err = init_cntr_names(dd->portcntrnames, dd->portcntrnameslen,
1677ef90f0a1SDean Luick 0,
1678ef90f0a1SDean Luick &num_port_cntrs, &port_cntr_descs);
1679ef90f0a1SDean Luick if (err)
16804b5f4d3fSJason Gunthorpe return NULL;
1681ef90f0a1SDean Luick }
168213f30b0fSAharon Landau return rdma_alloc_hw_stats_struct(port_cntr_descs, num_port_cntrs,
1683b7481944SJianxin Xiong RDMA_HW_STATS_DEFAULT_LIFESPAN);
1684b7481944SJianxin Xiong }
1685b7481944SJianxin Xiong
hfi1_sps_ints(void)1686b7481944SJianxin Xiong static u64 hfi1_sps_ints(void)
1687b7481944SJianxin Xiong {
168803b92789SMatthew Wilcox unsigned long index, flags;
1689b7481944SJianxin Xiong struct hfi1_devdata *dd;
1690b7481944SJianxin Xiong u64 sps_ints = 0;
1691b7481944SJianxin Xiong
169203b92789SMatthew Wilcox xa_lock_irqsave(&hfi1_dev_table, flags);
169303b92789SMatthew Wilcox xa_for_each(&hfi1_dev_table, index, dd) {
1694b7481944SJianxin Xiong sps_ints += get_all_cpu_total(dd->int_counter);
1695b7481944SJianxin Xiong }
169603b92789SMatthew Wilcox xa_unlock_irqrestore(&hfi1_dev_table, flags);
1697b7481944SJianxin Xiong return sps_ints;
1698b7481944SJianxin Xiong }
1699b7481944SJianxin Xiong
get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u32 port,int index)1700b7481944SJianxin Xiong static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
17011fb7f897SMark Bloch u32 port, int index)
1702b7481944SJianxin Xiong {
1703b7481944SJianxin Xiong u64 *values;
1704b7481944SJianxin Xiong int count;
1705b7481944SJianxin Xiong
1706b7481944SJianxin Xiong if (!port) {
1707b7481944SJianxin Xiong u64 *stats = (u64 *)&hfi1_stats;
1708b7481944SJianxin Xiong int i;
1709b7481944SJianxin Xiong
1710b7481944SJianxin Xiong hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1711b7481944SJianxin Xiong values[num_dev_cntrs] = hfi1_sps_ints();
1712b7481944SJianxin Xiong for (i = 1; i < num_driver_cntrs; i++)
1713b7481944SJianxin Xiong values[num_dev_cntrs + i] = stats[i];
1714b7481944SJianxin Xiong count = num_dev_cntrs + num_driver_cntrs;
1715b7481944SJianxin Xiong } else {
1716b7481944SJianxin Xiong struct hfi1_ibport *ibp = to_iport(ibdev, port);
1717b7481944SJianxin Xiong
1718b7481944SJianxin Xiong hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1719b7481944SJianxin Xiong count = num_port_cntrs;
1720b7481944SJianxin Xiong }
1721b7481944SJianxin Xiong
1722b7481944SJianxin Xiong memcpy(stats->value, values, count * sizeof(u64));
1723b7481944SJianxin Xiong return count;
1724b7481944SJianxin Xiong }
1725b7481944SJianxin Xiong
1726e3c320caSKamal Heib static const struct ib_device_ops hfi1_dev_ops = {
17277a154142SJason Gunthorpe .owner = THIS_MODULE,
1728b9560a41SJason Gunthorpe .driver_id = RDMA_DRIVER_HFI1,
1729b9560a41SJason Gunthorpe
17304b5f4d3fSJason Gunthorpe .alloc_hw_device_stats = hfi1_alloc_hw_device_stats,
17314b5f4d3fSJason Gunthorpe .alloc_hw_port_stats = hfi_alloc_hw_port_stats,
1732e3c320caSKamal Heib .alloc_rdma_netdev = hfi1_vnic_alloc_rn,
1733915e4af5SJason Gunthorpe .device_group = &ib_hfi1_attr_group,
1734e3c320caSKamal Heib .get_dev_fw_str = hfi1_get_dev_fw_str,
1735e3c320caSKamal Heib .get_hw_stats = get_hw_stats,
1736e3c320caSKamal Heib .modify_device = modify_device,
1737d7407d16SJason Gunthorpe .port_groups = hfi1_attr_port_groups,
1738e3c320caSKamal Heib /* keep process mad in the driver */
1739e3c320caSKamal Heib .process_mad = hfi1_process_mad,
17400ad45e5fSPiotr Stankiewicz .rdma_netdev_get_params = hfi1_ipoib_rn_get_params,
1741e3c320caSKamal Heib };
1742e3c320caSKamal Heib
1743f48ad614SDennis Dalessandro /**
1744f48ad614SDennis Dalessandro * hfi1_register_ib_device - register our device with the infiniband core
1745f48ad614SDennis Dalessandro * @dd: the device data structure
1746f48ad614SDennis Dalessandro * Return 0 if successful, errno if unsuccessful.
1747f48ad614SDennis Dalessandro */
hfi1_register_ib_device(struct hfi1_devdata * dd)1748f48ad614SDennis Dalessandro int hfi1_register_ib_device(struct hfi1_devdata *dd)
1749f48ad614SDennis Dalessandro {
1750f48ad614SDennis Dalessandro struct hfi1_ibdev *dev = &dd->verbs_dev;
1751f48ad614SDennis Dalessandro struct ib_device *ibdev = &dev->rdi.ibdev;
1752f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = dd->pport;
1753a6cd5f08SJakub Pawlak struct hfi1_ibport *ibp = &ppd->ibport_data;
1754f48ad614SDennis Dalessandro unsigned i;
1755f48ad614SDennis Dalessandro int ret;
1756f48ad614SDennis Dalessandro
1757f48ad614SDennis Dalessandro for (i = 0; i < dd->num_pports; i++)
1758f48ad614SDennis Dalessandro init_ibport(ppd + i);
1759f48ad614SDennis Dalessandro
1760f48ad614SDennis Dalessandro /* Only need to initialize non-zero fields. */
1761f48ad614SDennis Dalessandro
17628064135eSKees Cook timer_setup(&dev->mem_timer, mem_timer, 0);
1763f48ad614SDennis Dalessandro
1764f48ad614SDennis Dalessandro seqlock_init(&dev->iowait_lock);
17654e045572SMike Marciniszyn seqlock_init(&dev->txwait_lock);
1766f48ad614SDennis Dalessandro INIT_LIST_HEAD(&dev->txwait);
1767f48ad614SDennis Dalessandro INIT_LIST_HEAD(&dev->memwait);
1768f48ad614SDennis Dalessandro
1769f48ad614SDennis Dalessandro ret = verbs_txreq_init(dev);
1770f48ad614SDennis Dalessandro if (ret)
1771f48ad614SDennis Dalessandro goto err_verbs_txreq;
1772f48ad614SDennis Dalessandro
1773a6cd5f08SJakub Pawlak /* Use first-port GUID as node guid */
1774a6cd5f08SJakub Pawlak ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1775a6cd5f08SJakub Pawlak
1776f48ad614SDennis Dalessandro /*
1777f48ad614SDennis Dalessandro * The system image GUID is supposed to be the same for all
1778f48ad614SDennis Dalessandro * HFIs in a single system but since there can be other
1779f48ad614SDennis Dalessandro * device types in the system, we can't be sure this is unique.
1780f48ad614SDennis Dalessandro */
1781f48ad614SDennis Dalessandro if (!ib_hfi1_sys_image_guid)
1782a6cd5f08SJakub Pawlak ib_hfi1_sys_image_guid = ibdev->node_guid;
1783f48ad614SDennis Dalessandro ibdev->phys_port_cnt = dd->num_pports;
17843067771cSBart Van Assche ibdev->dev.parent = &dd->pcidev->dev;
1785f48ad614SDennis Dalessandro
1786e3c320caSKamal Heib ib_set_device_ops(ibdev, &hfi1_dev_ops);
1787f48ad614SDennis Dalessandro
17882c34bb6dSWolfram Sang strscpy(ibdev->node_desc, init_utsname()->nodename,
1789f48ad614SDennis Dalessandro sizeof(ibdev->node_desc));
1790f48ad614SDennis Dalessandro
1791f48ad614SDennis Dalessandro /*
1792f48ad614SDennis Dalessandro * Fill in rvt info object.
1793f48ad614SDennis Dalessandro */
1794f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1795f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1796f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1797f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1798f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1799f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1800f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1801f48ad614SDennis Dalessandro /*
1802f48ad614SDennis Dalessandro * Fill in rvt info device attributes.
1803f48ad614SDennis Dalessandro */
1804f48ad614SDennis Dalessandro hfi1_fill_device_attr(dd);
1805f48ad614SDennis Dalessandro
1806f48ad614SDennis Dalessandro /* queue pair */
1807f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1808f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.qpn_start = 0;
1809f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1810f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
181184e3b19aSGary Leshner dd->verbs_dev.rdi.dparms.qpn_res_start = RVT_KDETH_QP_BASE;
181284e3b19aSGary Leshner dd->verbs_dev.rdi.dparms.qpn_res_end = RVT_AIP_QP_MAX;
1813f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1814f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1815f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1816f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
18177221403dSDasaratharaman Chandramouli dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA |
18187221403dSDasaratharaman Chandramouli RDMA_CORE_CAP_OPA_AH;
1819f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1820f48ad614SDennis Dalessandro
1821f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
18225190f052SMike Marciniszyn dd->verbs_dev.rdi.driver_f.qp_priv_init = hfi1_qp_priv_init;
1823f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1824f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1825f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1826b6eac931SMike Marciniszyn dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt;
1827f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1828f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1829f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1830f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1831f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1832f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1833f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1834f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1835f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1836f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1837f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1838f48ad614SDennis Dalessandro dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
183956acbbfbSVenkata Sandeep Dhanalakota dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc;
1840d205a06aSKaike Wan dd->verbs_dev.rdi.driver_f.setup_wqe = hfi1_setup_wqe;
18415d18ee67SSebastian Sanchez dd->verbs_dev.rdi.driver_f.comp_vect_cpu_lookup =
18425d18ee67SSebastian Sanchez hfi1_comp_vect_mappings_lookup;
1843f48ad614SDennis Dalessandro
1844f48ad614SDennis Dalessandro /* completeion queue */
18455d18ee67SSebastian Sanchez dd->verbs_dev.rdi.ibdev.num_comp_vectors = dd->comp_vect_possible_cpus;
1846f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.node = dd->node;
1847f48ad614SDennis Dalessandro
1848f48ad614SDennis Dalessandro /* misc settings */
1849f48ad614SDennis Dalessandro dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1850f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1851f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1852f48ad614SDennis Dalessandro dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1853019f118bSBrian Welty dd->verbs_dev.rdi.dparms.sge_copy_mode = sge_copy_mode;
1854019f118bSBrian Welty dd->verbs_dev.rdi.dparms.wss_threshold = wss_threshold;
1855019f118bSBrian Welty dd->verbs_dev.rdi.dparms.wss_clean_period = wss_clean_period;
185648a615dcSKaike Wan dd->verbs_dev.rdi.dparms.reserved_operations = 1;
1857f5a4a95fSKaike Wan dd->verbs_dev.rdi.dparms.extra_rdma_atomic = HFI1_TID_RDMA_WRITE_CNT;
1858f48ad614SDennis Dalessandro
18591ac57c50SMike Marciniszyn /* post send table */
18601ac57c50SMike Marciniszyn dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
18611ac57c50SMike Marciniszyn
1862116aa033SVenkata Sandeep Dhanalakota /* opcode translation table */
1863116aa033SVenkata Sandeep Dhanalakota dd->verbs_dev.rdi.wc_opcode = ib_hfi1_wc_opcode;
1864116aa033SVenkata Sandeep Dhanalakota
1865f48ad614SDennis Dalessandro ppd = dd->pport;
1866f48ad614SDennis Dalessandro for (i = 0; i < dd->num_pports; i++, ppd++)
1867f48ad614SDennis Dalessandro rvt_init_port(&dd->verbs_dev.rdi,
1868f48ad614SDennis Dalessandro &ppd->ibport_data.rvp,
1869f48ad614SDennis Dalessandro i,
1870f48ad614SDennis Dalessandro ppd->pkeys);
1871f48ad614SDennis Dalessandro
1872b9560a41SJason Gunthorpe ret = rvt_register_device(&dd->verbs_dev.rdi);
1873f48ad614SDennis Dalessandro if (ret)
1874f48ad614SDennis Dalessandro goto err_verbs_txreq;
1875f48ad614SDennis Dalessandro
1876f48ad614SDennis Dalessandro ret = hfi1_verbs_register_sysfs(dd);
1877f48ad614SDennis Dalessandro if (ret)
1878f48ad614SDennis Dalessandro goto err_class;
1879f48ad614SDennis Dalessandro
1880f48ad614SDennis Dalessandro return ret;
1881f48ad614SDennis Dalessandro
1882f48ad614SDennis Dalessandro err_class:
1883f48ad614SDennis Dalessandro rvt_unregister_device(&dd->verbs_dev.rdi);
1884f48ad614SDennis Dalessandro err_verbs_txreq:
1885f48ad614SDennis Dalessandro verbs_txreq_exit(dev);
1886f48ad614SDennis Dalessandro dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1887f48ad614SDennis Dalessandro return ret;
1888f48ad614SDennis Dalessandro }
1889f48ad614SDennis Dalessandro
hfi1_unregister_ib_device(struct hfi1_devdata * dd)1890f48ad614SDennis Dalessandro void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1891f48ad614SDennis Dalessandro {
1892f48ad614SDennis Dalessandro struct hfi1_ibdev *dev = &dd->verbs_dev;
1893f48ad614SDennis Dalessandro
1894f48ad614SDennis Dalessandro hfi1_verbs_unregister_sysfs(dd);
1895f48ad614SDennis Dalessandro
1896f48ad614SDennis Dalessandro rvt_unregister_device(&dd->verbs_dev.rdi);
1897f48ad614SDennis Dalessandro
1898f48ad614SDennis Dalessandro if (!list_empty(&dev->txwait))
1899f48ad614SDennis Dalessandro dd_dev_err(dd, "txwait list not empty!\n");
1900f48ad614SDennis Dalessandro if (!list_empty(&dev->memwait))
1901f48ad614SDennis Dalessandro dd_dev_err(dd, "memwait list not empty!\n");
1902f48ad614SDennis Dalessandro
1903f48ad614SDennis Dalessandro del_timer_sync(&dev->mem_timer);
1904f48ad614SDennis Dalessandro verbs_txreq_exit(dev);
1905b7481944SJianxin Xiong
190613f30b0fSAharon Landau kfree(dev_cntr_descs);
190713f30b0fSAharon Landau kfree(port_cntr_descs);
190813f30b0fSAharon Landau dev_cntr_descs = NULL;
190913f30b0fSAharon Landau port_cntr_descs = NULL;
1910f48ad614SDennis Dalessandro }
1911f48ad614SDennis Dalessandro
hfi1_cnp_rcv(struct hfi1_packet * packet)1912f48ad614SDennis Dalessandro void hfi1_cnp_rcv(struct hfi1_packet *packet)
1913f48ad614SDennis Dalessandro {
1914f3e862cbSSebastian Sanchez struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1915f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1916261a4351SMike Marciniszyn struct ib_header *hdr = packet->hdr;
1917f48ad614SDennis Dalessandro struct rvt_qp *qp = packet->qp;
1918f48ad614SDennis Dalessandro u32 lqpn, rqpn = 0;
1919f48ad614SDennis Dalessandro u16 rlid = 0;
1920b736a469SDasaratharaman Chandramouli u8 sl, sc5, svc_type;
1921f48ad614SDennis Dalessandro
1922f48ad614SDennis Dalessandro switch (packet->qp->ibqp.qp_type) {
1923f48ad614SDennis Dalessandro case IB_QPT_UC:
1924d8966fcdSDasaratharaman Chandramouli rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
1925f48ad614SDennis Dalessandro rqpn = qp->remote_qpn;
1926f48ad614SDennis Dalessandro svc_type = IB_CC_SVCTYPE_UC;
1927f48ad614SDennis Dalessandro break;
1928f48ad614SDennis Dalessandro case IB_QPT_RC:
1929d8966fcdSDasaratharaman Chandramouli rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
1930f48ad614SDennis Dalessandro rqpn = qp->remote_qpn;
1931f48ad614SDennis Dalessandro svc_type = IB_CC_SVCTYPE_RC;
1932f48ad614SDennis Dalessandro break;
1933f48ad614SDennis Dalessandro case IB_QPT_SMI:
1934f48ad614SDennis Dalessandro case IB_QPT_GSI:
1935f48ad614SDennis Dalessandro case IB_QPT_UD:
1936f48ad614SDennis Dalessandro svc_type = IB_CC_SVCTYPE_UD;
1937f48ad614SDennis Dalessandro break;
1938f48ad614SDennis Dalessandro default:
1939f48ad614SDennis Dalessandro ibp->rvp.n_pkt_drops++;
1940f48ad614SDennis Dalessandro return;
1941f48ad614SDennis Dalessandro }
1942f48ad614SDennis Dalessandro
1943aad559c2SDasaratharaman Chandramouli sc5 = hfi1_9B_get_sc5(hdr, packet->rhf);
1944f48ad614SDennis Dalessandro sl = ibp->sc_to_sl[sc5];
1945f48ad614SDennis Dalessandro lqpn = qp->ibqp.qp_num;
1946f48ad614SDennis Dalessandro
1947f48ad614SDennis Dalessandro process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
1948f48ad614SDennis Dalessandro }
1949