1 #ifndef _HFI1_SDMA_H 2 #define _HFI1_SDMA_H 3 /* 4 * Copyright(c) 2015 - 2018 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 #include <linux/types.h> 51 #include <linux/list.h> 52 #include <asm/byteorder.h> 53 #include <linux/workqueue.h> 54 #include <linux/rculist.h> 55 56 #include "hfi.h" 57 #include "verbs.h" 58 #include "sdma_txreq.h" 59 60 /* Hardware limit */ 61 #define MAX_DESC 64 62 /* Hardware limit for SDMA packet size */ 63 #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1) 64 65 #define SDMA_MAP_NONE 0 66 #define SDMA_MAP_SINGLE 1 67 #define SDMA_MAP_PAGE 2 68 69 #define SDMA_AHG_VALUE_MASK 0xffff 70 #define SDMA_AHG_VALUE_SHIFT 0 71 #define SDMA_AHG_INDEX_MASK 0xf 72 #define SDMA_AHG_INDEX_SHIFT 16 73 #define SDMA_AHG_FIELD_LEN_MASK 0xf 74 #define SDMA_AHG_FIELD_LEN_SHIFT 20 75 #define SDMA_AHG_FIELD_START_MASK 0x1f 76 #define SDMA_AHG_FIELD_START_SHIFT 24 77 #define SDMA_AHG_UPDATE_ENABLE_MASK 0x1 78 #define SDMA_AHG_UPDATE_ENABLE_SHIFT 31 79 80 /* AHG modes */ 81 82 /* 83 * Be aware the ordering and values 84 * for SDMA_AHG_APPLY_UPDATE[123] 85 * are assumed in generating a skip 86 * count in submit_tx() in sdma.c 87 */ 88 #define SDMA_AHG_NO_AHG 0 89 #define SDMA_AHG_COPY 1 90 #define SDMA_AHG_APPLY_UPDATE1 2 91 #define SDMA_AHG_APPLY_UPDATE2 3 92 #define SDMA_AHG_APPLY_UPDATE3 4 93 94 /* 95 * Bits defined in the send DMA descriptor. 96 */ 97 #define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63) 98 #define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62) 99 #define SDMA_DESC0_BYTE_COUNT_SHIFT 48 100 #define SDMA_DESC0_BYTE_COUNT_WIDTH 14 101 #define SDMA_DESC0_BYTE_COUNT_MASK \ 102 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1) 103 #define SDMA_DESC0_BYTE_COUNT_SMASK \ 104 (SDMA_DESC0_BYTE_COUNT_MASK << SDMA_DESC0_BYTE_COUNT_SHIFT) 105 #define SDMA_DESC0_PHY_ADDR_SHIFT 0 106 #define SDMA_DESC0_PHY_ADDR_WIDTH 48 107 #define SDMA_DESC0_PHY_ADDR_MASK \ 108 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1) 109 #define SDMA_DESC0_PHY_ADDR_SMASK \ 110 (SDMA_DESC0_PHY_ADDR_MASK << SDMA_DESC0_PHY_ADDR_SHIFT) 111 112 #define SDMA_DESC1_HEADER_UPDATE1_SHIFT 32 113 #define SDMA_DESC1_HEADER_UPDATE1_WIDTH 32 114 #define SDMA_DESC1_HEADER_UPDATE1_MASK \ 115 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1) 116 #define SDMA_DESC1_HEADER_UPDATE1_SMASK \ 117 (SDMA_DESC1_HEADER_UPDATE1_MASK << SDMA_DESC1_HEADER_UPDATE1_SHIFT) 118 #define SDMA_DESC1_HEADER_MODE_SHIFT 13 119 #define SDMA_DESC1_HEADER_MODE_WIDTH 3 120 #define SDMA_DESC1_HEADER_MODE_MASK \ 121 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1) 122 #define SDMA_DESC1_HEADER_MODE_SMASK \ 123 (SDMA_DESC1_HEADER_MODE_MASK << SDMA_DESC1_HEADER_MODE_SHIFT) 124 #define SDMA_DESC1_HEADER_INDEX_SHIFT 8 125 #define SDMA_DESC1_HEADER_INDEX_WIDTH 5 126 #define SDMA_DESC1_HEADER_INDEX_MASK \ 127 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1) 128 #define SDMA_DESC1_HEADER_INDEX_SMASK \ 129 (SDMA_DESC1_HEADER_INDEX_MASK << SDMA_DESC1_HEADER_INDEX_SHIFT) 130 #define SDMA_DESC1_HEADER_DWS_SHIFT 4 131 #define SDMA_DESC1_HEADER_DWS_WIDTH 4 132 #define SDMA_DESC1_HEADER_DWS_MASK \ 133 ((1ULL << SDMA_DESC1_HEADER_DWS_WIDTH) - 1) 134 #define SDMA_DESC1_HEADER_DWS_SMASK \ 135 (SDMA_DESC1_HEADER_DWS_MASK << SDMA_DESC1_HEADER_DWS_SHIFT) 136 #define SDMA_DESC1_GENERATION_SHIFT 2 137 #define SDMA_DESC1_GENERATION_WIDTH 2 138 #define SDMA_DESC1_GENERATION_MASK \ 139 ((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1) 140 #define SDMA_DESC1_GENERATION_SMASK \ 141 (SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT) 142 #define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1) 143 #define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0) 144 145 enum sdma_states { 146 sdma_state_s00_hw_down, 147 sdma_state_s10_hw_start_up_halt_wait, 148 sdma_state_s15_hw_start_up_clean_wait, 149 sdma_state_s20_idle, 150 sdma_state_s30_sw_clean_up_wait, 151 sdma_state_s40_hw_clean_up_wait, 152 sdma_state_s50_hw_halt_wait, 153 sdma_state_s60_idle_halt_wait, 154 sdma_state_s80_hw_freeze, 155 sdma_state_s82_freeze_sw_clean, 156 sdma_state_s99_running, 157 }; 158 159 enum sdma_events { 160 sdma_event_e00_go_hw_down, 161 sdma_event_e10_go_hw_start, 162 sdma_event_e15_hw_halt_done, 163 sdma_event_e25_hw_clean_up_done, 164 sdma_event_e30_go_running, 165 sdma_event_e40_sw_cleaned, 166 sdma_event_e50_hw_cleaned, 167 sdma_event_e60_hw_halted, 168 sdma_event_e70_go_idle, 169 sdma_event_e80_hw_freeze, 170 sdma_event_e81_hw_frozen, 171 sdma_event_e82_hw_unfreeze, 172 sdma_event_e85_link_down, 173 sdma_event_e90_sw_halted, 174 }; 175 176 struct sdma_set_state_action { 177 unsigned op_enable:1; 178 unsigned op_intenable:1; 179 unsigned op_halt:1; 180 unsigned op_cleanup:1; 181 unsigned go_s99_running_tofalse:1; 182 unsigned go_s99_running_totrue:1; 183 }; 184 185 struct sdma_state { 186 struct kref kref; 187 struct completion comp; 188 enum sdma_states current_state; 189 unsigned current_op; 190 unsigned go_s99_running; 191 /* debugging/development */ 192 enum sdma_states previous_state; 193 unsigned previous_op; 194 enum sdma_events last_event; 195 }; 196 197 /** 198 * DOC: sdma exported routines 199 * 200 * These sdma routines fit into three categories: 201 * - The SDMA API for building and submitting packets 202 * to the ring 203 * 204 * - Initialization and tear down routines to buildup 205 * and tear down SDMA 206 * 207 * - ISR entrances to handle interrupts, state changes 208 * and errors 209 */ 210 211 /** 212 * DOC: sdma PSM/verbs API 213 * 214 * The sdma API is designed to be used by both PSM 215 * and verbs to supply packets to the SDMA ring. 216 * 217 * The usage of the API is as follows: 218 * 219 * Embed a struct iowait in the QP or 220 * PQ. The iowait should be initialized with a 221 * call to iowait_init(). 222 * 223 * The user of the API should create an allocation method 224 * for their version of the txreq. slabs, pre-allocated lists, 225 * and dma pools can be used. Once the user's overload of 226 * the sdma_txreq has been allocated, the sdma_txreq member 227 * must be initialized with sdma_txinit() or sdma_txinit_ahg(). 228 * 229 * The txreq must be declared with the sdma_txreq first. 230 * 231 * The tx request, once initialized, is manipulated with calls to 232 * sdma_txadd_daddr(), sdma_txadd_page(), or sdma_txadd_kvaddr() 233 * for each disjoint memory location. It is the user's responsibility 234 * to understand the packet boundaries and page boundaries to do the 235 * appropriate number of sdma_txadd_* calls.. The user 236 * must be prepared to deal with failures from these routines due to 237 * either memory allocation or dma_mapping failures. 238 * 239 * The mapping specifics for each memory location are recorded 240 * in the tx. Memory locations added with sdma_txadd_page() 241 * and sdma_txadd_kvaddr() are automatically mapped when added 242 * to the tx and nmapped as part of the progress processing in the 243 * SDMA interrupt handling. 244 * 245 * sdma_txadd_daddr() is used to add an dma_addr_t memory to the 246 * tx. An example of a use case would be a pre-allocated 247 * set of headers allocated via dma_pool_alloc() or 248 * dma_alloc_coherent(). For these memory locations, it 249 * is the responsibility of the user to handle that unmapping. 250 * (This would usually be at an unload or job termination.) 251 * 252 * The routine sdma_send_txreq() is used to submit 253 * a tx to the ring after the appropriate number of 254 * sdma_txadd_* have been done. 255 * 256 * If it is desired to send a burst of sdma_txreqs, sdma_send_txlist() 257 * can be used to submit a list of packets. 258 * 259 * The user is free to use the link overhead in the struct sdma_txreq as 260 * long as the tx isn't in flight. 261 * 262 * The extreme degenerate case of the number of descriptors 263 * exceeding the ring size is automatically handled as 264 * memory locations are added. An overflow of the descriptor 265 * array that is part of the sdma_txreq is also automatically 266 * handled. 267 * 268 */ 269 270 /** 271 * DOC: Infrastructure calls 272 * 273 * sdma_init() is used to initialize data structures and 274 * CSRs for the desired number of SDMA engines. 275 * 276 * sdma_start() is used to kick the SDMA engines initialized 277 * with sdma_init(). Interrupts must be enabled at this 278 * point since aspects of the state machine are interrupt 279 * driven. 280 * 281 * sdma_engine_error() and sdma_engine_interrupt() are 282 * entrances for interrupts. 283 * 284 * sdma_map_init() is for the management of the mapping 285 * table when the number of vls is changed. 286 * 287 */ 288 289 /* 290 * struct hw_sdma_desc - raw 128 bit SDMA descriptor 291 * 292 * This is the raw descriptor in the SDMA ring 293 */ 294 struct hw_sdma_desc { 295 /* private: don't use directly */ 296 __le64 qw[2]; 297 }; 298 299 /** 300 * struct sdma_engine - Data pertaining to each SDMA engine. 301 * @dd: a back-pointer to the device data 302 * @ppd: per port back-pointer 303 * @imask: mask for irq manipulation 304 * @idle_mask: mask for determining if an interrupt is due to sdma_idle 305 * 306 * This structure has the state for each sdma_engine. 307 * 308 * Accessing to non public fields are not supported 309 * since the private members are subject to change. 310 */ 311 struct sdma_engine { 312 /* read mostly */ 313 struct hfi1_devdata *dd; 314 struct hfi1_pportdata *ppd; 315 /* private: */ 316 void __iomem *tail_csr; 317 u64 imask; /* clear interrupt mask */ 318 u64 idle_mask; 319 u64 progress_mask; 320 u64 int_mask; 321 /* private: */ 322 volatile __le64 *head_dma; /* DMA'ed by chip */ 323 /* private: */ 324 dma_addr_t head_phys; 325 /* private: */ 326 struct hw_sdma_desc *descq; 327 /* private: */ 328 unsigned descq_full_count; 329 struct sdma_txreq **tx_ring; 330 /* private: */ 331 dma_addr_t descq_phys; 332 /* private */ 333 u32 sdma_mask; 334 /* private */ 335 struct sdma_state state; 336 /* private */ 337 int cpu; 338 /* private: */ 339 u8 sdma_shift; 340 /* private: */ 341 u8 this_idx; /* zero relative engine */ 342 /* protect changes to senddmactrl shadow */ 343 spinlock_t senddmactrl_lock; 344 /* private: */ 345 u64 p_senddmactrl; /* shadow per-engine SendDmaCtrl */ 346 347 /* read/write using tail_lock */ 348 spinlock_t tail_lock ____cacheline_aligned_in_smp; 349 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 350 /* private: */ 351 u64 tail_sn; 352 #endif 353 /* private: */ 354 u32 descq_tail; 355 /* private: */ 356 unsigned long ahg_bits; 357 /* private: */ 358 u16 desc_avail; 359 /* private: */ 360 u16 tx_tail; 361 /* private: */ 362 u16 descq_cnt; 363 364 /* read/write using head_lock */ 365 /* private: */ 366 seqlock_t head_lock ____cacheline_aligned_in_smp; 367 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 368 /* private: */ 369 u64 head_sn; 370 #endif 371 /* private: */ 372 u32 descq_head; 373 /* private: */ 374 u16 tx_head; 375 /* private: */ 376 u64 last_status; 377 /* private */ 378 u64 err_cnt; 379 /* private */ 380 u64 sdma_int_cnt; 381 u64 idle_int_cnt; 382 u64 progress_int_cnt; 383 384 /* private: */ 385 struct list_head dmawait; 386 387 /* CONFIG SDMA for now, just blindly duplicate */ 388 /* private: */ 389 struct tasklet_struct sdma_hw_clean_up_task 390 ____cacheline_aligned_in_smp; 391 392 /* private: */ 393 struct tasklet_struct sdma_sw_clean_up_task 394 ____cacheline_aligned_in_smp; 395 /* private: */ 396 struct work_struct err_halt_worker; 397 /* private */ 398 struct timer_list err_progress_check_timer; 399 u32 progress_check_head; 400 /* private: */ 401 struct work_struct flush_worker; 402 /* protect flush list */ 403 spinlock_t flushlist_lock; 404 /* private: */ 405 struct list_head flushlist; 406 struct cpumask cpu_mask; 407 struct kobject kobj; 408 u32 msix_intr; 409 }; 410 411 int sdma_init(struct hfi1_devdata *dd, u8 port); 412 void sdma_start(struct hfi1_devdata *dd); 413 void sdma_exit(struct hfi1_devdata *dd); 414 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines); 415 void sdma_all_running(struct hfi1_devdata *dd); 416 void sdma_all_idle(struct hfi1_devdata *dd); 417 void sdma_freeze_notify(struct hfi1_devdata *dd, int go_idle); 418 void sdma_freeze(struct hfi1_devdata *dd); 419 void sdma_unfreeze(struct hfi1_devdata *dd); 420 void sdma_wait(struct hfi1_devdata *dd); 421 422 /** 423 * sdma_empty() - idle engine test 424 * @engine: sdma engine 425 * 426 * Currently used by verbs as a latency optimization. 427 * 428 * Return: 429 * 1 - empty, 0 - non-empty 430 */ 431 static inline int sdma_empty(struct sdma_engine *sde) 432 { 433 return sde->descq_tail == sde->descq_head; 434 } 435 436 static inline u16 sdma_descq_freecnt(struct sdma_engine *sde) 437 { 438 return sde->descq_cnt - 439 (sde->descq_tail - 440 READ_ONCE(sde->descq_head)) - 1; 441 } 442 443 static inline u16 sdma_descq_inprocess(struct sdma_engine *sde) 444 { 445 return sde->descq_cnt - sdma_descq_freecnt(sde); 446 } 447 448 /* 449 * Either head_lock or tail lock required to see 450 * a steady state. 451 */ 452 static inline int __sdma_running(struct sdma_engine *engine) 453 { 454 return engine->state.current_state == sdma_state_s99_running; 455 } 456 457 /** 458 * sdma_running() - state suitability test 459 * @engine: sdma engine 460 * 461 * sdma_running probes the internal state to determine if it is suitable 462 * for submitting packets. 463 * 464 * Return: 465 * 1 - ok to submit, 0 - not ok to submit 466 * 467 */ 468 static inline int sdma_running(struct sdma_engine *engine) 469 { 470 unsigned long flags; 471 int ret; 472 473 spin_lock_irqsave(&engine->tail_lock, flags); 474 ret = __sdma_running(engine); 475 spin_unlock_irqrestore(&engine->tail_lock, flags); 476 return ret; 477 } 478 479 void _sdma_txreq_ahgadd( 480 struct sdma_txreq *tx, 481 u8 num_ahg, 482 u8 ahg_entry, 483 u32 *ahg, 484 u8 ahg_hlen); 485 486 /** 487 * sdma_txinit_ahg() - initialize an sdma_txreq struct with AHG 488 * @tx: tx request to initialize 489 * @flags: flags to key last descriptor additions 490 * @tlen: total packet length (pbc + headers + data) 491 * @ahg_entry: ahg entry to use (0 - 31) 492 * @num_ahg: ahg descriptor for first descriptor (0 - 9) 493 * @ahg: array of AHG descriptors (up to 9 entries) 494 * @ahg_hlen: number of bytes from ASIC entry to use 495 * @cb: callback 496 * 497 * The allocation of the sdma_txreq and it enclosing structure is user 498 * dependent. This routine must be called to initialize the user independent 499 * fields. 500 * 501 * The currently supported flags are SDMA_TXREQ_F_URGENT, 502 * SDMA_TXREQ_F_AHG_COPY, and SDMA_TXREQ_F_USE_AHG. 503 * 504 * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the 505 * completion is desired as soon as possible. 506 * 507 * SDMA_TXREQ_F_AHG_COPY causes the header in the first descriptor to be 508 * copied to chip entry. SDMA_TXREQ_F_USE_AHG causes the code to add in 509 * the AHG descriptors into the first 1 to 3 descriptors. 510 * 511 * Completions of submitted requests can be gotten on selected 512 * txreqs by giving a completion routine callback to sdma_txinit() or 513 * sdma_txinit_ahg(). The environment in which the callback runs 514 * can be from an ISR, a tasklet, or a thread, so no sleeping 515 * kernel routines can be used. Aspects of the sdma ring may 516 * be locked so care should be taken with locking. 517 * 518 * The callback pointer can be NULL to avoid any callback for the packet 519 * being submitted. The callback will be provided this tx, a status, and a flag. 520 * 521 * The status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR, 522 * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN. 523 * 524 * The flag, if the is the iowait had been used, indicates the iowait 525 * sdma_busy count has reached zero. 526 * 527 * user data portion of tlen should be precise. The sdma_txadd_* entrances 528 * will pad with a descriptor references 1 - 3 bytes when the number of bytes 529 * specified in tlen have been supplied to the sdma_txreq. 530 * 531 * ahg_hlen is used to determine the number of on-chip entry bytes to 532 * use as the header. This is for cases where the stored header is 533 * larger than the header to be used in a packet. This is typical 534 * for verbs where an RDMA_WRITE_FIRST is larger than the packet in 535 * and RDMA_WRITE_MIDDLE. 536 * 537 */ 538 static inline int sdma_txinit_ahg( 539 struct sdma_txreq *tx, 540 u16 flags, 541 u16 tlen, 542 u8 ahg_entry, 543 u8 num_ahg, 544 u32 *ahg, 545 u8 ahg_hlen, 546 void (*cb)(struct sdma_txreq *, int)) 547 { 548 if (tlen == 0) 549 return -ENODATA; 550 if (tlen > MAX_SDMA_PKT_SIZE) 551 return -EMSGSIZE; 552 tx->desc_limit = ARRAY_SIZE(tx->descs); 553 tx->descp = &tx->descs[0]; 554 INIT_LIST_HEAD(&tx->list); 555 tx->num_desc = 0; 556 tx->flags = flags; 557 tx->complete = cb; 558 tx->coalesce_buf = NULL; 559 tx->wait = NULL; 560 tx->packet_len = tlen; 561 tx->tlen = tx->packet_len; 562 tx->descs[0].qw[0] = SDMA_DESC0_FIRST_DESC_FLAG; 563 tx->descs[0].qw[1] = 0; 564 if (flags & SDMA_TXREQ_F_AHG_COPY) 565 tx->descs[0].qw[1] |= 566 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK) 567 << SDMA_DESC1_HEADER_INDEX_SHIFT) | 568 (((u64)SDMA_AHG_COPY & SDMA_DESC1_HEADER_MODE_MASK) 569 << SDMA_DESC1_HEADER_MODE_SHIFT); 570 else if (flags & SDMA_TXREQ_F_USE_AHG && num_ahg) 571 _sdma_txreq_ahgadd(tx, num_ahg, ahg_entry, ahg, ahg_hlen); 572 return 0; 573 } 574 575 /** 576 * sdma_txinit() - initialize an sdma_txreq struct (no AHG) 577 * @tx: tx request to initialize 578 * @flags: flags to key last descriptor additions 579 * @tlen: total packet length (pbc + headers + data) 580 * @cb: callback pointer 581 * 582 * The allocation of the sdma_txreq and it enclosing structure is user 583 * dependent. This routine must be called to initialize the user 584 * independent fields. 585 * 586 * The currently supported flags is SDMA_TXREQ_F_URGENT. 587 * 588 * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the 589 * completion is desired as soon as possible. 590 * 591 * Completions of submitted requests can be gotten on selected 592 * txreqs by giving a completion routine callback to sdma_txinit() or 593 * sdma_txinit_ahg(). The environment in which the callback runs 594 * can be from an ISR, a tasklet, or a thread, so no sleeping 595 * kernel routines can be used. The head size of the sdma ring may 596 * be locked so care should be taken with locking. 597 * 598 * The callback pointer can be NULL to avoid any callback for the packet 599 * being submitted. 600 * 601 * The callback, if non-NULL, will be provided this tx and a status. The 602 * status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR, 603 * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN. 604 * 605 */ 606 static inline int sdma_txinit( 607 struct sdma_txreq *tx, 608 u16 flags, 609 u16 tlen, 610 void (*cb)(struct sdma_txreq *, int)) 611 { 612 return sdma_txinit_ahg(tx, flags, tlen, 0, 0, NULL, 0, cb); 613 } 614 615 /* helpers - don't use */ 616 static inline int sdma_mapping_type(struct sdma_desc *d) 617 { 618 return (d->qw[1] & SDMA_DESC1_GENERATION_SMASK) 619 >> SDMA_DESC1_GENERATION_SHIFT; 620 } 621 622 static inline size_t sdma_mapping_len(struct sdma_desc *d) 623 { 624 return (d->qw[0] & SDMA_DESC0_BYTE_COUNT_SMASK) 625 >> SDMA_DESC0_BYTE_COUNT_SHIFT; 626 } 627 628 static inline dma_addr_t sdma_mapping_addr(struct sdma_desc *d) 629 { 630 return (d->qw[0] & SDMA_DESC0_PHY_ADDR_SMASK) 631 >> SDMA_DESC0_PHY_ADDR_SHIFT; 632 } 633 634 static inline void make_tx_sdma_desc( 635 struct sdma_txreq *tx, 636 int type, 637 dma_addr_t addr, 638 size_t len) 639 { 640 struct sdma_desc *desc = &tx->descp[tx->num_desc]; 641 642 if (!tx->num_desc) { 643 /* qw[0] zero; qw[1] first, ahg mode already in from init */ 644 desc->qw[1] |= ((u64)type & SDMA_DESC1_GENERATION_MASK) 645 << SDMA_DESC1_GENERATION_SHIFT; 646 } else { 647 desc->qw[0] = 0; 648 desc->qw[1] = ((u64)type & SDMA_DESC1_GENERATION_MASK) 649 << SDMA_DESC1_GENERATION_SHIFT; 650 } 651 desc->qw[0] |= (((u64)addr & SDMA_DESC0_PHY_ADDR_MASK) 652 << SDMA_DESC0_PHY_ADDR_SHIFT) | 653 (((u64)len & SDMA_DESC0_BYTE_COUNT_MASK) 654 << SDMA_DESC0_BYTE_COUNT_SHIFT); 655 } 656 657 /* helper to extend txreq */ 658 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx, 659 int type, void *kvaddr, struct page *page, 660 unsigned long offset, u16 len); 661 int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *); 662 void __sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *); 663 664 static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx) 665 { 666 if (tx->num_desc) 667 __sdma_txclean(dd, tx); 668 } 669 670 /* helpers used by public routines */ 671 static inline void _sdma_close_tx(struct hfi1_devdata *dd, 672 struct sdma_txreq *tx) 673 { 674 tx->descp[tx->num_desc].qw[0] |= 675 SDMA_DESC0_LAST_DESC_FLAG; 676 tx->descp[tx->num_desc].qw[1] |= 677 dd->default_desc1; 678 if (tx->flags & SDMA_TXREQ_F_URGENT) 679 tx->descp[tx->num_desc].qw[1] |= 680 (SDMA_DESC1_HEAD_TO_HOST_FLAG | 681 SDMA_DESC1_INT_REQ_FLAG); 682 } 683 684 static inline int _sdma_txadd_daddr( 685 struct hfi1_devdata *dd, 686 int type, 687 struct sdma_txreq *tx, 688 dma_addr_t addr, 689 u16 len) 690 { 691 int rval = 0; 692 693 make_tx_sdma_desc( 694 tx, 695 type, 696 addr, len); 697 WARN_ON(len > tx->tlen); 698 tx->tlen -= len; 699 /* special cases for last */ 700 if (!tx->tlen) { 701 if (tx->packet_len & (sizeof(u32) - 1)) { 702 rval = _pad_sdma_tx_descs(dd, tx); 703 if (rval) 704 return rval; 705 } else { 706 _sdma_close_tx(dd, tx); 707 } 708 } 709 tx->num_desc++; 710 return rval; 711 } 712 713 /** 714 * sdma_txadd_page() - add a page to the sdma_txreq 715 * @dd: the device to use for mapping 716 * @tx: tx request to which the page is added 717 * @page: page to map 718 * @offset: offset within the page 719 * @len: length in bytes 720 * 721 * This is used to add a page/offset/length descriptor. 722 * 723 * The mapping/unmapping of the page/offset/len is automatically handled. 724 * 725 * Return: 726 * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't 727 * extend/coalesce descriptor array 728 */ 729 static inline int sdma_txadd_page( 730 struct hfi1_devdata *dd, 731 struct sdma_txreq *tx, 732 struct page *page, 733 unsigned long offset, 734 u16 len) 735 { 736 dma_addr_t addr; 737 int rval; 738 739 if ((unlikely(tx->num_desc == tx->desc_limit))) { 740 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_PAGE, 741 NULL, page, offset, len); 742 if (rval <= 0) 743 return rval; 744 } 745 746 addr = dma_map_page( 747 &dd->pcidev->dev, 748 page, 749 offset, 750 len, 751 DMA_TO_DEVICE); 752 753 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 754 __sdma_txclean(dd, tx); 755 return -ENOSPC; 756 } 757 758 return _sdma_txadd_daddr( 759 dd, SDMA_MAP_PAGE, tx, addr, len); 760 } 761 762 /** 763 * sdma_txadd_daddr() - add a dma address to the sdma_txreq 764 * @dd: the device to use for mapping 765 * @tx: sdma_txreq to which the page is added 766 * @addr: dma address mapped by caller 767 * @len: length in bytes 768 * 769 * This is used to add a descriptor for memory that is already dma mapped. 770 * 771 * In this case, there is no unmapping as part of the progress processing for 772 * this memory location. 773 * 774 * Return: 775 * 0 - success, -ENOMEM - couldn't extend descriptor array 776 */ 777 778 static inline int sdma_txadd_daddr( 779 struct hfi1_devdata *dd, 780 struct sdma_txreq *tx, 781 dma_addr_t addr, 782 u16 len) 783 { 784 int rval; 785 786 if ((unlikely(tx->num_desc == tx->desc_limit))) { 787 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_NONE, 788 NULL, NULL, 0, 0); 789 if (rval <= 0) 790 return rval; 791 } 792 793 return _sdma_txadd_daddr(dd, SDMA_MAP_NONE, tx, addr, len); 794 } 795 796 /** 797 * sdma_txadd_kvaddr() - add a kernel virtual address to sdma_txreq 798 * @dd: the device to use for mapping 799 * @tx: sdma_txreq to which the page is added 800 * @kvaddr: the kernel virtual address 801 * @len: length in bytes 802 * 803 * This is used to add a descriptor referenced by the indicated kvaddr and 804 * len. 805 * 806 * The mapping/unmapping of the kvaddr and len is automatically handled. 807 * 808 * Return: 809 * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't extend/coalesce 810 * descriptor array 811 */ 812 static inline int sdma_txadd_kvaddr( 813 struct hfi1_devdata *dd, 814 struct sdma_txreq *tx, 815 void *kvaddr, 816 u16 len) 817 { 818 dma_addr_t addr; 819 int rval; 820 821 if ((unlikely(tx->num_desc == tx->desc_limit))) { 822 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_SINGLE, 823 kvaddr, NULL, 0, len); 824 if (rval <= 0) 825 return rval; 826 } 827 828 addr = dma_map_single( 829 &dd->pcidev->dev, 830 kvaddr, 831 len, 832 DMA_TO_DEVICE); 833 834 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 835 __sdma_txclean(dd, tx); 836 return -ENOSPC; 837 } 838 839 return _sdma_txadd_daddr( 840 dd, SDMA_MAP_SINGLE, tx, addr, len); 841 } 842 843 struct iowait_work; 844 845 int sdma_send_txreq(struct sdma_engine *sde, 846 struct iowait_work *wait, 847 struct sdma_txreq *tx, 848 bool pkts_sent); 849 int sdma_send_txlist(struct sdma_engine *sde, 850 struct iowait_work *wait, 851 struct list_head *tx_list, 852 u16 *count_out); 853 854 int sdma_ahg_alloc(struct sdma_engine *sde); 855 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index); 856 857 /** 858 * sdma_build_ahg - build ahg descriptor 859 * @data 860 * @dwindex 861 * @startbit 862 * @bits 863 * 864 * Build and return a 32 bit descriptor. 865 */ 866 static inline u32 sdma_build_ahg_descriptor( 867 u16 data, 868 u8 dwindex, 869 u8 startbit, 870 u8 bits) 871 { 872 return (u32)(1UL << SDMA_AHG_UPDATE_ENABLE_SHIFT | 873 ((startbit & SDMA_AHG_FIELD_START_MASK) << 874 SDMA_AHG_FIELD_START_SHIFT) | 875 ((bits & SDMA_AHG_FIELD_LEN_MASK) << 876 SDMA_AHG_FIELD_LEN_SHIFT) | 877 ((dwindex & SDMA_AHG_INDEX_MASK) << 878 SDMA_AHG_INDEX_SHIFT) | 879 ((data & SDMA_AHG_VALUE_MASK) << 880 SDMA_AHG_VALUE_SHIFT)); 881 } 882 883 /** 884 * sdma_progress - use seq number of detect head progress 885 * @sde: sdma_engine to check 886 * @seq: base seq count 887 * @tx: txreq for which we need to check descriptor availability 888 * 889 * This is used in the appropriate spot in the sleep routine 890 * to check for potential ring progress. This routine gets the 891 * seqcount before queuing the iowait structure for progress. 892 * 893 * If the seqcount indicates that progress needs to be checked, 894 * re-submission is detected by checking whether the descriptor 895 * queue has enough descriptor for the txreq. 896 */ 897 static inline unsigned sdma_progress(struct sdma_engine *sde, unsigned seq, 898 struct sdma_txreq *tx) 899 { 900 if (read_seqretry(&sde->head_lock, seq)) { 901 sde->desc_avail = sdma_descq_freecnt(sde); 902 if (tx->num_desc > sde->desc_avail) 903 return 0; 904 return 1; 905 } 906 return 0; 907 } 908 909 /** 910 * sdma_iowait_schedule() - initialize wait structure 911 * @sde: sdma_engine to schedule 912 * @wait: wait struct to schedule 913 * 914 * This function initializes the iowait 915 * structure embedded in the QP or PQ. 916 * 917 */ 918 static inline void sdma_iowait_schedule( 919 struct sdma_engine *sde, 920 struct iowait *wait) 921 { 922 struct hfi1_pportdata *ppd = sde->dd->pport; 923 924 iowait_schedule(wait, ppd->hfi1_wq, sde->cpu); 925 } 926 927 /* for use by interrupt handling */ 928 void sdma_engine_error(struct sdma_engine *sde, u64 status); 929 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status); 930 931 /* 932 * 933 * The diagram below details the relationship of the mapping structures 934 * 935 * Since the mapping now allows for non-uniform engines per vl, the 936 * number of engines for a vl is either the vl_engines[vl] or 937 * a computation based on num_sdma/num_vls: 938 * 939 * For example: 940 * nactual = vl_engines ? vl_engines[vl] : num_sdma/num_vls 941 * 942 * n = roundup to next highest power of 2 using nactual 943 * 944 * In the case where there are num_sdma/num_vls doesn't divide 945 * evenly, the extras are added from the last vl downward. 946 * 947 * For the case where n > nactual, the engines are assigned 948 * in a round robin fashion wrapping back to the first engine 949 * for a particular vl. 950 * 951 * dd->sdma_map 952 * | sdma_map_elem[0] 953 * | +--------------------+ 954 * v | mask | 955 * sdma_vl_map |--------------------| 956 * +--------------------------+ | sde[0] -> eng 1 | 957 * | list (RCU) | |--------------------| 958 * |--------------------------| ->| sde[1] -> eng 2 | 959 * | mask | --/ |--------------------| 960 * |--------------------------| -/ | * | 961 * | actual_vls (max 8) | -/ |--------------------| 962 * |--------------------------| --/ | sde[n-1] -> eng n | 963 * | vls (max 8) | -/ +--------------------+ 964 * |--------------------------| --/ 965 * | map[0] |-/ 966 * |--------------------------| +---------------------+ 967 * | map[1] |--- | mask | 968 * |--------------------------| \---- |---------------------| 969 * | * | \-- | sde[0] -> eng 1+n | 970 * | * | \---- |---------------------| 971 * | * | \->| sde[1] -> eng 2+n | 972 * |--------------------------| |---------------------| 973 * | map[vls - 1] |- | * | 974 * +--------------------------+ \- |---------------------| 975 * \- | sde[m-1] -> eng m+n | 976 * \ +---------------------+ 977 * \- 978 * \ 979 * \- +----------------------+ 980 * \- | mask | 981 * \ |----------------------| 982 * \- | sde[0] -> eng 1+m+n | 983 * \- |----------------------| 984 * >| sde[1] -> eng 2+m+n | 985 * |----------------------| 986 * | * | 987 * |----------------------| 988 * | sde[o-1] -> eng o+m+n| 989 * +----------------------+ 990 * 991 */ 992 993 /** 994 * struct sdma_map_elem - mapping for a vl 995 * @mask - selector mask 996 * @sde - array of engines for this vl 997 * 998 * The mask is used to "mod" the selector 999 * to produce index into the trailing 1000 * array of sdes. 1001 */ 1002 struct sdma_map_elem { 1003 u32 mask; 1004 struct sdma_engine *sde[0]; 1005 }; 1006 1007 /** 1008 * struct sdma_map_el - mapping for a vl 1009 * @engine_to_vl - map of an engine to a vl 1010 * @list - rcu head for free callback 1011 * @mask - vl mask to "mod" the vl to produce an index to map array 1012 * @actual_vls - number of vls 1013 * @vls - number of vls rounded to next power of 2 1014 * @map - array of sdma_map_elem entries 1015 * 1016 * This is the parent mapping structure. The trailing 1017 * members of the struct point to sdma_map_elem entries, which 1018 * in turn point to an array of sde's for that vl. 1019 */ 1020 struct sdma_vl_map { 1021 s8 engine_to_vl[TXE_NUM_SDMA_ENGINES]; 1022 struct rcu_head list; 1023 u32 mask; 1024 u8 actual_vls; 1025 u8 vls; 1026 struct sdma_map_elem *map[0]; 1027 }; 1028 1029 int sdma_map_init( 1030 struct hfi1_devdata *dd, 1031 u8 port, 1032 u8 num_vls, 1033 u8 *vl_engines); 1034 1035 /* slow path */ 1036 void _sdma_engine_progress_schedule(struct sdma_engine *sde); 1037 1038 /** 1039 * sdma_engine_progress_schedule() - schedule progress on engine 1040 * @sde: sdma_engine to schedule progress 1041 * 1042 * This is the fast path. 1043 * 1044 */ 1045 static inline void sdma_engine_progress_schedule( 1046 struct sdma_engine *sde) 1047 { 1048 if (!sde || sdma_descq_inprocess(sde) < (sde->descq_cnt / 8)) 1049 return; 1050 _sdma_engine_progress_schedule(sde); 1051 } 1052 1053 struct sdma_engine *sdma_select_engine_sc( 1054 struct hfi1_devdata *dd, 1055 u32 selector, 1056 u8 sc5); 1057 1058 struct sdma_engine *sdma_select_engine_vl( 1059 struct hfi1_devdata *dd, 1060 u32 selector, 1061 u8 vl); 1062 1063 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd, 1064 u32 selector, u8 vl); 1065 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf); 1066 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf, 1067 size_t count); 1068 int sdma_engine_get_vl(struct sdma_engine *sde); 1069 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *); 1070 void sdma_seqfile_dump_cpu_list(struct seq_file *s, struct hfi1_devdata *dd, 1071 unsigned long cpuid); 1072 1073 #ifdef CONFIG_SDMA_VERBOSITY 1074 void sdma_dumpstate(struct sdma_engine *); 1075 #endif 1076 static inline char *slashstrip(char *s) 1077 { 1078 char *r = s; 1079 1080 while (*s) 1081 if (*s++ == '/') 1082 r = s; 1083 return r; 1084 } 1085 1086 u16 sdma_get_descq_cnt(void); 1087 1088 extern uint mod_num_sdma; 1089 1090 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid); 1091 1092 #endif 1093