1 /* 2 * Copyright(c) 2015, 2016 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/spinlock.h> 49 #include <linux/seqlock.h> 50 #include <linux/netdevice.h> 51 #include <linux/moduleparam.h> 52 #include <linux/bitops.h> 53 #include <linux/timer.h> 54 #include <linux/vmalloc.h> 55 #include <linux/highmem.h> 56 57 #include "hfi.h" 58 #include "common.h" 59 #include "qp.h" 60 #include "sdma.h" 61 #include "iowait.h" 62 #include "trace.h" 63 64 /* must be a power of 2 >= 64 <= 32768 */ 65 #define SDMA_DESCQ_CNT 2048 66 #define SDMA_DESC_INTR 64 67 #define INVALID_TAIL 0xffff 68 69 static uint sdma_descq_cnt = SDMA_DESCQ_CNT; 70 module_param(sdma_descq_cnt, uint, S_IRUGO); 71 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries"); 72 73 static uint sdma_idle_cnt = 250; 74 module_param(sdma_idle_cnt, uint, S_IRUGO); 75 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)"); 76 77 uint mod_num_sdma; 78 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO); 79 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use"); 80 81 static uint sdma_desct_intr = SDMA_DESC_INTR; 82 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR); 83 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt"); 84 85 #define SDMA_WAIT_BATCH_SIZE 20 86 /* max wait time for a SDMA engine to indicate it has halted */ 87 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */ 88 /* all SDMA engine errors that cause a halt */ 89 90 #define SD(name) SEND_DMA_##name 91 #define ALL_SDMA_ENG_HALT_ERRS \ 92 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \ 93 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \ 94 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \ 95 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \ 96 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \ 97 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \ 98 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \ 99 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \ 100 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \ 101 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \ 102 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \ 103 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \ 104 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \ 105 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \ 106 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \ 107 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \ 108 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \ 109 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK)) 110 111 /* sdma_sendctrl operations */ 112 #define SDMA_SENDCTRL_OP_ENABLE BIT(0) 113 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1) 114 #define SDMA_SENDCTRL_OP_HALT BIT(2) 115 #define SDMA_SENDCTRL_OP_CLEANUP BIT(3) 116 117 /* handle long defines */ 118 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \ 119 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK 120 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \ 121 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT 122 123 static const char * const sdma_state_names[] = { 124 [sdma_state_s00_hw_down] = "s00_HwDown", 125 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait", 126 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait", 127 [sdma_state_s20_idle] = "s20_Idle", 128 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait", 129 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait", 130 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait", 131 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait", 132 [sdma_state_s80_hw_freeze] = "s80_HwFreeze", 133 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean", 134 [sdma_state_s99_running] = "s99_Running", 135 }; 136 137 #ifdef CONFIG_SDMA_VERBOSITY 138 static const char * const sdma_event_names[] = { 139 [sdma_event_e00_go_hw_down] = "e00_GoHwDown", 140 [sdma_event_e10_go_hw_start] = "e10_GoHwStart", 141 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone", 142 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone", 143 [sdma_event_e30_go_running] = "e30_GoRunning", 144 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned", 145 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned", 146 [sdma_event_e60_hw_halted] = "e60_HwHalted", 147 [sdma_event_e70_go_idle] = "e70_GoIdle", 148 [sdma_event_e80_hw_freeze] = "e80_HwFreeze", 149 [sdma_event_e81_hw_frozen] = "e81_HwFrozen", 150 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze", 151 [sdma_event_e85_link_down] = "e85_LinkDown", 152 [sdma_event_e90_sw_halted] = "e90_SwHalted", 153 }; 154 #endif 155 156 static const struct sdma_set_state_action sdma_action_table[] = { 157 [sdma_state_s00_hw_down] = { 158 .go_s99_running_tofalse = 1, 159 .op_enable = 0, 160 .op_intenable = 0, 161 .op_halt = 0, 162 .op_cleanup = 0, 163 }, 164 [sdma_state_s10_hw_start_up_halt_wait] = { 165 .op_enable = 0, 166 .op_intenable = 0, 167 .op_halt = 1, 168 .op_cleanup = 0, 169 }, 170 [sdma_state_s15_hw_start_up_clean_wait] = { 171 .op_enable = 0, 172 .op_intenable = 1, 173 .op_halt = 0, 174 .op_cleanup = 1, 175 }, 176 [sdma_state_s20_idle] = { 177 .op_enable = 0, 178 .op_intenable = 1, 179 .op_halt = 0, 180 .op_cleanup = 0, 181 }, 182 [sdma_state_s30_sw_clean_up_wait] = { 183 .op_enable = 0, 184 .op_intenable = 0, 185 .op_halt = 0, 186 .op_cleanup = 0, 187 }, 188 [sdma_state_s40_hw_clean_up_wait] = { 189 .op_enable = 0, 190 .op_intenable = 0, 191 .op_halt = 0, 192 .op_cleanup = 1, 193 }, 194 [sdma_state_s50_hw_halt_wait] = { 195 .op_enable = 0, 196 .op_intenable = 0, 197 .op_halt = 0, 198 .op_cleanup = 0, 199 }, 200 [sdma_state_s60_idle_halt_wait] = { 201 .go_s99_running_tofalse = 1, 202 .op_enable = 0, 203 .op_intenable = 0, 204 .op_halt = 1, 205 .op_cleanup = 0, 206 }, 207 [sdma_state_s80_hw_freeze] = { 208 .op_enable = 0, 209 .op_intenable = 0, 210 .op_halt = 0, 211 .op_cleanup = 0, 212 }, 213 [sdma_state_s82_freeze_sw_clean] = { 214 .op_enable = 0, 215 .op_intenable = 0, 216 .op_halt = 0, 217 .op_cleanup = 0, 218 }, 219 [sdma_state_s99_running] = { 220 .op_enable = 1, 221 .op_intenable = 1, 222 .op_halt = 0, 223 .op_cleanup = 0, 224 .go_s99_running_totrue = 1, 225 }, 226 }; 227 228 #define SDMA_TAIL_UPDATE_THRESH 0x1F 229 230 /* declare all statics here rather than keep sorting */ 231 static void sdma_complete(struct kref *); 232 static void sdma_finalput(struct sdma_state *); 233 static void sdma_get(struct sdma_state *); 234 static void sdma_hw_clean_up_task(unsigned long); 235 static void sdma_put(struct sdma_state *); 236 static void sdma_set_state(struct sdma_engine *, enum sdma_states); 237 static void sdma_start_hw_clean_up(struct sdma_engine *); 238 static void sdma_sw_clean_up_task(unsigned long); 239 static void sdma_sendctrl(struct sdma_engine *, unsigned); 240 static void init_sdma_regs(struct sdma_engine *, u32, uint); 241 static void sdma_process_event( 242 struct sdma_engine *sde, 243 enum sdma_events event); 244 static void __sdma_process_event( 245 struct sdma_engine *sde, 246 enum sdma_events event); 247 static void dump_sdma_state(struct sdma_engine *sde); 248 static void sdma_make_progress(struct sdma_engine *sde, u64 status); 249 static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail); 250 static void sdma_flush_descq(struct sdma_engine *sde); 251 252 /** 253 * sdma_state_name() - return state string from enum 254 * @state: state 255 */ 256 static const char *sdma_state_name(enum sdma_states state) 257 { 258 return sdma_state_names[state]; 259 } 260 261 static void sdma_get(struct sdma_state *ss) 262 { 263 kref_get(&ss->kref); 264 } 265 266 static void sdma_complete(struct kref *kref) 267 { 268 struct sdma_state *ss = 269 container_of(kref, struct sdma_state, kref); 270 271 complete(&ss->comp); 272 } 273 274 static void sdma_put(struct sdma_state *ss) 275 { 276 kref_put(&ss->kref, sdma_complete); 277 } 278 279 static void sdma_finalput(struct sdma_state *ss) 280 { 281 sdma_put(ss); 282 wait_for_completion(&ss->comp); 283 } 284 285 static inline void write_sde_csr( 286 struct sdma_engine *sde, 287 u32 offset0, 288 u64 value) 289 { 290 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value); 291 } 292 293 static inline u64 read_sde_csr( 294 struct sdma_engine *sde, 295 u32 offset0) 296 { 297 return read_kctxt_csr(sde->dd, sde->this_idx, offset0); 298 } 299 300 /* 301 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for 302 * sdma engine 'sde' to drop to 0. 303 */ 304 static void sdma_wait_for_packet_egress(struct sdma_engine *sde, 305 int pause) 306 { 307 u64 off = 8 * sde->this_idx; 308 struct hfi1_devdata *dd = sde->dd; 309 int lcnt = 0; 310 u64 reg_prev; 311 u64 reg = 0; 312 313 while (1) { 314 reg_prev = reg; 315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); 316 317 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK; 318 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT; 319 if (reg == 0) 320 break; 321 /* counter is reest if accupancy count changes */ 322 if (reg != reg_prev) 323 lcnt = 0; 324 if (lcnt++ > 500) { 325 /* timed out - bounce the link */ 326 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n", 327 __func__, sde->this_idx, (u32)reg); 328 queue_work(dd->pport->hfi1_wq, 329 &dd->pport->link_bounce_work); 330 break; 331 } 332 udelay(1); 333 } 334 } 335 336 /* 337 * sdma_wait() - wait for packet egress to complete for all SDMA engines, 338 * and pause for credit return. 339 */ 340 void sdma_wait(struct hfi1_devdata *dd) 341 { 342 int i; 343 344 for (i = 0; i < dd->num_sdma; i++) { 345 struct sdma_engine *sde = &dd->per_sdma[i]; 346 347 sdma_wait_for_packet_egress(sde, 0); 348 } 349 } 350 351 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt) 352 { 353 u64 reg; 354 355 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT)) 356 return; 357 reg = cnt; 358 reg &= SD(DESC_CNT_CNT_MASK); 359 reg <<= SD(DESC_CNT_CNT_SHIFT); 360 write_sde_csr(sde, SD(DESC_CNT), reg); 361 } 362 363 static inline void complete_tx(struct sdma_engine *sde, 364 struct sdma_txreq *tx, 365 int res) 366 { 367 /* protect against complete modifying */ 368 struct iowait *wait = tx->wait; 369 callback_t complete = tx->complete; 370 371 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 372 trace_hfi1_sdma_out_sn(sde, tx->sn); 373 if (WARN_ON_ONCE(sde->head_sn != tx->sn)) 374 dd_dev_err(sde->dd, "expected %llu got %llu\n", 375 sde->head_sn, tx->sn); 376 sde->head_sn++; 377 #endif 378 sdma_txclean(sde->dd, tx); 379 if (complete) 380 (*complete)(tx, res); 381 if (wait && iowait_sdma_dec(wait)) 382 iowait_drain_wakeup(wait); 383 } 384 385 /* 386 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status 387 * 388 * Depending on timing there can be txreqs in two places: 389 * - in the descq ring 390 * - in the flush list 391 * 392 * To avoid ordering issues the descq ring needs to be flushed 393 * first followed by the flush list. 394 * 395 * This routine is called from two places 396 * - From a work queue item 397 * - Directly from the state machine just before setting the 398 * state to running 399 * 400 * Must be called with head_lock held 401 * 402 */ 403 static void sdma_flush(struct sdma_engine *sde) 404 { 405 struct sdma_txreq *txp, *txp_next; 406 LIST_HEAD(flushlist); 407 unsigned long flags; 408 409 /* flush from head to tail */ 410 sdma_flush_descq(sde); 411 spin_lock_irqsave(&sde->flushlist_lock, flags); 412 /* copy flush list */ 413 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) { 414 list_del_init(&txp->list); 415 list_add_tail(&txp->list, &flushlist); 416 } 417 spin_unlock_irqrestore(&sde->flushlist_lock, flags); 418 /* flush from flush list */ 419 list_for_each_entry_safe(txp, txp_next, &flushlist, list) 420 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED); 421 } 422 423 /* 424 * Fields a work request for flushing the descq ring 425 * and the flush list 426 * 427 * If the engine has been brought to running during 428 * the scheduling delay, the flush is ignored, assuming 429 * that the process of bringing the engine to running 430 * would have done this flush prior to going to running. 431 * 432 */ 433 static void sdma_field_flush(struct work_struct *work) 434 { 435 unsigned long flags; 436 struct sdma_engine *sde = 437 container_of(work, struct sdma_engine, flush_worker); 438 439 write_seqlock_irqsave(&sde->head_lock, flags); 440 if (!__sdma_running(sde)) 441 sdma_flush(sde); 442 write_sequnlock_irqrestore(&sde->head_lock, flags); 443 } 444 445 static void sdma_err_halt_wait(struct work_struct *work) 446 { 447 struct sdma_engine *sde = container_of(work, struct sdma_engine, 448 err_halt_worker); 449 u64 statuscsr; 450 unsigned long timeout; 451 452 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT); 453 while (1) { 454 statuscsr = read_sde_csr(sde, SD(STATUS)); 455 statuscsr &= SD(STATUS_ENG_HALTED_SMASK); 456 if (statuscsr) 457 break; 458 if (time_after(jiffies, timeout)) { 459 dd_dev_err(sde->dd, 460 "SDMA engine %d - timeout waiting for engine to halt\n", 461 sde->this_idx); 462 /* 463 * Continue anyway. This could happen if there was 464 * an uncorrectable error in the wrong spot. 465 */ 466 break; 467 } 468 usleep_range(80, 120); 469 } 470 471 sdma_process_event(sde, sdma_event_e15_hw_halt_done); 472 } 473 474 static void sdma_err_progress_check_schedule(struct sdma_engine *sde) 475 { 476 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) { 477 unsigned index; 478 struct hfi1_devdata *dd = sde->dd; 479 480 for (index = 0; index < dd->num_sdma; index++) { 481 struct sdma_engine *curr_sdma = &dd->per_sdma[index]; 482 483 if (curr_sdma != sde) 484 curr_sdma->progress_check_head = 485 curr_sdma->descq_head; 486 } 487 dd_dev_err(sde->dd, 488 "SDMA engine %d - check scheduled\n", 489 sde->this_idx); 490 mod_timer(&sde->err_progress_check_timer, jiffies + 10); 491 } 492 } 493 494 static void sdma_err_progress_check(unsigned long data) 495 { 496 unsigned index; 497 struct sdma_engine *sde = (struct sdma_engine *)data; 498 499 dd_dev_err(sde->dd, "SDE progress check event\n"); 500 for (index = 0; index < sde->dd->num_sdma; index++) { 501 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index]; 502 unsigned long flags; 503 504 /* check progress on each engine except the current one */ 505 if (curr_sde == sde) 506 continue; 507 /* 508 * We must lock interrupts when acquiring sde->lock, 509 * to avoid a deadlock if interrupt triggers and spins on 510 * the same lock on same CPU 511 */ 512 spin_lock_irqsave(&curr_sde->tail_lock, flags); 513 write_seqlock(&curr_sde->head_lock); 514 515 /* skip non-running queues */ 516 if (curr_sde->state.current_state != sdma_state_s99_running) { 517 write_sequnlock(&curr_sde->head_lock); 518 spin_unlock_irqrestore(&curr_sde->tail_lock, flags); 519 continue; 520 } 521 522 if ((curr_sde->descq_head != curr_sde->descq_tail) && 523 (curr_sde->descq_head == 524 curr_sde->progress_check_head)) 525 __sdma_process_event(curr_sde, 526 sdma_event_e90_sw_halted); 527 write_sequnlock(&curr_sde->head_lock); 528 spin_unlock_irqrestore(&curr_sde->tail_lock, flags); 529 } 530 schedule_work(&sde->err_halt_worker); 531 } 532 533 static void sdma_hw_clean_up_task(unsigned long opaque) 534 { 535 struct sdma_engine *sde = (struct sdma_engine *)opaque; 536 u64 statuscsr; 537 538 while (1) { 539 #ifdef CONFIG_SDMA_VERBOSITY 540 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 541 sde->this_idx, slashstrip(__FILE__), __LINE__, 542 __func__); 543 #endif 544 statuscsr = read_sde_csr(sde, SD(STATUS)); 545 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK); 546 if (statuscsr) 547 break; 548 udelay(10); 549 } 550 551 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done); 552 } 553 554 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde) 555 { 556 smp_read_barrier_depends(); /* see sdma_update_tail() */ 557 return sde->tx_ring[sde->tx_head & sde->sdma_mask]; 558 } 559 560 /* 561 * flush ring for recovery 562 */ 563 static void sdma_flush_descq(struct sdma_engine *sde) 564 { 565 u16 head, tail; 566 int progress = 0; 567 struct sdma_txreq *txp = get_txhead(sde); 568 569 /* The reason for some of the complexity of this code is that 570 * not all descriptors have corresponding txps. So, we have to 571 * be able to skip over descs until we wander into the range of 572 * the next txp on the list. 573 */ 574 head = sde->descq_head & sde->sdma_mask; 575 tail = sde->descq_tail & sde->sdma_mask; 576 while (head != tail) { 577 /* advance head, wrap if needed */ 578 head = ++sde->descq_head & sde->sdma_mask; 579 /* if now past this txp's descs, do the callback */ 580 if (txp && txp->next_descq_idx == head) { 581 /* remove from list */ 582 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; 583 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED); 584 trace_hfi1_sdma_progress(sde, head, tail, txp); 585 txp = get_txhead(sde); 586 } 587 progress++; 588 } 589 if (progress) 590 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 591 } 592 593 static void sdma_sw_clean_up_task(unsigned long opaque) 594 { 595 struct sdma_engine *sde = (struct sdma_engine *)opaque; 596 unsigned long flags; 597 598 spin_lock_irqsave(&sde->tail_lock, flags); 599 write_seqlock(&sde->head_lock); 600 601 /* 602 * At this point, the following should always be true: 603 * - We are halted, so no more descriptors are getting retired. 604 * - We are not running, so no one is submitting new work. 605 * - Only we can send the e40_sw_cleaned, so we can't start 606 * running again until we say so. So, the active list and 607 * descq are ours to play with. 608 */ 609 610 /* 611 * In the error clean up sequence, software clean must be called 612 * before the hardware clean so we can use the hardware head in 613 * the progress routine. A hardware clean or SPC unfreeze will 614 * reset the hardware head. 615 * 616 * Process all retired requests. The progress routine will use the 617 * latest physical hardware head - we are not running so speed does 618 * not matter. 619 */ 620 sdma_make_progress(sde, 0); 621 622 sdma_flush(sde); 623 624 /* 625 * Reset our notion of head and tail. 626 * Note that the HW registers have been reset via an earlier 627 * clean up. 628 */ 629 sde->descq_tail = 0; 630 sde->descq_head = 0; 631 sde->desc_avail = sdma_descq_freecnt(sde); 632 *sde->head_dma = 0; 633 634 __sdma_process_event(sde, sdma_event_e40_sw_cleaned); 635 636 write_sequnlock(&sde->head_lock); 637 spin_unlock_irqrestore(&sde->tail_lock, flags); 638 } 639 640 static void sdma_sw_tear_down(struct sdma_engine *sde) 641 { 642 struct sdma_state *ss = &sde->state; 643 644 /* Releasing this reference means the state machine has stopped. */ 645 sdma_put(ss); 646 647 /* stop waiting for all unfreeze events to complete */ 648 atomic_set(&sde->dd->sdma_unfreeze_count, -1); 649 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 650 } 651 652 static void sdma_start_hw_clean_up(struct sdma_engine *sde) 653 { 654 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task); 655 } 656 657 static void sdma_set_state(struct sdma_engine *sde, 658 enum sdma_states next_state) 659 { 660 struct sdma_state *ss = &sde->state; 661 const struct sdma_set_state_action *action = sdma_action_table; 662 unsigned op = 0; 663 664 trace_hfi1_sdma_state( 665 sde, 666 sdma_state_names[ss->current_state], 667 sdma_state_names[next_state]); 668 669 /* debugging bookkeeping */ 670 ss->previous_state = ss->current_state; 671 ss->previous_op = ss->current_op; 672 ss->current_state = next_state; 673 674 if (ss->previous_state != sdma_state_s99_running && 675 next_state == sdma_state_s99_running) 676 sdma_flush(sde); 677 678 if (action[next_state].op_enable) 679 op |= SDMA_SENDCTRL_OP_ENABLE; 680 681 if (action[next_state].op_intenable) 682 op |= SDMA_SENDCTRL_OP_INTENABLE; 683 684 if (action[next_state].op_halt) 685 op |= SDMA_SENDCTRL_OP_HALT; 686 687 if (action[next_state].op_cleanup) 688 op |= SDMA_SENDCTRL_OP_CLEANUP; 689 690 if (action[next_state].go_s99_running_tofalse) 691 ss->go_s99_running = 0; 692 693 if (action[next_state].go_s99_running_totrue) 694 ss->go_s99_running = 1; 695 696 ss->current_op = op; 697 sdma_sendctrl(sde, ss->current_op); 698 } 699 700 /** 701 * sdma_get_descq_cnt() - called when device probed 702 * 703 * Return a validated descq count. 704 * 705 * This is currently only used in the verbs initialization to build the tx 706 * list. 707 * 708 * This will probably be deleted in favor of a more scalable approach to 709 * alloc tx's. 710 * 711 */ 712 u16 sdma_get_descq_cnt(void) 713 { 714 u16 count = sdma_descq_cnt; 715 716 if (!count) 717 return SDMA_DESCQ_CNT; 718 /* count must be a power of 2 greater than 64 and less than 719 * 32768. Otherwise return default. 720 */ 721 if (!is_power_of_2(count)) 722 return SDMA_DESCQ_CNT; 723 if (count < 64 || count > 32768) 724 return SDMA_DESCQ_CNT; 725 return count; 726 } 727 728 /** 729 * sdma_engine_get_vl() - return vl for a given sdma engine 730 * @sde: sdma engine 731 * 732 * This function returns the vl mapped to a given engine, or an error if 733 * the mapping can't be found. The mapping fields are protected by RCU. 734 */ 735 int sdma_engine_get_vl(struct sdma_engine *sde) 736 { 737 struct hfi1_devdata *dd = sde->dd; 738 struct sdma_vl_map *m; 739 u8 vl; 740 741 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES) 742 return -EINVAL; 743 744 rcu_read_lock(); 745 m = rcu_dereference(dd->sdma_map); 746 if (unlikely(!m)) { 747 rcu_read_unlock(); 748 return -EINVAL; 749 } 750 vl = m->engine_to_vl[sde->this_idx]; 751 rcu_read_unlock(); 752 753 return vl; 754 } 755 756 /** 757 * sdma_select_engine_vl() - select sdma engine 758 * @dd: devdata 759 * @selector: a spreading factor 760 * @vl: this vl 761 * 762 * 763 * This function returns an engine based on the selector and a vl. The 764 * mapping fields are protected by RCU. 765 */ 766 struct sdma_engine *sdma_select_engine_vl( 767 struct hfi1_devdata *dd, 768 u32 selector, 769 u8 vl) 770 { 771 struct sdma_vl_map *m; 772 struct sdma_map_elem *e; 773 struct sdma_engine *rval; 774 775 /* NOTE This should only happen if SC->VL changed after the initial 776 * checks on the QP/AH 777 * Default will return engine 0 below 778 */ 779 if (vl >= num_vls) { 780 rval = NULL; 781 goto done; 782 } 783 784 rcu_read_lock(); 785 m = rcu_dereference(dd->sdma_map); 786 if (unlikely(!m)) { 787 rcu_read_unlock(); 788 return &dd->per_sdma[0]; 789 } 790 e = m->map[vl & m->mask]; 791 rval = e->sde[selector & e->mask]; 792 rcu_read_unlock(); 793 794 done: 795 rval = !rval ? &dd->per_sdma[0] : rval; 796 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx); 797 return rval; 798 } 799 800 /** 801 * sdma_select_engine_sc() - select sdma engine 802 * @dd: devdata 803 * @selector: a spreading factor 804 * @sc5: the 5 bit sc 805 * 806 * 807 * This function returns an engine based on the selector and an sc. 808 */ 809 struct sdma_engine *sdma_select_engine_sc( 810 struct hfi1_devdata *dd, 811 u32 selector, 812 u8 sc5) 813 { 814 u8 vl = sc_to_vlt(dd, sc5); 815 816 return sdma_select_engine_vl(dd, selector, vl); 817 } 818 819 struct sdma_rht_map_elem { 820 u32 mask; 821 u8 ctr; 822 struct sdma_engine *sde[0]; 823 }; 824 825 struct sdma_rht_node { 826 unsigned long cpu_id; 827 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED]; 828 struct rhash_head node; 829 }; 830 831 #define NR_CPUS_HINT 192 832 833 static const struct rhashtable_params sdma_rht_params = { 834 .nelem_hint = NR_CPUS_HINT, 835 .head_offset = offsetof(struct sdma_rht_node, node), 836 .key_offset = offsetof(struct sdma_rht_node, cpu_id), 837 .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id), 838 .max_size = NR_CPUS, 839 .min_size = 8, 840 .automatic_shrinking = true, 841 }; 842 843 /* 844 * sdma_select_user_engine() - select sdma engine based on user setup 845 * @dd: devdata 846 * @selector: a spreading factor 847 * @vl: this vl 848 * 849 * This function returns an sdma engine for a user sdma request. 850 * User defined sdma engine affinity setting is honored when applicable, 851 * otherwise system default sdma engine mapping is used. To ensure correct 852 * ordering, the mapping from <selector, vl> to sde must remain unchanged. 853 */ 854 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd, 855 u32 selector, u8 vl) 856 { 857 struct sdma_rht_node *rht_node; 858 struct sdma_engine *sde = NULL; 859 const struct cpumask *current_mask = tsk_cpus_allowed(current); 860 unsigned long cpu_id; 861 862 /* 863 * To ensure that always the same sdma engine(s) will be 864 * selected make sure the process is pinned to this CPU only. 865 */ 866 if (cpumask_weight(current_mask) != 1) 867 goto out; 868 869 cpu_id = smp_processor_id(); 870 rcu_read_lock(); 871 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpu_id, 872 sdma_rht_params); 873 874 if (rht_node && rht_node->map[vl]) { 875 struct sdma_rht_map_elem *map = rht_node->map[vl]; 876 877 sde = map->sde[selector & map->mask]; 878 } 879 rcu_read_unlock(); 880 881 if (sde) 882 return sde; 883 884 out: 885 return sdma_select_engine_vl(dd, selector, vl); 886 } 887 888 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map) 889 { 890 int i; 891 892 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++) 893 map->sde[map->ctr + i] = map->sde[i]; 894 } 895 896 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map, 897 struct sdma_engine *sde) 898 { 899 unsigned int i, pow; 900 901 /* only need to check the first ctr entries for a match */ 902 for (i = 0; i < map->ctr; i++) { 903 if (map->sde[i] == sde) { 904 memmove(&map->sde[i], &map->sde[i + 1], 905 (map->ctr - i - 1) * sizeof(map->sde[0])); 906 map->ctr--; 907 pow = roundup_pow_of_two(map->ctr ? : 1); 908 map->mask = pow - 1; 909 sdma_populate_sde_map(map); 910 break; 911 } 912 } 913 } 914 915 /* 916 * Prevents concurrent reads and writes of the sdma engine cpu_mask 917 */ 918 static DEFINE_MUTEX(process_to_sde_mutex); 919 920 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf, 921 size_t count) 922 { 923 struct hfi1_devdata *dd = sde->dd; 924 cpumask_var_t mask, new_mask; 925 unsigned long cpu; 926 int ret, vl, sz; 927 928 vl = sdma_engine_get_vl(sde); 929 if (unlikely(vl < 0)) 930 return -EINVAL; 931 932 ret = zalloc_cpumask_var(&mask, GFP_KERNEL); 933 if (!ret) 934 return -ENOMEM; 935 936 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL); 937 if (!ret) { 938 free_cpumask_var(mask); 939 return -ENOMEM; 940 } 941 ret = cpulist_parse(buf, mask); 942 if (ret) 943 goto out_free; 944 945 if (!cpumask_subset(mask, cpu_online_mask)) { 946 dd_dev_warn(sde->dd, "Invalid CPU mask\n"); 947 ret = -EINVAL; 948 goto out_free; 949 } 950 951 sz = sizeof(struct sdma_rht_map_elem) + 952 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *)); 953 954 mutex_lock(&process_to_sde_mutex); 955 956 for_each_cpu(cpu, mask) { 957 struct sdma_rht_node *rht_node; 958 959 /* Check if we have this already mapped */ 960 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) { 961 cpumask_set_cpu(cpu, new_mask); 962 continue; 963 } 964 965 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpu, 966 sdma_rht_params); 967 if (!rht_node) { 968 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL); 969 if (!rht_node) { 970 ret = -ENOMEM; 971 goto out; 972 } 973 974 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL); 975 if (!rht_node->map[vl]) { 976 kfree(rht_node); 977 ret = -ENOMEM; 978 goto out; 979 } 980 rht_node->cpu_id = cpu; 981 rht_node->map[vl]->mask = 0; 982 rht_node->map[vl]->ctr = 1; 983 rht_node->map[vl]->sde[0] = sde; 984 985 ret = rhashtable_insert_fast(&dd->sdma_rht, 986 &rht_node->node, 987 sdma_rht_params); 988 if (ret) { 989 kfree(rht_node->map[vl]); 990 kfree(rht_node); 991 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n", 992 cpu); 993 goto out; 994 } 995 996 } else { 997 int ctr, pow; 998 999 /* Add new user mappings */ 1000 if (!rht_node->map[vl]) 1001 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL); 1002 1003 if (!rht_node->map[vl]) { 1004 ret = -ENOMEM; 1005 goto out; 1006 } 1007 1008 rht_node->map[vl]->ctr++; 1009 ctr = rht_node->map[vl]->ctr; 1010 rht_node->map[vl]->sde[ctr - 1] = sde; 1011 pow = roundup_pow_of_two(ctr); 1012 rht_node->map[vl]->mask = pow - 1; 1013 1014 /* Populate the sde map table */ 1015 sdma_populate_sde_map(rht_node->map[vl]); 1016 } 1017 cpumask_set_cpu(cpu, new_mask); 1018 } 1019 1020 /* Clean up old mappings */ 1021 for_each_cpu(cpu, cpu_online_mask) { 1022 struct sdma_rht_node *rht_node; 1023 1024 /* Don't cleanup sdes that are set in the new mask */ 1025 if (cpumask_test_cpu(cpu, mask)) 1026 continue; 1027 1028 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpu, 1029 sdma_rht_params); 1030 if (rht_node) { 1031 bool empty = true; 1032 int i; 1033 1034 /* Remove mappings for old sde */ 1035 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1036 if (rht_node->map[i]) 1037 sdma_cleanup_sde_map(rht_node->map[i], 1038 sde); 1039 1040 /* Free empty hash table entries */ 1041 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) { 1042 if (!rht_node->map[i]) 1043 continue; 1044 1045 if (rht_node->map[i]->ctr) { 1046 empty = false; 1047 break; 1048 } 1049 } 1050 1051 if (empty) { 1052 ret = rhashtable_remove_fast(&dd->sdma_rht, 1053 &rht_node->node, 1054 sdma_rht_params); 1055 WARN_ON(ret); 1056 1057 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1058 kfree(rht_node->map[i]); 1059 1060 kfree(rht_node); 1061 } 1062 } 1063 } 1064 1065 cpumask_copy(&sde->cpu_mask, new_mask); 1066 out: 1067 mutex_unlock(&process_to_sde_mutex); 1068 out_free: 1069 free_cpumask_var(mask); 1070 free_cpumask_var(new_mask); 1071 return ret ? : strnlen(buf, PAGE_SIZE); 1072 } 1073 1074 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf) 1075 { 1076 mutex_lock(&process_to_sde_mutex); 1077 if (cpumask_empty(&sde->cpu_mask)) 1078 snprintf(buf, PAGE_SIZE, "%s\n", "empty"); 1079 else 1080 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask); 1081 mutex_unlock(&process_to_sde_mutex); 1082 return strnlen(buf, PAGE_SIZE); 1083 } 1084 1085 static void sdma_rht_free(void *ptr, void *arg) 1086 { 1087 struct sdma_rht_node *rht_node = ptr; 1088 int i; 1089 1090 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1091 kfree(rht_node->map[i]); 1092 1093 kfree(rht_node); 1094 } 1095 1096 /** 1097 * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings 1098 * @s: seq file 1099 * @dd: hfi1_devdata 1100 * @cpuid: cpu id 1101 * 1102 * This routine dumps the process to sde mappings per cpu 1103 */ 1104 void sdma_seqfile_dump_cpu_list(struct seq_file *s, 1105 struct hfi1_devdata *dd, 1106 unsigned long cpuid) 1107 { 1108 struct sdma_rht_node *rht_node; 1109 int i, j; 1110 1111 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpuid, 1112 sdma_rht_params); 1113 if (!rht_node) 1114 return; 1115 1116 seq_printf(s, "cpu%3lu: ", cpuid); 1117 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) { 1118 if (!rht_node->map[i] || !rht_node->map[i]->ctr) 1119 continue; 1120 1121 seq_printf(s, " vl%d: [", i); 1122 1123 for (j = 0; j < rht_node->map[i]->ctr; j++) { 1124 if (!rht_node->map[i]->sde[j]) 1125 continue; 1126 1127 if (j > 0) 1128 seq_puts(s, ","); 1129 1130 seq_printf(s, " sdma%2d", 1131 rht_node->map[i]->sde[j]->this_idx); 1132 } 1133 seq_puts(s, " ]"); 1134 } 1135 1136 seq_puts(s, "\n"); 1137 } 1138 1139 /* 1140 * Free the indicated map struct 1141 */ 1142 static void sdma_map_free(struct sdma_vl_map *m) 1143 { 1144 int i; 1145 1146 for (i = 0; m && i < m->actual_vls; i++) 1147 kfree(m->map[i]); 1148 kfree(m); 1149 } 1150 1151 /* 1152 * Handle RCU callback 1153 */ 1154 static void sdma_map_rcu_callback(struct rcu_head *list) 1155 { 1156 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list); 1157 1158 sdma_map_free(m); 1159 } 1160 1161 /** 1162 * sdma_map_init - called when # vls change 1163 * @dd: hfi1_devdata 1164 * @port: port number 1165 * @num_vls: number of vls 1166 * @vl_engines: per vl engine mapping (optional) 1167 * 1168 * This routine changes the mapping based on the number of vls. 1169 * 1170 * vl_engines is used to specify a non-uniform vl/engine loading. NULL 1171 * implies auto computing the loading and giving each VLs a uniform 1172 * distribution of engines per VL. 1173 * 1174 * The auto algorithm computes the sde_per_vl and the number of extra 1175 * engines. Any extra engines are added from the last VL on down. 1176 * 1177 * rcu locking is used here to control access to the mapping fields. 1178 * 1179 * If either the num_vls or num_sdma are non-power of 2, the array sizes 1180 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded 1181 * up to the next highest power of 2 and the first entry is reused 1182 * in a round robin fashion. 1183 * 1184 * If an error occurs the map change is not done and the mapping is 1185 * not changed. 1186 * 1187 */ 1188 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines) 1189 { 1190 int i, j; 1191 int extra, sde_per_vl; 1192 int engine = 0; 1193 u8 lvl_engines[OPA_MAX_VLS]; 1194 struct sdma_vl_map *oldmap, *newmap; 1195 1196 if (!(dd->flags & HFI1_HAS_SEND_DMA)) 1197 return 0; 1198 1199 if (!vl_engines) { 1200 /* truncate divide */ 1201 sde_per_vl = dd->num_sdma / num_vls; 1202 /* extras */ 1203 extra = dd->num_sdma % num_vls; 1204 vl_engines = lvl_engines; 1205 /* add extras from last vl down */ 1206 for (i = num_vls - 1; i >= 0; i--, extra--) 1207 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0); 1208 } 1209 /* build new map */ 1210 newmap = kzalloc( 1211 sizeof(struct sdma_vl_map) + 1212 roundup_pow_of_two(num_vls) * 1213 sizeof(struct sdma_map_elem *), 1214 GFP_KERNEL); 1215 if (!newmap) 1216 goto bail; 1217 newmap->actual_vls = num_vls; 1218 newmap->vls = roundup_pow_of_two(num_vls); 1219 newmap->mask = (1 << ilog2(newmap->vls)) - 1; 1220 /* initialize back-map */ 1221 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++) 1222 newmap->engine_to_vl[i] = -1; 1223 for (i = 0; i < newmap->vls; i++) { 1224 /* save for wrap around */ 1225 int first_engine = engine; 1226 1227 if (i < newmap->actual_vls) { 1228 int sz = roundup_pow_of_two(vl_engines[i]); 1229 1230 /* only allocate once */ 1231 newmap->map[i] = kzalloc( 1232 sizeof(struct sdma_map_elem) + 1233 sz * sizeof(struct sdma_engine *), 1234 GFP_KERNEL); 1235 if (!newmap->map[i]) 1236 goto bail; 1237 newmap->map[i]->mask = (1 << ilog2(sz)) - 1; 1238 /* assign engines */ 1239 for (j = 0; j < sz; j++) { 1240 newmap->map[i]->sde[j] = 1241 &dd->per_sdma[engine]; 1242 if (++engine >= first_engine + vl_engines[i]) 1243 /* wrap back to first engine */ 1244 engine = first_engine; 1245 } 1246 /* assign back-map */ 1247 for (j = 0; j < vl_engines[i]; j++) 1248 newmap->engine_to_vl[first_engine + j] = i; 1249 } else { 1250 /* just re-use entry without allocating */ 1251 newmap->map[i] = newmap->map[i % num_vls]; 1252 } 1253 engine = first_engine + vl_engines[i]; 1254 } 1255 /* newmap in hand, save old map */ 1256 spin_lock_irq(&dd->sde_map_lock); 1257 oldmap = rcu_dereference_protected(dd->sdma_map, 1258 lockdep_is_held(&dd->sde_map_lock)); 1259 1260 /* publish newmap */ 1261 rcu_assign_pointer(dd->sdma_map, newmap); 1262 1263 spin_unlock_irq(&dd->sde_map_lock); 1264 /* success, free any old map after grace period */ 1265 if (oldmap) 1266 call_rcu(&oldmap->list, sdma_map_rcu_callback); 1267 return 0; 1268 bail: 1269 /* free any partial allocation */ 1270 sdma_map_free(newmap); 1271 return -ENOMEM; 1272 } 1273 1274 /* 1275 * Clean up allocated memory. 1276 * 1277 * This routine is can be called regardless of the success of sdma_init() 1278 * 1279 */ 1280 static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) 1281 { 1282 size_t i; 1283 struct sdma_engine *sde; 1284 1285 if (dd->sdma_pad_dma) { 1286 dma_free_coherent(&dd->pcidev->dev, 4, 1287 (void *)dd->sdma_pad_dma, 1288 dd->sdma_pad_phys); 1289 dd->sdma_pad_dma = NULL; 1290 dd->sdma_pad_phys = 0; 1291 } 1292 if (dd->sdma_heads_dma) { 1293 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size, 1294 (void *)dd->sdma_heads_dma, 1295 dd->sdma_heads_phys); 1296 dd->sdma_heads_dma = NULL; 1297 dd->sdma_heads_phys = 0; 1298 } 1299 for (i = 0; dd->per_sdma && i < num_engines; ++i) { 1300 sde = &dd->per_sdma[i]; 1301 1302 sde->head_dma = NULL; 1303 sde->head_phys = 0; 1304 1305 if (sde->descq) { 1306 dma_free_coherent( 1307 &dd->pcidev->dev, 1308 sde->descq_cnt * sizeof(u64[2]), 1309 sde->descq, 1310 sde->descq_phys 1311 ); 1312 sde->descq = NULL; 1313 sde->descq_phys = 0; 1314 } 1315 kvfree(sde->tx_ring); 1316 sde->tx_ring = NULL; 1317 } 1318 spin_lock_irq(&dd->sde_map_lock); 1319 sdma_map_free(rcu_access_pointer(dd->sdma_map)); 1320 RCU_INIT_POINTER(dd->sdma_map, NULL); 1321 spin_unlock_irq(&dd->sde_map_lock); 1322 synchronize_rcu(); 1323 kfree(dd->per_sdma); 1324 dd->per_sdma = NULL; 1325 } 1326 1327 /** 1328 * sdma_init() - called when device probed 1329 * @dd: hfi1_devdata 1330 * @port: port number (currently only zero) 1331 * 1332 * sdma_init initializes the specified number of engines. 1333 * 1334 * The code initializes each sde, its csrs. Interrupts 1335 * are not required to be enabled. 1336 * 1337 * Returns: 1338 * 0 - success, -errno on failure 1339 */ 1340 int sdma_init(struct hfi1_devdata *dd, u8 port) 1341 { 1342 unsigned this_idx; 1343 struct sdma_engine *sde; 1344 u16 descq_cnt; 1345 void *curr_head; 1346 struct hfi1_pportdata *ppd = dd->pport + port; 1347 u32 per_sdma_credits; 1348 uint idle_cnt = sdma_idle_cnt; 1349 size_t num_engines = dd->chip_sdma_engines; 1350 1351 if (!HFI1_CAP_IS_KSET(SDMA)) { 1352 HFI1_CAP_CLEAR(SDMA_AHG); 1353 return 0; 1354 } 1355 if (mod_num_sdma && 1356 /* can't exceed chip support */ 1357 mod_num_sdma <= dd->chip_sdma_engines && 1358 /* count must be >= vls */ 1359 mod_num_sdma >= num_vls) 1360 num_engines = mod_num_sdma; 1361 1362 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma); 1363 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines); 1364 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n", 1365 dd->chip_sdma_mem_size); 1366 1367 per_sdma_credits = 1368 dd->chip_sdma_mem_size / (num_engines * SDMA_BLOCK_SIZE); 1369 1370 /* set up freeze waitqueue */ 1371 init_waitqueue_head(&dd->sdma_unfreeze_wq); 1372 atomic_set(&dd->sdma_unfreeze_count, 0); 1373 1374 descq_cnt = sdma_get_descq_cnt(); 1375 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n", 1376 num_engines, descq_cnt); 1377 1378 /* alloc memory for array of send engines */ 1379 dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL); 1380 if (!dd->per_sdma) 1381 return -ENOMEM; 1382 1383 idle_cnt = ns_to_cclock(dd, idle_cnt); 1384 if (!sdma_desct_intr) 1385 sdma_desct_intr = SDMA_DESC_INTR; 1386 1387 /* Allocate memory for SendDMA descriptor FIFOs */ 1388 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1389 sde = &dd->per_sdma[this_idx]; 1390 sde->dd = dd; 1391 sde->ppd = ppd; 1392 sde->this_idx = this_idx; 1393 sde->descq_cnt = descq_cnt; 1394 sde->desc_avail = sdma_descq_freecnt(sde); 1395 sde->sdma_shift = ilog2(descq_cnt); 1396 sde->sdma_mask = (1 << sde->sdma_shift) - 1; 1397 1398 /* Create a mask specifically for each interrupt source */ 1399 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES + 1400 this_idx); 1401 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES + 1402 this_idx); 1403 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES + 1404 this_idx); 1405 /* Create a combined mask to cover all 3 interrupt sources */ 1406 sde->imask = sde->int_mask | sde->progress_mask | 1407 sde->idle_mask; 1408 1409 spin_lock_init(&sde->tail_lock); 1410 seqlock_init(&sde->head_lock); 1411 spin_lock_init(&sde->senddmactrl_lock); 1412 spin_lock_init(&sde->flushlist_lock); 1413 /* insure there is always a zero bit */ 1414 sde->ahg_bits = 0xfffffffe00000000ULL; 1415 1416 sdma_set_state(sde, sdma_state_s00_hw_down); 1417 1418 /* set up reference counting */ 1419 kref_init(&sde->state.kref); 1420 init_completion(&sde->state.comp); 1421 1422 INIT_LIST_HEAD(&sde->flushlist); 1423 INIT_LIST_HEAD(&sde->dmawait); 1424 1425 sde->tail_csr = 1426 get_kctxt_csr_addr(dd, this_idx, SD(TAIL)); 1427 1428 if (idle_cnt) 1429 dd->default_desc1 = 1430 SDMA_DESC1_HEAD_TO_HOST_FLAG; 1431 else 1432 dd->default_desc1 = 1433 SDMA_DESC1_INT_REQ_FLAG; 1434 1435 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task, 1436 (unsigned long)sde); 1437 1438 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task, 1439 (unsigned long)sde); 1440 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait); 1441 INIT_WORK(&sde->flush_worker, sdma_field_flush); 1442 1443 sde->progress_check_head = 0; 1444 1445 setup_timer(&sde->err_progress_check_timer, 1446 sdma_err_progress_check, (unsigned long)sde); 1447 1448 sde->descq = dma_zalloc_coherent( 1449 &dd->pcidev->dev, 1450 descq_cnt * sizeof(u64[2]), 1451 &sde->descq_phys, 1452 GFP_KERNEL 1453 ); 1454 if (!sde->descq) 1455 goto bail; 1456 sde->tx_ring = 1457 kcalloc(descq_cnt, sizeof(struct sdma_txreq *), 1458 GFP_KERNEL); 1459 if (!sde->tx_ring) 1460 sde->tx_ring = 1461 vzalloc( 1462 sizeof(struct sdma_txreq *) * 1463 descq_cnt); 1464 if (!sde->tx_ring) 1465 goto bail; 1466 } 1467 1468 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; 1469 /* Allocate memory for DMA of head registers to memory */ 1470 dd->sdma_heads_dma = dma_zalloc_coherent( 1471 &dd->pcidev->dev, 1472 dd->sdma_heads_size, 1473 &dd->sdma_heads_phys, 1474 GFP_KERNEL 1475 ); 1476 if (!dd->sdma_heads_dma) { 1477 dd_dev_err(dd, "failed to allocate SendDMA head memory\n"); 1478 goto bail; 1479 } 1480 1481 /* Allocate memory for pad */ 1482 dd->sdma_pad_dma = dma_zalloc_coherent( 1483 &dd->pcidev->dev, 1484 sizeof(u32), 1485 &dd->sdma_pad_phys, 1486 GFP_KERNEL 1487 ); 1488 if (!dd->sdma_pad_dma) { 1489 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n"); 1490 goto bail; 1491 } 1492 1493 /* assign each engine to different cacheline and init registers */ 1494 curr_head = (void *)dd->sdma_heads_dma; 1495 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1496 unsigned long phys_offset; 1497 1498 sde = &dd->per_sdma[this_idx]; 1499 1500 sde->head_dma = curr_head; 1501 curr_head += L1_CACHE_BYTES; 1502 phys_offset = (unsigned long)sde->head_dma - 1503 (unsigned long)dd->sdma_heads_dma; 1504 sde->head_phys = dd->sdma_heads_phys + phys_offset; 1505 init_sdma_regs(sde, per_sdma_credits, idle_cnt); 1506 } 1507 dd->flags |= HFI1_HAS_SEND_DMA; 1508 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0; 1509 dd->num_sdma = num_engines; 1510 if (sdma_map_init(dd, port, ppd->vls_operational, NULL)) 1511 goto bail; 1512 1513 if (rhashtable_init(&dd->sdma_rht, &sdma_rht_params)) 1514 goto bail; 1515 1516 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma); 1517 return 0; 1518 1519 bail: 1520 sdma_clean(dd, num_engines); 1521 return -ENOMEM; 1522 } 1523 1524 /** 1525 * sdma_all_running() - called when the link goes up 1526 * @dd: hfi1_devdata 1527 * 1528 * This routine moves all engines to the running state. 1529 */ 1530 void sdma_all_running(struct hfi1_devdata *dd) 1531 { 1532 struct sdma_engine *sde; 1533 unsigned int i; 1534 1535 /* move all engines to running */ 1536 for (i = 0; i < dd->num_sdma; ++i) { 1537 sde = &dd->per_sdma[i]; 1538 sdma_process_event(sde, sdma_event_e30_go_running); 1539 } 1540 } 1541 1542 /** 1543 * sdma_all_idle() - called when the link goes down 1544 * @dd: hfi1_devdata 1545 * 1546 * This routine moves all engines to the idle state. 1547 */ 1548 void sdma_all_idle(struct hfi1_devdata *dd) 1549 { 1550 struct sdma_engine *sde; 1551 unsigned int i; 1552 1553 /* idle all engines */ 1554 for (i = 0; i < dd->num_sdma; ++i) { 1555 sde = &dd->per_sdma[i]; 1556 sdma_process_event(sde, sdma_event_e70_go_idle); 1557 } 1558 } 1559 1560 /** 1561 * sdma_start() - called to kick off state processing for all engines 1562 * @dd: hfi1_devdata 1563 * 1564 * This routine is for kicking off the state processing for all required 1565 * sdma engines. Interrupts need to be working at this point. 1566 * 1567 */ 1568 void sdma_start(struct hfi1_devdata *dd) 1569 { 1570 unsigned i; 1571 struct sdma_engine *sde; 1572 1573 /* kick off the engines state processing */ 1574 for (i = 0; i < dd->num_sdma; ++i) { 1575 sde = &dd->per_sdma[i]; 1576 sdma_process_event(sde, sdma_event_e10_go_hw_start); 1577 } 1578 } 1579 1580 /** 1581 * sdma_exit() - used when module is removed 1582 * @dd: hfi1_devdata 1583 */ 1584 void sdma_exit(struct hfi1_devdata *dd) 1585 { 1586 unsigned this_idx; 1587 struct sdma_engine *sde; 1588 1589 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma; 1590 ++this_idx) { 1591 sde = &dd->per_sdma[this_idx]; 1592 if (!list_empty(&sde->dmawait)) 1593 dd_dev_err(dd, "sde %u: dmawait list not empty!\n", 1594 sde->this_idx); 1595 sdma_process_event(sde, sdma_event_e00_go_hw_down); 1596 1597 del_timer_sync(&sde->err_progress_check_timer); 1598 1599 /* 1600 * This waits for the state machine to exit so it is not 1601 * necessary to kill the sdma_sw_clean_up_task to make sure 1602 * it is not running. 1603 */ 1604 sdma_finalput(&sde->state); 1605 } 1606 sdma_clean(dd, dd->num_sdma); 1607 rhashtable_free_and_destroy(&dd->sdma_rht, sdma_rht_free, NULL); 1608 } 1609 1610 /* 1611 * unmap the indicated descriptor 1612 */ 1613 static inline void sdma_unmap_desc( 1614 struct hfi1_devdata *dd, 1615 struct sdma_desc *descp) 1616 { 1617 switch (sdma_mapping_type(descp)) { 1618 case SDMA_MAP_SINGLE: 1619 dma_unmap_single( 1620 &dd->pcidev->dev, 1621 sdma_mapping_addr(descp), 1622 sdma_mapping_len(descp), 1623 DMA_TO_DEVICE); 1624 break; 1625 case SDMA_MAP_PAGE: 1626 dma_unmap_page( 1627 &dd->pcidev->dev, 1628 sdma_mapping_addr(descp), 1629 sdma_mapping_len(descp), 1630 DMA_TO_DEVICE); 1631 break; 1632 } 1633 } 1634 1635 /* 1636 * return the mode as indicated by the first 1637 * descriptor in the tx. 1638 */ 1639 static inline u8 ahg_mode(struct sdma_txreq *tx) 1640 { 1641 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK) 1642 >> SDMA_DESC1_HEADER_MODE_SHIFT; 1643 } 1644 1645 /** 1646 * sdma_txclean() - clean tx of mappings, descp *kmalloc's 1647 * @dd: hfi1_devdata for unmapping 1648 * @tx: tx request to clean 1649 * 1650 * This is used in the progress routine to clean the tx or 1651 * by the ULP to toss an in-process tx build. 1652 * 1653 * The code can be called multiple times without issue. 1654 * 1655 */ 1656 void sdma_txclean( 1657 struct hfi1_devdata *dd, 1658 struct sdma_txreq *tx) 1659 { 1660 u16 i; 1661 1662 if (tx->num_desc) { 1663 u8 skip = 0, mode = ahg_mode(tx); 1664 1665 /* unmap first */ 1666 sdma_unmap_desc(dd, &tx->descp[0]); 1667 /* determine number of AHG descriptors to skip */ 1668 if (mode > SDMA_AHG_APPLY_UPDATE1) 1669 skip = mode >> 1; 1670 for (i = 1 + skip; i < tx->num_desc; i++) 1671 sdma_unmap_desc(dd, &tx->descp[i]); 1672 tx->num_desc = 0; 1673 } 1674 kfree(tx->coalesce_buf); 1675 tx->coalesce_buf = NULL; 1676 /* kmalloc'ed descp */ 1677 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) { 1678 tx->desc_limit = ARRAY_SIZE(tx->descs); 1679 kfree(tx->descp); 1680 } 1681 } 1682 1683 static inline u16 sdma_gethead(struct sdma_engine *sde) 1684 { 1685 struct hfi1_devdata *dd = sde->dd; 1686 int use_dmahead; 1687 u16 hwhead; 1688 1689 #ifdef CONFIG_SDMA_VERBOSITY 1690 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 1691 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 1692 #endif 1693 1694 retry: 1695 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) && 1696 (dd->flags & HFI1_HAS_SDMA_TIMEOUT); 1697 hwhead = use_dmahead ? 1698 (u16)le64_to_cpu(*sde->head_dma) : 1699 (u16)read_sde_csr(sde, SD(HEAD)); 1700 1701 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) { 1702 u16 cnt; 1703 u16 swtail; 1704 u16 swhead; 1705 int sane; 1706 1707 swhead = sde->descq_head & sde->sdma_mask; 1708 /* this code is really bad for cache line trading */ 1709 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask; 1710 cnt = sde->descq_cnt; 1711 1712 if (swhead < swtail) 1713 /* not wrapped */ 1714 sane = (hwhead >= swhead) & (hwhead <= swtail); 1715 else if (swhead > swtail) 1716 /* wrapped around */ 1717 sane = ((hwhead >= swhead) && (hwhead < cnt)) || 1718 (hwhead <= swtail); 1719 else 1720 /* empty */ 1721 sane = (hwhead == swhead); 1722 1723 if (unlikely(!sane)) { 1724 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n", 1725 sde->this_idx, 1726 use_dmahead ? "dma" : "kreg", 1727 hwhead, swhead, swtail, cnt); 1728 if (use_dmahead) { 1729 /* try one more time, using csr */ 1730 use_dmahead = 0; 1731 goto retry; 1732 } 1733 /* proceed as if no progress */ 1734 hwhead = swhead; 1735 } 1736 } 1737 return hwhead; 1738 } 1739 1740 /* 1741 * This is called when there are send DMA descriptors that might be 1742 * available. 1743 * 1744 * This is called with head_lock held. 1745 */ 1746 static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail) 1747 { 1748 struct iowait *wait, *nw; 1749 struct iowait *waits[SDMA_WAIT_BATCH_SIZE]; 1750 unsigned i, n = 0, seq; 1751 struct sdma_txreq *stx; 1752 struct hfi1_ibdev *dev = &sde->dd->verbs_dev; 1753 1754 #ifdef CONFIG_SDMA_VERBOSITY 1755 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 1756 slashstrip(__FILE__), __LINE__, __func__); 1757 dd_dev_err(sde->dd, "avail: %u\n", avail); 1758 #endif 1759 1760 do { 1761 seq = read_seqbegin(&dev->iowait_lock); 1762 if (!list_empty(&sde->dmawait)) { 1763 /* at least one item */ 1764 write_seqlock(&dev->iowait_lock); 1765 /* Harvest waiters wanting DMA descriptors */ 1766 list_for_each_entry_safe( 1767 wait, 1768 nw, 1769 &sde->dmawait, 1770 list) { 1771 u16 num_desc = 0; 1772 1773 if (!wait->wakeup) 1774 continue; 1775 if (n == ARRAY_SIZE(waits)) 1776 break; 1777 if (!list_empty(&wait->tx_head)) { 1778 stx = list_first_entry( 1779 &wait->tx_head, 1780 struct sdma_txreq, 1781 list); 1782 num_desc = stx->num_desc; 1783 } 1784 if (num_desc > avail) 1785 break; 1786 avail -= num_desc; 1787 list_del_init(&wait->list); 1788 waits[n++] = wait; 1789 } 1790 write_sequnlock(&dev->iowait_lock); 1791 break; 1792 } 1793 } while (read_seqretry(&dev->iowait_lock, seq)); 1794 1795 for (i = 0; i < n; i++) 1796 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON); 1797 } 1798 1799 /* head_lock must be held */ 1800 static void sdma_make_progress(struct sdma_engine *sde, u64 status) 1801 { 1802 struct sdma_txreq *txp = NULL; 1803 int progress = 0; 1804 u16 hwhead, swhead; 1805 int idle_check_done = 0; 1806 1807 hwhead = sdma_gethead(sde); 1808 1809 /* The reason for some of the complexity of this code is that 1810 * not all descriptors have corresponding txps. So, we have to 1811 * be able to skip over descs until we wander into the range of 1812 * the next txp on the list. 1813 */ 1814 1815 retry: 1816 txp = get_txhead(sde); 1817 swhead = sde->descq_head & sde->sdma_mask; 1818 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); 1819 while (swhead != hwhead) { 1820 /* advance head, wrap if needed */ 1821 swhead = ++sde->descq_head & sde->sdma_mask; 1822 1823 /* if now past this txp's descs, do the callback */ 1824 if (txp && txp->next_descq_idx == swhead) { 1825 /* remove from list */ 1826 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; 1827 complete_tx(sde, txp, SDMA_TXREQ_S_OK); 1828 /* see if there is another txp */ 1829 txp = get_txhead(sde); 1830 } 1831 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); 1832 progress++; 1833 } 1834 1835 /* 1836 * The SDMA idle interrupt is not guaranteed to be ordered with respect 1837 * to updates to the the dma_head location in host memory. The head 1838 * value read might not be fully up to date. If there are pending 1839 * descriptors and the SDMA idle interrupt fired then read from the 1840 * CSR SDMA head instead to get the latest value from the hardware. 1841 * The hardware SDMA head should be read at most once in this invocation 1842 * of sdma_make_progress(..) which is ensured by idle_check_done flag 1843 */ 1844 if ((status & sde->idle_mask) && !idle_check_done) { 1845 u16 swtail; 1846 1847 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask; 1848 if (swtail != hwhead) { 1849 hwhead = (u16)read_sde_csr(sde, SD(HEAD)); 1850 idle_check_done = 1; 1851 goto retry; 1852 } 1853 } 1854 1855 sde->last_status = status; 1856 if (progress) 1857 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 1858 } 1859 1860 /* 1861 * sdma_engine_interrupt() - interrupt handler for engine 1862 * @sde: sdma engine 1863 * @status: sdma interrupt reason 1864 * 1865 * Status is a mask of the 3 possible interrupts for this engine. It will 1866 * contain bits _only_ for this SDMA engine. It will contain at least one 1867 * bit, it may contain more. 1868 */ 1869 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status) 1870 { 1871 trace_hfi1_sdma_engine_interrupt(sde, status); 1872 write_seqlock(&sde->head_lock); 1873 sdma_set_desc_cnt(sde, sdma_desct_intr); 1874 if (status & sde->idle_mask) 1875 sde->idle_int_cnt++; 1876 else if (status & sde->progress_mask) 1877 sde->progress_int_cnt++; 1878 else if (status & sde->int_mask) 1879 sde->sdma_int_cnt++; 1880 sdma_make_progress(sde, status); 1881 write_sequnlock(&sde->head_lock); 1882 } 1883 1884 /** 1885 * sdma_engine_error() - error handler for engine 1886 * @sde: sdma engine 1887 * @status: sdma interrupt reason 1888 */ 1889 void sdma_engine_error(struct sdma_engine *sde, u64 status) 1890 { 1891 unsigned long flags; 1892 1893 #ifdef CONFIG_SDMA_VERBOSITY 1894 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n", 1895 sde->this_idx, 1896 (unsigned long long)status, 1897 sdma_state_names[sde->state.current_state]); 1898 #endif 1899 spin_lock_irqsave(&sde->tail_lock, flags); 1900 write_seqlock(&sde->head_lock); 1901 if (status & ALL_SDMA_ENG_HALT_ERRS) 1902 __sdma_process_event(sde, sdma_event_e60_hw_halted); 1903 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) { 1904 dd_dev_err(sde->dd, 1905 "SDMA (%u) engine error: 0x%llx state %s\n", 1906 sde->this_idx, 1907 (unsigned long long)status, 1908 sdma_state_names[sde->state.current_state]); 1909 dump_sdma_state(sde); 1910 } 1911 write_sequnlock(&sde->head_lock); 1912 spin_unlock_irqrestore(&sde->tail_lock, flags); 1913 } 1914 1915 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op) 1916 { 1917 u64 set_senddmactrl = 0; 1918 u64 clr_senddmactrl = 0; 1919 unsigned long flags; 1920 1921 #ifdef CONFIG_SDMA_VERBOSITY 1922 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n", 1923 sde->this_idx, 1924 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0, 1925 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0, 1926 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0, 1927 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0); 1928 #endif 1929 1930 if (op & SDMA_SENDCTRL_OP_ENABLE) 1931 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); 1932 else 1933 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); 1934 1935 if (op & SDMA_SENDCTRL_OP_INTENABLE) 1936 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); 1937 else 1938 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); 1939 1940 if (op & SDMA_SENDCTRL_OP_HALT) 1941 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); 1942 else 1943 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); 1944 1945 spin_lock_irqsave(&sde->senddmactrl_lock, flags); 1946 1947 sde->p_senddmactrl |= set_senddmactrl; 1948 sde->p_senddmactrl &= ~clr_senddmactrl; 1949 1950 if (op & SDMA_SENDCTRL_OP_CLEANUP) 1951 write_sde_csr(sde, SD(CTRL), 1952 sde->p_senddmactrl | 1953 SD(CTRL_SDMA_CLEANUP_SMASK)); 1954 else 1955 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl); 1956 1957 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags); 1958 1959 #ifdef CONFIG_SDMA_VERBOSITY 1960 sdma_dumpstate(sde); 1961 #endif 1962 } 1963 1964 static void sdma_setlengen(struct sdma_engine *sde) 1965 { 1966 #ifdef CONFIG_SDMA_VERBOSITY 1967 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 1968 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 1969 #endif 1970 1971 /* 1972 * Set SendDmaLenGen and clear-then-set the MSB of the generation 1973 * count to enable generation checking and load the internal 1974 * generation counter. 1975 */ 1976 write_sde_csr(sde, SD(LEN_GEN), 1977 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)); 1978 write_sde_csr(sde, SD(LEN_GEN), 1979 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) | 1980 (4ULL << SD(LEN_GEN_GENERATION_SHIFT))); 1981 } 1982 1983 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail) 1984 { 1985 /* Commit writes to memory and advance the tail on the chip */ 1986 smp_wmb(); /* see get_txhead() */ 1987 writeq(tail, sde->tail_csr); 1988 } 1989 1990 /* 1991 * This is called when changing to state s10_hw_start_up_halt_wait as 1992 * a result of send buffer errors or send DMA descriptor errors. 1993 */ 1994 static void sdma_hw_start_up(struct sdma_engine *sde) 1995 { 1996 u64 reg; 1997 1998 #ifdef CONFIG_SDMA_VERBOSITY 1999 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 2000 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 2001 #endif 2002 2003 sdma_setlengen(sde); 2004 sdma_update_tail(sde, 0); /* Set SendDmaTail */ 2005 *sde->head_dma = 0; 2006 2007 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) << 2008 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT); 2009 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg); 2010 } 2011 2012 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ 2013 (r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 2014 2015 #define SET_STATIC_RATE_CONTROL_SMASK(r) \ 2016 (r |= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 2017 /* 2018 * set_sdma_integrity 2019 * 2020 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'. 2021 */ 2022 static void set_sdma_integrity(struct sdma_engine *sde) 2023 { 2024 struct hfi1_devdata *dd = sde->dd; 2025 u64 reg; 2026 2027 if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY))) 2028 return; 2029 2030 reg = hfi1_pkt_base_sdma_integrity(dd); 2031 2032 if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) 2033 CLEAR_STATIC_RATE_CONTROL_SMASK(reg); 2034 else 2035 SET_STATIC_RATE_CONTROL_SMASK(reg); 2036 2037 write_sde_csr(sde, SD(CHECK_ENABLE), reg); 2038 } 2039 2040 static void init_sdma_regs( 2041 struct sdma_engine *sde, 2042 u32 credits, 2043 uint idle_cnt) 2044 { 2045 u8 opval, opmask; 2046 #ifdef CONFIG_SDMA_VERBOSITY 2047 struct hfi1_devdata *dd = sde->dd; 2048 2049 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", 2050 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 2051 #endif 2052 2053 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys); 2054 sdma_setlengen(sde); 2055 sdma_update_tail(sde, 0); /* Set SendDmaTail */ 2056 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt); 2057 write_sde_csr(sde, SD(DESC_CNT), 0); 2058 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys); 2059 write_sde_csr(sde, SD(MEMORY), 2060 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) | 2061 ((u64)(credits * sde->this_idx) << 2062 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT))); 2063 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull); 2064 set_sdma_integrity(sde); 2065 opmask = OPCODE_CHECK_MASK_DISABLED; 2066 opval = OPCODE_CHECK_VAL_DISABLED; 2067 write_sde_csr(sde, SD(CHECK_OPCODE), 2068 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) | 2069 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT)); 2070 } 2071 2072 #ifdef CONFIG_SDMA_VERBOSITY 2073 2074 #define sdma_dumpstate_helper0(reg) do { \ 2075 csr = read_csr(sde->dd, reg); \ 2076 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \ 2077 } while (0) 2078 2079 #define sdma_dumpstate_helper(reg) do { \ 2080 csr = read_sde_csr(sde, reg); \ 2081 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \ 2082 #reg, sde->this_idx, csr); \ 2083 } while (0) 2084 2085 #define sdma_dumpstate_helper2(reg) do { \ 2086 csr = read_csr(sde->dd, reg + (8 * i)); \ 2087 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \ 2088 #reg, i, csr); \ 2089 } while (0) 2090 2091 void sdma_dumpstate(struct sdma_engine *sde) 2092 { 2093 u64 csr; 2094 unsigned i; 2095 2096 sdma_dumpstate_helper(SD(CTRL)); 2097 sdma_dumpstate_helper(SD(STATUS)); 2098 sdma_dumpstate_helper0(SD(ERR_STATUS)); 2099 sdma_dumpstate_helper0(SD(ERR_MASK)); 2100 sdma_dumpstate_helper(SD(ENG_ERR_STATUS)); 2101 sdma_dumpstate_helper(SD(ENG_ERR_MASK)); 2102 2103 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) { 2104 sdma_dumpstate_helper2(CCE_INT_STATUS); 2105 sdma_dumpstate_helper2(CCE_INT_MASK); 2106 sdma_dumpstate_helper2(CCE_INT_BLOCKED); 2107 } 2108 2109 sdma_dumpstate_helper(SD(TAIL)); 2110 sdma_dumpstate_helper(SD(HEAD)); 2111 sdma_dumpstate_helper(SD(PRIORITY_THLD)); 2112 sdma_dumpstate_helper(SD(IDLE_CNT)); 2113 sdma_dumpstate_helper(SD(RELOAD_CNT)); 2114 sdma_dumpstate_helper(SD(DESC_CNT)); 2115 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT)); 2116 sdma_dumpstate_helper(SD(MEMORY)); 2117 sdma_dumpstate_helper0(SD(ENGINES)); 2118 sdma_dumpstate_helper0(SD(MEM_SIZE)); 2119 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */ 2120 sdma_dumpstate_helper(SD(BASE_ADDR)); 2121 sdma_dumpstate_helper(SD(LEN_GEN)); 2122 sdma_dumpstate_helper(SD(HEAD_ADDR)); 2123 sdma_dumpstate_helper(SD(CHECK_ENABLE)); 2124 sdma_dumpstate_helper(SD(CHECK_VL)); 2125 sdma_dumpstate_helper(SD(CHECK_JOB_KEY)); 2126 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY)); 2127 sdma_dumpstate_helper(SD(CHECK_SLID)); 2128 sdma_dumpstate_helper(SD(CHECK_OPCODE)); 2129 } 2130 #endif 2131 2132 static void dump_sdma_state(struct sdma_engine *sde) 2133 { 2134 struct hw_sdma_desc *descq; 2135 struct hw_sdma_desc *descqp; 2136 u64 desc[2]; 2137 u64 addr; 2138 u8 gen; 2139 u16 len; 2140 u16 head, tail, cnt; 2141 2142 head = sde->descq_head & sde->sdma_mask; 2143 tail = sde->descq_tail & sde->sdma_mask; 2144 cnt = sdma_descq_freecnt(sde); 2145 descq = sde->descq; 2146 2147 dd_dev_err(sde->dd, 2148 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n", 2149 sde->this_idx, head, tail, cnt, 2150 !list_empty(&sde->flushlist)); 2151 2152 /* print info for each entry in the descriptor queue */ 2153 while (head != tail) { 2154 char flags[6] = { 'x', 'x', 'x', 'x', 0 }; 2155 2156 descqp = &sde->descq[head]; 2157 desc[0] = le64_to_cpu(descqp->qw[0]); 2158 desc[1] = le64_to_cpu(descqp->qw[1]); 2159 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; 2160 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 2161 'H' : '-'; 2162 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; 2163 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; 2164 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) 2165 & SDMA_DESC0_PHY_ADDR_MASK; 2166 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) 2167 & SDMA_DESC1_GENERATION_MASK; 2168 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) 2169 & SDMA_DESC0_BYTE_COUNT_MASK; 2170 dd_dev_err(sde->dd, 2171 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", 2172 head, flags, addr, gen, len); 2173 dd_dev_err(sde->dd, 2174 "\tdesc0:0x%016llx desc1 0x%016llx\n", 2175 desc[0], desc[1]); 2176 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) 2177 dd_dev_err(sde->dd, 2178 "\taidx: %u amode: %u alen: %u\n", 2179 (u8)((desc[1] & 2180 SDMA_DESC1_HEADER_INDEX_SMASK) >> 2181 SDMA_DESC1_HEADER_INDEX_SHIFT), 2182 (u8)((desc[1] & 2183 SDMA_DESC1_HEADER_MODE_SMASK) >> 2184 SDMA_DESC1_HEADER_MODE_SHIFT), 2185 (u8)((desc[1] & 2186 SDMA_DESC1_HEADER_DWS_SMASK) >> 2187 SDMA_DESC1_HEADER_DWS_SHIFT)); 2188 head++; 2189 head &= sde->sdma_mask; 2190 } 2191 } 2192 2193 #define SDE_FMT \ 2194 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n" 2195 /** 2196 * sdma_seqfile_dump_sde() - debugfs dump of sde 2197 * @s: seq file 2198 * @sde: send dma engine to dump 2199 * 2200 * This routine dumps the sde to the indicated seq file. 2201 */ 2202 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde) 2203 { 2204 u16 head, tail; 2205 struct hw_sdma_desc *descqp; 2206 u64 desc[2]; 2207 u64 addr; 2208 u8 gen; 2209 u16 len; 2210 2211 head = sde->descq_head & sde->sdma_mask; 2212 tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask; 2213 seq_printf(s, SDE_FMT, sde->this_idx, 2214 sde->cpu, 2215 sdma_state_name(sde->state.current_state), 2216 (unsigned long long)read_sde_csr(sde, SD(CTRL)), 2217 (unsigned long long)read_sde_csr(sde, SD(STATUS)), 2218 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)), 2219 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail, 2220 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head, 2221 (unsigned long long)le64_to_cpu(*sde->head_dma), 2222 (unsigned long long)read_sde_csr(sde, SD(MEMORY)), 2223 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)), 2224 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)), 2225 (unsigned long long)sde->last_status, 2226 (unsigned long long)sde->ahg_bits, 2227 sde->tx_tail, 2228 sde->tx_head, 2229 sde->descq_tail, 2230 sde->descq_head, 2231 !list_empty(&sde->flushlist), 2232 sde->descq_full_count, 2233 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID)); 2234 2235 /* print info for each entry in the descriptor queue */ 2236 while (head != tail) { 2237 char flags[6] = { 'x', 'x', 'x', 'x', 0 }; 2238 2239 descqp = &sde->descq[head]; 2240 desc[0] = le64_to_cpu(descqp->qw[0]); 2241 desc[1] = le64_to_cpu(descqp->qw[1]); 2242 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; 2243 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 2244 'H' : '-'; 2245 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; 2246 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; 2247 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) 2248 & SDMA_DESC0_PHY_ADDR_MASK; 2249 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) 2250 & SDMA_DESC1_GENERATION_MASK; 2251 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) 2252 & SDMA_DESC0_BYTE_COUNT_MASK; 2253 seq_printf(s, 2254 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", 2255 head, flags, addr, gen, len); 2256 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) 2257 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n", 2258 (u8)((desc[1] & 2259 SDMA_DESC1_HEADER_INDEX_SMASK) >> 2260 SDMA_DESC1_HEADER_INDEX_SHIFT), 2261 (u8)((desc[1] & 2262 SDMA_DESC1_HEADER_MODE_SMASK) >> 2263 SDMA_DESC1_HEADER_MODE_SHIFT)); 2264 head = (head + 1) & sde->sdma_mask; 2265 } 2266 } 2267 2268 /* 2269 * add the generation number into 2270 * the qw1 and return 2271 */ 2272 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1) 2273 { 2274 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3; 2275 2276 qw1 &= ~SDMA_DESC1_GENERATION_SMASK; 2277 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK) 2278 << SDMA_DESC1_GENERATION_SHIFT; 2279 return qw1; 2280 } 2281 2282 /* 2283 * This routine submits the indicated tx 2284 * 2285 * Space has already been guaranteed and 2286 * tail side of ring is locked. 2287 * 2288 * The hardware tail update is done 2289 * in the caller and that is facilitated 2290 * by returning the new tail. 2291 * 2292 * There is special case logic for ahg 2293 * to not add the generation number for 2294 * up to 2 descriptors that follow the 2295 * first descriptor. 2296 * 2297 */ 2298 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx) 2299 { 2300 int i; 2301 u16 tail; 2302 struct sdma_desc *descp = tx->descp; 2303 u8 skip = 0, mode = ahg_mode(tx); 2304 2305 tail = sde->descq_tail & sde->sdma_mask; 2306 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); 2307 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1])); 2308 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1], 2309 tail, &sde->descq[tail]); 2310 tail = ++sde->descq_tail & sde->sdma_mask; 2311 descp++; 2312 if (mode > SDMA_AHG_APPLY_UPDATE1) 2313 skip = mode >> 1; 2314 for (i = 1; i < tx->num_desc; i++, descp++) { 2315 u64 qw1; 2316 2317 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); 2318 if (skip) { 2319 /* edits don't have generation */ 2320 qw1 = descp->qw[1]; 2321 skip--; 2322 } else { 2323 /* replace generation with real one for non-edits */ 2324 qw1 = add_gen(sde, descp->qw[1]); 2325 } 2326 sde->descq[tail].qw[1] = cpu_to_le64(qw1); 2327 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1, 2328 tail, &sde->descq[tail]); 2329 tail = ++sde->descq_tail & sde->sdma_mask; 2330 } 2331 tx->next_descq_idx = tail; 2332 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2333 tx->sn = sde->tail_sn++; 2334 trace_hfi1_sdma_in_sn(sde, tx->sn); 2335 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]); 2336 #endif 2337 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx; 2338 sde->desc_avail -= tx->num_desc; 2339 return tail; 2340 } 2341 2342 /* 2343 * Check for progress 2344 */ 2345 static int sdma_check_progress( 2346 struct sdma_engine *sde, 2347 struct iowait *wait, 2348 struct sdma_txreq *tx) 2349 { 2350 int ret; 2351 2352 sde->desc_avail = sdma_descq_freecnt(sde); 2353 if (tx->num_desc <= sde->desc_avail) 2354 return -EAGAIN; 2355 /* pulse the head_lock */ 2356 if (wait && wait->sleep) { 2357 unsigned seq; 2358 2359 seq = raw_seqcount_begin( 2360 (const seqcount_t *)&sde->head_lock.seqcount); 2361 ret = wait->sleep(sde, wait, tx, seq); 2362 if (ret == -EAGAIN) 2363 sde->desc_avail = sdma_descq_freecnt(sde); 2364 } else { 2365 ret = -EBUSY; 2366 } 2367 return ret; 2368 } 2369 2370 /** 2371 * sdma_send_txreq() - submit a tx req to ring 2372 * @sde: sdma engine to use 2373 * @wait: wait structure to use when full (may be NULL) 2374 * @tx: sdma_txreq to submit 2375 * 2376 * The call submits the tx into the ring. If a iowait structure is non-NULL 2377 * the packet will be queued to the list in wait. 2378 * 2379 * Return: 2380 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in 2381 * ring (wait == NULL) 2382 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state 2383 */ 2384 int sdma_send_txreq(struct sdma_engine *sde, 2385 struct iowait *wait, 2386 struct sdma_txreq *tx) 2387 { 2388 int ret = 0; 2389 u16 tail; 2390 unsigned long flags; 2391 2392 /* user should have supplied entire packet */ 2393 if (unlikely(tx->tlen)) 2394 return -EINVAL; 2395 tx->wait = wait; 2396 spin_lock_irqsave(&sde->tail_lock, flags); 2397 retry: 2398 if (unlikely(!__sdma_running(sde))) 2399 goto unlock_noconn; 2400 if (unlikely(tx->num_desc > sde->desc_avail)) 2401 goto nodesc; 2402 tail = submit_tx(sde, tx); 2403 if (wait) 2404 iowait_sdma_inc(wait); 2405 sdma_update_tail(sde, tail); 2406 unlock: 2407 spin_unlock_irqrestore(&sde->tail_lock, flags); 2408 return ret; 2409 unlock_noconn: 2410 if (wait) 2411 iowait_sdma_inc(wait); 2412 tx->next_descq_idx = 0; 2413 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2414 tx->sn = sde->tail_sn++; 2415 trace_hfi1_sdma_in_sn(sde, tx->sn); 2416 #endif 2417 spin_lock(&sde->flushlist_lock); 2418 list_add_tail(&tx->list, &sde->flushlist); 2419 spin_unlock(&sde->flushlist_lock); 2420 if (wait) { 2421 wait->tx_count++; 2422 wait->count += tx->num_desc; 2423 } 2424 schedule_work(&sde->flush_worker); 2425 ret = -ECOMM; 2426 goto unlock; 2427 nodesc: 2428 ret = sdma_check_progress(sde, wait, tx); 2429 if (ret == -EAGAIN) { 2430 ret = 0; 2431 goto retry; 2432 } 2433 sde->descq_full_count++; 2434 goto unlock; 2435 } 2436 2437 /** 2438 * sdma_send_txlist() - submit a list of tx req to ring 2439 * @sde: sdma engine to use 2440 * @wait: wait structure to use when full (may be NULL) 2441 * @tx_list: list of sdma_txreqs to submit 2442 * @count: pointer to a u32 which, after return will contain the total number of 2443 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs 2444 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs 2445 * which are added to SDMA engine flush list if the SDMA engine state is 2446 * not running. 2447 * 2448 * The call submits the list into the ring. 2449 * 2450 * If the iowait structure is non-NULL and not equal to the iowait list 2451 * the unprocessed part of the list will be appended to the list in wait. 2452 * 2453 * In all cases, the tx_list will be updated so the head of the tx_list is 2454 * the list of descriptors that have yet to be transmitted. 2455 * 2456 * The intent of this call is to provide a more efficient 2457 * way of submitting multiple packets to SDMA while holding the tail 2458 * side locking. 2459 * 2460 * Return: 2461 * 0 - Success, 2462 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL) 2463 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state 2464 */ 2465 int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait, 2466 struct list_head *tx_list, u32 *count_out) 2467 { 2468 struct sdma_txreq *tx, *tx_next; 2469 int ret = 0; 2470 unsigned long flags; 2471 u16 tail = INVALID_TAIL; 2472 u32 submit_count = 0, flush_count = 0, total_count; 2473 2474 spin_lock_irqsave(&sde->tail_lock, flags); 2475 retry: 2476 list_for_each_entry_safe(tx, tx_next, tx_list, list) { 2477 tx->wait = wait; 2478 if (unlikely(!__sdma_running(sde))) 2479 goto unlock_noconn; 2480 if (unlikely(tx->num_desc > sde->desc_avail)) 2481 goto nodesc; 2482 if (unlikely(tx->tlen)) { 2483 ret = -EINVAL; 2484 goto update_tail; 2485 } 2486 list_del_init(&tx->list); 2487 tail = submit_tx(sde, tx); 2488 submit_count++; 2489 if (tail != INVALID_TAIL && 2490 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) { 2491 sdma_update_tail(sde, tail); 2492 tail = INVALID_TAIL; 2493 } 2494 } 2495 update_tail: 2496 total_count = submit_count + flush_count; 2497 if (wait) 2498 iowait_sdma_add(wait, total_count); 2499 if (tail != INVALID_TAIL) 2500 sdma_update_tail(sde, tail); 2501 spin_unlock_irqrestore(&sde->tail_lock, flags); 2502 *count_out = total_count; 2503 return ret; 2504 unlock_noconn: 2505 spin_lock(&sde->flushlist_lock); 2506 list_for_each_entry_safe(tx, tx_next, tx_list, list) { 2507 tx->wait = wait; 2508 list_del_init(&tx->list); 2509 tx->next_descq_idx = 0; 2510 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2511 tx->sn = sde->tail_sn++; 2512 trace_hfi1_sdma_in_sn(sde, tx->sn); 2513 #endif 2514 list_add_tail(&tx->list, &sde->flushlist); 2515 flush_count++; 2516 if (wait) { 2517 wait->tx_count++; 2518 wait->count += tx->num_desc; 2519 } 2520 } 2521 spin_unlock(&sde->flushlist_lock); 2522 schedule_work(&sde->flush_worker); 2523 ret = -ECOMM; 2524 goto update_tail; 2525 nodesc: 2526 ret = sdma_check_progress(sde, wait, tx); 2527 if (ret == -EAGAIN) { 2528 ret = 0; 2529 goto retry; 2530 } 2531 sde->descq_full_count++; 2532 goto update_tail; 2533 } 2534 2535 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event) 2536 { 2537 unsigned long flags; 2538 2539 spin_lock_irqsave(&sde->tail_lock, flags); 2540 write_seqlock(&sde->head_lock); 2541 2542 __sdma_process_event(sde, event); 2543 2544 if (sde->state.current_state == sdma_state_s99_running) 2545 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 2546 2547 write_sequnlock(&sde->head_lock); 2548 spin_unlock_irqrestore(&sde->tail_lock, flags); 2549 } 2550 2551 static void __sdma_process_event(struct sdma_engine *sde, 2552 enum sdma_events event) 2553 { 2554 struct sdma_state *ss = &sde->state; 2555 int need_progress = 0; 2556 2557 /* CONFIG SDMA temporary */ 2558 #ifdef CONFIG_SDMA_VERBOSITY 2559 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx, 2560 sdma_state_names[ss->current_state], 2561 sdma_event_names[event]); 2562 #endif 2563 2564 switch (ss->current_state) { 2565 case sdma_state_s00_hw_down: 2566 switch (event) { 2567 case sdma_event_e00_go_hw_down: 2568 break; 2569 case sdma_event_e30_go_running: 2570 /* 2571 * If down, but running requested (usually result 2572 * of link up, then we need to start up. 2573 * This can happen when hw down is requested while 2574 * bringing the link up with traffic active on 2575 * 7220, e.g. 2576 */ 2577 ss->go_s99_running = 1; 2578 /* fall through and start dma engine */ 2579 case sdma_event_e10_go_hw_start: 2580 /* This reference means the state machine is started */ 2581 sdma_get(&sde->state); 2582 sdma_set_state(sde, 2583 sdma_state_s10_hw_start_up_halt_wait); 2584 break; 2585 case sdma_event_e15_hw_halt_done: 2586 break; 2587 case sdma_event_e25_hw_clean_up_done: 2588 break; 2589 case sdma_event_e40_sw_cleaned: 2590 sdma_sw_tear_down(sde); 2591 break; 2592 case sdma_event_e50_hw_cleaned: 2593 break; 2594 case sdma_event_e60_hw_halted: 2595 break; 2596 case sdma_event_e70_go_idle: 2597 break; 2598 case sdma_event_e80_hw_freeze: 2599 break; 2600 case sdma_event_e81_hw_frozen: 2601 break; 2602 case sdma_event_e82_hw_unfreeze: 2603 break; 2604 case sdma_event_e85_link_down: 2605 break; 2606 case sdma_event_e90_sw_halted: 2607 break; 2608 } 2609 break; 2610 2611 case sdma_state_s10_hw_start_up_halt_wait: 2612 switch (event) { 2613 case sdma_event_e00_go_hw_down: 2614 sdma_set_state(sde, sdma_state_s00_hw_down); 2615 sdma_sw_tear_down(sde); 2616 break; 2617 case sdma_event_e10_go_hw_start: 2618 break; 2619 case sdma_event_e15_hw_halt_done: 2620 sdma_set_state(sde, 2621 sdma_state_s15_hw_start_up_clean_wait); 2622 sdma_start_hw_clean_up(sde); 2623 break; 2624 case sdma_event_e25_hw_clean_up_done: 2625 break; 2626 case sdma_event_e30_go_running: 2627 ss->go_s99_running = 1; 2628 break; 2629 case sdma_event_e40_sw_cleaned: 2630 break; 2631 case sdma_event_e50_hw_cleaned: 2632 break; 2633 case sdma_event_e60_hw_halted: 2634 schedule_work(&sde->err_halt_worker); 2635 break; 2636 case sdma_event_e70_go_idle: 2637 ss->go_s99_running = 0; 2638 break; 2639 case sdma_event_e80_hw_freeze: 2640 break; 2641 case sdma_event_e81_hw_frozen: 2642 break; 2643 case sdma_event_e82_hw_unfreeze: 2644 break; 2645 case sdma_event_e85_link_down: 2646 break; 2647 case sdma_event_e90_sw_halted: 2648 break; 2649 } 2650 break; 2651 2652 case sdma_state_s15_hw_start_up_clean_wait: 2653 switch (event) { 2654 case sdma_event_e00_go_hw_down: 2655 sdma_set_state(sde, sdma_state_s00_hw_down); 2656 sdma_sw_tear_down(sde); 2657 break; 2658 case sdma_event_e10_go_hw_start: 2659 break; 2660 case sdma_event_e15_hw_halt_done: 2661 break; 2662 case sdma_event_e25_hw_clean_up_done: 2663 sdma_hw_start_up(sde); 2664 sdma_set_state(sde, ss->go_s99_running ? 2665 sdma_state_s99_running : 2666 sdma_state_s20_idle); 2667 break; 2668 case sdma_event_e30_go_running: 2669 ss->go_s99_running = 1; 2670 break; 2671 case sdma_event_e40_sw_cleaned: 2672 break; 2673 case sdma_event_e50_hw_cleaned: 2674 break; 2675 case sdma_event_e60_hw_halted: 2676 break; 2677 case sdma_event_e70_go_idle: 2678 ss->go_s99_running = 0; 2679 break; 2680 case sdma_event_e80_hw_freeze: 2681 break; 2682 case sdma_event_e81_hw_frozen: 2683 break; 2684 case sdma_event_e82_hw_unfreeze: 2685 break; 2686 case sdma_event_e85_link_down: 2687 break; 2688 case sdma_event_e90_sw_halted: 2689 break; 2690 } 2691 break; 2692 2693 case sdma_state_s20_idle: 2694 switch (event) { 2695 case sdma_event_e00_go_hw_down: 2696 sdma_set_state(sde, sdma_state_s00_hw_down); 2697 sdma_sw_tear_down(sde); 2698 break; 2699 case sdma_event_e10_go_hw_start: 2700 break; 2701 case sdma_event_e15_hw_halt_done: 2702 break; 2703 case sdma_event_e25_hw_clean_up_done: 2704 break; 2705 case sdma_event_e30_go_running: 2706 sdma_set_state(sde, sdma_state_s99_running); 2707 ss->go_s99_running = 1; 2708 break; 2709 case sdma_event_e40_sw_cleaned: 2710 break; 2711 case sdma_event_e50_hw_cleaned: 2712 break; 2713 case sdma_event_e60_hw_halted: 2714 sdma_set_state(sde, sdma_state_s50_hw_halt_wait); 2715 schedule_work(&sde->err_halt_worker); 2716 break; 2717 case sdma_event_e70_go_idle: 2718 break; 2719 case sdma_event_e85_link_down: 2720 /* fall through */ 2721 case sdma_event_e80_hw_freeze: 2722 sdma_set_state(sde, sdma_state_s80_hw_freeze); 2723 atomic_dec(&sde->dd->sdma_unfreeze_count); 2724 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 2725 break; 2726 case sdma_event_e81_hw_frozen: 2727 break; 2728 case sdma_event_e82_hw_unfreeze: 2729 break; 2730 case sdma_event_e90_sw_halted: 2731 break; 2732 } 2733 break; 2734 2735 case sdma_state_s30_sw_clean_up_wait: 2736 switch (event) { 2737 case sdma_event_e00_go_hw_down: 2738 sdma_set_state(sde, sdma_state_s00_hw_down); 2739 break; 2740 case sdma_event_e10_go_hw_start: 2741 break; 2742 case sdma_event_e15_hw_halt_done: 2743 break; 2744 case sdma_event_e25_hw_clean_up_done: 2745 break; 2746 case sdma_event_e30_go_running: 2747 ss->go_s99_running = 1; 2748 break; 2749 case sdma_event_e40_sw_cleaned: 2750 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait); 2751 sdma_start_hw_clean_up(sde); 2752 break; 2753 case sdma_event_e50_hw_cleaned: 2754 break; 2755 case sdma_event_e60_hw_halted: 2756 break; 2757 case sdma_event_e70_go_idle: 2758 ss->go_s99_running = 0; 2759 break; 2760 case sdma_event_e80_hw_freeze: 2761 break; 2762 case sdma_event_e81_hw_frozen: 2763 break; 2764 case sdma_event_e82_hw_unfreeze: 2765 break; 2766 case sdma_event_e85_link_down: 2767 ss->go_s99_running = 0; 2768 break; 2769 case sdma_event_e90_sw_halted: 2770 break; 2771 } 2772 break; 2773 2774 case sdma_state_s40_hw_clean_up_wait: 2775 switch (event) { 2776 case sdma_event_e00_go_hw_down: 2777 sdma_set_state(sde, sdma_state_s00_hw_down); 2778 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2779 break; 2780 case sdma_event_e10_go_hw_start: 2781 break; 2782 case sdma_event_e15_hw_halt_done: 2783 break; 2784 case sdma_event_e25_hw_clean_up_done: 2785 sdma_hw_start_up(sde); 2786 sdma_set_state(sde, ss->go_s99_running ? 2787 sdma_state_s99_running : 2788 sdma_state_s20_idle); 2789 break; 2790 case sdma_event_e30_go_running: 2791 ss->go_s99_running = 1; 2792 break; 2793 case sdma_event_e40_sw_cleaned: 2794 break; 2795 case sdma_event_e50_hw_cleaned: 2796 break; 2797 case sdma_event_e60_hw_halted: 2798 break; 2799 case sdma_event_e70_go_idle: 2800 ss->go_s99_running = 0; 2801 break; 2802 case sdma_event_e80_hw_freeze: 2803 break; 2804 case sdma_event_e81_hw_frozen: 2805 break; 2806 case sdma_event_e82_hw_unfreeze: 2807 break; 2808 case sdma_event_e85_link_down: 2809 ss->go_s99_running = 0; 2810 break; 2811 case sdma_event_e90_sw_halted: 2812 break; 2813 } 2814 break; 2815 2816 case sdma_state_s50_hw_halt_wait: 2817 switch (event) { 2818 case sdma_event_e00_go_hw_down: 2819 sdma_set_state(sde, sdma_state_s00_hw_down); 2820 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2821 break; 2822 case sdma_event_e10_go_hw_start: 2823 break; 2824 case sdma_event_e15_hw_halt_done: 2825 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); 2826 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2827 break; 2828 case sdma_event_e25_hw_clean_up_done: 2829 break; 2830 case sdma_event_e30_go_running: 2831 ss->go_s99_running = 1; 2832 break; 2833 case sdma_event_e40_sw_cleaned: 2834 break; 2835 case sdma_event_e50_hw_cleaned: 2836 break; 2837 case sdma_event_e60_hw_halted: 2838 schedule_work(&sde->err_halt_worker); 2839 break; 2840 case sdma_event_e70_go_idle: 2841 ss->go_s99_running = 0; 2842 break; 2843 case sdma_event_e80_hw_freeze: 2844 break; 2845 case sdma_event_e81_hw_frozen: 2846 break; 2847 case sdma_event_e82_hw_unfreeze: 2848 break; 2849 case sdma_event_e85_link_down: 2850 ss->go_s99_running = 0; 2851 break; 2852 case sdma_event_e90_sw_halted: 2853 break; 2854 } 2855 break; 2856 2857 case sdma_state_s60_idle_halt_wait: 2858 switch (event) { 2859 case sdma_event_e00_go_hw_down: 2860 sdma_set_state(sde, sdma_state_s00_hw_down); 2861 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2862 break; 2863 case sdma_event_e10_go_hw_start: 2864 break; 2865 case sdma_event_e15_hw_halt_done: 2866 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); 2867 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2868 break; 2869 case sdma_event_e25_hw_clean_up_done: 2870 break; 2871 case sdma_event_e30_go_running: 2872 ss->go_s99_running = 1; 2873 break; 2874 case sdma_event_e40_sw_cleaned: 2875 break; 2876 case sdma_event_e50_hw_cleaned: 2877 break; 2878 case sdma_event_e60_hw_halted: 2879 schedule_work(&sde->err_halt_worker); 2880 break; 2881 case sdma_event_e70_go_idle: 2882 ss->go_s99_running = 0; 2883 break; 2884 case sdma_event_e80_hw_freeze: 2885 break; 2886 case sdma_event_e81_hw_frozen: 2887 break; 2888 case sdma_event_e82_hw_unfreeze: 2889 break; 2890 case sdma_event_e85_link_down: 2891 break; 2892 case sdma_event_e90_sw_halted: 2893 break; 2894 } 2895 break; 2896 2897 case sdma_state_s80_hw_freeze: 2898 switch (event) { 2899 case sdma_event_e00_go_hw_down: 2900 sdma_set_state(sde, sdma_state_s00_hw_down); 2901 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2902 break; 2903 case sdma_event_e10_go_hw_start: 2904 break; 2905 case sdma_event_e15_hw_halt_done: 2906 break; 2907 case sdma_event_e25_hw_clean_up_done: 2908 break; 2909 case sdma_event_e30_go_running: 2910 ss->go_s99_running = 1; 2911 break; 2912 case sdma_event_e40_sw_cleaned: 2913 break; 2914 case sdma_event_e50_hw_cleaned: 2915 break; 2916 case sdma_event_e60_hw_halted: 2917 break; 2918 case sdma_event_e70_go_idle: 2919 ss->go_s99_running = 0; 2920 break; 2921 case sdma_event_e80_hw_freeze: 2922 break; 2923 case sdma_event_e81_hw_frozen: 2924 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean); 2925 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2926 break; 2927 case sdma_event_e82_hw_unfreeze: 2928 break; 2929 case sdma_event_e85_link_down: 2930 break; 2931 case sdma_event_e90_sw_halted: 2932 break; 2933 } 2934 break; 2935 2936 case sdma_state_s82_freeze_sw_clean: 2937 switch (event) { 2938 case sdma_event_e00_go_hw_down: 2939 sdma_set_state(sde, sdma_state_s00_hw_down); 2940 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2941 break; 2942 case sdma_event_e10_go_hw_start: 2943 break; 2944 case sdma_event_e15_hw_halt_done: 2945 break; 2946 case sdma_event_e25_hw_clean_up_done: 2947 break; 2948 case sdma_event_e30_go_running: 2949 ss->go_s99_running = 1; 2950 break; 2951 case sdma_event_e40_sw_cleaned: 2952 /* notify caller this engine is done cleaning */ 2953 atomic_dec(&sde->dd->sdma_unfreeze_count); 2954 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 2955 break; 2956 case sdma_event_e50_hw_cleaned: 2957 break; 2958 case sdma_event_e60_hw_halted: 2959 break; 2960 case sdma_event_e70_go_idle: 2961 ss->go_s99_running = 0; 2962 break; 2963 case sdma_event_e80_hw_freeze: 2964 break; 2965 case sdma_event_e81_hw_frozen: 2966 break; 2967 case sdma_event_e82_hw_unfreeze: 2968 sdma_hw_start_up(sde); 2969 sdma_set_state(sde, ss->go_s99_running ? 2970 sdma_state_s99_running : 2971 sdma_state_s20_idle); 2972 break; 2973 case sdma_event_e85_link_down: 2974 break; 2975 case sdma_event_e90_sw_halted: 2976 break; 2977 } 2978 break; 2979 2980 case sdma_state_s99_running: 2981 switch (event) { 2982 case sdma_event_e00_go_hw_down: 2983 sdma_set_state(sde, sdma_state_s00_hw_down); 2984 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2985 break; 2986 case sdma_event_e10_go_hw_start: 2987 break; 2988 case sdma_event_e15_hw_halt_done: 2989 break; 2990 case sdma_event_e25_hw_clean_up_done: 2991 break; 2992 case sdma_event_e30_go_running: 2993 break; 2994 case sdma_event_e40_sw_cleaned: 2995 break; 2996 case sdma_event_e50_hw_cleaned: 2997 break; 2998 case sdma_event_e60_hw_halted: 2999 need_progress = 1; 3000 sdma_err_progress_check_schedule(sde); 3001 case sdma_event_e90_sw_halted: 3002 /* 3003 * SW initiated halt does not perform engines 3004 * progress check 3005 */ 3006 sdma_set_state(sde, sdma_state_s50_hw_halt_wait); 3007 schedule_work(&sde->err_halt_worker); 3008 break; 3009 case sdma_event_e70_go_idle: 3010 sdma_set_state(sde, sdma_state_s60_idle_halt_wait); 3011 break; 3012 case sdma_event_e85_link_down: 3013 ss->go_s99_running = 0; 3014 /* fall through */ 3015 case sdma_event_e80_hw_freeze: 3016 sdma_set_state(sde, sdma_state_s80_hw_freeze); 3017 atomic_dec(&sde->dd->sdma_unfreeze_count); 3018 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 3019 break; 3020 case sdma_event_e81_hw_frozen: 3021 break; 3022 case sdma_event_e82_hw_unfreeze: 3023 break; 3024 } 3025 break; 3026 } 3027 3028 ss->last_event = event; 3029 if (need_progress) 3030 sdma_make_progress(sde, 0); 3031 } 3032 3033 /* 3034 * _extend_sdma_tx_descs() - helper to extend txreq 3035 * 3036 * This is called once the initial nominal allocation 3037 * of descriptors in the sdma_txreq is exhausted. 3038 * 3039 * The code will bump the allocation up to the max 3040 * of MAX_DESC (64) descriptors. There doesn't seem 3041 * much point in an interim step. The last descriptor 3042 * is reserved for coalesce buffer in order to support 3043 * cases where input packet has >MAX_DESC iovecs. 3044 * 3045 */ 3046 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) 3047 { 3048 int i; 3049 3050 /* Handle last descriptor */ 3051 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) { 3052 /* if tlen is 0, it is for padding, release last descriptor */ 3053 if (!tx->tlen) { 3054 tx->desc_limit = MAX_DESC; 3055 } else if (!tx->coalesce_buf) { 3056 /* allocate coalesce buffer with space for padding */ 3057 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32), 3058 GFP_ATOMIC); 3059 if (!tx->coalesce_buf) 3060 goto enomem; 3061 tx->coalesce_idx = 0; 3062 } 3063 return 0; 3064 } 3065 3066 if (unlikely(tx->num_desc == MAX_DESC)) 3067 goto enomem; 3068 3069 tx->descp = kmalloc_array( 3070 MAX_DESC, 3071 sizeof(struct sdma_desc), 3072 GFP_ATOMIC); 3073 if (!tx->descp) 3074 goto enomem; 3075 3076 /* reserve last descriptor for coalescing */ 3077 tx->desc_limit = MAX_DESC - 1; 3078 /* copy ones already built */ 3079 for (i = 0; i < tx->num_desc; i++) 3080 tx->descp[i] = tx->descs[i]; 3081 return 0; 3082 enomem: 3083 sdma_txclean(dd, tx); 3084 return -ENOMEM; 3085 } 3086 3087 /* 3088 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors 3089 * 3090 * This is called once the initial nominal allocation of descriptors 3091 * in the sdma_txreq is exhausted. 3092 * 3093 * This function calls _extend_sdma_tx_descs to extend or allocate 3094 * coalesce buffer. If there is a allocated coalesce buffer, it will 3095 * copy the input packet data into the coalesce buffer. It also adds 3096 * coalesce buffer descriptor once when whole packet is received. 3097 * 3098 * Return: 3099 * <0 - error 3100 * 0 - coalescing, don't populate descriptor 3101 * 1 - continue with populating descriptor 3102 */ 3103 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx, 3104 int type, void *kvaddr, struct page *page, 3105 unsigned long offset, u16 len) 3106 { 3107 int pad_len, rval; 3108 dma_addr_t addr; 3109 3110 rval = _extend_sdma_tx_descs(dd, tx); 3111 if (rval) { 3112 sdma_txclean(dd, tx); 3113 return rval; 3114 } 3115 3116 /* If coalesce buffer is allocated, copy data into it */ 3117 if (tx->coalesce_buf) { 3118 if (type == SDMA_MAP_NONE) { 3119 sdma_txclean(dd, tx); 3120 return -EINVAL; 3121 } 3122 3123 if (type == SDMA_MAP_PAGE) { 3124 kvaddr = kmap(page); 3125 kvaddr += offset; 3126 } else if (WARN_ON(!kvaddr)) { 3127 sdma_txclean(dd, tx); 3128 return -EINVAL; 3129 } 3130 3131 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len); 3132 tx->coalesce_idx += len; 3133 if (type == SDMA_MAP_PAGE) 3134 kunmap(page); 3135 3136 /* If there is more data, return */ 3137 if (tx->tlen - tx->coalesce_idx) 3138 return 0; 3139 3140 /* Whole packet is received; add any padding */ 3141 pad_len = tx->packet_len & (sizeof(u32) - 1); 3142 if (pad_len) { 3143 pad_len = sizeof(u32) - pad_len; 3144 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len); 3145 /* padding is taken care of for coalescing case */ 3146 tx->packet_len += pad_len; 3147 tx->tlen += pad_len; 3148 } 3149 3150 /* dma map the coalesce buffer */ 3151 addr = dma_map_single(&dd->pcidev->dev, 3152 tx->coalesce_buf, 3153 tx->tlen, 3154 DMA_TO_DEVICE); 3155 3156 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 3157 sdma_txclean(dd, tx); 3158 return -ENOSPC; 3159 } 3160 3161 /* Add descriptor for coalesce buffer */ 3162 tx->desc_limit = MAX_DESC; 3163 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx, 3164 addr, tx->tlen); 3165 } 3166 3167 return 1; 3168 } 3169 3170 /* Update sdes when the lmc changes */ 3171 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid) 3172 { 3173 struct sdma_engine *sde; 3174 int i; 3175 u64 sreg; 3176 3177 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) << 3178 SD(CHECK_SLID_MASK_SHIFT)) | 3179 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) << 3180 SD(CHECK_SLID_VALUE_SHIFT)); 3181 3182 for (i = 0; i < dd->num_sdma; i++) { 3183 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x", 3184 i, (u32)sreg); 3185 sde = &dd->per_sdma[i]; 3186 write_sde_csr(sde, SD(CHECK_SLID), sreg); 3187 } 3188 } 3189 3190 /* tx not dword sized - pad */ 3191 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) 3192 { 3193 int rval = 0; 3194 3195 tx->num_desc++; 3196 if ((unlikely(tx->num_desc == tx->desc_limit))) { 3197 rval = _extend_sdma_tx_descs(dd, tx); 3198 if (rval) { 3199 sdma_txclean(dd, tx); 3200 return rval; 3201 } 3202 } 3203 /* finish the one just added */ 3204 make_tx_sdma_desc( 3205 tx, 3206 SDMA_MAP_NONE, 3207 dd->sdma_pad_phys, 3208 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1))); 3209 _sdma_close_tx(dd, tx); 3210 return rval; 3211 } 3212 3213 /* 3214 * Add ahg to the sdma_txreq 3215 * 3216 * The logic will consume up to 3 3217 * descriptors at the beginning of 3218 * sdma_txreq. 3219 */ 3220 void _sdma_txreq_ahgadd( 3221 struct sdma_txreq *tx, 3222 u8 num_ahg, 3223 u8 ahg_entry, 3224 u32 *ahg, 3225 u8 ahg_hlen) 3226 { 3227 u32 i, shift = 0, desc = 0; 3228 u8 mode; 3229 3230 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4); 3231 /* compute mode */ 3232 if (num_ahg == 1) 3233 mode = SDMA_AHG_APPLY_UPDATE1; 3234 else if (num_ahg <= 5) 3235 mode = SDMA_AHG_APPLY_UPDATE2; 3236 else 3237 mode = SDMA_AHG_APPLY_UPDATE3; 3238 tx->num_desc++; 3239 /* initialize to consumed descriptors to zero */ 3240 switch (mode) { 3241 case SDMA_AHG_APPLY_UPDATE3: 3242 tx->num_desc++; 3243 tx->descs[2].qw[0] = 0; 3244 tx->descs[2].qw[1] = 0; 3245 /* FALLTHROUGH */ 3246 case SDMA_AHG_APPLY_UPDATE2: 3247 tx->num_desc++; 3248 tx->descs[1].qw[0] = 0; 3249 tx->descs[1].qw[1] = 0; 3250 break; 3251 } 3252 ahg_hlen >>= 2; 3253 tx->descs[0].qw[1] |= 3254 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK) 3255 << SDMA_DESC1_HEADER_INDEX_SHIFT) | 3256 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK) 3257 << SDMA_DESC1_HEADER_DWS_SHIFT) | 3258 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK) 3259 << SDMA_DESC1_HEADER_MODE_SHIFT) | 3260 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK) 3261 << SDMA_DESC1_HEADER_UPDATE1_SHIFT); 3262 for (i = 0; i < (num_ahg - 1); i++) { 3263 if (!shift && !(i & 2)) 3264 desc++; 3265 tx->descs[desc].qw[!!(i & 2)] |= 3266 (((u64)ahg[i + 1]) 3267 << shift); 3268 shift = (shift + 32) & 63; 3269 } 3270 } 3271 3272 /** 3273 * sdma_ahg_alloc - allocate an AHG entry 3274 * @sde: engine to allocate from 3275 * 3276 * Return: 3277 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled, 3278 * -ENOSPC if an entry is not available 3279 */ 3280 int sdma_ahg_alloc(struct sdma_engine *sde) 3281 { 3282 int nr; 3283 int oldbit; 3284 3285 if (!sde) { 3286 trace_hfi1_ahg_allocate(sde, -EINVAL); 3287 return -EINVAL; 3288 } 3289 while (1) { 3290 nr = ffz(ACCESS_ONCE(sde->ahg_bits)); 3291 if (nr > 31) { 3292 trace_hfi1_ahg_allocate(sde, -ENOSPC); 3293 return -ENOSPC; 3294 } 3295 oldbit = test_and_set_bit(nr, &sde->ahg_bits); 3296 if (!oldbit) 3297 break; 3298 cpu_relax(); 3299 } 3300 trace_hfi1_ahg_allocate(sde, nr); 3301 return nr; 3302 } 3303 3304 /** 3305 * sdma_ahg_free - free an AHG entry 3306 * @sde: engine to return AHG entry 3307 * @ahg_index: index to free 3308 * 3309 * This routine frees the indicate AHG entry. 3310 */ 3311 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index) 3312 { 3313 if (!sde) 3314 return; 3315 trace_hfi1_ahg_deallocate(sde, ahg_index); 3316 if (ahg_index < 0 || ahg_index > 31) 3317 return; 3318 clear_bit(ahg_index, &sde->ahg_bits); 3319 } 3320 3321 /* 3322 * SPC freeze handling for SDMA engines. Called when the driver knows 3323 * the SPC is going into a freeze but before the freeze is fully 3324 * settled. Generally an error interrupt. 3325 * 3326 * This event will pull the engine out of running so no more entries can be 3327 * added to the engine's queue. 3328 */ 3329 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down) 3330 { 3331 int i; 3332 enum sdma_events event = link_down ? sdma_event_e85_link_down : 3333 sdma_event_e80_hw_freeze; 3334 3335 /* set up the wait but do not wait here */ 3336 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); 3337 3338 /* tell all engines to stop running and wait */ 3339 for (i = 0; i < dd->num_sdma; i++) 3340 sdma_process_event(&dd->per_sdma[i], event); 3341 3342 /* sdma_freeze() will wait for all engines to have stopped */ 3343 } 3344 3345 /* 3346 * SPC freeze handling for SDMA engines. Called when the driver knows 3347 * the SPC is fully frozen. 3348 */ 3349 void sdma_freeze(struct hfi1_devdata *dd) 3350 { 3351 int i; 3352 int ret; 3353 3354 /* 3355 * Make sure all engines have moved out of the running state before 3356 * continuing. 3357 */ 3358 ret = wait_event_interruptible(dd->sdma_unfreeze_wq, 3359 atomic_read(&dd->sdma_unfreeze_count) <= 3360 0); 3361 /* interrupted or count is negative, then unloading - just exit */ 3362 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0) 3363 return; 3364 3365 /* set up the count for the next wait */ 3366 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); 3367 3368 /* tell all engines that the SPC is frozen, they can start cleaning */ 3369 for (i = 0; i < dd->num_sdma; i++) 3370 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen); 3371 3372 /* 3373 * Wait for everyone to finish software clean before exiting. The 3374 * software clean will read engine CSRs, so must be completed before 3375 * the next step, which will clear the engine CSRs. 3376 */ 3377 (void)wait_event_interruptible(dd->sdma_unfreeze_wq, 3378 atomic_read(&dd->sdma_unfreeze_count) <= 0); 3379 /* no need to check results - done no matter what */ 3380 } 3381 3382 /* 3383 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen. 3384 * 3385 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All 3386 * that is left is a software clean. We could do it after the SPC is fully 3387 * frozen, but then we'd have to add another state to wait for the unfreeze. 3388 * Instead, just defer the software clean until the unfreeze step. 3389 */ 3390 void sdma_unfreeze(struct hfi1_devdata *dd) 3391 { 3392 int i; 3393 3394 /* tell all engines start freeze clean up */ 3395 for (i = 0; i < dd->num_sdma; i++) 3396 sdma_process_event(&dd->per_sdma[i], 3397 sdma_event_e82_hw_unfreeze); 3398 } 3399 3400 /** 3401 * _sdma_engine_progress_schedule() - schedule progress on engine 3402 * @sde: sdma_engine to schedule progress 3403 * 3404 */ 3405 void _sdma_engine_progress_schedule( 3406 struct sdma_engine *sde) 3407 { 3408 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask); 3409 /* assume we have selected a good cpu */ 3410 write_csr(sde->dd, 3411 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)), 3412 sde->progress_mask); 3413 } 3414