1 /* 2 * Copyright(c) 2015 - 2018 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/spinlock.h> 49 #include <linux/seqlock.h> 50 #include <linux/netdevice.h> 51 #include <linux/moduleparam.h> 52 #include <linux/bitops.h> 53 #include <linux/timer.h> 54 #include <linux/vmalloc.h> 55 #include <linux/highmem.h> 56 57 #include "hfi.h" 58 #include "common.h" 59 #include "qp.h" 60 #include "sdma.h" 61 #include "iowait.h" 62 #include "trace.h" 63 64 /* must be a power of 2 >= 64 <= 32768 */ 65 #define SDMA_DESCQ_CNT 2048 66 #define SDMA_DESC_INTR 64 67 #define INVALID_TAIL 0xffff 68 69 static uint sdma_descq_cnt = SDMA_DESCQ_CNT; 70 module_param(sdma_descq_cnt, uint, S_IRUGO); 71 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries"); 72 73 static uint sdma_idle_cnt = 250; 74 module_param(sdma_idle_cnt, uint, S_IRUGO); 75 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)"); 76 77 uint mod_num_sdma; 78 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO); 79 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use"); 80 81 static uint sdma_desct_intr = SDMA_DESC_INTR; 82 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR); 83 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt"); 84 85 #define SDMA_WAIT_BATCH_SIZE 20 86 /* max wait time for a SDMA engine to indicate it has halted */ 87 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */ 88 /* all SDMA engine errors that cause a halt */ 89 90 #define SD(name) SEND_DMA_##name 91 #define ALL_SDMA_ENG_HALT_ERRS \ 92 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \ 93 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \ 94 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \ 95 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \ 96 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \ 97 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \ 98 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \ 99 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \ 100 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \ 101 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \ 102 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \ 103 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \ 104 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \ 105 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \ 106 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \ 107 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \ 108 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \ 109 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK)) 110 111 /* sdma_sendctrl operations */ 112 #define SDMA_SENDCTRL_OP_ENABLE BIT(0) 113 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1) 114 #define SDMA_SENDCTRL_OP_HALT BIT(2) 115 #define SDMA_SENDCTRL_OP_CLEANUP BIT(3) 116 117 /* handle long defines */ 118 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \ 119 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK 120 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \ 121 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT 122 123 static const char * const sdma_state_names[] = { 124 [sdma_state_s00_hw_down] = "s00_HwDown", 125 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait", 126 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait", 127 [sdma_state_s20_idle] = "s20_Idle", 128 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait", 129 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait", 130 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait", 131 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait", 132 [sdma_state_s80_hw_freeze] = "s80_HwFreeze", 133 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean", 134 [sdma_state_s99_running] = "s99_Running", 135 }; 136 137 #ifdef CONFIG_SDMA_VERBOSITY 138 static const char * const sdma_event_names[] = { 139 [sdma_event_e00_go_hw_down] = "e00_GoHwDown", 140 [sdma_event_e10_go_hw_start] = "e10_GoHwStart", 141 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone", 142 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone", 143 [sdma_event_e30_go_running] = "e30_GoRunning", 144 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned", 145 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned", 146 [sdma_event_e60_hw_halted] = "e60_HwHalted", 147 [sdma_event_e70_go_idle] = "e70_GoIdle", 148 [sdma_event_e80_hw_freeze] = "e80_HwFreeze", 149 [sdma_event_e81_hw_frozen] = "e81_HwFrozen", 150 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze", 151 [sdma_event_e85_link_down] = "e85_LinkDown", 152 [sdma_event_e90_sw_halted] = "e90_SwHalted", 153 }; 154 #endif 155 156 static const struct sdma_set_state_action sdma_action_table[] = { 157 [sdma_state_s00_hw_down] = { 158 .go_s99_running_tofalse = 1, 159 .op_enable = 0, 160 .op_intenable = 0, 161 .op_halt = 0, 162 .op_cleanup = 0, 163 }, 164 [sdma_state_s10_hw_start_up_halt_wait] = { 165 .op_enable = 0, 166 .op_intenable = 0, 167 .op_halt = 1, 168 .op_cleanup = 0, 169 }, 170 [sdma_state_s15_hw_start_up_clean_wait] = { 171 .op_enable = 0, 172 .op_intenable = 1, 173 .op_halt = 0, 174 .op_cleanup = 1, 175 }, 176 [sdma_state_s20_idle] = { 177 .op_enable = 0, 178 .op_intenable = 1, 179 .op_halt = 0, 180 .op_cleanup = 0, 181 }, 182 [sdma_state_s30_sw_clean_up_wait] = { 183 .op_enable = 0, 184 .op_intenable = 0, 185 .op_halt = 0, 186 .op_cleanup = 0, 187 }, 188 [sdma_state_s40_hw_clean_up_wait] = { 189 .op_enable = 0, 190 .op_intenable = 0, 191 .op_halt = 0, 192 .op_cleanup = 1, 193 }, 194 [sdma_state_s50_hw_halt_wait] = { 195 .op_enable = 0, 196 .op_intenable = 0, 197 .op_halt = 0, 198 .op_cleanup = 0, 199 }, 200 [sdma_state_s60_idle_halt_wait] = { 201 .go_s99_running_tofalse = 1, 202 .op_enable = 0, 203 .op_intenable = 0, 204 .op_halt = 1, 205 .op_cleanup = 0, 206 }, 207 [sdma_state_s80_hw_freeze] = { 208 .op_enable = 0, 209 .op_intenable = 0, 210 .op_halt = 0, 211 .op_cleanup = 0, 212 }, 213 [sdma_state_s82_freeze_sw_clean] = { 214 .op_enable = 0, 215 .op_intenable = 0, 216 .op_halt = 0, 217 .op_cleanup = 0, 218 }, 219 [sdma_state_s99_running] = { 220 .op_enable = 1, 221 .op_intenable = 1, 222 .op_halt = 0, 223 .op_cleanup = 0, 224 .go_s99_running_totrue = 1, 225 }, 226 }; 227 228 #define SDMA_TAIL_UPDATE_THRESH 0x1F 229 230 /* declare all statics here rather than keep sorting */ 231 static void sdma_complete(struct kref *); 232 static void sdma_finalput(struct sdma_state *); 233 static void sdma_get(struct sdma_state *); 234 static void sdma_hw_clean_up_task(unsigned long); 235 static void sdma_put(struct sdma_state *); 236 static void sdma_set_state(struct sdma_engine *, enum sdma_states); 237 static void sdma_start_hw_clean_up(struct sdma_engine *); 238 static void sdma_sw_clean_up_task(unsigned long); 239 static void sdma_sendctrl(struct sdma_engine *, unsigned); 240 static void init_sdma_regs(struct sdma_engine *, u32, uint); 241 static void sdma_process_event( 242 struct sdma_engine *sde, 243 enum sdma_events event); 244 static void __sdma_process_event( 245 struct sdma_engine *sde, 246 enum sdma_events event); 247 static void dump_sdma_state(struct sdma_engine *sde); 248 static void sdma_make_progress(struct sdma_engine *sde, u64 status); 249 static void sdma_desc_avail(struct sdma_engine *sde, uint avail); 250 static void sdma_flush_descq(struct sdma_engine *sde); 251 252 /** 253 * sdma_state_name() - return state string from enum 254 * @state: state 255 */ 256 static const char *sdma_state_name(enum sdma_states state) 257 { 258 return sdma_state_names[state]; 259 } 260 261 static void sdma_get(struct sdma_state *ss) 262 { 263 kref_get(&ss->kref); 264 } 265 266 static void sdma_complete(struct kref *kref) 267 { 268 struct sdma_state *ss = 269 container_of(kref, struct sdma_state, kref); 270 271 complete(&ss->comp); 272 } 273 274 static void sdma_put(struct sdma_state *ss) 275 { 276 kref_put(&ss->kref, sdma_complete); 277 } 278 279 static void sdma_finalput(struct sdma_state *ss) 280 { 281 sdma_put(ss); 282 wait_for_completion(&ss->comp); 283 } 284 285 static inline void write_sde_csr( 286 struct sdma_engine *sde, 287 u32 offset0, 288 u64 value) 289 { 290 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value); 291 } 292 293 static inline u64 read_sde_csr( 294 struct sdma_engine *sde, 295 u32 offset0) 296 { 297 return read_kctxt_csr(sde->dd, sde->this_idx, offset0); 298 } 299 300 /* 301 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for 302 * sdma engine 'sde' to drop to 0. 303 */ 304 static void sdma_wait_for_packet_egress(struct sdma_engine *sde, 305 int pause) 306 { 307 u64 off = 8 * sde->this_idx; 308 struct hfi1_devdata *dd = sde->dd; 309 int lcnt = 0; 310 u64 reg_prev; 311 u64 reg = 0; 312 313 while (1) { 314 reg_prev = reg; 315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); 316 317 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK; 318 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT; 319 if (reg == 0) 320 break; 321 /* counter is reest if accupancy count changes */ 322 if (reg != reg_prev) 323 lcnt = 0; 324 if (lcnt++ > 500) { 325 /* timed out - bounce the link */ 326 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n", 327 __func__, sde->this_idx, (u32)reg); 328 queue_work(dd->pport->link_wq, 329 &dd->pport->link_bounce_work); 330 break; 331 } 332 udelay(1); 333 } 334 } 335 336 /* 337 * sdma_wait() - wait for packet egress to complete for all SDMA engines, 338 * and pause for credit return. 339 */ 340 void sdma_wait(struct hfi1_devdata *dd) 341 { 342 int i; 343 344 for (i = 0; i < dd->num_sdma; i++) { 345 struct sdma_engine *sde = &dd->per_sdma[i]; 346 347 sdma_wait_for_packet_egress(sde, 0); 348 } 349 } 350 351 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt) 352 { 353 u64 reg; 354 355 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT)) 356 return; 357 reg = cnt; 358 reg &= SD(DESC_CNT_CNT_MASK); 359 reg <<= SD(DESC_CNT_CNT_SHIFT); 360 write_sde_csr(sde, SD(DESC_CNT), reg); 361 } 362 363 static inline void complete_tx(struct sdma_engine *sde, 364 struct sdma_txreq *tx, 365 int res) 366 { 367 /* protect against complete modifying */ 368 struct iowait *wait = tx->wait; 369 callback_t complete = tx->complete; 370 371 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 372 trace_hfi1_sdma_out_sn(sde, tx->sn); 373 if (WARN_ON_ONCE(sde->head_sn != tx->sn)) 374 dd_dev_err(sde->dd, "expected %llu got %llu\n", 375 sde->head_sn, tx->sn); 376 sde->head_sn++; 377 #endif 378 __sdma_txclean(sde->dd, tx); 379 if (complete) 380 (*complete)(tx, res); 381 if (iowait_sdma_dec(wait)) 382 iowait_drain_wakeup(wait); 383 } 384 385 /* 386 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status 387 * 388 * Depending on timing there can be txreqs in two places: 389 * - in the descq ring 390 * - in the flush list 391 * 392 * To avoid ordering issues the descq ring needs to be flushed 393 * first followed by the flush list. 394 * 395 * This routine is called from two places 396 * - From a work queue item 397 * - Directly from the state machine just before setting the 398 * state to running 399 * 400 * Must be called with head_lock held 401 * 402 */ 403 static void sdma_flush(struct sdma_engine *sde) 404 { 405 struct sdma_txreq *txp, *txp_next; 406 LIST_HEAD(flushlist); 407 unsigned long flags; 408 409 /* flush from head to tail */ 410 sdma_flush_descq(sde); 411 spin_lock_irqsave(&sde->flushlist_lock, flags); 412 /* copy flush list */ 413 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) { 414 list_del_init(&txp->list); 415 list_add_tail(&txp->list, &flushlist); 416 } 417 spin_unlock_irqrestore(&sde->flushlist_lock, flags); 418 /* flush from flush list */ 419 list_for_each_entry_safe(txp, txp_next, &flushlist, list) 420 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED); 421 } 422 423 /* 424 * Fields a work request for flushing the descq ring 425 * and the flush list 426 * 427 * If the engine has been brought to running during 428 * the scheduling delay, the flush is ignored, assuming 429 * that the process of bringing the engine to running 430 * would have done this flush prior to going to running. 431 * 432 */ 433 static void sdma_field_flush(struct work_struct *work) 434 { 435 unsigned long flags; 436 struct sdma_engine *sde = 437 container_of(work, struct sdma_engine, flush_worker); 438 439 write_seqlock_irqsave(&sde->head_lock, flags); 440 if (!__sdma_running(sde)) 441 sdma_flush(sde); 442 write_sequnlock_irqrestore(&sde->head_lock, flags); 443 } 444 445 static void sdma_err_halt_wait(struct work_struct *work) 446 { 447 struct sdma_engine *sde = container_of(work, struct sdma_engine, 448 err_halt_worker); 449 u64 statuscsr; 450 unsigned long timeout; 451 452 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT); 453 while (1) { 454 statuscsr = read_sde_csr(sde, SD(STATUS)); 455 statuscsr &= SD(STATUS_ENG_HALTED_SMASK); 456 if (statuscsr) 457 break; 458 if (time_after(jiffies, timeout)) { 459 dd_dev_err(sde->dd, 460 "SDMA engine %d - timeout waiting for engine to halt\n", 461 sde->this_idx); 462 /* 463 * Continue anyway. This could happen if there was 464 * an uncorrectable error in the wrong spot. 465 */ 466 break; 467 } 468 usleep_range(80, 120); 469 } 470 471 sdma_process_event(sde, sdma_event_e15_hw_halt_done); 472 } 473 474 static void sdma_err_progress_check_schedule(struct sdma_engine *sde) 475 { 476 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) { 477 unsigned index; 478 struct hfi1_devdata *dd = sde->dd; 479 480 for (index = 0; index < dd->num_sdma; index++) { 481 struct sdma_engine *curr_sdma = &dd->per_sdma[index]; 482 483 if (curr_sdma != sde) 484 curr_sdma->progress_check_head = 485 curr_sdma->descq_head; 486 } 487 dd_dev_err(sde->dd, 488 "SDMA engine %d - check scheduled\n", 489 sde->this_idx); 490 mod_timer(&sde->err_progress_check_timer, jiffies + 10); 491 } 492 } 493 494 static void sdma_err_progress_check(struct timer_list *t) 495 { 496 unsigned index; 497 struct sdma_engine *sde = from_timer(sde, t, err_progress_check_timer); 498 499 dd_dev_err(sde->dd, "SDE progress check event\n"); 500 for (index = 0; index < sde->dd->num_sdma; index++) { 501 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index]; 502 unsigned long flags; 503 504 /* check progress on each engine except the current one */ 505 if (curr_sde == sde) 506 continue; 507 /* 508 * We must lock interrupts when acquiring sde->lock, 509 * to avoid a deadlock if interrupt triggers and spins on 510 * the same lock on same CPU 511 */ 512 spin_lock_irqsave(&curr_sde->tail_lock, flags); 513 write_seqlock(&curr_sde->head_lock); 514 515 /* skip non-running queues */ 516 if (curr_sde->state.current_state != sdma_state_s99_running) { 517 write_sequnlock(&curr_sde->head_lock); 518 spin_unlock_irqrestore(&curr_sde->tail_lock, flags); 519 continue; 520 } 521 522 if ((curr_sde->descq_head != curr_sde->descq_tail) && 523 (curr_sde->descq_head == 524 curr_sde->progress_check_head)) 525 __sdma_process_event(curr_sde, 526 sdma_event_e90_sw_halted); 527 write_sequnlock(&curr_sde->head_lock); 528 spin_unlock_irqrestore(&curr_sde->tail_lock, flags); 529 } 530 schedule_work(&sde->err_halt_worker); 531 } 532 533 static void sdma_hw_clean_up_task(unsigned long opaque) 534 { 535 struct sdma_engine *sde = (struct sdma_engine *)opaque; 536 u64 statuscsr; 537 538 while (1) { 539 #ifdef CONFIG_SDMA_VERBOSITY 540 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 541 sde->this_idx, slashstrip(__FILE__), __LINE__, 542 __func__); 543 #endif 544 statuscsr = read_sde_csr(sde, SD(STATUS)); 545 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK); 546 if (statuscsr) 547 break; 548 udelay(10); 549 } 550 551 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done); 552 } 553 554 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde) 555 { 556 return sde->tx_ring[sde->tx_head & sde->sdma_mask]; 557 } 558 559 /* 560 * flush ring for recovery 561 */ 562 static void sdma_flush_descq(struct sdma_engine *sde) 563 { 564 u16 head, tail; 565 int progress = 0; 566 struct sdma_txreq *txp = get_txhead(sde); 567 568 /* The reason for some of the complexity of this code is that 569 * not all descriptors have corresponding txps. So, we have to 570 * be able to skip over descs until we wander into the range of 571 * the next txp on the list. 572 */ 573 head = sde->descq_head & sde->sdma_mask; 574 tail = sde->descq_tail & sde->sdma_mask; 575 while (head != tail) { 576 /* advance head, wrap if needed */ 577 head = ++sde->descq_head & sde->sdma_mask; 578 /* if now past this txp's descs, do the callback */ 579 if (txp && txp->next_descq_idx == head) { 580 /* remove from list */ 581 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; 582 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED); 583 trace_hfi1_sdma_progress(sde, head, tail, txp); 584 txp = get_txhead(sde); 585 } 586 progress++; 587 } 588 if (progress) 589 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 590 } 591 592 static void sdma_sw_clean_up_task(unsigned long opaque) 593 { 594 struct sdma_engine *sde = (struct sdma_engine *)opaque; 595 unsigned long flags; 596 597 spin_lock_irqsave(&sde->tail_lock, flags); 598 write_seqlock(&sde->head_lock); 599 600 /* 601 * At this point, the following should always be true: 602 * - We are halted, so no more descriptors are getting retired. 603 * - We are not running, so no one is submitting new work. 604 * - Only we can send the e40_sw_cleaned, so we can't start 605 * running again until we say so. So, the active list and 606 * descq are ours to play with. 607 */ 608 609 /* 610 * In the error clean up sequence, software clean must be called 611 * before the hardware clean so we can use the hardware head in 612 * the progress routine. A hardware clean or SPC unfreeze will 613 * reset the hardware head. 614 * 615 * Process all retired requests. The progress routine will use the 616 * latest physical hardware head - we are not running so speed does 617 * not matter. 618 */ 619 sdma_make_progress(sde, 0); 620 621 sdma_flush(sde); 622 623 /* 624 * Reset our notion of head and tail. 625 * Note that the HW registers have been reset via an earlier 626 * clean up. 627 */ 628 sde->descq_tail = 0; 629 sde->descq_head = 0; 630 sde->desc_avail = sdma_descq_freecnt(sde); 631 *sde->head_dma = 0; 632 633 __sdma_process_event(sde, sdma_event_e40_sw_cleaned); 634 635 write_sequnlock(&sde->head_lock); 636 spin_unlock_irqrestore(&sde->tail_lock, flags); 637 } 638 639 static void sdma_sw_tear_down(struct sdma_engine *sde) 640 { 641 struct sdma_state *ss = &sde->state; 642 643 /* Releasing this reference means the state machine has stopped. */ 644 sdma_put(ss); 645 646 /* stop waiting for all unfreeze events to complete */ 647 atomic_set(&sde->dd->sdma_unfreeze_count, -1); 648 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 649 } 650 651 static void sdma_start_hw_clean_up(struct sdma_engine *sde) 652 { 653 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task); 654 } 655 656 static void sdma_set_state(struct sdma_engine *sde, 657 enum sdma_states next_state) 658 { 659 struct sdma_state *ss = &sde->state; 660 const struct sdma_set_state_action *action = sdma_action_table; 661 unsigned op = 0; 662 663 trace_hfi1_sdma_state( 664 sde, 665 sdma_state_names[ss->current_state], 666 sdma_state_names[next_state]); 667 668 /* debugging bookkeeping */ 669 ss->previous_state = ss->current_state; 670 ss->previous_op = ss->current_op; 671 ss->current_state = next_state; 672 673 if (ss->previous_state != sdma_state_s99_running && 674 next_state == sdma_state_s99_running) 675 sdma_flush(sde); 676 677 if (action[next_state].op_enable) 678 op |= SDMA_SENDCTRL_OP_ENABLE; 679 680 if (action[next_state].op_intenable) 681 op |= SDMA_SENDCTRL_OP_INTENABLE; 682 683 if (action[next_state].op_halt) 684 op |= SDMA_SENDCTRL_OP_HALT; 685 686 if (action[next_state].op_cleanup) 687 op |= SDMA_SENDCTRL_OP_CLEANUP; 688 689 if (action[next_state].go_s99_running_tofalse) 690 ss->go_s99_running = 0; 691 692 if (action[next_state].go_s99_running_totrue) 693 ss->go_s99_running = 1; 694 695 ss->current_op = op; 696 sdma_sendctrl(sde, ss->current_op); 697 } 698 699 /** 700 * sdma_get_descq_cnt() - called when device probed 701 * 702 * Return a validated descq count. 703 * 704 * This is currently only used in the verbs initialization to build the tx 705 * list. 706 * 707 * This will probably be deleted in favor of a more scalable approach to 708 * alloc tx's. 709 * 710 */ 711 u16 sdma_get_descq_cnt(void) 712 { 713 u16 count = sdma_descq_cnt; 714 715 if (!count) 716 return SDMA_DESCQ_CNT; 717 /* count must be a power of 2 greater than 64 and less than 718 * 32768. Otherwise return default. 719 */ 720 if (!is_power_of_2(count)) 721 return SDMA_DESCQ_CNT; 722 if (count < 64 || count > 32768) 723 return SDMA_DESCQ_CNT; 724 return count; 725 } 726 727 /** 728 * sdma_engine_get_vl() - return vl for a given sdma engine 729 * @sde: sdma engine 730 * 731 * This function returns the vl mapped to a given engine, or an error if 732 * the mapping can't be found. The mapping fields are protected by RCU. 733 */ 734 int sdma_engine_get_vl(struct sdma_engine *sde) 735 { 736 struct hfi1_devdata *dd = sde->dd; 737 struct sdma_vl_map *m; 738 u8 vl; 739 740 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES) 741 return -EINVAL; 742 743 rcu_read_lock(); 744 m = rcu_dereference(dd->sdma_map); 745 if (unlikely(!m)) { 746 rcu_read_unlock(); 747 return -EINVAL; 748 } 749 vl = m->engine_to_vl[sde->this_idx]; 750 rcu_read_unlock(); 751 752 return vl; 753 } 754 755 /** 756 * sdma_select_engine_vl() - select sdma engine 757 * @dd: devdata 758 * @selector: a spreading factor 759 * @vl: this vl 760 * 761 * 762 * This function returns an engine based on the selector and a vl. The 763 * mapping fields are protected by RCU. 764 */ 765 struct sdma_engine *sdma_select_engine_vl( 766 struct hfi1_devdata *dd, 767 u32 selector, 768 u8 vl) 769 { 770 struct sdma_vl_map *m; 771 struct sdma_map_elem *e; 772 struct sdma_engine *rval; 773 774 /* NOTE This should only happen if SC->VL changed after the initial 775 * checks on the QP/AH 776 * Default will return engine 0 below 777 */ 778 if (vl >= num_vls) { 779 rval = NULL; 780 goto done; 781 } 782 783 rcu_read_lock(); 784 m = rcu_dereference(dd->sdma_map); 785 if (unlikely(!m)) { 786 rcu_read_unlock(); 787 return &dd->per_sdma[0]; 788 } 789 e = m->map[vl & m->mask]; 790 rval = e->sde[selector & e->mask]; 791 rcu_read_unlock(); 792 793 done: 794 rval = !rval ? &dd->per_sdma[0] : rval; 795 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx); 796 return rval; 797 } 798 799 /** 800 * sdma_select_engine_sc() - select sdma engine 801 * @dd: devdata 802 * @selector: a spreading factor 803 * @sc5: the 5 bit sc 804 * 805 * 806 * This function returns an engine based on the selector and an sc. 807 */ 808 struct sdma_engine *sdma_select_engine_sc( 809 struct hfi1_devdata *dd, 810 u32 selector, 811 u8 sc5) 812 { 813 u8 vl = sc_to_vlt(dd, sc5); 814 815 return sdma_select_engine_vl(dd, selector, vl); 816 } 817 818 struct sdma_rht_map_elem { 819 u32 mask; 820 u8 ctr; 821 struct sdma_engine *sde[0]; 822 }; 823 824 struct sdma_rht_node { 825 unsigned long cpu_id; 826 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED]; 827 struct rhash_head node; 828 }; 829 830 #define NR_CPUS_HINT 192 831 832 static const struct rhashtable_params sdma_rht_params = { 833 .nelem_hint = NR_CPUS_HINT, 834 .head_offset = offsetof(struct sdma_rht_node, node), 835 .key_offset = offsetof(struct sdma_rht_node, cpu_id), 836 .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id), 837 .max_size = NR_CPUS, 838 .min_size = 8, 839 .automatic_shrinking = true, 840 }; 841 842 /* 843 * sdma_select_user_engine() - select sdma engine based on user setup 844 * @dd: devdata 845 * @selector: a spreading factor 846 * @vl: this vl 847 * 848 * This function returns an sdma engine for a user sdma request. 849 * User defined sdma engine affinity setting is honored when applicable, 850 * otherwise system default sdma engine mapping is used. To ensure correct 851 * ordering, the mapping from <selector, vl> to sde must remain unchanged. 852 */ 853 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd, 854 u32 selector, u8 vl) 855 { 856 struct sdma_rht_node *rht_node; 857 struct sdma_engine *sde = NULL; 858 const struct cpumask *current_mask = ¤t->cpus_allowed; 859 unsigned long cpu_id; 860 861 /* 862 * To ensure that always the same sdma engine(s) will be 863 * selected make sure the process is pinned to this CPU only. 864 */ 865 if (cpumask_weight(current_mask) != 1) 866 goto out; 867 868 cpu_id = smp_processor_id(); 869 rcu_read_lock(); 870 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu_id, 871 sdma_rht_params); 872 873 if (rht_node && rht_node->map[vl]) { 874 struct sdma_rht_map_elem *map = rht_node->map[vl]; 875 876 sde = map->sde[selector & map->mask]; 877 } 878 rcu_read_unlock(); 879 880 if (sde) 881 return sde; 882 883 out: 884 return sdma_select_engine_vl(dd, selector, vl); 885 } 886 887 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map) 888 { 889 int i; 890 891 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++) 892 map->sde[map->ctr + i] = map->sde[i]; 893 } 894 895 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map, 896 struct sdma_engine *sde) 897 { 898 unsigned int i, pow; 899 900 /* only need to check the first ctr entries for a match */ 901 for (i = 0; i < map->ctr; i++) { 902 if (map->sde[i] == sde) { 903 memmove(&map->sde[i], &map->sde[i + 1], 904 (map->ctr - i - 1) * sizeof(map->sde[0])); 905 map->ctr--; 906 pow = roundup_pow_of_two(map->ctr ? : 1); 907 map->mask = pow - 1; 908 sdma_populate_sde_map(map); 909 break; 910 } 911 } 912 } 913 914 /* 915 * Prevents concurrent reads and writes of the sdma engine cpu_mask 916 */ 917 static DEFINE_MUTEX(process_to_sde_mutex); 918 919 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf, 920 size_t count) 921 { 922 struct hfi1_devdata *dd = sde->dd; 923 cpumask_var_t mask, new_mask; 924 unsigned long cpu; 925 int ret, vl, sz; 926 struct sdma_rht_node *rht_node; 927 928 vl = sdma_engine_get_vl(sde); 929 if (unlikely(vl < 0 || vl >= ARRAY_SIZE(rht_node->map))) 930 return -EINVAL; 931 932 ret = zalloc_cpumask_var(&mask, GFP_KERNEL); 933 if (!ret) 934 return -ENOMEM; 935 936 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL); 937 if (!ret) { 938 free_cpumask_var(mask); 939 return -ENOMEM; 940 } 941 ret = cpulist_parse(buf, mask); 942 if (ret) 943 goto out_free; 944 945 if (!cpumask_subset(mask, cpu_online_mask)) { 946 dd_dev_warn(sde->dd, "Invalid CPU mask\n"); 947 ret = -EINVAL; 948 goto out_free; 949 } 950 951 sz = sizeof(struct sdma_rht_map_elem) + 952 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *)); 953 954 mutex_lock(&process_to_sde_mutex); 955 956 for_each_cpu(cpu, mask) { 957 /* Check if we have this already mapped */ 958 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) { 959 cpumask_set_cpu(cpu, new_mask); 960 continue; 961 } 962 963 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu, 964 sdma_rht_params); 965 if (!rht_node) { 966 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL); 967 if (!rht_node) { 968 ret = -ENOMEM; 969 goto out; 970 } 971 972 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL); 973 if (!rht_node->map[vl]) { 974 kfree(rht_node); 975 ret = -ENOMEM; 976 goto out; 977 } 978 rht_node->cpu_id = cpu; 979 rht_node->map[vl]->mask = 0; 980 rht_node->map[vl]->ctr = 1; 981 rht_node->map[vl]->sde[0] = sde; 982 983 ret = rhashtable_insert_fast(dd->sdma_rht, 984 &rht_node->node, 985 sdma_rht_params); 986 if (ret) { 987 kfree(rht_node->map[vl]); 988 kfree(rht_node); 989 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n", 990 cpu); 991 goto out; 992 } 993 994 } else { 995 int ctr, pow; 996 997 /* Add new user mappings */ 998 if (!rht_node->map[vl]) 999 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL); 1000 1001 if (!rht_node->map[vl]) { 1002 ret = -ENOMEM; 1003 goto out; 1004 } 1005 1006 rht_node->map[vl]->ctr++; 1007 ctr = rht_node->map[vl]->ctr; 1008 rht_node->map[vl]->sde[ctr - 1] = sde; 1009 pow = roundup_pow_of_two(ctr); 1010 rht_node->map[vl]->mask = pow - 1; 1011 1012 /* Populate the sde map table */ 1013 sdma_populate_sde_map(rht_node->map[vl]); 1014 } 1015 cpumask_set_cpu(cpu, new_mask); 1016 } 1017 1018 /* Clean up old mappings */ 1019 for_each_cpu(cpu, cpu_online_mask) { 1020 struct sdma_rht_node *rht_node; 1021 1022 /* Don't cleanup sdes that are set in the new mask */ 1023 if (cpumask_test_cpu(cpu, mask)) 1024 continue; 1025 1026 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu, 1027 sdma_rht_params); 1028 if (rht_node) { 1029 bool empty = true; 1030 int i; 1031 1032 /* Remove mappings for old sde */ 1033 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1034 if (rht_node->map[i]) 1035 sdma_cleanup_sde_map(rht_node->map[i], 1036 sde); 1037 1038 /* Free empty hash table entries */ 1039 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) { 1040 if (!rht_node->map[i]) 1041 continue; 1042 1043 if (rht_node->map[i]->ctr) { 1044 empty = false; 1045 break; 1046 } 1047 } 1048 1049 if (empty) { 1050 ret = rhashtable_remove_fast(dd->sdma_rht, 1051 &rht_node->node, 1052 sdma_rht_params); 1053 WARN_ON(ret); 1054 1055 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1056 kfree(rht_node->map[i]); 1057 1058 kfree(rht_node); 1059 } 1060 } 1061 } 1062 1063 cpumask_copy(&sde->cpu_mask, new_mask); 1064 out: 1065 mutex_unlock(&process_to_sde_mutex); 1066 out_free: 1067 free_cpumask_var(mask); 1068 free_cpumask_var(new_mask); 1069 return ret ? : strnlen(buf, PAGE_SIZE); 1070 } 1071 1072 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf) 1073 { 1074 mutex_lock(&process_to_sde_mutex); 1075 if (cpumask_empty(&sde->cpu_mask)) 1076 snprintf(buf, PAGE_SIZE, "%s\n", "empty"); 1077 else 1078 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask); 1079 mutex_unlock(&process_to_sde_mutex); 1080 return strnlen(buf, PAGE_SIZE); 1081 } 1082 1083 static void sdma_rht_free(void *ptr, void *arg) 1084 { 1085 struct sdma_rht_node *rht_node = ptr; 1086 int i; 1087 1088 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1089 kfree(rht_node->map[i]); 1090 1091 kfree(rht_node); 1092 } 1093 1094 /** 1095 * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings 1096 * @s: seq file 1097 * @dd: hfi1_devdata 1098 * @cpuid: cpu id 1099 * 1100 * This routine dumps the process to sde mappings per cpu 1101 */ 1102 void sdma_seqfile_dump_cpu_list(struct seq_file *s, 1103 struct hfi1_devdata *dd, 1104 unsigned long cpuid) 1105 { 1106 struct sdma_rht_node *rht_node; 1107 int i, j; 1108 1109 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpuid, 1110 sdma_rht_params); 1111 if (!rht_node) 1112 return; 1113 1114 seq_printf(s, "cpu%3lu: ", cpuid); 1115 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) { 1116 if (!rht_node->map[i] || !rht_node->map[i]->ctr) 1117 continue; 1118 1119 seq_printf(s, " vl%d: [", i); 1120 1121 for (j = 0; j < rht_node->map[i]->ctr; j++) { 1122 if (!rht_node->map[i]->sde[j]) 1123 continue; 1124 1125 if (j > 0) 1126 seq_puts(s, ","); 1127 1128 seq_printf(s, " sdma%2d", 1129 rht_node->map[i]->sde[j]->this_idx); 1130 } 1131 seq_puts(s, " ]"); 1132 } 1133 1134 seq_puts(s, "\n"); 1135 } 1136 1137 /* 1138 * Free the indicated map struct 1139 */ 1140 static void sdma_map_free(struct sdma_vl_map *m) 1141 { 1142 int i; 1143 1144 for (i = 0; m && i < m->actual_vls; i++) 1145 kfree(m->map[i]); 1146 kfree(m); 1147 } 1148 1149 /* 1150 * Handle RCU callback 1151 */ 1152 static void sdma_map_rcu_callback(struct rcu_head *list) 1153 { 1154 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list); 1155 1156 sdma_map_free(m); 1157 } 1158 1159 /** 1160 * sdma_map_init - called when # vls change 1161 * @dd: hfi1_devdata 1162 * @port: port number 1163 * @num_vls: number of vls 1164 * @vl_engines: per vl engine mapping (optional) 1165 * 1166 * This routine changes the mapping based on the number of vls. 1167 * 1168 * vl_engines is used to specify a non-uniform vl/engine loading. NULL 1169 * implies auto computing the loading and giving each VLs a uniform 1170 * distribution of engines per VL. 1171 * 1172 * The auto algorithm computes the sde_per_vl and the number of extra 1173 * engines. Any extra engines are added from the last VL on down. 1174 * 1175 * rcu locking is used here to control access to the mapping fields. 1176 * 1177 * If either the num_vls or num_sdma are non-power of 2, the array sizes 1178 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded 1179 * up to the next highest power of 2 and the first entry is reused 1180 * in a round robin fashion. 1181 * 1182 * If an error occurs the map change is not done and the mapping is 1183 * not changed. 1184 * 1185 */ 1186 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines) 1187 { 1188 int i, j; 1189 int extra, sde_per_vl; 1190 int engine = 0; 1191 u8 lvl_engines[OPA_MAX_VLS]; 1192 struct sdma_vl_map *oldmap, *newmap; 1193 1194 if (!(dd->flags & HFI1_HAS_SEND_DMA)) 1195 return 0; 1196 1197 if (!vl_engines) { 1198 /* truncate divide */ 1199 sde_per_vl = dd->num_sdma / num_vls; 1200 /* extras */ 1201 extra = dd->num_sdma % num_vls; 1202 vl_engines = lvl_engines; 1203 /* add extras from last vl down */ 1204 for (i = num_vls - 1; i >= 0; i--, extra--) 1205 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0); 1206 } 1207 /* build new map */ 1208 newmap = kzalloc( 1209 sizeof(struct sdma_vl_map) + 1210 roundup_pow_of_two(num_vls) * 1211 sizeof(struct sdma_map_elem *), 1212 GFP_KERNEL); 1213 if (!newmap) 1214 goto bail; 1215 newmap->actual_vls = num_vls; 1216 newmap->vls = roundup_pow_of_two(num_vls); 1217 newmap->mask = (1 << ilog2(newmap->vls)) - 1; 1218 /* initialize back-map */ 1219 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++) 1220 newmap->engine_to_vl[i] = -1; 1221 for (i = 0; i < newmap->vls; i++) { 1222 /* save for wrap around */ 1223 int first_engine = engine; 1224 1225 if (i < newmap->actual_vls) { 1226 int sz = roundup_pow_of_two(vl_engines[i]); 1227 1228 /* only allocate once */ 1229 newmap->map[i] = kzalloc( 1230 sizeof(struct sdma_map_elem) + 1231 sz * sizeof(struct sdma_engine *), 1232 GFP_KERNEL); 1233 if (!newmap->map[i]) 1234 goto bail; 1235 newmap->map[i]->mask = (1 << ilog2(sz)) - 1; 1236 /* assign engines */ 1237 for (j = 0; j < sz; j++) { 1238 newmap->map[i]->sde[j] = 1239 &dd->per_sdma[engine]; 1240 if (++engine >= first_engine + vl_engines[i]) 1241 /* wrap back to first engine */ 1242 engine = first_engine; 1243 } 1244 /* assign back-map */ 1245 for (j = 0; j < vl_engines[i]; j++) 1246 newmap->engine_to_vl[first_engine + j] = i; 1247 } else { 1248 /* just re-use entry without allocating */ 1249 newmap->map[i] = newmap->map[i % num_vls]; 1250 } 1251 engine = first_engine + vl_engines[i]; 1252 } 1253 /* newmap in hand, save old map */ 1254 spin_lock_irq(&dd->sde_map_lock); 1255 oldmap = rcu_dereference_protected(dd->sdma_map, 1256 lockdep_is_held(&dd->sde_map_lock)); 1257 1258 /* publish newmap */ 1259 rcu_assign_pointer(dd->sdma_map, newmap); 1260 1261 spin_unlock_irq(&dd->sde_map_lock); 1262 /* success, free any old map after grace period */ 1263 if (oldmap) 1264 call_rcu(&oldmap->list, sdma_map_rcu_callback); 1265 return 0; 1266 bail: 1267 /* free any partial allocation */ 1268 sdma_map_free(newmap); 1269 return -ENOMEM; 1270 } 1271 1272 /** 1273 * sdma_clean() Clean up allocated memory 1274 * @dd: struct hfi1_devdata 1275 * @num_engines: num sdma engines 1276 * 1277 * This routine can be called regardless of the success of 1278 * sdma_init() 1279 */ 1280 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) 1281 { 1282 size_t i; 1283 struct sdma_engine *sde; 1284 1285 if (dd->sdma_pad_dma) { 1286 dma_free_coherent(&dd->pcidev->dev, 4, 1287 (void *)dd->sdma_pad_dma, 1288 dd->sdma_pad_phys); 1289 dd->sdma_pad_dma = NULL; 1290 dd->sdma_pad_phys = 0; 1291 } 1292 if (dd->sdma_heads_dma) { 1293 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size, 1294 (void *)dd->sdma_heads_dma, 1295 dd->sdma_heads_phys); 1296 dd->sdma_heads_dma = NULL; 1297 dd->sdma_heads_phys = 0; 1298 } 1299 for (i = 0; dd->per_sdma && i < num_engines; ++i) { 1300 sde = &dd->per_sdma[i]; 1301 1302 sde->head_dma = NULL; 1303 sde->head_phys = 0; 1304 1305 if (sde->descq) { 1306 dma_free_coherent( 1307 &dd->pcidev->dev, 1308 sde->descq_cnt * sizeof(u64[2]), 1309 sde->descq, 1310 sde->descq_phys 1311 ); 1312 sde->descq = NULL; 1313 sde->descq_phys = 0; 1314 } 1315 kvfree(sde->tx_ring); 1316 sde->tx_ring = NULL; 1317 } 1318 spin_lock_irq(&dd->sde_map_lock); 1319 sdma_map_free(rcu_access_pointer(dd->sdma_map)); 1320 RCU_INIT_POINTER(dd->sdma_map, NULL); 1321 spin_unlock_irq(&dd->sde_map_lock); 1322 synchronize_rcu(); 1323 kfree(dd->per_sdma); 1324 dd->per_sdma = NULL; 1325 1326 if (dd->sdma_rht) { 1327 rhashtable_free_and_destroy(dd->sdma_rht, sdma_rht_free, NULL); 1328 kfree(dd->sdma_rht); 1329 dd->sdma_rht = NULL; 1330 } 1331 } 1332 1333 /** 1334 * sdma_init() - called when device probed 1335 * @dd: hfi1_devdata 1336 * @port: port number (currently only zero) 1337 * 1338 * Initializes each sde and its csrs. 1339 * Interrupts are not required to be enabled. 1340 * 1341 * Returns: 1342 * 0 - success, -errno on failure 1343 */ 1344 int sdma_init(struct hfi1_devdata *dd, u8 port) 1345 { 1346 unsigned this_idx; 1347 struct sdma_engine *sde; 1348 struct rhashtable *tmp_sdma_rht; 1349 u16 descq_cnt; 1350 void *curr_head; 1351 struct hfi1_pportdata *ppd = dd->pport + port; 1352 u32 per_sdma_credits; 1353 uint idle_cnt = sdma_idle_cnt; 1354 size_t num_engines = chip_sdma_engines(dd); 1355 int ret = -ENOMEM; 1356 1357 if (!HFI1_CAP_IS_KSET(SDMA)) { 1358 HFI1_CAP_CLEAR(SDMA_AHG); 1359 return 0; 1360 } 1361 if (mod_num_sdma && 1362 /* can't exceed chip support */ 1363 mod_num_sdma <= chip_sdma_engines(dd) && 1364 /* count must be >= vls */ 1365 mod_num_sdma >= num_vls) 1366 num_engines = mod_num_sdma; 1367 1368 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma); 1369 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", chip_sdma_engines(dd)); 1370 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n", 1371 chip_sdma_mem_size(dd)); 1372 1373 per_sdma_credits = 1374 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE); 1375 1376 /* set up freeze waitqueue */ 1377 init_waitqueue_head(&dd->sdma_unfreeze_wq); 1378 atomic_set(&dd->sdma_unfreeze_count, 0); 1379 1380 descq_cnt = sdma_get_descq_cnt(); 1381 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n", 1382 num_engines, descq_cnt); 1383 1384 /* alloc memory for array of send engines */ 1385 dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma), 1386 GFP_KERNEL, dd->node); 1387 if (!dd->per_sdma) 1388 return ret; 1389 1390 idle_cnt = ns_to_cclock(dd, idle_cnt); 1391 if (idle_cnt) 1392 dd->default_desc1 = 1393 SDMA_DESC1_HEAD_TO_HOST_FLAG; 1394 else 1395 dd->default_desc1 = 1396 SDMA_DESC1_INT_REQ_FLAG; 1397 1398 if (!sdma_desct_intr) 1399 sdma_desct_intr = SDMA_DESC_INTR; 1400 1401 /* Allocate memory for SendDMA descriptor FIFOs */ 1402 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1403 sde = &dd->per_sdma[this_idx]; 1404 sde->dd = dd; 1405 sde->ppd = ppd; 1406 sde->this_idx = this_idx; 1407 sde->descq_cnt = descq_cnt; 1408 sde->desc_avail = sdma_descq_freecnt(sde); 1409 sde->sdma_shift = ilog2(descq_cnt); 1410 sde->sdma_mask = (1 << sde->sdma_shift) - 1; 1411 1412 /* Create a mask specifically for each interrupt source */ 1413 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES + 1414 this_idx); 1415 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES + 1416 this_idx); 1417 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES + 1418 this_idx); 1419 /* Create a combined mask to cover all 3 interrupt sources */ 1420 sde->imask = sde->int_mask | sde->progress_mask | 1421 sde->idle_mask; 1422 1423 spin_lock_init(&sde->tail_lock); 1424 seqlock_init(&sde->head_lock); 1425 spin_lock_init(&sde->senddmactrl_lock); 1426 spin_lock_init(&sde->flushlist_lock); 1427 seqlock_init(&sde->waitlock); 1428 /* insure there is always a zero bit */ 1429 sde->ahg_bits = 0xfffffffe00000000ULL; 1430 1431 sdma_set_state(sde, sdma_state_s00_hw_down); 1432 1433 /* set up reference counting */ 1434 kref_init(&sde->state.kref); 1435 init_completion(&sde->state.comp); 1436 1437 INIT_LIST_HEAD(&sde->flushlist); 1438 INIT_LIST_HEAD(&sde->dmawait); 1439 1440 sde->tail_csr = 1441 get_kctxt_csr_addr(dd, this_idx, SD(TAIL)); 1442 1443 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task, 1444 (unsigned long)sde); 1445 1446 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task, 1447 (unsigned long)sde); 1448 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait); 1449 INIT_WORK(&sde->flush_worker, sdma_field_flush); 1450 1451 sde->progress_check_head = 0; 1452 1453 timer_setup(&sde->err_progress_check_timer, 1454 sdma_err_progress_check, 0); 1455 1456 sde->descq = dma_alloc_coherent(&dd->pcidev->dev, 1457 descq_cnt * sizeof(u64[2]), 1458 &sde->descq_phys, GFP_KERNEL); 1459 if (!sde->descq) 1460 goto bail; 1461 sde->tx_ring = 1462 kvzalloc_node(array_size(descq_cnt, 1463 sizeof(struct sdma_txreq *)), 1464 GFP_KERNEL, dd->node); 1465 if (!sde->tx_ring) 1466 goto bail; 1467 } 1468 1469 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; 1470 /* Allocate memory for DMA of head registers to memory */ 1471 dd->sdma_heads_dma = dma_alloc_coherent(&dd->pcidev->dev, 1472 dd->sdma_heads_size, 1473 &dd->sdma_heads_phys, 1474 GFP_KERNEL); 1475 if (!dd->sdma_heads_dma) { 1476 dd_dev_err(dd, "failed to allocate SendDMA head memory\n"); 1477 goto bail; 1478 } 1479 1480 /* Allocate memory for pad */ 1481 dd->sdma_pad_dma = dma_alloc_coherent(&dd->pcidev->dev, sizeof(u32), 1482 &dd->sdma_pad_phys, GFP_KERNEL); 1483 if (!dd->sdma_pad_dma) { 1484 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n"); 1485 goto bail; 1486 } 1487 1488 /* assign each engine to different cacheline and init registers */ 1489 curr_head = (void *)dd->sdma_heads_dma; 1490 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1491 unsigned long phys_offset; 1492 1493 sde = &dd->per_sdma[this_idx]; 1494 1495 sde->head_dma = curr_head; 1496 curr_head += L1_CACHE_BYTES; 1497 phys_offset = (unsigned long)sde->head_dma - 1498 (unsigned long)dd->sdma_heads_dma; 1499 sde->head_phys = dd->sdma_heads_phys + phys_offset; 1500 init_sdma_regs(sde, per_sdma_credits, idle_cnt); 1501 } 1502 dd->flags |= HFI1_HAS_SEND_DMA; 1503 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0; 1504 dd->num_sdma = num_engines; 1505 ret = sdma_map_init(dd, port, ppd->vls_operational, NULL); 1506 if (ret < 0) 1507 goto bail; 1508 1509 tmp_sdma_rht = kzalloc(sizeof(*tmp_sdma_rht), GFP_KERNEL); 1510 if (!tmp_sdma_rht) { 1511 ret = -ENOMEM; 1512 goto bail; 1513 } 1514 1515 ret = rhashtable_init(tmp_sdma_rht, &sdma_rht_params); 1516 if (ret < 0) 1517 goto bail; 1518 dd->sdma_rht = tmp_sdma_rht; 1519 1520 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma); 1521 return 0; 1522 1523 bail: 1524 sdma_clean(dd, num_engines); 1525 return ret; 1526 } 1527 1528 /** 1529 * sdma_all_running() - called when the link goes up 1530 * @dd: hfi1_devdata 1531 * 1532 * This routine moves all engines to the running state. 1533 */ 1534 void sdma_all_running(struct hfi1_devdata *dd) 1535 { 1536 struct sdma_engine *sde; 1537 unsigned int i; 1538 1539 /* move all engines to running */ 1540 for (i = 0; i < dd->num_sdma; ++i) { 1541 sde = &dd->per_sdma[i]; 1542 sdma_process_event(sde, sdma_event_e30_go_running); 1543 } 1544 } 1545 1546 /** 1547 * sdma_all_idle() - called when the link goes down 1548 * @dd: hfi1_devdata 1549 * 1550 * This routine moves all engines to the idle state. 1551 */ 1552 void sdma_all_idle(struct hfi1_devdata *dd) 1553 { 1554 struct sdma_engine *sde; 1555 unsigned int i; 1556 1557 /* idle all engines */ 1558 for (i = 0; i < dd->num_sdma; ++i) { 1559 sde = &dd->per_sdma[i]; 1560 sdma_process_event(sde, sdma_event_e70_go_idle); 1561 } 1562 } 1563 1564 /** 1565 * sdma_start() - called to kick off state processing for all engines 1566 * @dd: hfi1_devdata 1567 * 1568 * This routine is for kicking off the state processing for all required 1569 * sdma engines. Interrupts need to be working at this point. 1570 * 1571 */ 1572 void sdma_start(struct hfi1_devdata *dd) 1573 { 1574 unsigned i; 1575 struct sdma_engine *sde; 1576 1577 /* kick off the engines state processing */ 1578 for (i = 0; i < dd->num_sdma; ++i) { 1579 sde = &dd->per_sdma[i]; 1580 sdma_process_event(sde, sdma_event_e10_go_hw_start); 1581 } 1582 } 1583 1584 /** 1585 * sdma_exit() - used when module is removed 1586 * @dd: hfi1_devdata 1587 */ 1588 void sdma_exit(struct hfi1_devdata *dd) 1589 { 1590 unsigned this_idx; 1591 struct sdma_engine *sde; 1592 1593 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma; 1594 ++this_idx) { 1595 sde = &dd->per_sdma[this_idx]; 1596 if (!list_empty(&sde->dmawait)) 1597 dd_dev_err(dd, "sde %u: dmawait list not empty!\n", 1598 sde->this_idx); 1599 sdma_process_event(sde, sdma_event_e00_go_hw_down); 1600 1601 del_timer_sync(&sde->err_progress_check_timer); 1602 1603 /* 1604 * This waits for the state machine to exit so it is not 1605 * necessary to kill the sdma_sw_clean_up_task to make sure 1606 * it is not running. 1607 */ 1608 sdma_finalput(&sde->state); 1609 } 1610 } 1611 1612 /* 1613 * unmap the indicated descriptor 1614 */ 1615 static inline void sdma_unmap_desc( 1616 struct hfi1_devdata *dd, 1617 struct sdma_desc *descp) 1618 { 1619 switch (sdma_mapping_type(descp)) { 1620 case SDMA_MAP_SINGLE: 1621 dma_unmap_single( 1622 &dd->pcidev->dev, 1623 sdma_mapping_addr(descp), 1624 sdma_mapping_len(descp), 1625 DMA_TO_DEVICE); 1626 break; 1627 case SDMA_MAP_PAGE: 1628 dma_unmap_page( 1629 &dd->pcidev->dev, 1630 sdma_mapping_addr(descp), 1631 sdma_mapping_len(descp), 1632 DMA_TO_DEVICE); 1633 break; 1634 } 1635 } 1636 1637 /* 1638 * return the mode as indicated by the first 1639 * descriptor in the tx. 1640 */ 1641 static inline u8 ahg_mode(struct sdma_txreq *tx) 1642 { 1643 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK) 1644 >> SDMA_DESC1_HEADER_MODE_SHIFT; 1645 } 1646 1647 /** 1648 * __sdma_txclean() - clean tx of mappings, descp *kmalloc's 1649 * @dd: hfi1_devdata for unmapping 1650 * @tx: tx request to clean 1651 * 1652 * This is used in the progress routine to clean the tx or 1653 * by the ULP to toss an in-process tx build. 1654 * 1655 * The code can be called multiple times without issue. 1656 * 1657 */ 1658 void __sdma_txclean( 1659 struct hfi1_devdata *dd, 1660 struct sdma_txreq *tx) 1661 { 1662 u16 i; 1663 1664 if (tx->num_desc) { 1665 u8 skip = 0, mode = ahg_mode(tx); 1666 1667 /* unmap first */ 1668 sdma_unmap_desc(dd, &tx->descp[0]); 1669 /* determine number of AHG descriptors to skip */ 1670 if (mode > SDMA_AHG_APPLY_UPDATE1) 1671 skip = mode >> 1; 1672 for (i = 1 + skip; i < tx->num_desc; i++) 1673 sdma_unmap_desc(dd, &tx->descp[i]); 1674 tx->num_desc = 0; 1675 } 1676 kfree(tx->coalesce_buf); 1677 tx->coalesce_buf = NULL; 1678 /* kmalloc'ed descp */ 1679 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) { 1680 tx->desc_limit = ARRAY_SIZE(tx->descs); 1681 kfree(tx->descp); 1682 } 1683 } 1684 1685 static inline u16 sdma_gethead(struct sdma_engine *sde) 1686 { 1687 struct hfi1_devdata *dd = sde->dd; 1688 int use_dmahead; 1689 u16 hwhead; 1690 1691 #ifdef CONFIG_SDMA_VERBOSITY 1692 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 1693 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 1694 #endif 1695 1696 retry: 1697 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) && 1698 (dd->flags & HFI1_HAS_SDMA_TIMEOUT); 1699 hwhead = use_dmahead ? 1700 (u16)le64_to_cpu(*sde->head_dma) : 1701 (u16)read_sde_csr(sde, SD(HEAD)); 1702 1703 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) { 1704 u16 cnt; 1705 u16 swtail; 1706 u16 swhead; 1707 int sane; 1708 1709 swhead = sde->descq_head & sde->sdma_mask; 1710 /* this code is really bad for cache line trading */ 1711 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask; 1712 cnt = sde->descq_cnt; 1713 1714 if (swhead < swtail) 1715 /* not wrapped */ 1716 sane = (hwhead >= swhead) & (hwhead <= swtail); 1717 else if (swhead > swtail) 1718 /* wrapped around */ 1719 sane = ((hwhead >= swhead) && (hwhead < cnt)) || 1720 (hwhead <= swtail); 1721 else 1722 /* empty */ 1723 sane = (hwhead == swhead); 1724 1725 if (unlikely(!sane)) { 1726 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n", 1727 sde->this_idx, 1728 use_dmahead ? "dma" : "kreg", 1729 hwhead, swhead, swtail, cnt); 1730 if (use_dmahead) { 1731 /* try one more time, using csr */ 1732 use_dmahead = 0; 1733 goto retry; 1734 } 1735 /* proceed as if no progress */ 1736 hwhead = swhead; 1737 } 1738 } 1739 return hwhead; 1740 } 1741 1742 /* 1743 * This is called when there are send DMA descriptors that might be 1744 * available. 1745 * 1746 * This is called with head_lock held. 1747 */ 1748 static void sdma_desc_avail(struct sdma_engine *sde, uint avail) 1749 { 1750 struct iowait *wait, *nw; 1751 struct iowait *waits[SDMA_WAIT_BATCH_SIZE]; 1752 uint i, n = 0, seq, max_idx = 0; 1753 u8 max_starved_cnt = 0; 1754 1755 #ifdef CONFIG_SDMA_VERBOSITY 1756 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 1757 slashstrip(__FILE__), __LINE__, __func__); 1758 dd_dev_err(sde->dd, "avail: %u\n", avail); 1759 #endif 1760 1761 do { 1762 seq = read_seqbegin(&sde->waitlock); 1763 if (!list_empty(&sde->dmawait)) { 1764 /* at least one item */ 1765 write_seqlock(&sde->waitlock); 1766 /* Harvest waiters wanting DMA descriptors */ 1767 list_for_each_entry_safe( 1768 wait, 1769 nw, 1770 &sde->dmawait, 1771 list) { 1772 u32 num_desc; 1773 1774 if (!wait->wakeup) 1775 continue; 1776 if (n == ARRAY_SIZE(waits)) 1777 break; 1778 num_desc = iowait_get_all_desc(wait); 1779 if (num_desc > avail) 1780 break; 1781 avail -= num_desc; 1782 /* Find the most starved wait memeber */ 1783 iowait_starve_find_max(wait, &max_starved_cnt, 1784 n, &max_idx); 1785 list_del_init(&wait->list); 1786 waits[n++] = wait; 1787 } 1788 write_sequnlock(&sde->waitlock); 1789 break; 1790 } 1791 } while (read_seqretry(&sde->waitlock, seq)); 1792 1793 /* Schedule the most starved one first */ 1794 if (n) 1795 waits[max_idx]->wakeup(waits[max_idx], SDMA_AVAIL_REASON); 1796 1797 for (i = 0; i < n; i++) 1798 if (i != max_idx) 1799 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON); 1800 } 1801 1802 /* head_lock must be held */ 1803 static void sdma_make_progress(struct sdma_engine *sde, u64 status) 1804 { 1805 struct sdma_txreq *txp = NULL; 1806 int progress = 0; 1807 u16 hwhead, swhead; 1808 int idle_check_done = 0; 1809 1810 hwhead = sdma_gethead(sde); 1811 1812 /* The reason for some of the complexity of this code is that 1813 * not all descriptors have corresponding txps. So, we have to 1814 * be able to skip over descs until we wander into the range of 1815 * the next txp on the list. 1816 */ 1817 1818 retry: 1819 txp = get_txhead(sde); 1820 swhead = sde->descq_head & sde->sdma_mask; 1821 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); 1822 while (swhead != hwhead) { 1823 /* advance head, wrap if needed */ 1824 swhead = ++sde->descq_head & sde->sdma_mask; 1825 1826 /* if now past this txp's descs, do the callback */ 1827 if (txp && txp->next_descq_idx == swhead) { 1828 /* remove from list */ 1829 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; 1830 complete_tx(sde, txp, SDMA_TXREQ_S_OK); 1831 /* see if there is another txp */ 1832 txp = get_txhead(sde); 1833 } 1834 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); 1835 progress++; 1836 } 1837 1838 /* 1839 * The SDMA idle interrupt is not guaranteed to be ordered with respect 1840 * to updates to the the dma_head location in host memory. The head 1841 * value read might not be fully up to date. If there are pending 1842 * descriptors and the SDMA idle interrupt fired then read from the 1843 * CSR SDMA head instead to get the latest value from the hardware. 1844 * The hardware SDMA head should be read at most once in this invocation 1845 * of sdma_make_progress(..) which is ensured by idle_check_done flag 1846 */ 1847 if ((status & sde->idle_mask) && !idle_check_done) { 1848 u16 swtail; 1849 1850 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask; 1851 if (swtail != hwhead) { 1852 hwhead = (u16)read_sde_csr(sde, SD(HEAD)); 1853 idle_check_done = 1; 1854 goto retry; 1855 } 1856 } 1857 1858 sde->last_status = status; 1859 if (progress) 1860 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 1861 } 1862 1863 /* 1864 * sdma_engine_interrupt() - interrupt handler for engine 1865 * @sde: sdma engine 1866 * @status: sdma interrupt reason 1867 * 1868 * Status is a mask of the 3 possible interrupts for this engine. It will 1869 * contain bits _only_ for this SDMA engine. It will contain at least one 1870 * bit, it may contain more. 1871 */ 1872 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status) 1873 { 1874 trace_hfi1_sdma_engine_interrupt(sde, status); 1875 write_seqlock(&sde->head_lock); 1876 sdma_set_desc_cnt(sde, sdma_desct_intr); 1877 if (status & sde->idle_mask) 1878 sde->idle_int_cnt++; 1879 else if (status & sde->progress_mask) 1880 sde->progress_int_cnt++; 1881 else if (status & sde->int_mask) 1882 sde->sdma_int_cnt++; 1883 sdma_make_progress(sde, status); 1884 write_sequnlock(&sde->head_lock); 1885 } 1886 1887 /** 1888 * sdma_engine_error() - error handler for engine 1889 * @sde: sdma engine 1890 * @status: sdma interrupt reason 1891 */ 1892 void sdma_engine_error(struct sdma_engine *sde, u64 status) 1893 { 1894 unsigned long flags; 1895 1896 #ifdef CONFIG_SDMA_VERBOSITY 1897 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n", 1898 sde->this_idx, 1899 (unsigned long long)status, 1900 sdma_state_names[sde->state.current_state]); 1901 #endif 1902 spin_lock_irqsave(&sde->tail_lock, flags); 1903 write_seqlock(&sde->head_lock); 1904 if (status & ALL_SDMA_ENG_HALT_ERRS) 1905 __sdma_process_event(sde, sdma_event_e60_hw_halted); 1906 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) { 1907 dd_dev_err(sde->dd, 1908 "SDMA (%u) engine error: 0x%llx state %s\n", 1909 sde->this_idx, 1910 (unsigned long long)status, 1911 sdma_state_names[sde->state.current_state]); 1912 dump_sdma_state(sde); 1913 } 1914 write_sequnlock(&sde->head_lock); 1915 spin_unlock_irqrestore(&sde->tail_lock, flags); 1916 } 1917 1918 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op) 1919 { 1920 u64 set_senddmactrl = 0; 1921 u64 clr_senddmactrl = 0; 1922 unsigned long flags; 1923 1924 #ifdef CONFIG_SDMA_VERBOSITY 1925 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n", 1926 sde->this_idx, 1927 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0, 1928 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0, 1929 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0, 1930 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0); 1931 #endif 1932 1933 if (op & SDMA_SENDCTRL_OP_ENABLE) 1934 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); 1935 else 1936 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); 1937 1938 if (op & SDMA_SENDCTRL_OP_INTENABLE) 1939 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); 1940 else 1941 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); 1942 1943 if (op & SDMA_SENDCTRL_OP_HALT) 1944 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); 1945 else 1946 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); 1947 1948 spin_lock_irqsave(&sde->senddmactrl_lock, flags); 1949 1950 sde->p_senddmactrl |= set_senddmactrl; 1951 sde->p_senddmactrl &= ~clr_senddmactrl; 1952 1953 if (op & SDMA_SENDCTRL_OP_CLEANUP) 1954 write_sde_csr(sde, SD(CTRL), 1955 sde->p_senddmactrl | 1956 SD(CTRL_SDMA_CLEANUP_SMASK)); 1957 else 1958 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl); 1959 1960 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags); 1961 1962 #ifdef CONFIG_SDMA_VERBOSITY 1963 sdma_dumpstate(sde); 1964 #endif 1965 } 1966 1967 static void sdma_setlengen(struct sdma_engine *sde) 1968 { 1969 #ifdef CONFIG_SDMA_VERBOSITY 1970 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 1971 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 1972 #endif 1973 1974 /* 1975 * Set SendDmaLenGen and clear-then-set the MSB of the generation 1976 * count to enable generation checking and load the internal 1977 * generation counter. 1978 */ 1979 write_sde_csr(sde, SD(LEN_GEN), 1980 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)); 1981 write_sde_csr(sde, SD(LEN_GEN), 1982 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) | 1983 (4ULL << SD(LEN_GEN_GENERATION_SHIFT))); 1984 } 1985 1986 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail) 1987 { 1988 /* Commit writes to memory and advance the tail on the chip */ 1989 smp_wmb(); /* see get_txhead() */ 1990 writeq(tail, sde->tail_csr); 1991 } 1992 1993 /* 1994 * This is called when changing to state s10_hw_start_up_halt_wait as 1995 * a result of send buffer errors or send DMA descriptor errors. 1996 */ 1997 static void sdma_hw_start_up(struct sdma_engine *sde) 1998 { 1999 u64 reg; 2000 2001 #ifdef CONFIG_SDMA_VERBOSITY 2002 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 2003 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 2004 #endif 2005 2006 sdma_setlengen(sde); 2007 sdma_update_tail(sde, 0); /* Set SendDmaTail */ 2008 *sde->head_dma = 0; 2009 2010 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) << 2011 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT); 2012 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg); 2013 } 2014 2015 /* 2016 * set_sdma_integrity 2017 * 2018 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'. 2019 */ 2020 static void set_sdma_integrity(struct sdma_engine *sde) 2021 { 2022 struct hfi1_devdata *dd = sde->dd; 2023 2024 write_sde_csr(sde, SD(CHECK_ENABLE), 2025 hfi1_pkt_base_sdma_integrity(dd)); 2026 } 2027 2028 static void init_sdma_regs( 2029 struct sdma_engine *sde, 2030 u32 credits, 2031 uint idle_cnt) 2032 { 2033 u8 opval, opmask; 2034 #ifdef CONFIG_SDMA_VERBOSITY 2035 struct hfi1_devdata *dd = sde->dd; 2036 2037 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", 2038 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 2039 #endif 2040 2041 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys); 2042 sdma_setlengen(sde); 2043 sdma_update_tail(sde, 0); /* Set SendDmaTail */ 2044 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt); 2045 write_sde_csr(sde, SD(DESC_CNT), 0); 2046 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys); 2047 write_sde_csr(sde, SD(MEMORY), 2048 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) | 2049 ((u64)(credits * sde->this_idx) << 2050 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT))); 2051 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull); 2052 set_sdma_integrity(sde); 2053 opmask = OPCODE_CHECK_MASK_DISABLED; 2054 opval = OPCODE_CHECK_VAL_DISABLED; 2055 write_sde_csr(sde, SD(CHECK_OPCODE), 2056 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) | 2057 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT)); 2058 } 2059 2060 #ifdef CONFIG_SDMA_VERBOSITY 2061 2062 #define sdma_dumpstate_helper0(reg) do { \ 2063 csr = read_csr(sde->dd, reg); \ 2064 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \ 2065 } while (0) 2066 2067 #define sdma_dumpstate_helper(reg) do { \ 2068 csr = read_sde_csr(sde, reg); \ 2069 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \ 2070 #reg, sde->this_idx, csr); \ 2071 } while (0) 2072 2073 #define sdma_dumpstate_helper2(reg) do { \ 2074 csr = read_csr(sde->dd, reg + (8 * i)); \ 2075 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \ 2076 #reg, i, csr); \ 2077 } while (0) 2078 2079 void sdma_dumpstate(struct sdma_engine *sde) 2080 { 2081 u64 csr; 2082 unsigned i; 2083 2084 sdma_dumpstate_helper(SD(CTRL)); 2085 sdma_dumpstate_helper(SD(STATUS)); 2086 sdma_dumpstate_helper0(SD(ERR_STATUS)); 2087 sdma_dumpstate_helper0(SD(ERR_MASK)); 2088 sdma_dumpstate_helper(SD(ENG_ERR_STATUS)); 2089 sdma_dumpstate_helper(SD(ENG_ERR_MASK)); 2090 2091 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) { 2092 sdma_dumpstate_helper2(CCE_INT_STATUS); 2093 sdma_dumpstate_helper2(CCE_INT_MASK); 2094 sdma_dumpstate_helper2(CCE_INT_BLOCKED); 2095 } 2096 2097 sdma_dumpstate_helper(SD(TAIL)); 2098 sdma_dumpstate_helper(SD(HEAD)); 2099 sdma_dumpstate_helper(SD(PRIORITY_THLD)); 2100 sdma_dumpstate_helper(SD(IDLE_CNT)); 2101 sdma_dumpstate_helper(SD(RELOAD_CNT)); 2102 sdma_dumpstate_helper(SD(DESC_CNT)); 2103 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT)); 2104 sdma_dumpstate_helper(SD(MEMORY)); 2105 sdma_dumpstate_helper0(SD(ENGINES)); 2106 sdma_dumpstate_helper0(SD(MEM_SIZE)); 2107 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */ 2108 sdma_dumpstate_helper(SD(BASE_ADDR)); 2109 sdma_dumpstate_helper(SD(LEN_GEN)); 2110 sdma_dumpstate_helper(SD(HEAD_ADDR)); 2111 sdma_dumpstate_helper(SD(CHECK_ENABLE)); 2112 sdma_dumpstate_helper(SD(CHECK_VL)); 2113 sdma_dumpstate_helper(SD(CHECK_JOB_KEY)); 2114 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY)); 2115 sdma_dumpstate_helper(SD(CHECK_SLID)); 2116 sdma_dumpstate_helper(SD(CHECK_OPCODE)); 2117 } 2118 #endif 2119 2120 static void dump_sdma_state(struct sdma_engine *sde) 2121 { 2122 struct hw_sdma_desc *descqp; 2123 u64 desc[2]; 2124 u64 addr; 2125 u8 gen; 2126 u16 len; 2127 u16 head, tail, cnt; 2128 2129 head = sde->descq_head & sde->sdma_mask; 2130 tail = sde->descq_tail & sde->sdma_mask; 2131 cnt = sdma_descq_freecnt(sde); 2132 2133 dd_dev_err(sde->dd, 2134 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n", 2135 sde->this_idx, head, tail, cnt, 2136 !list_empty(&sde->flushlist)); 2137 2138 /* print info for each entry in the descriptor queue */ 2139 while (head != tail) { 2140 char flags[6] = { 'x', 'x', 'x', 'x', 0 }; 2141 2142 descqp = &sde->descq[head]; 2143 desc[0] = le64_to_cpu(descqp->qw[0]); 2144 desc[1] = le64_to_cpu(descqp->qw[1]); 2145 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; 2146 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 2147 'H' : '-'; 2148 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; 2149 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; 2150 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) 2151 & SDMA_DESC0_PHY_ADDR_MASK; 2152 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) 2153 & SDMA_DESC1_GENERATION_MASK; 2154 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) 2155 & SDMA_DESC0_BYTE_COUNT_MASK; 2156 dd_dev_err(sde->dd, 2157 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", 2158 head, flags, addr, gen, len); 2159 dd_dev_err(sde->dd, 2160 "\tdesc0:0x%016llx desc1 0x%016llx\n", 2161 desc[0], desc[1]); 2162 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) 2163 dd_dev_err(sde->dd, 2164 "\taidx: %u amode: %u alen: %u\n", 2165 (u8)((desc[1] & 2166 SDMA_DESC1_HEADER_INDEX_SMASK) >> 2167 SDMA_DESC1_HEADER_INDEX_SHIFT), 2168 (u8)((desc[1] & 2169 SDMA_DESC1_HEADER_MODE_SMASK) >> 2170 SDMA_DESC1_HEADER_MODE_SHIFT), 2171 (u8)((desc[1] & 2172 SDMA_DESC1_HEADER_DWS_SMASK) >> 2173 SDMA_DESC1_HEADER_DWS_SHIFT)); 2174 head++; 2175 head &= sde->sdma_mask; 2176 } 2177 } 2178 2179 #define SDE_FMT \ 2180 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n" 2181 /** 2182 * sdma_seqfile_dump_sde() - debugfs dump of sde 2183 * @s: seq file 2184 * @sde: send dma engine to dump 2185 * 2186 * This routine dumps the sde to the indicated seq file. 2187 */ 2188 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde) 2189 { 2190 u16 head, tail; 2191 struct hw_sdma_desc *descqp; 2192 u64 desc[2]; 2193 u64 addr; 2194 u8 gen; 2195 u16 len; 2196 2197 head = sde->descq_head & sde->sdma_mask; 2198 tail = READ_ONCE(sde->descq_tail) & sde->sdma_mask; 2199 seq_printf(s, SDE_FMT, sde->this_idx, 2200 sde->cpu, 2201 sdma_state_name(sde->state.current_state), 2202 (unsigned long long)read_sde_csr(sde, SD(CTRL)), 2203 (unsigned long long)read_sde_csr(sde, SD(STATUS)), 2204 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)), 2205 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail, 2206 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head, 2207 (unsigned long long)le64_to_cpu(*sde->head_dma), 2208 (unsigned long long)read_sde_csr(sde, SD(MEMORY)), 2209 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)), 2210 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)), 2211 (unsigned long long)sde->last_status, 2212 (unsigned long long)sde->ahg_bits, 2213 sde->tx_tail, 2214 sde->tx_head, 2215 sde->descq_tail, 2216 sde->descq_head, 2217 !list_empty(&sde->flushlist), 2218 sde->descq_full_count, 2219 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID)); 2220 2221 /* print info for each entry in the descriptor queue */ 2222 while (head != tail) { 2223 char flags[6] = { 'x', 'x', 'x', 'x', 0 }; 2224 2225 descqp = &sde->descq[head]; 2226 desc[0] = le64_to_cpu(descqp->qw[0]); 2227 desc[1] = le64_to_cpu(descqp->qw[1]); 2228 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; 2229 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 2230 'H' : '-'; 2231 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; 2232 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; 2233 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) 2234 & SDMA_DESC0_PHY_ADDR_MASK; 2235 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) 2236 & SDMA_DESC1_GENERATION_MASK; 2237 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) 2238 & SDMA_DESC0_BYTE_COUNT_MASK; 2239 seq_printf(s, 2240 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", 2241 head, flags, addr, gen, len); 2242 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) 2243 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n", 2244 (u8)((desc[1] & 2245 SDMA_DESC1_HEADER_INDEX_SMASK) >> 2246 SDMA_DESC1_HEADER_INDEX_SHIFT), 2247 (u8)((desc[1] & 2248 SDMA_DESC1_HEADER_MODE_SMASK) >> 2249 SDMA_DESC1_HEADER_MODE_SHIFT)); 2250 head = (head + 1) & sde->sdma_mask; 2251 } 2252 } 2253 2254 /* 2255 * add the generation number into 2256 * the qw1 and return 2257 */ 2258 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1) 2259 { 2260 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3; 2261 2262 qw1 &= ~SDMA_DESC1_GENERATION_SMASK; 2263 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK) 2264 << SDMA_DESC1_GENERATION_SHIFT; 2265 return qw1; 2266 } 2267 2268 /* 2269 * This routine submits the indicated tx 2270 * 2271 * Space has already been guaranteed and 2272 * tail side of ring is locked. 2273 * 2274 * The hardware tail update is done 2275 * in the caller and that is facilitated 2276 * by returning the new tail. 2277 * 2278 * There is special case logic for ahg 2279 * to not add the generation number for 2280 * up to 2 descriptors that follow the 2281 * first descriptor. 2282 * 2283 */ 2284 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx) 2285 { 2286 int i; 2287 u16 tail; 2288 struct sdma_desc *descp = tx->descp; 2289 u8 skip = 0, mode = ahg_mode(tx); 2290 2291 tail = sde->descq_tail & sde->sdma_mask; 2292 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); 2293 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1])); 2294 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1], 2295 tail, &sde->descq[tail]); 2296 tail = ++sde->descq_tail & sde->sdma_mask; 2297 descp++; 2298 if (mode > SDMA_AHG_APPLY_UPDATE1) 2299 skip = mode >> 1; 2300 for (i = 1; i < tx->num_desc; i++, descp++) { 2301 u64 qw1; 2302 2303 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); 2304 if (skip) { 2305 /* edits don't have generation */ 2306 qw1 = descp->qw[1]; 2307 skip--; 2308 } else { 2309 /* replace generation with real one for non-edits */ 2310 qw1 = add_gen(sde, descp->qw[1]); 2311 } 2312 sde->descq[tail].qw[1] = cpu_to_le64(qw1); 2313 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1, 2314 tail, &sde->descq[tail]); 2315 tail = ++sde->descq_tail & sde->sdma_mask; 2316 } 2317 tx->next_descq_idx = tail; 2318 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2319 tx->sn = sde->tail_sn++; 2320 trace_hfi1_sdma_in_sn(sde, tx->sn); 2321 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]); 2322 #endif 2323 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx; 2324 sde->desc_avail -= tx->num_desc; 2325 return tail; 2326 } 2327 2328 /* 2329 * Check for progress 2330 */ 2331 static int sdma_check_progress( 2332 struct sdma_engine *sde, 2333 struct iowait_work *wait, 2334 struct sdma_txreq *tx, 2335 bool pkts_sent) 2336 { 2337 int ret; 2338 2339 sde->desc_avail = sdma_descq_freecnt(sde); 2340 if (tx->num_desc <= sde->desc_avail) 2341 return -EAGAIN; 2342 /* pulse the head_lock */ 2343 if (wait && iowait_ioww_to_iow(wait)->sleep) { 2344 unsigned seq; 2345 2346 seq = raw_seqcount_begin( 2347 (const seqcount_t *)&sde->head_lock.seqcount); 2348 ret = wait->iow->sleep(sde, wait, tx, seq, pkts_sent); 2349 if (ret == -EAGAIN) 2350 sde->desc_avail = sdma_descq_freecnt(sde); 2351 } else { 2352 ret = -EBUSY; 2353 } 2354 return ret; 2355 } 2356 2357 /** 2358 * sdma_send_txreq() - submit a tx req to ring 2359 * @sde: sdma engine to use 2360 * @wait: SE wait structure to use when full (may be NULL) 2361 * @tx: sdma_txreq to submit 2362 * @pkts_sent: has any packet been sent yet? 2363 * 2364 * The call submits the tx into the ring. If a iowait structure is non-NULL 2365 * the packet will be queued to the list in wait. 2366 * 2367 * Return: 2368 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in 2369 * ring (wait == NULL) 2370 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state 2371 */ 2372 int sdma_send_txreq(struct sdma_engine *sde, 2373 struct iowait_work *wait, 2374 struct sdma_txreq *tx, 2375 bool pkts_sent) 2376 { 2377 int ret = 0; 2378 u16 tail; 2379 unsigned long flags; 2380 2381 /* user should have supplied entire packet */ 2382 if (unlikely(tx->tlen)) 2383 return -EINVAL; 2384 tx->wait = iowait_ioww_to_iow(wait); 2385 spin_lock_irqsave(&sde->tail_lock, flags); 2386 retry: 2387 if (unlikely(!__sdma_running(sde))) 2388 goto unlock_noconn; 2389 if (unlikely(tx->num_desc > sde->desc_avail)) 2390 goto nodesc; 2391 tail = submit_tx(sde, tx); 2392 if (wait) 2393 iowait_sdma_inc(iowait_ioww_to_iow(wait)); 2394 sdma_update_tail(sde, tail); 2395 unlock: 2396 spin_unlock_irqrestore(&sde->tail_lock, flags); 2397 return ret; 2398 unlock_noconn: 2399 if (wait) 2400 iowait_sdma_inc(iowait_ioww_to_iow(wait)); 2401 tx->next_descq_idx = 0; 2402 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2403 tx->sn = sde->tail_sn++; 2404 trace_hfi1_sdma_in_sn(sde, tx->sn); 2405 #endif 2406 spin_lock(&sde->flushlist_lock); 2407 list_add_tail(&tx->list, &sde->flushlist); 2408 spin_unlock(&sde->flushlist_lock); 2409 iowait_inc_wait_count(wait, tx->num_desc); 2410 schedule_work(&sde->flush_worker); 2411 ret = -ECOMM; 2412 goto unlock; 2413 nodesc: 2414 ret = sdma_check_progress(sde, wait, tx, pkts_sent); 2415 if (ret == -EAGAIN) { 2416 ret = 0; 2417 goto retry; 2418 } 2419 sde->descq_full_count++; 2420 goto unlock; 2421 } 2422 2423 /** 2424 * sdma_send_txlist() - submit a list of tx req to ring 2425 * @sde: sdma engine to use 2426 * @wait: SE wait structure to use when full (may be NULL) 2427 * @tx_list: list of sdma_txreqs to submit 2428 * @count: pointer to a u16 which, after return will contain the total number of 2429 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs 2430 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs 2431 * which are added to SDMA engine flush list if the SDMA engine state is 2432 * not running. 2433 * 2434 * The call submits the list into the ring. 2435 * 2436 * If the iowait structure is non-NULL and not equal to the iowait list 2437 * the unprocessed part of the list will be appended to the list in wait. 2438 * 2439 * In all cases, the tx_list will be updated so the head of the tx_list is 2440 * the list of descriptors that have yet to be transmitted. 2441 * 2442 * The intent of this call is to provide a more efficient 2443 * way of submitting multiple packets to SDMA while holding the tail 2444 * side locking. 2445 * 2446 * Return: 2447 * 0 - Success, 2448 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL) 2449 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state 2450 */ 2451 int sdma_send_txlist(struct sdma_engine *sde, struct iowait_work *wait, 2452 struct list_head *tx_list, u16 *count_out) 2453 { 2454 struct sdma_txreq *tx, *tx_next; 2455 int ret = 0; 2456 unsigned long flags; 2457 u16 tail = INVALID_TAIL; 2458 u32 submit_count = 0, flush_count = 0, total_count; 2459 2460 spin_lock_irqsave(&sde->tail_lock, flags); 2461 retry: 2462 list_for_each_entry_safe(tx, tx_next, tx_list, list) { 2463 tx->wait = iowait_ioww_to_iow(wait); 2464 if (unlikely(!__sdma_running(sde))) 2465 goto unlock_noconn; 2466 if (unlikely(tx->num_desc > sde->desc_avail)) 2467 goto nodesc; 2468 if (unlikely(tx->tlen)) { 2469 ret = -EINVAL; 2470 goto update_tail; 2471 } 2472 list_del_init(&tx->list); 2473 tail = submit_tx(sde, tx); 2474 submit_count++; 2475 if (tail != INVALID_TAIL && 2476 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) { 2477 sdma_update_tail(sde, tail); 2478 tail = INVALID_TAIL; 2479 } 2480 } 2481 update_tail: 2482 total_count = submit_count + flush_count; 2483 if (wait) { 2484 iowait_sdma_add(iowait_ioww_to_iow(wait), total_count); 2485 iowait_starve_clear(submit_count > 0, 2486 iowait_ioww_to_iow(wait)); 2487 } 2488 if (tail != INVALID_TAIL) 2489 sdma_update_tail(sde, tail); 2490 spin_unlock_irqrestore(&sde->tail_lock, flags); 2491 *count_out = total_count; 2492 return ret; 2493 unlock_noconn: 2494 spin_lock(&sde->flushlist_lock); 2495 list_for_each_entry_safe(tx, tx_next, tx_list, list) { 2496 tx->wait = iowait_ioww_to_iow(wait); 2497 list_del_init(&tx->list); 2498 tx->next_descq_idx = 0; 2499 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2500 tx->sn = sde->tail_sn++; 2501 trace_hfi1_sdma_in_sn(sde, tx->sn); 2502 #endif 2503 list_add_tail(&tx->list, &sde->flushlist); 2504 flush_count++; 2505 iowait_inc_wait_count(wait, tx->num_desc); 2506 } 2507 spin_unlock(&sde->flushlist_lock); 2508 schedule_work(&sde->flush_worker); 2509 ret = -ECOMM; 2510 goto update_tail; 2511 nodesc: 2512 ret = sdma_check_progress(sde, wait, tx, submit_count > 0); 2513 if (ret == -EAGAIN) { 2514 ret = 0; 2515 goto retry; 2516 } 2517 sde->descq_full_count++; 2518 goto update_tail; 2519 } 2520 2521 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event) 2522 { 2523 unsigned long flags; 2524 2525 spin_lock_irqsave(&sde->tail_lock, flags); 2526 write_seqlock(&sde->head_lock); 2527 2528 __sdma_process_event(sde, event); 2529 2530 if (sde->state.current_state == sdma_state_s99_running) 2531 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 2532 2533 write_sequnlock(&sde->head_lock); 2534 spin_unlock_irqrestore(&sde->tail_lock, flags); 2535 } 2536 2537 static void __sdma_process_event(struct sdma_engine *sde, 2538 enum sdma_events event) 2539 { 2540 struct sdma_state *ss = &sde->state; 2541 int need_progress = 0; 2542 2543 /* CONFIG SDMA temporary */ 2544 #ifdef CONFIG_SDMA_VERBOSITY 2545 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx, 2546 sdma_state_names[ss->current_state], 2547 sdma_event_names[event]); 2548 #endif 2549 2550 switch (ss->current_state) { 2551 case sdma_state_s00_hw_down: 2552 switch (event) { 2553 case sdma_event_e00_go_hw_down: 2554 break; 2555 case sdma_event_e30_go_running: 2556 /* 2557 * If down, but running requested (usually result 2558 * of link up, then we need to start up. 2559 * This can happen when hw down is requested while 2560 * bringing the link up with traffic active on 2561 * 7220, e.g. 2562 */ 2563 ss->go_s99_running = 1; 2564 /* fall through -- and start dma engine */ 2565 case sdma_event_e10_go_hw_start: 2566 /* This reference means the state machine is started */ 2567 sdma_get(&sde->state); 2568 sdma_set_state(sde, 2569 sdma_state_s10_hw_start_up_halt_wait); 2570 break; 2571 case sdma_event_e15_hw_halt_done: 2572 break; 2573 case sdma_event_e25_hw_clean_up_done: 2574 break; 2575 case sdma_event_e40_sw_cleaned: 2576 sdma_sw_tear_down(sde); 2577 break; 2578 case sdma_event_e50_hw_cleaned: 2579 break; 2580 case sdma_event_e60_hw_halted: 2581 break; 2582 case sdma_event_e70_go_idle: 2583 break; 2584 case sdma_event_e80_hw_freeze: 2585 break; 2586 case sdma_event_e81_hw_frozen: 2587 break; 2588 case sdma_event_e82_hw_unfreeze: 2589 break; 2590 case sdma_event_e85_link_down: 2591 break; 2592 case sdma_event_e90_sw_halted: 2593 break; 2594 } 2595 break; 2596 2597 case sdma_state_s10_hw_start_up_halt_wait: 2598 switch (event) { 2599 case sdma_event_e00_go_hw_down: 2600 sdma_set_state(sde, sdma_state_s00_hw_down); 2601 sdma_sw_tear_down(sde); 2602 break; 2603 case sdma_event_e10_go_hw_start: 2604 break; 2605 case sdma_event_e15_hw_halt_done: 2606 sdma_set_state(sde, 2607 sdma_state_s15_hw_start_up_clean_wait); 2608 sdma_start_hw_clean_up(sde); 2609 break; 2610 case sdma_event_e25_hw_clean_up_done: 2611 break; 2612 case sdma_event_e30_go_running: 2613 ss->go_s99_running = 1; 2614 break; 2615 case sdma_event_e40_sw_cleaned: 2616 break; 2617 case sdma_event_e50_hw_cleaned: 2618 break; 2619 case sdma_event_e60_hw_halted: 2620 schedule_work(&sde->err_halt_worker); 2621 break; 2622 case sdma_event_e70_go_idle: 2623 ss->go_s99_running = 0; 2624 break; 2625 case sdma_event_e80_hw_freeze: 2626 break; 2627 case sdma_event_e81_hw_frozen: 2628 break; 2629 case sdma_event_e82_hw_unfreeze: 2630 break; 2631 case sdma_event_e85_link_down: 2632 break; 2633 case sdma_event_e90_sw_halted: 2634 break; 2635 } 2636 break; 2637 2638 case sdma_state_s15_hw_start_up_clean_wait: 2639 switch (event) { 2640 case sdma_event_e00_go_hw_down: 2641 sdma_set_state(sde, sdma_state_s00_hw_down); 2642 sdma_sw_tear_down(sde); 2643 break; 2644 case sdma_event_e10_go_hw_start: 2645 break; 2646 case sdma_event_e15_hw_halt_done: 2647 break; 2648 case sdma_event_e25_hw_clean_up_done: 2649 sdma_hw_start_up(sde); 2650 sdma_set_state(sde, ss->go_s99_running ? 2651 sdma_state_s99_running : 2652 sdma_state_s20_idle); 2653 break; 2654 case sdma_event_e30_go_running: 2655 ss->go_s99_running = 1; 2656 break; 2657 case sdma_event_e40_sw_cleaned: 2658 break; 2659 case sdma_event_e50_hw_cleaned: 2660 break; 2661 case sdma_event_e60_hw_halted: 2662 break; 2663 case sdma_event_e70_go_idle: 2664 ss->go_s99_running = 0; 2665 break; 2666 case sdma_event_e80_hw_freeze: 2667 break; 2668 case sdma_event_e81_hw_frozen: 2669 break; 2670 case sdma_event_e82_hw_unfreeze: 2671 break; 2672 case sdma_event_e85_link_down: 2673 break; 2674 case sdma_event_e90_sw_halted: 2675 break; 2676 } 2677 break; 2678 2679 case sdma_state_s20_idle: 2680 switch (event) { 2681 case sdma_event_e00_go_hw_down: 2682 sdma_set_state(sde, sdma_state_s00_hw_down); 2683 sdma_sw_tear_down(sde); 2684 break; 2685 case sdma_event_e10_go_hw_start: 2686 break; 2687 case sdma_event_e15_hw_halt_done: 2688 break; 2689 case sdma_event_e25_hw_clean_up_done: 2690 break; 2691 case sdma_event_e30_go_running: 2692 sdma_set_state(sde, sdma_state_s99_running); 2693 ss->go_s99_running = 1; 2694 break; 2695 case sdma_event_e40_sw_cleaned: 2696 break; 2697 case sdma_event_e50_hw_cleaned: 2698 break; 2699 case sdma_event_e60_hw_halted: 2700 sdma_set_state(sde, sdma_state_s50_hw_halt_wait); 2701 schedule_work(&sde->err_halt_worker); 2702 break; 2703 case sdma_event_e70_go_idle: 2704 break; 2705 case sdma_event_e85_link_down: 2706 /* fall through */ 2707 case sdma_event_e80_hw_freeze: 2708 sdma_set_state(sde, sdma_state_s80_hw_freeze); 2709 atomic_dec(&sde->dd->sdma_unfreeze_count); 2710 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 2711 break; 2712 case sdma_event_e81_hw_frozen: 2713 break; 2714 case sdma_event_e82_hw_unfreeze: 2715 break; 2716 case sdma_event_e90_sw_halted: 2717 break; 2718 } 2719 break; 2720 2721 case sdma_state_s30_sw_clean_up_wait: 2722 switch (event) { 2723 case sdma_event_e00_go_hw_down: 2724 sdma_set_state(sde, sdma_state_s00_hw_down); 2725 break; 2726 case sdma_event_e10_go_hw_start: 2727 break; 2728 case sdma_event_e15_hw_halt_done: 2729 break; 2730 case sdma_event_e25_hw_clean_up_done: 2731 break; 2732 case sdma_event_e30_go_running: 2733 ss->go_s99_running = 1; 2734 break; 2735 case sdma_event_e40_sw_cleaned: 2736 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait); 2737 sdma_start_hw_clean_up(sde); 2738 break; 2739 case sdma_event_e50_hw_cleaned: 2740 break; 2741 case sdma_event_e60_hw_halted: 2742 break; 2743 case sdma_event_e70_go_idle: 2744 ss->go_s99_running = 0; 2745 break; 2746 case sdma_event_e80_hw_freeze: 2747 break; 2748 case sdma_event_e81_hw_frozen: 2749 break; 2750 case sdma_event_e82_hw_unfreeze: 2751 break; 2752 case sdma_event_e85_link_down: 2753 ss->go_s99_running = 0; 2754 break; 2755 case sdma_event_e90_sw_halted: 2756 break; 2757 } 2758 break; 2759 2760 case sdma_state_s40_hw_clean_up_wait: 2761 switch (event) { 2762 case sdma_event_e00_go_hw_down: 2763 sdma_set_state(sde, sdma_state_s00_hw_down); 2764 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2765 break; 2766 case sdma_event_e10_go_hw_start: 2767 break; 2768 case sdma_event_e15_hw_halt_done: 2769 break; 2770 case sdma_event_e25_hw_clean_up_done: 2771 sdma_hw_start_up(sde); 2772 sdma_set_state(sde, ss->go_s99_running ? 2773 sdma_state_s99_running : 2774 sdma_state_s20_idle); 2775 break; 2776 case sdma_event_e30_go_running: 2777 ss->go_s99_running = 1; 2778 break; 2779 case sdma_event_e40_sw_cleaned: 2780 break; 2781 case sdma_event_e50_hw_cleaned: 2782 break; 2783 case sdma_event_e60_hw_halted: 2784 break; 2785 case sdma_event_e70_go_idle: 2786 ss->go_s99_running = 0; 2787 break; 2788 case sdma_event_e80_hw_freeze: 2789 break; 2790 case sdma_event_e81_hw_frozen: 2791 break; 2792 case sdma_event_e82_hw_unfreeze: 2793 break; 2794 case sdma_event_e85_link_down: 2795 ss->go_s99_running = 0; 2796 break; 2797 case sdma_event_e90_sw_halted: 2798 break; 2799 } 2800 break; 2801 2802 case sdma_state_s50_hw_halt_wait: 2803 switch (event) { 2804 case sdma_event_e00_go_hw_down: 2805 sdma_set_state(sde, sdma_state_s00_hw_down); 2806 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2807 break; 2808 case sdma_event_e10_go_hw_start: 2809 break; 2810 case sdma_event_e15_hw_halt_done: 2811 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); 2812 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2813 break; 2814 case sdma_event_e25_hw_clean_up_done: 2815 break; 2816 case sdma_event_e30_go_running: 2817 ss->go_s99_running = 1; 2818 break; 2819 case sdma_event_e40_sw_cleaned: 2820 break; 2821 case sdma_event_e50_hw_cleaned: 2822 break; 2823 case sdma_event_e60_hw_halted: 2824 schedule_work(&sde->err_halt_worker); 2825 break; 2826 case sdma_event_e70_go_idle: 2827 ss->go_s99_running = 0; 2828 break; 2829 case sdma_event_e80_hw_freeze: 2830 break; 2831 case sdma_event_e81_hw_frozen: 2832 break; 2833 case sdma_event_e82_hw_unfreeze: 2834 break; 2835 case sdma_event_e85_link_down: 2836 ss->go_s99_running = 0; 2837 break; 2838 case sdma_event_e90_sw_halted: 2839 break; 2840 } 2841 break; 2842 2843 case sdma_state_s60_idle_halt_wait: 2844 switch (event) { 2845 case sdma_event_e00_go_hw_down: 2846 sdma_set_state(sde, sdma_state_s00_hw_down); 2847 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2848 break; 2849 case sdma_event_e10_go_hw_start: 2850 break; 2851 case sdma_event_e15_hw_halt_done: 2852 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); 2853 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2854 break; 2855 case sdma_event_e25_hw_clean_up_done: 2856 break; 2857 case sdma_event_e30_go_running: 2858 ss->go_s99_running = 1; 2859 break; 2860 case sdma_event_e40_sw_cleaned: 2861 break; 2862 case sdma_event_e50_hw_cleaned: 2863 break; 2864 case sdma_event_e60_hw_halted: 2865 schedule_work(&sde->err_halt_worker); 2866 break; 2867 case sdma_event_e70_go_idle: 2868 ss->go_s99_running = 0; 2869 break; 2870 case sdma_event_e80_hw_freeze: 2871 break; 2872 case sdma_event_e81_hw_frozen: 2873 break; 2874 case sdma_event_e82_hw_unfreeze: 2875 break; 2876 case sdma_event_e85_link_down: 2877 break; 2878 case sdma_event_e90_sw_halted: 2879 break; 2880 } 2881 break; 2882 2883 case sdma_state_s80_hw_freeze: 2884 switch (event) { 2885 case sdma_event_e00_go_hw_down: 2886 sdma_set_state(sde, sdma_state_s00_hw_down); 2887 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2888 break; 2889 case sdma_event_e10_go_hw_start: 2890 break; 2891 case sdma_event_e15_hw_halt_done: 2892 break; 2893 case sdma_event_e25_hw_clean_up_done: 2894 break; 2895 case sdma_event_e30_go_running: 2896 ss->go_s99_running = 1; 2897 break; 2898 case sdma_event_e40_sw_cleaned: 2899 break; 2900 case sdma_event_e50_hw_cleaned: 2901 break; 2902 case sdma_event_e60_hw_halted: 2903 break; 2904 case sdma_event_e70_go_idle: 2905 ss->go_s99_running = 0; 2906 break; 2907 case sdma_event_e80_hw_freeze: 2908 break; 2909 case sdma_event_e81_hw_frozen: 2910 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean); 2911 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2912 break; 2913 case sdma_event_e82_hw_unfreeze: 2914 break; 2915 case sdma_event_e85_link_down: 2916 break; 2917 case sdma_event_e90_sw_halted: 2918 break; 2919 } 2920 break; 2921 2922 case sdma_state_s82_freeze_sw_clean: 2923 switch (event) { 2924 case sdma_event_e00_go_hw_down: 2925 sdma_set_state(sde, sdma_state_s00_hw_down); 2926 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2927 break; 2928 case sdma_event_e10_go_hw_start: 2929 break; 2930 case sdma_event_e15_hw_halt_done: 2931 break; 2932 case sdma_event_e25_hw_clean_up_done: 2933 break; 2934 case sdma_event_e30_go_running: 2935 ss->go_s99_running = 1; 2936 break; 2937 case sdma_event_e40_sw_cleaned: 2938 /* notify caller this engine is done cleaning */ 2939 atomic_dec(&sde->dd->sdma_unfreeze_count); 2940 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 2941 break; 2942 case sdma_event_e50_hw_cleaned: 2943 break; 2944 case sdma_event_e60_hw_halted: 2945 break; 2946 case sdma_event_e70_go_idle: 2947 ss->go_s99_running = 0; 2948 break; 2949 case sdma_event_e80_hw_freeze: 2950 break; 2951 case sdma_event_e81_hw_frozen: 2952 break; 2953 case sdma_event_e82_hw_unfreeze: 2954 sdma_hw_start_up(sde); 2955 sdma_set_state(sde, ss->go_s99_running ? 2956 sdma_state_s99_running : 2957 sdma_state_s20_idle); 2958 break; 2959 case sdma_event_e85_link_down: 2960 break; 2961 case sdma_event_e90_sw_halted: 2962 break; 2963 } 2964 break; 2965 2966 case sdma_state_s99_running: 2967 switch (event) { 2968 case sdma_event_e00_go_hw_down: 2969 sdma_set_state(sde, sdma_state_s00_hw_down); 2970 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2971 break; 2972 case sdma_event_e10_go_hw_start: 2973 break; 2974 case sdma_event_e15_hw_halt_done: 2975 break; 2976 case sdma_event_e25_hw_clean_up_done: 2977 break; 2978 case sdma_event_e30_go_running: 2979 break; 2980 case sdma_event_e40_sw_cleaned: 2981 break; 2982 case sdma_event_e50_hw_cleaned: 2983 break; 2984 case sdma_event_e60_hw_halted: 2985 need_progress = 1; 2986 sdma_err_progress_check_schedule(sde); 2987 /* fall through */ 2988 case sdma_event_e90_sw_halted: 2989 /* 2990 * SW initiated halt does not perform engines 2991 * progress check 2992 */ 2993 sdma_set_state(sde, sdma_state_s50_hw_halt_wait); 2994 schedule_work(&sde->err_halt_worker); 2995 break; 2996 case sdma_event_e70_go_idle: 2997 sdma_set_state(sde, sdma_state_s60_idle_halt_wait); 2998 break; 2999 case sdma_event_e85_link_down: 3000 ss->go_s99_running = 0; 3001 /* fall through */ 3002 case sdma_event_e80_hw_freeze: 3003 sdma_set_state(sde, sdma_state_s80_hw_freeze); 3004 atomic_dec(&sde->dd->sdma_unfreeze_count); 3005 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 3006 break; 3007 case sdma_event_e81_hw_frozen: 3008 break; 3009 case sdma_event_e82_hw_unfreeze: 3010 break; 3011 } 3012 break; 3013 } 3014 3015 ss->last_event = event; 3016 if (need_progress) 3017 sdma_make_progress(sde, 0); 3018 } 3019 3020 /* 3021 * _extend_sdma_tx_descs() - helper to extend txreq 3022 * 3023 * This is called once the initial nominal allocation 3024 * of descriptors in the sdma_txreq is exhausted. 3025 * 3026 * The code will bump the allocation up to the max 3027 * of MAX_DESC (64) descriptors. There doesn't seem 3028 * much point in an interim step. The last descriptor 3029 * is reserved for coalesce buffer in order to support 3030 * cases where input packet has >MAX_DESC iovecs. 3031 * 3032 */ 3033 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) 3034 { 3035 int i; 3036 3037 /* Handle last descriptor */ 3038 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) { 3039 /* if tlen is 0, it is for padding, release last descriptor */ 3040 if (!tx->tlen) { 3041 tx->desc_limit = MAX_DESC; 3042 } else if (!tx->coalesce_buf) { 3043 /* allocate coalesce buffer with space for padding */ 3044 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32), 3045 GFP_ATOMIC); 3046 if (!tx->coalesce_buf) 3047 goto enomem; 3048 tx->coalesce_idx = 0; 3049 } 3050 return 0; 3051 } 3052 3053 if (unlikely(tx->num_desc == MAX_DESC)) 3054 goto enomem; 3055 3056 tx->descp = kmalloc_array( 3057 MAX_DESC, 3058 sizeof(struct sdma_desc), 3059 GFP_ATOMIC); 3060 if (!tx->descp) 3061 goto enomem; 3062 3063 /* reserve last descriptor for coalescing */ 3064 tx->desc_limit = MAX_DESC - 1; 3065 /* copy ones already built */ 3066 for (i = 0; i < tx->num_desc; i++) 3067 tx->descp[i] = tx->descs[i]; 3068 return 0; 3069 enomem: 3070 __sdma_txclean(dd, tx); 3071 return -ENOMEM; 3072 } 3073 3074 /* 3075 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors 3076 * 3077 * This is called once the initial nominal allocation of descriptors 3078 * in the sdma_txreq is exhausted. 3079 * 3080 * This function calls _extend_sdma_tx_descs to extend or allocate 3081 * coalesce buffer. If there is a allocated coalesce buffer, it will 3082 * copy the input packet data into the coalesce buffer. It also adds 3083 * coalesce buffer descriptor once when whole packet is received. 3084 * 3085 * Return: 3086 * <0 - error 3087 * 0 - coalescing, don't populate descriptor 3088 * 1 - continue with populating descriptor 3089 */ 3090 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx, 3091 int type, void *kvaddr, struct page *page, 3092 unsigned long offset, u16 len) 3093 { 3094 int pad_len, rval; 3095 dma_addr_t addr; 3096 3097 rval = _extend_sdma_tx_descs(dd, tx); 3098 if (rval) { 3099 __sdma_txclean(dd, tx); 3100 return rval; 3101 } 3102 3103 /* If coalesce buffer is allocated, copy data into it */ 3104 if (tx->coalesce_buf) { 3105 if (type == SDMA_MAP_NONE) { 3106 __sdma_txclean(dd, tx); 3107 return -EINVAL; 3108 } 3109 3110 if (type == SDMA_MAP_PAGE) { 3111 kvaddr = kmap(page); 3112 kvaddr += offset; 3113 } else if (WARN_ON(!kvaddr)) { 3114 __sdma_txclean(dd, tx); 3115 return -EINVAL; 3116 } 3117 3118 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len); 3119 tx->coalesce_idx += len; 3120 if (type == SDMA_MAP_PAGE) 3121 kunmap(page); 3122 3123 /* If there is more data, return */ 3124 if (tx->tlen - tx->coalesce_idx) 3125 return 0; 3126 3127 /* Whole packet is received; add any padding */ 3128 pad_len = tx->packet_len & (sizeof(u32) - 1); 3129 if (pad_len) { 3130 pad_len = sizeof(u32) - pad_len; 3131 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len); 3132 /* padding is taken care of for coalescing case */ 3133 tx->packet_len += pad_len; 3134 tx->tlen += pad_len; 3135 } 3136 3137 /* dma map the coalesce buffer */ 3138 addr = dma_map_single(&dd->pcidev->dev, 3139 tx->coalesce_buf, 3140 tx->tlen, 3141 DMA_TO_DEVICE); 3142 3143 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 3144 __sdma_txclean(dd, tx); 3145 return -ENOSPC; 3146 } 3147 3148 /* Add descriptor for coalesce buffer */ 3149 tx->desc_limit = MAX_DESC; 3150 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx, 3151 addr, tx->tlen); 3152 } 3153 3154 return 1; 3155 } 3156 3157 /* Update sdes when the lmc changes */ 3158 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid) 3159 { 3160 struct sdma_engine *sde; 3161 int i; 3162 u64 sreg; 3163 3164 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) << 3165 SD(CHECK_SLID_MASK_SHIFT)) | 3166 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) << 3167 SD(CHECK_SLID_VALUE_SHIFT)); 3168 3169 for (i = 0; i < dd->num_sdma; i++) { 3170 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x", 3171 i, (u32)sreg); 3172 sde = &dd->per_sdma[i]; 3173 write_sde_csr(sde, SD(CHECK_SLID), sreg); 3174 } 3175 } 3176 3177 /* tx not dword sized - pad */ 3178 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) 3179 { 3180 int rval = 0; 3181 3182 tx->num_desc++; 3183 if ((unlikely(tx->num_desc == tx->desc_limit))) { 3184 rval = _extend_sdma_tx_descs(dd, tx); 3185 if (rval) { 3186 __sdma_txclean(dd, tx); 3187 return rval; 3188 } 3189 } 3190 /* finish the one just added */ 3191 make_tx_sdma_desc( 3192 tx, 3193 SDMA_MAP_NONE, 3194 dd->sdma_pad_phys, 3195 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1))); 3196 _sdma_close_tx(dd, tx); 3197 return rval; 3198 } 3199 3200 /* 3201 * Add ahg to the sdma_txreq 3202 * 3203 * The logic will consume up to 3 3204 * descriptors at the beginning of 3205 * sdma_txreq. 3206 */ 3207 void _sdma_txreq_ahgadd( 3208 struct sdma_txreq *tx, 3209 u8 num_ahg, 3210 u8 ahg_entry, 3211 u32 *ahg, 3212 u8 ahg_hlen) 3213 { 3214 u32 i, shift = 0, desc = 0; 3215 u8 mode; 3216 3217 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4); 3218 /* compute mode */ 3219 if (num_ahg == 1) 3220 mode = SDMA_AHG_APPLY_UPDATE1; 3221 else if (num_ahg <= 5) 3222 mode = SDMA_AHG_APPLY_UPDATE2; 3223 else 3224 mode = SDMA_AHG_APPLY_UPDATE3; 3225 tx->num_desc++; 3226 /* initialize to consumed descriptors to zero */ 3227 switch (mode) { 3228 case SDMA_AHG_APPLY_UPDATE3: 3229 tx->num_desc++; 3230 tx->descs[2].qw[0] = 0; 3231 tx->descs[2].qw[1] = 0; 3232 /* FALLTHROUGH */ 3233 case SDMA_AHG_APPLY_UPDATE2: 3234 tx->num_desc++; 3235 tx->descs[1].qw[0] = 0; 3236 tx->descs[1].qw[1] = 0; 3237 break; 3238 } 3239 ahg_hlen >>= 2; 3240 tx->descs[0].qw[1] |= 3241 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK) 3242 << SDMA_DESC1_HEADER_INDEX_SHIFT) | 3243 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK) 3244 << SDMA_DESC1_HEADER_DWS_SHIFT) | 3245 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK) 3246 << SDMA_DESC1_HEADER_MODE_SHIFT) | 3247 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK) 3248 << SDMA_DESC1_HEADER_UPDATE1_SHIFT); 3249 for (i = 0; i < (num_ahg - 1); i++) { 3250 if (!shift && !(i & 2)) 3251 desc++; 3252 tx->descs[desc].qw[!!(i & 2)] |= 3253 (((u64)ahg[i + 1]) 3254 << shift); 3255 shift = (shift + 32) & 63; 3256 } 3257 } 3258 3259 /** 3260 * sdma_ahg_alloc - allocate an AHG entry 3261 * @sde: engine to allocate from 3262 * 3263 * Return: 3264 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled, 3265 * -ENOSPC if an entry is not available 3266 */ 3267 int sdma_ahg_alloc(struct sdma_engine *sde) 3268 { 3269 int nr; 3270 int oldbit; 3271 3272 if (!sde) { 3273 trace_hfi1_ahg_allocate(sde, -EINVAL); 3274 return -EINVAL; 3275 } 3276 while (1) { 3277 nr = ffz(READ_ONCE(sde->ahg_bits)); 3278 if (nr > 31) { 3279 trace_hfi1_ahg_allocate(sde, -ENOSPC); 3280 return -ENOSPC; 3281 } 3282 oldbit = test_and_set_bit(nr, &sde->ahg_bits); 3283 if (!oldbit) 3284 break; 3285 cpu_relax(); 3286 } 3287 trace_hfi1_ahg_allocate(sde, nr); 3288 return nr; 3289 } 3290 3291 /** 3292 * sdma_ahg_free - free an AHG entry 3293 * @sde: engine to return AHG entry 3294 * @ahg_index: index to free 3295 * 3296 * This routine frees the indicate AHG entry. 3297 */ 3298 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index) 3299 { 3300 if (!sde) 3301 return; 3302 trace_hfi1_ahg_deallocate(sde, ahg_index); 3303 if (ahg_index < 0 || ahg_index > 31) 3304 return; 3305 clear_bit(ahg_index, &sde->ahg_bits); 3306 } 3307 3308 /* 3309 * SPC freeze handling for SDMA engines. Called when the driver knows 3310 * the SPC is going into a freeze but before the freeze is fully 3311 * settled. Generally an error interrupt. 3312 * 3313 * This event will pull the engine out of running so no more entries can be 3314 * added to the engine's queue. 3315 */ 3316 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down) 3317 { 3318 int i; 3319 enum sdma_events event = link_down ? sdma_event_e85_link_down : 3320 sdma_event_e80_hw_freeze; 3321 3322 /* set up the wait but do not wait here */ 3323 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); 3324 3325 /* tell all engines to stop running and wait */ 3326 for (i = 0; i < dd->num_sdma; i++) 3327 sdma_process_event(&dd->per_sdma[i], event); 3328 3329 /* sdma_freeze() will wait for all engines to have stopped */ 3330 } 3331 3332 /* 3333 * SPC freeze handling for SDMA engines. Called when the driver knows 3334 * the SPC is fully frozen. 3335 */ 3336 void sdma_freeze(struct hfi1_devdata *dd) 3337 { 3338 int i; 3339 int ret; 3340 3341 /* 3342 * Make sure all engines have moved out of the running state before 3343 * continuing. 3344 */ 3345 ret = wait_event_interruptible(dd->sdma_unfreeze_wq, 3346 atomic_read(&dd->sdma_unfreeze_count) <= 3347 0); 3348 /* interrupted or count is negative, then unloading - just exit */ 3349 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0) 3350 return; 3351 3352 /* set up the count for the next wait */ 3353 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); 3354 3355 /* tell all engines that the SPC is frozen, they can start cleaning */ 3356 for (i = 0; i < dd->num_sdma; i++) 3357 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen); 3358 3359 /* 3360 * Wait for everyone to finish software clean before exiting. The 3361 * software clean will read engine CSRs, so must be completed before 3362 * the next step, which will clear the engine CSRs. 3363 */ 3364 (void)wait_event_interruptible(dd->sdma_unfreeze_wq, 3365 atomic_read(&dd->sdma_unfreeze_count) <= 0); 3366 /* no need to check results - done no matter what */ 3367 } 3368 3369 /* 3370 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen. 3371 * 3372 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All 3373 * that is left is a software clean. We could do it after the SPC is fully 3374 * frozen, but then we'd have to add another state to wait for the unfreeze. 3375 * Instead, just defer the software clean until the unfreeze step. 3376 */ 3377 void sdma_unfreeze(struct hfi1_devdata *dd) 3378 { 3379 int i; 3380 3381 /* tell all engines start freeze clean up */ 3382 for (i = 0; i < dd->num_sdma; i++) 3383 sdma_process_event(&dd->per_sdma[i], 3384 sdma_event_e82_hw_unfreeze); 3385 } 3386 3387 /** 3388 * _sdma_engine_progress_schedule() - schedule progress on engine 3389 * @sde: sdma_engine to schedule progress 3390 * 3391 */ 3392 void _sdma_engine_progress_schedule( 3393 struct sdma_engine *sde) 3394 { 3395 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask); 3396 /* assume we have selected a good cpu */ 3397 write_csr(sde->dd, 3398 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)), 3399 sde->progress_mask); 3400 } 3401