1 /* 2 * Copyright(c) 2015 - 2018 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/err.h> 49 #include <linux/vmalloc.h> 50 #include <linux/hash.h> 51 #include <linux/module.h> 52 #include <linux/seq_file.h> 53 #include <rdma/rdma_vt.h> 54 #include <rdma/rdmavt_qp.h> 55 #include <rdma/ib_verbs.h> 56 57 #include "hfi.h" 58 #include "qp.h" 59 #include "trace.h" 60 #include "verbs_txreq.h" 61 62 unsigned int hfi1_qp_table_size = 256; 63 module_param_named(qp_table_size, hfi1_qp_table_size, uint, S_IRUGO); 64 MODULE_PARM_DESC(qp_table_size, "QP table size"); 65 66 static void flush_tx_list(struct rvt_qp *qp); 67 static int iowait_sleep( 68 struct sdma_engine *sde, 69 struct iowait_work *wait, 70 struct sdma_txreq *stx, 71 unsigned int seq, 72 bool pkts_sent); 73 static void iowait_wakeup(struct iowait *wait, int reason); 74 static void iowait_sdma_drained(struct iowait *wait); 75 static void qp_pio_drain(struct rvt_qp *qp); 76 77 const struct rvt_operation_params hfi1_post_parms[RVT_OPERATION_MAX] = { 78 [IB_WR_RDMA_WRITE] = { 79 .length = sizeof(struct ib_rdma_wr), 80 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), 81 }, 82 83 [IB_WR_RDMA_READ] = { 84 .length = sizeof(struct ib_rdma_wr), 85 .qpt_support = BIT(IB_QPT_RC), 86 .flags = RVT_OPERATION_ATOMIC, 87 }, 88 89 [IB_WR_ATOMIC_CMP_AND_SWP] = { 90 .length = sizeof(struct ib_atomic_wr), 91 .qpt_support = BIT(IB_QPT_RC), 92 .flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE, 93 }, 94 95 [IB_WR_ATOMIC_FETCH_AND_ADD] = { 96 .length = sizeof(struct ib_atomic_wr), 97 .qpt_support = BIT(IB_QPT_RC), 98 .flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE, 99 }, 100 101 [IB_WR_RDMA_WRITE_WITH_IMM] = { 102 .length = sizeof(struct ib_rdma_wr), 103 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), 104 }, 105 106 [IB_WR_SEND] = { 107 .length = sizeof(struct ib_send_wr), 108 .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | 109 BIT(IB_QPT_UC) | BIT(IB_QPT_RC), 110 }, 111 112 [IB_WR_SEND_WITH_IMM] = { 113 .length = sizeof(struct ib_send_wr), 114 .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | 115 BIT(IB_QPT_UC) | BIT(IB_QPT_RC), 116 }, 117 118 [IB_WR_REG_MR] = { 119 .length = sizeof(struct ib_reg_wr), 120 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), 121 .flags = RVT_OPERATION_LOCAL, 122 }, 123 124 [IB_WR_LOCAL_INV] = { 125 .length = sizeof(struct ib_send_wr), 126 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), 127 .flags = RVT_OPERATION_LOCAL, 128 }, 129 130 [IB_WR_SEND_WITH_INV] = { 131 .length = sizeof(struct ib_send_wr), 132 .qpt_support = BIT(IB_QPT_RC), 133 }, 134 135 }; 136 137 static void flush_list_head(struct list_head *l) 138 { 139 while (!list_empty(l)) { 140 struct sdma_txreq *tx; 141 142 tx = list_first_entry( 143 l, 144 struct sdma_txreq, 145 list); 146 list_del_init(&tx->list); 147 hfi1_put_txreq( 148 container_of(tx, struct verbs_txreq, txreq)); 149 } 150 } 151 152 static void flush_tx_list(struct rvt_qp *qp) 153 { 154 struct hfi1_qp_priv *priv = qp->priv; 155 156 flush_list_head(&iowait_get_ib_work(&priv->s_iowait)->tx_head); 157 flush_list_head(&iowait_get_tid_work(&priv->s_iowait)->tx_head); 158 } 159 160 static void flush_iowait(struct rvt_qp *qp) 161 { 162 struct hfi1_qp_priv *priv = qp->priv; 163 unsigned long flags; 164 seqlock_t *lock = priv->s_iowait.lock; 165 166 if (!lock) 167 return; 168 write_seqlock_irqsave(lock, flags); 169 if (!list_empty(&priv->s_iowait.list)) { 170 list_del_init(&priv->s_iowait.list); 171 priv->s_iowait.lock = NULL; 172 rvt_put_qp(qp); 173 } 174 write_sequnlock_irqrestore(lock, flags); 175 } 176 177 static inline int opa_mtu_enum_to_int(int mtu) 178 { 179 switch (mtu) { 180 case OPA_MTU_8192: return 8192; 181 case OPA_MTU_10240: return 10240; 182 default: return -1; 183 } 184 } 185 186 /** 187 * This function is what we would push to the core layer if we wanted to be a 188 * "first class citizen". Instead we hide this here and rely on Verbs ULPs 189 * to blindly pass the MTU enum value from the PathRecord to us. 190 */ 191 static inline int verbs_mtu_enum_to_int(struct ib_device *dev, enum ib_mtu mtu) 192 { 193 int val; 194 195 /* Constraining 10KB packets to 8KB packets */ 196 if (mtu == (enum ib_mtu)OPA_MTU_10240) 197 mtu = OPA_MTU_8192; 198 val = opa_mtu_enum_to_int((int)mtu); 199 if (val > 0) 200 return val; 201 return ib_mtu_enum_to_int(mtu); 202 } 203 204 int hfi1_check_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr, 205 int attr_mask, struct ib_udata *udata) 206 { 207 struct ib_qp *ibqp = &qp->ibqp; 208 struct hfi1_ibdev *dev = to_idev(ibqp->device); 209 struct hfi1_devdata *dd = dd_from_dev(dev); 210 u8 sc; 211 212 if (attr_mask & IB_QP_AV) { 213 sc = ah_to_sc(ibqp->device, &attr->ah_attr); 214 if (sc == 0xf) 215 return -EINVAL; 216 217 if (!qp_to_sdma_engine(qp, sc) && 218 dd->flags & HFI1_HAS_SEND_DMA) 219 return -EINVAL; 220 221 if (!qp_to_send_context(qp, sc)) 222 return -EINVAL; 223 } 224 225 if (attr_mask & IB_QP_ALT_PATH) { 226 sc = ah_to_sc(ibqp->device, &attr->alt_ah_attr); 227 if (sc == 0xf) 228 return -EINVAL; 229 230 if (!qp_to_sdma_engine(qp, sc) && 231 dd->flags & HFI1_HAS_SEND_DMA) 232 return -EINVAL; 233 234 if (!qp_to_send_context(qp, sc)) 235 return -EINVAL; 236 } 237 238 return 0; 239 } 240 241 /* 242 * qp_set_16b - Set the hdr_type based on whether the slid or the 243 * dlid in the connection is extended. Only applicable for RC and UC 244 * QPs. UD QPs determine this on the fly from the ah in the wqe 245 */ 246 static inline void qp_set_16b(struct rvt_qp *qp) 247 { 248 struct hfi1_pportdata *ppd; 249 struct hfi1_ibport *ibp; 250 struct hfi1_qp_priv *priv = qp->priv; 251 252 /* Update ah_attr to account for extended LIDs */ 253 hfi1_update_ah_attr(qp->ibqp.device, &qp->remote_ah_attr); 254 255 /* Create 32 bit LIDs */ 256 hfi1_make_opa_lid(&qp->remote_ah_attr); 257 258 if (!(rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)) 259 return; 260 261 ibp = to_iport(qp->ibqp.device, qp->port_num); 262 ppd = ppd_from_ibp(ibp); 263 priv->hdr_type = hfi1_get_hdr_type(ppd->lid, &qp->remote_ah_attr); 264 } 265 266 void hfi1_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr, 267 int attr_mask, struct ib_udata *udata) 268 { 269 struct ib_qp *ibqp = &qp->ibqp; 270 struct hfi1_qp_priv *priv = qp->priv; 271 272 if (attr_mask & IB_QP_AV) { 273 priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr); 274 priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc); 275 priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc); 276 qp_set_16b(qp); 277 } 278 279 if (attr_mask & IB_QP_PATH_MIG_STATE && 280 attr->path_mig_state == IB_MIG_MIGRATED && 281 qp->s_mig_state == IB_MIG_ARMED) { 282 qp->s_flags |= HFI1_S_AHG_CLEAR; 283 priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr); 284 priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc); 285 priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc); 286 qp_set_16b(qp); 287 } 288 } 289 290 /** 291 * hfi1_setup_wqe - set up the wqe 292 * @qp - The qp 293 * @wqe - The built wqe 294 * @call_send - Determine if the send should be posted or scheduled. 295 * 296 * Perform setup of the wqe. This is called 297 * prior to inserting the wqe into the ring but after 298 * the wqe has been setup by RDMAVT. This function 299 * allows the driver the opportunity to perform 300 * validation and additional setup of the wqe. 301 * 302 * Returns 0 on success, -EINVAL on failure 303 * 304 */ 305 int hfi1_setup_wqe(struct rvt_qp *qp, struct rvt_swqe *wqe, bool *call_send) 306 { 307 struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num); 308 struct rvt_ah *ah; 309 struct hfi1_pportdata *ppd; 310 struct hfi1_devdata *dd; 311 312 switch (qp->ibqp.qp_type) { 313 case IB_QPT_RC: 314 case IB_QPT_UC: 315 if (wqe->length > 0x80000000U) 316 return -EINVAL; 317 if (wqe->length > qp->pmtu) 318 *call_send = false; 319 break; 320 case IB_QPT_SMI: 321 /* 322 * SM packets should exclusively use VL15 and their SL is 323 * ignored (IBTA v1.3, Section 3.5.8.2). Therefore, when ah 324 * is created, SL is 0 in most cases and as a result some 325 * fields (vl and pmtu) in ah may not be set correctly, 326 * depending on the SL2SC and SC2VL tables at the time. 327 */ 328 ppd = ppd_from_ibp(ibp); 329 dd = dd_from_ppd(ppd); 330 if (wqe->length > dd->vld[15].mtu) 331 return -EINVAL; 332 break; 333 case IB_QPT_GSI: 334 case IB_QPT_UD: 335 ah = ibah_to_rvtah(wqe->ud_wr.ah); 336 if (wqe->length > (1 << ah->log_pmtu)) 337 return -EINVAL; 338 if (ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)] == 0xf) 339 return -EINVAL; 340 default: 341 break; 342 } 343 return 0; 344 } 345 346 /** 347 * _hfi1_schedule_send - schedule progress 348 * @qp: the QP 349 * 350 * This schedules qp progress w/o regard to the s_flags. 351 * 352 * It is only used in the post send, which doesn't hold 353 * the s_lock. 354 */ 355 bool _hfi1_schedule_send(struct rvt_qp *qp) 356 { 357 struct hfi1_qp_priv *priv = qp->priv; 358 struct hfi1_ibport *ibp = 359 to_iport(qp->ibqp.device, qp->port_num); 360 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 361 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 362 363 return iowait_schedule(&priv->s_iowait, ppd->hfi1_wq, 364 priv->s_sde ? 365 priv->s_sde->cpu : 366 cpumask_first(cpumask_of_node(dd->node))); 367 } 368 369 static void qp_pio_drain(struct rvt_qp *qp) 370 { 371 struct hfi1_ibdev *dev; 372 struct hfi1_qp_priv *priv = qp->priv; 373 374 if (!priv->s_sendcontext) 375 return; 376 dev = to_idev(qp->ibqp.device); 377 while (iowait_pio_pending(&priv->s_iowait)) { 378 write_seqlock_irq(&dev->iowait_lock); 379 hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 1); 380 write_sequnlock_irq(&dev->iowait_lock); 381 iowait_pio_drain(&priv->s_iowait); 382 write_seqlock_irq(&dev->iowait_lock); 383 hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 0); 384 write_sequnlock_irq(&dev->iowait_lock); 385 } 386 } 387 388 /** 389 * hfi1_schedule_send - schedule progress 390 * @qp: the QP 391 * 392 * This schedules qp progress and caller should hold 393 * the s_lock. 394 * @return true if the first leg is scheduled; 395 * false if the first leg is not scheduled. 396 */ 397 bool hfi1_schedule_send(struct rvt_qp *qp) 398 { 399 lockdep_assert_held(&qp->s_lock); 400 if (hfi1_send_ok(qp)) { 401 _hfi1_schedule_send(qp); 402 return true; 403 } 404 if (qp->s_flags & HFI1_S_ANY_WAIT_IO) 405 iowait_set_flag(&((struct hfi1_qp_priv *)qp->priv)->s_iowait, 406 IOWAIT_PENDING_IB); 407 return false; 408 } 409 410 static void hfi1_qp_schedule(struct rvt_qp *qp) 411 { 412 struct hfi1_qp_priv *priv = qp->priv; 413 bool ret; 414 415 if (iowait_flag_set(&priv->s_iowait, IOWAIT_PENDING_IB)) { 416 ret = hfi1_schedule_send(qp); 417 if (ret) 418 iowait_clear_flag(&priv->s_iowait, IOWAIT_PENDING_IB); 419 } 420 } 421 422 void hfi1_qp_wakeup(struct rvt_qp *qp, u32 flag) 423 { 424 unsigned long flags; 425 426 spin_lock_irqsave(&qp->s_lock, flags); 427 if (qp->s_flags & flag) { 428 qp->s_flags &= ~flag; 429 trace_hfi1_qpwakeup(qp, flag); 430 hfi1_qp_schedule(qp); 431 } 432 spin_unlock_irqrestore(&qp->s_lock, flags); 433 /* Notify hfi1_destroy_qp() if it is waiting. */ 434 rvt_put_qp(qp); 435 } 436 437 void hfi1_qp_unbusy(struct rvt_qp *qp, struct iowait_work *wait) 438 { 439 if (iowait_set_work_flag(wait) == IOWAIT_IB_SE) 440 qp->s_flags &= ~RVT_S_BUSY; 441 } 442 443 static int iowait_sleep( 444 struct sdma_engine *sde, 445 struct iowait_work *wait, 446 struct sdma_txreq *stx, 447 uint seq, 448 bool pkts_sent) 449 { 450 struct verbs_txreq *tx = container_of(stx, struct verbs_txreq, txreq); 451 struct rvt_qp *qp; 452 struct hfi1_qp_priv *priv; 453 unsigned long flags; 454 int ret = 0; 455 struct hfi1_ibdev *dev; 456 457 qp = tx->qp; 458 priv = qp->priv; 459 460 spin_lock_irqsave(&qp->s_lock, flags); 461 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { 462 /* 463 * If we couldn't queue the DMA request, save the info 464 * and try again later rather than destroying the 465 * buffer and undoing the side effects of the copy. 466 */ 467 /* Make a common routine? */ 468 dev = &sde->dd->verbs_dev; 469 list_add_tail(&stx->list, &wait->tx_head); 470 write_seqlock(&dev->iowait_lock); 471 if (sdma_progress(sde, seq, stx)) 472 goto eagain; 473 if (list_empty(&priv->s_iowait.list)) { 474 struct hfi1_ibport *ibp = 475 to_iport(qp->ibqp.device, qp->port_num); 476 477 ibp->rvp.n_dmawait++; 478 qp->s_flags |= RVT_S_WAIT_DMA_DESC; 479 iowait_queue(pkts_sent, &priv->s_iowait, 480 &sde->dmawait); 481 priv->s_iowait.lock = &dev->iowait_lock; 482 trace_hfi1_qpsleep(qp, RVT_S_WAIT_DMA_DESC); 483 rvt_get_qp(qp); 484 } 485 write_sequnlock(&dev->iowait_lock); 486 hfi1_qp_unbusy(qp, wait); 487 spin_unlock_irqrestore(&qp->s_lock, flags); 488 ret = -EBUSY; 489 } else { 490 spin_unlock_irqrestore(&qp->s_lock, flags); 491 hfi1_put_txreq(tx); 492 } 493 return ret; 494 eagain: 495 write_sequnlock(&dev->iowait_lock); 496 spin_unlock_irqrestore(&qp->s_lock, flags); 497 list_del_init(&stx->list); 498 return -EAGAIN; 499 } 500 501 static void iowait_wakeup(struct iowait *wait, int reason) 502 { 503 struct rvt_qp *qp = iowait_to_qp(wait); 504 505 WARN_ON(reason != SDMA_AVAIL_REASON); 506 hfi1_qp_wakeup(qp, RVT_S_WAIT_DMA_DESC); 507 } 508 509 static void iowait_sdma_drained(struct iowait *wait) 510 { 511 struct rvt_qp *qp = iowait_to_qp(wait); 512 unsigned long flags; 513 514 /* 515 * This happens when the send engine notes 516 * a QP in the error state and cannot 517 * do the flush work until that QP's 518 * sdma work has finished. 519 */ 520 spin_lock_irqsave(&qp->s_lock, flags); 521 if (qp->s_flags & RVT_S_WAIT_DMA) { 522 qp->s_flags &= ~RVT_S_WAIT_DMA; 523 hfi1_schedule_send(qp); 524 } 525 spin_unlock_irqrestore(&qp->s_lock, flags); 526 } 527 528 /** 529 * qp_to_sdma_engine - map a qp to a send engine 530 * @qp: the QP 531 * @sc5: the 5 bit sc 532 * 533 * Return: 534 * A send engine for the qp or NULL for SMI type qp. 535 */ 536 struct sdma_engine *qp_to_sdma_engine(struct rvt_qp *qp, u8 sc5) 537 { 538 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 539 struct sdma_engine *sde; 540 541 if (!(dd->flags & HFI1_HAS_SEND_DMA)) 542 return NULL; 543 switch (qp->ibqp.qp_type) { 544 case IB_QPT_SMI: 545 return NULL; 546 default: 547 break; 548 } 549 sde = sdma_select_engine_sc(dd, qp->ibqp.qp_num >> dd->qos_shift, sc5); 550 return sde; 551 } 552 553 /* 554 * qp_to_send_context - map a qp to a send context 555 * @qp: the QP 556 * @sc5: the 5 bit sc 557 * 558 * Return: 559 * A send context for the qp 560 */ 561 struct send_context *qp_to_send_context(struct rvt_qp *qp, u8 sc5) 562 { 563 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 564 565 switch (qp->ibqp.qp_type) { 566 case IB_QPT_SMI: 567 /* SMA packets to VL15 */ 568 return dd->vld[15].sc; 569 default: 570 break; 571 } 572 573 return pio_select_send_context_sc(dd, qp->ibqp.qp_num >> dd->qos_shift, 574 sc5); 575 } 576 577 static const char * const qp_type_str[] = { 578 "SMI", "GSI", "RC", "UC", "UD", 579 }; 580 581 static int qp_idle(struct rvt_qp *qp) 582 { 583 return 584 qp->s_last == qp->s_acked && 585 qp->s_acked == qp->s_cur && 586 qp->s_cur == qp->s_tail && 587 qp->s_tail == qp->s_head; 588 } 589 590 /** 591 * qp_iter_print - print the qp information to seq_file 592 * @s: the seq_file to emit the qp information on 593 * @iter: the iterator for the qp hash list 594 */ 595 void qp_iter_print(struct seq_file *s, struct rvt_qp_iter *iter) 596 { 597 struct rvt_swqe *wqe; 598 struct rvt_qp *qp = iter->qp; 599 struct hfi1_qp_priv *priv = qp->priv; 600 struct sdma_engine *sde; 601 struct send_context *send_context; 602 struct rvt_ack_entry *e = NULL; 603 struct rvt_srq *srq = qp->ibqp.srq ? 604 ibsrq_to_rvtsrq(qp->ibqp.srq) : NULL; 605 606 sde = qp_to_sdma_engine(qp, priv->s_sc); 607 wqe = rvt_get_swqe_ptr(qp, qp->s_last); 608 send_context = qp_to_send_context(qp, priv->s_sc); 609 if (qp->s_ack_queue) 610 e = &qp->s_ack_queue[qp->s_tail_ack_queue]; 611 seq_printf(s, 612 "N %d %s QP %x R %u %s %u %u f=%x %u %u %u %u %u %u SPSN %x %x %x %x %x RPSN %x S(%u %u %u %u %u %u %u) R(%u %u %u) RQP %x LID %x SL %u MTU %u %u %u %u %u SDE %p,%u SC %p,%u SCQ %u %u PID %d OS %x %x E %x %x %x RNR %d %s %d\n", 613 iter->n, 614 qp_idle(qp) ? "I" : "B", 615 qp->ibqp.qp_num, 616 atomic_read(&qp->refcount), 617 qp_type_str[qp->ibqp.qp_type], 618 qp->state, 619 wqe ? wqe->wr.opcode : 0, 620 qp->s_flags, 621 iowait_sdma_pending(&priv->s_iowait), 622 iowait_pio_pending(&priv->s_iowait), 623 !list_empty(&priv->s_iowait.list), 624 qp->timeout, 625 wqe ? wqe->ssn : 0, 626 qp->s_lsn, 627 qp->s_last_psn, 628 qp->s_psn, qp->s_next_psn, 629 qp->s_sending_psn, qp->s_sending_hpsn, 630 qp->r_psn, 631 qp->s_last, qp->s_acked, qp->s_cur, 632 qp->s_tail, qp->s_head, qp->s_size, 633 qp->s_avail, 634 /* ack_queue ring pointers, size */ 635 qp->s_tail_ack_queue, qp->r_head_ack_queue, 636 rvt_max_atomic(&to_idev(qp->ibqp.device)->rdi), 637 /* remote QP info */ 638 qp->remote_qpn, 639 rdma_ah_get_dlid(&qp->remote_ah_attr), 640 rdma_ah_get_sl(&qp->remote_ah_attr), 641 qp->pmtu, 642 qp->s_retry, 643 qp->s_retry_cnt, 644 qp->s_rnr_retry_cnt, 645 qp->s_rnr_retry, 646 sde, 647 sde ? sde->this_idx : 0, 648 send_context, 649 send_context ? send_context->sw_index : 0, 650 ibcq_to_rvtcq(qp->ibqp.send_cq)->queue->head, 651 ibcq_to_rvtcq(qp->ibqp.send_cq)->queue->tail, 652 qp->pid, 653 qp->s_state, 654 qp->s_ack_state, 655 /* ack queue information */ 656 e ? e->opcode : 0, 657 e ? e->psn : 0, 658 e ? e->lpsn : 0, 659 qp->r_min_rnr_timer, 660 srq ? "SRQ" : "RQ", 661 srq ? srq->rq.size : qp->r_rq.size 662 ); 663 } 664 665 void *qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp) 666 { 667 struct hfi1_qp_priv *priv; 668 669 priv = kzalloc_node(sizeof(*priv), GFP_KERNEL, rdi->dparms.node); 670 if (!priv) 671 return ERR_PTR(-ENOMEM); 672 673 priv->owner = qp; 674 675 priv->s_ahg = kzalloc_node(sizeof(*priv->s_ahg), GFP_KERNEL, 676 rdi->dparms.node); 677 if (!priv->s_ahg) { 678 kfree(priv); 679 return ERR_PTR(-ENOMEM); 680 } 681 iowait_init( 682 &priv->s_iowait, 683 1, 684 _hfi1_do_send, 685 NULL, 686 iowait_sleep, 687 iowait_wakeup, 688 iowait_sdma_drained); 689 return priv; 690 } 691 692 void qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp) 693 { 694 struct hfi1_qp_priv *priv = qp->priv; 695 696 kfree(priv->s_ahg); 697 kfree(priv); 698 } 699 700 unsigned free_all_qps(struct rvt_dev_info *rdi) 701 { 702 struct hfi1_ibdev *verbs_dev = container_of(rdi, 703 struct hfi1_ibdev, 704 rdi); 705 struct hfi1_devdata *dd = container_of(verbs_dev, 706 struct hfi1_devdata, 707 verbs_dev); 708 int n; 709 unsigned qp_inuse = 0; 710 711 for (n = 0; n < dd->num_pports; n++) { 712 struct hfi1_ibport *ibp = &dd->pport[n].ibport_data; 713 714 rcu_read_lock(); 715 if (rcu_dereference(ibp->rvp.qp[0])) 716 qp_inuse++; 717 if (rcu_dereference(ibp->rvp.qp[1])) 718 qp_inuse++; 719 rcu_read_unlock(); 720 } 721 722 return qp_inuse; 723 } 724 725 void flush_qp_waiters(struct rvt_qp *qp) 726 { 727 lockdep_assert_held(&qp->s_lock); 728 flush_iowait(qp); 729 } 730 731 void stop_send_queue(struct rvt_qp *qp) 732 { 733 struct hfi1_qp_priv *priv = qp->priv; 734 735 iowait_cancel_work(&priv->s_iowait); 736 } 737 738 void quiesce_qp(struct rvt_qp *qp) 739 { 740 struct hfi1_qp_priv *priv = qp->priv; 741 742 iowait_sdma_drain(&priv->s_iowait); 743 qp_pio_drain(qp); 744 flush_tx_list(qp); 745 } 746 747 void notify_qp_reset(struct rvt_qp *qp) 748 { 749 qp->r_adefered = 0; 750 clear_ahg(qp); 751 } 752 753 /* 754 * Switch to alternate path. 755 * The QP s_lock should be held and interrupts disabled. 756 */ 757 void hfi1_migrate_qp(struct rvt_qp *qp) 758 { 759 struct hfi1_qp_priv *priv = qp->priv; 760 struct ib_event ev; 761 762 qp->s_mig_state = IB_MIG_MIGRATED; 763 qp->remote_ah_attr = qp->alt_ah_attr; 764 qp->port_num = rdma_ah_get_port_num(&qp->alt_ah_attr); 765 qp->s_pkey_index = qp->s_alt_pkey_index; 766 qp->s_flags |= HFI1_S_AHG_CLEAR; 767 priv->s_sc = ah_to_sc(qp->ibqp.device, &qp->remote_ah_attr); 768 priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc); 769 qp_set_16b(qp); 770 771 ev.device = qp->ibqp.device; 772 ev.element.qp = &qp->ibqp; 773 ev.event = IB_EVENT_PATH_MIG; 774 qp->ibqp.event_handler(&ev, qp->ibqp.qp_context); 775 } 776 777 int mtu_to_path_mtu(u32 mtu) 778 { 779 return mtu_to_enum(mtu, OPA_MTU_8192); 780 } 781 782 u32 mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu) 783 { 784 u32 mtu; 785 struct hfi1_ibdev *verbs_dev = container_of(rdi, 786 struct hfi1_ibdev, 787 rdi); 788 struct hfi1_devdata *dd = container_of(verbs_dev, 789 struct hfi1_devdata, 790 verbs_dev); 791 struct hfi1_ibport *ibp; 792 u8 sc, vl; 793 794 ibp = &dd->pport[qp->port_num - 1].ibport_data; 795 sc = ibp->sl_to_sc[rdma_ah_get_sl(&qp->remote_ah_attr)]; 796 vl = sc_to_vlt(dd, sc); 797 798 mtu = verbs_mtu_enum_to_int(qp->ibqp.device, pmtu); 799 if (vl < PER_VL_SEND_CONTEXTS) 800 mtu = min_t(u32, mtu, dd->vld[vl].mtu); 801 return mtu; 802 } 803 804 int get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp, 805 struct ib_qp_attr *attr) 806 { 807 int mtu, pidx = qp->port_num - 1; 808 struct hfi1_ibdev *verbs_dev = container_of(rdi, 809 struct hfi1_ibdev, 810 rdi); 811 struct hfi1_devdata *dd = container_of(verbs_dev, 812 struct hfi1_devdata, 813 verbs_dev); 814 mtu = verbs_mtu_enum_to_int(qp->ibqp.device, attr->path_mtu); 815 if (mtu == -1) 816 return -1; /* values less than 0 are error */ 817 818 if (mtu > dd->pport[pidx].ibmtu) 819 return mtu_to_enum(dd->pport[pidx].ibmtu, IB_MTU_2048); 820 else 821 return attr->path_mtu; 822 } 823 824 void notify_error_qp(struct rvt_qp *qp) 825 { 826 struct hfi1_qp_priv *priv = qp->priv; 827 seqlock_t *lock = priv->s_iowait.lock; 828 829 if (lock) { 830 write_seqlock(lock); 831 if (!list_empty(&priv->s_iowait.list) && 832 !(qp->s_flags & RVT_S_BUSY)) { 833 qp->s_flags &= ~RVT_S_ANY_WAIT_IO; 834 list_del_init(&priv->s_iowait.list); 835 priv->s_iowait.lock = NULL; 836 rvt_put_qp(qp); 837 } 838 write_sequnlock(lock); 839 } 840 841 if (!(qp->s_flags & RVT_S_BUSY)) { 842 if (qp->s_rdma_mr) { 843 rvt_put_mr(qp->s_rdma_mr); 844 qp->s_rdma_mr = NULL; 845 } 846 flush_tx_list(qp); 847 } 848 } 849 850 /** 851 * hfi1_qp_iter_cb - callback for iterator 852 * @qp - the qp 853 * @v - the sl in low bits of v 854 * 855 * This is called from the iterator callback to work 856 * on an individual qp. 857 */ 858 static void hfi1_qp_iter_cb(struct rvt_qp *qp, u64 v) 859 { 860 int lastwqe; 861 struct ib_event ev; 862 struct hfi1_ibport *ibp = 863 to_iport(qp->ibqp.device, qp->port_num); 864 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 865 u8 sl = (u8)v; 866 867 if (qp->port_num != ppd->port || 868 (qp->ibqp.qp_type != IB_QPT_UC && 869 qp->ibqp.qp_type != IB_QPT_RC) || 870 rdma_ah_get_sl(&qp->remote_ah_attr) != sl || 871 !(ib_rvt_state_ops[qp->state] & RVT_POST_SEND_OK)) 872 return; 873 874 spin_lock_irq(&qp->r_lock); 875 spin_lock(&qp->s_hlock); 876 spin_lock(&qp->s_lock); 877 lastwqe = rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR); 878 spin_unlock(&qp->s_lock); 879 spin_unlock(&qp->s_hlock); 880 spin_unlock_irq(&qp->r_lock); 881 if (lastwqe) { 882 ev.device = qp->ibqp.device; 883 ev.element.qp = &qp->ibqp; 884 ev.event = IB_EVENT_QP_LAST_WQE_REACHED; 885 qp->ibqp.event_handler(&ev, qp->ibqp.qp_context); 886 } 887 } 888 889 /** 890 * hfi1_error_port_qps - put a port's RC/UC qps into error state 891 * @ibp: the ibport. 892 * @sl: the service level. 893 * 894 * This function places all RC/UC qps with a given service level into error 895 * state. It is generally called to force upper lay apps to abandon stale qps 896 * after an sl->sc mapping change. 897 */ 898 void hfi1_error_port_qps(struct hfi1_ibport *ibp, u8 sl) 899 { 900 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 901 struct hfi1_ibdev *dev = &ppd->dd->verbs_dev; 902 903 rvt_qp_iter(&dev->rdi, sl, hfi1_qp_iter_cb); 904 } 905