1 /*
2  * Copyright(c) 2015, 2016 Intel Corporation.
3  *
4  * This file is provided under a dual BSD/GPLv2 license.  When using or
5  * redistributing this file, you may do so under either license.
6  *
7  * GPL LICENSE SUMMARY
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * BSD LICENSE
19  *
20  * Redistribution and use in source and binary forms, with or without
21  * modification, are permitted provided that the following conditions
22  * are met:
23  *
24  *  - Redistributions of source code must retain the above copyright
25  *    notice, this list of conditions and the following disclaimer.
26  *  - Redistributions in binary form must reproduce the above copyright
27  *    notice, this list of conditions and the following disclaimer in
28  *    the documentation and/or other materials provided with the
29  *    distribution.
30  *  - Neither the name of Intel Corporation nor the names of its
31  *    contributors may be used to endorse or promote products derived
32  *    from this software without specific prior written permission.
33  *
34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45  *
46  */
47 #ifndef __PLATFORM_H
48 #define __PLATFORM_H
49 
50 #define METADATA_TABLE_FIELD_START_SHIFT		0
51 #define METADATA_TABLE_FIELD_START_LEN_BITS		15
52 #define METADATA_TABLE_FIELD_LEN_SHIFT			16
53 #define METADATA_TABLE_FIELD_LEN_LEN_BITS		16
54 
55 /* Header structure */
56 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT			0
57 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS		6
58 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT		16
59 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS		12
60 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT			28
61 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS		4
62 
63 enum platform_config_table_type_encoding {
64 	PLATFORM_CONFIG_TABLE_RESERVED,
65 	PLATFORM_CONFIG_SYSTEM_TABLE,
66 	PLATFORM_CONFIG_PORT_TABLE,
67 	PLATFORM_CONFIG_RX_PRESET_TABLE,
68 	PLATFORM_CONFIG_TX_PRESET_TABLE,
69 	PLATFORM_CONFIG_QSFP_ATTEN_TABLE,
70 	PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE,
71 	PLATFORM_CONFIG_TABLE_MAX
72 };
73 
74 enum platform_config_system_table_fields {
75 	SYSTEM_TABLE_RESERVED,
76 	SYSTEM_TABLE_NODE_STRING,
77 	SYSTEM_TABLE_SYSTEM_IMAGE_GUID,
78 	SYSTEM_TABLE_NODE_GUID,
79 	SYSTEM_TABLE_REVISION,
80 	SYSTEM_TABLE_VENDOR_OUI,
81 	SYSTEM_TABLE_META_VERSION,
82 	SYSTEM_TABLE_DEVICE_ID,
83 	SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP,
84 	SYSTEM_TABLE_QSFP_POWER_CLASS_MAX,
85 	SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G,
86 	SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
87 	SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT,
88 	SYSTEM_TABLE_MAX
89 };
90 
91 enum platform_config_port_table_fields {
92 	PORT_TABLE_RESERVED,
93 	PORT_TABLE_PORT_TYPE,
94 	PORT_TABLE_LOCAL_ATTEN_12G,
95 	PORT_TABLE_LOCAL_ATTEN_25G,
96 	PORT_TABLE_LINK_SPEED_SUPPORTED,
97 	PORT_TABLE_LINK_WIDTH_SUPPORTED,
98 	PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED,
99 	PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED,
100 	PORT_TABLE_VL_CAP,
101 	PORT_TABLE_MTU_CAP,
102 	PORT_TABLE_TX_LANE_ENABLE_MASK,
103 	PORT_TABLE_LOCAL_MAX_TIMEOUT,
104 	PORT_TABLE_REMOTE_ATTEN_12G,
105 	PORT_TABLE_REMOTE_ATTEN_25G,
106 	PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
107 	PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
108 	PORT_TABLE_RX_PRESET_IDX,
109 	PORT_TABLE_CABLE_REACH_CLASS,
110 	PORT_TABLE_MAX
111 };
112 
113 enum platform_config_rx_preset_table_fields {
114 	RX_PRESET_TABLE_RESERVED,
115 	RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
116 	RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
117 	RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
118 	RX_PRESET_TABLE_QSFP_RX_CDR,
119 	RX_PRESET_TABLE_QSFP_RX_EMP,
120 	RX_PRESET_TABLE_QSFP_RX_AMP,
121 	RX_PRESET_TABLE_MAX
122 };
123 
124 enum platform_config_tx_preset_table_fields {
125 	TX_PRESET_TABLE_RESERVED,
126 	TX_PRESET_TABLE_PRECUR,
127 	TX_PRESET_TABLE_ATTN,
128 	TX_PRESET_TABLE_POSTCUR,
129 	TX_PRESET_TABLE_QSFP_TX_CDR_APPLY,
130 	TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
131 	TX_PRESET_TABLE_QSFP_TX_CDR,
132 	TX_PRESET_TABLE_QSFP_TX_EQ,
133 	TX_PRESET_TABLE_MAX
134 };
135 
136 enum platform_config_qsfp_attn_table_fields {
137 	QSFP_ATTEN_TABLE_RESERVED,
138 	QSFP_ATTEN_TABLE_TX_PRESET_IDX,
139 	QSFP_ATTEN_TABLE_RX_PRESET_IDX,
140 	QSFP_ATTEN_TABLE_MAX
141 };
142 
143 enum platform_config_variable_settings_table_fields {
144 	VARIABLE_SETTINGS_TABLE_RESERVED,
145 	VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX,
146 	VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX,
147 	VARIABLE_SETTINGS_TABLE_MAX
148 };
149 
150 struct platform_config {
151 	size_t size;
152 	const u8 *data;
153 };
154 
155 struct platform_config_data {
156 	u32 *table;
157 	u32 *table_metadata;
158 	u32 num_table;
159 };
160 
161 /*
162  * This struct acts as a quick reference into the platform_data binary image
163  * and is populated by parse_platform_config(...) depending on the specific
164  * META_VERSION
165  */
166 struct platform_config_cache {
167 	u8  cache_valid;
168 	struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
169 };
170 
171 static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
172 	0,
173 	SYSTEM_TABLE_MAX,
174 	PORT_TABLE_MAX,
175 	RX_PRESET_TABLE_MAX,
176 	TX_PRESET_TABLE_MAX,
177 	QSFP_ATTEN_TABLE_MAX,
178 	VARIABLE_SETTINGS_TABLE_MAX
179 };
180 
181 /* This section defines default values and encodings for the
182  * fields defined for each table above
183  */
184 
185 /*
186  * =====================================================
187  *  System table encodings
188  * =====================================================
189  */
190 #define PLATFORM_CONFIG_MAGIC_NUM		0x3d4f5041
191 #define PLATFORM_CONFIG_MAGIC_NUMBER_LEN	4
192 
193 /*
194  * These power classes are the same as defined in SFF 8636 spec rev 2.4
195  * describing byte 129 in table 6-16, except enumerated in a different order
196  */
197 enum platform_config_qsfp_power_class_encoding {
198 	QSFP_POWER_CLASS_1 = 1,
199 	QSFP_POWER_CLASS_2,
200 	QSFP_POWER_CLASS_3,
201 	QSFP_POWER_CLASS_4,
202 	QSFP_POWER_CLASS_5,
203 	QSFP_POWER_CLASS_6,
204 	QSFP_POWER_CLASS_7
205 };
206 
207 /*
208  * ====================================================
209  *  Port table encodings
210  * ====================================================
211  */
212 enum platform_config_port_type_encoding {
213 	PORT_TYPE_UNKNOWN,
214 	PORT_TYPE_DISCONNECTED,
215 	PORT_TYPE_FIXED,
216 	PORT_TYPE_VARIABLE,
217 	PORT_TYPE_QSFP,
218 	PORT_TYPE_MAX
219 };
220 
221 enum platform_config_link_speed_supported_encoding {
222 	LINK_SPEED_SUPP_12G = 1,
223 	LINK_SPEED_SUPP_25G,
224 	LINK_SPEED_SUPP_12G_25G,
225 	LINK_SPEED_SUPP_MAX
226 };
227 
228 /*
229  * This is a subset (not strict) of the link downgrades
230  * supported. The link downgrades supported are expected
231  * to be supplied to the driver by another entity such as
232  * the fabric manager
233  */
234 enum platform_config_link_width_supported_encoding {
235 	LINK_WIDTH_SUPP_1X = 1,
236 	LINK_WIDTH_SUPP_2X,
237 	LINK_WIDTH_SUPP_2X_1X,
238 	LINK_WIDTH_SUPP_3X,
239 	LINK_WIDTH_SUPP_3X_1X,
240 	LINK_WIDTH_SUPP_3X_2X,
241 	LINK_WIDTH_SUPP_3X_2X_1X,
242 	LINK_WIDTH_SUPP_4X,
243 	LINK_WIDTH_SUPP_4X_1X,
244 	LINK_WIDTH_SUPP_4X_2X,
245 	LINK_WIDTH_SUPP_4X_2X_1X,
246 	LINK_WIDTH_SUPP_4X_3X,
247 	LINK_WIDTH_SUPP_4X_3X_1X,
248 	LINK_WIDTH_SUPP_4X_3X_2X,
249 	LINK_WIDTH_SUPP_4X_3X_2X_1X,
250 	LINK_WIDTH_SUPP_MAX
251 };
252 
253 enum platform_config_virtual_lane_capability_encoding {
254 	VL_CAP_VL0 = 1,
255 	VL_CAP_VL0_1,
256 	VL_CAP_VL0_2,
257 	VL_CAP_VL0_3,
258 	VL_CAP_VL0_4,
259 	VL_CAP_VL0_5,
260 	VL_CAP_VL0_6,
261 	VL_CAP_VL0_7,
262 	VL_CAP_VL0_8,
263 	VL_CAP_VL0_9,
264 	VL_CAP_VL0_10,
265 	VL_CAP_VL0_11,
266 	VL_CAP_VL0_12,
267 	VL_CAP_VL0_13,
268 	VL_CAP_VL0_14,
269 	VL_CAP_MAX
270 };
271 
272 /* Max MTU */
273 enum platform_config_mtu_capability_encoding {
274 	MTU_CAP_256   = 1,
275 	MTU_CAP_512   = 2,
276 	MTU_CAP_1024  = 3,
277 	MTU_CAP_2048  = 4,
278 	MTU_CAP_4096  = 5,
279 	MTU_CAP_8192  = 6,
280 	MTU_CAP_10240 = 7
281 };
282 
283 enum platform_config_local_max_timeout_encoding {
284 	LOCAL_MAX_TIMEOUT_10_MS = 1,
285 	LOCAL_MAX_TIMEOUT_100_MS,
286 	LOCAL_MAX_TIMEOUT_1_S,
287 	LOCAL_MAX_TIMEOUT_10_S,
288 	LOCAL_MAX_TIMEOUT_100_S,
289 	LOCAL_MAX_TIMEOUT_1000_S
290 };
291 
292 enum link_tuning_encoding {
293 	OPA_PASSIVE_TUNING,
294 	OPA_ACTIVE_TUNING,
295 	OPA_UNKNOWN_TUNING
296 };
297 
298 /* platform.c */
299 void get_platform_config(struct hfi1_devdata *dd);
300 void free_platform_config(struct hfi1_devdata *dd);
301 void get_port_type(struct hfi1_pportdata *ppd);
302 int set_qsfp_tx(struct hfi1_pportdata *ppd, int on);
303 void tune_serdes(struct hfi1_pportdata *ppd);
304 
305 #endif			/*__PLATFORM_H*/
306