1*145eba1aSCai Huoqing /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2f48ad614SDennis Dalessandro /* 3f48ad614SDennis Dalessandro * Copyright(c) 2015, 2016 Intel Corporation. 4f48ad614SDennis Dalessandro */ 5*145eba1aSCai Huoqing 6f48ad614SDennis Dalessandro #ifndef __PLATFORM_H 7f48ad614SDennis Dalessandro #define __PLATFORM_H 8f48ad614SDennis Dalessandro 9f48ad614SDennis Dalessandro #define METADATA_TABLE_FIELD_START_SHIFT 0 10f48ad614SDennis Dalessandro #define METADATA_TABLE_FIELD_START_LEN_BITS 15 11f48ad614SDennis Dalessandro #define METADATA_TABLE_FIELD_LEN_SHIFT 16 12f48ad614SDennis Dalessandro #define METADATA_TABLE_FIELD_LEN_LEN_BITS 16 13f48ad614SDennis Dalessandro 14f48ad614SDennis Dalessandro /* Header structure */ 15f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT 0 16f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS 6 17f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT 16 18f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS 12 19f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT 28 20f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS 4 21f48ad614SDennis Dalessandro 22f48ad614SDennis Dalessandro enum platform_config_table_type_encoding { 23f48ad614SDennis Dalessandro PLATFORM_CONFIG_TABLE_RESERVED, 24f48ad614SDennis Dalessandro PLATFORM_CONFIG_SYSTEM_TABLE, 25f48ad614SDennis Dalessandro PLATFORM_CONFIG_PORT_TABLE, 26f48ad614SDennis Dalessandro PLATFORM_CONFIG_RX_PRESET_TABLE, 27f48ad614SDennis Dalessandro PLATFORM_CONFIG_TX_PRESET_TABLE, 28f48ad614SDennis Dalessandro PLATFORM_CONFIG_QSFP_ATTEN_TABLE, 29f48ad614SDennis Dalessandro PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE, 30f48ad614SDennis Dalessandro PLATFORM_CONFIG_TABLE_MAX 31f48ad614SDennis Dalessandro }; 32f48ad614SDennis Dalessandro 33f48ad614SDennis Dalessandro enum platform_config_system_table_fields { 34f48ad614SDennis Dalessandro SYSTEM_TABLE_RESERVED, 35f48ad614SDennis Dalessandro SYSTEM_TABLE_NODE_STRING, 36f48ad614SDennis Dalessandro SYSTEM_TABLE_SYSTEM_IMAGE_GUID, 37f48ad614SDennis Dalessandro SYSTEM_TABLE_NODE_GUID, 38f48ad614SDennis Dalessandro SYSTEM_TABLE_REVISION, 39f48ad614SDennis Dalessandro SYSTEM_TABLE_VENDOR_OUI, 40f48ad614SDennis Dalessandro SYSTEM_TABLE_META_VERSION, 41f48ad614SDennis Dalessandro SYSTEM_TABLE_DEVICE_ID, 42f48ad614SDennis Dalessandro SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP, 43f48ad614SDennis Dalessandro SYSTEM_TABLE_QSFP_POWER_CLASS_MAX, 44f48ad614SDennis Dalessandro SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G, 45f48ad614SDennis Dalessandro SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G, 46f48ad614SDennis Dalessandro SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT, 47f48ad614SDennis Dalessandro SYSTEM_TABLE_MAX 48f48ad614SDennis Dalessandro }; 49f48ad614SDennis Dalessandro 50f48ad614SDennis Dalessandro enum platform_config_port_table_fields { 51f48ad614SDennis Dalessandro PORT_TABLE_RESERVED, 52f48ad614SDennis Dalessandro PORT_TABLE_PORT_TYPE, 53f48ad614SDennis Dalessandro PORT_TABLE_LOCAL_ATTEN_12G, 54f48ad614SDennis Dalessandro PORT_TABLE_LOCAL_ATTEN_25G, 55f48ad614SDennis Dalessandro PORT_TABLE_LINK_SPEED_SUPPORTED, 56f48ad614SDennis Dalessandro PORT_TABLE_LINK_WIDTH_SUPPORTED, 57f48ad614SDennis Dalessandro PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED, 58f48ad614SDennis Dalessandro PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED, 59f48ad614SDennis Dalessandro PORT_TABLE_VL_CAP, 60f48ad614SDennis Dalessandro PORT_TABLE_MTU_CAP, 61f48ad614SDennis Dalessandro PORT_TABLE_TX_LANE_ENABLE_MASK, 62f48ad614SDennis Dalessandro PORT_TABLE_LOCAL_MAX_TIMEOUT, 63f48ad614SDennis Dalessandro PORT_TABLE_REMOTE_ATTEN_12G, 64f48ad614SDennis Dalessandro PORT_TABLE_REMOTE_ATTEN_25G, 65f48ad614SDennis Dalessandro PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ, 66f48ad614SDennis Dalessandro PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ, 67f48ad614SDennis Dalessandro PORT_TABLE_RX_PRESET_IDX, 68f48ad614SDennis Dalessandro PORT_TABLE_CABLE_REACH_CLASS, 69f48ad614SDennis Dalessandro PORT_TABLE_MAX 70f48ad614SDennis Dalessandro }; 71f48ad614SDennis Dalessandro 72f48ad614SDennis Dalessandro enum platform_config_rx_preset_table_fields { 73f48ad614SDennis Dalessandro RX_PRESET_TABLE_RESERVED, 74f48ad614SDennis Dalessandro RX_PRESET_TABLE_QSFP_RX_CDR_APPLY, 75f48ad614SDennis Dalessandro RX_PRESET_TABLE_QSFP_RX_EMP_APPLY, 76f48ad614SDennis Dalessandro RX_PRESET_TABLE_QSFP_RX_AMP_APPLY, 77f48ad614SDennis Dalessandro RX_PRESET_TABLE_QSFP_RX_CDR, 78f48ad614SDennis Dalessandro RX_PRESET_TABLE_QSFP_RX_EMP, 79f48ad614SDennis Dalessandro RX_PRESET_TABLE_QSFP_RX_AMP, 80f48ad614SDennis Dalessandro RX_PRESET_TABLE_MAX 81f48ad614SDennis Dalessandro }; 82f48ad614SDennis Dalessandro 83f48ad614SDennis Dalessandro enum platform_config_tx_preset_table_fields { 84f48ad614SDennis Dalessandro TX_PRESET_TABLE_RESERVED, 85f48ad614SDennis Dalessandro TX_PRESET_TABLE_PRECUR, 86f48ad614SDennis Dalessandro TX_PRESET_TABLE_ATTN, 87f48ad614SDennis Dalessandro TX_PRESET_TABLE_POSTCUR, 88f48ad614SDennis Dalessandro TX_PRESET_TABLE_QSFP_TX_CDR_APPLY, 89f48ad614SDennis Dalessandro TX_PRESET_TABLE_QSFP_TX_EQ_APPLY, 90f48ad614SDennis Dalessandro TX_PRESET_TABLE_QSFP_TX_CDR, 91f48ad614SDennis Dalessandro TX_PRESET_TABLE_QSFP_TX_EQ, 92f48ad614SDennis Dalessandro TX_PRESET_TABLE_MAX 93f48ad614SDennis Dalessandro }; 94f48ad614SDennis Dalessandro 95f48ad614SDennis Dalessandro enum platform_config_qsfp_attn_table_fields { 96f48ad614SDennis Dalessandro QSFP_ATTEN_TABLE_RESERVED, 97f48ad614SDennis Dalessandro QSFP_ATTEN_TABLE_TX_PRESET_IDX, 98f48ad614SDennis Dalessandro QSFP_ATTEN_TABLE_RX_PRESET_IDX, 99f48ad614SDennis Dalessandro QSFP_ATTEN_TABLE_MAX 100f48ad614SDennis Dalessandro }; 101f48ad614SDennis Dalessandro 102f48ad614SDennis Dalessandro enum platform_config_variable_settings_table_fields { 103f48ad614SDennis Dalessandro VARIABLE_SETTINGS_TABLE_RESERVED, 104f48ad614SDennis Dalessandro VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX, 105f48ad614SDennis Dalessandro VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX, 106f48ad614SDennis Dalessandro VARIABLE_SETTINGS_TABLE_MAX 107f48ad614SDennis Dalessandro }; 108f48ad614SDennis Dalessandro 109f48ad614SDennis Dalessandro struct platform_config { 110f48ad614SDennis Dalessandro size_t size; 111f48ad614SDennis Dalessandro const u8 *data; 112f48ad614SDennis Dalessandro }; 113f48ad614SDennis Dalessandro 114f48ad614SDennis Dalessandro struct platform_config_data { 115f48ad614SDennis Dalessandro u32 *table; 116f48ad614SDennis Dalessandro u32 *table_metadata; 117f48ad614SDennis Dalessandro u32 num_table; 118f48ad614SDennis Dalessandro }; 119f48ad614SDennis Dalessandro 120f48ad614SDennis Dalessandro /* 121f48ad614SDennis Dalessandro * This struct acts as a quick reference into the platform_data binary image 122f48ad614SDennis Dalessandro * and is populated by parse_platform_config(...) depending on the specific 123f48ad614SDennis Dalessandro * META_VERSION 124f48ad614SDennis Dalessandro */ 125f48ad614SDennis Dalessandro struct platform_config_cache { 126f48ad614SDennis Dalessandro u8 cache_valid; 127f48ad614SDennis Dalessandro struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX]; 128f48ad614SDennis Dalessandro }; 129f48ad614SDennis Dalessandro 130f48ad614SDennis Dalessandro /* This section defines default values and encodings for the 131f48ad614SDennis Dalessandro * fields defined for each table above 132f48ad614SDennis Dalessandro */ 133f48ad614SDennis Dalessandro 134f48ad614SDennis Dalessandro /* 135f48ad614SDennis Dalessandro * ===================================================== 136f48ad614SDennis Dalessandro * System table encodings 137f48ad614SDennis Dalessandro * ===================================================== 138f48ad614SDennis Dalessandro */ 139f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_MAGIC_NUM 0x3d4f5041 140f48ad614SDennis Dalessandro #define PLATFORM_CONFIG_MAGIC_NUMBER_LEN 4 141f48ad614SDennis Dalessandro 142f48ad614SDennis Dalessandro /* 143f48ad614SDennis Dalessandro * These power classes are the same as defined in SFF 8636 spec rev 2.4 144f48ad614SDennis Dalessandro * describing byte 129 in table 6-16, except enumerated in a different order 145f48ad614SDennis Dalessandro */ 146f48ad614SDennis Dalessandro enum platform_config_qsfp_power_class_encoding { 147f48ad614SDennis Dalessandro QSFP_POWER_CLASS_1 = 1, 148f48ad614SDennis Dalessandro QSFP_POWER_CLASS_2, 149f48ad614SDennis Dalessandro QSFP_POWER_CLASS_3, 150f48ad614SDennis Dalessandro QSFP_POWER_CLASS_4, 151f48ad614SDennis Dalessandro QSFP_POWER_CLASS_5, 152f48ad614SDennis Dalessandro QSFP_POWER_CLASS_6, 153f48ad614SDennis Dalessandro QSFP_POWER_CLASS_7 154f48ad614SDennis Dalessandro }; 155f48ad614SDennis Dalessandro 156f48ad614SDennis Dalessandro /* 157f48ad614SDennis Dalessandro * ==================================================== 158f48ad614SDennis Dalessandro * Port table encodings 159f48ad614SDennis Dalessandro * ==================================================== 160f48ad614SDennis Dalessandro */ 161f48ad614SDennis Dalessandro enum platform_config_port_type_encoding { 162f48ad614SDennis Dalessandro PORT_TYPE_UNKNOWN, 163f48ad614SDennis Dalessandro PORT_TYPE_DISCONNECTED, 164f48ad614SDennis Dalessandro PORT_TYPE_FIXED, 165f48ad614SDennis Dalessandro PORT_TYPE_VARIABLE, 166f48ad614SDennis Dalessandro PORT_TYPE_QSFP, 167f48ad614SDennis Dalessandro PORT_TYPE_MAX 168f48ad614SDennis Dalessandro }; 169f48ad614SDennis Dalessandro 170f48ad614SDennis Dalessandro enum platform_config_link_speed_supported_encoding { 171f48ad614SDennis Dalessandro LINK_SPEED_SUPP_12G = 1, 172f48ad614SDennis Dalessandro LINK_SPEED_SUPP_25G, 173f48ad614SDennis Dalessandro LINK_SPEED_SUPP_12G_25G, 174f48ad614SDennis Dalessandro LINK_SPEED_SUPP_MAX 175f48ad614SDennis Dalessandro }; 176f48ad614SDennis Dalessandro 177f48ad614SDennis Dalessandro /* 178f48ad614SDennis Dalessandro * This is a subset (not strict) of the link downgrades 179f48ad614SDennis Dalessandro * supported. The link downgrades supported are expected 180f48ad614SDennis Dalessandro * to be supplied to the driver by another entity such as 181f48ad614SDennis Dalessandro * the fabric manager 182f48ad614SDennis Dalessandro */ 183f48ad614SDennis Dalessandro enum platform_config_link_width_supported_encoding { 184f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_1X = 1, 185f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_2X, 186f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_2X_1X, 187f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_3X, 188f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_3X_1X, 189f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_3X_2X, 190f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_3X_2X_1X, 191f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X, 192f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_1X, 193f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_2X, 194f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_2X_1X, 195f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_3X, 196f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_3X_1X, 197f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_3X_2X, 198f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_4X_3X_2X_1X, 199f48ad614SDennis Dalessandro LINK_WIDTH_SUPP_MAX 200f48ad614SDennis Dalessandro }; 201f48ad614SDennis Dalessandro 202f48ad614SDennis Dalessandro enum platform_config_virtual_lane_capability_encoding { 203f48ad614SDennis Dalessandro VL_CAP_VL0 = 1, 204f48ad614SDennis Dalessandro VL_CAP_VL0_1, 205f48ad614SDennis Dalessandro VL_CAP_VL0_2, 206f48ad614SDennis Dalessandro VL_CAP_VL0_3, 207f48ad614SDennis Dalessandro VL_CAP_VL0_4, 208f48ad614SDennis Dalessandro VL_CAP_VL0_5, 209f48ad614SDennis Dalessandro VL_CAP_VL0_6, 210f48ad614SDennis Dalessandro VL_CAP_VL0_7, 211f48ad614SDennis Dalessandro VL_CAP_VL0_8, 212f48ad614SDennis Dalessandro VL_CAP_VL0_9, 213f48ad614SDennis Dalessandro VL_CAP_VL0_10, 214f48ad614SDennis Dalessandro VL_CAP_VL0_11, 215f48ad614SDennis Dalessandro VL_CAP_VL0_12, 216f48ad614SDennis Dalessandro VL_CAP_VL0_13, 217f48ad614SDennis Dalessandro VL_CAP_VL0_14, 218f48ad614SDennis Dalessandro VL_CAP_MAX 219f48ad614SDennis Dalessandro }; 220f48ad614SDennis Dalessandro 221f48ad614SDennis Dalessandro /* Max MTU */ 222f48ad614SDennis Dalessandro enum platform_config_mtu_capability_encoding { 223f48ad614SDennis Dalessandro MTU_CAP_256 = 1, 224f48ad614SDennis Dalessandro MTU_CAP_512 = 2, 225f48ad614SDennis Dalessandro MTU_CAP_1024 = 3, 226f48ad614SDennis Dalessandro MTU_CAP_2048 = 4, 227f48ad614SDennis Dalessandro MTU_CAP_4096 = 5, 228f48ad614SDennis Dalessandro MTU_CAP_8192 = 6, 229f48ad614SDennis Dalessandro MTU_CAP_10240 = 7 230f48ad614SDennis Dalessandro }; 231f48ad614SDennis Dalessandro 232f48ad614SDennis Dalessandro enum platform_config_local_max_timeout_encoding { 233f48ad614SDennis Dalessandro LOCAL_MAX_TIMEOUT_10_MS = 1, 234f48ad614SDennis Dalessandro LOCAL_MAX_TIMEOUT_100_MS, 235f48ad614SDennis Dalessandro LOCAL_MAX_TIMEOUT_1_S, 236f48ad614SDennis Dalessandro LOCAL_MAX_TIMEOUT_10_S, 237f48ad614SDennis Dalessandro LOCAL_MAX_TIMEOUT_100_S, 238f48ad614SDennis Dalessandro LOCAL_MAX_TIMEOUT_1000_S 239f48ad614SDennis Dalessandro }; 240f48ad614SDennis Dalessandro 241f48ad614SDennis Dalessandro enum link_tuning_encoding { 242f48ad614SDennis Dalessandro OPA_PASSIVE_TUNING, 243f48ad614SDennis Dalessandro OPA_ACTIVE_TUNING, 244f48ad614SDennis Dalessandro OPA_UNKNOWN_TUNING 245f48ad614SDennis Dalessandro }; 246f48ad614SDennis Dalessandro 247fe4d9243SEaswar Hariharan /* 248fe4d9243SEaswar Hariharan * Shifts and masks for the link SI tuning values stuffed into the ASIC scratch 249fe4d9243SEaswar Hariharan * registers for integrated platforms 250fe4d9243SEaswar Hariharan */ 251fe4d9243SEaswar Hariharan #define PORT0_PORT_TYPE_SHIFT 0 252fe4d9243SEaswar Hariharan #define PORT0_LOCAL_ATTEN_SHIFT 4 253fe4d9243SEaswar Hariharan #define PORT0_REMOTE_ATTEN_SHIFT 10 254fe4d9243SEaswar Hariharan #define PORT0_DEFAULT_ATTEN_SHIFT 32 255fe4d9243SEaswar Hariharan 256fe4d9243SEaswar Hariharan #define PORT1_PORT_TYPE_SHIFT 16 257fe4d9243SEaswar Hariharan #define PORT1_LOCAL_ATTEN_SHIFT 20 258fe4d9243SEaswar Hariharan #define PORT1_REMOTE_ATTEN_SHIFT 26 259fe4d9243SEaswar Hariharan #define PORT1_DEFAULT_ATTEN_SHIFT 40 260fe4d9243SEaswar Hariharan 261fe4d9243SEaswar Hariharan #define PORT0_PORT_TYPE_MASK 0xFUL 262fe4d9243SEaswar Hariharan #define PORT0_LOCAL_ATTEN_MASK 0x3FUL 263fe4d9243SEaswar Hariharan #define PORT0_REMOTE_ATTEN_MASK 0x3FUL 264fe4d9243SEaswar Hariharan #define PORT0_DEFAULT_ATTEN_MASK 0xFFUL 265fe4d9243SEaswar Hariharan 266fe4d9243SEaswar Hariharan #define PORT1_PORT_TYPE_MASK 0xFUL 267fe4d9243SEaswar Hariharan #define PORT1_LOCAL_ATTEN_MASK 0x3FUL 268fe4d9243SEaswar Hariharan #define PORT1_REMOTE_ATTEN_MASK 0x3FUL 269fe4d9243SEaswar Hariharan #define PORT1_DEFAULT_ATTEN_MASK 0xFFUL 270fe4d9243SEaswar Hariharan 271fe4d9243SEaswar Hariharan #define PORT0_PORT_TYPE_SMASK (PORT0_PORT_TYPE_MASK << \ 272fe4d9243SEaswar Hariharan PORT0_PORT_TYPE_SHIFT) 273fe4d9243SEaswar Hariharan #define PORT0_LOCAL_ATTEN_SMASK (PORT0_LOCAL_ATTEN_MASK << \ 274fe4d9243SEaswar Hariharan PORT0_LOCAL_ATTEN_SHIFT) 275fe4d9243SEaswar Hariharan #define PORT0_REMOTE_ATTEN_SMASK (PORT0_REMOTE_ATTEN_MASK << \ 276fe4d9243SEaswar Hariharan PORT0_REMOTE_ATTEN_SHIFT) 277fe4d9243SEaswar Hariharan #define PORT0_DEFAULT_ATTEN_SMASK (PORT0_DEFAULT_ATTEN_MASK << \ 278fe4d9243SEaswar Hariharan PORT0_DEFAULT_ATTEN_SHIFT) 279fe4d9243SEaswar Hariharan 280fe4d9243SEaswar Hariharan #define PORT1_PORT_TYPE_SMASK (PORT1_PORT_TYPE_MASK << \ 281fe4d9243SEaswar Hariharan PORT1_PORT_TYPE_SHIFT) 282fe4d9243SEaswar Hariharan #define PORT1_LOCAL_ATTEN_SMASK (PORT1_LOCAL_ATTEN_MASK << \ 283fe4d9243SEaswar Hariharan PORT1_LOCAL_ATTEN_SHIFT) 284fe4d9243SEaswar Hariharan #define PORT1_REMOTE_ATTEN_SMASK (PORT1_REMOTE_ATTEN_MASK << \ 285fe4d9243SEaswar Hariharan PORT1_REMOTE_ATTEN_SHIFT) 286fe4d9243SEaswar Hariharan #define PORT1_DEFAULT_ATTEN_SMASK (PORT1_DEFAULT_ATTEN_MASK << \ 287fe4d9243SEaswar Hariharan PORT1_DEFAULT_ATTEN_SHIFT) 288fe4d9243SEaswar Hariharan 289fe4d9243SEaswar Hariharan #define QSFP_MAX_POWER_SHIFT 0 290fe4d9243SEaswar Hariharan #define TX_NO_EQ_SHIFT 4 291fe4d9243SEaswar Hariharan #define TX_EQ_SHIFT 25 292fe4d9243SEaswar Hariharan #define RX_SHIFT 46 293fe4d9243SEaswar Hariharan 294fe4d9243SEaswar Hariharan #define QSFP_MAX_POWER_MASK 0xFUL 295fe4d9243SEaswar Hariharan #define TX_NO_EQ_MASK 0x1FFFFFUL 296fe4d9243SEaswar Hariharan #define TX_EQ_MASK 0x1FFFFFUL 297fe4d9243SEaswar Hariharan #define RX_MASK 0xFFFFUL 298fe4d9243SEaswar Hariharan 299fe4d9243SEaswar Hariharan #define QSFP_MAX_POWER_SMASK (QSFP_MAX_POWER_MASK << \ 300fe4d9243SEaswar Hariharan QSFP_MAX_POWER_SHIFT) 301fe4d9243SEaswar Hariharan #define TX_NO_EQ_SMASK (TX_NO_EQ_MASK << TX_NO_EQ_SHIFT) 302fe4d9243SEaswar Hariharan #define TX_EQ_SMASK (TX_EQ_MASK << TX_EQ_SHIFT) 303fe4d9243SEaswar Hariharan #define RX_SMASK (RX_MASK << RX_SHIFT) 304fe4d9243SEaswar Hariharan 305fe4d9243SEaswar Hariharan #define TX_PRECUR_SHIFT 0 306fe4d9243SEaswar Hariharan #define TX_ATTN_SHIFT 4 307fe4d9243SEaswar Hariharan #define QSFP_TX_CDR_APPLY_SHIFT 9 308fe4d9243SEaswar Hariharan #define QSFP_TX_EQ_APPLY_SHIFT 10 309fe4d9243SEaswar Hariharan #define QSFP_TX_CDR_SHIFT 11 310fe4d9243SEaswar Hariharan #define QSFP_TX_EQ_SHIFT 12 311fe4d9243SEaswar Hariharan #define TX_POSTCUR_SHIFT 16 312fe4d9243SEaswar Hariharan 313fe4d9243SEaswar Hariharan #define TX_PRECUR_MASK 0xFUL 314fe4d9243SEaswar Hariharan #define TX_ATTN_MASK 0x1FUL 315fe4d9243SEaswar Hariharan #define QSFP_TX_CDR_APPLY_MASK 0x1UL 316fe4d9243SEaswar Hariharan #define QSFP_TX_EQ_APPLY_MASK 0x1UL 317fe4d9243SEaswar Hariharan #define QSFP_TX_CDR_MASK 0x1UL 318fe4d9243SEaswar Hariharan #define QSFP_TX_EQ_MASK 0xFUL 319fe4d9243SEaswar Hariharan #define TX_POSTCUR_MASK 0x1FUL 320fe4d9243SEaswar Hariharan 321fe4d9243SEaswar Hariharan #define TX_PRECUR_SMASK (TX_PRECUR_MASK << TX_PRECUR_SHIFT) 322fe4d9243SEaswar Hariharan #define TX_ATTN_SMASK (TX_ATTN_MASK << TX_ATTN_SHIFT) 323fe4d9243SEaswar Hariharan #define QSFP_TX_CDR_APPLY_SMASK (QSFP_TX_CDR_APPLY_MASK << \ 324fe4d9243SEaswar Hariharan QSFP_TX_CDR_APPLY_SHIFT) 325fe4d9243SEaswar Hariharan #define QSFP_TX_EQ_APPLY_SMASK (QSFP_TX_EQ_APPLY_MASK << \ 326fe4d9243SEaswar Hariharan QSFP_TX_EQ_APPLY_SHIFT) 327fe4d9243SEaswar Hariharan #define QSFP_TX_CDR_SMASK (QSFP_TX_CDR_MASK << QSFP_TX_CDR_SHIFT) 328fe4d9243SEaswar Hariharan #define QSFP_TX_EQ_SMASK (QSFP_TX_EQ_MASK << QSFP_TX_EQ_SHIFT) 329fe4d9243SEaswar Hariharan #define TX_POSTCUR_SMASK (TX_POSTCUR_MASK << TX_POSTCUR_SHIFT) 330fe4d9243SEaswar Hariharan 331fe4d9243SEaswar Hariharan #define QSFP_RX_CDR_APPLY_SHIFT 0 332fe4d9243SEaswar Hariharan #define QSFP_RX_EMP_APPLY_SHIFT 1 333fe4d9243SEaswar Hariharan #define QSFP_RX_AMP_APPLY_SHIFT 2 334fe4d9243SEaswar Hariharan #define QSFP_RX_CDR_SHIFT 3 335fe4d9243SEaswar Hariharan #define QSFP_RX_EMP_SHIFT 4 336fe4d9243SEaswar Hariharan #define QSFP_RX_AMP_SHIFT 8 337fe4d9243SEaswar Hariharan 338fe4d9243SEaswar Hariharan #define QSFP_RX_CDR_APPLY_MASK 0x1UL 339fe4d9243SEaswar Hariharan #define QSFP_RX_EMP_APPLY_MASK 0x1UL 340fe4d9243SEaswar Hariharan #define QSFP_RX_AMP_APPLY_MASK 0x1UL 341fe4d9243SEaswar Hariharan #define QSFP_RX_CDR_MASK 0x1UL 342fe4d9243SEaswar Hariharan #define QSFP_RX_EMP_MASK 0xFUL 343fe4d9243SEaswar Hariharan #define QSFP_RX_AMP_MASK 0x3UL 344fe4d9243SEaswar Hariharan 345fe4d9243SEaswar Hariharan #define QSFP_RX_CDR_APPLY_SMASK (QSFP_RX_CDR_APPLY_MASK << \ 346fe4d9243SEaswar Hariharan QSFP_RX_CDR_APPLY_SHIFT) 347fe4d9243SEaswar Hariharan #define QSFP_RX_EMP_APPLY_SMASK (QSFP_RX_EMP_APPLY_MASK << \ 348fe4d9243SEaswar Hariharan QSFP_RX_EMP_APPLY_SHIFT) 349fe4d9243SEaswar Hariharan #define QSFP_RX_AMP_APPLY_SMASK (QSFP_RX_AMP_APPLY_MASK << \ 350fe4d9243SEaswar Hariharan QSFP_RX_AMP_APPLY_SHIFT) 351fe4d9243SEaswar Hariharan #define QSFP_RX_CDR_SMASK (QSFP_RX_CDR_MASK << QSFP_RX_CDR_SHIFT) 352fe4d9243SEaswar Hariharan #define QSFP_RX_EMP_SMASK (QSFP_RX_EMP_MASK << QSFP_RX_EMP_SHIFT) 353fe4d9243SEaswar Hariharan #define QSFP_RX_AMP_SMASK (QSFP_RX_AMP_MASK << QSFP_RX_AMP_SHIFT) 354fe4d9243SEaswar Hariharan 355fe4d9243SEaswar Hariharan #define BITMAP_VERSION 1 356fe4d9243SEaswar Hariharan #define BITMAP_VERSION_SHIFT 44 357fe4d9243SEaswar Hariharan #define BITMAP_VERSION_MASK 0xFUL 358fe4d9243SEaswar Hariharan #define BITMAP_VERSION_SMASK (BITMAP_VERSION_MASK << \ 359fe4d9243SEaswar Hariharan BITMAP_VERSION_SHIFT) 360fe4d9243SEaswar Hariharan #define CHECKSUM_SHIFT 48 361fe4d9243SEaswar Hariharan #define CHECKSUM_MASK 0xFFFFUL 362fe4d9243SEaswar Hariharan #define CHECKSUM_SMASK (CHECKSUM_MASK << CHECKSUM_SHIFT) 363fe4d9243SEaswar Hariharan 364f48ad614SDennis Dalessandro /* platform.c */ 365f48ad614SDennis Dalessandro void get_platform_config(struct hfi1_devdata *dd); 366f48ad614SDennis Dalessandro void free_platform_config(struct hfi1_devdata *dd); 367f48ad614SDennis Dalessandro void get_port_type(struct hfi1_pportdata *ppd); 368f48ad614SDennis Dalessandro int set_qsfp_tx(struct hfi1_pportdata *ppd, int on); 369f48ad614SDennis Dalessandro void tune_serdes(struct hfi1_pportdata *ppd); 370f48ad614SDennis Dalessandro 371f48ad614SDennis Dalessandro #endif /*__PLATFORM_H*/ 372