1 /* 2 * Copyright(c) 2015 - 2019 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* 60 * This file contains PCIe utility routines. 61 */ 62 63 /* 64 * Do all the common PCIe setup and initialization. 65 */ 66 int hfi1_pcie_init(struct hfi1_devdata *dd) 67 { 68 int ret; 69 struct pci_dev *pdev = dd->pcidev; 70 71 ret = pci_enable_device(pdev); 72 if (ret) { 73 /* 74 * This can happen (in theory) iff: 75 * We did a chip reset, and then failed to reprogram the 76 * BAR, or the chip reset due to an internal error. We then 77 * unloaded the driver and reloaded it. 78 * 79 * Both reset cases set the BAR back to initial state. For 80 * the latter case, the AER sticky error bit at offset 0x718 81 * should be set, but the Linux kernel doesn't yet know 82 * about that, it appears. If the original BAR was retained 83 * in the kernel data structures, this may be OK. 84 */ 85 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); 86 return ret; 87 } 88 89 ret = pci_request_regions(pdev, DRIVER_NAME); 90 if (ret) { 91 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); 92 goto bail; 93 } 94 95 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 96 if (ret) { 97 /* 98 * If the 64 bit setup fails, try 32 bit. Some systems 99 * do not setup 64 bit maps on systems with 2GB or less 100 * memory installed. 101 */ 102 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 103 if (ret) { 104 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret); 105 goto bail; 106 } 107 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 108 } else { 109 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 110 } 111 if (ret) { 112 dd_dev_err(dd, "Unable to set DMA consistent mask: %d\n", ret); 113 goto bail; 114 } 115 116 pci_set_master(pdev); 117 (void)pci_enable_pcie_error_reporting(pdev); 118 return 0; 119 120 bail: 121 hfi1_pcie_cleanup(pdev); 122 return ret; 123 } 124 125 /* 126 * Clean what was done in hfi1_pcie_init() 127 */ 128 void hfi1_pcie_cleanup(struct pci_dev *pdev) 129 { 130 pci_disable_device(pdev); 131 /* 132 * Release regions should be called after the disable. OK to 133 * call if request regions has not been called or failed. 134 */ 135 pci_release_regions(pdev); 136 } 137 138 /* 139 * Do remaining PCIe setup, once dd is allocated, and save away 140 * fields required to re-initialize after a chip reset, or for 141 * various other purposes 142 */ 143 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 144 { 145 unsigned long len; 146 resource_size_t addr; 147 int ret = 0; 148 u32 rcv_array_count; 149 150 addr = pci_resource_start(pdev, 0); 151 len = pci_resource_len(pdev, 0); 152 153 /* 154 * The TXE PIO buffers are at the tail end of the chip space. 155 * Cut them off and map them separately. 156 */ 157 158 /* sanity check vs expectations */ 159 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 160 dd_dev_err(dd, "chip PIO range does not match\n"); 161 return -EINVAL; 162 } 163 164 dd->kregbase1 = ioremap(addr, RCV_ARRAY); 165 if (!dd->kregbase1) { 166 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); 167 return -ENOMEM; 168 } 169 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); 170 171 /* verify that reads actually work, save revision for reset check */ 172 dd->revision = readq(dd->kregbase1 + CCE_REVISION); 173 if (dd->revision == ~(u64)0) { 174 dd_dev_err(dd, "Cannot read chip CSRs\n"); 175 goto nomem; 176 } 177 178 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); 179 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); 180 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; 181 182 dd->kregbase2 = ioremap( 183 addr + dd->base2_start, 184 TXE_PIO_SEND - dd->base2_start); 185 if (!dd->kregbase2) { 186 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); 187 goto nomem; 188 } 189 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, 190 TXE_PIO_SEND - dd->base2_start); 191 192 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 193 if (!dd->piobase) { 194 dd_dev_err(dd, "WC mapping of send buffers failed\n"); 195 goto nomem; 196 } 197 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); 198 199 dd->physaddr = addr; /* used for io_remap, etc. */ 200 201 /* 202 * Map the chip's RcvArray as write-combining to allow us 203 * to write an entire cacheline worth of entries in one shot. 204 */ 205 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 206 rcv_array_count * 8); 207 if (!dd->rcvarray_wc) { 208 dd_dev_err(dd, "WC mapping of receive array failed\n"); 209 goto nomem; 210 } 211 dd_dev_info(dd, "WC RcvArray: %p for %x\n", 212 dd->rcvarray_wc, rcv_array_count * 8); 213 214 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ 215 return 0; 216 nomem: 217 ret = -ENOMEM; 218 hfi1_pcie_ddcleanup(dd); 219 return ret; 220 } 221 222 /* 223 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 224 * to releasing the dd memory. 225 * Void because all of the core pcie cleanup functions are void. 226 */ 227 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 228 { 229 dd->flags &= ~HFI1_PRESENT; 230 if (dd->kregbase1) 231 iounmap(dd->kregbase1); 232 dd->kregbase1 = NULL; 233 if (dd->kregbase2) 234 iounmap(dd->kregbase2); 235 dd->kregbase2 = NULL; 236 if (dd->rcvarray_wc) 237 iounmap(dd->rcvarray_wc); 238 dd->rcvarray_wc = NULL; 239 if (dd->piobase) 240 iounmap(dd->piobase); 241 dd->piobase = NULL; 242 } 243 244 /* return the PCIe link speed from the given link status */ 245 static u32 extract_speed(u16 linkstat) 246 { 247 u32 speed; 248 249 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 250 default: /* not defined, assume Gen1 */ 251 case PCI_EXP_LNKSTA_CLS_2_5GB: 252 speed = 2500; /* Gen 1, 2.5GHz */ 253 break; 254 case PCI_EXP_LNKSTA_CLS_5_0GB: 255 speed = 5000; /* Gen 2, 5GHz */ 256 break; 257 case PCI_EXP_LNKSTA_CLS_8_0GB: 258 speed = 8000; /* Gen 3, 8GHz */ 259 break; 260 } 261 return speed; 262 } 263 264 /* return the PCIe link speed from the given link status */ 265 static u32 extract_width(u16 linkstat) 266 { 267 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 268 } 269 270 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 271 static void update_lbus_info(struct hfi1_devdata *dd) 272 { 273 u16 linkstat; 274 int ret; 275 276 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 277 if (ret) { 278 dd_dev_err(dd, "Unable to read from PCI config\n"); 279 return; 280 } 281 282 dd->lbus_width = extract_width(linkstat); 283 dd->lbus_speed = extract_speed(linkstat); 284 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 285 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 286 } 287 288 /* 289 * Read in the current PCIe link width and speed. Find if the link is 290 * Gen3 capable. 291 */ 292 int pcie_speeds(struct hfi1_devdata *dd) 293 { 294 u32 linkcap; 295 struct pci_dev *parent = dd->pcidev->bus->self; 296 int ret; 297 298 if (!pci_is_pcie(dd->pcidev)) { 299 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 300 return -EINVAL; 301 } 302 303 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 304 dd->link_gen3_capable = 1; 305 306 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 307 if (ret) { 308 dd_dev_err(dd, "Unable to read from PCI config\n"); 309 return pcibios_err_to_errno(ret); 310 } 311 312 if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GB) { 313 dd_dev_info(dd, 314 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 315 linkcap & PCI_EXP_LNKCAP_SLS); 316 dd->link_gen3_capable = 0; 317 } 318 319 /* 320 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 321 */ 322 if (parent && 323 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || 324 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { 325 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 326 dd->link_gen3_capable = 0; 327 } 328 329 /* obtain the link width and current speed */ 330 update_lbus_info(dd); 331 332 dd_dev_info(dd, "%s\n", dd->lbus_info); 333 334 return 0; 335 } 336 337 /** 338 * Restore command and BARs after a reset has wiped them out 339 * 340 * Returns 0 on success, otherwise a negative error value 341 */ 342 int restore_pci_variables(struct hfi1_devdata *dd) 343 { 344 int ret; 345 346 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 347 if (ret) 348 goto error; 349 350 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 351 dd->pcibar0); 352 if (ret) 353 goto error; 354 355 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 356 dd->pcibar1); 357 if (ret) 358 goto error; 359 360 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 361 if (ret) 362 goto error; 363 364 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, 365 dd->pcie_devctl); 366 if (ret) 367 goto error; 368 369 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, 370 dd->pcie_lnkctl); 371 if (ret) 372 goto error; 373 374 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 375 dd->pcie_devctl2); 376 if (ret) 377 goto error; 378 379 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 380 if (ret) 381 goto error; 382 383 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { 384 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, 385 dd->pci_tph2); 386 if (ret) 387 goto error; 388 } 389 return 0; 390 391 error: 392 dd_dev_err(dd, "Unable to write to PCI config\n"); 393 return pcibios_err_to_errno(ret); 394 } 395 396 /** 397 * Save BARs and command to rewrite after device reset 398 * 399 * Returns 0 on success, otherwise a negative error value 400 */ 401 int save_pci_variables(struct hfi1_devdata *dd) 402 { 403 int ret; 404 405 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 406 &dd->pcibar0); 407 if (ret) 408 goto error; 409 410 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 411 &dd->pcibar1); 412 if (ret) 413 goto error; 414 415 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 416 if (ret) 417 goto error; 418 419 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 420 if (ret) 421 goto error; 422 423 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, 424 &dd->pcie_devctl); 425 if (ret) 426 goto error; 427 428 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, 429 &dd->pcie_lnkctl); 430 if (ret) 431 goto error; 432 433 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 434 &dd->pcie_devctl2); 435 if (ret) 436 goto error; 437 438 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 439 if (ret) 440 goto error; 441 442 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { 443 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, 444 &dd->pci_tph2); 445 if (ret) 446 goto error; 447 } 448 return 0; 449 450 error: 451 dd_dev_err(dd, "Unable to read from PCI config\n"); 452 return pcibios_err_to_errno(ret); 453 } 454 455 /* 456 * BIOS may not set PCIe bus-utilization parameters for best performance. 457 * Check and optionally adjust them to maximize our throughput. 458 */ 459 static int hfi1_pcie_caps; 460 module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444); 461 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 462 463 /** 464 * tune_pcie_caps() - Code to adjust PCIe capabilities. 465 * @dd: Valid device data structure 466 * 467 */ 468 void tune_pcie_caps(struct hfi1_devdata *dd) 469 { 470 struct pci_dev *parent; 471 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 472 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 473 int ret; 474 475 /* 476 * Turn on extended tags in DevCtl in case the BIOS has turned it off 477 * to improve WFR SDMA bandwidth 478 */ 479 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); 480 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 481 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 482 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 483 ret = pcie_capability_write_word(dd->pcidev, 484 PCI_EXP_DEVCTL, ectl); 485 if (ret) 486 dd_dev_info(dd, "Unable to write to PCI config\n"); 487 } 488 /* Find out supported and configured values for parent (root) */ 489 parent = dd->pcidev->bus->self; 490 /* 491 * The driver cannot perform the tuning if it does not have 492 * access to the upstream component. 493 */ 494 if (!parent) { 495 dd_dev_info(dd, "Parent not found\n"); 496 return; 497 } 498 if (!pci_is_root_bus(parent->bus)) { 499 dd_dev_info(dd, "Parent not root\n"); 500 return; 501 } 502 if (!pci_is_pcie(parent)) { 503 dd_dev_info(dd, "Parent is not PCI Express capable\n"); 504 return; 505 } 506 if (!pci_is_pcie(dd->pcidev)) { 507 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); 508 return; 509 } 510 rc_mpss = parent->pcie_mpss; 511 rc_mps = ffs(pcie_get_mps(parent)) - 8; 512 /* Find out supported and configured values for endpoint (us) */ 513 ep_mpss = dd->pcidev->pcie_mpss; 514 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 515 516 /* Find max payload supported by root, endpoint */ 517 if (rc_mpss > ep_mpss) 518 rc_mpss = ep_mpss; 519 520 /* If Supported greater than limit in module param, limit it */ 521 if (rc_mpss > (hfi1_pcie_caps & 7)) 522 rc_mpss = hfi1_pcie_caps & 7; 523 /* If less than (allowed, supported), bump root payload */ 524 if (rc_mpss > rc_mps) { 525 rc_mps = rc_mpss; 526 pcie_set_mps(parent, 128 << rc_mps); 527 } 528 /* If less than (allowed, supported), bump endpoint payload */ 529 if (rc_mpss > ep_mps) { 530 ep_mps = rc_mpss; 531 pcie_set_mps(dd->pcidev, 128 << ep_mps); 532 } 533 534 /* 535 * Now the Read Request size. 536 * No field for max supported, but PCIe spec limits it to 4096, 537 * which is code '5' (log2(4096) - 7) 538 */ 539 max_mrrs = 5; 540 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 541 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 542 543 max_mrrs = 128 << max_mrrs; 544 rc_mrrs = pcie_get_readrq(parent); 545 ep_mrrs = pcie_get_readrq(dd->pcidev); 546 547 if (max_mrrs > rc_mrrs) { 548 rc_mrrs = max_mrrs; 549 pcie_set_readrq(parent, rc_mrrs); 550 } 551 if (max_mrrs > ep_mrrs) { 552 ep_mrrs = max_mrrs; 553 pcie_set_readrq(dd->pcidev, ep_mrrs); 554 } 555 } 556 557 /* End of PCIe capability tuning */ 558 559 /* 560 * From here through hfi1_pci_err_handler definition is invoked via 561 * PCI error infrastructure, registered via pci 562 */ 563 static pci_ers_result_t 564 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 565 { 566 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 567 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 568 569 switch (state) { 570 case pci_channel_io_normal: 571 dd_dev_info(dd, "State Normal, ignoring\n"); 572 break; 573 574 case pci_channel_io_frozen: 575 dd_dev_info(dd, "State Frozen, requesting reset\n"); 576 pci_disable_device(pdev); 577 ret = PCI_ERS_RESULT_NEED_RESET; 578 break; 579 580 case pci_channel_io_perm_failure: 581 if (dd) { 582 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 583 /* no more register accesses! */ 584 dd->flags &= ~HFI1_PRESENT; 585 hfi1_disable_after_error(dd); 586 } 587 /* else early, or other problem */ 588 ret = PCI_ERS_RESULT_DISCONNECT; 589 break; 590 591 default: /* shouldn't happen */ 592 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 593 state); 594 break; 595 } 596 return ret; 597 } 598 599 static pci_ers_result_t 600 pci_mmio_enabled(struct pci_dev *pdev) 601 { 602 u64 words = 0U; 603 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 604 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 605 606 if (dd && dd->pport) { 607 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 608 if (words == ~0ULL) 609 ret = PCI_ERS_RESULT_NEED_RESET; 610 dd_dev_info(dd, 611 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", 612 words, ret); 613 } 614 return ret; 615 } 616 617 static pci_ers_result_t 618 pci_slot_reset(struct pci_dev *pdev) 619 { 620 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 621 622 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 623 return PCI_ERS_RESULT_CAN_RECOVER; 624 } 625 626 static void 627 pci_resume(struct pci_dev *pdev) 628 { 629 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 630 631 dd_dev_info(dd, "HFI1 resume function called\n"); 632 /* 633 * Running jobs will fail, since it's asynchronous 634 * unlike sysfs-requested reset. Better than 635 * doing nothing. 636 */ 637 hfi1_init(dd, 1); /* same as re-init after reset */ 638 } 639 640 const struct pci_error_handlers hfi1_pci_err_handler = { 641 .error_detected = pci_error_detected, 642 .mmio_enabled = pci_mmio_enabled, 643 .slot_reset = pci_slot_reset, 644 .resume = pci_resume, 645 }; 646 647 /*============================================================================*/ 648 /* PCIe Gen3 support */ 649 650 /* 651 * This code is separated out because it is expected to be removed in the 652 * final shipping product. If not, then it will be revisited and items 653 * will be moved to more standard locations. 654 */ 655 656 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 657 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 658 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 659 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 660 661 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 662 #define DL_ERR_NONE 0x0 /* no error */ 663 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 664 /* or response data */ 665 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 666 #define DL_ERR_SECURITY 0x3 /* security check failed */ 667 #define DL_ERR_SBUS 0x4 /* SBus status error */ 668 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 669 670 /* gasket block secondary bus reset delay */ 671 #define SBR_DELAY_US 200000 /* 200ms */ 672 673 static uint pcie_target = 3; 674 module_param(pcie_target, uint, S_IRUGO); 675 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 676 677 static uint pcie_force; 678 module_param(pcie_force, uint, S_IRUGO); 679 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 680 681 static uint pcie_retry = 5; 682 module_param(pcie_retry, uint, S_IRUGO); 683 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 684 685 #define UNSET_PSET 255 686 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 687 #define DEFAULT_MCP_PSET 6 /* MCP HFI */ 688 static uint pcie_pset = UNSET_PSET; 689 module_param(pcie_pset, uint, S_IRUGO); 690 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 691 692 static uint pcie_ctle = 3; /* discrete on, integrated on */ 693 module_param(pcie_ctle, uint, S_IRUGO); 694 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 695 696 /* equalization columns */ 697 #define PREC 0 698 #define ATTN 1 699 #define POST 2 700 701 /* discrete silicon preliminary equalization values */ 702 static const u8 discrete_preliminary_eq[11][3] = { 703 /* prec attn post */ 704 { 0x00, 0x00, 0x12 }, /* p0 */ 705 { 0x00, 0x00, 0x0c }, /* p1 */ 706 { 0x00, 0x00, 0x0f }, /* p2 */ 707 { 0x00, 0x00, 0x09 }, /* p3 */ 708 { 0x00, 0x00, 0x00 }, /* p4 */ 709 { 0x06, 0x00, 0x00 }, /* p5 */ 710 { 0x09, 0x00, 0x00 }, /* p6 */ 711 { 0x06, 0x00, 0x0f }, /* p7 */ 712 { 0x09, 0x00, 0x09 }, /* p8 */ 713 { 0x0c, 0x00, 0x00 }, /* p9 */ 714 { 0x00, 0x00, 0x18 }, /* p10 */ 715 }; 716 717 /* integrated silicon preliminary equalization values */ 718 static const u8 integrated_preliminary_eq[11][3] = { 719 /* prec attn post */ 720 { 0x00, 0x1e, 0x07 }, /* p0 */ 721 { 0x00, 0x1e, 0x05 }, /* p1 */ 722 { 0x00, 0x1e, 0x06 }, /* p2 */ 723 { 0x00, 0x1e, 0x04 }, /* p3 */ 724 { 0x00, 0x1e, 0x00 }, /* p4 */ 725 { 0x03, 0x1e, 0x00 }, /* p5 */ 726 { 0x04, 0x1e, 0x00 }, /* p6 */ 727 { 0x03, 0x1e, 0x06 }, /* p7 */ 728 { 0x03, 0x1e, 0x04 }, /* p8 */ 729 { 0x05, 0x1e, 0x00 }, /* p9 */ 730 { 0x00, 0x1e, 0x0a }, /* p10 */ 731 }; 732 733 static const u8 discrete_ctle_tunings[11][4] = { 734 /* DC LF HF BW */ 735 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 736 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 737 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 738 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 739 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 740 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 741 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 742 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 743 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 744 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 745 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 746 }; 747 748 static const u8 integrated_ctle_tunings[11][4] = { 749 /* DC LF HF BW */ 750 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 751 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 752 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 753 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 754 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 755 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 756 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 757 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 758 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 759 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 760 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 761 }; 762 763 /* helper to format the value to write to hardware */ 764 #define eq_value(pre, curr, post) \ 765 ((((u32)(pre)) << \ 766 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 767 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 768 | (((u32)(post)) << \ 769 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 770 771 /* 772 * Load the given EQ preset table into the PCIe hardware. 773 */ 774 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 775 u8 div) 776 { 777 struct pci_dev *pdev = dd->pcidev; 778 u32 hit_error = 0; 779 u32 violation; 780 u32 i; 781 u8 c_minus1, c0, c_plus1; 782 int ret; 783 784 for (i = 0; i < 11; i++) { 785 /* set index */ 786 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 787 /* write the value */ 788 c_minus1 = eq[i][PREC] / div; 789 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 790 c_plus1 = eq[i][POST] / div; 791 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 792 eq_value(c_minus1, c0, c_plus1)); 793 /* check if these coefficients violate EQ rules */ 794 ret = pci_read_config_dword(dd->pcidev, 795 PCIE_CFG_REG_PL105, &violation); 796 if (ret) { 797 dd_dev_err(dd, "Unable to read from PCI config\n"); 798 hit_error = 1; 799 break; 800 } 801 802 if (violation 803 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 804 if (hit_error == 0) { 805 dd_dev_err(dd, 806 "Gen3 EQ Table Coefficient rule violations\n"); 807 dd_dev_err(dd, " prec attn post\n"); 808 } 809 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 810 i, (u32)eq[i][0], (u32)eq[i][1], 811 (u32)eq[i][2]); 812 dd_dev_err(dd, " %02x %02x %02x\n", 813 (u32)c_minus1, (u32)c0, (u32)c_plus1); 814 hit_error = 1; 815 } 816 } 817 if (hit_error) 818 return -EINVAL; 819 return 0; 820 } 821 822 /* 823 * Steps to be done after the PCIe firmware is downloaded and 824 * before the SBR for the Pcie Gen3. 825 * The SBus resource is already being held. 826 */ 827 static void pcie_post_steps(struct hfi1_devdata *dd) 828 { 829 int i; 830 831 set_sbus_fast_mode(dd); 832 /* 833 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 834 * This avoids a spurious framing error that can otherwise be 835 * generated by the MAC layer. 836 * 837 * Use individual addresses since no broadcast is set up. 838 */ 839 for (i = 0; i < NUM_PCIE_SERDES; i++) { 840 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 841 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 842 } 843 844 clear_sbus_fast_mode(dd); 845 } 846 847 /* 848 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 849 * 850 * Based on pci_parent_bus_reset() which is not exported by the 851 * kernel core. 852 */ 853 static int trigger_sbr(struct hfi1_devdata *dd) 854 { 855 struct pci_dev *dev = dd->pcidev; 856 struct pci_dev *pdev; 857 858 /* need a parent */ 859 if (!dev->bus->self) { 860 dd_dev_err(dd, "%s: no parent device\n", __func__); 861 return -ENOTTY; 862 } 863 864 /* should not be anyone else on the bus */ 865 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 866 if (pdev != dev) { 867 dd_dev_err(dd, 868 "%s: another device is on the same bus\n", 869 __func__); 870 return -ENOTTY; 871 } 872 873 /* 874 * This is an end around to do an SBR during probe time. A new API needs 875 * to be implemented to have cleaner interface but this fixes the 876 * current brokenness 877 */ 878 return pci_bridge_secondary_bus_reset(dev->bus->self); 879 } 880 881 /* 882 * Write the given gasket interrupt register. 883 */ 884 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 885 u16 code, u16 data) 886 { 887 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 888 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 889 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 890 } 891 892 /* 893 * Tell the gasket logic how to react to the reset. 894 */ 895 static void arm_gasket_logic(struct hfi1_devdata *dd) 896 { 897 u64 reg; 898 899 reg = (((u64)1 << dd->hfi1_id) << 900 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 901 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 902 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 903 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 904 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 905 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 906 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 907 /* read back to push the write */ 908 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 909 } 910 911 /* 912 * CCE_PCIE_CTRL long name helpers 913 * We redefine these shorter macros to use in the code while leaving 914 * chip_registers.h to be autogenerated from the hardware spec. 915 */ 916 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 917 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 918 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 919 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 920 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 921 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 922 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 923 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 924 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 925 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 926 927 /* 928 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 929 */ 930 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 931 { 932 u64 pcie_ctrl; 933 u64 xmt_margin; 934 u64 xmt_margin_oe; 935 u64 lane_delay; 936 u64 lane_bundle; 937 938 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 939 940 /* 941 * For Discrete, use full-swing. 942 * - PCIe TX defaults to full-swing. 943 * Leave this register as default. 944 * For Integrated, use half-swing 945 * - Copy xmt_margin and xmt_margin_oe 946 * from Gen1/Gen2 to Gen3. 947 */ 948 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 949 /* extract initial fields */ 950 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 951 & MARGIN_GEN1_GEN2_MASK; 952 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 953 & MARGIN_G1_G2_OVERWRITE_MASK; 954 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 955 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 956 & LANE_BUNDLE_MASK; 957 958 /* 959 * For A0, EFUSE values are not set. Override with the 960 * correct values. 961 */ 962 if (is_ax(dd)) { 963 /* 964 * xmt_margin and OverwiteEnabel should be the 965 * same for Gen1/Gen2 and Gen3 966 */ 967 xmt_margin = 0x5; 968 xmt_margin_oe = 0x1; 969 lane_delay = 0xF; /* Delay 240ns. */ 970 lane_bundle = 0x0; /* Set to 1 lane. */ 971 } 972 973 /* overwrite existing values */ 974 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 975 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 976 | (xmt_margin << MARGIN_SHIFT) 977 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 978 | (lane_delay << LANE_DELAY_SHIFT) 979 | (lane_bundle << LANE_BUNDLE_SHIFT); 980 981 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 982 } 983 984 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 985 fname, pcie_ctrl); 986 } 987 988 /* 989 * Do all the steps needed to transition the PCIe link to Gen3 speed. 990 */ 991 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 992 { 993 struct pci_dev *parent = dd->pcidev->bus->self; 994 u64 fw_ctrl; 995 u64 reg, therm; 996 u32 reg32, fs, lf; 997 u32 status, err; 998 int ret; 999 int do_retry, retry_count = 0; 1000 int intnum = 0; 1001 uint default_pset; 1002 uint pset = pcie_pset; 1003 u16 target_vector, target_speed; 1004 u16 lnkctl2, vendor; 1005 u8 div; 1006 const u8 (*eq)[3]; 1007 const u8 (*ctle_tunings)[4]; 1008 uint static_ctle_mode; 1009 int return_error = 0; 1010 u32 target_width; 1011 1012 /* PCIe Gen3 is for the ASIC only */ 1013 if (dd->icode != ICODE_RTL_SILICON) 1014 return 0; 1015 1016 if (pcie_target == 1) { /* target Gen1 */ 1017 target_vector = PCI_EXP_LNKCTL2_TLS_2_5GT; 1018 target_speed = 2500; 1019 } else if (pcie_target == 2) { /* target Gen2 */ 1020 target_vector = PCI_EXP_LNKCTL2_TLS_5_0GT; 1021 target_speed = 5000; 1022 } else if (pcie_target == 3) { /* target Gen3 */ 1023 target_vector = PCI_EXP_LNKCTL2_TLS_8_0GT; 1024 target_speed = 8000; 1025 } else { 1026 /* off or invalid target - skip */ 1027 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 1028 return 0; 1029 } 1030 1031 /* if already at target speed, done (unless forced) */ 1032 if (dd->lbus_speed == target_speed) { 1033 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 1034 pcie_target, 1035 pcie_force ? "re-doing anyway" : "skipping"); 1036 if (!pcie_force) 1037 return 0; 1038 } 1039 1040 /* 1041 * The driver cannot do the transition if it has no access to the 1042 * upstream component 1043 */ 1044 if (!parent) { 1045 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 1046 __func__); 1047 return 0; 1048 } 1049 1050 /* Previous Gen1/Gen2 bus width */ 1051 target_width = dd->lbus_width; 1052 1053 /* 1054 * Do the Gen3 transition. Steps are those of the PCIe Gen3 1055 * recipe. 1056 */ 1057 1058 /* step 1: pcie link working in gen1/gen2 */ 1059 1060 /* step 2: if either side is not capable of Gen3, done */ 1061 if (pcie_target == 3 && !dd->link_gen3_capable) { 1062 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1063 ret = -ENOSYS; 1064 goto done_no_mutex; 1065 } 1066 1067 /* hold the SBus resource across the firmware download and SBR */ 1068 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1069 if (ret) { 1070 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1071 __func__); 1072 return ret; 1073 } 1074 1075 /* make sure thermal polling is not causing interrupts */ 1076 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1077 if (therm) { 1078 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1079 msleep(100); 1080 dd_dev_info(dd, "%s: Disabled therm polling\n", 1081 __func__); 1082 } 1083 1084 retry: 1085 /* the SBus download will reset the spico for thermal */ 1086 1087 /* step 3: download SBus Master firmware */ 1088 /* step 4: download PCIe Gen3 SerDes firmware */ 1089 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1090 ret = load_pcie_firmware(dd); 1091 if (ret) { 1092 /* do not proceed if the firmware cannot be downloaded */ 1093 return_error = 1; 1094 goto done; 1095 } 1096 1097 /* step 5: set up device parameter settings */ 1098 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1099 1100 /* 1101 * PcieCfgSpcie1 - Link Control 3 1102 * Leave at reset value. No need to set PerfEq - link equalization 1103 * will be performed automatically after the SBR when the target 1104 * speed is 8GT/s. 1105 */ 1106 1107 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1108 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1109 1110 /* step 5a: Set Synopsys Port Logic registers */ 1111 1112 /* 1113 * PcieCfgRegPl2 - Port Force Link 1114 * 1115 * Set the low power field to 0x10 to avoid unnecessary power 1116 * management messages. All other fields are zero. 1117 */ 1118 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1119 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1120 1121 /* 1122 * PcieCfgRegPl100 - Gen3 Control 1123 * 1124 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1125 * turn on PcieCfgRegPl100.EqEieosCnt 1126 * Everything else zero. 1127 */ 1128 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1129 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1130 1131 /* 1132 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1133 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1134 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1135 * PcieCfgRegPl105 - Gen3 EQ Status 1136 * 1137 * Give initial EQ settings. 1138 */ 1139 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1140 /* 1000mV, FS=24, LF = 8 */ 1141 fs = 24; 1142 lf = 8; 1143 div = 3; 1144 eq = discrete_preliminary_eq; 1145 default_pset = DEFAULT_DISCRETE_PSET; 1146 ctle_tunings = discrete_ctle_tunings; 1147 /* bit 0 - discrete on/off */ 1148 static_ctle_mode = pcie_ctle & 0x1; 1149 } else { 1150 /* 400mV, FS=29, LF = 9 */ 1151 fs = 29; 1152 lf = 9; 1153 div = 1; 1154 eq = integrated_preliminary_eq; 1155 default_pset = DEFAULT_MCP_PSET; 1156 ctle_tunings = integrated_ctle_tunings; 1157 /* bit 1 - integrated on/off */ 1158 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1159 } 1160 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1161 (fs << 1162 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1163 (lf << 1164 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1165 ret = load_eq_table(dd, eq, fs, div); 1166 if (ret) 1167 goto done; 1168 1169 /* 1170 * PcieCfgRegPl106 - Gen3 EQ Control 1171 * 1172 * Set Gen3EqPsetReqVec, leave other fields 0. 1173 */ 1174 if (pset == UNSET_PSET) 1175 pset = default_pset; 1176 if (pset > 10) { /* valid range is 0-10, inclusive */ 1177 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1178 __func__, pset, default_pset); 1179 pset = default_pset; 1180 } 1181 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); 1182 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1183 ((1 << pset) << 1184 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1185 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1186 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1187 1188 /* 1189 * step 5b: Do post firmware download steps via SBus 1190 */ 1191 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1192 pcie_post_steps(dd); 1193 1194 /* 1195 * step 5c: Program gasket interrupts 1196 */ 1197 /* set the Rx Bit Rate to REFCLK ratio */ 1198 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1199 /* disable pCal for PCIe Gen3 RX equalization */ 1200 /* select adaptive or static CTLE */ 1201 write_gasket_interrupt(dd, intnum++, 0x0026, 1202 0x5b01 | (static_ctle_mode << 3)); 1203 /* 1204 * Enable iCal for PCIe Gen3 RX equalization, and set which 1205 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1206 */ 1207 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1208 1209 if (static_ctle_mode) { 1210 /* apply static CTLE tunings */ 1211 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1212 1213 pcie_dc = ctle_tunings[pset][0]; 1214 pcie_lf = ctle_tunings[pset][1]; 1215 pcie_hf = ctle_tunings[pset][2]; 1216 pcie_bw = ctle_tunings[pset][3]; 1217 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1218 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1219 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1220 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1221 } 1222 1223 /* terminate list */ 1224 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1225 1226 /* 1227 * step 5d: program XMT margin 1228 */ 1229 write_xmt_margin(dd, __func__); 1230 1231 /* 1232 * step 5e: disable active state power management (ASPM). It 1233 * will be enabled if required later 1234 */ 1235 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1236 aspm_hw_disable_l1(dd); 1237 1238 /* 1239 * step 5f: clear DirectSpeedChange 1240 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1241 * change in the speed target from starting before we are ready. 1242 * This field defaults to 0 and we are not changing it, so nothing 1243 * needs to be done. 1244 */ 1245 1246 /* step 5g: Set target link speed */ 1247 /* 1248 * Set target link speed to be target on both device and parent. 1249 * On setting the parent: Some system BIOSs "helpfully" set the 1250 * parent target speed to Gen2 to match the ASIC's initial speed. 1251 * We can set the target Gen3 because we have already checked 1252 * that it is Gen3 capable earlier. 1253 */ 1254 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1255 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1256 if (ret) { 1257 dd_dev_err(dd, "Unable to read from PCI config\n"); 1258 return_error = 1; 1259 goto done; 1260 } 1261 1262 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1263 (u32)lnkctl2); 1264 /* only write to parent if target is not as high as ours */ 1265 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) { 1266 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 1267 lnkctl2 |= target_vector; 1268 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1269 (u32)lnkctl2); 1270 ret = pcie_capability_write_word(parent, 1271 PCI_EXP_LNKCTL2, lnkctl2); 1272 if (ret) { 1273 dd_dev_err(dd, "Unable to write to PCI config\n"); 1274 return_error = 1; 1275 goto done; 1276 } 1277 } else { 1278 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1279 } 1280 1281 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1282 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1283 if (ret) { 1284 dd_dev_err(dd, "Unable to read from PCI config\n"); 1285 return_error = 1; 1286 goto done; 1287 } 1288 1289 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1290 (u32)lnkctl2); 1291 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 1292 lnkctl2 |= target_vector; 1293 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1294 (u32)lnkctl2); 1295 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1296 if (ret) { 1297 dd_dev_err(dd, "Unable to write to PCI config\n"); 1298 return_error = 1; 1299 goto done; 1300 } 1301 1302 /* step 5h: arm gasket logic */ 1303 /* hold DC in reset across the SBR */ 1304 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1305 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1306 /* save firmware control across the SBR */ 1307 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1308 1309 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1310 arm_gasket_logic(dd); 1311 1312 /* 1313 * step 6: quiesce PCIe link 1314 * The chip has already been reset, so there will be no traffic 1315 * from the chip. Linux has no easy way to enforce that it will 1316 * not try to access the device, so we just need to hope it doesn't 1317 * do it while we are doing the reset. 1318 */ 1319 1320 /* 1321 * step 7: initiate the secondary bus reset (SBR) 1322 * step 8: hardware brings the links back up 1323 * step 9: wait for link speed transition to be complete 1324 */ 1325 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1326 ret = trigger_sbr(dd); 1327 if (ret) 1328 goto done; 1329 1330 /* step 10: decide what to do next */ 1331 1332 /* check if we can read PCI space */ 1333 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1334 if (ret) { 1335 dd_dev_info(dd, 1336 "%s: read of VendorID failed after SBR, err %d\n", 1337 __func__, ret); 1338 return_error = 1; 1339 goto done; 1340 } 1341 if (vendor == 0xffff) { 1342 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1343 return_error = 1; 1344 ret = -EIO; 1345 goto done; 1346 } 1347 1348 /* restore PCI space registers we know were reset */ 1349 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1350 ret = restore_pci_variables(dd); 1351 if (ret) { 1352 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 1353 __func__); 1354 return_error = 1; 1355 goto done; 1356 } 1357 1358 /* restore firmware control */ 1359 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1360 1361 /* 1362 * Check the gasket block status. 1363 * 1364 * This is the first CSR read after the SBR. If the read returns 1365 * all 1s (fails), the link did not make it back. 1366 * 1367 * Once we're sure we can read and write, clear the DC reset after 1368 * the SBR. Then check for any per-lane errors. Then look over 1369 * the status. 1370 */ 1371 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1372 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1373 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1374 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1375 return_error = 1; 1376 ret = -ENOSYS; 1377 goto done; 1378 } 1379 1380 /* clear the DC reset */ 1381 write_csr(dd, CCE_DC_CTRL, 0); 1382 1383 /* Set the LED off */ 1384 setextled(dd, 0); 1385 1386 /* check for any per-lane errors */ 1387 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1388 if (ret) { 1389 dd_dev_err(dd, "Unable to read from PCI config\n"); 1390 return_error = 1; 1391 goto done; 1392 } 1393 1394 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1395 1396 /* extract status, look for our HFI */ 1397 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1398 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1399 if ((status & (1 << dd->hfi1_id)) == 0) { 1400 dd_dev_err(dd, 1401 "%s: gasket status 0x%x, expecting 0x%x\n", 1402 __func__, status, 1 << dd->hfi1_id); 1403 ret = -EIO; 1404 goto done; 1405 } 1406 1407 /* extract error */ 1408 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1409 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1410 if (err) { 1411 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1412 ret = -EIO; 1413 goto done; 1414 } 1415 1416 /* update our link information cache */ 1417 update_lbus_info(dd); 1418 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1419 dd->lbus_info); 1420 1421 if (dd->lbus_speed != target_speed || 1422 dd->lbus_width < target_width) { /* not target */ 1423 /* maybe retry */ 1424 do_retry = retry_count < pcie_retry; 1425 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n", 1426 do_retry ? ", retrying" : ""); 1427 retry_count++; 1428 if (do_retry) { 1429 msleep(100); /* allow time to settle */ 1430 goto retry; 1431 } 1432 ret = -EIO; 1433 } 1434 1435 done: 1436 if (therm) { 1437 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1438 msleep(100); 1439 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1440 __func__); 1441 } 1442 release_chip_resource(dd, CR_SBUS); 1443 done_no_mutex: 1444 /* return no error if it is OK to be at current speed */ 1445 if (ret && !return_error) { 1446 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1447 ret = 0; 1448 } 1449 1450 dd_dev_info(dd, "%s: done\n", __func__); 1451 return ret; 1452 } 1453