1 /* 2 * Copyright(c) 2015, 2016 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* link speed vector for Gen3 speed - not in Linux headers */ 60 #define GEN1_SPEED_VECTOR 0x1 61 #define GEN2_SPEED_VECTOR 0x2 62 #define GEN3_SPEED_VECTOR 0x3 63 64 /* 65 * This file contains PCIe utility routines. 66 */ 67 68 /* 69 * Code to adjust PCIe capabilities. 70 */ 71 static void tune_pcie_caps(struct hfi1_devdata *); 72 73 /* 74 * Do all the common PCIe setup and initialization. 75 * devdata is not yet allocated, and is not allocated until after this 76 * routine returns success. Therefore dd_dev_err() can't be used for error 77 * printing. 78 */ 79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 80 { 81 int ret; 82 83 ret = pci_enable_device(pdev); 84 if (ret) { 85 /* 86 * This can happen (in theory) iff: 87 * We did a chip reset, and then failed to reprogram the 88 * BAR, or the chip reset due to an internal error. We then 89 * unloaded the driver and reloaded it. 90 * 91 * Both reset cases set the BAR back to initial state. For 92 * the latter case, the AER sticky error bit at offset 0x718 93 * should be set, but the Linux kernel doesn't yet know 94 * about that, it appears. If the original BAR was retained 95 * in the kernel data structures, this may be OK. 96 */ 97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", 98 -ret); 99 goto done; 100 } 101 102 ret = pci_request_regions(pdev, DRIVER_NAME); 103 if (ret) { 104 hfi1_early_err(&pdev->dev, 105 "pci_request_regions fails: err %d\n", -ret); 106 goto bail; 107 } 108 109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 110 if (ret) { 111 /* 112 * If the 64 bit setup fails, try 32 bit. Some systems 113 * do not setup 64 bit maps on systems with 2GB or less 114 * memory installed. 115 */ 116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 117 if (ret) { 118 hfi1_early_err(&pdev->dev, 119 "Unable to set DMA mask: %d\n", ret); 120 goto bail; 121 } 122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 123 } else { 124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 125 } 126 if (ret) { 127 hfi1_early_err(&pdev->dev, 128 "Unable to set DMA consistent mask: %d\n", ret); 129 goto bail; 130 } 131 132 pci_set_master(pdev); 133 (void)pci_enable_pcie_error_reporting(pdev); 134 goto done; 135 136 bail: 137 hfi1_pcie_cleanup(pdev); 138 done: 139 return ret; 140 } 141 142 /* 143 * Clean what was done in hfi1_pcie_init() 144 */ 145 void hfi1_pcie_cleanup(struct pci_dev *pdev) 146 { 147 pci_disable_device(pdev); 148 /* 149 * Release regions should be called after the disable. OK to 150 * call if request regions has not been called or failed. 151 */ 152 pci_release_regions(pdev); 153 } 154 155 /* 156 * Do remaining PCIe setup, once dd is allocated, and save away 157 * fields required to re-initialize after a chip reset, or for 158 * various other purposes 159 */ 160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 161 { 162 unsigned long len; 163 resource_size_t addr; 164 165 dd->pcidev = pdev; 166 pci_set_drvdata(pdev, dd); 167 168 addr = pci_resource_start(pdev, 0); 169 len = pci_resource_len(pdev, 0); 170 171 /* 172 * The TXE PIO buffers are at the tail end of the chip space. 173 * Cut them off and map them separately. 174 */ 175 176 /* sanity check vs expectations */ 177 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 178 dd_dev_err(dd, "chip PIO range does not match\n"); 179 return -EINVAL; 180 } 181 182 dd->kregbase = ioremap_nocache(addr, TXE_PIO_SEND); 183 if (!dd->kregbase) 184 return -ENOMEM; 185 186 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 187 if (!dd->piobase) { 188 iounmap(dd->kregbase); 189 return -ENOMEM; 190 } 191 192 dd->flags |= HFI1_PRESENT; /* now register routines work */ 193 194 dd->kregend = dd->kregbase + TXE_PIO_SEND; 195 dd->physaddr = addr; /* used for io_remap, etc. */ 196 197 /* 198 * Re-map the chip's RcvArray as write-combining to allow us 199 * to write an entire cacheline worth of entries in one shot. 200 * If this re-map fails, just continue - the RcvArray programming 201 * function will handle both cases. 202 */ 203 dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); 204 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 205 dd->chip_rcv_array_count * 8); 206 dd_dev_info(dd, "WC Remapped RcvArray: %p\n", dd->rcvarray_wc); 207 /* 208 * Save BARs and command to rewrite after device reset. 209 */ 210 dd->pcibar0 = addr; 211 dd->pcibar1 = addr >> 32; 212 pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 213 pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 214 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl); 215 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, &dd->pcie_lnkctl); 216 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 217 &dd->pcie_devctl2); 218 pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 219 pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, &dd->pci_lnkctl3); 220 pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2); 221 222 return 0; 223 } 224 225 /* 226 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 227 * to releasing the dd memory. 228 * Void because all of the core pcie cleanup functions are void. 229 */ 230 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 231 { 232 u64 __iomem *base = (void __iomem *)dd->kregbase; 233 234 dd->flags &= ~HFI1_PRESENT; 235 dd->kregbase = NULL; 236 iounmap(base); 237 if (dd->rcvarray_wc) 238 iounmap(dd->rcvarray_wc); 239 if (dd->piobase) 240 iounmap(dd->piobase); 241 } 242 243 /* 244 * Do a Function Level Reset (FLR) on the device. 245 * Based on static function drivers/pci/pci.c:pcie_flr(). 246 */ 247 void hfi1_pcie_flr(struct hfi1_devdata *dd) 248 { 249 int i; 250 u16 status; 251 252 /* no need to check for the capability - we know the device has it */ 253 254 /* wait for Transaction Pending bit to clear, at most a few ms */ 255 for (i = 0; i < 4; i++) { 256 if (i) 257 msleep((1 << (i - 1)) * 100); 258 259 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVSTA, &status); 260 if (!(status & PCI_EXP_DEVSTA_TRPND)) 261 goto clear; 262 } 263 264 dd_dev_err(dd, "Transaction Pending bit is not clearing, proceeding with reset anyway\n"); 265 266 clear: 267 pcie_capability_set_word(dd->pcidev, PCI_EXP_DEVCTL, 268 PCI_EXP_DEVCTL_BCR_FLR); 269 /* PCIe spec requires the function to be back within 100ms */ 270 msleep(100); 271 } 272 273 static void msix_setup(struct hfi1_devdata *dd, int pos, u32 *msixcnt, 274 struct hfi1_msix_entry *hfi1_msix_entry) 275 { 276 int ret; 277 int nvec = *msixcnt; 278 struct msix_entry *msix_entry; 279 int i; 280 281 /* 282 * We can't pass hfi1_msix_entry array to msix_setup 283 * so use a dummy msix_entry array and copy the allocated 284 * irq back to the hfi1_msix_entry array. 285 */ 286 msix_entry = kmalloc_array(nvec, sizeof(*msix_entry), GFP_KERNEL); 287 if (!msix_entry) { 288 ret = -ENOMEM; 289 goto do_intx; 290 } 291 292 for (i = 0; i < nvec; i++) 293 msix_entry[i] = hfi1_msix_entry[i].msix; 294 295 ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec); 296 if (ret < 0) 297 goto free_msix_entry; 298 nvec = ret; 299 300 for (i = 0; i < nvec; i++) 301 hfi1_msix_entry[i].msix = msix_entry[i]; 302 303 kfree(msix_entry); 304 *msixcnt = nvec; 305 return; 306 307 free_msix_entry: 308 kfree(msix_entry); 309 310 do_intx: 311 dd_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, falling back to INTx\n", 312 nvec, ret); 313 *msixcnt = 0; 314 hfi1_enable_intx(dd->pcidev); 315 } 316 317 /* return the PCIe link speed from the given link status */ 318 static u32 extract_speed(u16 linkstat) 319 { 320 u32 speed; 321 322 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 323 default: /* not defined, assume Gen1 */ 324 case PCI_EXP_LNKSTA_CLS_2_5GB: 325 speed = 2500; /* Gen 1, 2.5GHz */ 326 break; 327 case PCI_EXP_LNKSTA_CLS_5_0GB: 328 speed = 5000; /* Gen 2, 5GHz */ 329 break; 330 case GEN3_SPEED_VECTOR: 331 speed = 8000; /* Gen 3, 8GHz */ 332 break; 333 } 334 return speed; 335 } 336 337 /* return the PCIe link speed from the given link status */ 338 static u32 extract_width(u16 linkstat) 339 { 340 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 341 } 342 343 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 344 static void update_lbus_info(struct hfi1_devdata *dd) 345 { 346 u16 linkstat; 347 348 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 349 dd->lbus_width = extract_width(linkstat); 350 dd->lbus_speed = extract_speed(linkstat); 351 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 352 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 353 } 354 355 /* 356 * Read in the current PCIe link width and speed. Find if the link is 357 * Gen3 capable. 358 */ 359 int pcie_speeds(struct hfi1_devdata *dd) 360 { 361 u32 linkcap; 362 struct pci_dev *parent = dd->pcidev->bus->self; 363 364 if (!pci_is_pcie(dd->pcidev)) { 365 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 366 return -EINVAL; 367 } 368 369 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 370 dd->link_gen3_capable = 1; 371 372 pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 373 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) { 374 dd_dev_info(dd, 375 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 376 linkcap & PCI_EXP_LNKCAP_SLS); 377 dd->link_gen3_capable = 0; 378 } 379 380 /* 381 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 382 */ 383 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 384 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 385 dd->link_gen3_capable = 0; 386 } 387 388 /* obtain the link width and current speed */ 389 update_lbus_info(dd); 390 391 dd_dev_info(dd, "%s\n", dd->lbus_info); 392 393 return 0; 394 } 395 396 /* 397 * Returns in *nent: 398 * - actual number of interrupts allocated 399 * - 0 if fell back to INTx. 400 */ 401 void request_msix(struct hfi1_devdata *dd, u32 *nent, 402 struct hfi1_msix_entry *entry) 403 { 404 int pos; 405 406 pos = dd->pcidev->msix_cap; 407 if (*nent && pos) { 408 msix_setup(dd, pos, nent, entry); 409 /* did it, either MSI-X or INTx */ 410 } else { 411 *nent = 0; 412 hfi1_enable_intx(dd->pcidev); 413 } 414 415 tune_pcie_caps(dd); 416 } 417 418 void hfi1_enable_intx(struct pci_dev *pdev) 419 { 420 /* first, turn on INTx */ 421 pci_intx(pdev, 1); 422 /* then turn off MSI-X */ 423 pci_disable_msix(pdev); 424 } 425 426 /* restore command and BARs after a reset has wiped them out */ 427 void restore_pci_variables(struct hfi1_devdata *dd) 428 { 429 pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 430 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, dd->pcibar0); 431 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, dd->pcibar1); 432 pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 433 pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, dd->pcie_devctl); 434 pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, dd->pcie_lnkctl); 435 pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 436 dd->pcie_devctl2); 437 pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 438 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, dd->pci_lnkctl3); 439 pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2); 440 } 441 442 /* 443 * BIOS may not set PCIe bus-utilization parameters for best performance. 444 * Check and optionally adjust them to maximize our throughput. 445 */ 446 static int hfi1_pcie_caps; 447 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); 448 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 449 450 uint aspm_mode = ASPM_MODE_DISABLED; 451 module_param_named(aspm, aspm_mode, uint, S_IRUGO); 452 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); 453 454 static void tune_pcie_caps(struct hfi1_devdata *dd) 455 { 456 struct pci_dev *parent; 457 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 458 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 459 460 /* 461 * Turn on extended tags in DevCtl in case the BIOS has turned it off 462 * to improve WFR SDMA bandwidth 463 */ 464 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); 465 if (!(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 466 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 467 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 468 pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl); 469 } 470 /* Find out supported and configured values for parent (root) */ 471 parent = dd->pcidev->bus->self; 472 /* 473 * The driver cannot perform the tuning if it does not have 474 * access to the upstream component. 475 */ 476 if (!parent) 477 return; 478 if (!pci_is_root_bus(parent->bus)) { 479 dd_dev_info(dd, "Parent not root\n"); 480 return; 481 } 482 483 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) 484 return; 485 rc_mpss = parent->pcie_mpss; 486 rc_mps = ffs(pcie_get_mps(parent)) - 8; 487 /* Find out supported and configured values for endpoint (us) */ 488 ep_mpss = dd->pcidev->pcie_mpss; 489 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 490 491 /* Find max payload supported by root, endpoint */ 492 if (rc_mpss > ep_mpss) 493 rc_mpss = ep_mpss; 494 495 /* If Supported greater than limit in module param, limit it */ 496 if (rc_mpss > (hfi1_pcie_caps & 7)) 497 rc_mpss = hfi1_pcie_caps & 7; 498 /* If less than (allowed, supported), bump root payload */ 499 if (rc_mpss > rc_mps) { 500 rc_mps = rc_mpss; 501 pcie_set_mps(parent, 128 << rc_mps); 502 } 503 /* If less than (allowed, supported), bump endpoint payload */ 504 if (rc_mpss > ep_mps) { 505 ep_mps = rc_mpss; 506 pcie_set_mps(dd->pcidev, 128 << ep_mps); 507 } 508 509 /* 510 * Now the Read Request size. 511 * No field for max supported, but PCIe spec limits it to 4096, 512 * which is code '5' (log2(4096) - 7) 513 */ 514 max_mrrs = 5; 515 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 516 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 517 518 max_mrrs = 128 << max_mrrs; 519 rc_mrrs = pcie_get_readrq(parent); 520 ep_mrrs = pcie_get_readrq(dd->pcidev); 521 522 if (max_mrrs > rc_mrrs) { 523 rc_mrrs = max_mrrs; 524 pcie_set_readrq(parent, rc_mrrs); 525 } 526 if (max_mrrs > ep_mrrs) { 527 ep_mrrs = max_mrrs; 528 pcie_set_readrq(dd->pcidev, ep_mrrs); 529 } 530 } 531 532 /* End of PCIe capability tuning */ 533 534 /* 535 * From here through hfi1_pci_err_handler definition is invoked via 536 * PCI error infrastructure, registered via pci 537 */ 538 static pci_ers_result_t 539 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 540 { 541 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 542 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 543 544 switch (state) { 545 case pci_channel_io_normal: 546 dd_dev_info(dd, "State Normal, ignoring\n"); 547 break; 548 549 case pci_channel_io_frozen: 550 dd_dev_info(dd, "State Frozen, requesting reset\n"); 551 pci_disable_device(pdev); 552 ret = PCI_ERS_RESULT_NEED_RESET; 553 break; 554 555 case pci_channel_io_perm_failure: 556 if (dd) { 557 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 558 /* no more register accesses! */ 559 dd->flags &= ~HFI1_PRESENT; 560 hfi1_disable_after_error(dd); 561 } 562 /* else early, or other problem */ 563 ret = PCI_ERS_RESULT_DISCONNECT; 564 break; 565 566 default: /* shouldn't happen */ 567 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 568 state); 569 break; 570 } 571 return ret; 572 } 573 574 static pci_ers_result_t 575 pci_mmio_enabled(struct pci_dev *pdev) 576 { 577 u64 words = 0U; 578 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 579 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 580 581 if (dd && dd->pport) { 582 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 583 if (words == ~0ULL) 584 ret = PCI_ERS_RESULT_NEED_RESET; 585 dd_dev_info(dd, 586 "HFI1 mmio_enabled function called, read wordscntr %Lx, returning %d\n", 587 words, ret); 588 } 589 return ret; 590 } 591 592 static pci_ers_result_t 593 pci_slot_reset(struct pci_dev *pdev) 594 { 595 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 596 597 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 598 return PCI_ERS_RESULT_CAN_RECOVER; 599 } 600 601 static pci_ers_result_t 602 pci_link_reset(struct pci_dev *pdev) 603 { 604 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 605 606 dd_dev_info(dd, "HFI1 link_reset function called, ignored\n"); 607 return PCI_ERS_RESULT_CAN_RECOVER; 608 } 609 610 static void 611 pci_resume(struct pci_dev *pdev) 612 { 613 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 614 615 dd_dev_info(dd, "HFI1 resume function called\n"); 616 pci_cleanup_aer_uncorrect_error_status(pdev); 617 /* 618 * Running jobs will fail, since it's asynchronous 619 * unlike sysfs-requested reset. Better than 620 * doing nothing. 621 */ 622 hfi1_init(dd, 1); /* same as re-init after reset */ 623 } 624 625 const struct pci_error_handlers hfi1_pci_err_handler = { 626 .error_detected = pci_error_detected, 627 .mmio_enabled = pci_mmio_enabled, 628 .link_reset = pci_link_reset, 629 .slot_reset = pci_slot_reset, 630 .resume = pci_resume, 631 }; 632 633 /*============================================================================*/ 634 /* PCIe Gen3 support */ 635 636 /* 637 * This code is separated out because it is expected to be removed in the 638 * final shipping product. If not, then it will be revisited and items 639 * will be moved to more standard locations. 640 */ 641 642 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 643 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 644 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 645 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 646 647 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 648 #define DL_ERR_NONE 0x0 /* no error */ 649 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 650 /* or response data */ 651 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 652 #define DL_ERR_SECURITY 0x3 /* security check failed */ 653 #define DL_ERR_SBUS 0x4 /* SBus status error */ 654 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 655 656 /* gasket block secondary bus reset delay */ 657 #define SBR_DELAY_US 200000 /* 200ms */ 658 659 /* mask for PCIe capability register lnkctl2 target link speed */ 660 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf 661 662 static uint pcie_target = 3; 663 module_param(pcie_target, uint, S_IRUGO); 664 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 665 666 static uint pcie_force; 667 module_param(pcie_force, uint, S_IRUGO); 668 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 669 670 static uint pcie_retry = 5; 671 module_param(pcie_retry, uint, S_IRUGO); 672 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 673 674 #define UNSET_PSET 255 675 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 676 #define DEFAULT_MCP_PSET 4 /* MCP HFI */ 677 static uint pcie_pset = UNSET_PSET; 678 module_param(pcie_pset, uint, S_IRUGO); 679 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 680 681 static uint pcie_ctle = 1; /* discrete on, integrated off */ 682 module_param(pcie_ctle, uint, S_IRUGO); 683 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 684 685 /* equalization columns */ 686 #define PREC 0 687 #define ATTN 1 688 #define POST 2 689 690 /* discrete silicon preliminary equalization values */ 691 static const u8 discrete_preliminary_eq[11][3] = { 692 /* prec attn post */ 693 { 0x00, 0x00, 0x12 }, /* p0 */ 694 { 0x00, 0x00, 0x0c }, /* p1 */ 695 { 0x00, 0x00, 0x0f }, /* p2 */ 696 { 0x00, 0x00, 0x09 }, /* p3 */ 697 { 0x00, 0x00, 0x00 }, /* p4 */ 698 { 0x06, 0x00, 0x00 }, /* p5 */ 699 { 0x09, 0x00, 0x00 }, /* p6 */ 700 { 0x06, 0x00, 0x0f }, /* p7 */ 701 { 0x09, 0x00, 0x09 }, /* p8 */ 702 { 0x0c, 0x00, 0x00 }, /* p9 */ 703 { 0x00, 0x00, 0x18 }, /* p10 */ 704 }; 705 706 /* integrated silicon preliminary equalization values */ 707 static const u8 integrated_preliminary_eq[11][3] = { 708 /* prec attn post */ 709 { 0x00, 0x1e, 0x07 }, /* p0 */ 710 { 0x00, 0x1e, 0x05 }, /* p1 */ 711 { 0x00, 0x1e, 0x06 }, /* p2 */ 712 { 0x00, 0x1e, 0x04 }, /* p3 */ 713 { 0x00, 0x1e, 0x00 }, /* p4 */ 714 { 0x03, 0x1e, 0x00 }, /* p5 */ 715 { 0x04, 0x1e, 0x00 }, /* p6 */ 716 { 0x03, 0x1e, 0x06 }, /* p7 */ 717 { 0x03, 0x1e, 0x04 }, /* p8 */ 718 { 0x05, 0x1e, 0x00 }, /* p9 */ 719 { 0x00, 0x1e, 0x0a }, /* p10 */ 720 }; 721 722 static const u8 discrete_ctle_tunings[11][4] = { 723 /* DC LF HF BW */ 724 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 725 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 726 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 727 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 728 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 729 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 730 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 731 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 732 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 733 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 734 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 735 }; 736 737 static const u8 integrated_ctle_tunings[11][4] = { 738 /* DC LF HF BW */ 739 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 740 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 741 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 742 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 743 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 744 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 745 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 746 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 747 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 748 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 749 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 750 }; 751 752 /* helper to format the value to write to hardware */ 753 #define eq_value(pre, curr, post) \ 754 ((((u32)(pre)) << \ 755 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 756 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 757 | (((u32)(post)) << \ 758 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 759 760 /* 761 * Load the given EQ preset table into the PCIe hardware. 762 */ 763 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 764 u8 div) 765 { 766 struct pci_dev *pdev = dd->pcidev; 767 u32 hit_error = 0; 768 u32 violation; 769 u32 i; 770 u8 c_minus1, c0, c_plus1; 771 772 for (i = 0; i < 11; i++) { 773 /* set index */ 774 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 775 /* write the value */ 776 c_minus1 = eq[i][PREC] / div; 777 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 778 c_plus1 = eq[i][POST] / div; 779 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 780 eq_value(c_minus1, c0, c_plus1)); 781 /* check if these coefficients violate EQ rules */ 782 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL105, 783 &violation); 784 if (violation 785 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 786 if (hit_error == 0) { 787 dd_dev_err(dd, 788 "Gen3 EQ Table Coefficient rule violations\n"); 789 dd_dev_err(dd, " prec attn post\n"); 790 } 791 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 792 i, (u32)eq[i][0], (u32)eq[i][1], 793 (u32)eq[i][2]); 794 dd_dev_err(dd, " %02x %02x %02x\n", 795 (u32)c_minus1, (u32)c0, (u32)c_plus1); 796 hit_error = 1; 797 } 798 } 799 if (hit_error) 800 return -EINVAL; 801 return 0; 802 } 803 804 /* 805 * Steps to be done after the PCIe firmware is downloaded and 806 * before the SBR for the Pcie Gen3. 807 * The SBus resource is already being held. 808 */ 809 static void pcie_post_steps(struct hfi1_devdata *dd) 810 { 811 int i; 812 813 set_sbus_fast_mode(dd); 814 /* 815 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 816 * This avoids a spurious framing error that can otherwise be 817 * generated by the MAC layer. 818 * 819 * Use individual addresses since no broadcast is set up. 820 */ 821 for (i = 0; i < NUM_PCIE_SERDES; i++) { 822 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 823 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 824 } 825 826 clear_sbus_fast_mode(dd); 827 } 828 829 /* 830 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 831 * 832 * Based on pci_parent_bus_reset() which is not exported by the 833 * kernel core. 834 */ 835 static int trigger_sbr(struct hfi1_devdata *dd) 836 { 837 struct pci_dev *dev = dd->pcidev; 838 struct pci_dev *pdev; 839 840 /* need a parent */ 841 if (!dev->bus->self) { 842 dd_dev_err(dd, "%s: no parent device\n", __func__); 843 return -ENOTTY; 844 } 845 846 /* should not be anyone else on the bus */ 847 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 848 if (pdev != dev) { 849 dd_dev_err(dd, 850 "%s: another device is on the same bus\n", 851 __func__); 852 return -ENOTTY; 853 } 854 855 /* 856 * A secondary bus reset (SBR) issues a hot reset to our device. 857 * The following routine does a 1s wait after the reset is dropped 858 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - 859 * Conventional Reset, paragraph 3, line 35 also says that a 1s 860 * delay after a reset is required. Per spec requirements, 861 * the link is either working or not after that point. 862 */ 863 pci_reset_bridge_secondary_bus(dev->bus->self); 864 865 return 0; 866 } 867 868 /* 869 * Write the given gasket interrupt register. 870 */ 871 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 872 u16 code, u16 data) 873 { 874 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 875 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 876 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 877 } 878 879 /* 880 * Tell the gasket logic how to react to the reset. 881 */ 882 static void arm_gasket_logic(struct hfi1_devdata *dd) 883 { 884 u64 reg; 885 886 reg = (((u64)1 << dd->hfi1_id) << 887 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 888 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 889 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 890 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 891 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 892 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 893 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 894 /* read back to push the write */ 895 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 896 } 897 898 /* 899 * CCE_PCIE_CTRL long name helpers 900 * We redefine these shorter macros to use in the code while leaving 901 * chip_registers.h to be autogenerated from the hardware spec. 902 */ 903 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 904 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 905 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 906 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 907 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 908 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 909 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 910 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 911 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 912 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 913 914 /* 915 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 916 */ 917 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 918 { 919 u64 pcie_ctrl; 920 u64 xmt_margin; 921 u64 xmt_margin_oe; 922 u64 lane_delay; 923 u64 lane_bundle; 924 925 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 926 927 /* 928 * For Discrete, use full-swing. 929 * - PCIe TX defaults to full-swing. 930 * Leave this register as default. 931 * For Integrated, use half-swing 932 * - Copy xmt_margin and xmt_margin_oe 933 * from Gen1/Gen2 to Gen3. 934 */ 935 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 936 /* extract initial fields */ 937 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 938 & MARGIN_GEN1_GEN2_MASK; 939 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 940 & MARGIN_G1_G2_OVERWRITE_MASK; 941 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 942 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 943 & LANE_BUNDLE_MASK; 944 945 /* 946 * For A0, EFUSE values are not set. Override with the 947 * correct values. 948 */ 949 if (is_ax(dd)) { 950 /* 951 * xmt_margin and OverwiteEnabel should be the 952 * same for Gen1/Gen2 and Gen3 953 */ 954 xmt_margin = 0x5; 955 xmt_margin_oe = 0x1; 956 lane_delay = 0xF; /* Delay 240ns. */ 957 lane_bundle = 0x0; /* Set to 1 lane. */ 958 } 959 960 /* overwrite existing values */ 961 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 962 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 963 | (xmt_margin << MARGIN_SHIFT) 964 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 965 | (lane_delay << LANE_DELAY_SHIFT) 966 | (lane_bundle << LANE_BUNDLE_SHIFT); 967 968 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 969 } 970 971 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 972 fname, pcie_ctrl); 973 } 974 975 /* 976 * Do all the steps needed to transition the PCIe link to Gen3 speed. 977 */ 978 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 979 { 980 struct pci_dev *parent = dd->pcidev->bus->self; 981 u64 fw_ctrl; 982 u64 reg, therm; 983 u32 reg32, fs, lf; 984 u32 status, err; 985 int ret; 986 int do_retry, retry_count = 0; 987 int intnum = 0; 988 uint default_pset; 989 u16 target_vector, target_speed; 990 u16 lnkctl2, vendor; 991 u8 div; 992 const u8 (*eq)[3]; 993 const u8 (*ctle_tunings)[4]; 994 uint static_ctle_mode; 995 int return_error = 0; 996 997 /* PCIe Gen3 is for the ASIC only */ 998 if (dd->icode != ICODE_RTL_SILICON) 999 return 0; 1000 1001 if (pcie_target == 1) { /* target Gen1 */ 1002 target_vector = GEN1_SPEED_VECTOR; 1003 target_speed = 2500; 1004 } else if (pcie_target == 2) { /* target Gen2 */ 1005 target_vector = GEN2_SPEED_VECTOR; 1006 target_speed = 5000; 1007 } else if (pcie_target == 3) { /* target Gen3 */ 1008 target_vector = GEN3_SPEED_VECTOR; 1009 target_speed = 8000; 1010 } else { 1011 /* off or invalid target - skip */ 1012 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 1013 return 0; 1014 } 1015 1016 /* if already at target speed, done (unless forced) */ 1017 if (dd->lbus_speed == target_speed) { 1018 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 1019 pcie_target, 1020 pcie_force ? "re-doing anyway" : "skipping"); 1021 if (!pcie_force) 1022 return 0; 1023 } 1024 1025 /* 1026 * The driver cannot do the transition if it has no access to the 1027 * upstream component 1028 */ 1029 if (!parent) { 1030 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 1031 __func__); 1032 return 0; 1033 } 1034 1035 /* 1036 * Do the Gen3 transition. Steps are those of the PCIe Gen3 1037 * recipe. 1038 */ 1039 1040 /* step 1: pcie link working in gen1/gen2 */ 1041 1042 /* step 2: if either side is not capable of Gen3, done */ 1043 if (pcie_target == 3 && !dd->link_gen3_capable) { 1044 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1045 ret = -ENOSYS; 1046 goto done_no_mutex; 1047 } 1048 1049 /* hold the SBus resource across the firmware download and SBR */ 1050 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1051 if (ret) { 1052 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1053 __func__); 1054 return ret; 1055 } 1056 1057 /* make sure thermal polling is not causing interrupts */ 1058 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1059 if (therm) { 1060 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1061 msleep(100); 1062 dd_dev_info(dd, "%s: Disabled therm polling\n", 1063 __func__); 1064 } 1065 1066 retry: 1067 /* the SBus download will reset the spico for thermal */ 1068 1069 /* step 3: download SBus Master firmware */ 1070 /* step 4: download PCIe Gen3 SerDes firmware */ 1071 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1072 ret = load_pcie_firmware(dd); 1073 if (ret) { 1074 /* do not proceed if the firmware cannot be downloaded */ 1075 return_error = 1; 1076 goto done; 1077 } 1078 1079 /* step 5: set up device parameter settings */ 1080 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1081 1082 /* 1083 * PcieCfgSpcie1 - Link Control 3 1084 * Leave at reset value. No need to set PerfEq - link equalization 1085 * will be performed automatically after the SBR when the target 1086 * speed is 8GT/s. 1087 */ 1088 1089 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1090 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1091 1092 /* step 5a: Set Synopsys Port Logic registers */ 1093 1094 /* 1095 * PcieCfgRegPl2 - Port Force Link 1096 * 1097 * Set the low power field to 0x10 to avoid unnecessary power 1098 * management messages. All other fields are zero. 1099 */ 1100 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1101 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1102 1103 /* 1104 * PcieCfgRegPl100 - Gen3 Control 1105 * 1106 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1107 * turn on PcieCfgRegPl100.EqEieosCnt 1108 * Everything else zero. 1109 */ 1110 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1111 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1112 1113 /* 1114 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1115 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1116 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1117 * PcieCfgRegPl105 - Gen3 EQ Status 1118 * 1119 * Give initial EQ settings. 1120 */ 1121 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1122 /* 1000mV, FS=24, LF = 8 */ 1123 fs = 24; 1124 lf = 8; 1125 div = 3; 1126 eq = discrete_preliminary_eq; 1127 default_pset = DEFAULT_DISCRETE_PSET; 1128 ctle_tunings = discrete_ctle_tunings; 1129 /* bit 0 - discrete on/off */ 1130 static_ctle_mode = pcie_ctle & 0x1; 1131 } else { 1132 /* 400mV, FS=29, LF = 9 */ 1133 fs = 29; 1134 lf = 9; 1135 div = 1; 1136 eq = integrated_preliminary_eq; 1137 default_pset = DEFAULT_MCP_PSET; 1138 ctle_tunings = integrated_ctle_tunings; 1139 /* bit 1 - integrated on/off */ 1140 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1141 } 1142 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1143 (fs << 1144 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1145 (lf << 1146 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1147 ret = load_eq_table(dd, eq, fs, div); 1148 if (ret) 1149 goto done; 1150 1151 /* 1152 * PcieCfgRegPl106 - Gen3 EQ Control 1153 * 1154 * Set Gen3EqPsetReqVec, leave other fields 0. 1155 */ 1156 if (pcie_pset == UNSET_PSET) 1157 pcie_pset = default_pset; 1158 if (pcie_pset > 10) { /* valid range is 0-10, inclusive */ 1159 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1160 __func__, pcie_pset, default_pset); 1161 pcie_pset = default_pset; 1162 } 1163 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset); 1164 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1165 ((1 << pcie_pset) << 1166 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1167 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1168 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1169 1170 /* 1171 * step 5b: Do post firmware download steps via SBus 1172 */ 1173 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1174 pcie_post_steps(dd); 1175 1176 /* 1177 * step 5c: Program gasket interrupts 1178 */ 1179 /* set the Rx Bit Rate to REFCLK ratio */ 1180 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1181 /* disable pCal for PCIe Gen3 RX equalization */ 1182 /* select adaptive or static CTLE */ 1183 write_gasket_interrupt(dd, intnum++, 0x0026, 1184 0x5b01 | (static_ctle_mode << 3)); 1185 /* 1186 * Enable iCal for PCIe Gen3 RX equalization, and set which 1187 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1188 */ 1189 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1190 1191 if (static_ctle_mode) { 1192 /* apply static CTLE tunings */ 1193 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1194 1195 pcie_dc = ctle_tunings[pcie_pset][0]; 1196 pcie_lf = ctle_tunings[pcie_pset][1]; 1197 pcie_hf = ctle_tunings[pcie_pset][2]; 1198 pcie_bw = ctle_tunings[pcie_pset][3]; 1199 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1200 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1201 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1202 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1203 } 1204 1205 /* terminate list */ 1206 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1207 1208 /* 1209 * step 5d: program XMT margin 1210 */ 1211 write_xmt_margin(dd, __func__); 1212 1213 /* 1214 * step 5e: disable active state power management (ASPM). It 1215 * will be enabled if required later 1216 */ 1217 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1218 aspm_hw_disable_l1(dd); 1219 1220 /* 1221 * step 5f: clear DirectSpeedChange 1222 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1223 * change in the speed target from starting before we are ready. 1224 * This field defaults to 0 and we are not changing it, so nothing 1225 * needs to be done. 1226 */ 1227 1228 /* step 5g: Set target link speed */ 1229 /* 1230 * Set target link speed to be target on both device and parent. 1231 * On setting the parent: Some system BIOSs "helpfully" set the 1232 * parent target speed to Gen2 to match the ASIC's initial speed. 1233 * We can set the target Gen3 because we have already checked 1234 * that it is Gen3 capable earlier. 1235 */ 1236 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1237 pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1238 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1239 (u32)lnkctl2); 1240 /* only write to parent if target is not as high as ours */ 1241 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) { 1242 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1243 lnkctl2 |= target_vector; 1244 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1245 (u32)lnkctl2); 1246 pcie_capability_write_word(parent, PCI_EXP_LNKCTL2, lnkctl2); 1247 } else { 1248 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1249 } 1250 1251 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1252 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1253 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1254 (u32)lnkctl2); 1255 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1256 lnkctl2 |= target_vector; 1257 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1258 (u32)lnkctl2); 1259 pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1260 1261 /* step 5h: arm gasket logic */ 1262 /* hold DC in reset across the SBR */ 1263 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1264 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1265 /* save firmware control across the SBR */ 1266 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1267 1268 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1269 arm_gasket_logic(dd); 1270 1271 /* 1272 * step 6: quiesce PCIe link 1273 * The chip has already been reset, so there will be no traffic 1274 * from the chip. Linux has no easy way to enforce that it will 1275 * not try to access the device, so we just need to hope it doesn't 1276 * do it while we are doing the reset. 1277 */ 1278 1279 /* 1280 * step 7: initiate the secondary bus reset (SBR) 1281 * step 8: hardware brings the links back up 1282 * step 9: wait for link speed transition to be complete 1283 */ 1284 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1285 ret = trigger_sbr(dd); 1286 if (ret) 1287 goto done; 1288 1289 /* step 10: decide what to do next */ 1290 1291 /* check if we can read PCI space */ 1292 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1293 if (ret) { 1294 dd_dev_info(dd, 1295 "%s: read of VendorID failed after SBR, err %d\n", 1296 __func__, ret); 1297 return_error = 1; 1298 goto done; 1299 } 1300 if (vendor == 0xffff) { 1301 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1302 return_error = 1; 1303 ret = -EIO; 1304 goto done; 1305 } 1306 1307 /* restore PCI space registers we know were reset */ 1308 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1309 restore_pci_variables(dd); 1310 /* restore firmware control */ 1311 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1312 1313 /* 1314 * Check the gasket block status. 1315 * 1316 * This is the first CSR read after the SBR. If the read returns 1317 * all 1s (fails), the link did not make it back. 1318 * 1319 * Once we're sure we can read and write, clear the DC reset after 1320 * the SBR. Then check for any per-lane errors. Then look over 1321 * the status. 1322 */ 1323 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1324 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1325 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1326 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1327 return_error = 1; 1328 ret = -ENOSYS; 1329 goto done; 1330 } 1331 1332 /* clear the DC reset */ 1333 write_csr(dd, CCE_DC_CTRL, 0); 1334 1335 /* Set the LED off */ 1336 setextled(dd, 0); 1337 1338 /* check for any per-lane errors */ 1339 pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1340 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1341 1342 /* extract status, look for our HFI */ 1343 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1344 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1345 if ((status & (1 << dd->hfi1_id)) == 0) { 1346 dd_dev_err(dd, 1347 "%s: gasket status 0x%x, expecting 0x%x\n", 1348 __func__, status, 1 << dd->hfi1_id); 1349 ret = -EIO; 1350 goto done; 1351 } 1352 1353 /* extract error */ 1354 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1355 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1356 if (err) { 1357 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1358 ret = -EIO; 1359 goto done; 1360 } 1361 1362 /* update our link information cache */ 1363 update_lbus_info(dd); 1364 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1365 dd->lbus_info); 1366 1367 if (dd->lbus_speed != target_speed) { /* not target */ 1368 /* maybe retry */ 1369 do_retry = retry_count < pcie_retry; 1370 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", 1371 pcie_target, do_retry ? ", retrying" : ""); 1372 retry_count++; 1373 if (do_retry) { 1374 msleep(100); /* allow time to settle */ 1375 goto retry; 1376 } 1377 ret = -EIO; 1378 } 1379 1380 done: 1381 if (therm) { 1382 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1383 msleep(100); 1384 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1385 __func__); 1386 } 1387 release_chip_resource(dd, CR_SBUS); 1388 done_no_mutex: 1389 /* return no error if it is OK to be at current speed */ 1390 if (ret && !return_error) { 1391 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1392 ret = 0; 1393 } 1394 1395 dd_dev_info(dd, "%s: done\n", __func__); 1396 return ret; 1397 } 1398