1 /* 2 * Copyright(c) 2015, 2016 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* link speed vector for Gen3 speed - not in Linux headers */ 60 #define GEN1_SPEED_VECTOR 0x1 61 #define GEN2_SPEED_VECTOR 0x2 62 #define GEN3_SPEED_VECTOR 0x3 63 64 /* 65 * This file contains PCIe utility routines. 66 */ 67 68 /* 69 * Code to adjust PCIe capabilities. 70 */ 71 static void tune_pcie_caps(struct hfi1_devdata *); 72 73 /* 74 * Do all the common PCIe setup and initialization. 75 * devdata is not yet allocated, and is not allocated until after this 76 * routine returns success. Therefore dd_dev_err() can't be used for error 77 * printing. 78 */ 79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 80 { 81 int ret; 82 83 ret = pci_enable_device(pdev); 84 if (ret) { 85 /* 86 * This can happen (in theory) iff: 87 * We did a chip reset, and then failed to reprogram the 88 * BAR, or the chip reset due to an internal error. We then 89 * unloaded the driver and reloaded it. 90 * 91 * Both reset cases set the BAR back to initial state. For 92 * the latter case, the AER sticky error bit at offset 0x718 93 * should be set, but the Linux kernel doesn't yet know 94 * about that, it appears. If the original BAR was retained 95 * in the kernel data structures, this may be OK. 96 */ 97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", 98 -ret); 99 goto done; 100 } 101 102 ret = pci_request_regions(pdev, DRIVER_NAME); 103 if (ret) { 104 hfi1_early_err(&pdev->dev, 105 "pci_request_regions fails: err %d\n", -ret); 106 goto bail; 107 } 108 109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 110 if (ret) { 111 /* 112 * If the 64 bit setup fails, try 32 bit. Some systems 113 * do not setup 64 bit maps on systems with 2GB or less 114 * memory installed. 115 */ 116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 117 if (ret) { 118 hfi1_early_err(&pdev->dev, 119 "Unable to set DMA mask: %d\n", ret); 120 goto bail; 121 } 122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 123 } else { 124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 125 } 126 if (ret) { 127 hfi1_early_err(&pdev->dev, 128 "Unable to set DMA consistent mask: %d\n", ret); 129 goto bail; 130 } 131 132 pci_set_master(pdev); 133 (void)pci_enable_pcie_error_reporting(pdev); 134 goto done; 135 136 bail: 137 hfi1_pcie_cleanup(pdev); 138 done: 139 return ret; 140 } 141 142 /* 143 * Clean what was done in hfi1_pcie_init() 144 */ 145 void hfi1_pcie_cleanup(struct pci_dev *pdev) 146 { 147 pci_disable_device(pdev); 148 /* 149 * Release regions should be called after the disable. OK to 150 * call if request regions has not been called or failed. 151 */ 152 pci_release_regions(pdev); 153 } 154 155 /* 156 * Do remaining PCIe setup, once dd is allocated, and save away 157 * fields required to re-initialize after a chip reset, or for 158 * various other purposes 159 */ 160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 161 { 162 unsigned long len; 163 resource_size_t addr; 164 165 dd->pcidev = pdev; 166 pci_set_drvdata(pdev, dd); 167 168 addr = pci_resource_start(pdev, 0); 169 len = pci_resource_len(pdev, 0); 170 171 /* 172 * The TXE PIO buffers are at the tail end of the chip space. 173 * Cut them off and map them separately. 174 */ 175 176 /* sanity check vs expectations */ 177 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 178 dd_dev_err(dd, "chip PIO range does not match\n"); 179 return -EINVAL; 180 } 181 182 dd->kregbase = ioremap_nocache(addr, TXE_PIO_SEND); 183 if (!dd->kregbase) 184 return -ENOMEM; 185 186 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 187 if (!dd->piobase) { 188 iounmap(dd->kregbase); 189 return -ENOMEM; 190 } 191 192 dd->flags |= HFI1_PRESENT; /* now register routines work */ 193 194 dd->kregend = dd->kregbase + TXE_PIO_SEND; 195 dd->physaddr = addr; /* used for io_remap, etc. */ 196 197 /* 198 * Re-map the chip's RcvArray as write-combining to allow us 199 * to write an entire cacheline worth of entries in one shot. 200 * If this re-map fails, just continue - the RcvArray programming 201 * function will handle both cases. 202 */ 203 dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); 204 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 205 dd->chip_rcv_array_count * 8); 206 dd_dev_info(dd, "WC Remapped RcvArray: %p\n", dd->rcvarray_wc); 207 /* 208 * Save BARs and command to rewrite after device reset. 209 */ 210 pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, &dd->pcibar0); 211 pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, &dd->pcibar1); 212 pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 213 pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 214 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl); 215 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, &dd->pcie_lnkctl); 216 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 217 &dd->pcie_devctl2); 218 pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 219 pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, &dd->pci_lnkctl3); 220 pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2); 221 222 return 0; 223 } 224 225 /* 226 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 227 * to releasing the dd memory. 228 * Void because all of the core pcie cleanup functions are void. 229 */ 230 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 231 { 232 u64 __iomem *base = (void __iomem *)dd->kregbase; 233 234 dd->flags &= ~HFI1_PRESENT; 235 dd->kregbase = NULL; 236 iounmap(base); 237 if (dd->rcvarray_wc) 238 iounmap(dd->rcvarray_wc); 239 if (dd->piobase) 240 iounmap(dd->piobase); 241 } 242 243 static void msix_setup(struct hfi1_devdata *dd, int pos, u32 *msixcnt, 244 struct hfi1_msix_entry *hfi1_msix_entry) 245 { 246 int ret; 247 int nvec = *msixcnt; 248 struct msix_entry *msix_entry; 249 int i; 250 251 /* 252 * We can't pass hfi1_msix_entry array to msix_setup 253 * so use a dummy msix_entry array and copy the allocated 254 * irq back to the hfi1_msix_entry array. 255 */ 256 msix_entry = kmalloc_array(nvec, sizeof(*msix_entry), GFP_KERNEL); 257 if (!msix_entry) { 258 ret = -ENOMEM; 259 goto do_intx; 260 } 261 262 for (i = 0; i < nvec; i++) 263 msix_entry[i] = hfi1_msix_entry[i].msix; 264 265 ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec); 266 if (ret < 0) 267 goto free_msix_entry; 268 nvec = ret; 269 270 for (i = 0; i < nvec; i++) 271 hfi1_msix_entry[i].msix = msix_entry[i]; 272 273 kfree(msix_entry); 274 *msixcnt = nvec; 275 return; 276 277 free_msix_entry: 278 kfree(msix_entry); 279 280 do_intx: 281 dd_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, falling back to INTx\n", 282 nvec, ret); 283 *msixcnt = 0; 284 hfi1_enable_intx(dd->pcidev); 285 } 286 287 /* return the PCIe link speed from the given link status */ 288 static u32 extract_speed(u16 linkstat) 289 { 290 u32 speed; 291 292 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 293 default: /* not defined, assume Gen1 */ 294 case PCI_EXP_LNKSTA_CLS_2_5GB: 295 speed = 2500; /* Gen 1, 2.5GHz */ 296 break; 297 case PCI_EXP_LNKSTA_CLS_5_0GB: 298 speed = 5000; /* Gen 2, 5GHz */ 299 break; 300 case GEN3_SPEED_VECTOR: 301 speed = 8000; /* Gen 3, 8GHz */ 302 break; 303 } 304 return speed; 305 } 306 307 /* return the PCIe link speed from the given link status */ 308 static u32 extract_width(u16 linkstat) 309 { 310 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 311 } 312 313 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 314 static void update_lbus_info(struct hfi1_devdata *dd) 315 { 316 u16 linkstat; 317 318 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 319 dd->lbus_width = extract_width(linkstat); 320 dd->lbus_speed = extract_speed(linkstat); 321 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 322 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 323 } 324 325 /* 326 * Read in the current PCIe link width and speed. Find if the link is 327 * Gen3 capable. 328 */ 329 int pcie_speeds(struct hfi1_devdata *dd) 330 { 331 u32 linkcap; 332 struct pci_dev *parent = dd->pcidev->bus->self; 333 334 if (!pci_is_pcie(dd->pcidev)) { 335 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 336 return -EINVAL; 337 } 338 339 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 340 dd->link_gen3_capable = 1; 341 342 pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 343 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) { 344 dd_dev_info(dd, 345 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 346 linkcap & PCI_EXP_LNKCAP_SLS); 347 dd->link_gen3_capable = 0; 348 } 349 350 /* 351 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 352 */ 353 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 354 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 355 dd->link_gen3_capable = 0; 356 } 357 358 /* obtain the link width and current speed */ 359 update_lbus_info(dd); 360 361 dd_dev_info(dd, "%s\n", dd->lbus_info); 362 363 return 0; 364 } 365 366 /* 367 * Returns in *nent: 368 * - actual number of interrupts allocated 369 * - 0 if fell back to INTx. 370 */ 371 void request_msix(struct hfi1_devdata *dd, u32 *nent, 372 struct hfi1_msix_entry *entry) 373 { 374 int pos; 375 376 pos = dd->pcidev->msix_cap; 377 if (*nent && pos) { 378 msix_setup(dd, pos, nent, entry); 379 /* did it, either MSI-X or INTx */ 380 } else { 381 *nent = 0; 382 hfi1_enable_intx(dd->pcidev); 383 } 384 385 tune_pcie_caps(dd); 386 } 387 388 void hfi1_enable_intx(struct pci_dev *pdev) 389 { 390 /* first, turn on INTx */ 391 pci_intx(pdev, 1); 392 /* then turn off MSI-X */ 393 pci_disable_msix(pdev); 394 } 395 396 /* restore command and BARs after a reset has wiped them out */ 397 void restore_pci_variables(struct hfi1_devdata *dd) 398 { 399 pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 400 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, dd->pcibar0); 401 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, dd->pcibar1); 402 pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 403 pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, dd->pcie_devctl); 404 pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, dd->pcie_lnkctl); 405 pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 406 dd->pcie_devctl2); 407 pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 408 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, dd->pci_lnkctl3); 409 pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2); 410 } 411 412 /* 413 * BIOS may not set PCIe bus-utilization parameters for best performance. 414 * Check and optionally adjust them to maximize our throughput. 415 */ 416 static int hfi1_pcie_caps; 417 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); 418 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 419 420 uint aspm_mode = ASPM_MODE_DISABLED; 421 module_param_named(aspm, aspm_mode, uint, S_IRUGO); 422 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); 423 424 static void tune_pcie_caps(struct hfi1_devdata *dd) 425 { 426 struct pci_dev *parent; 427 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 428 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 429 430 /* 431 * Turn on extended tags in DevCtl in case the BIOS has turned it off 432 * to improve WFR SDMA bandwidth 433 */ 434 pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); 435 if (!(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 436 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 437 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 438 pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl); 439 } 440 /* Find out supported and configured values for parent (root) */ 441 parent = dd->pcidev->bus->self; 442 /* 443 * The driver cannot perform the tuning if it does not have 444 * access to the upstream component. 445 */ 446 if (!parent) 447 return; 448 if (!pci_is_root_bus(parent->bus)) { 449 dd_dev_info(dd, "Parent not root\n"); 450 return; 451 } 452 453 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) 454 return; 455 rc_mpss = parent->pcie_mpss; 456 rc_mps = ffs(pcie_get_mps(parent)) - 8; 457 /* Find out supported and configured values for endpoint (us) */ 458 ep_mpss = dd->pcidev->pcie_mpss; 459 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 460 461 /* Find max payload supported by root, endpoint */ 462 if (rc_mpss > ep_mpss) 463 rc_mpss = ep_mpss; 464 465 /* If Supported greater than limit in module param, limit it */ 466 if (rc_mpss > (hfi1_pcie_caps & 7)) 467 rc_mpss = hfi1_pcie_caps & 7; 468 /* If less than (allowed, supported), bump root payload */ 469 if (rc_mpss > rc_mps) { 470 rc_mps = rc_mpss; 471 pcie_set_mps(parent, 128 << rc_mps); 472 } 473 /* If less than (allowed, supported), bump endpoint payload */ 474 if (rc_mpss > ep_mps) { 475 ep_mps = rc_mpss; 476 pcie_set_mps(dd->pcidev, 128 << ep_mps); 477 } 478 479 /* 480 * Now the Read Request size. 481 * No field for max supported, but PCIe spec limits it to 4096, 482 * which is code '5' (log2(4096) - 7) 483 */ 484 max_mrrs = 5; 485 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 486 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 487 488 max_mrrs = 128 << max_mrrs; 489 rc_mrrs = pcie_get_readrq(parent); 490 ep_mrrs = pcie_get_readrq(dd->pcidev); 491 492 if (max_mrrs > rc_mrrs) { 493 rc_mrrs = max_mrrs; 494 pcie_set_readrq(parent, rc_mrrs); 495 } 496 if (max_mrrs > ep_mrrs) { 497 ep_mrrs = max_mrrs; 498 pcie_set_readrq(dd->pcidev, ep_mrrs); 499 } 500 } 501 502 /* End of PCIe capability tuning */ 503 504 /* 505 * From here through hfi1_pci_err_handler definition is invoked via 506 * PCI error infrastructure, registered via pci 507 */ 508 static pci_ers_result_t 509 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 510 { 511 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 512 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 513 514 switch (state) { 515 case pci_channel_io_normal: 516 dd_dev_info(dd, "State Normal, ignoring\n"); 517 break; 518 519 case pci_channel_io_frozen: 520 dd_dev_info(dd, "State Frozen, requesting reset\n"); 521 pci_disable_device(pdev); 522 ret = PCI_ERS_RESULT_NEED_RESET; 523 break; 524 525 case pci_channel_io_perm_failure: 526 if (dd) { 527 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 528 /* no more register accesses! */ 529 dd->flags &= ~HFI1_PRESENT; 530 hfi1_disable_after_error(dd); 531 } 532 /* else early, or other problem */ 533 ret = PCI_ERS_RESULT_DISCONNECT; 534 break; 535 536 default: /* shouldn't happen */ 537 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 538 state); 539 break; 540 } 541 return ret; 542 } 543 544 static pci_ers_result_t 545 pci_mmio_enabled(struct pci_dev *pdev) 546 { 547 u64 words = 0U; 548 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 549 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 550 551 if (dd && dd->pport) { 552 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 553 if (words == ~0ULL) 554 ret = PCI_ERS_RESULT_NEED_RESET; 555 dd_dev_info(dd, 556 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", 557 words, ret); 558 } 559 return ret; 560 } 561 562 static pci_ers_result_t 563 pci_slot_reset(struct pci_dev *pdev) 564 { 565 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 566 567 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 568 return PCI_ERS_RESULT_CAN_RECOVER; 569 } 570 571 static void 572 pci_resume(struct pci_dev *pdev) 573 { 574 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 575 576 dd_dev_info(dd, "HFI1 resume function called\n"); 577 pci_cleanup_aer_uncorrect_error_status(pdev); 578 /* 579 * Running jobs will fail, since it's asynchronous 580 * unlike sysfs-requested reset. Better than 581 * doing nothing. 582 */ 583 hfi1_init(dd, 1); /* same as re-init after reset */ 584 } 585 586 const struct pci_error_handlers hfi1_pci_err_handler = { 587 .error_detected = pci_error_detected, 588 .mmio_enabled = pci_mmio_enabled, 589 .slot_reset = pci_slot_reset, 590 .resume = pci_resume, 591 }; 592 593 /*============================================================================*/ 594 /* PCIe Gen3 support */ 595 596 /* 597 * This code is separated out because it is expected to be removed in the 598 * final shipping product. If not, then it will be revisited and items 599 * will be moved to more standard locations. 600 */ 601 602 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 603 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 604 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 605 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 606 607 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 608 #define DL_ERR_NONE 0x0 /* no error */ 609 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 610 /* or response data */ 611 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 612 #define DL_ERR_SECURITY 0x3 /* security check failed */ 613 #define DL_ERR_SBUS 0x4 /* SBus status error */ 614 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 615 616 /* gasket block secondary bus reset delay */ 617 #define SBR_DELAY_US 200000 /* 200ms */ 618 619 /* mask for PCIe capability register lnkctl2 target link speed */ 620 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf 621 622 static uint pcie_target = 3; 623 module_param(pcie_target, uint, S_IRUGO); 624 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 625 626 static uint pcie_force; 627 module_param(pcie_force, uint, S_IRUGO); 628 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 629 630 static uint pcie_retry = 5; 631 module_param(pcie_retry, uint, S_IRUGO); 632 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 633 634 #define UNSET_PSET 255 635 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 636 #define DEFAULT_MCP_PSET 6 /* MCP HFI */ 637 static uint pcie_pset = UNSET_PSET; 638 module_param(pcie_pset, uint, S_IRUGO); 639 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 640 641 static uint pcie_ctle = 3; /* discrete on, integrated on */ 642 module_param(pcie_ctle, uint, S_IRUGO); 643 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 644 645 /* equalization columns */ 646 #define PREC 0 647 #define ATTN 1 648 #define POST 2 649 650 /* discrete silicon preliminary equalization values */ 651 static const u8 discrete_preliminary_eq[11][3] = { 652 /* prec attn post */ 653 { 0x00, 0x00, 0x12 }, /* p0 */ 654 { 0x00, 0x00, 0x0c }, /* p1 */ 655 { 0x00, 0x00, 0x0f }, /* p2 */ 656 { 0x00, 0x00, 0x09 }, /* p3 */ 657 { 0x00, 0x00, 0x00 }, /* p4 */ 658 { 0x06, 0x00, 0x00 }, /* p5 */ 659 { 0x09, 0x00, 0x00 }, /* p6 */ 660 { 0x06, 0x00, 0x0f }, /* p7 */ 661 { 0x09, 0x00, 0x09 }, /* p8 */ 662 { 0x0c, 0x00, 0x00 }, /* p9 */ 663 { 0x00, 0x00, 0x18 }, /* p10 */ 664 }; 665 666 /* integrated silicon preliminary equalization values */ 667 static const u8 integrated_preliminary_eq[11][3] = { 668 /* prec attn post */ 669 { 0x00, 0x1e, 0x07 }, /* p0 */ 670 { 0x00, 0x1e, 0x05 }, /* p1 */ 671 { 0x00, 0x1e, 0x06 }, /* p2 */ 672 { 0x00, 0x1e, 0x04 }, /* p3 */ 673 { 0x00, 0x1e, 0x00 }, /* p4 */ 674 { 0x03, 0x1e, 0x00 }, /* p5 */ 675 { 0x04, 0x1e, 0x00 }, /* p6 */ 676 { 0x03, 0x1e, 0x06 }, /* p7 */ 677 { 0x03, 0x1e, 0x04 }, /* p8 */ 678 { 0x05, 0x1e, 0x00 }, /* p9 */ 679 { 0x00, 0x1e, 0x0a }, /* p10 */ 680 }; 681 682 static const u8 discrete_ctle_tunings[11][4] = { 683 /* DC LF HF BW */ 684 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 685 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 686 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 687 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 688 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 689 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 690 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 691 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 692 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 693 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 694 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 695 }; 696 697 static const u8 integrated_ctle_tunings[11][4] = { 698 /* DC LF HF BW */ 699 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 700 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 701 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 702 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 703 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 704 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 705 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 706 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 707 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 708 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 709 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 710 }; 711 712 /* helper to format the value to write to hardware */ 713 #define eq_value(pre, curr, post) \ 714 ((((u32)(pre)) << \ 715 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 716 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 717 | (((u32)(post)) << \ 718 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 719 720 /* 721 * Load the given EQ preset table into the PCIe hardware. 722 */ 723 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 724 u8 div) 725 { 726 struct pci_dev *pdev = dd->pcidev; 727 u32 hit_error = 0; 728 u32 violation; 729 u32 i; 730 u8 c_minus1, c0, c_plus1; 731 732 for (i = 0; i < 11; i++) { 733 /* set index */ 734 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 735 /* write the value */ 736 c_minus1 = eq[i][PREC] / div; 737 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 738 c_plus1 = eq[i][POST] / div; 739 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 740 eq_value(c_minus1, c0, c_plus1)); 741 /* check if these coefficients violate EQ rules */ 742 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL105, 743 &violation); 744 if (violation 745 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 746 if (hit_error == 0) { 747 dd_dev_err(dd, 748 "Gen3 EQ Table Coefficient rule violations\n"); 749 dd_dev_err(dd, " prec attn post\n"); 750 } 751 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 752 i, (u32)eq[i][0], (u32)eq[i][1], 753 (u32)eq[i][2]); 754 dd_dev_err(dd, " %02x %02x %02x\n", 755 (u32)c_minus1, (u32)c0, (u32)c_plus1); 756 hit_error = 1; 757 } 758 } 759 if (hit_error) 760 return -EINVAL; 761 return 0; 762 } 763 764 /* 765 * Steps to be done after the PCIe firmware is downloaded and 766 * before the SBR for the Pcie Gen3. 767 * The SBus resource is already being held. 768 */ 769 static void pcie_post_steps(struct hfi1_devdata *dd) 770 { 771 int i; 772 773 set_sbus_fast_mode(dd); 774 /* 775 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 776 * This avoids a spurious framing error that can otherwise be 777 * generated by the MAC layer. 778 * 779 * Use individual addresses since no broadcast is set up. 780 */ 781 for (i = 0; i < NUM_PCIE_SERDES; i++) { 782 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 783 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 784 } 785 786 clear_sbus_fast_mode(dd); 787 } 788 789 /* 790 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 791 * 792 * Based on pci_parent_bus_reset() which is not exported by the 793 * kernel core. 794 */ 795 static int trigger_sbr(struct hfi1_devdata *dd) 796 { 797 struct pci_dev *dev = dd->pcidev; 798 struct pci_dev *pdev; 799 800 /* need a parent */ 801 if (!dev->bus->self) { 802 dd_dev_err(dd, "%s: no parent device\n", __func__); 803 return -ENOTTY; 804 } 805 806 /* should not be anyone else on the bus */ 807 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 808 if (pdev != dev) { 809 dd_dev_err(dd, 810 "%s: another device is on the same bus\n", 811 __func__); 812 return -ENOTTY; 813 } 814 815 /* 816 * A secondary bus reset (SBR) issues a hot reset to our device. 817 * The following routine does a 1s wait after the reset is dropped 818 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - 819 * Conventional Reset, paragraph 3, line 35 also says that a 1s 820 * delay after a reset is required. Per spec requirements, 821 * the link is either working or not after that point. 822 */ 823 pci_reset_bridge_secondary_bus(dev->bus->self); 824 825 return 0; 826 } 827 828 /* 829 * Write the given gasket interrupt register. 830 */ 831 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 832 u16 code, u16 data) 833 { 834 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 835 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 836 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 837 } 838 839 /* 840 * Tell the gasket logic how to react to the reset. 841 */ 842 static void arm_gasket_logic(struct hfi1_devdata *dd) 843 { 844 u64 reg; 845 846 reg = (((u64)1 << dd->hfi1_id) << 847 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 848 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 849 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 850 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 851 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 852 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 853 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 854 /* read back to push the write */ 855 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 856 } 857 858 /* 859 * CCE_PCIE_CTRL long name helpers 860 * We redefine these shorter macros to use in the code while leaving 861 * chip_registers.h to be autogenerated from the hardware spec. 862 */ 863 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 864 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 865 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 866 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 867 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 868 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 869 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 870 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 871 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 872 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 873 874 /* 875 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 876 */ 877 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 878 { 879 u64 pcie_ctrl; 880 u64 xmt_margin; 881 u64 xmt_margin_oe; 882 u64 lane_delay; 883 u64 lane_bundle; 884 885 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 886 887 /* 888 * For Discrete, use full-swing. 889 * - PCIe TX defaults to full-swing. 890 * Leave this register as default. 891 * For Integrated, use half-swing 892 * - Copy xmt_margin and xmt_margin_oe 893 * from Gen1/Gen2 to Gen3. 894 */ 895 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 896 /* extract initial fields */ 897 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 898 & MARGIN_GEN1_GEN2_MASK; 899 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 900 & MARGIN_G1_G2_OVERWRITE_MASK; 901 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 902 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 903 & LANE_BUNDLE_MASK; 904 905 /* 906 * For A0, EFUSE values are not set. Override with the 907 * correct values. 908 */ 909 if (is_ax(dd)) { 910 /* 911 * xmt_margin and OverwiteEnabel should be the 912 * same for Gen1/Gen2 and Gen3 913 */ 914 xmt_margin = 0x5; 915 xmt_margin_oe = 0x1; 916 lane_delay = 0xF; /* Delay 240ns. */ 917 lane_bundle = 0x0; /* Set to 1 lane. */ 918 } 919 920 /* overwrite existing values */ 921 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 922 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 923 | (xmt_margin << MARGIN_SHIFT) 924 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 925 | (lane_delay << LANE_DELAY_SHIFT) 926 | (lane_bundle << LANE_BUNDLE_SHIFT); 927 928 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 929 } 930 931 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 932 fname, pcie_ctrl); 933 } 934 935 /* 936 * Do all the steps needed to transition the PCIe link to Gen3 speed. 937 */ 938 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 939 { 940 struct pci_dev *parent = dd->pcidev->bus->self; 941 u64 fw_ctrl; 942 u64 reg, therm; 943 u32 reg32, fs, lf; 944 u32 status, err; 945 int ret; 946 int do_retry, retry_count = 0; 947 int intnum = 0; 948 uint default_pset; 949 u16 target_vector, target_speed; 950 u16 lnkctl2, vendor; 951 u8 div; 952 const u8 (*eq)[3]; 953 const u8 (*ctle_tunings)[4]; 954 uint static_ctle_mode; 955 int return_error = 0; 956 957 /* PCIe Gen3 is for the ASIC only */ 958 if (dd->icode != ICODE_RTL_SILICON) 959 return 0; 960 961 if (pcie_target == 1) { /* target Gen1 */ 962 target_vector = GEN1_SPEED_VECTOR; 963 target_speed = 2500; 964 } else if (pcie_target == 2) { /* target Gen2 */ 965 target_vector = GEN2_SPEED_VECTOR; 966 target_speed = 5000; 967 } else if (pcie_target == 3) { /* target Gen3 */ 968 target_vector = GEN3_SPEED_VECTOR; 969 target_speed = 8000; 970 } else { 971 /* off or invalid target - skip */ 972 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 973 return 0; 974 } 975 976 /* if already at target speed, done (unless forced) */ 977 if (dd->lbus_speed == target_speed) { 978 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 979 pcie_target, 980 pcie_force ? "re-doing anyway" : "skipping"); 981 if (!pcie_force) 982 return 0; 983 } 984 985 /* 986 * The driver cannot do the transition if it has no access to the 987 * upstream component 988 */ 989 if (!parent) { 990 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 991 __func__); 992 return 0; 993 } 994 995 /* 996 * Do the Gen3 transition. Steps are those of the PCIe Gen3 997 * recipe. 998 */ 999 1000 /* step 1: pcie link working in gen1/gen2 */ 1001 1002 /* step 2: if either side is not capable of Gen3, done */ 1003 if (pcie_target == 3 && !dd->link_gen3_capable) { 1004 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1005 ret = -ENOSYS; 1006 goto done_no_mutex; 1007 } 1008 1009 /* hold the SBus resource across the firmware download and SBR */ 1010 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1011 if (ret) { 1012 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1013 __func__); 1014 return ret; 1015 } 1016 1017 /* make sure thermal polling is not causing interrupts */ 1018 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1019 if (therm) { 1020 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1021 msleep(100); 1022 dd_dev_info(dd, "%s: Disabled therm polling\n", 1023 __func__); 1024 } 1025 1026 retry: 1027 /* the SBus download will reset the spico for thermal */ 1028 1029 /* step 3: download SBus Master firmware */ 1030 /* step 4: download PCIe Gen3 SerDes firmware */ 1031 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1032 ret = load_pcie_firmware(dd); 1033 if (ret) { 1034 /* do not proceed if the firmware cannot be downloaded */ 1035 return_error = 1; 1036 goto done; 1037 } 1038 1039 /* step 5: set up device parameter settings */ 1040 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1041 1042 /* 1043 * PcieCfgSpcie1 - Link Control 3 1044 * Leave at reset value. No need to set PerfEq - link equalization 1045 * will be performed automatically after the SBR when the target 1046 * speed is 8GT/s. 1047 */ 1048 1049 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1050 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1051 1052 /* step 5a: Set Synopsys Port Logic registers */ 1053 1054 /* 1055 * PcieCfgRegPl2 - Port Force Link 1056 * 1057 * Set the low power field to 0x10 to avoid unnecessary power 1058 * management messages. All other fields are zero. 1059 */ 1060 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1061 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1062 1063 /* 1064 * PcieCfgRegPl100 - Gen3 Control 1065 * 1066 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1067 * turn on PcieCfgRegPl100.EqEieosCnt 1068 * Everything else zero. 1069 */ 1070 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1071 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1072 1073 /* 1074 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1075 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1076 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1077 * PcieCfgRegPl105 - Gen3 EQ Status 1078 * 1079 * Give initial EQ settings. 1080 */ 1081 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1082 /* 1000mV, FS=24, LF = 8 */ 1083 fs = 24; 1084 lf = 8; 1085 div = 3; 1086 eq = discrete_preliminary_eq; 1087 default_pset = DEFAULT_DISCRETE_PSET; 1088 ctle_tunings = discrete_ctle_tunings; 1089 /* bit 0 - discrete on/off */ 1090 static_ctle_mode = pcie_ctle & 0x1; 1091 } else { 1092 /* 400mV, FS=29, LF = 9 */ 1093 fs = 29; 1094 lf = 9; 1095 div = 1; 1096 eq = integrated_preliminary_eq; 1097 default_pset = DEFAULT_MCP_PSET; 1098 ctle_tunings = integrated_ctle_tunings; 1099 /* bit 1 - integrated on/off */ 1100 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1101 } 1102 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1103 (fs << 1104 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1105 (lf << 1106 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1107 ret = load_eq_table(dd, eq, fs, div); 1108 if (ret) 1109 goto done; 1110 1111 /* 1112 * PcieCfgRegPl106 - Gen3 EQ Control 1113 * 1114 * Set Gen3EqPsetReqVec, leave other fields 0. 1115 */ 1116 if (pcie_pset == UNSET_PSET) 1117 pcie_pset = default_pset; 1118 if (pcie_pset > 10) { /* valid range is 0-10, inclusive */ 1119 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1120 __func__, pcie_pset, default_pset); 1121 pcie_pset = default_pset; 1122 } 1123 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset); 1124 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1125 ((1 << pcie_pset) << 1126 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1127 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1128 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1129 1130 /* 1131 * step 5b: Do post firmware download steps via SBus 1132 */ 1133 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1134 pcie_post_steps(dd); 1135 1136 /* 1137 * step 5c: Program gasket interrupts 1138 */ 1139 /* set the Rx Bit Rate to REFCLK ratio */ 1140 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1141 /* disable pCal for PCIe Gen3 RX equalization */ 1142 /* select adaptive or static CTLE */ 1143 write_gasket_interrupt(dd, intnum++, 0x0026, 1144 0x5b01 | (static_ctle_mode << 3)); 1145 /* 1146 * Enable iCal for PCIe Gen3 RX equalization, and set which 1147 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1148 */ 1149 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1150 1151 if (static_ctle_mode) { 1152 /* apply static CTLE tunings */ 1153 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1154 1155 pcie_dc = ctle_tunings[pcie_pset][0]; 1156 pcie_lf = ctle_tunings[pcie_pset][1]; 1157 pcie_hf = ctle_tunings[pcie_pset][2]; 1158 pcie_bw = ctle_tunings[pcie_pset][3]; 1159 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1160 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1161 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1162 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1163 } 1164 1165 /* terminate list */ 1166 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1167 1168 /* 1169 * step 5d: program XMT margin 1170 */ 1171 write_xmt_margin(dd, __func__); 1172 1173 /* 1174 * step 5e: disable active state power management (ASPM). It 1175 * will be enabled if required later 1176 */ 1177 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1178 aspm_hw_disable_l1(dd); 1179 1180 /* 1181 * step 5f: clear DirectSpeedChange 1182 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1183 * change in the speed target from starting before we are ready. 1184 * This field defaults to 0 and we are not changing it, so nothing 1185 * needs to be done. 1186 */ 1187 1188 /* step 5g: Set target link speed */ 1189 /* 1190 * Set target link speed to be target on both device and parent. 1191 * On setting the parent: Some system BIOSs "helpfully" set the 1192 * parent target speed to Gen2 to match the ASIC's initial speed. 1193 * We can set the target Gen3 because we have already checked 1194 * that it is Gen3 capable earlier. 1195 */ 1196 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1197 pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1198 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1199 (u32)lnkctl2); 1200 /* only write to parent if target is not as high as ours */ 1201 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) { 1202 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1203 lnkctl2 |= target_vector; 1204 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1205 (u32)lnkctl2); 1206 pcie_capability_write_word(parent, PCI_EXP_LNKCTL2, lnkctl2); 1207 } else { 1208 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1209 } 1210 1211 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1212 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1213 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1214 (u32)lnkctl2); 1215 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1216 lnkctl2 |= target_vector; 1217 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1218 (u32)lnkctl2); 1219 pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1220 1221 /* step 5h: arm gasket logic */ 1222 /* hold DC in reset across the SBR */ 1223 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1224 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1225 /* save firmware control across the SBR */ 1226 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1227 1228 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1229 arm_gasket_logic(dd); 1230 1231 /* 1232 * step 6: quiesce PCIe link 1233 * The chip has already been reset, so there will be no traffic 1234 * from the chip. Linux has no easy way to enforce that it will 1235 * not try to access the device, so we just need to hope it doesn't 1236 * do it while we are doing the reset. 1237 */ 1238 1239 /* 1240 * step 7: initiate the secondary bus reset (SBR) 1241 * step 8: hardware brings the links back up 1242 * step 9: wait for link speed transition to be complete 1243 */ 1244 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1245 ret = trigger_sbr(dd); 1246 if (ret) 1247 goto done; 1248 1249 /* step 10: decide what to do next */ 1250 1251 /* check if we can read PCI space */ 1252 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1253 if (ret) { 1254 dd_dev_info(dd, 1255 "%s: read of VendorID failed after SBR, err %d\n", 1256 __func__, ret); 1257 return_error = 1; 1258 goto done; 1259 } 1260 if (vendor == 0xffff) { 1261 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1262 return_error = 1; 1263 ret = -EIO; 1264 goto done; 1265 } 1266 1267 /* restore PCI space registers we know were reset */ 1268 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1269 restore_pci_variables(dd); 1270 /* restore firmware control */ 1271 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1272 1273 /* 1274 * Check the gasket block status. 1275 * 1276 * This is the first CSR read after the SBR. If the read returns 1277 * all 1s (fails), the link did not make it back. 1278 * 1279 * Once we're sure we can read and write, clear the DC reset after 1280 * the SBR. Then check for any per-lane errors. Then look over 1281 * the status. 1282 */ 1283 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1284 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1285 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1286 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1287 return_error = 1; 1288 ret = -ENOSYS; 1289 goto done; 1290 } 1291 1292 /* clear the DC reset */ 1293 write_csr(dd, CCE_DC_CTRL, 0); 1294 1295 /* Set the LED off */ 1296 setextled(dd, 0); 1297 1298 /* check for any per-lane errors */ 1299 pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1300 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1301 1302 /* extract status, look for our HFI */ 1303 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1304 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1305 if ((status & (1 << dd->hfi1_id)) == 0) { 1306 dd_dev_err(dd, 1307 "%s: gasket status 0x%x, expecting 0x%x\n", 1308 __func__, status, 1 << dd->hfi1_id); 1309 ret = -EIO; 1310 goto done; 1311 } 1312 1313 /* extract error */ 1314 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1315 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1316 if (err) { 1317 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1318 ret = -EIO; 1319 goto done; 1320 } 1321 1322 /* update our link information cache */ 1323 update_lbus_info(dd); 1324 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1325 dd->lbus_info); 1326 1327 if (dd->lbus_speed != target_speed) { /* not target */ 1328 /* maybe retry */ 1329 do_retry = retry_count < pcie_retry; 1330 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", 1331 pcie_target, do_retry ? ", retrying" : ""); 1332 retry_count++; 1333 if (do_retry) { 1334 msleep(100); /* allow time to settle */ 1335 goto retry; 1336 } 1337 ret = -EIO; 1338 } 1339 1340 done: 1341 if (therm) { 1342 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1343 msleep(100); 1344 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1345 __func__); 1346 } 1347 release_chip_resource(dd, CR_SBUS); 1348 done_no_mutex: 1349 /* return no error if it is OK to be at current speed */ 1350 if (ret && !return_error) { 1351 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1352 ret = 0; 1353 } 1354 1355 dd_dev_info(dd, "%s: done\n", __func__); 1356 return ret; 1357 } 1358