1 /* 2 * Copyright(c) 2015 - 2017 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* link speed vector for Gen3 speed - not in Linux headers */ 60 #define GEN1_SPEED_VECTOR 0x1 61 #define GEN2_SPEED_VECTOR 0x2 62 #define GEN3_SPEED_VECTOR 0x3 63 64 /* 65 * This file contains PCIe utility routines. 66 */ 67 68 /* 69 * Code to adjust PCIe capabilities. 70 */ 71 static int tune_pcie_caps(struct hfi1_devdata *); 72 73 /* 74 * Do all the common PCIe setup and initialization. 75 * devdata is not yet allocated, and is not allocated until after this 76 * routine returns success. Therefore dd_dev_err() can't be used for error 77 * printing. 78 */ 79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 80 { 81 int ret; 82 83 ret = pci_enable_device(pdev); 84 if (ret) { 85 /* 86 * This can happen (in theory) iff: 87 * We did a chip reset, and then failed to reprogram the 88 * BAR, or the chip reset due to an internal error. We then 89 * unloaded the driver and reloaded it. 90 * 91 * Both reset cases set the BAR back to initial state. For 92 * the latter case, the AER sticky error bit at offset 0x718 93 * should be set, but the Linux kernel doesn't yet know 94 * about that, it appears. If the original BAR was retained 95 * in the kernel data structures, this may be OK. 96 */ 97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", 98 -ret); 99 goto done; 100 } 101 102 ret = pci_request_regions(pdev, DRIVER_NAME); 103 if (ret) { 104 hfi1_early_err(&pdev->dev, 105 "pci_request_regions fails: err %d\n", -ret); 106 goto bail; 107 } 108 109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 110 if (ret) { 111 /* 112 * If the 64 bit setup fails, try 32 bit. Some systems 113 * do not setup 64 bit maps on systems with 2GB or less 114 * memory installed. 115 */ 116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 117 if (ret) { 118 hfi1_early_err(&pdev->dev, 119 "Unable to set DMA mask: %d\n", ret); 120 goto bail; 121 } 122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 123 } else { 124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 125 } 126 if (ret) { 127 hfi1_early_err(&pdev->dev, 128 "Unable to set DMA consistent mask: %d\n", ret); 129 goto bail; 130 } 131 132 pci_set_master(pdev); 133 (void)pci_enable_pcie_error_reporting(pdev); 134 goto done; 135 136 bail: 137 hfi1_pcie_cleanup(pdev); 138 done: 139 return ret; 140 } 141 142 /* 143 * Clean what was done in hfi1_pcie_init() 144 */ 145 void hfi1_pcie_cleanup(struct pci_dev *pdev) 146 { 147 pci_disable_device(pdev); 148 /* 149 * Release regions should be called after the disable. OK to 150 * call if request regions has not been called or failed. 151 */ 152 pci_release_regions(pdev); 153 } 154 155 /* 156 * Do remaining PCIe setup, once dd is allocated, and save away 157 * fields required to re-initialize after a chip reset, or for 158 * various other purposes 159 */ 160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 161 { 162 unsigned long len; 163 resource_size_t addr; 164 int ret = 0; 165 166 dd->pcidev = pdev; 167 pci_set_drvdata(pdev, dd); 168 169 addr = pci_resource_start(pdev, 0); 170 len = pci_resource_len(pdev, 0); 171 172 /* 173 * The TXE PIO buffers are at the tail end of the chip space. 174 * Cut them off and map them separately. 175 */ 176 177 /* sanity check vs expectations */ 178 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 179 dd_dev_err(dd, "chip PIO range does not match\n"); 180 return -EINVAL; 181 } 182 183 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY); 184 if (!dd->kregbase1) { 185 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); 186 return -ENOMEM; 187 } 188 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); 189 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); 190 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count); 191 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8; 192 193 dd->kregbase2 = ioremap_nocache( 194 addr + dd->base2_start, 195 TXE_PIO_SEND - dd->base2_start); 196 if (!dd->kregbase2) { 197 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); 198 goto nomem; 199 } 200 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, 201 TXE_PIO_SEND - dd->base2_start); 202 203 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 204 if (!dd->piobase) { 205 dd_dev_err(dd, "WC mapping of send buffers failed\n"); 206 goto nomem; 207 } 208 dd_dev_info(dd, "WC piobase: %p\n for %x", dd->piobase, TXE_PIO_SIZE); 209 210 dd->physaddr = addr; /* used for io_remap, etc. */ 211 212 /* 213 * Map the chip's RcvArray as write-combining to allow us 214 * to write an entire cacheline worth of entries in one shot. 215 */ 216 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 217 dd->chip_rcv_array_count * 8); 218 if (!dd->rcvarray_wc) { 219 dd_dev_err(dd, "WC mapping of receive array failed\n"); 220 goto nomem; 221 } 222 dd_dev_info(dd, "WC RcvArray: %p for %x\n", 223 dd->rcvarray_wc, dd->chip_rcv_array_count * 8); 224 225 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ 226 return 0; 227 nomem: 228 ret = -ENOMEM; 229 hfi1_pcie_ddcleanup(dd); 230 return ret; 231 } 232 233 /* 234 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 235 * to releasing the dd memory. 236 * Void because all of the core pcie cleanup functions are void. 237 */ 238 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 239 { 240 dd->flags &= ~HFI1_PRESENT; 241 if (dd->kregbase1) 242 iounmap(dd->kregbase1); 243 dd->kregbase1 = NULL; 244 if (dd->kregbase2) 245 iounmap(dd->kregbase2); 246 dd->kregbase2 = NULL; 247 if (dd->rcvarray_wc) 248 iounmap(dd->rcvarray_wc); 249 dd->rcvarray_wc = NULL; 250 if (dd->piobase) 251 iounmap(dd->piobase); 252 dd->piobase = NULL; 253 } 254 255 /* return the PCIe link speed from the given link status */ 256 static u32 extract_speed(u16 linkstat) 257 { 258 u32 speed; 259 260 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 261 default: /* not defined, assume Gen1 */ 262 case PCI_EXP_LNKSTA_CLS_2_5GB: 263 speed = 2500; /* Gen 1, 2.5GHz */ 264 break; 265 case PCI_EXP_LNKSTA_CLS_5_0GB: 266 speed = 5000; /* Gen 2, 5GHz */ 267 break; 268 case GEN3_SPEED_VECTOR: 269 speed = 8000; /* Gen 3, 8GHz */ 270 break; 271 } 272 return speed; 273 } 274 275 /* return the PCIe link speed from the given link status */ 276 static u32 extract_width(u16 linkstat) 277 { 278 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 279 } 280 281 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 282 static void update_lbus_info(struct hfi1_devdata *dd) 283 { 284 u16 linkstat; 285 int ret; 286 287 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 288 if (ret) { 289 dd_dev_err(dd, "Unable to read from PCI config\n"); 290 return; 291 } 292 293 dd->lbus_width = extract_width(linkstat); 294 dd->lbus_speed = extract_speed(linkstat); 295 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 296 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 297 } 298 299 /* 300 * Read in the current PCIe link width and speed. Find if the link is 301 * Gen3 capable. 302 */ 303 int pcie_speeds(struct hfi1_devdata *dd) 304 { 305 u32 linkcap; 306 struct pci_dev *parent = dd->pcidev->bus->self; 307 int ret; 308 309 if (!pci_is_pcie(dd->pcidev)) { 310 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 311 return -EINVAL; 312 } 313 314 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 315 dd->link_gen3_capable = 1; 316 317 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 318 if (ret) { 319 dd_dev_err(dd, "Unable to read from PCI config\n"); 320 return ret; 321 } 322 323 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) { 324 dd_dev_info(dd, 325 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 326 linkcap & PCI_EXP_LNKCAP_SLS); 327 dd->link_gen3_capable = 0; 328 } 329 330 /* 331 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 332 */ 333 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 334 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 335 dd->link_gen3_capable = 0; 336 } 337 338 /* obtain the link width and current speed */ 339 update_lbus_info(dd); 340 341 dd_dev_info(dd, "%s\n", dd->lbus_info); 342 343 return 0; 344 } 345 346 /* 347 * Returns: 348 * - actual number of interrupts allocated or 349 * - 0 if fell back to INTx. 350 * - error 351 */ 352 int request_msix(struct hfi1_devdata *dd, u32 msireq) 353 { 354 int nvec, ret; 355 356 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq, 357 PCI_IRQ_MSIX | PCI_IRQ_LEGACY); 358 if (nvec < 0) { 359 dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", nvec); 360 return nvec; 361 } 362 363 ret = tune_pcie_caps(dd); 364 if (ret) { 365 dd_dev_err(dd, "tune_pcie_caps() failed: %d\n", ret); 366 pci_free_irq_vectors(dd->pcidev); 367 return ret; 368 } 369 370 /* check for legacy IRQ */ 371 if (nvec == 1 && !dd->pcidev->msix_enabled) 372 return 0; 373 374 return nvec; 375 } 376 377 /* restore command and BARs after a reset has wiped them out */ 378 int restore_pci_variables(struct hfi1_devdata *dd) 379 { 380 int ret = 0; 381 382 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 383 if (ret) 384 goto error; 385 386 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 387 dd->pcibar0); 388 if (ret) 389 goto error; 390 391 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 392 dd->pcibar1); 393 if (ret) 394 goto error; 395 396 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 397 if (ret) 398 goto error; 399 400 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, 401 dd->pcie_devctl); 402 if (ret) 403 goto error; 404 405 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, 406 dd->pcie_lnkctl); 407 if (ret) 408 goto error; 409 410 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 411 dd->pcie_devctl2); 412 if (ret) 413 goto error; 414 415 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 416 if (ret) 417 goto error; 418 419 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, 420 dd->pci_lnkctl3); 421 if (ret) 422 goto error; 423 424 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2); 425 if (ret) 426 goto error; 427 428 return 0; 429 430 error: 431 dd_dev_err(dd, "Unable to write to PCI config\n"); 432 return ret; 433 } 434 435 /* Save BARs and command to rewrite after device reset */ 436 int save_pci_variables(struct hfi1_devdata *dd) 437 { 438 int ret = 0; 439 440 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 441 &dd->pcibar0); 442 if (ret) 443 goto error; 444 445 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 446 &dd->pcibar1); 447 if (ret) 448 goto error; 449 450 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 451 if (ret) 452 goto error; 453 454 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 455 if (ret) 456 goto error; 457 458 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, 459 &dd->pcie_devctl); 460 if (ret) 461 goto error; 462 463 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, 464 &dd->pcie_lnkctl); 465 if (ret) 466 goto error; 467 468 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 469 &dd->pcie_devctl2); 470 if (ret) 471 goto error; 472 473 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 474 if (ret) 475 goto error; 476 477 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, 478 &dd->pci_lnkctl3); 479 if (ret) 480 goto error; 481 482 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2); 483 if (ret) 484 goto error; 485 486 return 0; 487 488 error: 489 dd_dev_err(dd, "Unable to read from PCI config\n"); 490 return ret; 491 } 492 493 /* 494 * BIOS may not set PCIe bus-utilization parameters for best performance. 495 * Check and optionally adjust them to maximize our throughput. 496 */ 497 static int hfi1_pcie_caps; 498 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); 499 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 500 501 uint aspm_mode = ASPM_MODE_DISABLED; 502 module_param_named(aspm, aspm_mode, uint, S_IRUGO); 503 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); 504 505 static int tune_pcie_caps(struct hfi1_devdata *dd) 506 { 507 struct pci_dev *parent; 508 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 509 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 510 int ret; 511 512 /* 513 * Turn on extended tags in DevCtl in case the BIOS has turned it off 514 * to improve WFR SDMA bandwidth 515 */ 516 ret = pcie_capability_read_word(dd->pcidev, 517 PCI_EXP_DEVCTL, &ectl); 518 if (ret) { 519 dd_dev_err(dd, "Unable to read from PCI config\n"); 520 return ret; 521 } 522 523 if (!(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 524 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 525 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 526 ret = pcie_capability_write_word(dd->pcidev, 527 PCI_EXP_DEVCTL, ectl); 528 if (ret) { 529 dd_dev_err(dd, "Unable to write to PCI config\n"); 530 return ret; 531 } 532 } 533 /* Find out supported and configured values for parent (root) */ 534 parent = dd->pcidev->bus->self; 535 /* 536 * The driver cannot perform the tuning if it does not have 537 * access to the upstream component. 538 */ 539 if (!parent) 540 return -EINVAL; 541 if (!pci_is_root_bus(parent->bus)) { 542 dd_dev_info(dd, "Parent not root\n"); 543 return -EINVAL; 544 } 545 546 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) 547 return -EINVAL; 548 rc_mpss = parent->pcie_mpss; 549 rc_mps = ffs(pcie_get_mps(parent)) - 8; 550 /* Find out supported and configured values for endpoint (us) */ 551 ep_mpss = dd->pcidev->pcie_mpss; 552 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 553 554 /* Find max payload supported by root, endpoint */ 555 if (rc_mpss > ep_mpss) 556 rc_mpss = ep_mpss; 557 558 /* If Supported greater than limit in module param, limit it */ 559 if (rc_mpss > (hfi1_pcie_caps & 7)) 560 rc_mpss = hfi1_pcie_caps & 7; 561 /* If less than (allowed, supported), bump root payload */ 562 if (rc_mpss > rc_mps) { 563 rc_mps = rc_mpss; 564 pcie_set_mps(parent, 128 << rc_mps); 565 } 566 /* If less than (allowed, supported), bump endpoint payload */ 567 if (rc_mpss > ep_mps) { 568 ep_mps = rc_mpss; 569 pcie_set_mps(dd->pcidev, 128 << ep_mps); 570 } 571 572 /* 573 * Now the Read Request size. 574 * No field for max supported, but PCIe spec limits it to 4096, 575 * which is code '5' (log2(4096) - 7) 576 */ 577 max_mrrs = 5; 578 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 579 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 580 581 max_mrrs = 128 << max_mrrs; 582 rc_mrrs = pcie_get_readrq(parent); 583 ep_mrrs = pcie_get_readrq(dd->pcidev); 584 585 if (max_mrrs > rc_mrrs) { 586 rc_mrrs = max_mrrs; 587 pcie_set_readrq(parent, rc_mrrs); 588 } 589 if (max_mrrs > ep_mrrs) { 590 ep_mrrs = max_mrrs; 591 pcie_set_readrq(dd->pcidev, ep_mrrs); 592 } 593 594 return 0; 595 } 596 597 /* End of PCIe capability tuning */ 598 599 /* 600 * From here through hfi1_pci_err_handler definition is invoked via 601 * PCI error infrastructure, registered via pci 602 */ 603 static pci_ers_result_t 604 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 605 { 606 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 607 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 608 609 switch (state) { 610 case pci_channel_io_normal: 611 dd_dev_info(dd, "State Normal, ignoring\n"); 612 break; 613 614 case pci_channel_io_frozen: 615 dd_dev_info(dd, "State Frozen, requesting reset\n"); 616 pci_disable_device(pdev); 617 ret = PCI_ERS_RESULT_NEED_RESET; 618 break; 619 620 case pci_channel_io_perm_failure: 621 if (dd) { 622 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 623 /* no more register accesses! */ 624 dd->flags &= ~HFI1_PRESENT; 625 hfi1_disable_after_error(dd); 626 } 627 /* else early, or other problem */ 628 ret = PCI_ERS_RESULT_DISCONNECT; 629 break; 630 631 default: /* shouldn't happen */ 632 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 633 state); 634 break; 635 } 636 return ret; 637 } 638 639 static pci_ers_result_t 640 pci_mmio_enabled(struct pci_dev *pdev) 641 { 642 u64 words = 0U; 643 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 644 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 645 646 if (dd && dd->pport) { 647 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 648 if (words == ~0ULL) 649 ret = PCI_ERS_RESULT_NEED_RESET; 650 dd_dev_info(dd, 651 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", 652 words, ret); 653 } 654 return ret; 655 } 656 657 static pci_ers_result_t 658 pci_slot_reset(struct pci_dev *pdev) 659 { 660 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 661 662 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 663 return PCI_ERS_RESULT_CAN_RECOVER; 664 } 665 666 static void 667 pci_resume(struct pci_dev *pdev) 668 { 669 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 670 671 dd_dev_info(dd, "HFI1 resume function called\n"); 672 pci_cleanup_aer_uncorrect_error_status(pdev); 673 /* 674 * Running jobs will fail, since it's asynchronous 675 * unlike sysfs-requested reset. Better than 676 * doing nothing. 677 */ 678 hfi1_init(dd, 1); /* same as re-init after reset */ 679 } 680 681 const struct pci_error_handlers hfi1_pci_err_handler = { 682 .error_detected = pci_error_detected, 683 .mmio_enabled = pci_mmio_enabled, 684 .slot_reset = pci_slot_reset, 685 .resume = pci_resume, 686 }; 687 688 /*============================================================================*/ 689 /* PCIe Gen3 support */ 690 691 /* 692 * This code is separated out because it is expected to be removed in the 693 * final shipping product. If not, then it will be revisited and items 694 * will be moved to more standard locations. 695 */ 696 697 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 698 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 699 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 700 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 701 702 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 703 #define DL_ERR_NONE 0x0 /* no error */ 704 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 705 /* or response data */ 706 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 707 #define DL_ERR_SECURITY 0x3 /* security check failed */ 708 #define DL_ERR_SBUS 0x4 /* SBus status error */ 709 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 710 711 /* gasket block secondary bus reset delay */ 712 #define SBR_DELAY_US 200000 /* 200ms */ 713 714 /* mask for PCIe capability register lnkctl2 target link speed */ 715 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf 716 717 static uint pcie_target = 3; 718 module_param(pcie_target, uint, S_IRUGO); 719 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 720 721 static uint pcie_force; 722 module_param(pcie_force, uint, S_IRUGO); 723 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 724 725 static uint pcie_retry = 5; 726 module_param(pcie_retry, uint, S_IRUGO); 727 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 728 729 #define UNSET_PSET 255 730 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 731 #define DEFAULT_MCP_PSET 6 /* MCP HFI */ 732 static uint pcie_pset = UNSET_PSET; 733 module_param(pcie_pset, uint, S_IRUGO); 734 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 735 736 static uint pcie_ctle = 3; /* discrete on, integrated on */ 737 module_param(pcie_ctle, uint, S_IRUGO); 738 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 739 740 /* equalization columns */ 741 #define PREC 0 742 #define ATTN 1 743 #define POST 2 744 745 /* discrete silicon preliminary equalization values */ 746 static const u8 discrete_preliminary_eq[11][3] = { 747 /* prec attn post */ 748 { 0x00, 0x00, 0x12 }, /* p0 */ 749 { 0x00, 0x00, 0x0c }, /* p1 */ 750 { 0x00, 0x00, 0x0f }, /* p2 */ 751 { 0x00, 0x00, 0x09 }, /* p3 */ 752 { 0x00, 0x00, 0x00 }, /* p4 */ 753 { 0x06, 0x00, 0x00 }, /* p5 */ 754 { 0x09, 0x00, 0x00 }, /* p6 */ 755 { 0x06, 0x00, 0x0f }, /* p7 */ 756 { 0x09, 0x00, 0x09 }, /* p8 */ 757 { 0x0c, 0x00, 0x00 }, /* p9 */ 758 { 0x00, 0x00, 0x18 }, /* p10 */ 759 }; 760 761 /* integrated silicon preliminary equalization values */ 762 static const u8 integrated_preliminary_eq[11][3] = { 763 /* prec attn post */ 764 { 0x00, 0x1e, 0x07 }, /* p0 */ 765 { 0x00, 0x1e, 0x05 }, /* p1 */ 766 { 0x00, 0x1e, 0x06 }, /* p2 */ 767 { 0x00, 0x1e, 0x04 }, /* p3 */ 768 { 0x00, 0x1e, 0x00 }, /* p4 */ 769 { 0x03, 0x1e, 0x00 }, /* p5 */ 770 { 0x04, 0x1e, 0x00 }, /* p6 */ 771 { 0x03, 0x1e, 0x06 }, /* p7 */ 772 { 0x03, 0x1e, 0x04 }, /* p8 */ 773 { 0x05, 0x1e, 0x00 }, /* p9 */ 774 { 0x00, 0x1e, 0x0a }, /* p10 */ 775 }; 776 777 static const u8 discrete_ctle_tunings[11][4] = { 778 /* DC LF HF BW */ 779 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 780 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 781 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 782 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 783 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 784 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 785 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 786 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 787 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 788 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 789 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 790 }; 791 792 static const u8 integrated_ctle_tunings[11][4] = { 793 /* DC LF HF BW */ 794 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 795 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 796 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 797 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 798 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 799 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 800 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 801 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 802 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 803 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 804 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 805 }; 806 807 /* helper to format the value to write to hardware */ 808 #define eq_value(pre, curr, post) \ 809 ((((u32)(pre)) << \ 810 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 811 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 812 | (((u32)(post)) << \ 813 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 814 815 /* 816 * Load the given EQ preset table into the PCIe hardware. 817 */ 818 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 819 u8 div) 820 { 821 struct pci_dev *pdev = dd->pcidev; 822 u32 hit_error = 0; 823 u32 violation; 824 u32 i; 825 u8 c_minus1, c0, c_plus1; 826 int ret; 827 828 for (i = 0; i < 11; i++) { 829 /* set index */ 830 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 831 /* write the value */ 832 c_minus1 = eq[i][PREC] / div; 833 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 834 c_plus1 = eq[i][POST] / div; 835 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 836 eq_value(c_minus1, c0, c_plus1)); 837 /* check if these coefficients violate EQ rules */ 838 ret = pci_read_config_dword(dd->pcidev, 839 PCIE_CFG_REG_PL105, &violation); 840 if (ret) { 841 dd_dev_err(dd, "Unable to read from PCI config\n"); 842 hit_error = 1; 843 break; 844 } 845 846 if (violation 847 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 848 if (hit_error == 0) { 849 dd_dev_err(dd, 850 "Gen3 EQ Table Coefficient rule violations\n"); 851 dd_dev_err(dd, " prec attn post\n"); 852 } 853 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 854 i, (u32)eq[i][0], (u32)eq[i][1], 855 (u32)eq[i][2]); 856 dd_dev_err(dd, " %02x %02x %02x\n", 857 (u32)c_minus1, (u32)c0, (u32)c_plus1); 858 hit_error = 1; 859 } 860 } 861 if (hit_error) 862 return -EINVAL; 863 return 0; 864 } 865 866 /* 867 * Steps to be done after the PCIe firmware is downloaded and 868 * before the SBR for the Pcie Gen3. 869 * The SBus resource is already being held. 870 */ 871 static void pcie_post_steps(struct hfi1_devdata *dd) 872 { 873 int i; 874 875 set_sbus_fast_mode(dd); 876 /* 877 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 878 * This avoids a spurious framing error that can otherwise be 879 * generated by the MAC layer. 880 * 881 * Use individual addresses since no broadcast is set up. 882 */ 883 for (i = 0; i < NUM_PCIE_SERDES; i++) { 884 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 885 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 886 } 887 888 clear_sbus_fast_mode(dd); 889 } 890 891 /* 892 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 893 * 894 * Based on pci_parent_bus_reset() which is not exported by the 895 * kernel core. 896 */ 897 static int trigger_sbr(struct hfi1_devdata *dd) 898 { 899 struct pci_dev *dev = dd->pcidev; 900 struct pci_dev *pdev; 901 902 /* need a parent */ 903 if (!dev->bus->self) { 904 dd_dev_err(dd, "%s: no parent device\n", __func__); 905 return -ENOTTY; 906 } 907 908 /* should not be anyone else on the bus */ 909 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 910 if (pdev != dev) { 911 dd_dev_err(dd, 912 "%s: another device is on the same bus\n", 913 __func__); 914 return -ENOTTY; 915 } 916 917 /* 918 * A secondary bus reset (SBR) issues a hot reset to our device. 919 * The following routine does a 1s wait after the reset is dropped 920 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - 921 * Conventional Reset, paragraph 3, line 35 also says that a 1s 922 * delay after a reset is required. Per spec requirements, 923 * the link is either working or not after that point. 924 */ 925 pci_reset_bridge_secondary_bus(dev->bus->self); 926 927 return 0; 928 } 929 930 /* 931 * Write the given gasket interrupt register. 932 */ 933 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 934 u16 code, u16 data) 935 { 936 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 937 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 938 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 939 } 940 941 /* 942 * Tell the gasket logic how to react to the reset. 943 */ 944 static void arm_gasket_logic(struct hfi1_devdata *dd) 945 { 946 u64 reg; 947 948 reg = (((u64)1 << dd->hfi1_id) << 949 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 950 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 951 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 952 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 953 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 954 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 955 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 956 /* read back to push the write */ 957 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 958 } 959 960 /* 961 * CCE_PCIE_CTRL long name helpers 962 * We redefine these shorter macros to use in the code while leaving 963 * chip_registers.h to be autogenerated from the hardware spec. 964 */ 965 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 966 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 967 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 968 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 969 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 970 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 971 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 972 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 973 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 974 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 975 976 /* 977 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 978 */ 979 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 980 { 981 u64 pcie_ctrl; 982 u64 xmt_margin; 983 u64 xmt_margin_oe; 984 u64 lane_delay; 985 u64 lane_bundle; 986 987 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 988 989 /* 990 * For Discrete, use full-swing. 991 * - PCIe TX defaults to full-swing. 992 * Leave this register as default. 993 * For Integrated, use half-swing 994 * - Copy xmt_margin and xmt_margin_oe 995 * from Gen1/Gen2 to Gen3. 996 */ 997 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 998 /* extract initial fields */ 999 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 1000 & MARGIN_GEN1_GEN2_MASK; 1001 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 1002 & MARGIN_G1_G2_OVERWRITE_MASK; 1003 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 1004 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 1005 & LANE_BUNDLE_MASK; 1006 1007 /* 1008 * For A0, EFUSE values are not set. Override with the 1009 * correct values. 1010 */ 1011 if (is_ax(dd)) { 1012 /* 1013 * xmt_margin and OverwiteEnabel should be the 1014 * same for Gen1/Gen2 and Gen3 1015 */ 1016 xmt_margin = 0x5; 1017 xmt_margin_oe = 0x1; 1018 lane_delay = 0xF; /* Delay 240ns. */ 1019 lane_bundle = 0x0; /* Set to 1 lane. */ 1020 } 1021 1022 /* overwrite existing values */ 1023 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 1024 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 1025 | (xmt_margin << MARGIN_SHIFT) 1026 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 1027 | (lane_delay << LANE_DELAY_SHIFT) 1028 | (lane_bundle << LANE_BUNDLE_SHIFT); 1029 1030 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 1031 } 1032 1033 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 1034 fname, pcie_ctrl); 1035 } 1036 1037 /* 1038 * Do all the steps needed to transition the PCIe link to Gen3 speed. 1039 */ 1040 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 1041 { 1042 struct pci_dev *parent = dd->pcidev->bus->self; 1043 u64 fw_ctrl; 1044 u64 reg, therm; 1045 u32 reg32, fs, lf; 1046 u32 status, err; 1047 int ret; 1048 int do_retry, retry_count = 0; 1049 int intnum = 0; 1050 uint default_pset; 1051 u16 target_vector, target_speed; 1052 u16 lnkctl2, vendor; 1053 u8 div; 1054 const u8 (*eq)[3]; 1055 const u8 (*ctle_tunings)[4]; 1056 uint static_ctle_mode; 1057 int return_error = 0; 1058 1059 /* PCIe Gen3 is for the ASIC only */ 1060 if (dd->icode != ICODE_RTL_SILICON) 1061 return 0; 1062 1063 if (pcie_target == 1) { /* target Gen1 */ 1064 target_vector = GEN1_SPEED_VECTOR; 1065 target_speed = 2500; 1066 } else if (pcie_target == 2) { /* target Gen2 */ 1067 target_vector = GEN2_SPEED_VECTOR; 1068 target_speed = 5000; 1069 } else if (pcie_target == 3) { /* target Gen3 */ 1070 target_vector = GEN3_SPEED_VECTOR; 1071 target_speed = 8000; 1072 } else { 1073 /* off or invalid target - skip */ 1074 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 1075 return 0; 1076 } 1077 1078 /* if already at target speed, done (unless forced) */ 1079 if (dd->lbus_speed == target_speed) { 1080 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 1081 pcie_target, 1082 pcie_force ? "re-doing anyway" : "skipping"); 1083 if (!pcie_force) 1084 return 0; 1085 } 1086 1087 /* 1088 * The driver cannot do the transition if it has no access to the 1089 * upstream component 1090 */ 1091 if (!parent) { 1092 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 1093 __func__); 1094 return 0; 1095 } 1096 1097 /* 1098 * Do the Gen3 transition. Steps are those of the PCIe Gen3 1099 * recipe. 1100 */ 1101 1102 /* step 1: pcie link working in gen1/gen2 */ 1103 1104 /* step 2: if either side is not capable of Gen3, done */ 1105 if (pcie_target == 3 && !dd->link_gen3_capable) { 1106 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1107 ret = -ENOSYS; 1108 goto done_no_mutex; 1109 } 1110 1111 /* hold the SBus resource across the firmware download and SBR */ 1112 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1113 if (ret) { 1114 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1115 __func__); 1116 return ret; 1117 } 1118 1119 /* make sure thermal polling is not causing interrupts */ 1120 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1121 if (therm) { 1122 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1123 msleep(100); 1124 dd_dev_info(dd, "%s: Disabled therm polling\n", 1125 __func__); 1126 } 1127 1128 retry: 1129 /* the SBus download will reset the spico for thermal */ 1130 1131 /* step 3: download SBus Master firmware */ 1132 /* step 4: download PCIe Gen3 SerDes firmware */ 1133 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1134 ret = load_pcie_firmware(dd); 1135 if (ret) { 1136 /* do not proceed if the firmware cannot be downloaded */ 1137 return_error = 1; 1138 goto done; 1139 } 1140 1141 /* step 5: set up device parameter settings */ 1142 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1143 1144 /* 1145 * PcieCfgSpcie1 - Link Control 3 1146 * Leave at reset value. No need to set PerfEq - link equalization 1147 * will be performed automatically after the SBR when the target 1148 * speed is 8GT/s. 1149 */ 1150 1151 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1152 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1153 1154 /* step 5a: Set Synopsys Port Logic registers */ 1155 1156 /* 1157 * PcieCfgRegPl2 - Port Force Link 1158 * 1159 * Set the low power field to 0x10 to avoid unnecessary power 1160 * management messages. All other fields are zero. 1161 */ 1162 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1163 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1164 1165 /* 1166 * PcieCfgRegPl100 - Gen3 Control 1167 * 1168 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1169 * turn on PcieCfgRegPl100.EqEieosCnt 1170 * Everything else zero. 1171 */ 1172 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1173 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1174 1175 /* 1176 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1177 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1178 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1179 * PcieCfgRegPl105 - Gen3 EQ Status 1180 * 1181 * Give initial EQ settings. 1182 */ 1183 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1184 /* 1000mV, FS=24, LF = 8 */ 1185 fs = 24; 1186 lf = 8; 1187 div = 3; 1188 eq = discrete_preliminary_eq; 1189 default_pset = DEFAULT_DISCRETE_PSET; 1190 ctle_tunings = discrete_ctle_tunings; 1191 /* bit 0 - discrete on/off */ 1192 static_ctle_mode = pcie_ctle & 0x1; 1193 } else { 1194 /* 400mV, FS=29, LF = 9 */ 1195 fs = 29; 1196 lf = 9; 1197 div = 1; 1198 eq = integrated_preliminary_eq; 1199 default_pset = DEFAULT_MCP_PSET; 1200 ctle_tunings = integrated_ctle_tunings; 1201 /* bit 1 - integrated on/off */ 1202 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1203 } 1204 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1205 (fs << 1206 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1207 (lf << 1208 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1209 ret = load_eq_table(dd, eq, fs, div); 1210 if (ret) 1211 goto done; 1212 1213 /* 1214 * PcieCfgRegPl106 - Gen3 EQ Control 1215 * 1216 * Set Gen3EqPsetReqVec, leave other fields 0. 1217 */ 1218 if (pcie_pset == UNSET_PSET) 1219 pcie_pset = default_pset; 1220 if (pcie_pset > 10) { /* valid range is 0-10, inclusive */ 1221 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1222 __func__, pcie_pset, default_pset); 1223 pcie_pset = default_pset; 1224 } 1225 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset); 1226 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1227 ((1 << pcie_pset) << 1228 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1229 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1230 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1231 1232 /* 1233 * step 5b: Do post firmware download steps via SBus 1234 */ 1235 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1236 pcie_post_steps(dd); 1237 1238 /* 1239 * step 5c: Program gasket interrupts 1240 */ 1241 /* set the Rx Bit Rate to REFCLK ratio */ 1242 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1243 /* disable pCal for PCIe Gen3 RX equalization */ 1244 /* select adaptive or static CTLE */ 1245 write_gasket_interrupt(dd, intnum++, 0x0026, 1246 0x5b01 | (static_ctle_mode << 3)); 1247 /* 1248 * Enable iCal for PCIe Gen3 RX equalization, and set which 1249 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1250 */ 1251 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1252 1253 if (static_ctle_mode) { 1254 /* apply static CTLE tunings */ 1255 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1256 1257 pcie_dc = ctle_tunings[pcie_pset][0]; 1258 pcie_lf = ctle_tunings[pcie_pset][1]; 1259 pcie_hf = ctle_tunings[pcie_pset][2]; 1260 pcie_bw = ctle_tunings[pcie_pset][3]; 1261 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1262 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1263 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1264 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1265 } 1266 1267 /* terminate list */ 1268 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1269 1270 /* 1271 * step 5d: program XMT margin 1272 */ 1273 write_xmt_margin(dd, __func__); 1274 1275 /* 1276 * step 5e: disable active state power management (ASPM). It 1277 * will be enabled if required later 1278 */ 1279 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1280 aspm_hw_disable_l1(dd); 1281 1282 /* 1283 * step 5f: clear DirectSpeedChange 1284 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1285 * change in the speed target from starting before we are ready. 1286 * This field defaults to 0 and we are not changing it, so nothing 1287 * needs to be done. 1288 */ 1289 1290 /* step 5g: Set target link speed */ 1291 /* 1292 * Set target link speed to be target on both device and parent. 1293 * On setting the parent: Some system BIOSs "helpfully" set the 1294 * parent target speed to Gen2 to match the ASIC's initial speed. 1295 * We can set the target Gen3 because we have already checked 1296 * that it is Gen3 capable earlier. 1297 */ 1298 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1299 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1300 if (ret) { 1301 dd_dev_err(dd, "Unable to read from PCI config\n"); 1302 return_error = 1; 1303 goto done; 1304 } 1305 1306 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1307 (u32)lnkctl2); 1308 /* only write to parent if target is not as high as ours */ 1309 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) { 1310 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1311 lnkctl2 |= target_vector; 1312 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1313 (u32)lnkctl2); 1314 ret = pcie_capability_write_word(parent, 1315 PCI_EXP_LNKCTL2, lnkctl2); 1316 if (ret) { 1317 dd_dev_err(dd, "Unable to write to PCI config\n"); 1318 return_error = 1; 1319 goto done; 1320 } 1321 } else { 1322 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1323 } 1324 1325 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1326 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1327 if (ret) { 1328 dd_dev_err(dd, "Unable to read from PCI config\n"); 1329 return_error = 1; 1330 goto done; 1331 } 1332 1333 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1334 (u32)lnkctl2); 1335 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1336 lnkctl2 |= target_vector; 1337 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1338 (u32)lnkctl2); 1339 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1340 if (ret) { 1341 dd_dev_err(dd, "Unable to write to PCI config\n"); 1342 return_error = 1; 1343 goto done; 1344 } 1345 1346 /* step 5h: arm gasket logic */ 1347 /* hold DC in reset across the SBR */ 1348 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1349 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1350 /* save firmware control across the SBR */ 1351 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1352 1353 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1354 arm_gasket_logic(dd); 1355 1356 /* 1357 * step 6: quiesce PCIe link 1358 * The chip has already been reset, so there will be no traffic 1359 * from the chip. Linux has no easy way to enforce that it will 1360 * not try to access the device, so we just need to hope it doesn't 1361 * do it while we are doing the reset. 1362 */ 1363 1364 /* 1365 * step 7: initiate the secondary bus reset (SBR) 1366 * step 8: hardware brings the links back up 1367 * step 9: wait for link speed transition to be complete 1368 */ 1369 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1370 ret = trigger_sbr(dd); 1371 if (ret) 1372 goto done; 1373 1374 /* step 10: decide what to do next */ 1375 1376 /* check if we can read PCI space */ 1377 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1378 if (ret) { 1379 dd_dev_info(dd, 1380 "%s: read of VendorID failed after SBR, err %d\n", 1381 __func__, ret); 1382 return_error = 1; 1383 goto done; 1384 } 1385 if (vendor == 0xffff) { 1386 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1387 return_error = 1; 1388 ret = -EIO; 1389 goto done; 1390 } 1391 1392 /* restore PCI space registers we know were reset */ 1393 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1394 ret = restore_pci_variables(dd); 1395 if (ret) { 1396 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 1397 __func__); 1398 return_error = 1; 1399 goto done; 1400 } 1401 1402 /* restore firmware control */ 1403 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1404 1405 /* 1406 * Check the gasket block status. 1407 * 1408 * This is the first CSR read after the SBR. If the read returns 1409 * all 1s (fails), the link did not make it back. 1410 * 1411 * Once we're sure we can read and write, clear the DC reset after 1412 * the SBR. Then check for any per-lane errors. Then look over 1413 * the status. 1414 */ 1415 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1416 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1417 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1418 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1419 return_error = 1; 1420 ret = -ENOSYS; 1421 goto done; 1422 } 1423 1424 /* clear the DC reset */ 1425 write_csr(dd, CCE_DC_CTRL, 0); 1426 1427 /* Set the LED off */ 1428 setextled(dd, 0); 1429 1430 /* check for any per-lane errors */ 1431 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1432 if (ret) { 1433 dd_dev_err(dd, "Unable to read from PCI config\n"); 1434 return_error = 1; 1435 goto done; 1436 } 1437 1438 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1439 1440 /* extract status, look for our HFI */ 1441 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1442 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1443 if ((status & (1 << dd->hfi1_id)) == 0) { 1444 dd_dev_err(dd, 1445 "%s: gasket status 0x%x, expecting 0x%x\n", 1446 __func__, status, 1 << dd->hfi1_id); 1447 ret = -EIO; 1448 goto done; 1449 } 1450 1451 /* extract error */ 1452 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1453 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1454 if (err) { 1455 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1456 ret = -EIO; 1457 goto done; 1458 } 1459 1460 /* update our link information cache */ 1461 update_lbus_info(dd); 1462 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1463 dd->lbus_info); 1464 1465 if (dd->lbus_speed != target_speed) { /* not target */ 1466 /* maybe retry */ 1467 do_retry = retry_count < pcie_retry; 1468 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", 1469 pcie_target, do_retry ? ", retrying" : ""); 1470 retry_count++; 1471 if (do_retry) { 1472 msleep(100); /* allow time to settle */ 1473 goto retry; 1474 } 1475 ret = -EIO; 1476 } 1477 1478 done: 1479 if (therm) { 1480 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1481 msleep(100); 1482 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1483 __func__); 1484 } 1485 release_chip_resource(dd, CR_SBUS); 1486 done_no_mutex: 1487 /* return no error if it is OK to be at current speed */ 1488 if (ret && !return_error) { 1489 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1490 ret = 0; 1491 } 1492 1493 dd_dev_info(dd, "%s: done\n", __func__); 1494 return ret; 1495 } 1496