1 /* 2 * Copyright(c) 2015 - 2017 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* link speed vector for Gen3 speed - not in Linux headers */ 60 #define GEN1_SPEED_VECTOR 0x1 61 #define GEN2_SPEED_VECTOR 0x2 62 #define GEN3_SPEED_VECTOR 0x3 63 64 /* 65 * This file contains PCIe utility routines. 66 */ 67 68 /* 69 * Code to adjust PCIe capabilities. 70 */ 71 static void tune_pcie_caps(struct hfi1_devdata *); 72 73 /* 74 * Do all the common PCIe setup and initialization. 75 * devdata is not yet allocated, and is not allocated until after this 76 * routine returns success. Therefore dd_dev_err() can't be used for error 77 * printing. 78 */ 79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 80 { 81 int ret; 82 83 ret = pci_enable_device(pdev); 84 if (ret) { 85 /* 86 * This can happen (in theory) iff: 87 * We did a chip reset, and then failed to reprogram the 88 * BAR, or the chip reset due to an internal error. We then 89 * unloaded the driver and reloaded it. 90 * 91 * Both reset cases set the BAR back to initial state. For 92 * the latter case, the AER sticky error bit at offset 0x718 93 * should be set, but the Linux kernel doesn't yet know 94 * about that, it appears. If the original BAR was retained 95 * in the kernel data structures, this may be OK. 96 */ 97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", 98 -ret); 99 goto done; 100 } 101 102 ret = pci_request_regions(pdev, DRIVER_NAME); 103 if (ret) { 104 hfi1_early_err(&pdev->dev, 105 "pci_request_regions fails: err %d\n", -ret); 106 goto bail; 107 } 108 109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 110 if (ret) { 111 /* 112 * If the 64 bit setup fails, try 32 bit. Some systems 113 * do not setup 64 bit maps on systems with 2GB or less 114 * memory installed. 115 */ 116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 117 if (ret) { 118 hfi1_early_err(&pdev->dev, 119 "Unable to set DMA mask: %d\n", ret); 120 goto bail; 121 } 122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 123 } else { 124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 125 } 126 if (ret) { 127 hfi1_early_err(&pdev->dev, 128 "Unable to set DMA consistent mask: %d\n", ret); 129 goto bail; 130 } 131 132 pci_set_master(pdev); 133 (void)pci_enable_pcie_error_reporting(pdev); 134 goto done; 135 136 bail: 137 hfi1_pcie_cleanup(pdev); 138 done: 139 return ret; 140 } 141 142 /* 143 * Clean what was done in hfi1_pcie_init() 144 */ 145 void hfi1_pcie_cleanup(struct pci_dev *pdev) 146 { 147 pci_disable_device(pdev); 148 /* 149 * Release regions should be called after the disable. OK to 150 * call if request regions has not been called or failed. 151 */ 152 pci_release_regions(pdev); 153 } 154 155 /* 156 * Do remaining PCIe setup, once dd is allocated, and save away 157 * fields required to re-initialize after a chip reset, or for 158 * various other purposes 159 */ 160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 161 { 162 unsigned long len; 163 resource_size_t addr; 164 int ret = 0; 165 166 dd->pcidev = pdev; 167 pci_set_drvdata(pdev, dd); 168 169 addr = pci_resource_start(pdev, 0); 170 len = pci_resource_len(pdev, 0); 171 172 /* 173 * The TXE PIO buffers are at the tail end of the chip space. 174 * Cut them off and map them separately. 175 */ 176 177 /* sanity check vs expectations */ 178 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 179 dd_dev_err(dd, "chip PIO range does not match\n"); 180 return -EINVAL; 181 } 182 183 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY); 184 if (!dd->kregbase1) { 185 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); 186 return -ENOMEM; 187 } 188 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); 189 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); 190 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count); 191 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8; 192 193 dd->kregbase2 = ioremap_nocache( 194 addr + dd->base2_start, 195 TXE_PIO_SEND - dd->base2_start); 196 if (!dd->kregbase2) { 197 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); 198 goto nomem; 199 } 200 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, 201 TXE_PIO_SEND - dd->base2_start); 202 203 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 204 if (!dd->piobase) { 205 dd_dev_err(dd, "WC mapping of send buffers failed\n"); 206 goto nomem; 207 } 208 dd_dev_info(dd, "WC piobase: %p\n for %x", dd->piobase, TXE_PIO_SIZE); 209 210 dd->physaddr = addr; /* used for io_remap, etc. */ 211 212 /* 213 * Map the chip's RcvArray as write-combining to allow us 214 * to write an entire cacheline worth of entries in one shot. 215 */ 216 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 217 dd->chip_rcv_array_count * 8); 218 if (!dd->rcvarray_wc) { 219 dd_dev_err(dd, "WC mapping of receive array failed\n"); 220 goto nomem; 221 } 222 dd_dev_info(dd, "WC RcvArray: %p for %x\n", 223 dd->rcvarray_wc, dd->chip_rcv_array_count * 8); 224 225 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ 226 return 0; 227 nomem: 228 ret = -ENOMEM; 229 hfi1_pcie_ddcleanup(dd); 230 return ret; 231 } 232 233 /* 234 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 235 * to releasing the dd memory. 236 * Void because all of the core pcie cleanup functions are void. 237 */ 238 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 239 { 240 dd->flags &= ~HFI1_PRESENT; 241 if (dd->kregbase1) 242 iounmap(dd->kregbase1); 243 dd->kregbase1 = NULL; 244 if (dd->kregbase2) 245 iounmap(dd->kregbase2); 246 dd->kregbase2 = NULL; 247 if (dd->rcvarray_wc) 248 iounmap(dd->rcvarray_wc); 249 dd->rcvarray_wc = NULL; 250 if (dd->piobase) 251 iounmap(dd->piobase); 252 dd->piobase = NULL; 253 } 254 255 /* return the PCIe link speed from the given link status */ 256 static u32 extract_speed(u16 linkstat) 257 { 258 u32 speed; 259 260 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 261 default: /* not defined, assume Gen1 */ 262 case PCI_EXP_LNKSTA_CLS_2_5GB: 263 speed = 2500; /* Gen 1, 2.5GHz */ 264 break; 265 case PCI_EXP_LNKSTA_CLS_5_0GB: 266 speed = 5000; /* Gen 2, 5GHz */ 267 break; 268 case GEN3_SPEED_VECTOR: 269 speed = 8000; /* Gen 3, 8GHz */ 270 break; 271 } 272 return speed; 273 } 274 275 /* return the PCIe link speed from the given link status */ 276 static u32 extract_width(u16 linkstat) 277 { 278 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 279 } 280 281 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 282 static void update_lbus_info(struct hfi1_devdata *dd) 283 { 284 u16 linkstat; 285 int ret; 286 287 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 288 if (ret) { 289 dd_dev_err(dd, "Unable to read from PCI config\n"); 290 return; 291 } 292 293 dd->lbus_width = extract_width(linkstat); 294 dd->lbus_speed = extract_speed(linkstat); 295 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 296 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 297 } 298 299 /* 300 * Read in the current PCIe link width and speed. Find if the link is 301 * Gen3 capable. 302 */ 303 int pcie_speeds(struct hfi1_devdata *dd) 304 { 305 u32 linkcap; 306 struct pci_dev *parent = dd->pcidev->bus->self; 307 int ret; 308 309 if (!pci_is_pcie(dd->pcidev)) { 310 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 311 return -EINVAL; 312 } 313 314 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 315 dd->link_gen3_capable = 1; 316 317 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 318 if (ret) { 319 dd_dev_err(dd, "Unable to read from PCI config\n"); 320 return ret; 321 } 322 323 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) { 324 dd_dev_info(dd, 325 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 326 linkcap & PCI_EXP_LNKCAP_SLS); 327 dd->link_gen3_capable = 0; 328 } 329 330 /* 331 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 332 */ 333 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 334 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 335 dd->link_gen3_capable = 0; 336 } 337 338 /* obtain the link width and current speed */ 339 update_lbus_info(dd); 340 341 dd_dev_info(dd, "%s\n", dd->lbus_info); 342 343 return 0; 344 } 345 346 /* 347 * Returns: 348 * - actual number of interrupts allocated or 349 * - 0 if fell back to INTx. 350 * - error 351 */ 352 int request_msix(struct hfi1_devdata *dd, u32 msireq) 353 { 354 int nvec; 355 356 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq, 357 PCI_IRQ_MSIX | PCI_IRQ_LEGACY); 358 if (nvec < 0) { 359 dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", nvec); 360 return nvec; 361 } 362 363 tune_pcie_caps(dd); 364 365 /* check for legacy IRQ */ 366 if (nvec == 1 && !dd->pcidev->msix_enabled) 367 return 0; 368 369 return nvec; 370 } 371 372 /* restore command and BARs after a reset has wiped them out */ 373 int restore_pci_variables(struct hfi1_devdata *dd) 374 { 375 int ret = 0; 376 377 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 378 if (ret) 379 goto error; 380 381 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 382 dd->pcibar0); 383 if (ret) 384 goto error; 385 386 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 387 dd->pcibar1); 388 if (ret) 389 goto error; 390 391 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 392 if (ret) 393 goto error; 394 395 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, 396 dd->pcie_devctl); 397 if (ret) 398 goto error; 399 400 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, 401 dd->pcie_lnkctl); 402 if (ret) 403 goto error; 404 405 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 406 dd->pcie_devctl2); 407 if (ret) 408 goto error; 409 410 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 411 if (ret) 412 goto error; 413 414 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, 415 dd->pci_lnkctl3); 416 if (ret) 417 goto error; 418 419 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2); 420 if (ret) 421 goto error; 422 423 return 0; 424 425 error: 426 dd_dev_err(dd, "Unable to write to PCI config\n"); 427 return ret; 428 } 429 430 /* Save BARs and command to rewrite after device reset */ 431 int save_pci_variables(struct hfi1_devdata *dd) 432 { 433 int ret = 0; 434 435 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 436 &dd->pcibar0); 437 if (ret) 438 goto error; 439 440 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 441 &dd->pcibar1); 442 if (ret) 443 goto error; 444 445 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 446 if (ret) 447 goto error; 448 449 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 450 if (ret) 451 goto error; 452 453 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, 454 &dd->pcie_devctl); 455 if (ret) 456 goto error; 457 458 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, 459 &dd->pcie_lnkctl); 460 if (ret) 461 goto error; 462 463 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 464 &dd->pcie_devctl2); 465 if (ret) 466 goto error; 467 468 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 469 if (ret) 470 goto error; 471 472 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, 473 &dd->pci_lnkctl3); 474 if (ret) 475 goto error; 476 477 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2); 478 if (ret) 479 goto error; 480 481 return 0; 482 483 error: 484 dd_dev_err(dd, "Unable to read from PCI config\n"); 485 return ret; 486 } 487 488 /* 489 * BIOS may not set PCIe bus-utilization parameters for best performance. 490 * Check and optionally adjust them to maximize our throughput. 491 */ 492 static int hfi1_pcie_caps; 493 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); 494 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 495 496 uint aspm_mode = ASPM_MODE_DISABLED; 497 module_param_named(aspm, aspm_mode, uint, S_IRUGO); 498 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); 499 500 static void tune_pcie_caps(struct hfi1_devdata *dd) 501 { 502 struct pci_dev *parent; 503 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 504 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 505 int ret; 506 507 /* 508 * Turn on extended tags in DevCtl in case the BIOS has turned it off 509 * to improve WFR SDMA bandwidth 510 */ 511 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); 512 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 513 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 514 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 515 ret = pcie_capability_write_word(dd->pcidev, 516 PCI_EXP_DEVCTL, ectl); 517 if (ret) 518 dd_dev_info(dd, "Unable to write to PCI config\n"); 519 } 520 /* Find out supported and configured values for parent (root) */ 521 parent = dd->pcidev->bus->self; 522 /* 523 * The driver cannot perform the tuning if it does not have 524 * access to the upstream component. 525 */ 526 if (!parent) { 527 dd_dev_info(dd, "Parent not found\n"); 528 return; 529 } 530 if (!pci_is_root_bus(parent->bus)) { 531 dd_dev_info(dd, "Parent not root\n"); 532 return; 533 } 534 if (!pci_is_pcie(parent)) { 535 dd_dev_info(dd, "Parent is not PCI Express capable\n"); 536 return; 537 } 538 if (!pci_is_pcie(dd->pcidev)) { 539 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); 540 return; 541 } 542 rc_mpss = parent->pcie_mpss; 543 rc_mps = ffs(pcie_get_mps(parent)) - 8; 544 /* Find out supported and configured values for endpoint (us) */ 545 ep_mpss = dd->pcidev->pcie_mpss; 546 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 547 548 /* Find max payload supported by root, endpoint */ 549 if (rc_mpss > ep_mpss) 550 rc_mpss = ep_mpss; 551 552 /* If Supported greater than limit in module param, limit it */ 553 if (rc_mpss > (hfi1_pcie_caps & 7)) 554 rc_mpss = hfi1_pcie_caps & 7; 555 /* If less than (allowed, supported), bump root payload */ 556 if (rc_mpss > rc_mps) { 557 rc_mps = rc_mpss; 558 pcie_set_mps(parent, 128 << rc_mps); 559 } 560 /* If less than (allowed, supported), bump endpoint payload */ 561 if (rc_mpss > ep_mps) { 562 ep_mps = rc_mpss; 563 pcie_set_mps(dd->pcidev, 128 << ep_mps); 564 } 565 566 /* 567 * Now the Read Request size. 568 * No field for max supported, but PCIe spec limits it to 4096, 569 * which is code '5' (log2(4096) - 7) 570 */ 571 max_mrrs = 5; 572 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 573 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 574 575 max_mrrs = 128 << max_mrrs; 576 rc_mrrs = pcie_get_readrq(parent); 577 ep_mrrs = pcie_get_readrq(dd->pcidev); 578 579 if (max_mrrs > rc_mrrs) { 580 rc_mrrs = max_mrrs; 581 pcie_set_readrq(parent, rc_mrrs); 582 } 583 if (max_mrrs > ep_mrrs) { 584 ep_mrrs = max_mrrs; 585 pcie_set_readrq(dd->pcidev, ep_mrrs); 586 } 587 } 588 589 /* End of PCIe capability tuning */ 590 591 /* 592 * From here through hfi1_pci_err_handler definition is invoked via 593 * PCI error infrastructure, registered via pci 594 */ 595 static pci_ers_result_t 596 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 597 { 598 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 599 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 600 601 switch (state) { 602 case pci_channel_io_normal: 603 dd_dev_info(dd, "State Normal, ignoring\n"); 604 break; 605 606 case pci_channel_io_frozen: 607 dd_dev_info(dd, "State Frozen, requesting reset\n"); 608 pci_disable_device(pdev); 609 ret = PCI_ERS_RESULT_NEED_RESET; 610 break; 611 612 case pci_channel_io_perm_failure: 613 if (dd) { 614 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 615 /* no more register accesses! */ 616 dd->flags &= ~HFI1_PRESENT; 617 hfi1_disable_after_error(dd); 618 } 619 /* else early, or other problem */ 620 ret = PCI_ERS_RESULT_DISCONNECT; 621 break; 622 623 default: /* shouldn't happen */ 624 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 625 state); 626 break; 627 } 628 return ret; 629 } 630 631 static pci_ers_result_t 632 pci_mmio_enabled(struct pci_dev *pdev) 633 { 634 u64 words = 0U; 635 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 636 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 637 638 if (dd && dd->pport) { 639 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 640 if (words == ~0ULL) 641 ret = PCI_ERS_RESULT_NEED_RESET; 642 dd_dev_info(dd, 643 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", 644 words, ret); 645 } 646 return ret; 647 } 648 649 static pci_ers_result_t 650 pci_slot_reset(struct pci_dev *pdev) 651 { 652 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 653 654 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 655 return PCI_ERS_RESULT_CAN_RECOVER; 656 } 657 658 static void 659 pci_resume(struct pci_dev *pdev) 660 { 661 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 662 663 dd_dev_info(dd, "HFI1 resume function called\n"); 664 pci_cleanup_aer_uncorrect_error_status(pdev); 665 /* 666 * Running jobs will fail, since it's asynchronous 667 * unlike sysfs-requested reset. Better than 668 * doing nothing. 669 */ 670 hfi1_init(dd, 1); /* same as re-init after reset */ 671 } 672 673 const struct pci_error_handlers hfi1_pci_err_handler = { 674 .error_detected = pci_error_detected, 675 .mmio_enabled = pci_mmio_enabled, 676 .slot_reset = pci_slot_reset, 677 .resume = pci_resume, 678 }; 679 680 /*============================================================================*/ 681 /* PCIe Gen3 support */ 682 683 /* 684 * This code is separated out because it is expected to be removed in the 685 * final shipping product. If not, then it will be revisited and items 686 * will be moved to more standard locations. 687 */ 688 689 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 690 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 691 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 692 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 693 694 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 695 #define DL_ERR_NONE 0x0 /* no error */ 696 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 697 /* or response data */ 698 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 699 #define DL_ERR_SECURITY 0x3 /* security check failed */ 700 #define DL_ERR_SBUS 0x4 /* SBus status error */ 701 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 702 703 /* gasket block secondary bus reset delay */ 704 #define SBR_DELAY_US 200000 /* 200ms */ 705 706 /* mask for PCIe capability register lnkctl2 target link speed */ 707 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf 708 709 static uint pcie_target = 3; 710 module_param(pcie_target, uint, S_IRUGO); 711 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 712 713 static uint pcie_force; 714 module_param(pcie_force, uint, S_IRUGO); 715 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 716 717 static uint pcie_retry = 5; 718 module_param(pcie_retry, uint, S_IRUGO); 719 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 720 721 #define UNSET_PSET 255 722 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 723 #define DEFAULT_MCP_PSET 6 /* MCP HFI */ 724 static uint pcie_pset = UNSET_PSET; 725 module_param(pcie_pset, uint, S_IRUGO); 726 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 727 728 static uint pcie_ctle = 3; /* discrete on, integrated on */ 729 module_param(pcie_ctle, uint, S_IRUGO); 730 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 731 732 /* equalization columns */ 733 #define PREC 0 734 #define ATTN 1 735 #define POST 2 736 737 /* discrete silicon preliminary equalization values */ 738 static const u8 discrete_preliminary_eq[11][3] = { 739 /* prec attn post */ 740 { 0x00, 0x00, 0x12 }, /* p0 */ 741 { 0x00, 0x00, 0x0c }, /* p1 */ 742 { 0x00, 0x00, 0x0f }, /* p2 */ 743 { 0x00, 0x00, 0x09 }, /* p3 */ 744 { 0x00, 0x00, 0x00 }, /* p4 */ 745 { 0x06, 0x00, 0x00 }, /* p5 */ 746 { 0x09, 0x00, 0x00 }, /* p6 */ 747 { 0x06, 0x00, 0x0f }, /* p7 */ 748 { 0x09, 0x00, 0x09 }, /* p8 */ 749 { 0x0c, 0x00, 0x00 }, /* p9 */ 750 { 0x00, 0x00, 0x18 }, /* p10 */ 751 }; 752 753 /* integrated silicon preliminary equalization values */ 754 static const u8 integrated_preliminary_eq[11][3] = { 755 /* prec attn post */ 756 { 0x00, 0x1e, 0x07 }, /* p0 */ 757 { 0x00, 0x1e, 0x05 }, /* p1 */ 758 { 0x00, 0x1e, 0x06 }, /* p2 */ 759 { 0x00, 0x1e, 0x04 }, /* p3 */ 760 { 0x00, 0x1e, 0x00 }, /* p4 */ 761 { 0x03, 0x1e, 0x00 }, /* p5 */ 762 { 0x04, 0x1e, 0x00 }, /* p6 */ 763 { 0x03, 0x1e, 0x06 }, /* p7 */ 764 { 0x03, 0x1e, 0x04 }, /* p8 */ 765 { 0x05, 0x1e, 0x00 }, /* p9 */ 766 { 0x00, 0x1e, 0x0a }, /* p10 */ 767 }; 768 769 static const u8 discrete_ctle_tunings[11][4] = { 770 /* DC LF HF BW */ 771 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 772 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 773 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 774 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 775 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 776 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 777 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 778 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 779 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 780 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 781 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 782 }; 783 784 static const u8 integrated_ctle_tunings[11][4] = { 785 /* DC LF HF BW */ 786 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 787 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 788 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 789 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 790 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 791 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 792 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 793 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 794 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 795 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 796 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 797 }; 798 799 /* helper to format the value to write to hardware */ 800 #define eq_value(pre, curr, post) \ 801 ((((u32)(pre)) << \ 802 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 803 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 804 | (((u32)(post)) << \ 805 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 806 807 /* 808 * Load the given EQ preset table into the PCIe hardware. 809 */ 810 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 811 u8 div) 812 { 813 struct pci_dev *pdev = dd->pcidev; 814 u32 hit_error = 0; 815 u32 violation; 816 u32 i; 817 u8 c_minus1, c0, c_plus1; 818 int ret; 819 820 for (i = 0; i < 11; i++) { 821 /* set index */ 822 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 823 /* write the value */ 824 c_minus1 = eq[i][PREC] / div; 825 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 826 c_plus1 = eq[i][POST] / div; 827 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 828 eq_value(c_minus1, c0, c_plus1)); 829 /* check if these coefficients violate EQ rules */ 830 ret = pci_read_config_dword(dd->pcidev, 831 PCIE_CFG_REG_PL105, &violation); 832 if (ret) { 833 dd_dev_err(dd, "Unable to read from PCI config\n"); 834 hit_error = 1; 835 break; 836 } 837 838 if (violation 839 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 840 if (hit_error == 0) { 841 dd_dev_err(dd, 842 "Gen3 EQ Table Coefficient rule violations\n"); 843 dd_dev_err(dd, " prec attn post\n"); 844 } 845 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 846 i, (u32)eq[i][0], (u32)eq[i][1], 847 (u32)eq[i][2]); 848 dd_dev_err(dd, " %02x %02x %02x\n", 849 (u32)c_minus1, (u32)c0, (u32)c_plus1); 850 hit_error = 1; 851 } 852 } 853 if (hit_error) 854 return -EINVAL; 855 return 0; 856 } 857 858 /* 859 * Steps to be done after the PCIe firmware is downloaded and 860 * before the SBR for the Pcie Gen3. 861 * The SBus resource is already being held. 862 */ 863 static void pcie_post_steps(struct hfi1_devdata *dd) 864 { 865 int i; 866 867 set_sbus_fast_mode(dd); 868 /* 869 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 870 * This avoids a spurious framing error that can otherwise be 871 * generated by the MAC layer. 872 * 873 * Use individual addresses since no broadcast is set up. 874 */ 875 for (i = 0; i < NUM_PCIE_SERDES; i++) { 876 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 877 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 878 } 879 880 clear_sbus_fast_mode(dd); 881 } 882 883 /* 884 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 885 * 886 * Based on pci_parent_bus_reset() which is not exported by the 887 * kernel core. 888 */ 889 static int trigger_sbr(struct hfi1_devdata *dd) 890 { 891 struct pci_dev *dev = dd->pcidev; 892 struct pci_dev *pdev; 893 894 /* need a parent */ 895 if (!dev->bus->self) { 896 dd_dev_err(dd, "%s: no parent device\n", __func__); 897 return -ENOTTY; 898 } 899 900 /* should not be anyone else on the bus */ 901 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 902 if (pdev != dev) { 903 dd_dev_err(dd, 904 "%s: another device is on the same bus\n", 905 __func__); 906 return -ENOTTY; 907 } 908 909 /* 910 * A secondary bus reset (SBR) issues a hot reset to our device. 911 * The following routine does a 1s wait after the reset is dropped 912 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - 913 * Conventional Reset, paragraph 3, line 35 also says that a 1s 914 * delay after a reset is required. Per spec requirements, 915 * the link is either working or not after that point. 916 */ 917 pci_reset_bridge_secondary_bus(dev->bus->self); 918 919 return 0; 920 } 921 922 /* 923 * Write the given gasket interrupt register. 924 */ 925 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 926 u16 code, u16 data) 927 { 928 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 929 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 930 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 931 } 932 933 /* 934 * Tell the gasket logic how to react to the reset. 935 */ 936 static void arm_gasket_logic(struct hfi1_devdata *dd) 937 { 938 u64 reg; 939 940 reg = (((u64)1 << dd->hfi1_id) << 941 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 942 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 943 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 944 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 945 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 946 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 947 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 948 /* read back to push the write */ 949 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 950 } 951 952 /* 953 * CCE_PCIE_CTRL long name helpers 954 * We redefine these shorter macros to use in the code while leaving 955 * chip_registers.h to be autogenerated from the hardware spec. 956 */ 957 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 958 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 959 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 960 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 961 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 962 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 963 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 964 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 965 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 966 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 967 968 /* 969 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 970 */ 971 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 972 { 973 u64 pcie_ctrl; 974 u64 xmt_margin; 975 u64 xmt_margin_oe; 976 u64 lane_delay; 977 u64 lane_bundle; 978 979 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 980 981 /* 982 * For Discrete, use full-swing. 983 * - PCIe TX defaults to full-swing. 984 * Leave this register as default. 985 * For Integrated, use half-swing 986 * - Copy xmt_margin and xmt_margin_oe 987 * from Gen1/Gen2 to Gen3. 988 */ 989 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 990 /* extract initial fields */ 991 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 992 & MARGIN_GEN1_GEN2_MASK; 993 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 994 & MARGIN_G1_G2_OVERWRITE_MASK; 995 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 996 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 997 & LANE_BUNDLE_MASK; 998 999 /* 1000 * For A0, EFUSE values are not set. Override with the 1001 * correct values. 1002 */ 1003 if (is_ax(dd)) { 1004 /* 1005 * xmt_margin and OverwiteEnabel should be the 1006 * same for Gen1/Gen2 and Gen3 1007 */ 1008 xmt_margin = 0x5; 1009 xmt_margin_oe = 0x1; 1010 lane_delay = 0xF; /* Delay 240ns. */ 1011 lane_bundle = 0x0; /* Set to 1 lane. */ 1012 } 1013 1014 /* overwrite existing values */ 1015 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 1016 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 1017 | (xmt_margin << MARGIN_SHIFT) 1018 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 1019 | (lane_delay << LANE_DELAY_SHIFT) 1020 | (lane_bundle << LANE_BUNDLE_SHIFT); 1021 1022 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 1023 } 1024 1025 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 1026 fname, pcie_ctrl); 1027 } 1028 1029 /* 1030 * Do all the steps needed to transition the PCIe link to Gen3 speed. 1031 */ 1032 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 1033 { 1034 struct pci_dev *parent = dd->pcidev->bus->self; 1035 u64 fw_ctrl; 1036 u64 reg, therm; 1037 u32 reg32, fs, lf; 1038 u32 status, err; 1039 int ret; 1040 int do_retry, retry_count = 0; 1041 int intnum = 0; 1042 uint default_pset; 1043 u16 target_vector, target_speed; 1044 u16 lnkctl2, vendor; 1045 u8 div; 1046 const u8 (*eq)[3]; 1047 const u8 (*ctle_tunings)[4]; 1048 uint static_ctle_mode; 1049 int return_error = 0; 1050 1051 /* PCIe Gen3 is for the ASIC only */ 1052 if (dd->icode != ICODE_RTL_SILICON) 1053 return 0; 1054 1055 if (pcie_target == 1) { /* target Gen1 */ 1056 target_vector = GEN1_SPEED_VECTOR; 1057 target_speed = 2500; 1058 } else if (pcie_target == 2) { /* target Gen2 */ 1059 target_vector = GEN2_SPEED_VECTOR; 1060 target_speed = 5000; 1061 } else if (pcie_target == 3) { /* target Gen3 */ 1062 target_vector = GEN3_SPEED_VECTOR; 1063 target_speed = 8000; 1064 } else { 1065 /* off or invalid target - skip */ 1066 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 1067 return 0; 1068 } 1069 1070 /* if already at target speed, done (unless forced) */ 1071 if (dd->lbus_speed == target_speed) { 1072 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 1073 pcie_target, 1074 pcie_force ? "re-doing anyway" : "skipping"); 1075 if (!pcie_force) 1076 return 0; 1077 } 1078 1079 /* 1080 * The driver cannot do the transition if it has no access to the 1081 * upstream component 1082 */ 1083 if (!parent) { 1084 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 1085 __func__); 1086 return 0; 1087 } 1088 1089 /* 1090 * Do the Gen3 transition. Steps are those of the PCIe Gen3 1091 * recipe. 1092 */ 1093 1094 /* step 1: pcie link working in gen1/gen2 */ 1095 1096 /* step 2: if either side is not capable of Gen3, done */ 1097 if (pcie_target == 3 && !dd->link_gen3_capable) { 1098 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1099 ret = -ENOSYS; 1100 goto done_no_mutex; 1101 } 1102 1103 /* hold the SBus resource across the firmware download and SBR */ 1104 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1105 if (ret) { 1106 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1107 __func__); 1108 return ret; 1109 } 1110 1111 /* make sure thermal polling is not causing interrupts */ 1112 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1113 if (therm) { 1114 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1115 msleep(100); 1116 dd_dev_info(dd, "%s: Disabled therm polling\n", 1117 __func__); 1118 } 1119 1120 retry: 1121 /* the SBus download will reset the spico for thermal */ 1122 1123 /* step 3: download SBus Master firmware */ 1124 /* step 4: download PCIe Gen3 SerDes firmware */ 1125 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1126 ret = load_pcie_firmware(dd); 1127 if (ret) { 1128 /* do not proceed if the firmware cannot be downloaded */ 1129 return_error = 1; 1130 goto done; 1131 } 1132 1133 /* step 5: set up device parameter settings */ 1134 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1135 1136 /* 1137 * PcieCfgSpcie1 - Link Control 3 1138 * Leave at reset value. No need to set PerfEq - link equalization 1139 * will be performed automatically after the SBR when the target 1140 * speed is 8GT/s. 1141 */ 1142 1143 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1144 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1145 1146 /* step 5a: Set Synopsys Port Logic registers */ 1147 1148 /* 1149 * PcieCfgRegPl2 - Port Force Link 1150 * 1151 * Set the low power field to 0x10 to avoid unnecessary power 1152 * management messages. All other fields are zero. 1153 */ 1154 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1155 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1156 1157 /* 1158 * PcieCfgRegPl100 - Gen3 Control 1159 * 1160 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1161 * turn on PcieCfgRegPl100.EqEieosCnt 1162 * Everything else zero. 1163 */ 1164 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1165 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1166 1167 /* 1168 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1169 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1170 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1171 * PcieCfgRegPl105 - Gen3 EQ Status 1172 * 1173 * Give initial EQ settings. 1174 */ 1175 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1176 /* 1000mV, FS=24, LF = 8 */ 1177 fs = 24; 1178 lf = 8; 1179 div = 3; 1180 eq = discrete_preliminary_eq; 1181 default_pset = DEFAULT_DISCRETE_PSET; 1182 ctle_tunings = discrete_ctle_tunings; 1183 /* bit 0 - discrete on/off */ 1184 static_ctle_mode = pcie_ctle & 0x1; 1185 } else { 1186 /* 400mV, FS=29, LF = 9 */ 1187 fs = 29; 1188 lf = 9; 1189 div = 1; 1190 eq = integrated_preliminary_eq; 1191 default_pset = DEFAULT_MCP_PSET; 1192 ctle_tunings = integrated_ctle_tunings; 1193 /* bit 1 - integrated on/off */ 1194 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1195 } 1196 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1197 (fs << 1198 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1199 (lf << 1200 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1201 ret = load_eq_table(dd, eq, fs, div); 1202 if (ret) 1203 goto done; 1204 1205 /* 1206 * PcieCfgRegPl106 - Gen3 EQ Control 1207 * 1208 * Set Gen3EqPsetReqVec, leave other fields 0. 1209 */ 1210 if (pcie_pset == UNSET_PSET) 1211 pcie_pset = default_pset; 1212 if (pcie_pset > 10) { /* valid range is 0-10, inclusive */ 1213 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1214 __func__, pcie_pset, default_pset); 1215 pcie_pset = default_pset; 1216 } 1217 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset); 1218 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1219 ((1 << pcie_pset) << 1220 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1221 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1222 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1223 1224 /* 1225 * step 5b: Do post firmware download steps via SBus 1226 */ 1227 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1228 pcie_post_steps(dd); 1229 1230 /* 1231 * step 5c: Program gasket interrupts 1232 */ 1233 /* set the Rx Bit Rate to REFCLK ratio */ 1234 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1235 /* disable pCal for PCIe Gen3 RX equalization */ 1236 /* select adaptive or static CTLE */ 1237 write_gasket_interrupt(dd, intnum++, 0x0026, 1238 0x5b01 | (static_ctle_mode << 3)); 1239 /* 1240 * Enable iCal for PCIe Gen3 RX equalization, and set which 1241 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1242 */ 1243 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1244 1245 if (static_ctle_mode) { 1246 /* apply static CTLE tunings */ 1247 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1248 1249 pcie_dc = ctle_tunings[pcie_pset][0]; 1250 pcie_lf = ctle_tunings[pcie_pset][1]; 1251 pcie_hf = ctle_tunings[pcie_pset][2]; 1252 pcie_bw = ctle_tunings[pcie_pset][3]; 1253 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1254 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1255 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1256 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1257 } 1258 1259 /* terminate list */ 1260 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1261 1262 /* 1263 * step 5d: program XMT margin 1264 */ 1265 write_xmt_margin(dd, __func__); 1266 1267 /* 1268 * step 5e: disable active state power management (ASPM). It 1269 * will be enabled if required later 1270 */ 1271 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1272 aspm_hw_disable_l1(dd); 1273 1274 /* 1275 * step 5f: clear DirectSpeedChange 1276 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1277 * change in the speed target from starting before we are ready. 1278 * This field defaults to 0 and we are not changing it, so nothing 1279 * needs to be done. 1280 */ 1281 1282 /* step 5g: Set target link speed */ 1283 /* 1284 * Set target link speed to be target on both device and parent. 1285 * On setting the parent: Some system BIOSs "helpfully" set the 1286 * parent target speed to Gen2 to match the ASIC's initial speed. 1287 * We can set the target Gen3 because we have already checked 1288 * that it is Gen3 capable earlier. 1289 */ 1290 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1291 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1292 if (ret) { 1293 dd_dev_err(dd, "Unable to read from PCI config\n"); 1294 return_error = 1; 1295 goto done; 1296 } 1297 1298 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1299 (u32)lnkctl2); 1300 /* only write to parent if target is not as high as ours */ 1301 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) { 1302 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1303 lnkctl2 |= target_vector; 1304 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1305 (u32)lnkctl2); 1306 ret = pcie_capability_write_word(parent, 1307 PCI_EXP_LNKCTL2, lnkctl2); 1308 if (ret) { 1309 dd_dev_err(dd, "Unable to write to PCI config\n"); 1310 return_error = 1; 1311 goto done; 1312 } 1313 } else { 1314 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1315 } 1316 1317 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1318 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1319 if (ret) { 1320 dd_dev_err(dd, "Unable to read from PCI config\n"); 1321 return_error = 1; 1322 goto done; 1323 } 1324 1325 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1326 (u32)lnkctl2); 1327 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; 1328 lnkctl2 |= target_vector; 1329 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1330 (u32)lnkctl2); 1331 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1332 if (ret) { 1333 dd_dev_err(dd, "Unable to write to PCI config\n"); 1334 return_error = 1; 1335 goto done; 1336 } 1337 1338 /* step 5h: arm gasket logic */ 1339 /* hold DC in reset across the SBR */ 1340 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1341 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1342 /* save firmware control across the SBR */ 1343 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1344 1345 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1346 arm_gasket_logic(dd); 1347 1348 /* 1349 * step 6: quiesce PCIe link 1350 * The chip has already been reset, so there will be no traffic 1351 * from the chip. Linux has no easy way to enforce that it will 1352 * not try to access the device, so we just need to hope it doesn't 1353 * do it while we are doing the reset. 1354 */ 1355 1356 /* 1357 * step 7: initiate the secondary bus reset (SBR) 1358 * step 8: hardware brings the links back up 1359 * step 9: wait for link speed transition to be complete 1360 */ 1361 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1362 ret = trigger_sbr(dd); 1363 if (ret) 1364 goto done; 1365 1366 /* step 10: decide what to do next */ 1367 1368 /* check if we can read PCI space */ 1369 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1370 if (ret) { 1371 dd_dev_info(dd, 1372 "%s: read of VendorID failed after SBR, err %d\n", 1373 __func__, ret); 1374 return_error = 1; 1375 goto done; 1376 } 1377 if (vendor == 0xffff) { 1378 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1379 return_error = 1; 1380 ret = -EIO; 1381 goto done; 1382 } 1383 1384 /* restore PCI space registers we know were reset */ 1385 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1386 ret = restore_pci_variables(dd); 1387 if (ret) { 1388 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 1389 __func__); 1390 return_error = 1; 1391 goto done; 1392 } 1393 1394 /* restore firmware control */ 1395 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1396 1397 /* 1398 * Check the gasket block status. 1399 * 1400 * This is the first CSR read after the SBR. If the read returns 1401 * all 1s (fails), the link did not make it back. 1402 * 1403 * Once we're sure we can read and write, clear the DC reset after 1404 * the SBR. Then check for any per-lane errors. Then look over 1405 * the status. 1406 */ 1407 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1408 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1409 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1410 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1411 return_error = 1; 1412 ret = -ENOSYS; 1413 goto done; 1414 } 1415 1416 /* clear the DC reset */ 1417 write_csr(dd, CCE_DC_CTRL, 0); 1418 1419 /* Set the LED off */ 1420 setextled(dd, 0); 1421 1422 /* check for any per-lane errors */ 1423 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1424 if (ret) { 1425 dd_dev_err(dd, "Unable to read from PCI config\n"); 1426 return_error = 1; 1427 goto done; 1428 } 1429 1430 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1431 1432 /* extract status, look for our HFI */ 1433 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1434 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1435 if ((status & (1 << dd->hfi1_id)) == 0) { 1436 dd_dev_err(dd, 1437 "%s: gasket status 0x%x, expecting 0x%x\n", 1438 __func__, status, 1 << dd->hfi1_id); 1439 ret = -EIO; 1440 goto done; 1441 } 1442 1443 /* extract error */ 1444 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1445 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1446 if (err) { 1447 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1448 ret = -EIO; 1449 goto done; 1450 } 1451 1452 /* update our link information cache */ 1453 update_lbus_info(dd); 1454 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1455 dd->lbus_info); 1456 1457 if (dd->lbus_speed != target_speed) { /* not target */ 1458 /* maybe retry */ 1459 do_retry = retry_count < pcie_retry; 1460 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", 1461 pcie_target, do_retry ? ", retrying" : ""); 1462 retry_count++; 1463 if (do_retry) { 1464 msleep(100); /* allow time to settle */ 1465 goto retry; 1466 } 1467 ret = -EIO; 1468 } 1469 1470 done: 1471 if (therm) { 1472 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1473 msleep(100); 1474 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1475 __func__); 1476 } 1477 release_chip_resource(dd, CR_SBUS); 1478 done_no_mutex: 1479 /* return no error if it is OK to be at current speed */ 1480 if (ret && !return_error) { 1481 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1482 ret = 0; 1483 } 1484 1485 dd_dev_info(dd, "%s: done\n", __func__); 1486 return ret; 1487 } 1488