1 /* 2 * Copyright(c) 2015 - 2017 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* 60 * This file contains PCIe utility routines. 61 */ 62 63 /* 64 * Code to adjust PCIe capabilities. 65 */ 66 static void tune_pcie_caps(struct hfi1_devdata *); 67 68 /* 69 * Do all the common PCIe setup and initialization. 70 * devdata is not yet allocated, and is not allocated until after this 71 * routine returns success. Therefore dd_dev_err() can't be used for error 72 * printing. 73 */ 74 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 75 { 76 int ret; 77 78 ret = pci_enable_device(pdev); 79 if (ret) { 80 /* 81 * This can happen (in theory) iff: 82 * We did a chip reset, and then failed to reprogram the 83 * BAR, or the chip reset due to an internal error. We then 84 * unloaded the driver and reloaded it. 85 * 86 * Both reset cases set the BAR back to initial state. For 87 * the latter case, the AER sticky error bit at offset 0x718 88 * should be set, but the Linux kernel doesn't yet know 89 * about that, it appears. If the original BAR was retained 90 * in the kernel data structures, this may be OK. 91 */ 92 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", 93 -ret); 94 goto done; 95 } 96 97 ret = pci_request_regions(pdev, DRIVER_NAME); 98 if (ret) { 99 hfi1_early_err(&pdev->dev, 100 "pci_request_regions fails: err %d\n", -ret); 101 goto bail; 102 } 103 104 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 105 if (ret) { 106 /* 107 * If the 64 bit setup fails, try 32 bit. Some systems 108 * do not setup 64 bit maps on systems with 2GB or less 109 * memory installed. 110 */ 111 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 112 if (ret) { 113 hfi1_early_err(&pdev->dev, 114 "Unable to set DMA mask: %d\n", ret); 115 goto bail; 116 } 117 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 118 } else { 119 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 120 } 121 if (ret) { 122 hfi1_early_err(&pdev->dev, 123 "Unable to set DMA consistent mask: %d\n", ret); 124 goto bail; 125 } 126 127 pci_set_master(pdev); 128 (void)pci_enable_pcie_error_reporting(pdev); 129 goto done; 130 131 bail: 132 hfi1_pcie_cleanup(pdev); 133 done: 134 return ret; 135 } 136 137 /* 138 * Clean what was done in hfi1_pcie_init() 139 */ 140 void hfi1_pcie_cleanup(struct pci_dev *pdev) 141 { 142 pci_disable_device(pdev); 143 /* 144 * Release regions should be called after the disable. OK to 145 * call if request regions has not been called or failed. 146 */ 147 pci_release_regions(pdev); 148 } 149 150 /* 151 * Do remaining PCIe setup, once dd is allocated, and save away 152 * fields required to re-initialize after a chip reset, or for 153 * various other purposes 154 */ 155 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 156 { 157 unsigned long len; 158 resource_size_t addr; 159 int ret = 0; 160 161 addr = pci_resource_start(pdev, 0); 162 len = pci_resource_len(pdev, 0); 163 164 /* 165 * The TXE PIO buffers are at the tail end of the chip space. 166 * Cut them off and map them separately. 167 */ 168 169 /* sanity check vs expectations */ 170 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 171 dd_dev_err(dd, "chip PIO range does not match\n"); 172 return -EINVAL; 173 } 174 175 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY); 176 if (!dd->kregbase1) { 177 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); 178 return -ENOMEM; 179 } 180 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); 181 182 /* verify that reads actually work, save revision for reset check */ 183 dd->revision = readq(dd->kregbase1 + CCE_REVISION); 184 if (dd->revision == ~(u64)0) { 185 dd_dev_err(dd, "Cannot read chip CSRs\n"); 186 goto nomem; 187 } 188 189 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); 190 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count); 191 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8; 192 193 dd->kregbase2 = ioremap_nocache( 194 addr + dd->base2_start, 195 TXE_PIO_SEND - dd->base2_start); 196 if (!dd->kregbase2) { 197 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); 198 goto nomem; 199 } 200 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, 201 TXE_PIO_SEND - dd->base2_start); 202 203 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 204 if (!dd->piobase) { 205 dd_dev_err(dd, "WC mapping of send buffers failed\n"); 206 goto nomem; 207 } 208 dd_dev_info(dd, "WC piobase: %p\n for %x", dd->piobase, TXE_PIO_SIZE); 209 210 dd->physaddr = addr; /* used for io_remap, etc. */ 211 212 /* 213 * Map the chip's RcvArray as write-combining to allow us 214 * to write an entire cacheline worth of entries in one shot. 215 */ 216 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 217 dd->chip_rcv_array_count * 8); 218 if (!dd->rcvarray_wc) { 219 dd_dev_err(dd, "WC mapping of receive array failed\n"); 220 goto nomem; 221 } 222 dd_dev_info(dd, "WC RcvArray: %p for %x\n", 223 dd->rcvarray_wc, dd->chip_rcv_array_count * 8); 224 225 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ 226 return 0; 227 nomem: 228 ret = -ENOMEM; 229 hfi1_pcie_ddcleanup(dd); 230 return ret; 231 } 232 233 /* 234 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 235 * to releasing the dd memory. 236 * Void because all of the core pcie cleanup functions are void. 237 */ 238 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 239 { 240 dd->flags &= ~HFI1_PRESENT; 241 if (dd->kregbase1) 242 iounmap(dd->kregbase1); 243 dd->kregbase1 = NULL; 244 if (dd->kregbase2) 245 iounmap(dd->kregbase2); 246 dd->kregbase2 = NULL; 247 if (dd->rcvarray_wc) 248 iounmap(dd->rcvarray_wc); 249 dd->rcvarray_wc = NULL; 250 if (dd->piobase) 251 iounmap(dd->piobase); 252 dd->piobase = NULL; 253 } 254 255 /* return the PCIe link speed from the given link status */ 256 static u32 extract_speed(u16 linkstat) 257 { 258 u32 speed; 259 260 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 261 default: /* not defined, assume Gen1 */ 262 case PCI_EXP_LNKSTA_CLS_2_5GB: 263 speed = 2500; /* Gen 1, 2.5GHz */ 264 break; 265 case PCI_EXP_LNKSTA_CLS_5_0GB: 266 speed = 5000; /* Gen 2, 5GHz */ 267 break; 268 case PCI_EXP_LNKSTA_CLS_8_0GB: 269 speed = 8000; /* Gen 3, 8GHz */ 270 break; 271 } 272 return speed; 273 } 274 275 /* return the PCIe link speed from the given link status */ 276 static u32 extract_width(u16 linkstat) 277 { 278 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 279 } 280 281 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 282 static void update_lbus_info(struct hfi1_devdata *dd) 283 { 284 u16 linkstat; 285 int ret; 286 287 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 288 if (ret) { 289 dd_dev_err(dd, "Unable to read from PCI config\n"); 290 return; 291 } 292 293 dd->lbus_width = extract_width(linkstat); 294 dd->lbus_speed = extract_speed(linkstat); 295 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 296 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 297 } 298 299 /* 300 * Read in the current PCIe link width and speed. Find if the link is 301 * Gen3 capable. 302 */ 303 int pcie_speeds(struct hfi1_devdata *dd) 304 { 305 u32 linkcap; 306 struct pci_dev *parent = dd->pcidev->bus->self; 307 int ret; 308 309 if (!pci_is_pcie(dd->pcidev)) { 310 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 311 return -EINVAL; 312 } 313 314 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 315 dd->link_gen3_capable = 1; 316 317 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 318 if (ret) { 319 dd_dev_err(dd, "Unable to read from PCI config\n"); 320 return ret; 321 } 322 323 if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GB) { 324 dd_dev_info(dd, 325 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 326 linkcap & PCI_EXP_LNKCAP_SLS); 327 dd->link_gen3_capable = 0; 328 } 329 330 /* 331 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 332 */ 333 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 334 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 335 dd->link_gen3_capable = 0; 336 } 337 338 /* obtain the link width and current speed */ 339 update_lbus_info(dd); 340 341 dd_dev_info(dd, "%s\n", dd->lbus_info); 342 343 return 0; 344 } 345 346 /* 347 * Returns: 348 * - actual number of interrupts allocated or 349 * - 0 if fell back to INTx. 350 * - error 351 */ 352 int request_msix(struct hfi1_devdata *dd, u32 msireq) 353 { 354 int nvec; 355 356 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq, 357 PCI_IRQ_MSIX | PCI_IRQ_LEGACY); 358 if (nvec < 0) { 359 dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", nvec); 360 return nvec; 361 } 362 363 tune_pcie_caps(dd); 364 365 /* check for legacy IRQ */ 366 if (nvec == 1 && !dd->pcidev->msix_enabled) 367 return 0; 368 369 return nvec; 370 } 371 372 /* restore command and BARs after a reset has wiped them out */ 373 int restore_pci_variables(struct hfi1_devdata *dd) 374 { 375 int ret = 0; 376 377 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 378 if (ret) 379 goto error; 380 381 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 382 dd->pcibar0); 383 if (ret) 384 goto error; 385 386 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 387 dd->pcibar1); 388 if (ret) 389 goto error; 390 391 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 392 if (ret) 393 goto error; 394 395 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, 396 dd->pcie_devctl); 397 if (ret) 398 goto error; 399 400 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, 401 dd->pcie_lnkctl); 402 if (ret) 403 goto error; 404 405 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 406 dd->pcie_devctl2); 407 if (ret) 408 goto error; 409 410 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 411 if (ret) 412 goto error; 413 414 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { 415 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, 416 dd->pci_tph2); 417 if (ret) 418 goto error; 419 } 420 return 0; 421 422 error: 423 dd_dev_err(dd, "Unable to write to PCI config\n"); 424 return ret; 425 } 426 427 /* Save BARs and command to rewrite after device reset */ 428 int save_pci_variables(struct hfi1_devdata *dd) 429 { 430 int ret = 0; 431 432 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 433 &dd->pcibar0); 434 if (ret) 435 goto error; 436 437 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 438 &dd->pcibar1); 439 if (ret) 440 goto error; 441 442 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 443 if (ret) 444 goto error; 445 446 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 447 if (ret) 448 goto error; 449 450 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, 451 &dd->pcie_devctl); 452 if (ret) 453 goto error; 454 455 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, 456 &dd->pcie_lnkctl); 457 if (ret) 458 goto error; 459 460 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 461 &dd->pcie_devctl2); 462 if (ret) 463 goto error; 464 465 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 466 if (ret) 467 goto error; 468 469 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { 470 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, 471 &dd->pci_tph2); 472 if (ret) 473 goto error; 474 } 475 return 0; 476 477 error: 478 dd_dev_err(dd, "Unable to read from PCI config\n"); 479 return ret; 480 } 481 482 /* 483 * BIOS may not set PCIe bus-utilization parameters for best performance. 484 * Check and optionally adjust them to maximize our throughput. 485 */ 486 static int hfi1_pcie_caps; 487 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); 488 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 489 490 uint aspm_mode = ASPM_MODE_DISABLED; 491 module_param_named(aspm, aspm_mode, uint, S_IRUGO); 492 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); 493 494 static void tune_pcie_caps(struct hfi1_devdata *dd) 495 { 496 struct pci_dev *parent; 497 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 498 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 499 int ret; 500 501 /* 502 * Turn on extended tags in DevCtl in case the BIOS has turned it off 503 * to improve WFR SDMA bandwidth 504 */ 505 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); 506 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 507 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 508 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 509 ret = pcie_capability_write_word(dd->pcidev, 510 PCI_EXP_DEVCTL, ectl); 511 if (ret) 512 dd_dev_info(dd, "Unable to write to PCI config\n"); 513 } 514 /* Find out supported and configured values for parent (root) */ 515 parent = dd->pcidev->bus->self; 516 /* 517 * The driver cannot perform the tuning if it does not have 518 * access to the upstream component. 519 */ 520 if (!parent) { 521 dd_dev_info(dd, "Parent not found\n"); 522 return; 523 } 524 if (!pci_is_root_bus(parent->bus)) { 525 dd_dev_info(dd, "Parent not root\n"); 526 return; 527 } 528 if (!pci_is_pcie(parent)) { 529 dd_dev_info(dd, "Parent is not PCI Express capable\n"); 530 return; 531 } 532 if (!pci_is_pcie(dd->pcidev)) { 533 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); 534 return; 535 } 536 rc_mpss = parent->pcie_mpss; 537 rc_mps = ffs(pcie_get_mps(parent)) - 8; 538 /* Find out supported and configured values for endpoint (us) */ 539 ep_mpss = dd->pcidev->pcie_mpss; 540 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 541 542 /* Find max payload supported by root, endpoint */ 543 if (rc_mpss > ep_mpss) 544 rc_mpss = ep_mpss; 545 546 /* If Supported greater than limit in module param, limit it */ 547 if (rc_mpss > (hfi1_pcie_caps & 7)) 548 rc_mpss = hfi1_pcie_caps & 7; 549 /* If less than (allowed, supported), bump root payload */ 550 if (rc_mpss > rc_mps) { 551 rc_mps = rc_mpss; 552 pcie_set_mps(parent, 128 << rc_mps); 553 } 554 /* If less than (allowed, supported), bump endpoint payload */ 555 if (rc_mpss > ep_mps) { 556 ep_mps = rc_mpss; 557 pcie_set_mps(dd->pcidev, 128 << ep_mps); 558 } 559 560 /* 561 * Now the Read Request size. 562 * No field for max supported, but PCIe spec limits it to 4096, 563 * which is code '5' (log2(4096) - 7) 564 */ 565 max_mrrs = 5; 566 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 567 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 568 569 max_mrrs = 128 << max_mrrs; 570 rc_mrrs = pcie_get_readrq(parent); 571 ep_mrrs = pcie_get_readrq(dd->pcidev); 572 573 if (max_mrrs > rc_mrrs) { 574 rc_mrrs = max_mrrs; 575 pcie_set_readrq(parent, rc_mrrs); 576 } 577 if (max_mrrs > ep_mrrs) { 578 ep_mrrs = max_mrrs; 579 pcie_set_readrq(dd->pcidev, ep_mrrs); 580 } 581 } 582 583 /* End of PCIe capability tuning */ 584 585 /* 586 * From here through hfi1_pci_err_handler definition is invoked via 587 * PCI error infrastructure, registered via pci 588 */ 589 static pci_ers_result_t 590 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 591 { 592 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 593 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 594 595 switch (state) { 596 case pci_channel_io_normal: 597 dd_dev_info(dd, "State Normal, ignoring\n"); 598 break; 599 600 case pci_channel_io_frozen: 601 dd_dev_info(dd, "State Frozen, requesting reset\n"); 602 pci_disable_device(pdev); 603 ret = PCI_ERS_RESULT_NEED_RESET; 604 break; 605 606 case pci_channel_io_perm_failure: 607 if (dd) { 608 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 609 /* no more register accesses! */ 610 dd->flags &= ~HFI1_PRESENT; 611 hfi1_disable_after_error(dd); 612 } 613 /* else early, or other problem */ 614 ret = PCI_ERS_RESULT_DISCONNECT; 615 break; 616 617 default: /* shouldn't happen */ 618 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 619 state); 620 break; 621 } 622 return ret; 623 } 624 625 static pci_ers_result_t 626 pci_mmio_enabled(struct pci_dev *pdev) 627 { 628 u64 words = 0U; 629 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 630 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 631 632 if (dd && dd->pport) { 633 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 634 if (words == ~0ULL) 635 ret = PCI_ERS_RESULT_NEED_RESET; 636 dd_dev_info(dd, 637 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", 638 words, ret); 639 } 640 return ret; 641 } 642 643 static pci_ers_result_t 644 pci_slot_reset(struct pci_dev *pdev) 645 { 646 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 647 648 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 649 return PCI_ERS_RESULT_CAN_RECOVER; 650 } 651 652 static void 653 pci_resume(struct pci_dev *pdev) 654 { 655 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 656 657 dd_dev_info(dd, "HFI1 resume function called\n"); 658 pci_cleanup_aer_uncorrect_error_status(pdev); 659 /* 660 * Running jobs will fail, since it's asynchronous 661 * unlike sysfs-requested reset. Better than 662 * doing nothing. 663 */ 664 hfi1_init(dd, 1); /* same as re-init after reset */ 665 } 666 667 const struct pci_error_handlers hfi1_pci_err_handler = { 668 .error_detected = pci_error_detected, 669 .mmio_enabled = pci_mmio_enabled, 670 .slot_reset = pci_slot_reset, 671 .resume = pci_resume, 672 }; 673 674 /*============================================================================*/ 675 /* PCIe Gen3 support */ 676 677 /* 678 * This code is separated out because it is expected to be removed in the 679 * final shipping product. If not, then it will be revisited and items 680 * will be moved to more standard locations. 681 */ 682 683 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 684 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 685 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 686 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 687 688 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 689 #define DL_ERR_NONE 0x0 /* no error */ 690 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 691 /* or response data */ 692 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 693 #define DL_ERR_SECURITY 0x3 /* security check failed */ 694 #define DL_ERR_SBUS 0x4 /* SBus status error */ 695 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 696 697 /* gasket block secondary bus reset delay */ 698 #define SBR_DELAY_US 200000 /* 200ms */ 699 700 static uint pcie_target = 3; 701 module_param(pcie_target, uint, S_IRUGO); 702 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 703 704 static uint pcie_force; 705 module_param(pcie_force, uint, S_IRUGO); 706 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 707 708 static uint pcie_retry = 5; 709 module_param(pcie_retry, uint, S_IRUGO); 710 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 711 712 #define UNSET_PSET 255 713 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 714 #define DEFAULT_MCP_PSET 6 /* MCP HFI */ 715 static uint pcie_pset = UNSET_PSET; 716 module_param(pcie_pset, uint, S_IRUGO); 717 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 718 719 static uint pcie_ctle = 3; /* discrete on, integrated on */ 720 module_param(pcie_ctle, uint, S_IRUGO); 721 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 722 723 /* equalization columns */ 724 #define PREC 0 725 #define ATTN 1 726 #define POST 2 727 728 /* discrete silicon preliminary equalization values */ 729 static const u8 discrete_preliminary_eq[11][3] = { 730 /* prec attn post */ 731 { 0x00, 0x00, 0x12 }, /* p0 */ 732 { 0x00, 0x00, 0x0c }, /* p1 */ 733 { 0x00, 0x00, 0x0f }, /* p2 */ 734 { 0x00, 0x00, 0x09 }, /* p3 */ 735 { 0x00, 0x00, 0x00 }, /* p4 */ 736 { 0x06, 0x00, 0x00 }, /* p5 */ 737 { 0x09, 0x00, 0x00 }, /* p6 */ 738 { 0x06, 0x00, 0x0f }, /* p7 */ 739 { 0x09, 0x00, 0x09 }, /* p8 */ 740 { 0x0c, 0x00, 0x00 }, /* p9 */ 741 { 0x00, 0x00, 0x18 }, /* p10 */ 742 }; 743 744 /* integrated silicon preliminary equalization values */ 745 static const u8 integrated_preliminary_eq[11][3] = { 746 /* prec attn post */ 747 { 0x00, 0x1e, 0x07 }, /* p0 */ 748 { 0x00, 0x1e, 0x05 }, /* p1 */ 749 { 0x00, 0x1e, 0x06 }, /* p2 */ 750 { 0x00, 0x1e, 0x04 }, /* p3 */ 751 { 0x00, 0x1e, 0x00 }, /* p4 */ 752 { 0x03, 0x1e, 0x00 }, /* p5 */ 753 { 0x04, 0x1e, 0x00 }, /* p6 */ 754 { 0x03, 0x1e, 0x06 }, /* p7 */ 755 { 0x03, 0x1e, 0x04 }, /* p8 */ 756 { 0x05, 0x1e, 0x00 }, /* p9 */ 757 { 0x00, 0x1e, 0x0a }, /* p10 */ 758 }; 759 760 static const u8 discrete_ctle_tunings[11][4] = { 761 /* DC LF HF BW */ 762 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 763 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 764 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 765 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 766 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 767 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 768 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 769 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 770 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 771 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 772 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 773 }; 774 775 static const u8 integrated_ctle_tunings[11][4] = { 776 /* DC LF HF BW */ 777 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 778 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 779 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 780 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 781 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 782 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 783 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 784 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 785 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 786 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 787 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 788 }; 789 790 /* helper to format the value to write to hardware */ 791 #define eq_value(pre, curr, post) \ 792 ((((u32)(pre)) << \ 793 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 794 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 795 | (((u32)(post)) << \ 796 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 797 798 /* 799 * Load the given EQ preset table into the PCIe hardware. 800 */ 801 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 802 u8 div) 803 { 804 struct pci_dev *pdev = dd->pcidev; 805 u32 hit_error = 0; 806 u32 violation; 807 u32 i; 808 u8 c_minus1, c0, c_plus1; 809 int ret; 810 811 for (i = 0; i < 11; i++) { 812 /* set index */ 813 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 814 /* write the value */ 815 c_minus1 = eq[i][PREC] / div; 816 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 817 c_plus1 = eq[i][POST] / div; 818 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 819 eq_value(c_minus1, c0, c_plus1)); 820 /* check if these coefficients violate EQ rules */ 821 ret = pci_read_config_dword(dd->pcidev, 822 PCIE_CFG_REG_PL105, &violation); 823 if (ret) { 824 dd_dev_err(dd, "Unable to read from PCI config\n"); 825 hit_error = 1; 826 break; 827 } 828 829 if (violation 830 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 831 if (hit_error == 0) { 832 dd_dev_err(dd, 833 "Gen3 EQ Table Coefficient rule violations\n"); 834 dd_dev_err(dd, " prec attn post\n"); 835 } 836 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 837 i, (u32)eq[i][0], (u32)eq[i][1], 838 (u32)eq[i][2]); 839 dd_dev_err(dd, " %02x %02x %02x\n", 840 (u32)c_minus1, (u32)c0, (u32)c_plus1); 841 hit_error = 1; 842 } 843 } 844 if (hit_error) 845 return -EINVAL; 846 return 0; 847 } 848 849 /* 850 * Steps to be done after the PCIe firmware is downloaded and 851 * before the SBR for the Pcie Gen3. 852 * The SBus resource is already being held. 853 */ 854 static void pcie_post_steps(struct hfi1_devdata *dd) 855 { 856 int i; 857 858 set_sbus_fast_mode(dd); 859 /* 860 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 861 * This avoids a spurious framing error that can otherwise be 862 * generated by the MAC layer. 863 * 864 * Use individual addresses since no broadcast is set up. 865 */ 866 for (i = 0; i < NUM_PCIE_SERDES; i++) { 867 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 868 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 869 } 870 871 clear_sbus_fast_mode(dd); 872 } 873 874 /* 875 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 876 * 877 * Based on pci_parent_bus_reset() which is not exported by the 878 * kernel core. 879 */ 880 static int trigger_sbr(struct hfi1_devdata *dd) 881 { 882 struct pci_dev *dev = dd->pcidev; 883 struct pci_dev *pdev; 884 885 /* need a parent */ 886 if (!dev->bus->self) { 887 dd_dev_err(dd, "%s: no parent device\n", __func__); 888 return -ENOTTY; 889 } 890 891 /* should not be anyone else on the bus */ 892 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 893 if (pdev != dev) { 894 dd_dev_err(dd, 895 "%s: another device is on the same bus\n", 896 __func__); 897 return -ENOTTY; 898 } 899 900 /* 901 * A secondary bus reset (SBR) issues a hot reset to our device. 902 * The following routine does a 1s wait after the reset is dropped 903 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - 904 * Conventional Reset, paragraph 3, line 35 also says that a 1s 905 * delay after a reset is required. Per spec requirements, 906 * the link is either working or not after that point. 907 */ 908 pci_reset_bridge_secondary_bus(dev->bus->self); 909 910 return 0; 911 } 912 913 /* 914 * Write the given gasket interrupt register. 915 */ 916 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 917 u16 code, u16 data) 918 { 919 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 920 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 921 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 922 } 923 924 /* 925 * Tell the gasket logic how to react to the reset. 926 */ 927 static void arm_gasket_logic(struct hfi1_devdata *dd) 928 { 929 u64 reg; 930 931 reg = (((u64)1 << dd->hfi1_id) << 932 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 933 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 934 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 935 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 936 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 937 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 938 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 939 /* read back to push the write */ 940 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 941 } 942 943 /* 944 * CCE_PCIE_CTRL long name helpers 945 * We redefine these shorter macros to use in the code while leaving 946 * chip_registers.h to be autogenerated from the hardware spec. 947 */ 948 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 949 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 950 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 951 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 952 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 953 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 954 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 955 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 956 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 957 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 958 959 /* 960 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 961 */ 962 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 963 { 964 u64 pcie_ctrl; 965 u64 xmt_margin; 966 u64 xmt_margin_oe; 967 u64 lane_delay; 968 u64 lane_bundle; 969 970 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 971 972 /* 973 * For Discrete, use full-swing. 974 * - PCIe TX defaults to full-swing. 975 * Leave this register as default. 976 * For Integrated, use half-swing 977 * - Copy xmt_margin and xmt_margin_oe 978 * from Gen1/Gen2 to Gen3. 979 */ 980 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 981 /* extract initial fields */ 982 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 983 & MARGIN_GEN1_GEN2_MASK; 984 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 985 & MARGIN_G1_G2_OVERWRITE_MASK; 986 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 987 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 988 & LANE_BUNDLE_MASK; 989 990 /* 991 * For A0, EFUSE values are not set. Override with the 992 * correct values. 993 */ 994 if (is_ax(dd)) { 995 /* 996 * xmt_margin and OverwiteEnabel should be the 997 * same for Gen1/Gen2 and Gen3 998 */ 999 xmt_margin = 0x5; 1000 xmt_margin_oe = 0x1; 1001 lane_delay = 0xF; /* Delay 240ns. */ 1002 lane_bundle = 0x0; /* Set to 1 lane. */ 1003 } 1004 1005 /* overwrite existing values */ 1006 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 1007 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 1008 | (xmt_margin << MARGIN_SHIFT) 1009 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 1010 | (lane_delay << LANE_DELAY_SHIFT) 1011 | (lane_bundle << LANE_BUNDLE_SHIFT); 1012 1013 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 1014 } 1015 1016 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 1017 fname, pcie_ctrl); 1018 } 1019 1020 /* 1021 * Do all the steps needed to transition the PCIe link to Gen3 speed. 1022 */ 1023 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 1024 { 1025 struct pci_dev *parent = dd->pcidev->bus->self; 1026 u64 fw_ctrl; 1027 u64 reg, therm; 1028 u32 reg32, fs, lf; 1029 u32 status, err; 1030 int ret; 1031 int do_retry, retry_count = 0; 1032 int intnum = 0; 1033 uint default_pset; 1034 uint pset = pcie_pset; 1035 u16 target_vector, target_speed; 1036 u16 lnkctl2, vendor; 1037 u8 div; 1038 const u8 (*eq)[3]; 1039 const u8 (*ctle_tunings)[4]; 1040 uint static_ctle_mode; 1041 int return_error = 0; 1042 1043 /* PCIe Gen3 is for the ASIC only */ 1044 if (dd->icode != ICODE_RTL_SILICON) 1045 return 0; 1046 1047 if (pcie_target == 1) { /* target Gen1 */ 1048 target_vector = PCI_EXP_LNKCTL2_TLS_2_5GT; 1049 target_speed = 2500; 1050 } else if (pcie_target == 2) { /* target Gen2 */ 1051 target_vector = PCI_EXP_LNKCTL2_TLS_5_0GT; 1052 target_speed = 5000; 1053 } else if (pcie_target == 3) { /* target Gen3 */ 1054 target_vector = PCI_EXP_LNKCTL2_TLS_8_0GT; 1055 target_speed = 8000; 1056 } else { 1057 /* off or invalid target - skip */ 1058 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 1059 return 0; 1060 } 1061 1062 /* if already at target speed, done (unless forced) */ 1063 if (dd->lbus_speed == target_speed) { 1064 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 1065 pcie_target, 1066 pcie_force ? "re-doing anyway" : "skipping"); 1067 if (!pcie_force) 1068 return 0; 1069 } 1070 1071 /* 1072 * The driver cannot do the transition if it has no access to the 1073 * upstream component 1074 */ 1075 if (!parent) { 1076 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 1077 __func__); 1078 return 0; 1079 } 1080 1081 /* 1082 * Do the Gen3 transition. Steps are those of the PCIe Gen3 1083 * recipe. 1084 */ 1085 1086 /* step 1: pcie link working in gen1/gen2 */ 1087 1088 /* step 2: if either side is not capable of Gen3, done */ 1089 if (pcie_target == 3 && !dd->link_gen3_capable) { 1090 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1091 ret = -ENOSYS; 1092 goto done_no_mutex; 1093 } 1094 1095 /* hold the SBus resource across the firmware download and SBR */ 1096 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1097 if (ret) { 1098 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1099 __func__); 1100 return ret; 1101 } 1102 1103 /* make sure thermal polling is not causing interrupts */ 1104 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1105 if (therm) { 1106 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1107 msleep(100); 1108 dd_dev_info(dd, "%s: Disabled therm polling\n", 1109 __func__); 1110 } 1111 1112 retry: 1113 /* the SBus download will reset the spico for thermal */ 1114 1115 /* step 3: download SBus Master firmware */ 1116 /* step 4: download PCIe Gen3 SerDes firmware */ 1117 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1118 ret = load_pcie_firmware(dd); 1119 if (ret) { 1120 /* do not proceed if the firmware cannot be downloaded */ 1121 return_error = 1; 1122 goto done; 1123 } 1124 1125 /* step 5: set up device parameter settings */ 1126 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1127 1128 /* 1129 * PcieCfgSpcie1 - Link Control 3 1130 * Leave at reset value. No need to set PerfEq - link equalization 1131 * will be performed automatically after the SBR when the target 1132 * speed is 8GT/s. 1133 */ 1134 1135 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1136 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1137 1138 /* step 5a: Set Synopsys Port Logic registers */ 1139 1140 /* 1141 * PcieCfgRegPl2 - Port Force Link 1142 * 1143 * Set the low power field to 0x10 to avoid unnecessary power 1144 * management messages. All other fields are zero. 1145 */ 1146 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1147 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1148 1149 /* 1150 * PcieCfgRegPl100 - Gen3 Control 1151 * 1152 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1153 * turn on PcieCfgRegPl100.EqEieosCnt 1154 * Everything else zero. 1155 */ 1156 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1157 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1158 1159 /* 1160 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1161 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1162 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1163 * PcieCfgRegPl105 - Gen3 EQ Status 1164 * 1165 * Give initial EQ settings. 1166 */ 1167 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1168 /* 1000mV, FS=24, LF = 8 */ 1169 fs = 24; 1170 lf = 8; 1171 div = 3; 1172 eq = discrete_preliminary_eq; 1173 default_pset = DEFAULT_DISCRETE_PSET; 1174 ctle_tunings = discrete_ctle_tunings; 1175 /* bit 0 - discrete on/off */ 1176 static_ctle_mode = pcie_ctle & 0x1; 1177 } else { 1178 /* 400mV, FS=29, LF = 9 */ 1179 fs = 29; 1180 lf = 9; 1181 div = 1; 1182 eq = integrated_preliminary_eq; 1183 default_pset = DEFAULT_MCP_PSET; 1184 ctle_tunings = integrated_ctle_tunings; 1185 /* bit 1 - integrated on/off */ 1186 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1187 } 1188 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1189 (fs << 1190 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1191 (lf << 1192 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1193 ret = load_eq_table(dd, eq, fs, div); 1194 if (ret) 1195 goto done; 1196 1197 /* 1198 * PcieCfgRegPl106 - Gen3 EQ Control 1199 * 1200 * Set Gen3EqPsetReqVec, leave other fields 0. 1201 */ 1202 if (pset == UNSET_PSET) 1203 pset = default_pset; 1204 if (pset > 10) { /* valid range is 0-10, inclusive */ 1205 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1206 __func__, pset, default_pset); 1207 pset = default_pset; 1208 } 1209 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); 1210 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1211 ((1 << pset) << 1212 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1213 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1214 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1215 1216 /* 1217 * step 5b: Do post firmware download steps via SBus 1218 */ 1219 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1220 pcie_post_steps(dd); 1221 1222 /* 1223 * step 5c: Program gasket interrupts 1224 */ 1225 /* set the Rx Bit Rate to REFCLK ratio */ 1226 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1227 /* disable pCal for PCIe Gen3 RX equalization */ 1228 /* select adaptive or static CTLE */ 1229 write_gasket_interrupt(dd, intnum++, 0x0026, 1230 0x5b01 | (static_ctle_mode << 3)); 1231 /* 1232 * Enable iCal for PCIe Gen3 RX equalization, and set which 1233 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1234 */ 1235 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1236 1237 if (static_ctle_mode) { 1238 /* apply static CTLE tunings */ 1239 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1240 1241 pcie_dc = ctle_tunings[pset][0]; 1242 pcie_lf = ctle_tunings[pset][1]; 1243 pcie_hf = ctle_tunings[pset][2]; 1244 pcie_bw = ctle_tunings[pset][3]; 1245 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1246 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1247 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1248 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1249 } 1250 1251 /* terminate list */ 1252 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1253 1254 /* 1255 * step 5d: program XMT margin 1256 */ 1257 write_xmt_margin(dd, __func__); 1258 1259 /* 1260 * step 5e: disable active state power management (ASPM). It 1261 * will be enabled if required later 1262 */ 1263 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1264 aspm_hw_disable_l1(dd); 1265 1266 /* 1267 * step 5f: clear DirectSpeedChange 1268 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1269 * change in the speed target from starting before we are ready. 1270 * This field defaults to 0 and we are not changing it, so nothing 1271 * needs to be done. 1272 */ 1273 1274 /* step 5g: Set target link speed */ 1275 /* 1276 * Set target link speed to be target on both device and parent. 1277 * On setting the parent: Some system BIOSs "helpfully" set the 1278 * parent target speed to Gen2 to match the ASIC's initial speed. 1279 * We can set the target Gen3 because we have already checked 1280 * that it is Gen3 capable earlier. 1281 */ 1282 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1283 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1284 if (ret) { 1285 dd_dev_err(dd, "Unable to read from PCI config\n"); 1286 return_error = 1; 1287 goto done; 1288 } 1289 1290 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1291 (u32)lnkctl2); 1292 /* only write to parent if target is not as high as ours */ 1293 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) { 1294 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 1295 lnkctl2 |= target_vector; 1296 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1297 (u32)lnkctl2); 1298 ret = pcie_capability_write_word(parent, 1299 PCI_EXP_LNKCTL2, lnkctl2); 1300 if (ret) { 1301 dd_dev_err(dd, "Unable to write to PCI config\n"); 1302 return_error = 1; 1303 goto done; 1304 } 1305 } else { 1306 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1307 } 1308 1309 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1310 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1311 if (ret) { 1312 dd_dev_err(dd, "Unable to read from PCI config\n"); 1313 return_error = 1; 1314 goto done; 1315 } 1316 1317 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1318 (u32)lnkctl2); 1319 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 1320 lnkctl2 |= target_vector; 1321 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1322 (u32)lnkctl2); 1323 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1324 if (ret) { 1325 dd_dev_err(dd, "Unable to write to PCI config\n"); 1326 return_error = 1; 1327 goto done; 1328 } 1329 1330 /* step 5h: arm gasket logic */ 1331 /* hold DC in reset across the SBR */ 1332 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1333 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1334 /* save firmware control across the SBR */ 1335 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1336 1337 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1338 arm_gasket_logic(dd); 1339 1340 /* 1341 * step 6: quiesce PCIe link 1342 * The chip has already been reset, so there will be no traffic 1343 * from the chip. Linux has no easy way to enforce that it will 1344 * not try to access the device, so we just need to hope it doesn't 1345 * do it while we are doing the reset. 1346 */ 1347 1348 /* 1349 * step 7: initiate the secondary bus reset (SBR) 1350 * step 8: hardware brings the links back up 1351 * step 9: wait for link speed transition to be complete 1352 */ 1353 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1354 ret = trigger_sbr(dd); 1355 if (ret) 1356 goto done; 1357 1358 /* step 10: decide what to do next */ 1359 1360 /* check if we can read PCI space */ 1361 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1362 if (ret) { 1363 dd_dev_info(dd, 1364 "%s: read of VendorID failed after SBR, err %d\n", 1365 __func__, ret); 1366 return_error = 1; 1367 goto done; 1368 } 1369 if (vendor == 0xffff) { 1370 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1371 return_error = 1; 1372 ret = -EIO; 1373 goto done; 1374 } 1375 1376 /* restore PCI space registers we know were reset */ 1377 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1378 ret = restore_pci_variables(dd); 1379 if (ret) { 1380 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 1381 __func__); 1382 return_error = 1; 1383 goto done; 1384 } 1385 1386 /* restore firmware control */ 1387 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1388 1389 /* 1390 * Check the gasket block status. 1391 * 1392 * This is the first CSR read after the SBR. If the read returns 1393 * all 1s (fails), the link did not make it back. 1394 * 1395 * Once we're sure we can read and write, clear the DC reset after 1396 * the SBR. Then check for any per-lane errors. Then look over 1397 * the status. 1398 */ 1399 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1400 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1401 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1402 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1403 return_error = 1; 1404 ret = -ENOSYS; 1405 goto done; 1406 } 1407 1408 /* clear the DC reset */ 1409 write_csr(dd, CCE_DC_CTRL, 0); 1410 1411 /* Set the LED off */ 1412 setextled(dd, 0); 1413 1414 /* check for any per-lane errors */ 1415 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1416 if (ret) { 1417 dd_dev_err(dd, "Unable to read from PCI config\n"); 1418 return_error = 1; 1419 goto done; 1420 } 1421 1422 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1423 1424 /* extract status, look for our HFI */ 1425 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1426 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1427 if ((status & (1 << dd->hfi1_id)) == 0) { 1428 dd_dev_err(dd, 1429 "%s: gasket status 0x%x, expecting 0x%x\n", 1430 __func__, status, 1 << dd->hfi1_id); 1431 ret = -EIO; 1432 goto done; 1433 } 1434 1435 /* extract error */ 1436 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1437 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1438 if (err) { 1439 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1440 ret = -EIO; 1441 goto done; 1442 } 1443 1444 /* update our link information cache */ 1445 update_lbus_info(dd); 1446 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1447 dd->lbus_info); 1448 1449 if (dd->lbus_speed != target_speed) { /* not target */ 1450 /* maybe retry */ 1451 do_retry = retry_count < pcie_retry; 1452 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", 1453 pcie_target, do_retry ? ", retrying" : ""); 1454 retry_count++; 1455 if (do_retry) { 1456 msleep(100); /* allow time to settle */ 1457 goto retry; 1458 } 1459 ret = -EIO; 1460 } 1461 1462 done: 1463 if (therm) { 1464 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1465 msleep(100); 1466 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1467 __func__); 1468 } 1469 release_chip_resource(dd, CR_SBUS); 1470 done_no_mutex: 1471 /* return no error if it is OK to be at current speed */ 1472 if (ret && !return_error) { 1473 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1474 ret = 0; 1475 } 1476 1477 dd_dev_info(dd, "%s: done\n", __func__); 1478 return ret; 1479 } 1480