1f48ad614SDennis Dalessandro /* 2d4829ea6SVishwanathapura, Niranjana * Copyright(c) 2015-2017 Intel Corporation. 3f48ad614SDennis Dalessandro * 4f48ad614SDennis Dalessandro * This file is provided under a dual BSD/GPLv2 license. When using or 5f48ad614SDennis Dalessandro * redistributing this file, you may do so under either license. 6f48ad614SDennis Dalessandro * 7f48ad614SDennis Dalessandro * GPL LICENSE SUMMARY 8f48ad614SDennis Dalessandro * 9f48ad614SDennis Dalessandro * This program is free software; you can redistribute it and/or modify 10f48ad614SDennis Dalessandro * it under the terms of version 2 of the GNU General Public License as 11f48ad614SDennis Dalessandro * published by the Free Software Foundation. 12f48ad614SDennis Dalessandro * 13f48ad614SDennis Dalessandro * This program is distributed in the hope that it will be useful, but 14f48ad614SDennis Dalessandro * WITHOUT ANY WARRANTY; without even the implied warranty of 15f48ad614SDennis Dalessandro * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16f48ad614SDennis Dalessandro * General Public License for more details. 17f48ad614SDennis Dalessandro * 18f48ad614SDennis Dalessandro * BSD LICENSE 19f48ad614SDennis Dalessandro * 20f48ad614SDennis Dalessandro * Redistribution and use in source and binary forms, with or without 21f48ad614SDennis Dalessandro * modification, are permitted provided that the following conditions 22f48ad614SDennis Dalessandro * are met: 23f48ad614SDennis Dalessandro * 24f48ad614SDennis Dalessandro * - Redistributions of source code must retain the above copyright 25f48ad614SDennis Dalessandro * notice, this list of conditions and the following disclaimer. 26f48ad614SDennis Dalessandro * - Redistributions in binary form must reproduce the above copyright 27f48ad614SDennis Dalessandro * notice, this list of conditions and the following disclaimer in 28f48ad614SDennis Dalessandro * the documentation and/or other materials provided with the 29f48ad614SDennis Dalessandro * distribution. 30f48ad614SDennis Dalessandro * - Neither the name of Intel Corporation nor the names of its 31f48ad614SDennis Dalessandro * contributors may be used to endorse or promote products derived 32f48ad614SDennis Dalessandro * from this software without specific prior written permission. 33f48ad614SDennis Dalessandro * 34f48ad614SDennis Dalessandro * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35f48ad614SDennis Dalessandro * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36f48ad614SDennis Dalessandro * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37f48ad614SDennis Dalessandro * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38f48ad614SDennis Dalessandro * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39f48ad614SDennis Dalessandro * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40f48ad614SDennis Dalessandro * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41f48ad614SDennis Dalessandro * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42f48ad614SDennis Dalessandro * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43f48ad614SDennis Dalessandro * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44f48ad614SDennis Dalessandro * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45f48ad614SDennis Dalessandro * 46f48ad614SDennis Dalessandro */ 47f48ad614SDennis Dalessandro 48f48ad614SDennis Dalessandro #include <linux/pci.h> 49f48ad614SDennis Dalessandro #include <linux/netdevice.h> 50f48ad614SDennis Dalessandro #include <linux/vmalloc.h> 51f48ad614SDennis Dalessandro #include <linux/delay.h> 52f48ad614SDennis Dalessandro #include <linux/idr.h> 53f48ad614SDennis Dalessandro #include <linux/module.h> 54f48ad614SDennis Dalessandro #include <linux/printk.h> 55f48ad614SDennis Dalessandro #include <linux/hrtimer.h> 568737ce95SMichael J. Ruhl #include <linux/bitmap.h> 57f48ad614SDennis Dalessandro #include <rdma/rdma_vt.h> 58f48ad614SDennis Dalessandro 59f48ad614SDennis Dalessandro #include "hfi.h" 60f48ad614SDennis Dalessandro #include "device.h" 61f48ad614SDennis Dalessandro #include "common.h" 62f48ad614SDennis Dalessandro #include "trace.h" 63f48ad614SDennis Dalessandro #include "mad.h" 64f48ad614SDennis Dalessandro #include "sdma.h" 65f48ad614SDennis Dalessandro #include "debugfs.h" 66f48ad614SDennis Dalessandro #include "verbs.h" 67f48ad614SDennis Dalessandro #include "aspm.h" 684197344bSDennis Dalessandro #include "affinity.h" 69d4829ea6SVishwanathapura, Niranjana #include "vnic.h" 70fe4e74eeSMichael J. Ruhl #include "exp_rcv.h" 71f48ad614SDennis Dalessandro 72f48ad614SDennis Dalessandro #undef pr_fmt 73f48ad614SDennis Dalessandro #define pr_fmt(fmt) DRIVER_NAME ": " fmt 74f48ad614SDennis Dalessandro 75dd1ed108SMike Marciniszyn #define HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES 5 76f48ad614SDennis Dalessandro /* 77f48ad614SDennis Dalessandro * min buffers we want to have per context, after driver 78f48ad614SDennis Dalessandro */ 79f48ad614SDennis Dalessandro #define HFI1_MIN_USER_CTXT_BUFCNT 7 80f48ad614SDennis Dalessandro 81f48ad614SDennis Dalessandro #define HFI1_MIN_HDRQ_EGRBUF_CNT 2 82f48ad614SDennis Dalessandro #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352 83f48ad614SDennis Dalessandro #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */ 84f48ad614SDennis Dalessandro #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */ 85f48ad614SDennis Dalessandro 86f48ad614SDennis Dalessandro /* 87f48ad614SDennis Dalessandro * Number of user receive contexts we are configured to use (to allow for more 88f48ad614SDennis Dalessandro * pio buffers per ctxt, etc.) Zero means use one user context per CPU. 89f48ad614SDennis Dalessandro */ 90f48ad614SDennis Dalessandro int num_user_contexts = -1; 915da9e742SMichael J. Ruhl module_param_named(num_user_contexts, num_user_contexts, int, 0444); 92f48ad614SDennis Dalessandro MODULE_PARM_DESC( 935da9e742SMichael J. Ruhl num_user_contexts, "Set max number of user contexts to use (default: -1 will use the real (non-HT) CPU count)"); 94f48ad614SDennis Dalessandro 95f48ad614SDennis Dalessandro uint krcvqs[RXE_NUM_DATA_VL]; 96f48ad614SDennis Dalessandro int krcvqsset; 97f48ad614SDennis Dalessandro module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO); 98f48ad614SDennis Dalessandro MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL"); 99f48ad614SDennis Dalessandro 100f48ad614SDennis Dalessandro /* computed based on above array */ 101429b6a72SHarish Chegondi unsigned long n_krcvqs; 102f48ad614SDennis Dalessandro 103f48ad614SDennis Dalessandro static unsigned hfi1_rcvarr_split = 25; 104f48ad614SDennis Dalessandro module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO); 105f48ad614SDennis Dalessandro MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers"); 106f48ad614SDennis Dalessandro 1079746fa43STymoteusz Kielan static uint eager_buffer_size = (8 << 20); /* 8MB */ 108f48ad614SDennis Dalessandro module_param(eager_buffer_size, uint, S_IRUGO); 1099746fa43STymoteusz Kielan MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 8MB"); 110f48ad614SDennis Dalessandro 111f48ad614SDennis Dalessandro static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */ 112f48ad614SDennis Dalessandro module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO); 113f48ad614SDennis Dalessandro MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)"); 114f48ad614SDennis Dalessandro 115f48ad614SDennis Dalessandro static uint hfi1_hdrq_entsize = 32; 116f48ad614SDennis Dalessandro module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO); 117f48ad614SDennis Dalessandro MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B"); 118f48ad614SDennis Dalessandro 119f48ad614SDennis Dalessandro unsigned int user_credit_return_threshold = 33; /* default is 33% */ 120f48ad614SDennis Dalessandro module_param(user_credit_return_threshold, uint, S_IRUGO); 121f48ad614SDennis Dalessandro MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)"); 122f48ad614SDennis Dalessandro 123f4cd8765SMichael J. Ruhl static inline u64 encode_rcv_header_entry_size(u16 size); 124f48ad614SDennis Dalessandro 125f48ad614SDennis Dalessandro static struct idr hfi1_unit_table; 126f48ad614SDennis Dalessandro 127f2a3bc00SMichael J. Ruhl static int hfi1_create_kctxt(struct hfi1_devdata *dd, 128f2a3bc00SMichael J. Ruhl struct hfi1_pportdata *ppd) 129f48ad614SDennis Dalessandro { 130f2a3bc00SMichael J. Ruhl struct hfi1_ctxtdata *rcd; 131f48ad614SDennis Dalessandro int ret; 132f48ad614SDennis Dalessandro 133f48ad614SDennis Dalessandro /* Control context has to be always 0 */ 134f48ad614SDennis Dalessandro BUILD_BUG_ON(HFI1_CTRL_CTXT != 0); 135f48ad614SDennis Dalessandro 136f2a3bc00SMichael J. Ruhl ret = hfi1_create_ctxtdata(ppd, dd->node, &rcd); 137f2a3bc00SMichael J. Ruhl if (ret < 0) { 138f2a3bc00SMichael J. Ruhl dd_dev_err(dd, "Kernel receive context allocation failed\n"); 139f2a3bc00SMichael J. Ruhl return ret; 140f48ad614SDennis Dalessandro } 141f2a3bc00SMichael J. Ruhl 142f48ad614SDennis Dalessandro /* 143f2a3bc00SMichael J. Ruhl * Set up the kernel context flags here and now because they use 144f2a3bc00SMichael J. Ruhl * default values for all receive side memories. User contexts will 145f2a3bc00SMichael J. Ruhl * be handled as they are created. 146f48ad614SDennis Dalessandro */ 147f48ad614SDennis Dalessandro rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) | 148f48ad614SDennis Dalessandro HFI1_CAP_KGET(NODROP_RHQ_FULL) | 149f48ad614SDennis Dalessandro HFI1_CAP_KGET(NODROP_EGR_FULL) | 150f48ad614SDennis Dalessandro HFI1_CAP_KGET(DMA_RTAIL); 151f48ad614SDennis Dalessandro 152f48ad614SDennis Dalessandro /* Control context must use DMA_RTAIL */ 153f48ad614SDennis Dalessandro if (rcd->ctxt == HFI1_CTRL_CTXT) 154f48ad614SDennis Dalessandro rcd->flags |= HFI1_CAP_DMA_RTAIL; 155f48ad614SDennis Dalessandro rcd->seq_cnt = 1; 156f48ad614SDennis Dalessandro 157f48ad614SDennis Dalessandro rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node); 158f48ad614SDennis Dalessandro if (!rcd->sc) { 159f2a3bc00SMichael J. Ruhl dd_dev_err(dd, "Kernel send context allocation failed\n"); 160f2a3bc00SMichael J. Ruhl return -ENOMEM; 161f48ad614SDennis Dalessandro } 1629b60d2cbSMichael J. Ruhl hfi1_init_ctxt(rcd->sc); 163f2a3bc00SMichael J. Ruhl 164f2a3bc00SMichael J. Ruhl return 0; 165f48ad614SDennis Dalessandro } 166f48ad614SDennis Dalessandro 167f48ad614SDennis Dalessandro /* 168f2a3bc00SMichael J. Ruhl * Create the receive context array and one or more kernel contexts 169f48ad614SDennis Dalessandro */ 170f2a3bc00SMichael J. Ruhl int hfi1_create_kctxts(struct hfi1_devdata *dd) 171f2a3bc00SMichael J. Ruhl { 172f2a3bc00SMichael J. Ruhl u16 i; 173f2a3bc00SMichael J. Ruhl int ret; 174f2a3bc00SMichael J. Ruhl 175953a9cebSKamenee Arumugam dd->rcd = kcalloc_node(dd->num_rcv_contexts, sizeof(*dd->rcd), 176f2a3bc00SMichael J. Ruhl GFP_KERNEL, dd->node); 177f2a3bc00SMichael J. Ruhl if (!dd->rcd) 178f2a3bc00SMichael J. Ruhl return -ENOMEM; 179f2a3bc00SMichael J. Ruhl 180f2a3bc00SMichael J. Ruhl for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) { 181f2a3bc00SMichael J. Ruhl ret = hfi1_create_kctxt(dd, dd->pport); 182f2a3bc00SMichael J. Ruhl if (ret) 183f2a3bc00SMichael J. Ruhl goto bail; 184f2a3bc00SMichael J. Ruhl } 185f48ad614SDennis Dalessandro 186f48ad614SDennis Dalessandro return 0; 187f2a3bc00SMichael J. Ruhl bail: 188f683c80cSMichael J. Ruhl for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) 189d295dbebSMichael J. Ruhl hfi1_free_ctxt(dd->rcd[i]); 190f683c80cSMichael J. Ruhl 191f683c80cSMichael J. Ruhl /* All the contexts should be freed, free the array */ 192f48ad614SDennis Dalessandro kfree(dd->rcd); 193f48ad614SDennis Dalessandro dd->rcd = NULL; 194f48ad614SDennis Dalessandro return ret; 195f48ad614SDennis Dalessandro } 196f48ad614SDennis Dalessandro 197f48ad614SDennis Dalessandro /* 198d295dbebSMichael J. Ruhl * Helper routines for the receive context reference count (rcd and uctxt). 199f683c80cSMichael J. Ruhl */ 200f683c80cSMichael J. Ruhl static void hfi1_rcd_init(struct hfi1_ctxtdata *rcd) 201f683c80cSMichael J. Ruhl { 202f683c80cSMichael J. Ruhl kref_init(&rcd->kref); 203f683c80cSMichael J. Ruhl } 204f683c80cSMichael J. Ruhl 205f2a3bc00SMichael J. Ruhl /** 206f2a3bc00SMichael J. Ruhl * hfi1_rcd_free - When reference is zero clean up. 207f2a3bc00SMichael J. Ruhl * @kref: pointer to an initialized rcd data structure 208f2a3bc00SMichael J. Ruhl * 209f2a3bc00SMichael J. Ruhl */ 210f683c80cSMichael J. Ruhl static void hfi1_rcd_free(struct kref *kref) 211f683c80cSMichael J. Ruhl { 212d295dbebSMichael J. Ruhl unsigned long flags; 213f683c80cSMichael J. Ruhl struct hfi1_ctxtdata *rcd = 214f683c80cSMichael J. Ruhl container_of(kref, struct hfi1_ctxtdata, kref); 215f683c80cSMichael J. Ruhl 216f683c80cSMichael J. Ruhl hfi1_free_ctxtdata(rcd->dd, rcd); 217d295dbebSMichael J. Ruhl 218d295dbebSMichael J. Ruhl spin_lock_irqsave(&rcd->dd->uctxt_lock, flags); 219d295dbebSMichael J. Ruhl rcd->dd->rcd[rcd->ctxt] = NULL; 220d295dbebSMichael J. Ruhl spin_unlock_irqrestore(&rcd->dd->uctxt_lock, flags); 221d295dbebSMichael J. Ruhl 222f683c80cSMichael J. Ruhl kfree(rcd); 223f683c80cSMichael J. Ruhl } 224f683c80cSMichael J. Ruhl 225f2a3bc00SMichael J. Ruhl /** 226f2a3bc00SMichael J. Ruhl * hfi1_rcd_put - decrement reference for rcd 227f2a3bc00SMichael J. Ruhl * @rcd: pointer to an initialized rcd data structure 228f2a3bc00SMichael J. Ruhl * 229f2a3bc00SMichael J. Ruhl * Use this to put a reference after the init. 230f2a3bc00SMichael J. Ruhl */ 231f683c80cSMichael J. Ruhl int hfi1_rcd_put(struct hfi1_ctxtdata *rcd) 232f683c80cSMichael J. Ruhl { 233f683c80cSMichael J. Ruhl if (rcd) 234f683c80cSMichael J. Ruhl return kref_put(&rcd->kref, hfi1_rcd_free); 235f683c80cSMichael J. Ruhl 236f683c80cSMichael J. Ruhl return 0; 237f683c80cSMichael J. Ruhl } 238f683c80cSMichael J. Ruhl 239f2a3bc00SMichael J. Ruhl /** 240f2a3bc00SMichael J. Ruhl * hfi1_rcd_get - increment reference for rcd 241f2a3bc00SMichael J. Ruhl * @rcd: pointer to an initialized rcd data structure 242f2a3bc00SMichael J. Ruhl * 243f2a3bc00SMichael J. Ruhl * Use this to get a reference after the init. 244f2a3bc00SMichael J. Ruhl */ 245f683c80cSMichael J. Ruhl void hfi1_rcd_get(struct hfi1_ctxtdata *rcd) 246f683c80cSMichael J. Ruhl { 247f683c80cSMichael J. Ruhl kref_get(&rcd->kref); 248f683c80cSMichael J. Ruhl } 249f683c80cSMichael J. Ruhl 250f2a3bc00SMichael J. Ruhl /** 251f2a3bc00SMichael J. Ruhl * allocate_rcd_index - allocate an rcd index from the rcd array 252f2a3bc00SMichael J. Ruhl * @dd: pointer to a valid devdata structure 253f2a3bc00SMichael J. Ruhl * @rcd: rcd data structure to assign 254f2a3bc00SMichael J. Ruhl * @index: pointer to index that is allocated 255f2a3bc00SMichael J. Ruhl * 256f2a3bc00SMichael J. Ruhl * Find an empty index in the rcd array, and assign the given rcd to it. 257f2a3bc00SMichael J. Ruhl * If the array is full, we are EBUSY. 258f2a3bc00SMichael J. Ruhl * 259f2a3bc00SMichael J. Ruhl */ 260d295dbebSMichael J. Ruhl static int allocate_rcd_index(struct hfi1_devdata *dd, 261f2a3bc00SMichael J. Ruhl struct hfi1_ctxtdata *rcd, u16 *index) 262f2a3bc00SMichael J. Ruhl { 263f2a3bc00SMichael J. Ruhl unsigned long flags; 264f2a3bc00SMichael J. Ruhl u16 ctxt; 265f2a3bc00SMichael J. Ruhl 266f2a3bc00SMichael J. Ruhl spin_lock_irqsave(&dd->uctxt_lock, flags); 267f2a3bc00SMichael J. Ruhl for (ctxt = 0; ctxt < dd->num_rcv_contexts; ctxt++) 268f2a3bc00SMichael J. Ruhl if (!dd->rcd[ctxt]) 269f2a3bc00SMichael J. Ruhl break; 270f2a3bc00SMichael J. Ruhl 271f2a3bc00SMichael J. Ruhl if (ctxt < dd->num_rcv_contexts) { 272f2a3bc00SMichael J. Ruhl rcd->ctxt = ctxt; 273f2a3bc00SMichael J. Ruhl dd->rcd[ctxt] = rcd; 274f2a3bc00SMichael J. Ruhl hfi1_rcd_init(rcd); 275f2a3bc00SMichael J. Ruhl } 276f2a3bc00SMichael J. Ruhl spin_unlock_irqrestore(&dd->uctxt_lock, flags); 277f2a3bc00SMichael J. Ruhl 278f2a3bc00SMichael J. Ruhl if (ctxt >= dd->num_rcv_contexts) 279f2a3bc00SMichael J. Ruhl return -EBUSY; 280f2a3bc00SMichael J. Ruhl 281f2a3bc00SMichael J. Ruhl *index = ctxt; 282f2a3bc00SMichael J. Ruhl 283f2a3bc00SMichael J. Ruhl return 0; 284f2a3bc00SMichael J. Ruhl } 285f2a3bc00SMichael J. Ruhl 286d295dbebSMichael J. Ruhl /** 287d59075adSMichael J. Ruhl * hfi1_rcd_get_by_index_safe - validate the ctxt index before accessing the 288d59075adSMichael J. Ruhl * array 289d59075adSMichael J. Ruhl * @dd: pointer to a valid devdata structure 290d59075adSMichael J. Ruhl * @ctxt: the index of an possilbe rcd 291d59075adSMichael J. Ruhl * 292d59075adSMichael J. Ruhl * This is a wrapper for hfi1_rcd_get_by_index() to validate that the given 293d59075adSMichael J. Ruhl * ctxt index is valid. 294d59075adSMichael J. Ruhl * 295d59075adSMichael J. Ruhl * The caller is responsible for making the _put(). 296d59075adSMichael J. Ruhl * 297d59075adSMichael J. Ruhl */ 298d59075adSMichael J. Ruhl struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd, 299d59075adSMichael J. Ruhl u16 ctxt) 300d59075adSMichael J. Ruhl { 301d59075adSMichael J. Ruhl if (ctxt < dd->num_rcv_contexts) 302d59075adSMichael J. Ruhl return hfi1_rcd_get_by_index(dd, ctxt); 303d59075adSMichael J. Ruhl 304d59075adSMichael J. Ruhl return NULL; 305d59075adSMichael J. Ruhl } 306d59075adSMichael J. Ruhl 307d59075adSMichael J. Ruhl /** 308d295dbebSMichael J. Ruhl * hfi1_rcd_get_by_index 309d295dbebSMichael J. Ruhl * @dd: pointer to a valid devdata structure 310d295dbebSMichael J. Ruhl * @ctxt: the index of an possilbe rcd 311d295dbebSMichael J. Ruhl * 312d295dbebSMichael J. Ruhl * We need to protect access to the rcd array. If access is needed to 313d295dbebSMichael J. Ruhl * one or more index, get the protecting spinlock and then increment the 314d295dbebSMichael J. Ruhl * kref. 315d295dbebSMichael J. Ruhl * 316d295dbebSMichael J. Ruhl * The caller is responsible for making the _put(). 317d295dbebSMichael J. Ruhl * 318d295dbebSMichael J. Ruhl */ 319d295dbebSMichael J. Ruhl struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt) 320d295dbebSMichael J. Ruhl { 321d295dbebSMichael J. Ruhl unsigned long flags; 322d295dbebSMichael J. Ruhl struct hfi1_ctxtdata *rcd = NULL; 323d295dbebSMichael J. Ruhl 324d295dbebSMichael J. Ruhl spin_lock_irqsave(&dd->uctxt_lock, flags); 325d295dbebSMichael J. Ruhl if (dd->rcd[ctxt]) { 326d295dbebSMichael J. Ruhl rcd = dd->rcd[ctxt]; 327d295dbebSMichael J. Ruhl hfi1_rcd_get(rcd); 328d295dbebSMichael J. Ruhl } 329d295dbebSMichael J. Ruhl spin_unlock_irqrestore(&dd->uctxt_lock, flags); 330d295dbebSMichael J. Ruhl 331d295dbebSMichael J. Ruhl return rcd; 332d295dbebSMichael J. Ruhl } 333d295dbebSMichael J. Ruhl 334f683c80cSMichael J. Ruhl /* 335d295dbebSMichael J. Ruhl * Common code for user and kernel context create and setup. 336d295dbebSMichael J. Ruhl * NOTE: the initial kref is done here (hf1_rcd_init()). 337f48ad614SDennis Dalessandro */ 338f2a3bc00SMichael J. Ruhl int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa, 339f2a3bc00SMichael J. Ruhl struct hfi1_ctxtdata **context) 340f48ad614SDennis Dalessandro { 341f48ad614SDennis Dalessandro struct hfi1_devdata *dd = ppd->dd; 342f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd; 343f48ad614SDennis Dalessandro unsigned kctxt_ngroups = 0; 344f48ad614SDennis Dalessandro u32 base; 345f48ad614SDennis Dalessandro 346f48ad614SDennis Dalessandro if (dd->rcv_entries.nctxt_extra > 3472280740fSVishwanathapura, Niranjana dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt) 348f48ad614SDennis Dalessandro kctxt_ngroups = (dd->rcv_entries.nctxt_extra - 3492280740fSVishwanathapura, Niranjana (dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt)); 3504dfe7cceSJianxin Xiong rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa); 351f48ad614SDennis Dalessandro if (rcd) { 352f48ad614SDennis Dalessandro u32 rcvtids, max_entries; 353f2a3bc00SMichael J. Ruhl u16 ctxt; 354f2a3bc00SMichael J. Ruhl int ret; 355f48ad614SDennis Dalessandro 356f2a3bc00SMichael J. Ruhl ret = allocate_rcd_index(dd, rcd, &ctxt); 357f2a3bc00SMichael J. Ruhl if (ret) { 358f2a3bc00SMichael J. Ruhl *context = NULL; 359f2a3bc00SMichael J. Ruhl kfree(rcd); 360f2a3bc00SMichael J. Ruhl return ret; 361f2a3bc00SMichael J. Ruhl } 362f2a3bc00SMichael J. Ruhl 363f48ad614SDennis Dalessandro INIT_LIST_HEAD(&rcd->qp_wait_list); 364fe4e74eeSMichael J. Ruhl hfi1_exp_tid_group_init(&rcd->tid_group_list); 365fe4e74eeSMichael J. Ruhl hfi1_exp_tid_group_init(&rcd->tid_used_list); 366fe4e74eeSMichael J. Ruhl hfi1_exp_tid_group_init(&rcd->tid_full_list); 367f48ad614SDennis Dalessandro rcd->ppd = ppd; 368f48ad614SDennis Dalessandro rcd->dd = dd; 3698737ce95SMichael J. Ruhl __set_bit(0, rcd->in_use_ctxts); 370f48ad614SDennis Dalessandro rcd->numa_id = numa; 371f48ad614SDennis Dalessandro rcd->rcv_array_groups = dd->rcv_entries.ngroups; 372f48ad614SDennis Dalessandro 373f48ad614SDennis Dalessandro mutex_init(&rcd->exp_lock); 374f48ad614SDennis Dalessandro 375d295dbebSMichael J. Ruhl hfi1_cdbg(PROC, "setting up context %u\n", rcd->ctxt); 376d295dbebSMichael J. Ruhl 377f48ad614SDennis Dalessandro /* 378f48ad614SDennis Dalessandro * Calculate the context's RcvArray entry starting point. 379f48ad614SDennis Dalessandro * We do this here because we have to take into account all 380f48ad614SDennis Dalessandro * the RcvArray entries that previous context would have 3812280740fSVishwanathapura, Niranjana * taken and we have to account for any extra groups assigned 3822280740fSVishwanathapura, Niranjana * to the static (kernel) or dynamic (vnic/user) contexts. 383f48ad614SDennis Dalessandro */ 3842280740fSVishwanathapura, Niranjana if (ctxt < dd->first_dyn_alloc_ctxt) { 385f48ad614SDennis Dalessandro if (ctxt < kctxt_ngroups) { 386f48ad614SDennis Dalessandro base = ctxt * (dd->rcv_entries.ngroups + 1); 387f48ad614SDennis Dalessandro rcd->rcv_array_groups++; 388ee495adaSDennis Dalessandro } else { 389f48ad614SDennis Dalessandro base = kctxt_ngroups + 390f48ad614SDennis Dalessandro (ctxt * dd->rcv_entries.ngroups); 391ee495adaSDennis Dalessandro } 392f48ad614SDennis Dalessandro } else { 3932280740fSVishwanathapura, Niranjana u16 ct = ctxt - dd->first_dyn_alloc_ctxt; 394f48ad614SDennis Dalessandro 395f48ad614SDennis Dalessandro base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) + 396f48ad614SDennis Dalessandro kctxt_ngroups); 397f48ad614SDennis Dalessandro if (ct < dd->rcv_entries.nctxt_extra) { 398f48ad614SDennis Dalessandro base += ct * (dd->rcv_entries.ngroups + 1); 399f48ad614SDennis Dalessandro rcd->rcv_array_groups++; 400ee495adaSDennis Dalessandro } else { 401f48ad614SDennis Dalessandro base += dd->rcv_entries.nctxt_extra + 402f48ad614SDennis Dalessandro (ct * dd->rcv_entries.ngroups); 403f48ad614SDennis Dalessandro } 404ee495adaSDennis Dalessandro } 405f48ad614SDennis Dalessandro rcd->eager_base = base * dd->rcv_entries.group_size; 406f48ad614SDennis Dalessandro 407f48ad614SDennis Dalessandro rcd->rcvhdrq_cnt = rcvhdrcnt; 408f48ad614SDennis Dalessandro rcd->rcvhdrqentsize = hfi1_hdrq_entsize; 409f48ad614SDennis Dalessandro /* 410f48ad614SDennis Dalessandro * Simple Eager buffer allocation: we have already pre-allocated 411f48ad614SDennis Dalessandro * the number of RcvArray entry groups. Each ctxtdata structure 412f48ad614SDennis Dalessandro * holds the number of groups for that context. 413f48ad614SDennis Dalessandro * 414f48ad614SDennis Dalessandro * To follow CSR requirements and maintain cacheline alignment, 415f48ad614SDennis Dalessandro * make sure all sizes and bases are multiples of group_size. 416f48ad614SDennis Dalessandro * 417f48ad614SDennis Dalessandro * The expected entry count is what is left after assigning 418f48ad614SDennis Dalessandro * eager. 419f48ad614SDennis Dalessandro */ 420f48ad614SDennis Dalessandro max_entries = rcd->rcv_array_groups * 421f48ad614SDennis Dalessandro dd->rcv_entries.group_size; 422f48ad614SDennis Dalessandro rcvtids = ((max_entries * hfi1_rcvarr_split) / 100); 423f48ad614SDennis Dalessandro rcd->egrbufs.count = round_down(rcvtids, 424f48ad614SDennis Dalessandro dd->rcv_entries.group_size); 425f48ad614SDennis Dalessandro if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) { 426f48ad614SDennis Dalessandro dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n", 427f48ad614SDennis Dalessandro rcd->ctxt); 428f48ad614SDennis Dalessandro rcd->egrbufs.count = MAX_EAGER_ENTRIES; 429f48ad614SDennis Dalessandro } 430f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 431f48ad614SDennis Dalessandro "ctxt%u: max Eager buffer RcvArray entries: %u\n", 432f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.count); 433f48ad614SDennis Dalessandro 434f48ad614SDennis Dalessandro /* 435f48ad614SDennis Dalessandro * Allocate array that will hold the eager buffer accounting 436f48ad614SDennis Dalessandro * data. 437f48ad614SDennis Dalessandro * This will allocate the maximum possible buffer count based 438f48ad614SDennis Dalessandro * on the value of the RcvArray split parameter. 439f48ad614SDennis Dalessandro * The resulting value will be rounded down to the closest 440f48ad614SDennis Dalessandro * multiple of dd->rcv_entries.group_size. 441f48ad614SDennis Dalessandro */ 442953a9cebSKamenee Arumugam rcd->egrbufs.buffers = 443953a9cebSKamenee Arumugam kcalloc_node(rcd->egrbufs.count, 444953a9cebSKamenee Arumugam sizeof(*rcd->egrbufs.buffers), 445b448bf9aSSebastian Sanchez GFP_KERNEL, numa); 446f48ad614SDennis Dalessandro if (!rcd->egrbufs.buffers) 447f48ad614SDennis Dalessandro goto bail; 448953a9cebSKamenee Arumugam rcd->egrbufs.rcvtids = 449953a9cebSKamenee Arumugam kcalloc_node(rcd->egrbufs.count, 450f48ad614SDennis Dalessandro sizeof(*rcd->egrbufs.rcvtids), 451b448bf9aSSebastian Sanchez GFP_KERNEL, numa); 452f48ad614SDennis Dalessandro if (!rcd->egrbufs.rcvtids) 453f48ad614SDennis Dalessandro goto bail; 454f48ad614SDennis Dalessandro rcd->egrbufs.size = eager_buffer_size; 455f48ad614SDennis Dalessandro /* 456f48ad614SDennis Dalessandro * The size of the buffers programmed into the RcvArray 457f48ad614SDennis Dalessandro * entries needs to be big enough to handle the highest 458f48ad614SDennis Dalessandro * MTU supported. 459f48ad614SDennis Dalessandro */ 460f48ad614SDennis Dalessandro if (rcd->egrbufs.size < hfi1_max_mtu) { 461f48ad614SDennis Dalessandro rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu); 462f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 463f48ad614SDennis Dalessandro "ctxt%u: eager bufs size too small. Adjusting to %zu\n", 464f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.size); 465f48ad614SDennis Dalessandro } 466f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE; 467f48ad614SDennis Dalessandro 4682280740fSVishwanathapura, Niranjana /* Applicable only for statically created kernel contexts */ 4692280740fSVishwanathapura, Niranjana if (ctxt < dd->first_dyn_alloc_ctxt) { 470b448bf9aSSebastian Sanchez rcd->opstats = kzalloc_node(sizeof(*rcd->opstats), 471b448bf9aSSebastian Sanchez GFP_KERNEL, numa); 472f48ad614SDennis Dalessandro if (!rcd->opstats) 473f48ad614SDennis Dalessandro goto bail; 474f48ad614SDennis Dalessandro } 475f683c80cSMichael J. Ruhl 476f2a3bc00SMichael J. Ruhl *context = rcd; 477f2a3bc00SMichael J. Ruhl return 0; 478f48ad614SDennis Dalessandro } 479f2a3bc00SMichael J. Ruhl 480f48ad614SDennis Dalessandro bail: 481f2a3bc00SMichael J. Ruhl *context = NULL; 482d295dbebSMichael J. Ruhl hfi1_free_ctxt(rcd); 483f2a3bc00SMichael J. Ruhl return -ENOMEM; 484f2a3bc00SMichael J. Ruhl } 485f2a3bc00SMichael J. Ruhl 486f2a3bc00SMichael J. Ruhl /** 487f2a3bc00SMichael J. Ruhl * hfi1_free_ctxt 488f2a3bc00SMichael J. Ruhl * @rcd: pointer to an initialized rcd data structure 489f2a3bc00SMichael J. Ruhl * 490d295dbebSMichael J. Ruhl * This wrapper is the free function that matches hfi1_create_ctxtdata(). 491d295dbebSMichael J. Ruhl * When a context is done being used (kernel or user), this function is called 492d295dbebSMichael J. Ruhl * for the "final" put to match the kref init from hf1i_create_ctxtdata(). 493d295dbebSMichael J. Ruhl * Other users of the context do a get/put sequence to make sure that the 494d295dbebSMichael J. Ruhl * structure isn't removed while in use. 495f2a3bc00SMichael J. Ruhl */ 496d295dbebSMichael J. Ruhl void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd) 497f2a3bc00SMichael J. Ruhl { 498f2a3bc00SMichael J. Ruhl hfi1_rcd_put(rcd); 499f2a3bc00SMichael J. Ruhl } 500f48ad614SDennis Dalessandro 501f48ad614SDennis Dalessandro /* 502f48ad614SDennis Dalessandro * Convert a receive header entry size that to the encoding used in the CSR. 503f48ad614SDennis Dalessandro * 504f48ad614SDennis Dalessandro * Return a zero if the given size is invalid. 505f48ad614SDennis Dalessandro */ 506f48ad614SDennis Dalessandro static inline u64 encode_rcv_header_entry_size(u16 size) 507f48ad614SDennis Dalessandro { 508f48ad614SDennis Dalessandro /* there are only 3 valid receive header entry sizes */ 509f48ad614SDennis Dalessandro if (size == 2) 510f48ad614SDennis Dalessandro return 1; 511f48ad614SDennis Dalessandro if (size == 16) 512f48ad614SDennis Dalessandro return 2; 513f48ad614SDennis Dalessandro else if (size == 32) 514f48ad614SDennis Dalessandro return 4; 515f48ad614SDennis Dalessandro return 0; /* invalid */ 516f48ad614SDennis Dalessandro } 517f48ad614SDennis Dalessandro 518f48ad614SDennis Dalessandro /* 519f48ad614SDennis Dalessandro * Select the largest ccti value over all SLs to determine the intra- 520f48ad614SDennis Dalessandro * packet gap for the link. 521f48ad614SDennis Dalessandro * 522f48ad614SDennis Dalessandro * called with cca_timer_lock held (to protect access to cca_timer 523f48ad614SDennis Dalessandro * array), and rcu_read_lock() (to protect access to cc_state). 524f48ad614SDennis Dalessandro */ 525f48ad614SDennis Dalessandro void set_link_ipg(struct hfi1_pportdata *ppd) 526f48ad614SDennis Dalessandro { 527f48ad614SDennis Dalessandro struct hfi1_devdata *dd = ppd->dd; 528f48ad614SDennis Dalessandro struct cc_state *cc_state; 529f48ad614SDennis Dalessandro int i; 530f48ad614SDennis Dalessandro u16 cce, ccti_limit, max_ccti = 0; 531f48ad614SDennis Dalessandro u16 shift, mult; 532f48ad614SDennis Dalessandro u64 src; 533f48ad614SDennis Dalessandro u32 current_egress_rate; /* Mbits /sec */ 534f48ad614SDennis Dalessandro u32 max_pkt_time; 535f48ad614SDennis Dalessandro /* 536f48ad614SDennis Dalessandro * max_pkt_time is the maximum packet egress time in units 537f48ad614SDennis Dalessandro * of the fabric clock period 1/(805 MHz). 538f48ad614SDennis Dalessandro */ 539f48ad614SDennis Dalessandro 540f48ad614SDennis Dalessandro cc_state = get_cc_state(ppd); 541f48ad614SDennis Dalessandro 542f48ad614SDennis Dalessandro if (!cc_state) 543f48ad614SDennis Dalessandro /* 544f48ad614SDennis Dalessandro * This should _never_ happen - rcu_read_lock() is held, 545f48ad614SDennis Dalessandro * and set_link_ipg() should not be called if cc_state 546f48ad614SDennis Dalessandro * is NULL. 547f48ad614SDennis Dalessandro */ 548f48ad614SDennis Dalessandro return; 549f48ad614SDennis Dalessandro 550f48ad614SDennis Dalessandro for (i = 0; i < OPA_MAX_SLS; i++) { 551f48ad614SDennis Dalessandro u16 ccti = ppd->cca_timer[i].ccti; 552f48ad614SDennis Dalessandro 553f48ad614SDennis Dalessandro if (ccti > max_ccti) 554f48ad614SDennis Dalessandro max_ccti = ccti; 555f48ad614SDennis Dalessandro } 556f48ad614SDennis Dalessandro 557f48ad614SDennis Dalessandro ccti_limit = cc_state->cct.ccti_limit; 558f48ad614SDennis Dalessandro if (max_ccti > ccti_limit) 559f48ad614SDennis Dalessandro max_ccti = ccti_limit; 560f48ad614SDennis Dalessandro 561f48ad614SDennis Dalessandro cce = cc_state->cct.entries[max_ccti].entry; 562f48ad614SDennis Dalessandro shift = (cce & 0xc000) >> 14; 563f48ad614SDennis Dalessandro mult = (cce & 0x3fff); 564f48ad614SDennis Dalessandro 565f48ad614SDennis Dalessandro current_egress_rate = active_egress_rate(ppd); 566f48ad614SDennis Dalessandro 567f48ad614SDennis Dalessandro max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate); 568f48ad614SDennis Dalessandro 569f48ad614SDennis Dalessandro src = (max_pkt_time >> shift) * mult; 570f48ad614SDennis Dalessandro 571f48ad614SDennis Dalessandro src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK; 572f48ad614SDennis Dalessandro src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT; 573f48ad614SDennis Dalessandro 574f48ad614SDennis Dalessandro write_csr(dd, SEND_STATIC_RATE_CONTROL, src); 575f48ad614SDennis Dalessandro } 576f48ad614SDennis Dalessandro 577f48ad614SDennis Dalessandro static enum hrtimer_restart cca_timer_fn(struct hrtimer *t) 578f48ad614SDennis Dalessandro { 579f48ad614SDennis Dalessandro struct cca_timer *cca_timer; 580f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 581f48ad614SDennis Dalessandro int sl; 582f48ad614SDennis Dalessandro u16 ccti_timer, ccti_min; 583f48ad614SDennis Dalessandro struct cc_state *cc_state; 584f48ad614SDennis Dalessandro unsigned long flags; 585f48ad614SDennis Dalessandro enum hrtimer_restart ret = HRTIMER_NORESTART; 586f48ad614SDennis Dalessandro 587f48ad614SDennis Dalessandro cca_timer = container_of(t, struct cca_timer, hrtimer); 588f48ad614SDennis Dalessandro ppd = cca_timer->ppd; 589f48ad614SDennis Dalessandro sl = cca_timer->sl; 590f48ad614SDennis Dalessandro 591f48ad614SDennis Dalessandro rcu_read_lock(); 592f48ad614SDennis Dalessandro 593f48ad614SDennis Dalessandro cc_state = get_cc_state(ppd); 594f48ad614SDennis Dalessandro 595f48ad614SDennis Dalessandro if (!cc_state) { 596f48ad614SDennis Dalessandro rcu_read_unlock(); 597f48ad614SDennis Dalessandro return HRTIMER_NORESTART; 598f48ad614SDennis Dalessandro } 599f48ad614SDennis Dalessandro 600f48ad614SDennis Dalessandro /* 601f48ad614SDennis Dalessandro * 1) decrement ccti for SL 602f48ad614SDennis Dalessandro * 2) calculate IPG for link (set_link_ipg()) 603f48ad614SDennis Dalessandro * 3) restart timer, unless ccti is at min value 604f48ad614SDennis Dalessandro */ 605f48ad614SDennis Dalessandro 606f48ad614SDennis Dalessandro ccti_min = cc_state->cong_setting.entries[sl].ccti_min; 607f48ad614SDennis Dalessandro ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer; 608f48ad614SDennis Dalessandro 609f48ad614SDennis Dalessandro spin_lock_irqsave(&ppd->cca_timer_lock, flags); 610f48ad614SDennis Dalessandro 611f48ad614SDennis Dalessandro if (cca_timer->ccti > ccti_min) { 612f48ad614SDennis Dalessandro cca_timer->ccti--; 613f48ad614SDennis Dalessandro set_link_ipg(ppd); 614f48ad614SDennis Dalessandro } 615f48ad614SDennis Dalessandro 616f48ad614SDennis Dalessandro if (cca_timer->ccti > ccti_min) { 617f48ad614SDennis Dalessandro unsigned long nsec = 1024 * ccti_timer; 618f48ad614SDennis Dalessandro /* ccti_timer is in units of 1.024 usec */ 619f48ad614SDennis Dalessandro hrtimer_forward_now(t, ns_to_ktime(nsec)); 620f48ad614SDennis Dalessandro ret = HRTIMER_RESTART; 621f48ad614SDennis Dalessandro } 622f48ad614SDennis Dalessandro 623f48ad614SDennis Dalessandro spin_unlock_irqrestore(&ppd->cca_timer_lock, flags); 624f48ad614SDennis Dalessandro rcu_read_unlock(); 625f48ad614SDennis Dalessandro return ret; 626f48ad614SDennis Dalessandro } 627f48ad614SDennis Dalessandro 628f48ad614SDennis Dalessandro /* 629f48ad614SDennis Dalessandro * Common code for initializing the physical port structure. 630f48ad614SDennis Dalessandro */ 631f48ad614SDennis Dalessandro void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, 632f48ad614SDennis Dalessandro struct hfi1_devdata *dd, u8 hw_pidx, u8 port) 633f48ad614SDennis Dalessandro { 6348adf71faSJianxin Xiong int i; 635f48ad614SDennis Dalessandro uint default_pkey_idx; 6368adf71faSJianxin Xiong struct cc_state *cc_state; 637f48ad614SDennis Dalessandro 638f48ad614SDennis Dalessandro ppd->dd = dd; 639f48ad614SDennis Dalessandro ppd->hw_pidx = hw_pidx; 640f48ad614SDennis Dalessandro ppd->port = port; /* IB port number, not index */ 64107190076SKamenee Arumugam ppd->prev_link_width = LINK_WIDTH_DEFAULT; 64207190076SKamenee Arumugam /* 64307190076SKamenee Arumugam * There are C_VL_COUNT number of PortVLXmitWait counters. 64407190076SKamenee Arumugam * Adding 1 to C_VL_COUNT to include the PortXmitWait counter. 64507190076SKamenee Arumugam */ 64607190076SKamenee Arumugam for (i = 0; i < C_VL_COUNT + 1; i++) { 64707190076SKamenee Arumugam ppd->port_vl_xmit_wait_last[i] = 0; 64807190076SKamenee Arumugam ppd->vl_xmit_flit_cnt[i] = 0; 64907190076SKamenee Arumugam } 650f48ad614SDennis Dalessandro 651f48ad614SDennis Dalessandro default_pkey_idx = 1; 652f48ad614SDennis Dalessandro 653f48ad614SDennis Dalessandro ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY; 65453526500SNeel Desai ppd->part_enforce |= HFI1_PART_ENFORCE_IN; 65553526500SNeel Desai 656f48ad614SDennis Dalessandro if (loopback) { 657f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 658f48ad614SDennis Dalessandro "Faking data partition 0x8001 in idx %u\n", 659f48ad614SDennis Dalessandro !default_pkey_idx); 660f48ad614SDennis Dalessandro ppd->pkeys[!default_pkey_idx] = 0x8001; 661f48ad614SDennis Dalessandro } 662f48ad614SDennis Dalessandro 663f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_vc_work, handle_verify_cap); 664f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_up_work, handle_link_up); 665f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_down_work, handle_link_down); 666f48ad614SDennis Dalessandro INIT_WORK(&ppd->freeze_work, handle_freeze); 667f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade); 668f48ad614SDennis Dalessandro INIT_WORK(&ppd->sma_message_work, handle_sma_message); 669f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_bounce_work, handle_link_bounce); 670673b975fSDean Luick INIT_DELAYED_WORK(&ppd->start_link_work, handle_start_link); 671f48ad614SDennis Dalessandro INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work); 672f48ad614SDennis Dalessandro INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event); 673f48ad614SDennis Dalessandro 674f48ad614SDennis Dalessandro mutex_init(&ppd->hls_lock); 675f48ad614SDennis Dalessandro spin_lock_init(&ppd->qsfp_info.qsfp_lock); 676f48ad614SDennis Dalessandro 677f48ad614SDennis Dalessandro ppd->qsfp_info.ppd = ppd; 678f48ad614SDennis Dalessandro ppd->sm_trap_qp = 0x0; 679f48ad614SDennis Dalessandro ppd->sa_qp = 0x1; 680f48ad614SDennis Dalessandro 681f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 682f48ad614SDennis Dalessandro 683f48ad614SDennis Dalessandro spin_lock_init(&ppd->cca_timer_lock); 684f48ad614SDennis Dalessandro 685f48ad614SDennis Dalessandro for (i = 0; i < OPA_MAX_SLS; i++) { 686f48ad614SDennis Dalessandro hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC, 687f48ad614SDennis Dalessandro HRTIMER_MODE_REL); 688f48ad614SDennis Dalessandro ppd->cca_timer[i].ppd = ppd; 689f48ad614SDennis Dalessandro ppd->cca_timer[i].sl = i; 690f48ad614SDennis Dalessandro ppd->cca_timer[i].ccti = 0; 691f48ad614SDennis Dalessandro ppd->cca_timer[i].hrtimer.function = cca_timer_fn; 692f48ad614SDennis Dalessandro } 693f48ad614SDennis Dalessandro 694f48ad614SDennis Dalessandro ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT; 695f48ad614SDennis Dalessandro 696f48ad614SDennis Dalessandro spin_lock_init(&ppd->cc_state_lock); 697f48ad614SDennis Dalessandro spin_lock_init(&ppd->cc_log_lock); 6988adf71faSJianxin Xiong cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL); 6998adf71faSJianxin Xiong RCU_INIT_POINTER(ppd->cc_state, cc_state); 7008adf71faSJianxin Xiong if (!cc_state) 701f48ad614SDennis Dalessandro goto bail; 702f48ad614SDennis Dalessandro return; 703f48ad614SDennis Dalessandro 704f48ad614SDennis Dalessandro bail: 705f48ad614SDennis Dalessandro 706f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 707f48ad614SDennis Dalessandro "Congestion Control Agent disabled for port %d\n", port); 708f48ad614SDennis Dalessandro } 709f48ad614SDennis Dalessandro 710f48ad614SDennis Dalessandro /* 711f48ad614SDennis Dalessandro * Do initialization for device that is only needed on 712f48ad614SDennis Dalessandro * first detect, not on resets. 713f48ad614SDennis Dalessandro */ 714f48ad614SDennis Dalessandro static int loadtime_init(struct hfi1_devdata *dd) 715f48ad614SDennis Dalessandro { 716f48ad614SDennis Dalessandro return 0; 717f48ad614SDennis Dalessandro } 718f48ad614SDennis Dalessandro 719f48ad614SDennis Dalessandro /** 720f48ad614SDennis Dalessandro * init_after_reset - re-initialize after a reset 721f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 722f48ad614SDennis Dalessandro * 723f48ad614SDennis Dalessandro * sanity check at least some of the values after reset, and 724f48ad614SDennis Dalessandro * ensure no receive or transmit (explicitly, in case reset 725f48ad614SDennis Dalessandro * failed 726f48ad614SDennis Dalessandro */ 727f48ad614SDennis Dalessandro static int init_after_reset(struct hfi1_devdata *dd) 728f48ad614SDennis Dalessandro { 729f48ad614SDennis Dalessandro int i; 730d295dbebSMichael J. Ruhl struct hfi1_ctxtdata *rcd; 731f48ad614SDennis Dalessandro /* 732f48ad614SDennis Dalessandro * Ensure chip does no sends or receives, tail updates, or 733f48ad614SDennis Dalessandro * pioavail updates while we re-initialize. This is mostly 734f48ad614SDennis Dalessandro * for the driver data structures, not chip registers. 735f48ad614SDennis Dalessandro */ 736d295dbebSMichael J. Ruhl for (i = 0; i < dd->num_rcv_contexts; i++) { 737d295dbebSMichael J. Ruhl rcd = hfi1_rcd_get_by_index(dd, i); 738f48ad614SDennis Dalessandro hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS | 739f48ad614SDennis Dalessandro HFI1_RCVCTRL_INTRAVAIL_DIS | 740d295dbebSMichael J. Ruhl HFI1_RCVCTRL_TAILUPD_DIS, rcd); 741d295dbebSMichael J. Ruhl hfi1_rcd_put(rcd); 742d295dbebSMichael J. Ruhl } 743f48ad614SDennis Dalessandro pio_send_control(dd, PSC_GLOBAL_DISABLE); 744f48ad614SDennis Dalessandro for (i = 0; i < dd->num_send_contexts; i++) 745f48ad614SDennis Dalessandro sc_disable(dd->send_contexts[i].sc); 746f48ad614SDennis Dalessandro 747f48ad614SDennis Dalessandro return 0; 748f48ad614SDennis Dalessandro } 749f48ad614SDennis Dalessandro 750f48ad614SDennis Dalessandro static void enable_chip(struct hfi1_devdata *dd) 751f48ad614SDennis Dalessandro { 752d295dbebSMichael J. Ruhl struct hfi1_ctxtdata *rcd; 753f48ad614SDennis Dalessandro u32 rcvmask; 754e6f7622dSMichael J. Ruhl u16 i; 755f48ad614SDennis Dalessandro 756f48ad614SDennis Dalessandro /* enable PIO send */ 757f48ad614SDennis Dalessandro pio_send_control(dd, PSC_GLOBAL_ENABLE); 758f48ad614SDennis Dalessandro 759f48ad614SDennis Dalessandro /* 760f48ad614SDennis Dalessandro * Enable kernel ctxts' receive and receive interrupt. 761f48ad614SDennis Dalessandro * Other ctxts done as user opens and initializes them. 762f48ad614SDennis Dalessandro */ 7632280740fSVishwanathapura, Niranjana for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) { 764d295dbebSMichael J. Ruhl rcd = hfi1_rcd_get_by_index(dd, i); 765d295dbebSMichael J. Ruhl if (!rcd) 766d295dbebSMichael J. Ruhl continue; 767f48ad614SDennis Dalessandro rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB; 768d295dbebSMichael J. Ruhl rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ? 769f48ad614SDennis Dalessandro HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 770d295dbebSMichael J. Ruhl if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) 771f48ad614SDennis Dalessandro rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB; 772d295dbebSMichael J. Ruhl if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_RHQ_FULL)) 773f48ad614SDennis Dalessandro rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB; 774d295dbebSMichael J. Ruhl if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_EGR_FULL)) 775f48ad614SDennis Dalessandro rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB; 776d295dbebSMichael J. Ruhl hfi1_rcvctrl(dd, rcvmask, rcd); 777d295dbebSMichael J. Ruhl sc_enable(rcd->sc); 778d295dbebSMichael J. Ruhl hfi1_rcd_put(rcd); 779f48ad614SDennis Dalessandro } 780f48ad614SDennis Dalessandro } 781f48ad614SDennis Dalessandro 782f48ad614SDennis Dalessandro /** 783f48ad614SDennis Dalessandro * create_workqueues - create per port workqueues 784f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 785f48ad614SDennis Dalessandro */ 786f48ad614SDennis Dalessandro static int create_workqueues(struct hfi1_devdata *dd) 787f48ad614SDennis Dalessandro { 788f48ad614SDennis Dalessandro int pidx; 789f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 790f48ad614SDennis Dalessandro 791f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 792f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 793f48ad614SDennis Dalessandro if (!ppd->hfi1_wq) { 794f48ad614SDennis Dalessandro ppd->hfi1_wq = 795f48ad614SDennis Dalessandro alloc_workqueue( 796f48ad614SDennis Dalessandro "hfi%d_%d", 797f48ad614SDennis Dalessandro WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 798dd1ed108SMike Marciniszyn HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES, 799f48ad614SDennis Dalessandro dd->unit, pidx); 800f48ad614SDennis Dalessandro if (!ppd->hfi1_wq) 801f48ad614SDennis Dalessandro goto wq_error; 802f48ad614SDennis Dalessandro } 80371d47008SSebastian Sanchez if (!ppd->link_wq) { 80471d47008SSebastian Sanchez /* 80571d47008SSebastian Sanchez * Make the link workqueue single-threaded to enforce 80671d47008SSebastian Sanchez * serialization. 80771d47008SSebastian Sanchez */ 80871d47008SSebastian Sanchez ppd->link_wq = 80971d47008SSebastian Sanchez alloc_workqueue( 81071d47008SSebastian Sanchez "hfi_link_%d_%d", 81171d47008SSebastian Sanchez WQ_SYSFS | WQ_MEM_RECLAIM | WQ_UNBOUND, 81271d47008SSebastian Sanchez 1, /* max_active */ 81371d47008SSebastian Sanchez dd->unit, pidx); 81471d47008SSebastian Sanchez if (!ppd->link_wq) 81571d47008SSebastian Sanchez goto wq_error; 81671d47008SSebastian Sanchez } 817f48ad614SDennis Dalessandro } 818f48ad614SDennis Dalessandro return 0; 819f48ad614SDennis Dalessandro wq_error: 820f48ad614SDennis Dalessandro pr_err("alloc_workqueue failed for port %d\n", pidx + 1); 821f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 822f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 823f48ad614SDennis Dalessandro if (ppd->hfi1_wq) { 824f48ad614SDennis Dalessandro destroy_workqueue(ppd->hfi1_wq); 825f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 826f48ad614SDennis Dalessandro } 82771d47008SSebastian Sanchez if (ppd->link_wq) { 82871d47008SSebastian Sanchez destroy_workqueue(ppd->link_wq); 82971d47008SSebastian Sanchez ppd->link_wq = NULL; 83071d47008SSebastian Sanchez } 831f48ad614SDennis Dalessandro } 832f48ad614SDennis Dalessandro return -ENOMEM; 833f48ad614SDennis Dalessandro } 834f48ad614SDennis Dalessandro 835f48ad614SDennis Dalessandro /** 836f48ad614SDennis Dalessandro * hfi1_init - do the actual initialization sequence on the chip 837f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 838f48ad614SDennis Dalessandro * @reinit: re-initializing, so don't allocate new memory 839f48ad614SDennis Dalessandro * 840f48ad614SDennis Dalessandro * Do the actual initialization sequence on the chip. This is done 841f48ad614SDennis Dalessandro * both from the init routine called from the PCI infrastructure, and 842f48ad614SDennis Dalessandro * when we reset the chip, or detect that it was reset internally, 843f48ad614SDennis Dalessandro * or it's administratively re-enabled. 844f48ad614SDennis Dalessandro * 845f48ad614SDennis Dalessandro * Memory allocation here and in called routines is only done in 846f48ad614SDennis Dalessandro * the first case (reinit == 0). We have to be careful, because even 847f48ad614SDennis Dalessandro * without memory allocation, we need to re-write all the chip registers 848f48ad614SDennis Dalessandro * TIDs, etc. after the reset or enable has completed. 849f48ad614SDennis Dalessandro */ 850f48ad614SDennis Dalessandro int hfi1_init(struct hfi1_devdata *dd, int reinit) 851f48ad614SDennis Dalessandro { 852f48ad614SDennis Dalessandro int ret = 0, pidx, lastfail = 0; 853e6f7622dSMichael J. Ruhl unsigned long len; 854e6f7622dSMichael J. Ruhl u16 i; 855f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd; 856f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 857f48ad614SDennis Dalessandro 858f48ad614SDennis Dalessandro /* Set up recv low level handlers */ 859f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] = 860f48ad614SDennis Dalessandro kdeth_process_expected; 861f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] = 862f48ad614SDennis Dalessandro kdeth_process_eager; 863f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib; 864f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] = 865f48ad614SDennis Dalessandro process_receive_error; 866f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] = 867f48ad614SDennis Dalessandro process_receive_bypass; 868f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] = 869f48ad614SDennis Dalessandro process_receive_invalid; 870f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] = 871f48ad614SDennis Dalessandro process_receive_invalid; 872f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] = 873f48ad614SDennis Dalessandro process_receive_invalid; 874f48ad614SDennis Dalessandro dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions; 875f48ad614SDennis Dalessandro 876f48ad614SDennis Dalessandro /* Set up send low level handlers */ 877f48ad614SDennis Dalessandro dd->process_pio_send = hfi1_verbs_send_pio; 878f48ad614SDennis Dalessandro dd->process_dma_send = hfi1_verbs_send_dma; 879f48ad614SDennis Dalessandro dd->pio_inline_send = pio_copy; 88064551edeSVishwanathapura, Niranjana dd->process_vnic_dma_send = hfi1_vnic_send_dma; 881f48ad614SDennis Dalessandro 882f48ad614SDennis Dalessandro if (is_ax(dd)) { 883f48ad614SDennis Dalessandro atomic_set(&dd->drop_packet, DROP_PACKET_ON); 884f48ad614SDennis Dalessandro dd->do_drop = 1; 885f48ad614SDennis Dalessandro } else { 886f48ad614SDennis Dalessandro atomic_set(&dd->drop_packet, DROP_PACKET_OFF); 887f48ad614SDennis Dalessandro dd->do_drop = 0; 888f48ad614SDennis Dalessandro } 889f48ad614SDennis Dalessandro 890f48ad614SDennis Dalessandro /* make sure the link is not "up" */ 891f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 892f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 893f48ad614SDennis Dalessandro ppd->linkup = 0; 894f48ad614SDennis Dalessandro } 895f48ad614SDennis Dalessandro 896f48ad614SDennis Dalessandro if (reinit) 897f48ad614SDennis Dalessandro ret = init_after_reset(dd); 898f48ad614SDennis Dalessandro else 899f48ad614SDennis Dalessandro ret = loadtime_init(dd); 900f48ad614SDennis Dalessandro if (ret) 901f48ad614SDennis Dalessandro goto done; 902f48ad614SDennis Dalessandro 903f48ad614SDennis Dalessandro /* allocate dummy tail memory for all receive contexts */ 904f48ad614SDennis Dalessandro dd->rcvhdrtail_dummy_kvaddr = dma_zalloc_coherent( 905f48ad614SDennis Dalessandro &dd->pcidev->dev, sizeof(u64), 90660368186STymoteusz Kielan &dd->rcvhdrtail_dummy_dma, 907f48ad614SDennis Dalessandro GFP_KERNEL); 908f48ad614SDennis Dalessandro 909f48ad614SDennis Dalessandro if (!dd->rcvhdrtail_dummy_kvaddr) { 910f48ad614SDennis Dalessandro dd_dev_err(dd, "cannot allocate dummy tail memory\n"); 911f48ad614SDennis Dalessandro ret = -ENOMEM; 912f48ad614SDennis Dalessandro goto done; 913f48ad614SDennis Dalessandro } 914f48ad614SDennis Dalessandro 915f48ad614SDennis Dalessandro /* dd->rcd can be NULL if early initialization failed */ 9162280740fSVishwanathapura, Niranjana for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) { 917f48ad614SDennis Dalessandro /* 918f48ad614SDennis Dalessandro * Set up the (kernel) rcvhdr queue and egr TIDs. If doing 919f48ad614SDennis Dalessandro * re-init, the simplest way to handle this is to free 920f48ad614SDennis Dalessandro * existing, and re-allocate. 921f48ad614SDennis Dalessandro * Need to re-create rest of ctxt 0 ctxtdata as well. 922f48ad614SDennis Dalessandro */ 923d295dbebSMichael J. Ruhl rcd = hfi1_rcd_get_by_index(dd, i); 924f48ad614SDennis Dalessandro if (!rcd) 925f48ad614SDennis Dalessandro continue; 926f48ad614SDennis Dalessandro 927f48ad614SDennis Dalessandro rcd->do_interrupt = &handle_receive_interrupt; 928f48ad614SDennis Dalessandro 929f48ad614SDennis Dalessandro lastfail = hfi1_create_rcvhdrq(dd, rcd); 930f48ad614SDennis Dalessandro if (!lastfail) 931f48ad614SDennis Dalessandro lastfail = hfi1_setup_eagerbufs(rcd); 932f48ad614SDennis Dalessandro if (lastfail) { 933f48ad614SDennis Dalessandro dd_dev_err(dd, 934f48ad614SDennis Dalessandro "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n"); 935f48ad614SDennis Dalessandro ret = lastfail; 936f48ad614SDennis Dalessandro } 937d295dbebSMichael J. Ruhl hfi1_rcd_put(rcd); 938f48ad614SDennis Dalessandro } 939f48ad614SDennis Dalessandro 940f48ad614SDennis Dalessandro /* Allocate enough memory for user event notification. */ 941f48ad614SDennis Dalessandro len = PAGE_ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS * 942f48ad614SDennis Dalessandro sizeof(*dd->events)); 943f48ad614SDennis Dalessandro dd->events = vmalloc_user(len); 944f48ad614SDennis Dalessandro if (!dd->events) 945f48ad614SDennis Dalessandro dd_dev_err(dd, "Failed to allocate user events page\n"); 946f48ad614SDennis Dalessandro /* 947f48ad614SDennis Dalessandro * Allocate a page for device and port status. 948f48ad614SDennis Dalessandro * Page will be shared amongst all user processes. 949f48ad614SDennis Dalessandro */ 950f48ad614SDennis Dalessandro dd->status = vmalloc_user(PAGE_SIZE); 951f48ad614SDennis Dalessandro if (!dd->status) 952f48ad614SDennis Dalessandro dd_dev_err(dd, "Failed to allocate dev status page\n"); 953f48ad614SDennis Dalessandro else 954f48ad614SDennis Dalessandro dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) - 955f48ad614SDennis Dalessandro sizeof(dd->status->freezemsg)); 956f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 957f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 958f48ad614SDennis Dalessandro if (dd->status) 959f48ad614SDennis Dalessandro /* Currently, we only have one port */ 960f48ad614SDennis Dalessandro ppd->statusp = &dd->status->port; 961f48ad614SDennis Dalessandro 962f48ad614SDennis Dalessandro set_mtu(ppd); 963f48ad614SDennis Dalessandro } 964f48ad614SDennis Dalessandro 965f48ad614SDennis Dalessandro /* enable chip even if we have an error, so we can debug cause */ 966f48ad614SDennis Dalessandro enable_chip(dd); 967f48ad614SDennis Dalessandro 968f48ad614SDennis Dalessandro done: 969f48ad614SDennis Dalessandro /* 970f48ad614SDennis Dalessandro * Set status even if port serdes is not initialized 971f48ad614SDennis Dalessandro * so that diags will work. 972f48ad614SDennis Dalessandro */ 973f48ad614SDennis Dalessandro if (dd->status) 974f48ad614SDennis Dalessandro dd->status->dev |= HFI1_STATUS_CHIP_PRESENT | 975f48ad614SDennis Dalessandro HFI1_STATUS_INITTED; 976f48ad614SDennis Dalessandro if (!ret) { 977f48ad614SDennis Dalessandro /* enable all interrupts from the chip */ 978f48ad614SDennis Dalessandro set_intr_state(dd, 1); 979f48ad614SDennis Dalessandro 980f48ad614SDennis Dalessandro /* chip is OK for user apps; mark it as initialized */ 981f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 982f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 983f48ad614SDennis Dalessandro 984f48ad614SDennis Dalessandro /* 985f48ad614SDennis Dalessandro * start the serdes - must be after interrupts are 986f48ad614SDennis Dalessandro * enabled so we are notified when the link goes up 987f48ad614SDennis Dalessandro */ 988f48ad614SDennis Dalessandro lastfail = bringup_serdes(ppd); 989f48ad614SDennis Dalessandro if (lastfail) 990f48ad614SDennis Dalessandro dd_dev_info(dd, 991f48ad614SDennis Dalessandro "Failed to bring up port %u\n", 992f48ad614SDennis Dalessandro ppd->port); 993f48ad614SDennis Dalessandro 994f48ad614SDennis Dalessandro /* 995f48ad614SDennis Dalessandro * Set status even if port serdes is not initialized 996f48ad614SDennis Dalessandro * so that diags will work. 997f48ad614SDennis Dalessandro */ 998f48ad614SDennis Dalessandro if (ppd->statusp) 999f48ad614SDennis Dalessandro *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT | 1000f48ad614SDennis Dalessandro HFI1_STATUS_INITTED; 1001f48ad614SDennis Dalessandro if (!ppd->link_speed_enabled) 1002f48ad614SDennis Dalessandro continue; 1003f48ad614SDennis Dalessandro } 1004f48ad614SDennis Dalessandro } 1005f48ad614SDennis Dalessandro 1006f48ad614SDennis Dalessandro /* if ret is non-zero, we probably should do some cleanup here... */ 1007f48ad614SDennis Dalessandro return ret; 1008f48ad614SDennis Dalessandro } 1009f48ad614SDennis Dalessandro 1010f48ad614SDennis Dalessandro static inline struct hfi1_devdata *__hfi1_lookup(int unit) 1011f48ad614SDennis Dalessandro { 1012f48ad614SDennis Dalessandro return idr_find(&hfi1_unit_table, unit); 1013f48ad614SDennis Dalessandro } 1014f48ad614SDennis Dalessandro 1015f48ad614SDennis Dalessandro struct hfi1_devdata *hfi1_lookup(int unit) 1016f48ad614SDennis Dalessandro { 1017f48ad614SDennis Dalessandro struct hfi1_devdata *dd; 1018f48ad614SDennis Dalessandro unsigned long flags; 1019f48ad614SDennis Dalessandro 1020f48ad614SDennis Dalessandro spin_lock_irqsave(&hfi1_devs_lock, flags); 1021f48ad614SDennis Dalessandro dd = __hfi1_lookup(unit); 1022f48ad614SDennis Dalessandro spin_unlock_irqrestore(&hfi1_devs_lock, flags); 1023f48ad614SDennis Dalessandro 1024f48ad614SDennis Dalessandro return dd; 1025f48ad614SDennis Dalessandro } 1026f48ad614SDennis Dalessandro 1027f48ad614SDennis Dalessandro /* 1028f48ad614SDennis Dalessandro * Stop the timers during unit shutdown, or after an error late 1029f48ad614SDennis Dalessandro * in initialization. 1030f48ad614SDennis Dalessandro */ 1031f48ad614SDennis Dalessandro static void stop_timers(struct hfi1_devdata *dd) 1032f48ad614SDennis Dalessandro { 1033f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 1034f48ad614SDennis Dalessandro int pidx; 1035f48ad614SDennis Dalessandro 1036f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1037f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 10388064135eSKees Cook if (ppd->led_override_timer.function) { 1039f48ad614SDennis Dalessandro del_timer_sync(&ppd->led_override_timer); 1040f48ad614SDennis Dalessandro atomic_set(&ppd->led_override_timer_active, 0); 1041f48ad614SDennis Dalessandro } 1042f48ad614SDennis Dalessandro } 1043f48ad614SDennis Dalessandro } 1044f48ad614SDennis Dalessandro 1045f48ad614SDennis Dalessandro /** 1046f48ad614SDennis Dalessandro * shutdown_device - shut down a device 1047f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 1048f48ad614SDennis Dalessandro * 1049f48ad614SDennis Dalessandro * This is called to make the device quiet when we are about to 1050f48ad614SDennis Dalessandro * unload the driver, and also when the device is administratively 1051f48ad614SDennis Dalessandro * disabled. It does not free any data structures. 1052f48ad614SDennis Dalessandro * Everything it does has to be setup again by hfi1_init(dd, 1) 1053f48ad614SDennis Dalessandro */ 1054f48ad614SDennis Dalessandro static void shutdown_device(struct hfi1_devdata *dd) 1055f48ad614SDennis Dalessandro { 1056f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 1057d295dbebSMichael J. Ruhl struct hfi1_ctxtdata *rcd; 1058f48ad614SDennis Dalessandro unsigned pidx; 1059f48ad614SDennis Dalessandro int i; 1060f48ad614SDennis Dalessandro 1061f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1062f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1063f48ad614SDennis Dalessandro 1064f48ad614SDennis Dalessandro ppd->linkup = 0; 1065f48ad614SDennis Dalessandro if (ppd->statusp) 1066f48ad614SDennis Dalessandro *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 1067f48ad614SDennis Dalessandro HFI1_STATUS_IB_READY); 1068f48ad614SDennis Dalessandro } 1069f48ad614SDennis Dalessandro dd->flags &= ~HFI1_INITTED; 1070f48ad614SDennis Dalessandro 107182a97926SMichael J. Ruhl /* mask and clean up interrupts, but not errors */ 1072f48ad614SDennis Dalessandro set_intr_state(dd, 0); 107382a97926SMichael J. Ruhl hfi1_clean_up_interrupts(dd); 1074f48ad614SDennis Dalessandro 1075f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1076f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1077d295dbebSMichael J. Ruhl for (i = 0; i < dd->num_rcv_contexts; i++) { 1078d295dbebSMichael J. Ruhl rcd = hfi1_rcd_get_by_index(dd, i); 1079f48ad614SDennis Dalessandro hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS | 1080f48ad614SDennis Dalessandro HFI1_RCVCTRL_CTXT_DIS | 1081f48ad614SDennis Dalessandro HFI1_RCVCTRL_INTRAVAIL_DIS | 1082f48ad614SDennis Dalessandro HFI1_RCVCTRL_PKEY_DIS | 1083d295dbebSMichael J. Ruhl HFI1_RCVCTRL_ONE_PKT_EGR_DIS, rcd); 1084d295dbebSMichael J. Ruhl hfi1_rcd_put(rcd); 1085d295dbebSMichael J. Ruhl } 1086f48ad614SDennis Dalessandro /* 1087f48ad614SDennis Dalessandro * Gracefully stop all sends allowing any in progress to 1088f48ad614SDennis Dalessandro * trickle out first. 1089f48ad614SDennis Dalessandro */ 1090f48ad614SDennis Dalessandro for (i = 0; i < dd->num_send_contexts; i++) 1091f48ad614SDennis Dalessandro sc_flush(dd->send_contexts[i].sc); 1092f48ad614SDennis Dalessandro } 1093f48ad614SDennis Dalessandro 1094f48ad614SDennis Dalessandro /* 1095f48ad614SDennis Dalessandro * Enough for anything that's going to trickle out to have actually 1096f48ad614SDennis Dalessandro * done so. 1097f48ad614SDennis Dalessandro */ 1098f48ad614SDennis Dalessandro udelay(20); 1099f48ad614SDennis Dalessandro 1100f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1101f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1102f48ad614SDennis Dalessandro 1103f48ad614SDennis Dalessandro /* disable all contexts */ 1104f48ad614SDennis Dalessandro for (i = 0; i < dd->num_send_contexts; i++) 1105f48ad614SDennis Dalessandro sc_disable(dd->send_contexts[i].sc); 1106f48ad614SDennis Dalessandro /* disable the send device */ 1107f48ad614SDennis Dalessandro pio_send_control(dd, PSC_GLOBAL_DISABLE); 1108f48ad614SDennis Dalessandro 1109f48ad614SDennis Dalessandro shutdown_led_override(ppd); 1110f48ad614SDennis Dalessandro 1111f48ad614SDennis Dalessandro /* 1112f48ad614SDennis Dalessandro * Clear SerdesEnable. 1113f48ad614SDennis Dalessandro * We can't count on interrupts since we are stopping. 1114f48ad614SDennis Dalessandro */ 1115f48ad614SDennis Dalessandro hfi1_quiet_serdes(ppd); 1116f48ad614SDennis Dalessandro 1117f48ad614SDennis Dalessandro if (ppd->hfi1_wq) { 1118f48ad614SDennis Dalessandro destroy_workqueue(ppd->hfi1_wq); 1119f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 1120f48ad614SDennis Dalessandro } 112171d47008SSebastian Sanchez if (ppd->link_wq) { 112271d47008SSebastian Sanchez destroy_workqueue(ppd->link_wq); 112371d47008SSebastian Sanchez ppd->link_wq = NULL; 112471d47008SSebastian Sanchez } 1125f48ad614SDennis Dalessandro } 1126f48ad614SDennis Dalessandro sdma_exit(dd); 1127f48ad614SDennis Dalessandro } 1128f48ad614SDennis Dalessandro 1129f48ad614SDennis Dalessandro /** 1130f48ad614SDennis Dalessandro * hfi1_free_ctxtdata - free a context's allocated data 1131f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 1132f48ad614SDennis Dalessandro * @rcd: the ctxtdata structure 1133f48ad614SDennis Dalessandro * 1134f48ad614SDennis Dalessandro * free up any allocated data for a context 1135f48ad614SDennis Dalessandro * It should never change any chip state, or global driver state. 1136f48ad614SDennis Dalessandro */ 1137f48ad614SDennis Dalessandro void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 1138f48ad614SDennis Dalessandro { 1139f683c80cSMichael J. Ruhl u32 e; 1140f48ad614SDennis Dalessandro 1141f48ad614SDennis Dalessandro if (!rcd) 1142f48ad614SDennis Dalessandro return; 1143f48ad614SDennis Dalessandro 1144f48ad614SDennis Dalessandro if (rcd->rcvhdrq) { 1145f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size, 114660368186STymoteusz Kielan rcd->rcvhdrq, rcd->rcvhdrq_dma); 1147f48ad614SDennis Dalessandro rcd->rcvhdrq = NULL; 1148f48ad614SDennis Dalessandro if (rcd->rcvhdrtail_kvaddr) { 1149f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, 1150f48ad614SDennis Dalessandro (void *)rcd->rcvhdrtail_kvaddr, 115160368186STymoteusz Kielan rcd->rcvhdrqtailaddr_dma); 1152f48ad614SDennis Dalessandro rcd->rcvhdrtail_kvaddr = NULL; 1153f48ad614SDennis Dalessandro } 1154f48ad614SDennis Dalessandro } 1155f48ad614SDennis Dalessandro 1156f48ad614SDennis Dalessandro /* all the RcvArray entries should have been cleared by now */ 1157f48ad614SDennis Dalessandro kfree(rcd->egrbufs.rcvtids); 1158f683c80cSMichael J. Ruhl rcd->egrbufs.rcvtids = NULL; 1159f48ad614SDennis Dalessandro 1160f48ad614SDennis Dalessandro for (e = 0; e < rcd->egrbufs.alloced; e++) { 116160368186STymoteusz Kielan if (rcd->egrbufs.buffers[e].dma) 1162f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, 1163f48ad614SDennis Dalessandro rcd->egrbufs.buffers[e].len, 1164f48ad614SDennis Dalessandro rcd->egrbufs.buffers[e].addr, 116560368186STymoteusz Kielan rcd->egrbufs.buffers[e].dma); 1166f48ad614SDennis Dalessandro } 1167f48ad614SDennis Dalessandro kfree(rcd->egrbufs.buffers); 1168f683c80cSMichael J. Ruhl rcd->egrbufs.alloced = 0; 1169f683c80cSMichael J. Ruhl rcd->egrbufs.buffers = NULL; 1170f48ad614SDennis Dalessandro 1171f48ad614SDennis Dalessandro sc_free(rcd->sc); 1172f683c80cSMichael J. Ruhl rcd->sc = NULL; 1173f683c80cSMichael J. Ruhl 1174f48ad614SDennis Dalessandro vfree(rcd->subctxt_uregbase); 1175f48ad614SDennis Dalessandro vfree(rcd->subctxt_rcvegrbuf); 1176f48ad614SDennis Dalessandro vfree(rcd->subctxt_rcvhdr_base); 1177f48ad614SDennis Dalessandro kfree(rcd->opstats); 1178f683c80cSMichael J. Ruhl 1179f683c80cSMichael J. Ruhl rcd->subctxt_uregbase = NULL; 1180f683c80cSMichael J. Ruhl rcd->subctxt_rcvegrbuf = NULL; 1181f683c80cSMichael J. Ruhl rcd->subctxt_rcvhdr_base = NULL; 1182f683c80cSMichael J. Ruhl rcd->opstats = NULL; 1183f48ad614SDennis Dalessandro } 1184f48ad614SDennis Dalessandro 1185f48ad614SDennis Dalessandro /* 1186f48ad614SDennis Dalessandro * Release our hold on the shared asic data. If we are the last one, 1187dba715f0SDean Luick * return the structure to be finalized outside the lock. Must be 1188dba715f0SDean Luick * holding hfi1_devs_lock. 1189f48ad614SDennis Dalessandro */ 1190dba715f0SDean Luick static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd) 1191f48ad614SDennis Dalessandro { 1192dba715f0SDean Luick struct hfi1_asic_data *ad; 1193f48ad614SDennis Dalessandro int other; 1194f48ad614SDennis Dalessandro 1195f48ad614SDennis Dalessandro if (!dd->asic_data) 1196dba715f0SDean Luick return NULL; 1197f48ad614SDennis Dalessandro dd->asic_data->dds[dd->hfi1_id] = NULL; 1198f48ad614SDennis Dalessandro other = dd->hfi1_id ? 0 : 1; 1199dba715f0SDean Luick ad = dd->asic_data; 1200f48ad614SDennis Dalessandro dd->asic_data = NULL; 1201dba715f0SDean Luick /* return NULL if the other dd still has a link */ 1202dba715f0SDean Luick return ad->dds[other] ? NULL : ad; 1203dba715f0SDean Luick } 1204dba715f0SDean Luick 1205dba715f0SDean Luick static void finalize_asic_data(struct hfi1_devdata *dd, 1206dba715f0SDean Luick struct hfi1_asic_data *ad) 1207dba715f0SDean Luick { 1208dba715f0SDean Luick clean_up_i2c(dd, ad); 1209dba715f0SDean Luick kfree(ad); 1210f48ad614SDennis Dalessandro } 1211f48ad614SDennis Dalessandro 1212e9777ad4SSebastian Sanchez /** 1213e9777ad4SSebastian Sanchez * hfi1_clean_devdata - cleans up per-unit data structure 1214e9777ad4SSebastian Sanchez * @dd: pointer to a valid devdata structure 1215e9777ad4SSebastian Sanchez * 1216e9777ad4SSebastian Sanchez * It cleans up all data structures set up by 1217e9777ad4SSebastian Sanchez * by hfi1_alloc_devdata(). 1218e9777ad4SSebastian Sanchez */ 1219e9777ad4SSebastian Sanchez static void hfi1_clean_devdata(struct hfi1_devdata *dd) 1220f48ad614SDennis Dalessandro { 1221dba715f0SDean Luick struct hfi1_asic_data *ad; 1222f48ad614SDennis Dalessandro unsigned long flags; 1223f48ad614SDennis Dalessandro 1224f48ad614SDennis Dalessandro spin_lock_irqsave(&hfi1_devs_lock, flags); 1225e9777ad4SSebastian Sanchez if (!list_empty(&dd->list)) { 1226f48ad614SDennis Dalessandro idr_remove(&hfi1_unit_table, dd->unit); 1227e9777ad4SSebastian Sanchez list_del_init(&dd->list); 1228e9777ad4SSebastian Sanchez } 1229dba715f0SDean Luick ad = release_asic_data(dd); 1230f48ad614SDennis Dalessandro spin_unlock_irqrestore(&hfi1_devs_lock, flags); 1231e9777ad4SSebastian Sanchez 1232dba715f0SDean Luick finalize_asic_data(dd, ad); 1233f48ad614SDennis Dalessandro free_platform_config(dd); 1234f48ad614SDennis Dalessandro rcu_barrier(); /* wait for rcu callbacks to complete */ 1235f48ad614SDennis Dalessandro free_percpu(dd->int_counter); 1236f48ad614SDennis Dalessandro free_percpu(dd->rcv_limit); 1237f48ad614SDennis Dalessandro free_percpu(dd->send_schedule); 12381b311f89SMike Marciniszyn free_percpu(dd->tx_opstats); 1239e9777ad4SSebastian Sanchez dd->int_counter = NULL; 1240e9777ad4SSebastian Sanchez dd->rcv_limit = NULL; 1241e9777ad4SSebastian Sanchez dd->send_schedule = NULL; 1242e9777ad4SSebastian Sanchez dd->tx_opstats = NULL; 1243473291b3SAlex Estrin sdma_clean(dd, dd->num_sdma); 1244f48ad614SDennis Dalessandro rvt_dealloc_device(&dd->verbs_dev.rdi); 1245f48ad614SDennis Dalessandro } 1246f48ad614SDennis Dalessandro 1247e9777ad4SSebastian Sanchez static void __hfi1_free_devdata(struct kobject *kobj) 1248e9777ad4SSebastian Sanchez { 1249e9777ad4SSebastian Sanchez struct hfi1_devdata *dd = 1250e9777ad4SSebastian Sanchez container_of(kobj, struct hfi1_devdata, kobj); 1251e9777ad4SSebastian Sanchez 1252e9777ad4SSebastian Sanchez hfi1_clean_devdata(dd); 1253e9777ad4SSebastian Sanchez } 1254e9777ad4SSebastian Sanchez 1255f48ad614SDennis Dalessandro static struct kobj_type hfi1_devdata_type = { 1256f48ad614SDennis Dalessandro .release = __hfi1_free_devdata, 1257f48ad614SDennis Dalessandro }; 1258f48ad614SDennis Dalessandro 1259f48ad614SDennis Dalessandro void hfi1_free_devdata(struct hfi1_devdata *dd) 1260f48ad614SDennis Dalessandro { 1261f48ad614SDennis Dalessandro kobject_put(&dd->kobj); 1262f48ad614SDennis Dalessandro } 1263f48ad614SDennis Dalessandro 1264f48ad614SDennis Dalessandro /* 1265f48ad614SDennis Dalessandro * Allocate our primary per-unit data structure. Must be done via verbs 1266f48ad614SDennis Dalessandro * allocator, because the verbs cleanup process both does cleanup and 1267f48ad614SDennis Dalessandro * free of the data structure. 1268f48ad614SDennis Dalessandro * "extra" is for chip-specific data. 1269f48ad614SDennis Dalessandro * 1270f48ad614SDennis Dalessandro * Use the idr mechanism to get a unit number for this unit. 1271f48ad614SDennis Dalessandro */ 1272f48ad614SDennis Dalessandro struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra) 1273f48ad614SDennis Dalessandro { 1274f48ad614SDennis Dalessandro unsigned long flags; 1275f48ad614SDennis Dalessandro struct hfi1_devdata *dd; 1276f48ad614SDennis Dalessandro int ret, nports; 1277f48ad614SDennis Dalessandro 1278f48ad614SDennis Dalessandro /* extra is * number of ports */ 1279f48ad614SDennis Dalessandro nports = extra / sizeof(struct hfi1_pportdata); 1280f48ad614SDennis Dalessandro 1281f48ad614SDennis Dalessandro dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra, 1282f48ad614SDennis Dalessandro nports); 1283f48ad614SDennis Dalessandro if (!dd) 1284f48ad614SDennis Dalessandro return ERR_PTR(-ENOMEM); 1285f48ad614SDennis Dalessandro dd->num_pports = nports; 1286f48ad614SDennis Dalessandro dd->pport = (struct hfi1_pportdata *)(dd + 1); 128745d92457SSebastian Sanchez dd->pcidev = pdev; 128845d92457SSebastian Sanchez pci_set_drvdata(pdev, dd); 1289f48ad614SDennis Dalessandro 1290f48ad614SDennis Dalessandro INIT_LIST_HEAD(&dd->list); 1291f48ad614SDennis Dalessandro idr_preload(GFP_KERNEL); 1292f48ad614SDennis Dalessandro spin_lock_irqsave(&hfi1_devs_lock, flags); 1293f48ad614SDennis Dalessandro 1294f48ad614SDennis Dalessandro ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT); 1295f48ad614SDennis Dalessandro if (ret >= 0) { 1296f48ad614SDennis Dalessandro dd->unit = ret; 1297f48ad614SDennis Dalessandro list_add(&dd->list, &hfi1_dev_list); 1298f48ad614SDennis Dalessandro } 1299f48ad614SDennis Dalessandro 1300f48ad614SDennis Dalessandro spin_unlock_irqrestore(&hfi1_devs_lock, flags); 1301f48ad614SDennis Dalessandro idr_preload_end(); 1302f48ad614SDennis Dalessandro 1303f48ad614SDennis Dalessandro if (ret < 0) { 1304f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 1305f48ad614SDennis Dalessandro "Could not allocate unit ID: error %d\n", -ret); 1306f48ad614SDennis Dalessandro goto bail; 1307f48ad614SDennis Dalessandro } 13085084c8ffSMichael J. Ruhl rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s_%d", class_name(), dd->unit); 13095084c8ffSMichael J. Ruhl 1310f48ad614SDennis Dalessandro /* 1311f48ad614SDennis Dalessandro * Initialize all locks for the device. This needs to be as early as 1312f48ad614SDennis Dalessandro * possible so locks are usable. 1313f48ad614SDennis Dalessandro */ 1314f48ad614SDennis Dalessandro spin_lock_init(&dd->sc_lock); 1315f48ad614SDennis Dalessandro spin_lock_init(&dd->sendctrl_lock); 1316f48ad614SDennis Dalessandro spin_lock_init(&dd->rcvctrl_lock); 1317f48ad614SDennis Dalessandro spin_lock_init(&dd->uctxt_lock); 1318f48ad614SDennis Dalessandro spin_lock_init(&dd->hfi1_diag_trans_lock); 1319f48ad614SDennis Dalessandro spin_lock_init(&dd->sc_init_lock); 1320f48ad614SDennis Dalessandro spin_lock_init(&dd->dc8051_memlock); 1321f48ad614SDennis Dalessandro seqlock_init(&dd->sc2vl_lock); 1322f48ad614SDennis Dalessandro spin_lock_init(&dd->sde_map_lock); 1323f48ad614SDennis Dalessandro spin_lock_init(&dd->pio_map_lock); 132422546b74STadeusz Struk mutex_init(&dd->dc8051_lock); 1325f48ad614SDennis Dalessandro init_waitqueue_head(&dd->event_queue); 1326f48ad614SDennis Dalessandro 1327f48ad614SDennis Dalessandro dd->int_counter = alloc_percpu(u64); 1328f48ad614SDennis Dalessandro if (!dd->int_counter) { 1329f48ad614SDennis Dalessandro ret = -ENOMEM; 1330f48ad614SDennis Dalessandro goto bail; 1331f48ad614SDennis Dalessandro } 1332f48ad614SDennis Dalessandro 1333f48ad614SDennis Dalessandro dd->rcv_limit = alloc_percpu(u64); 1334f48ad614SDennis Dalessandro if (!dd->rcv_limit) { 1335f48ad614SDennis Dalessandro ret = -ENOMEM; 1336f48ad614SDennis Dalessandro goto bail; 1337f48ad614SDennis Dalessandro } 1338f48ad614SDennis Dalessandro 1339f48ad614SDennis Dalessandro dd->send_schedule = alloc_percpu(u64); 1340f48ad614SDennis Dalessandro if (!dd->send_schedule) { 1341f48ad614SDennis Dalessandro ret = -ENOMEM; 1342f48ad614SDennis Dalessandro goto bail; 1343f48ad614SDennis Dalessandro } 1344f48ad614SDennis Dalessandro 13451b311f89SMike Marciniszyn dd->tx_opstats = alloc_percpu(struct hfi1_opcode_stats_perctx); 13461b311f89SMike Marciniszyn if (!dd->tx_opstats) { 13471b311f89SMike Marciniszyn ret = -ENOMEM; 13481b311f89SMike Marciniszyn goto bail; 13491b311f89SMike Marciniszyn } 13501b311f89SMike Marciniszyn 1351f48ad614SDennis Dalessandro kobject_init(&dd->kobj, &hfi1_devdata_type); 1352f48ad614SDennis Dalessandro return dd; 1353f48ad614SDennis Dalessandro 1354f48ad614SDennis Dalessandro bail: 1355e9777ad4SSebastian Sanchez hfi1_clean_devdata(dd); 1356f48ad614SDennis Dalessandro return ERR_PTR(ret); 1357f48ad614SDennis Dalessandro } 1358f48ad614SDennis Dalessandro 1359f48ad614SDennis Dalessandro /* 1360f48ad614SDennis Dalessandro * Called from freeze mode handlers, and from PCI error 1361f48ad614SDennis Dalessandro * reporting code. Should be paranoid about state of 1362f48ad614SDennis Dalessandro * system and data structures. 1363f48ad614SDennis Dalessandro */ 1364f48ad614SDennis Dalessandro void hfi1_disable_after_error(struct hfi1_devdata *dd) 1365f48ad614SDennis Dalessandro { 1366f48ad614SDennis Dalessandro if (dd->flags & HFI1_INITTED) { 1367f48ad614SDennis Dalessandro u32 pidx; 1368f48ad614SDennis Dalessandro 1369f48ad614SDennis Dalessandro dd->flags &= ~HFI1_INITTED; 1370f48ad614SDennis Dalessandro if (dd->pport) 1371f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1372f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 1373f48ad614SDennis Dalessandro 1374f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1375f48ad614SDennis Dalessandro if (dd->flags & HFI1_PRESENT) 1376f48ad614SDennis Dalessandro set_link_state(ppd, HLS_DN_DISABLE); 1377f48ad614SDennis Dalessandro 1378f48ad614SDennis Dalessandro if (ppd->statusp) 1379f48ad614SDennis Dalessandro *ppd->statusp &= ~HFI1_STATUS_IB_READY; 1380f48ad614SDennis Dalessandro } 1381f48ad614SDennis Dalessandro } 1382f48ad614SDennis Dalessandro 1383f48ad614SDennis Dalessandro /* 1384f48ad614SDennis Dalessandro * Mark as having had an error for driver, and also 1385f48ad614SDennis Dalessandro * for /sys and status word mapped to user programs. 1386f48ad614SDennis Dalessandro * This marks unit as not usable, until reset. 1387f48ad614SDennis Dalessandro */ 1388f48ad614SDennis Dalessandro if (dd->status) 1389f48ad614SDennis Dalessandro dd->status->dev |= HFI1_STATUS_HWERROR; 1390f48ad614SDennis Dalessandro } 1391f48ad614SDennis Dalessandro 1392f48ad614SDennis Dalessandro static void remove_one(struct pci_dev *); 1393f48ad614SDennis Dalessandro static int init_one(struct pci_dev *, const struct pci_device_id *); 1394f48ad614SDennis Dalessandro 1395f48ad614SDennis Dalessandro #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: " 1396f48ad614SDennis Dalessandro #define PFX DRIVER_NAME ": " 1397f48ad614SDennis Dalessandro 1398d6373019SSebastian Sanchez const struct pci_device_id hfi1_pci_tbl[] = { 1399f48ad614SDennis Dalessandro { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) }, 1400f48ad614SDennis Dalessandro { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) }, 1401f48ad614SDennis Dalessandro { 0, } 1402f48ad614SDennis Dalessandro }; 1403f48ad614SDennis Dalessandro 1404f48ad614SDennis Dalessandro MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl); 1405f48ad614SDennis Dalessandro 1406f48ad614SDennis Dalessandro static struct pci_driver hfi1_pci_driver = { 1407f48ad614SDennis Dalessandro .name = DRIVER_NAME, 1408f48ad614SDennis Dalessandro .probe = init_one, 1409f48ad614SDennis Dalessandro .remove = remove_one, 1410f48ad614SDennis Dalessandro .id_table = hfi1_pci_tbl, 1411f48ad614SDennis Dalessandro .err_handler = &hfi1_pci_err_handler, 1412f48ad614SDennis Dalessandro }; 1413f48ad614SDennis Dalessandro 1414f48ad614SDennis Dalessandro static void __init compute_krcvqs(void) 1415f48ad614SDennis Dalessandro { 1416f48ad614SDennis Dalessandro int i; 1417f48ad614SDennis Dalessandro 1418f48ad614SDennis Dalessandro for (i = 0; i < krcvqsset; i++) 1419f48ad614SDennis Dalessandro n_krcvqs += krcvqs[i]; 1420f48ad614SDennis Dalessandro } 1421f48ad614SDennis Dalessandro 1422f48ad614SDennis Dalessandro /* 1423f48ad614SDennis Dalessandro * Do all the generic driver unit- and chip-independent memory 1424f48ad614SDennis Dalessandro * allocation and initialization. 1425f48ad614SDennis Dalessandro */ 1426f48ad614SDennis Dalessandro static int __init hfi1_mod_init(void) 1427f48ad614SDennis Dalessandro { 1428f48ad614SDennis Dalessandro int ret; 1429f48ad614SDennis Dalessandro 1430f48ad614SDennis Dalessandro ret = dev_init(); 1431f48ad614SDennis Dalessandro if (ret) 1432f48ad614SDennis Dalessandro goto bail; 1433f48ad614SDennis Dalessandro 1434d6373019SSebastian Sanchez ret = node_affinity_init(); 1435d6373019SSebastian Sanchez if (ret) 1436d6373019SSebastian Sanchez goto bail; 14374197344bSDennis Dalessandro 1438f48ad614SDennis Dalessandro /* validate max MTU before any devices start */ 1439f48ad614SDennis Dalessandro if (!valid_opa_max_mtu(hfi1_max_mtu)) { 1440f48ad614SDennis Dalessandro pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n", 1441f48ad614SDennis Dalessandro hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU); 1442f48ad614SDennis Dalessandro hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU; 1443f48ad614SDennis Dalessandro } 1444f48ad614SDennis Dalessandro /* valid CUs run from 1-128 in powers of 2 */ 1445f48ad614SDennis Dalessandro if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu)) 1446f48ad614SDennis Dalessandro hfi1_cu = 1; 1447f48ad614SDennis Dalessandro /* valid credit return threshold is 0-100, variable is unsigned */ 1448f48ad614SDennis Dalessandro if (user_credit_return_threshold > 100) 1449f48ad614SDennis Dalessandro user_credit_return_threshold = 100; 1450f48ad614SDennis Dalessandro 1451f48ad614SDennis Dalessandro compute_krcvqs(); 1452f48ad614SDennis Dalessandro /* 1453f48ad614SDennis Dalessandro * sanitize receive interrupt count, time must wait until after 1454f48ad614SDennis Dalessandro * the hardware type is known 1455f48ad614SDennis Dalessandro */ 1456f48ad614SDennis Dalessandro if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK) 1457f48ad614SDennis Dalessandro rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK; 1458f48ad614SDennis Dalessandro /* reject invalid combinations */ 1459f48ad614SDennis Dalessandro if (rcv_intr_count == 0 && rcv_intr_timeout == 0) { 1460f48ad614SDennis Dalessandro pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n"); 1461f48ad614SDennis Dalessandro rcv_intr_count = 1; 1462f48ad614SDennis Dalessandro } 1463f48ad614SDennis Dalessandro if (rcv_intr_count > 1 && rcv_intr_timeout == 0) { 1464f48ad614SDennis Dalessandro /* 1465f48ad614SDennis Dalessandro * Avoid indefinite packet delivery by requiring a timeout 1466f48ad614SDennis Dalessandro * if count is > 1. 1467f48ad614SDennis Dalessandro */ 1468f48ad614SDennis Dalessandro pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n"); 1469f48ad614SDennis Dalessandro rcv_intr_timeout = 1; 1470f48ad614SDennis Dalessandro } 1471f48ad614SDennis Dalessandro if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) { 1472f48ad614SDennis Dalessandro /* 1473f48ad614SDennis Dalessandro * The dynamic algorithm expects a non-zero timeout 1474f48ad614SDennis Dalessandro * and a count > 1. 1475f48ad614SDennis Dalessandro */ 1476f48ad614SDennis Dalessandro pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n"); 1477f48ad614SDennis Dalessandro rcv_intr_dynamic = 0; 1478f48ad614SDennis Dalessandro } 1479f48ad614SDennis Dalessandro 1480f48ad614SDennis Dalessandro /* sanitize link CRC options */ 1481f48ad614SDennis Dalessandro link_crc_mask &= SUPPORTED_CRCS; 1482f48ad614SDennis Dalessandro 1483f48ad614SDennis Dalessandro /* 1484f48ad614SDennis Dalessandro * These must be called before the driver is registered with 1485f48ad614SDennis Dalessandro * the PCI subsystem. 1486f48ad614SDennis Dalessandro */ 1487f48ad614SDennis Dalessandro idr_init(&hfi1_unit_table); 1488f48ad614SDennis Dalessandro 1489f48ad614SDennis Dalessandro hfi1_dbg_init(); 1490f48ad614SDennis Dalessandro ret = hfi1_wss_init(); 1491f48ad614SDennis Dalessandro if (ret < 0) 1492f48ad614SDennis Dalessandro goto bail_wss; 1493f48ad614SDennis Dalessandro ret = pci_register_driver(&hfi1_pci_driver); 1494f48ad614SDennis Dalessandro if (ret < 0) { 1495f48ad614SDennis Dalessandro pr_err("Unable to register driver: error %d\n", -ret); 1496f48ad614SDennis Dalessandro goto bail_dev; 1497f48ad614SDennis Dalessandro } 1498f48ad614SDennis Dalessandro goto bail; /* all OK */ 1499f48ad614SDennis Dalessandro 1500f48ad614SDennis Dalessandro bail_dev: 1501f48ad614SDennis Dalessandro hfi1_wss_exit(); 1502f48ad614SDennis Dalessandro bail_wss: 1503f48ad614SDennis Dalessandro hfi1_dbg_exit(); 1504f48ad614SDennis Dalessandro idr_destroy(&hfi1_unit_table); 1505f48ad614SDennis Dalessandro dev_cleanup(); 1506f48ad614SDennis Dalessandro bail: 1507f48ad614SDennis Dalessandro return ret; 1508f48ad614SDennis Dalessandro } 1509f48ad614SDennis Dalessandro 1510f48ad614SDennis Dalessandro module_init(hfi1_mod_init); 1511f48ad614SDennis Dalessandro 1512f48ad614SDennis Dalessandro /* 1513f48ad614SDennis Dalessandro * Do the non-unit driver cleanup, memory free, etc. at unload. 1514f48ad614SDennis Dalessandro */ 1515f48ad614SDennis Dalessandro static void __exit hfi1_mod_cleanup(void) 1516f48ad614SDennis Dalessandro { 1517f48ad614SDennis Dalessandro pci_unregister_driver(&hfi1_pci_driver); 15184197344bSDennis Dalessandro node_affinity_destroy(); 1519f48ad614SDennis Dalessandro hfi1_wss_exit(); 1520f48ad614SDennis Dalessandro hfi1_dbg_exit(); 1521f48ad614SDennis Dalessandro 1522f48ad614SDennis Dalessandro idr_destroy(&hfi1_unit_table); 1523f48ad614SDennis Dalessandro dispose_firmware(); /* asymmetric with obtain_firmware() */ 1524f48ad614SDennis Dalessandro dev_cleanup(); 1525f48ad614SDennis Dalessandro } 1526f48ad614SDennis Dalessandro 1527f48ad614SDennis Dalessandro module_exit(hfi1_mod_cleanup); 1528f48ad614SDennis Dalessandro 1529f48ad614SDennis Dalessandro /* this can only be called after a successful initialization */ 1530f48ad614SDennis Dalessandro static void cleanup_device_data(struct hfi1_devdata *dd) 1531f48ad614SDennis Dalessandro { 1532f48ad614SDennis Dalessandro int ctxt; 1533f48ad614SDennis Dalessandro int pidx; 1534f48ad614SDennis Dalessandro 1535f48ad614SDennis Dalessandro /* users can't do anything more with chip */ 1536f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1537f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = &dd->pport[pidx]; 1538f48ad614SDennis Dalessandro struct cc_state *cc_state; 1539f48ad614SDennis Dalessandro int i; 1540f48ad614SDennis Dalessandro 1541f48ad614SDennis Dalessandro if (ppd->statusp) 1542f48ad614SDennis Dalessandro *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT; 1543f48ad614SDennis Dalessandro 1544f48ad614SDennis Dalessandro for (i = 0; i < OPA_MAX_SLS; i++) 1545f48ad614SDennis Dalessandro hrtimer_cancel(&ppd->cca_timer[i].hrtimer); 1546f48ad614SDennis Dalessandro 1547f48ad614SDennis Dalessandro spin_lock(&ppd->cc_state_lock); 15488adf71faSJianxin Xiong cc_state = get_cc_state_protected(ppd); 1549f48ad614SDennis Dalessandro RCU_INIT_POINTER(ppd->cc_state, NULL); 1550f48ad614SDennis Dalessandro spin_unlock(&ppd->cc_state_lock); 1551f48ad614SDennis Dalessandro 1552f48ad614SDennis Dalessandro if (cc_state) 1553476d95bdSWei Yongjun kfree_rcu(cc_state, rcu); 1554f48ad614SDennis Dalessandro } 1555f48ad614SDennis Dalessandro 1556f48ad614SDennis Dalessandro free_credit_return(dd); 1557f48ad614SDennis Dalessandro 1558f48ad614SDennis Dalessandro if (dd->rcvhdrtail_dummy_kvaddr) { 1559f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, sizeof(u64), 1560f48ad614SDennis Dalessandro (void *)dd->rcvhdrtail_dummy_kvaddr, 156160368186STymoteusz Kielan dd->rcvhdrtail_dummy_dma); 1562f48ad614SDennis Dalessandro dd->rcvhdrtail_dummy_kvaddr = NULL; 1563f48ad614SDennis Dalessandro } 1564f48ad614SDennis Dalessandro 1565d295dbebSMichael J. Ruhl /* 1566d295dbebSMichael J. Ruhl * Free any resources still in use (usually just kernel contexts) 1567d295dbebSMichael J. Ruhl * at unload; we do for ctxtcnt, because that's what we allocate. 1568d295dbebSMichael J. Ruhl */ 1569d295dbebSMichael J. Ruhl for (ctxt = 0; dd->rcd && ctxt < dd->num_rcv_contexts; ctxt++) { 1570d295dbebSMichael J. Ruhl struct hfi1_ctxtdata *rcd = dd->rcd[ctxt]; 1571f48ad614SDennis Dalessandro 1572f48ad614SDennis Dalessandro if (rcd) { 1573f48ad614SDennis Dalessandro hfi1_clear_tids(rcd); 1574d295dbebSMichael J. Ruhl hfi1_free_ctxt(rcd); 1575f48ad614SDennis Dalessandro } 1576f48ad614SDennis Dalessandro } 1577d295dbebSMichael J. Ruhl 1578d295dbebSMichael J. Ruhl kfree(dd->rcd); 1579d295dbebSMichael J. Ruhl dd->rcd = NULL; 1580d295dbebSMichael J. Ruhl 1581f48ad614SDennis Dalessandro free_pio_map(dd); 1582f48ad614SDennis Dalessandro /* must follow rcv context free - need to remove rcv's hooks */ 1583f48ad614SDennis Dalessandro for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++) 1584f48ad614SDennis Dalessandro sc_free(dd->send_contexts[ctxt].sc); 1585f48ad614SDennis Dalessandro dd->num_send_contexts = 0; 1586f48ad614SDennis Dalessandro kfree(dd->send_contexts); 1587f48ad614SDennis Dalessandro dd->send_contexts = NULL; 1588f48ad614SDennis Dalessandro kfree(dd->hw_to_sw); 1589f48ad614SDennis Dalessandro dd->hw_to_sw = NULL; 1590f48ad614SDennis Dalessandro kfree(dd->boardname); 1591f48ad614SDennis Dalessandro vfree(dd->events); 1592f48ad614SDennis Dalessandro vfree(dd->status); 1593f48ad614SDennis Dalessandro } 1594f48ad614SDennis Dalessandro 1595f48ad614SDennis Dalessandro /* 1596f48ad614SDennis Dalessandro * Clean up on unit shutdown, or error during unit load after 1597f48ad614SDennis Dalessandro * successful initialization. 1598f48ad614SDennis Dalessandro */ 1599f48ad614SDennis Dalessandro static void postinit_cleanup(struct hfi1_devdata *dd) 1600f48ad614SDennis Dalessandro { 1601f48ad614SDennis Dalessandro hfi1_start_cleanup(dd); 1602f48ad614SDennis Dalessandro 1603f48ad614SDennis Dalessandro hfi1_pcie_ddcleanup(dd); 1604f48ad614SDennis Dalessandro hfi1_pcie_cleanup(dd->pcidev); 1605f48ad614SDennis Dalessandro 1606f48ad614SDennis Dalessandro cleanup_device_data(dd); 1607f48ad614SDennis Dalessandro 1608f48ad614SDennis Dalessandro hfi1_free_devdata(dd); 1609f48ad614SDennis Dalessandro } 1610f48ad614SDennis Dalessandro 161111501ab9SKrzysztof Blaszkowski static int init_validate_rcvhdrcnt(struct device *dev, uint thecnt) 161211501ab9SKrzysztof Blaszkowski { 161311501ab9SKrzysztof Blaszkowski if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { 161411501ab9SKrzysztof Blaszkowski hfi1_early_err(dev, "Receive header queue count too small\n"); 161511501ab9SKrzysztof Blaszkowski return -EINVAL; 161611501ab9SKrzysztof Blaszkowski } 161711501ab9SKrzysztof Blaszkowski 161811501ab9SKrzysztof Blaszkowski if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) { 161911501ab9SKrzysztof Blaszkowski hfi1_early_err(dev, 162011501ab9SKrzysztof Blaszkowski "Receive header queue count cannot be greater than %u\n", 162111501ab9SKrzysztof Blaszkowski HFI1_MAX_HDRQ_EGRBUF_CNT); 162211501ab9SKrzysztof Blaszkowski return -EINVAL; 162311501ab9SKrzysztof Blaszkowski } 162411501ab9SKrzysztof Blaszkowski 162511501ab9SKrzysztof Blaszkowski if (thecnt % HDRQ_INCREMENT) { 162611501ab9SKrzysztof Blaszkowski hfi1_early_err(dev, "Receive header queue count %d must be divisible by %lu\n", 162711501ab9SKrzysztof Blaszkowski thecnt, HDRQ_INCREMENT); 162811501ab9SKrzysztof Blaszkowski return -EINVAL; 162911501ab9SKrzysztof Blaszkowski } 163011501ab9SKrzysztof Blaszkowski 163111501ab9SKrzysztof Blaszkowski return 0; 163211501ab9SKrzysztof Blaszkowski } 163311501ab9SKrzysztof Blaszkowski 1634f48ad614SDennis Dalessandro static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1635f48ad614SDennis Dalessandro { 1636f48ad614SDennis Dalessandro int ret = 0, j, pidx, initfail; 163783fb4af6SKrzysztof Blaszkowski struct hfi1_devdata *dd; 1638f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 1639f48ad614SDennis Dalessandro 1640f48ad614SDennis Dalessandro /* First, lock the non-writable module parameters */ 1641f48ad614SDennis Dalessandro HFI1_CAP_LOCK(); 1642f48ad614SDennis Dalessandro 16435d6f08afSTadeusz Struk /* Validate dev ids */ 16445d6f08afSTadeusz Struk if (!(ent->device == PCI_DEVICE_ID_INTEL0 || 16455d6f08afSTadeusz Struk ent->device == PCI_DEVICE_ID_INTEL1)) { 16465d6f08afSTadeusz Struk hfi1_early_err(&pdev->dev, 16475d6f08afSTadeusz Struk "Failing on unknown Intel deviceid 0x%x\n", 16485d6f08afSTadeusz Struk ent->device); 16495d6f08afSTadeusz Struk ret = -ENODEV; 16505d6f08afSTadeusz Struk goto bail; 16515d6f08afSTadeusz Struk } 16525d6f08afSTadeusz Struk 1653f48ad614SDennis Dalessandro /* Validate some global module parameters */ 165411501ab9SKrzysztof Blaszkowski ret = init_validate_rcvhdrcnt(&pdev->dev, rcvhdrcnt); 165511501ab9SKrzysztof Blaszkowski if (ret) 1656f48ad614SDennis Dalessandro goto bail; 165711501ab9SKrzysztof Blaszkowski 1658f48ad614SDennis Dalessandro /* use the encoding function as a sanitization check */ 1659f48ad614SDennis Dalessandro if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) { 1660f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n", 1661f48ad614SDennis Dalessandro hfi1_hdrq_entsize); 1662f48ad614SDennis Dalessandro ret = -EINVAL; 1663f48ad614SDennis Dalessandro goto bail; 1664f48ad614SDennis Dalessandro } 1665f48ad614SDennis Dalessandro 1666f48ad614SDennis Dalessandro /* The receive eager buffer size must be set before the receive 1667f48ad614SDennis Dalessandro * contexts are created. 1668f48ad614SDennis Dalessandro * 1669f48ad614SDennis Dalessandro * Set the eager buffer size. Validate that it falls in a range 1670f48ad614SDennis Dalessandro * allowed by the hardware - all powers of 2 between the min and 1671f48ad614SDennis Dalessandro * max. The maximum valid MTU is within the eager buffer range 1672f48ad614SDennis Dalessandro * so we do not need to cap the max_mtu by an eager buffer size 1673f48ad614SDennis Dalessandro * setting. 1674f48ad614SDennis Dalessandro */ 1675f48ad614SDennis Dalessandro if (eager_buffer_size) { 1676f48ad614SDennis Dalessandro if (!is_power_of_2(eager_buffer_size)) 1677f48ad614SDennis Dalessandro eager_buffer_size = 1678f48ad614SDennis Dalessandro roundup_pow_of_two(eager_buffer_size); 1679f48ad614SDennis Dalessandro eager_buffer_size = 1680f48ad614SDennis Dalessandro clamp_val(eager_buffer_size, 1681f48ad614SDennis Dalessandro MIN_EAGER_BUFFER * 8, 1682f48ad614SDennis Dalessandro MAX_EAGER_BUFFER_TOTAL); 1683f48ad614SDennis Dalessandro hfi1_early_info(&pdev->dev, "Eager buffer size %u\n", 1684f48ad614SDennis Dalessandro eager_buffer_size); 1685f48ad614SDennis Dalessandro } else { 1686f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n"); 1687f48ad614SDennis Dalessandro ret = -EINVAL; 1688f48ad614SDennis Dalessandro goto bail; 1689f48ad614SDennis Dalessandro } 1690f48ad614SDennis Dalessandro 1691f48ad614SDennis Dalessandro /* restrict value of hfi1_rcvarr_split */ 1692f48ad614SDennis Dalessandro hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100); 1693f48ad614SDennis Dalessandro 1694f48ad614SDennis Dalessandro ret = hfi1_pcie_init(pdev, ent); 1695f48ad614SDennis Dalessandro if (ret) 1696f48ad614SDennis Dalessandro goto bail; 1697f48ad614SDennis Dalessandro 169883fb4af6SKrzysztof Blaszkowski /* 169983fb4af6SKrzysztof Blaszkowski * Do device-specific initialization, function table setup, dd 170083fb4af6SKrzysztof Blaszkowski * allocation, etc. 170183fb4af6SKrzysztof Blaszkowski */ 170283fb4af6SKrzysztof Blaszkowski dd = hfi1_init_dd(pdev, ent); 170383fb4af6SKrzysztof Blaszkowski 170483fb4af6SKrzysztof Blaszkowski if (IS_ERR(dd)) { 1705f48ad614SDennis Dalessandro ret = PTR_ERR(dd); 1706f48ad614SDennis Dalessandro goto clean_bail; /* error already printed */ 170783fb4af6SKrzysztof Blaszkowski } 1708f48ad614SDennis Dalessandro 1709f48ad614SDennis Dalessandro ret = create_workqueues(dd); 1710f48ad614SDennis Dalessandro if (ret) 1711f48ad614SDennis Dalessandro goto clean_bail; 1712f48ad614SDennis Dalessandro 1713f48ad614SDennis Dalessandro /* do the generic initialization */ 1714f48ad614SDennis Dalessandro initfail = hfi1_init(dd, 0); 1715f48ad614SDennis Dalessandro 1716d4829ea6SVishwanathapura, Niranjana /* setup vnic */ 1717d4829ea6SVishwanathapura, Niranjana hfi1_vnic_setup(dd); 1718d4829ea6SVishwanathapura, Niranjana 1719f48ad614SDennis Dalessandro ret = hfi1_register_ib_device(dd); 1720f48ad614SDennis Dalessandro 1721f48ad614SDennis Dalessandro /* 1722f48ad614SDennis Dalessandro * Now ready for use. this should be cleared whenever we 1723f48ad614SDennis Dalessandro * detect a reset, or initiate one. If earlier failure, 1724f48ad614SDennis Dalessandro * we still create devices, so diags, etc. can be used 1725f48ad614SDennis Dalessandro * to determine cause of problem. 1726f48ad614SDennis Dalessandro */ 1727f48ad614SDennis Dalessandro if (!initfail && !ret) { 1728f48ad614SDennis Dalessandro dd->flags |= HFI1_INITTED; 1729f48ad614SDennis Dalessandro /* create debufs files after init and ib register */ 1730f48ad614SDennis Dalessandro hfi1_dbg_ibdev_init(&dd->verbs_dev); 1731f48ad614SDennis Dalessandro } 1732f48ad614SDennis Dalessandro 1733f48ad614SDennis Dalessandro j = hfi1_device_create(dd); 1734f48ad614SDennis Dalessandro if (j) 1735f48ad614SDennis Dalessandro dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j); 1736f48ad614SDennis Dalessandro 1737f48ad614SDennis Dalessandro if (initfail || ret) { 173882a97926SMichael J. Ruhl hfi1_clean_up_interrupts(dd); 1739f48ad614SDennis Dalessandro stop_timers(dd); 1740f48ad614SDennis Dalessandro flush_workqueue(ib_wq); 1741f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1742f48ad614SDennis Dalessandro hfi1_quiet_serdes(dd->pport + pidx); 1743f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1744f48ad614SDennis Dalessandro if (ppd->hfi1_wq) { 1745f48ad614SDennis Dalessandro destroy_workqueue(ppd->hfi1_wq); 1746f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 1747f48ad614SDennis Dalessandro } 174871d47008SSebastian Sanchez if (ppd->link_wq) { 174971d47008SSebastian Sanchez destroy_workqueue(ppd->link_wq); 175071d47008SSebastian Sanchez ppd->link_wq = NULL; 175171d47008SSebastian Sanchez } 1752f48ad614SDennis Dalessandro } 1753f48ad614SDennis Dalessandro if (!j) 1754f48ad614SDennis Dalessandro hfi1_device_remove(dd); 1755f48ad614SDennis Dalessandro if (!ret) 1756f48ad614SDennis Dalessandro hfi1_unregister_ib_device(dd); 17572280740fSVishwanathapura, Niranjana hfi1_vnic_cleanup(dd); 1758f48ad614SDennis Dalessandro postinit_cleanup(dd); 1759f48ad614SDennis Dalessandro if (initfail) 1760f48ad614SDennis Dalessandro ret = initfail; 1761f48ad614SDennis Dalessandro goto bail; /* everything already cleaned */ 1762f48ad614SDennis Dalessandro } 1763f48ad614SDennis Dalessandro 1764f48ad614SDennis Dalessandro sdma_start(dd); 1765f48ad614SDennis Dalessandro 1766f48ad614SDennis Dalessandro return 0; 1767f48ad614SDennis Dalessandro 1768f48ad614SDennis Dalessandro clean_bail: 1769f48ad614SDennis Dalessandro hfi1_pcie_cleanup(pdev); 1770f48ad614SDennis Dalessandro bail: 1771f48ad614SDennis Dalessandro return ret; 1772f48ad614SDennis Dalessandro } 1773f48ad614SDennis Dalessandro 1774acd7c8feSTadeusz Struk static void wait_for_clients(struct hfi1_devdata *dd) 1775acd7c8feSTadeusz Struk { 1776acd7c8feSTadeusz Struk /* 1777acd7c8feSTadeusz Struk * Remove the device init value and complete the device if there is 1778acd7c8feSTadeusz Struk * no clients or wait for active clients to finish. 1779acd7c8feSTadeusz Struk */ 1780acd7c8feSTadeusz Struk if (atomic_dec_and_test(&dd->user_refcount)) 1781acd7c8feSTadeusz Struk complete(&dd->user_comp); 1782acd7c8feSTadeusz Struk 1783acd7c8feSTadeusz Struk wait_for_completion(&dd->user_comp); 1784acd7c8feSTadeusz Struk } 1785acd7c8feSTadeusz Struk 1786f48ad614SDennis Dalessandro static void remove_one(struct pci_dev *pdev) 1787f48ad614SDennis Dalessandro { 1788f48ad614SDennis Dalessandro struct hfi1_devdata *dd = pci_get_drvdata(pdev); 1789f48ad614SDennis Dalessandro 1790f48ad614SDennis Dalessandro /* close debugfs files before ib unregister */ 1791f48ad614SDennis Dalessandro hfi1_dbg_ibdev_exit(&dd->verbs_dev); 1792acd7c8feSTadeusz Struk 1793acd7c8feSTadeusz Struk /* remove the /dev hfi1 interface */ 1794acd7c8feSTadeusz Struk hfi1_device_remove(dd); 1795acd7c8feSTadeusz Struk 1796acd7c8feSTadeusz Struk /* wait for existing user space clients to finish */ 1797acd7c8feSTadeusz Struk wait_for_clients(dd); 1798acd7c8feSTadeusz Struk 1799f48ad614SDennis Dalessandro /* unregister from IB core */ 1800f48ad614SDennis Dalessandro hfi1_unregister_ib_device(dd); 1801f48ad614SDennis Dalessandro 1802d4829ea6SVishwanathapura, Niranjana /* cleanup vnic */ 1803d4829ea6SVishwanathapura, Niranjana hfi1_vnic_cleanup(dd); 1804d4829ea6SVishwanathapura, Niranjana 1805f48ad614SDennis Dalessandro /* 1806f48ad614SDennis Dalessandro * Disable the IB link, disable interrupts on the device, 1807f48ad614SDennis Dalessandro * clear dma engines, etc. 1808f48ad614SDennis Dalessandro */ 1809f48ad614SDennis Dalessandro shutdown_device(dd); 1810f48ad614SDennis Dalessandro 1811f48ad614SDennis Dalessandro stop_timers(dd); 1812f48ad614SDennis Dalessandro 1813f48ad614SDennis Dalessandro /* wait until all of our (qsfp) queue_work() calls complete */ 1814f48ad614SDennis Dalessandro flush_workqueue(ib_wq); 1815f48ad614SDennis Dalessandro 1816f48ad614SDennis Dalessandro postinit_cleanup(dd); 1817f48ad614SDennis Dalessandro } 1818f48ad614SDennis Dalessandro 1819f48ad614SDennis Dalessandro /** 1820f48ad614SDennis Dalessandro * hfi1_create_rcvhdrq - create a receive header queue 1821f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 1822f48ad614SDennis Dalessandro * @rcd: the context data 1823f48ad614SDennis Dalessandro * 1824f48ad614SDennis Dalessandro * This must be contiguous memory (from an i/o perspective), and must be 1825f48ad614SDennis Dalessandro * DMA'able (which means for some systems, it will go through an IOMMU, 1826f48ad614SDennis Dalessandro * or be forced into a low address range). 1827f48ad614SDennis Dalessandro */ 1828f48ad614SDennis Dalessandro int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 1829f48ad614SDennis Dalessandro { 1830f48ad614SDennis Dalessandro unsigned amt; 1831f48ad614SDennis Dalessandro u64 reg; 1832f48ad614SDennis Dalessandro 1833f48ad614SDennis Dalessandro if (!rcd->rcvhdrq) { 183460368186STymoteusz Kielan dma_addr_t dma_hdrqtail; 1835f48ad614SDennis Dalessandro gfp_t gfp_flags; 1836f48ad614SDennis Dalessandro 1837f48ad614SDennis Dalessandro /* 1838f48ad614SDennis Dalessandro * rcvhdrqentsize is in DWs, so we have to convert to bytes 1839f48ad614SDennis Dalessandro * (* sizeof(u32)). 1840f48ad614SDennis Dalessandro */ 1841f48ad614SDennis Dalessandro amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize * 1842f48ad614SDennis Dalessandro sizeof(u32)); 1843f48ad614SDennis Dalessandro 1844cc9a97eaSNiranjana Vishwanathapura if (rcd->ctxt < dd->first_dyn_alloc_ctxt || rcd->is_vnic) 18452280740fSVishwanathapura, Niranjana gfp_flags = GFP_KERNEL; 18462280740fSVishwanathapura, Niranjana else 18472280740fSVishwanathapura, Niranjana gfp_flags = GFP_USER; 1848f48ad614SDennis Dalessandro rcd->rcvhdrq = dma_zalloc_coherent( 184960368186STymoteusz Kielan &dd->pcidev->dev, amt, &rcd->rcvhdrq_dma, 1850f48ad614SDennis Dalessandro gfp_flags | __GFP_COMP); 1851f48ad614SDennis Dalessandro 1852f48ad614SDennis Dalessandro if (!rcd->rcvhdrq) { 1853f48ad614SDennis Dalessandro dd_dev_err(dd, 1854f48ad614SDennis Dalessandro "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n", 1855f48ad614SDennis Dalessandro amt, rcd->ctxt); 1856f48ad614SDennis Dalessandro goto bail; 1857f48ad614SDennis Dalessandro } 1858f48ad614SDennis Dalessandro 1859f48ad614SDennis Dalessandro if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) { 1860f48ad614SDennis Dalessandro rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent( 186160368186STymoteusz Kielan &dd->pcidev->dev, PAGE_SIZE, &dma_hdrqtail, 1862f48ad614SDennis Dalessandro gfp_flags); 1863f48ad614SDennis Dalessandro if (!rcd->rcvhdrtail_kvaddr) 1864f48ad614SDennis Dalessandro goto bail_free; 186560368186STymoteusz Kielan rcd->rcvhdrqtailaddr_dma = dma_hdrqtail; 1866f48ad614SDennis Dalessandro } 1867f48ad614SDennis Dalessandro 1868f48ad614SDennis Dalessandro rcd->rcvhdrq_size = amt; 1869f48ad614SDennis Dalessandro } 1870f48ad614SDennis Dalessandro /* 1871f48ad614SDennis Dalessandro * These values are per-context: 1872f48ad614SDennis Dalessandro * RcvHdrCnt 1873f48ad614SDennis Dalessandro * RcvHdrEntSize 1874f48ad614SDennis Dalessandro * RcvHdrSize 1875f48ad614SDennis Dalessandro */ 1876f48ad614SDennis Dalessandro reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT) 1877f48ad614SDennis Dalessandro & RCV_HDR_CNT_CNT_MASK) 1878f48ad614SDennis Dalessandro << RCV_HDR_CNT_CNT_SHIFT; 1879f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg); 1880f48ad614SDennis Dalessandro reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize) 1881f48ad614SDennis Dalessandro & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) 1882f48ad614SDennis Dalessandro << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT; 1883f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg); 1884f48ad614SDennis Dalessandro reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK) 1885f48ad614SDennis Dalessandro << RCV_HDR_SIZE_HDR_SIZE_SHIFT; 1886f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg); 1887f48ad614SDennis Dalessandro 1888f48ad614SDennis Dalessandro /* 1889f48ad614SDennis Dalessandro * Program dummy tail address for every receive context 1890f48ad614SDennis Dalessandro * before enabling any receive context 1891f48ad614SDennis Dalessandro */ 1892f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR, 189360368186STymoteusz Kielan dd->rcvhdrtail_dummy_dma); 1894f48ad614SDennis Dalessandro 1895f48ad614SDennis Dalessandro return 0; 1896f48ad614SDennis Dalessandro 1897f48ad614SDennis Dalessandro bail_free: 1898f48ad614SDennis Dalessandro dd_dev_err(dd, 1899f48ad614SDennis Dalessandro "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n", 1900f48ad614SDennis Dalessandro rcd->ctxt); 1901f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq, 190260368186STymoteusz Kielan rcd->rcvhdrq_dma); 1903f48ad614SDennis Dalessandro rcd->rcvhdrq = NULL; 1904f48ad614SDennis Dalessandro bail: 1905f48ad614SDennis Dalessandro return -ENOMEM; 1906f48ad614SDennis Dalessandro } 1907f48ad614SDennis Dalessandro 1908f48ad614SDennis Dalessandro /** 1909f48ad614SDennis Dalessandro * allocate eager buffers, both kernel and user contexts. 1910f48ad614SDennis Dalessandro * @rcd: the context we are setting up. 1911f48ad614SDennis Dalessandro * 1912f48ad614SDennis Dalessandro * Allocate the eager TID buffers and program them into hip. 1913f48ad614SDennis Dalessandro * They are no longer completely contiguous, we do multiple allocation 1914f48ad614SDennis Dalessandro * calls. Otherwise we get the OOM code involved, by asking for too 1915f48ad614SDennis Dalessandro * much per call, with disastrous results on some kernels. 1916f48ad614SDennis Dalessandro */ 1917f48ad614SDennis Dalessandro int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd) 1918f48ad614SDennis Dalessandro { 1919f48ad614SDennis Dalessandro struct hfi1_devdata *dd = rcd->dd; 1920f48ad614SDennis Dalessandro u32 max_entries, egrtop, alloced_bytes = 0, idx = 0; 1921f48ad614SDennis Dalessandro gfp_t gfp_flags; 1922f48ad614SDennis Dalessandro u16 order; 1923f48ad614SDennis Dalessandro int ret = 0; 1924f48ad614SDennis Dalessandro u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu); 1925f48ad614SDennis Dalessandro 1926f48ad614SDennis Dalessandro /* 1927f48ad614SDennis Dalessandro * GFP_USER, but without GFP_FS, so buffer cache can be 1928f48ad614SDennis Dalessandro * coalesced (we hope); otherwise, even at order 4, 1929f48ad614SDennis Dalessandro * heavy filesystem activity makes these fail, and we can 1930f48ad614SDennis Dalessandro * use compound pages. 1931f48ad614SDennis Dalessandro */ 1932f48ad614SDennis Dalessandro gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP; 1933f48ad614SDennis Dalessandro 1934f48ad614SDennis Dalessandro /* 1935f48ad614SDennis Dalessandro * The minimum size of the eager buffers is a groups of MTU-sized 1936f48ad614SDennis Dalessandro * buffers. 1937f48ad614SDennis Dalessandro * The global eager_buffer_size parameter is checked against the 1938f48ad614SDennis Dalessandro * theoretical lower limit of the value. Here, we check against the 1939f48ad614SDennis Dalessandro * MTU. 1940f48ad614SDennis Dalessandro */ 1941f48ad614SDennis Dalessandro if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size)) 1942f48ad614SDennis Dalessandro rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size; 1943f48ad614SDennis Dalessandro /* 1944f48ad614SDennis Dalessandro * If using one-pkt-per-egr-buffer, lower the eager buffer 1945f48ad614SDennis Dalessandro * size to the max MTU (page-aligned). 1946f48ad614SDennis Dalessandro */ 1947f48ad614SDennis Dalessandro if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) 1948f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = round_mtu; 1949f48ad614SDennis Dalessandro 1950f48ad614SDennis Dalessandro /* 1951f48ad614SDennis Dalessandro * Eager buffers sizes of 1MB or less require smaller TID sizes 1952f48ad614SDennis Dalessandro * to satisfy the "multiple of 8 RcvArray entries" requirement. 1953f48ad614SDennis Dalessandro */ 1954f48ad614SDennis Dalessandro if (rcd->egrbufs.size <= (1 << 20)) 1955f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu, 1956f48ad614SDennis Dalessandro rounddown_pow_of_two(rcd->egrbufs.size / 8)); 1957f48ad614SDennis Dalessandro 1958f48ad614SDennis Dalessandro while (alloced_bytes < rcd->egrbufs.size && 1959f48ad614SDennis Dalessandro rcd->egrbufs.alloced < rcd->egrbufs.count) { 1960f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr = 1961f48ad614SDennis Dalessandro dma_zalloc_coherent(&dd->pcidev->dev, 1962f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size, 196360368186STymoteusz Kielan &rcd->egrbufs.buffers[idx].dma, 1964f48ad614SDennis Dalessandro gfp_flags); 1965f48ad614SDennis Dalessandro if (rcd->egrbufs.buffers[idx].addr) { 1966f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].len = 1967f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size; 1968f48ad614SDennis Dalessandro rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr = 1969f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr; 197060368186STymoteusz Kielan rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].dma = 197160368186STymoteusz Kielan rcd->egrbufs.buffers[idx].dma; 1972f48ad614SDennis Dalessandro rcd->egrbufs.alloced++; 1973f48ad614SDennis Dalessandro alloced_bytes += rcd->egrbufs.rcvtid_size; 1974f48ad614SDennis Dalessandro idx++; 1975f48ad614SDennis Dalessandro } else { 1976f48ad614SDennis Dalessandro u32 new_size, i, j; 1977f48ad614SDennis Dalessandro u64 offset = 0; 1978f48ad614SDennis Dalessandro 1979f48ad614SDennis Dalessandro /* 1980f48ad614SDennis Dalessandro * Fail the eager buffer allocation if: 1981f48ad614SDennis Dalessandro * - we are already using the lowest acceptable size 1982f48ad614SDennis Dalessandro * - we are using one-pkt-per-egr-buffer (this implies 1983f48ad614SDennis Dalessandro * that we are accepting only one size) 1984f48ad614SDennis Dalessandro */ 1985f48ad614SDennis Dalessandro if (rcd->egrbufs.rcvtid_size == round_mtu || 1986f48ad614SDennis Dalessandro !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) { 1987f48ad614SDennis Dalessandro dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n", 1988f48ad614SDennis Dalessandro rcd->ctxt); 198994679061SMichael J. Ruhl ret = -ENOMEM; 1990f48ad614SDennis Dalessandro goto bail_rcvegrbuf_phys; 1991f48ad614SDennis Dalessandro } 1992f48ad614SDennis Dalessandro 1993f48ad614SDennis Dalessandro new_size = rcd->egrbufs.rcvtid_size / 2; 1994f48ad614SDennis Dalessandro 1995f48ad614SDennis Dalessandro /* 1996f48ad614SDennis Dalessandro * If the first attempt to allocate memory failed, don't 1997f48ad614SDennis Dalessandro * fail everything but continue with the next lower 1998f48ad614SDennis Dalessandro * size. 1999f48ad614SDennis Dalessandro */ 2000f48ad614SDennis Dalessandro if (idx == 0) { 2001f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = new_size; 2002f48ad614SDennis Dalessandro continue; 2003f48ad614SDennis Dalessandro } 2004f48ad614SDennis Dalessandro 2005f48ad614SDennis Dalessandro /* 2006f48ad614SDennis Dalessandro * Re-partition already allocated buffers to a smaller 2007f48ad614SDennis Dalessandro * size. 2008f48ad614SDennis Dalessandro */ 2009f48ad614SDennis Dalessandro rcd->egrbufs.alloced = 0; 2010f48ad614SDennis Dalessandro for (i = 0, j = 0, offset = 0; j < idx; i++) { 2011f48ad614SDennis Dalessandro if (i >= rcd->egrbufs.count) 2012f48ad614SDennis Dalessandro break; 201360368186STymoteusz Kielan rcd->egrbufs.rcvtids[i].dma = 201460368186STymoteusz Kielan rcd->egrbufs.buffers[j].dma + offset; 2015f48ad614SDennis Dalessandro rcd->egrbufs.rcvtids[i].addr = 2016f48ad614SDennis Dalessandro rcd->egrbufs.buffers[j].addr + offset; 2017f48ad614SDennis Dalessandro rcd->egrbufs.alloced++; 201860368186STymoteusz Kielan if ((rcd->egrbufs.buffers[j].dma + offset + 2019f48ad614SDennis Dalessandro new_size) == 202060368186STymoteusz Kielan (rcd->egrbufs.buffers[j].dma + 2021f48ad614SDennis Dalessandro rcd->egrbufs.buffers[j].len)) { 2022f48ad614SDennis Dalessandro j++; 2023f48ad614SDennis Dalessandro offset = 0; 2024f48ad614SDennis Dalessandro } else { 2025f48ad614SDennis Dalessandro offset += new_size; 2026f48ad614SDennis Dalessandro } 2027f48ad614SDennis Dalessandro } 2028f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = new_size; 2029f48ad614SDennis Dalessandro } 2030f48ad614SDennis Dalessandro } 2031f48ad614SDennis Dalessandro rcd->egrbufs.numbufs = idx; 2032f48ad614SDennis Dalessandro rcd->egrbufs.size = alloced_bytes; 2033f48ad614SDennis Dalessandro 2034f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 2035f48ad614SDennis Dalessandro "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n", 203623002d5bSGrzegorz Heldt rcd->ctxt, rcd->egrbufs.alloced, 203723002d5bSGrzegorz Heldt rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024); 2038f48ad614SDennis Dalessandro 2039f48ad614SDennis Dalessandro /* 2040f48ad614SDennis Dalessandro * Set the contexts rcv array head update threshold to the closest 2041f48ad614SDennis Dalessandro * power of 2 (so we can use a mask instead of modulo) below half 2042f48ad614SDennis Dalessandro * the allocated entries. 2043f48ad614SDennis Dalessandro */ 2044f48ad614SDennis Dalessandro rcd->egrbufs.threshold = 2045f48ad614SDennis Dalessandro rounddown_pow_of_two(rcd->egrbufs.alloced / 2); 2046f48ad614SDennis Dalessandro /* 2047f48ad614SDennis Dalessandro * Compute the expected RcvArray entry base. This is done after 2048f48ad614SDennis Dalessandro * allocating the eager buffers in order to maximize the 2049f48ad614SDennis Dalessandro * expected RcvArray entries for the context. 2050f48ad614SDennis Dalessandro */ 2051f48ad614SDennis Dalessandro max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size; 2052f48ad614SDennis Dalessandro egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size); 2053f48ad614SDennis Dalessandro rcd->expected_count = max_entries - egrtop; 2054f48ad614SDennis Dalessandro if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2) 2055f48ad614SDennis Dalessandro rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2; 2056f48ad614SDennis Dalessandro 2057f48ad614SDennis Dalessandro rcd->expected_base = rcd->eager_base + egrtop; 2058f48ad614SDennis Dalessandro hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n", 2059f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count, 2060f48ad614SDennis Dalessandro rcd->eager_base, rcd->expected_base); 2061f48ad614SDennis Dalessandro 2062f48ad614SDennis Dalessandro if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) { 2063f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 2064f48ad614SDennis Dalessandro "ctxt%u: current Eager buffer size is invalid %u\n", 2065f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.rcvtid_size); 2066f48ad614SDennis Dalessandro ret = -EINVAL; 206762239fc6SMichael J. Ruhl goto bail_rcvegrbuf_phys; 2068f48ad614SDennis Dalessandro } 2069f48ad614SDennis Dalessandro 2070f48ad614SDennis Dalessandro for (idx = 0; idx < rcd->egrbufs.alloced; idx++) { 2071f48ad614SDennis Dalessandro hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER, 207260368186STymoteusz Kielan rcd->egrbufs.rcvtids[idx].dma, order); 2073f48ad614SDennis Dalessandro cond_resched(); 2074f48ad614SDennis Dalessandro } 207562239fc6SMichael J. Ruhl 207662239fc6SMichael J. Ruhl return 0; 2077f48ad614SDennis Dalessandro 2078f48ad614SDennis Dalessandro bail_rcvegrbuf_phys: 2079f48ad614SDennis Dalessandro for (idx = 0; idx < rcd->egrbufs.alloced && 2080f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr; 2081f48ad614SDennis Dalessandro idx++) { 2082f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, 2083f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].len, 2084f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr, 208560368186STymoteusz Kielan rcd->egrbufs.buffers[idx].dma); 2086f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr = NULL; 208760368186STymoteusz Kielan rcd->egrbufs.buffers[idx].dma = 0; 2088f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].len = 0; 2089f48ad614SDennis Dalessandro } 209062239fc6SMichael J. Ruhl 2091f48ad614SDennis Dalessandro return ret; 2092f48ad614SDennis Dalessandro } 2093