1f48ad614SDennis Dalessandro /* 2d4829ea6SVishwanathapura, Niranjana * Copyright(c) 2015-2017 Intel Corporation. 3f48ad614SDennis Dalessandro * 4f48ad614SDennis Dalessandro * This file is provided under a dual BSD/GPLv2 license. When using or 5f48ad614SDennis Dalessandro * redistributing this file, you may do so under either license. 6f48ad614SDennis Dalessandro * 7f48ad614SDennis Dalessandro * GPL LICENSE SUMMARY 8f48ad614SDennis Dalessandro * 9f48ad614SDennis Dalessandro * This program is free software; you can redistribute it and/or modify 10f48ad614SDennis Dalessandro * it under the terms of version 2 of the GNU General Public License as 11f48ad614SDennis Dalessandro * published by the Free Software Foundation. 12f48ad614SDennis Dalessandro * 13f48ad614SDennis Dalessandro * This program is distributed in the hope that it will be useful, but 14f48ad614SDennis Dalessandro * WITHOUT ANY WARRANTY; without even the implied warranty of 15f48ad614SDennis Dalessandro * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16f48ad614SDennis Dalessandro * General Public License for more details. 17f48ad614SDennis Dalessandro * 18f48ad614SDennis Dalessandro * BSD LICENSE 19f48ad614SDennis Dalessandro * 20f48ad614SDennis Dalessandro * Redistribution and use in source and binary forms, with or without 21f48ad614SDennis Dalessandro * modification, are permitted provided that the following conditions 22f48ad614SDennis Dalessandro * are met: 23f48ad614SDennis Dalessandro * 24f48ad614SDennis Dalessandro * - Redistributions of source code must retain the above copyright 25f48ad614SDennis Dalessandro * notice, this list of conditions and the following disclaimer. 26f48ad614SDennis Dalessandro * - Redistributions in binary form must reproduce the above copyright 27f48ad614SDennis Dalessandro * notice, this list of conditions and the following disclaimer in 28f48ad614SDennis Dalessandro * the documentation and/or other materials provided with the 29f48ad614SDennis Dalessandro * distribution. 30f48ad614SDennis Dalessandro * - Neither the name of Intel Corporation nor the names of its 31f48ad614SDennis Dalessandro * contributors may be used to endorse or promote products derived 32f48ad614SDennis Dalessandro * from this software without specific prior written permission. 33f48ad614SDennis Dalessandro * 34f48ad614SDennis Dalessandro * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35f48ad614SDennis Dalessandro * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36f48ad614SDennis Dalessandro * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37f48ad614SDennis Dalessandro * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38f48ad614SDennis Dalessandro * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39f48ad614SDennis Dalessandro * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40f48ad614SDennis Dalessandro * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41f48ad614SDennis Dalessandro * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42f48ad614SDennis Dalessandro * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43f48ad614SDennis Dalessandro * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44f48ad614SDennis Dalessandro * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45f48ad614SDennis Dalessandro * 46f48ad614SDennis Dalessandro */ 47f48ad614SDennis Dalessandro 48f48ad614SDennis Dalessandro #include <linux/pci.h> 49f48ad614SDennis Dalessandro #include <linux/netdevice.h> 50f48ad614SDennis Dalessandro #include <linux/vmalloc.h> 51f48ad614SDennis Dalessandro #include <linux/delay.h> 52f48ad614SDennis Dalessandro #include <linux/idr.h> 53f48ad614SDennis Dalessandro #include <linux/module.h> 54f48ad614SDennis Dalessandro #include <linux/printk.h> 55f48ad614SDennis Dalessandro #include <linux/hrtimer.h> 568737ce95SMichael J. Ruhl #include <linux/bitmap.h> 57f48ad614SDennis Dalessandro #include <rdma/rdma_vt.h> 58f48ad614SDennis Dalessandro 59f48ad614SDennis Dalessandro #include "hfi.h" 60f48ad614SDennis Dalessandro #include "device.h" 61f48ad614SDennis Dalessandro #include "common.h" 62f48ad614SDennis Dalessandro #include "trace.h" 63f48ad614SDennis Dalessandro #include "mad.h" 64f48ad614SDennis Dalessandro #include "sdma.h" 65f48ad614SDennis Dalessandro #include "debugfs.h" 66f48ad614SDennis Dalessandro #include "verbs.h" 67f48ad614SDennis Dalessandro #include "aspm.h" 684197344bSDennis Dalessandro #include "affinity.h" 69d4829ea6SVishwanathapura, Niranjana #include "vnic.h" 70fe4e74eeSMichael J. Ruhl #include "exp_rcv.h" 71f48ad614SDennis Dalessandro 72f48ad614SDennis Dalessandro #undef pr_fmt 73f48ad614SDennis Dalessandro #define pr_fmt(fmt) DRIVER_NAME ": " fmt 74f48ad614SDennis Dalessandro 75dd1ed108SMike Marciniszyn #define HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES 5 76f48ad614SDennis Dalessandro /* 77f48ad614SDennis Dalessandro * min buffers we want to have per context, after driver 78f48ad614SDennis Dalessandro */ 79f48ad614SDennis Dalessandro #define HFI1_MIN_USER_CTXT_BUFCNT 7 80f48ad614SDennis Dalessandro 81f48ad614SDennis Dalessandro #define HFI1_MIN_HDRQ_EGRBUF_CNT 2 82f48ad614SDennis Dalessandro #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352 83f48ad614SDennis Dalessandro #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */ 84f48ad614SDennis Dalessandro #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */ 85f48ad614SDennis Dalessandro 86f48ad614SDennis Dalessandro /* 87f48ad614SDennis Dalessandro * Number of user receive contexts we are configured to use (to allow for more 88f48ad614SDennis Dalessandro * pio buffers per ctxt, etc.) Zero means use one user context per CPU. 89f48ad614SDennis Dalessandro */ 90f48ad614SDennis Dalessandro int num_user_contexts = -1; 91f48ad614SDennis Dalessandro module_param_named(num_user_contexts, num_user_contexts, uint, S_IRUGO); 92f48ad614SDennis Dalessandro MODULE_PARM_DESC( 93f48ad614SDennis Dalessandro num_user_contexts, "Set max number of user contexts to use"); 94f48ad614SDennis Dalessandro 95f48ad614SDennis Dalessandro uint krcvqs[RXE_NUM_DATA_VL]; 96f48ad614SDennis Dalessandro int krcvqsset; 97f48ad614SDennis Dalessandro module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO); 98f48ad614SDennis Dalessandro MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL"); 99f48ad614SDennis Dalessandro 100f48ad614SDennis Dalessandro /* computed based on above array */ 101429b6a72SHarish Chegondi unsigned long n_krcvqs; 102f48ad614SDennis Dalessandro 103f48ad614SDennis Dalessandro static unsigned hfi1_rcvarr_split = 25; 104f48ad614SDennis Dalessandro module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO); 105f48ad614SDennis Dalessandro MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers"); 106f48ad614SDennis Dalessandro 1079746fa43STymoteusz Kielan static uint eager_buffer_size = (8 << 20); /* 8MB */ 108f48ad614SDennis Dalessandro module_param(eager_buffer_size, uint, S_IRUGO); 1099746fa43STymoteusz Kielan MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 8MB"); 110f48ad614SDennis Dalessandro 111f48ad614SDennis Dalessandro static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */ 112f48ad614SDennis Dalessandro module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO); 113f48ad614SDennis Dalessandro MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)"); 114f48ad614SDennis Dalessandro 115f48ad614SDennis Dalessandro static uint hfi1_hdrq_entsize = 32; 116f48ad614SDennis Dalessandro module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO); 117f48ad614SDennis Dalessandro MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B"); 118f48ad614SDennis Dalessandro 119f48ad614SDennis Dalessandro unsigned int user_credit_return_threshold = 33; /* default is 33% */ 120f48ad614SDennis Dalessandro module_param(user_credit_return_threshold, uint, S_IRUGO); 121f48ad614SDennis Dalessandro MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)"); 122f48ad614SDennis Dalessandro 123f4cd8765SMichael J. Ruhl static inline u64 encode_rcv_header_entry_size(u16 size); 124f48ad614SDennis Dalessandro 125f48ad614SDennis Dalessandro static struct idr hfi1_unit_table; 126f48ad614SDennis Dalessandro u32 hfi1_cpulist_count; 127f48ad614SDennis Dalessandro unsigned long *hfi1_cpulist; 128f48ad614SDennis Dalessandro 129f48ad614SDennis Dalessandro /* 130f48ad614SDennis Dalessandro * Common code for creating the receive context array. 131f48ad614SDennis Dalessandro */ 132f48ad614SDennis Dalessandro int hfi1_create_ctxts(struct hfi1_devdata *dd) 133f48ad614SDennis Dalessandro { 134e6f7622dSMichael J. Ruhl u16 i; 135f48ad614SDennis Dalessandro int ret; 136f48ad614SDennis Dalessandro 137f48ad614SDennis Dalessandro /* Control context has to be always 0 */ 138f48ad614SDennis Dalessandro BUILD_BUG_ON(HFI1_CTRL_CTXT != 0); 139f48ad614SDennis Dalessandro 140f48ad614SDennis Dalessandro dd->rcd = kzalloc_node(dd->num_rcv_contexts * sizeof(*dd->rcd), 141f48ad614SDennis Dalessandro GFP_KERNEL, dd->node); 142f48ad614SDennis Dalessandro if (!dd->rcd) 143f48ad614SDennis Dalessandro goto nomem; 144f48ad614SDennis Dalessandro 145f48ad614SDennis Dalessandro /* create one or more kernel contexts */ 1462280740fSVishwanathapura, Niranjana for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) { 147f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 148f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd; 149f48ad614SDennis Dalessandro 150f48ad614SDennis Dalessandro ppd = dd->pport + (i % dd->num_pports); 1514dfe7cceSJianxin Xiong 1524dfe7cceSJianxin Xiong /* dd->rcd[i] gets assigned inside the callee */ 153f48ad614SDennis Dalessandro rcd = hfi1_create_ctxtdata(ppd, i, dd->node); 154f48ad614SDennis Dalessandro if (!rcd) { 155f48ad614SDennis Dalessandro dd_dev_err(dd, 156f48ad614SDennis Dalessandro "Unable to allocate kernel receive context, failing\n"); 157f48ad614SDennis Dalessandro goto nomem; 158f48ad614SDennis Dalessandro } 159f48ad614SDennis Dalessandro /* 160f48ad614SDennis Dalessandro * Set up the kernel context flags here and now because they 161f48ad614SDennis Dalessandro * use default values for all receive side memories. User 162f48ad614SDennis Dalessandro * contexts will be handled as they are created. 163f48ad614SDennis Dalessandro */ 164f48ad614SDennis Dalessandro rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) | 165f48ad614SDennis Dalessandro HFI1_CAP_KGET(NODROP_RHQ_FULL) | 166f48ad614SDennis Dalessandro HFI1_CAP_KGET(NODROP_EGR_FULL) | 167f48ad614SDennis Dalessandro HFI1_CAP_KGET(DMA_RTAIL); 168f48ad614SDennis Dalessandro 169f48ad614SDennis Dalessandro /* Control context must use DMA_RTAIL */ 170f48ad614SDennis Dalessandro if (rcd->ctxt == HFI1_CTRL_CTXT) 171f48ad614SDennis Dalessandro rcd->flags |= HFI1_CAP_DMA_RTAIL; 172f48ad614SDennis Dalessandro rcd->seq_cnt = 1; 173f48ad614SDennis Dalessandro 174f48ad614SDennis Dalessandro rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node); 175f48ad614SDennis Dalessandro if (!rcd->sc) { 176f48ad614SDennis Dalessandro dd_dev_err(dd, 177f48ad614SDennis Dalessandro "Unable to allocate kernel send context, failing\n"); 178f48ad614SDennis Dalessandro goto nomem; 179f48ad614SDennis Dalessandro } 180f48ad614SDennis Dalessandro 1819b60d2cbSMichael J. Ruhl hfi1_init_ctxt(rcd->sc); 182f48ad614SDennis Dalessandro } 183f48ad614SDennis Dalessandro 184f48ad614SDennis Dalessandro /* 185f48ad614SDennis Dalessandro * Initialize aspm, to be done after gen3 transition and setting up 186f48ad614SDennis Dalessandro * contexts and before enabling interrupts 187f48ad614SDennis Dalessandro */ 188f48ad614SDennis Dalessandro aspm_init(dd); 189f48ad614SDennis Dalessandro 190f48ad614SDennis Dalessandro return 0; 191f48ad614SDennis Dalessandro nomem: 192f48ad614SDennis Dalessandro ret = -ENOMEM; 1939b60d2cbSMichael J. Ruhl 194f683c80cSMichael J. Ruhl for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) 195f683c80cSMichael J. Ruhl hfi1_rcd_put(dd->rcd[i]); 196f683c80cSMichael J. Ruhl 197f683c80cSMichael J. Ruhl /* All the contexts should be freed, free the array */ 198f48ad614SDennis Dalessandro kfree(dd->rcd); 199f48ad614SDennis Dalessandro dd->rcd = NULL; 200f48ad614SDennis Dalessandro return ret; 201f48ad614SDennis Dalessandro } 202f48ad614SDennis Dalessandro 203f48ad614SDennis Dalessandro /* 204f683c80cSMichael J. Ruhl * Helper routines for the receive context reference count (rcd and uctxt) 205f683c80cSMichael J. Ruhl */ 206f683c80cSMichael J. Ruhl static void hfi1_rcd_init(struct hfi1_ctxtdata *rcd) 207f683c80cSMichael J. Ruhl { 208f683c80cSMichael J. Ruhl kref_init(&rcd->kref); 209f683c80cSMichael J. Ruhl } 210f683c80cSMichael J. Ruhl 211f683c80cSMichael J. Ruhl static void hfi1_rcd_free(struct kref *kref) 212f683c80cSMichael J. Ruhl { 213f683c80cSMichael J. Ruhl struct hfi1_ctxtdata *rcd = 214f683c80cSMichael J. Ruhl container_of(kref, struct hfi1_ctxtdata, kref); 215f683c80cSMichael J. Ruhl 216f683c80cSMichael J. Ruhl hfi1_free_ctxtdata(rcd->dd, rcd); 217f683c80cSMichael J. Ruhl kfree(rcd); 218f683c80cSMichael J. Ruhl } 219f683c80cSMichael J. Ruhl 220f683c80cSMichael J. Ruhl int hfi1_rcd_put(struct hfi1_ctxtdata *rcd) 221f683c80cSMichael J. Ruhl { 222f683c80cSMichael J. Ruhl if (rcd) 223f683c80cSMichael J. Ruhl return kref_put(&rcd->kref, hfi1_rcd_free); 224f683c80cSMichael J. Ruhl 225f683c80cSMichael J. Ruhl return 0; 226f683c80cSMichael J. Ruhl } 227f683c80cSMichael J. Ruhl 228f683c80cSMichael J. Ruhl void hfi1_rcd_get(struct hfi1_ctxtdata *rcd) 229f683c80cSMichael J. Ruhl { 230f683c80cSMichael J. Ruhl kref_get(&rcd->kref); 231f683c80cSMichael J. Ruhl } 232f683c80cSMichael J. Ruhl 233f683c80cSMichael J. Ruhl /* 234f48ad614SDennis Dalessandro * Common code for user and kernel context setup. 235f48ad614SDennis Dalessandro */ 236e6f7622dSMichael J. Ruhl struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u16 ctxt, 237f48ad614SDennis Dalessandro int numa) 238f48ad614SDennis Dalessandro { 239f48ad614SDennis Dalessandro struct hfi1_devdata *dd = ppd->dd; 240f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd; 241f48ad614SDennis Dalessandro unsigned kctxt_ngroups = 0; 242f48ad614SDennis Dalessandro u32 base; 243f48ad614SDennis Dalessandro 244f48ad614SDennis Dalessandro if (dd->rcv_entries.nctxt_extra > 2452280740fSVishwanathapura, Niranjana dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt) 246f48ad614SDennis Dalessandro kctxt_ngroups = (dd->rcv_entries.nctxt_extra - 2472280740fSVishwanathapura, Niranjana (dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt)); 2484dfe7cceSJianxin Xiong rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa); 249f48ad614SDennis Dalessandro if (rcd) { 250f48ad614SDennis Dalessandro u32 rcvtids, max_entries; 251f48ad614SDennis Dalessandro 252f48ad614SDennis Dalessandro hfi1_cdbg(PROC, "setting up context %u\n", ctxt); 253f48ad614SDennis Dalessandro 254f48ad614SDennis Dalessandro INIT_LIST_HEAD(&rcd->qp_wait_list); 255fe4e74eeSMichael J. Ruhl hfi1_exp_tid_group_init(&rcd->tid_group_list); 256fe4e74eeSMichael J. Ruhl hfi1_exp_tid_group_init(&rcd->tid_used_list); 257fe4e74eeSMichael J. Ruhl hfi1_exp_tid_group_init(&rcd->tid_full_list); 258f48ad614SDennis Dalessandro rcd->ppd = ppd; 259f48ad614SDennis Dalessandro rcd->dd = dd; 2608737ce95SMichael J. Ruhl __set_bit(0, rcd->in_use_ctxts); 261f48ad614SDennis Dalessandro rcd->ctxt = ctxt; 262f48ad614SDennis Dalessandro dd->rcd[ctxt] = rcd; 263f48ad614SDennis Dalessandro rcd->numa_id = numa; 264f48ad614SDennis Dalessandro rcd->rcv_array_groups = dd->rcv_entries.ngroups; 265f48ad614SDennis Dalessandro 266f48ad614SDennis Dalessandro mutex_init(&rcd->exp_lock); 267f48ad614SDennis Dalessandro 268f48ad614SDennis Dalessandro /* 269f48ad614SDennis Dalessandro * Calculate the context's RcvArray entry starting point. 270f48ad614SDennis Dalessandro * We do this here because we have to take into account all 271f48ad614SDennis Dalessandro * the RcvArray entries that previous context would have 2722280740fSVishwanathapura, Niranjana * taken and we have to account for any extra groups assigned 2732280740fSVishwanathapura, Niranjana * to the static (kernel) or dynamic (vnic/user) contexts. 274f48ad614SDennis Dalessandro */ 2752280740fSVishwanathapura, Niranjana if (ctxt < dd->first_dyn_alloc_ctxt) { 276f48ad614SDennis Dalessandro if (ctxt < kctxt_ngroups) { 277f48ad614SDennis Dalessandro base = ctxt * (dd->rcv_entries.ngroups + 1); 278f48ad614SDennis Dalessandro rcd->rcv_array_groups++; 279ee495adaSDennis Dalessandro } else { 280f48ad614SDennis Dalessandro base = kctxt_ngroups + 281f48ad614SDennis Dalessandro (ctxt * dd->rcv_entries.ngroups); 282ee495adaSDennis Dalessandro } 283f48ad614SDennis Dalessandro } else { 2842280740fSVishwanathapura, Niranjana u16 ct = ctxt - dd->first_dyn_alloc_ctxt; 285f48ad614SDennis Dalessandro 286f48ad614SDennis Dalessandro base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) + 287f48ad614SDennis Dalessandro kctxt_ngroups); 288f48ad614SDennis Dalessandro if (ct < dd->rcv_entries.nctxt_extra) { 289f48ad614SDennis Dalessandro base += ct * (dd->rcv_entries.ngroups + 1); 290f48ad614SDennis Dalessandro rcd->rcv_array_groups++; 291ee495adaSDennis Dalessandro } else { 292f48ad614SDennis Dalessandro base += dd->rcv_entries.nctxt_extra + 293f48ad614SDennis Dalessandro (ct * dd->rcv_entries.ngroups); 294f48ad614SDennis Dalessandro } 295ee495adaSDennis Dalessandro } 296f48ad614SDennis Dalessandro rcd->eager_base = base * dd->rcv_entries.group_size; 297f48ad614SDennis Dalessandro 298f48ad614SDennis Dalessandro rcd->rcvhdrq_cnt = rcvhdrcnt; 299f48ad614SDennis Dalessandro rcd->rcvhdrqentsize = hfi1_hdrq_entsize; 300f48ad614SDennis Dalessandro /* 301f48ad614SDennis Dalessandro * Simple Eager buffer allocation: we have already pre-allocated 302f48ad614SDennis Dalessandro * the number of RcvArray entry groups. Each ctxtdata structure 303f48ad614SDennis Dalessandro * holds the number of groups for that context. 304f48ad614SDennis Dalessandro * 305f48ad614SDennis Dalessandro * To follow CSR requirements and maintain cacheline alignment, 306f48ad614SDennis Dalessandro * make sure all sizes and bases are multiples of group_size. 307f48ad614SDennis Dalessandro * 308f48ad614SDennis Dalessandro * The expected entry count is what is left after assigning 309f48ad614SDennis Dalessandro * eager. 310f48ad614SDennis Dalessandro */ 311f48ad614SDennis Dalessandro max_entries = rcd->rcv_array_groups * 312f48ad614SDennis Dalessandro dd->rcv_entries.group_size; 313f48ad614SDennis Dalessandro rcvtids = ((max_entries * hfi1_rcvarr_split) / 100); 314f48ad614SDennis Dalessandro rcd->egrbufs.count = round_down(rcvtids, 315f48ad614SDennis Dalessandro dd->rcv_entries.group_size); 316f48ad614SDennis Dalessandro if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) { 317f48ad614SDennis Dalessandro dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n", 318f48ad614SDennis Dalessandro rcd->ctxt); 319f48ad614SDennis Dalessandro rcd->egrbufs.count = MAX_EAGER_ENTRIES; 320f48ad614SDennis Dalessandro } 321f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 322f48ad614SDennis Dalessandro "ctxt%u: max Eager buffer RcvArray entries: %u\n", 323f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.count); 324f48ad614SDennis Dalessandro 325f48ad614SDennis Dalessandro /* 326f48ad614SDennis Dalessandro * Allocate array that will hold the eager buffer accounting 327f48ad614SDennis Dalessandro * data. 328f48ad614SDennis Dalessandro * This will allocate the maximum possible buffer count based 329f48ad614SDennis Dalessandro * on the value of the RcvArray split parameter. 330f48ad614SDennis Dalessandro * The resulting value will be rounded down to the closest 331f48ad614SDennis Dalessandro * multiple of dd->rcv_entries.group_size. 332f48ad614SDennis Dalessandro */ 333b448bf9aSSebastian Sanchez rcd->egrbufs.buffers = kzalloc_node( 334b448bf9aSSebastian Sanchez rcd->egrbufs.count * sizeof(*rcd->egrbufs.buffers), 335b448bf9aSSebastian Sanchez GFP_KERNEL, numa); 336f48ad614SDennis Dalessandro if (!rcd->egrbufs.buffers) 337f48ad614SDennis Dalessandro goto bail; 338b448bf9aSSebastian Sanchez rcd->egrbufs.rcvtids = kzalloc_node( 339b448bf9aSSebastian Sanchez rcd->egrbufs.count * 340f48ad614SDennis Dalessandro sizeof(*rcd->egrbufs.rcvtids), 341b448bf9aSSebastian Sanchez GFP_KERNEL, numa); 342f48ad614SDennis Dalessandro if (!rcd->egrbufs.rcvtids) 343f48ad614SDennis Dalessandro goto bail; 344f48ad614SDennis Dalessandro rcd->egrbufs.size = eager_buffer_size; 345f48ad614SDennis Dalessandro /* 346f48ad614SDennis Dalessandro * The size of the buffers programmed into the RcvArray 347f48ad614SDennis Dalessandro * entries needs to be big enough to handle the highest 348f48ad614SDennis Dalessandro * MTU supported. 349f48ad614SDennis Dalessandro */ 350f48ad614SDennis Dalessandro if (rcd->egrbufs.size < hfi1_max_mtu) { 351f48ad614SDennis Dalessandro rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu); 352f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 353f48ad614SDennis Dalessandro "ctxt%u: eager bufs size too small. Adjusting to %zu\n", 354f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.size); 355f48ad614SDennis Dalessandro } 356f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE; 357f48ad614SDennis Dalessandro 3582280740fSVishwanathapura, Niranjana /* Applicable only for statically created kernel contexts */ 3592280740fSVishwanathapura, Niranjana if (ctxt < dd->first_dyn_alloc_ctxt) { 360b448bf9aSSebastian Sanchez rcd->opstats = kzalloc_node(sizeof(*rcd->opstats), 361b448bf9aSSebastian Sanchez GFP_KERNEL, numa); 362f48ad614SDennis Dalessandro if (!rcd->opstats) 363f48ad614SDennis Dalessandro goto bail; 364f48ad614SDennis Dalessandro } 365f683c80cSMichael J. Ruhl 366f683c80cSMichael J. Ruhl hfi1_rcd_init(rcd); 367f48ad614SDennis Dalessandro } 368f48ad614SDennis Dalessandro return rcd; 369f48ad614SDennis Dalessandro bail: 3703a6982dfSJakub Pawlak dd->rcd[ctxt] = NULL; 371f48ad614SDennis Dalessandro kfree(rcd->egrbufs.rcvtids); 372f48ad614SDennis Dalessandro kfree(rcd->egrbufs.buffers); 373f48ad614SDennis Dalessandro kfree(rcd); 374f48ad614SDennis Dalessandro return NULL; 375f48ad614SDennis Dalessandro } 376f48ad614SDennis Dalessandro 377f48ad614SDennis Dalessandro /* 378f48ad614SDennis Dalessandro * Convert a receive header entry size that to the encoding used in the CSR. 379f48ad614SDennis Dalessandro * 380f48ad614SDennis Dalessandro * Return a zero if the given size is invalid. 381f48ad614SDennis Dalessandro */ 382f48ad614SDennis Dalessandro static inline u64 encode_rcv_header_entry_size(u16 size) 383f48ad614SDennis Dalessandro { 384f48ad614SDennis Dalessandro /* there are only 3 valid receive header entry sizes */ 385f48ad614SDennis Dalessandro if (size == 2) 386f48ad614SDennis Dalessandro return 1; 387f48ad614SDennis Dalessandro if (size == 16) 388f48ad614SDennis Dalessandro return 2; 389f48ad614SDennis Dalessandro else if (size == 32) 390f48ad614SDennis Dalessandro return 4; 391f48ad614SDennis Dalessandro return 0; /* invalid */ 392f48ad614SDennis Dalessandro } 393f48ad614SDennis Dalessandro 394f48ad614SDennis Dalessandro /* 395f48ad614SDennis Dalessandro * Select the largest ccti value over all SLs to determine the intra- 396f48ad614SDennis Dalessandro * packet gap for the link. 397f48ad614SDennis Dalessandro * 398f48ad614SDennis Dalessandro * called with cca_timer_lock held (to protect access to cca_timer 399f48ad614SDennis Dalessandro * array), and rcu_read_lock() (to protect access to cc_state). 400f48ad614SDennis Dalessandro */ 401f48ad614SDennis Dalessandro void set_link_ipg(struct hfi1_pportdata *ppd) 402f48ad614SDennis Dalessandro { 403f48ad614SDennis Dalessandro struct hfi1_devdata *dd = ppd->dd; 404f48ad614SDennis Dalessandro struct cc_state *cc_state; 405f48ad614SDennis Dalessandro int i; 406f48ad614SDennis Dalessandro u16 cce, ccti_limit, max_ccti = 0; 407f48ad614SDennis Dalessandro u16 shift, mult; 408f48ad614SDennis Dalessandro u64 src; 409f48ad614SDennis Dalessandro u32 current_egress_rate; /* Mbits /sec */ 410f48ad614SDennis Dalessandro u32 max_pkt_time; 411f48ad614SDennis Dalessandro /* 412f48ad614SDennis Dalessandro * max_pkt_time is the maximum packet egress time in units 413f48ad614SDennis Dalessandro * of the fabric clock period 1/(805 MHz). 414f48ad614SDennis Dalessandro */ 415f48ad614SDennis Dalessandro 416f48ad614SDennis Dalessandro cc_state = get_cc_state(ppd); 417f48ad614SDennis Dalessandro 418f48ad614SDennis Dalessandro if (!cc_state) 419f48ad614SDennis Dalessandro /* 420f48ad614SDennis Dalessandro * This should _never_ happen - rcu_read_lock() is held, 421f48ad614SDennis Dalessandro * and set_link_ipg() should not be called if cc_state 422f48ad614SDennis Dalessandro * is NULL. 423f48ad614SDennis Dalessandro */ 424f48ad614SDennis Dalessandro return; 425f48ad614SDennis Dalessandro 426f48ad614SDennis Dalessandro for (i = 0; i < OPA_MAX_SLS; i++) { 427f48ad614SDennis Dalessandro u16 ccti = ppd->cca_timer[i].ccti; 428f48ad614SDennis Dalessandro 429f48ad614SDennis Dalessandro if (ccti > max_ccti) 430f48ad614SDennis Dalessandro max_ccti = ccti; 431f48ad614SDennis Dalessandro } 432f48ad614SDennis Dalessandro 433f48ad614SDennis Dalessandro ccti_limit = cc_state->cct.ccti_limit; 434f48ad614SDennis Dalessandro if (max_ccti > ccti_limit) 435f48ad614SDennis Dalessandro max_ccti = ccti_limit; 436f48ad614SDennis Dalessandro 437f48ad614SDennis Dalessandro cce = cc_state->cct.entries[max_ccti].entry; 438f48ad614SDennis Dalessandro shift = (cce & 0xc000) >> 14; 439f48ad614SDennis Dalessandro mult = (cce & 0x3fff); 440f48ad614SDennis Dalessandro 441f48ad614SDennis Dalessandro current_egress_rate = active_egress_rate(ppd); 442f48ad614SDennis Dalessandro 443f48ad614SDennis Dalessandro max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate); 444f48ad614SDennis Dalessandro 445f48ad614SDennis Dalessandro src = (max_pkt_time >> shift) * mult; 446f48ad614SDennis Dalessandro 447f48ad614SDennis Dalessandro src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK; 448f48ad614SDennis Dalessandro src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT; 449f48ad614SDennis Dalessandro 450f48ad614SDennis Dalessandro write_csr(dd, SEND_STATIC_RATE_CONTROL, src); 451f48ad614SDennis Dalessandro } 452f48ad614SDennis Dalessandro 453f48ad614SDennis Dalessandro static enum hrtimer_restart cca_timer_fn(struct hrtimer *t) 454f48ad614SDennis Dalessandro { 455f48ad614SDennis Dalessandro struct cca_timer *cca_timer; 456f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 457f48ad614SDennis Dalessandro int sl; 458f48ad614SDennis Dalessandro u16 ccti_timer, ccti_min; 459f48ad614SDennis Dalessandro struct cc_state *cc_state; 460f48ad614SDennis Dalessandro unsigned long flags; 461f48ad614SDennis Dalessandro enum hrtimer_restart ret = HRTIMER_NORESTART; 462f48ad614SDennis Dalessandro 463f48ad614SDennis Dalessandro cca_timer = container_of(t, struct cca_timer, hrtimer); 464f48ad614SDennis Dalessandro ppd = cca_timer->ppd; 465f48ad614SDennis Dalessandro sl = cca_timer->sl; 466f48ad614SDennis Dalessandro 467f48ad614SDennis Dalessandro rcu_read_lock(); 468f48ad614SDennis Dalessandro 469f48ad614SDennis Dalessandro cc_state = get_cc_state(ppd); 470f48ad614SDennis Dalessandro 471f48ad614SDennis Dalessandro if (!cc_state) { 472f48ad614SDennis Dalessandro rcu_read_unlock(); 473f48ad614SDennis Dalessandro return HRTIMER_NORESTART; 474f48ad614SDennis Dalessandro } 475f48ad614SDennis Dalessandro 476f48ad614SDennis Dalessandro /* 477f48ad614SDennis Dalessandro * 1) decrement ccti for SL 478f48ad614SDennis Dalessandro * 2) calculate IPG for link (set_link_ipg()) 479f48ad614SDennis Dalessandro * 3) restart timer, unless ccti is at min value 480f48ad614SDennis Dalessandro */ 481f48ad614SDennis Dalessandro 482f48ad614SDennis Dalessandro ccti_min = cc_state->cong_setting.entries[sl].ccti_min; 483f48ad614SDennis Dalessandro ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer; 484f48ad614SDennis Dalessandro 485f48ad614SDennis Dalessandro spin_lock_irqsave(&ppd->cca_timer_lock, flags); 486f48ad614SDennis Dalessandro 487f48ad614SDennis Dalessandro if (cca_timer->ccti > ccti_min) { 488f48ad614SDennis Dalessandro cca_timer->ccti--; 489f48ad614SDennis Dalessandro set_link_ipg(ppd); 490f48ad614SDennis Dalessandro } 491f48ad614SDennis Dalessandro 492f48ad614SDennis Dalessandro if (cca_timer->ccti > ccti_min) { 493f48ad614SDennis Dalessandro unsigned long nsec = 1024 * ccti_timer; 494f48ad614SDennis Dalessandro /* ccti_timer is in units of 1.024 usec */ 495f48ad614SDennis Dalessandro hrtimer_forward_now(t, ns_to_ktime(nsec)); 496f48ad614SDennis Dalessandro ret = HRTIMER_RESTART; 497f48ad614SDennis Dalessandro } 498f48ad614SDennis Dalessandro 499f48ad614SDennis Dalessandro spin_unlock_irqrestore(&ppd->cca_timer_lock, flags); 500f48ad614SDennis Dalessandro rcu_read_unlock(); 501f48ad614SDennis Dalessandro return ret; 502f48ad614SDennis Dalessandro } 503f48ad614SDennis Dalessandro 504f48ad614SDennis Dalessandro /* 505f48ad614SDennis Dalessandro * Common code for initializing the physical port structure. 506f48ad614SDennis Dalessandro */ 507f48ad614SDennis Dalessandro void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, 508f48ad614SDennis Dalessandro struct hfi1_devdata *dd, u8 hw_pidx, u8 port) 509f48ad614SDennis Dalessandro { 5108adf71faSJianxin Xiong int i; 511f48ad614SDennis Dalessandro uint default_pkey_idx; 5128adf71faSJianxin Xiong struct cc_state *cc_state; 513f48ad614SDennis Dalessandro 514f48ad614SDennis Dalessandro ppd->dd = dd; 515f48ad614SDennis Dalessandro ppd->hw_pidx = hw_pidx; 516f48ad614SDennis Dalessandro ppd->port = port; /* IB port number, not index */ 517f48ad614SDennis Dalessandro 518f48ad614SDennis Dalessandro default_pkey_idx = 1; 519f48ad614SDennis Dalessandro 520f48ad614SDennis Dalessandro ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY; 52153526500SNeel Desai ppd->part_enforce |= HFI1_PART_ENFORCE_IN; 52253526500SNeel Desai ppd->part_enforce |= HFI1_PART_ENFORCE_OUT; 52353526500SNeel Desai 524f48ad614SDennis Dalessandro if (loopback) { 525f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 526f48ad614SDennis Dalessandro "Faking data partition 0x8001 in idx %u\n", 527f48ad614SDennis Dalessandro !default_pkey_idx); 528f48ad614SDennis Dalessandro ppd->pkeys[!default_pkey_idx] = 0x8001; 529f48ad614SDennis Dalessandro } 530f48ad614SDennis Dalessandro 531f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_vc_work, handle_verify_cap); 532f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_up_work, handle_link_up); 533f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_down_work, handle_link_down); 534f48ad614SDennis Dalessandro INIT_WORK(&ppd->freeze_work, handle_freeze); 535f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade); 536f48ad614SDennis Dalessandro INIT_WORK(&ppd->sma_message_work, handle_sma_message); 537f48ad614SDennis Dalessandro INIT_WORK(&ppd->link_bounce_work, handle_link_bounce); 538673b975fSDean Luick INIT_DELAYED_WORK(&ppd->start_link_work, handle_start_link); 539f48ad614SDennis Dalessandro INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work); 540f48ad614SDennis Dalessandro INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event); 541f48ad614SDennis Dalessandro 542f48ad614SDennis Dalessandro mutex_init(&ppd->hls_lock); 543f48ad614SDennis Dalessandro spin_lock_init(&ppd->qsfp_info.qsfp_lock); 544f48ad614SDennis Dalessandro 545f48ad614SDennis Dalessandro ppd->qsfp_info.ppd = ppd; 546f48ad614SDennis Dalessandro ppd->sm_trap_qp = 0x0; 547f48ad614SDennis Dalessandro ppd->sa_qp = 0x1; 548f48ad614SDennis Dalessandro 549f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 550f48ad614SDennis Dalessandro 551f48ad614SDennis Dalessandro spin_lock_init(&ppd->cca_timer_lock); 552f48ad614SDennis Dalessandro 553f48ad614SDennis Dalessandro for (i = 0; i < OPA_MAX_SLS; i++) { 554f48ad614SDennis Dalessandro hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC, 555f48ad614SDennis Dalessandro HRTIMER_MODE_REL); 556f48ad614SDennis Dalessandro ppd->cca_timer[i].ppd = ppd; 557f48ad614SDennis Dalessandro ppd->cca_timer[i].sl = i; 558f48ad614SDennis Dalessandro ppd->cca_timer[i].ccti = 0; 559f48ad614SDennis Dalessandro ppd->cca_timer[i].hrtimer.function = cca_timer_fn; 560f48ad614SDennis Dalessandro } 561f48ad614SDennis Dalessandro 562f48ad614SDennis Dalessandro ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT; 563f48ad614SDennis Dalessandro 564f48ad614SDennis Dalessandro spin_lock_init(&ppd->cc_state_lock); 565f48ad614SDennis Dalessandro spin_lock_init(&ppd->cc_log_lock); 5668adf71faSJianxin Xiong cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL); 5678adf71faSJianxin Xiong RCU_INIT_POINTER(ppd->cc_state, cc_state); 5688adf71faSJianxin Xiong if (!cc_state) 569f48ad614SDennis Dalessandro goto bail; 570f48ad614SDennis Dalessandro return; 571f48ad614SDennis Dalessandro 572f48ad614SDennis Dalessandro bail: 573f48ad614SDennis Dalessandro 574f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 575f48ad614SDennis Dalessandro "Congestion Control Agent disabled for port %d\n", port); 576f48ad614SDennis Dalessandro } 577f48ad614SDennis Dalessandro 578f48ad614SDennis Dalessandro /* 579f48ad614SDennis Dalessandro * Do initialization for device that is only needed on 580f48ad614SDennis Dalessandro * first detect, not on resets. 581f48ad614SDennis Dalessandro */ 582f48ad614SDennis Dalessandro static int loadtime_init(struct hfi1_devdata *dd) 583f48ad614SDennis Dalessandro { 584f48ad614SDennis Dalessandro return 0; 585f48ad614SDennis Dalessandro } 586f48ad614SDennis Dalessandro 587f48ad614SDennis Dalessandro /** 588f48ad614SDennis Dalessandro * init_after_reset - re-initialize after a reset 589f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 590f48ad614SDennis Dalessandro * 591f48ad614SDennis Dalessandro * sanity check at least some of the values after reset, and 592f48ad614SDennis Dalessandro * ensure no receive or transmit (explicitly, in case reset 593f48ad614SDennis Dalessandro * failed 594f48ad614SDennis Dalessandro */ 595f48ad614SDennis Dalessandro static int init_after_reset(struct hfi1_devdata *dd) 596f48ad614SDennis Dalessandro { 597f48ad614SDennis Dalessandro int i; 598f48ad614SDennis Dalessandro 599f48ad614SDennis Dalessandro /* 600f48ad614SDennis Dalessandro * Ensure chip does no sends or receives, tail updates, or 601f48ad614SDennis Dalessandro * pioavail updates while we re-initialize. This is mostly 602f48ad614SDennis Dalessandro * for the driver data structures, not chip registers. 603f48ad614SDennis Dalessandro */ 604f48ad614SDennis Dalessandro for (i = 0; i < dd->num_rcv_contexts; i++) 605f48ad614SDennis Dalessandro hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS | 606f48ad614SDennis Dalessandro HFI1_RCVCTRL_INTRAVAIL_DIS | 607f48ad614SDennis Dalessandro HFI1_RCVCTRL_TAILUPD_DIS, i); 608f48ad614SDennis Dalessandro pio_send_control(dd, PSC_GLOBAL_DISABLE); 609f48ad614SDennis Dalessandro for (i = 0; i < dd->num_send_contexts; i++) 610f48ad614SDennis Dalessandro sc_disable(dd->send_contexts[i].sc); 611f48ad614SDennis Dalessandro 612f48ad614SDennis Dalessandro return 0; 613f48ad614SDennis Dalessandro } 614f48ad614SDennis Dalessandro 615f48ad614SDennis Dalessandro static void enable_chip(struct hfi1_devdata *dd) 616f48ad614SDennis Dalessandro { 617f48ad614SDennis Dalessandro u32 rcvmask; 618e6f7622dSMichael J. Ruhl u16 i; 619f48ad614SDennis Dalessandro 620f48ad614SDennis Dalessandro /* enable PIO send */ 621f48ad614SDennis Dalessandro pio_send_control(dd, PSC_GLOBAL_ENABLE); 622f48ad614SDennis Dalessandro 623f48ad614SDennis Dalessandro /* 624f48ad614SDennis Dalessandro * Enable kernel ctxts' receive and receive interrupt. 625f48ad614SDennis Dalessandro * Other ctxts done as user opens and initializes them. 626f48ad614SDennis Dalessandro */ 6272280740fSVishwanathapura, Niranjana for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) { 628f48ad614SDennis Dalessandro rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB; 629f48ad614SDennis Dalessandro rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ? 630f48ad614SDennis Dalessandro HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 631f48ad614SDennis Dalessandro if (!HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, MULTI_PKT_EGR)) 632f48ad614SDennis Dalessandro rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB; 633f48ad614SDennis Dalessandro if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_RHQ_FULL)) 634f48ad614SDennis Dalessandro rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB; 635f48ad614SDennis Dalessandro if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_EGR_FULL)) 636f48ad614SDennis Dalessandro rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB; 637f48ad614SDennis Dalessandro hfi1_rcvctrl(dd, rcvmask, i); 638f48ad614SDennis Dalessandro sc_enable(dd->rcd[i]->sc); 639f48ad614SDennis Dalessandro } 640f48ad614SDennis Dalessandro } 641f48ad614SDennis Dalessandro 642f48ad614SDennis Dalessandro /** 643f48ad614SDennis Dalessandro * create_workqueues - create per port workqueues 644f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 645f48ad614SDennis Dalessandro */ 646f48ad614SDennis Dalessandro static int create_workqueues(struct hfi1_devdata *dd) 647f48ad614SDennis Dalessandro { 648f48ad614SDennis Dalessandro int pidx; 649f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 650f48ad614SDennis Dalessandro 651f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 652f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 653f48ad614SDennis Dalessandro if (!ppd->hfi1_wq) { 654f48ad614SDennis Dalessandro ppd->hfi1_wq = 655f48ad614SDennis Dalessandro alloc_workqueue( 656f48ad614SDennis Dalessandro "hfi%d_%d", 657f48ad614SDennis Dalessandro WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 658dd1ed108SMike Marciniszyn HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES, 659f48ad614SDennis Dalessandro dd->unit, pidx); 660f48ad614SDennis Dalessandro if (!ppd->hfi1_wq) 661f48ad614SDennis Dalessandro goto wq_error; 662f48ad614SDennis Dalessandro } 663f48ad614SDennis Dalessandro } 664f48ad614SDennis Dalessandro return 0; 665f48ad614SDennis Dalessandro wq_error: 666f48ad614SDennis Dalessandro pr_err("alloc_workqueue failed for port %d\n", pidx + 1); 667f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 668f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 669f48ad614SDennis Dalessandro if (ppd->hfi1_wq) { 670f48ad614SDennis Dalessandro destroy_workqueue(ppd->hfi1_wq); 671f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 672f48ad614SDennis Dalessandro } 673f48ad614SDennis Dalessandro } 674f48ad614SDennis Dalessandro return -ENOMEM; 675f48ad614SDennis Dalessandro } 676f48ad614SDennis Dalessandro 677f48ad614SDennis Dalessandro /** 678f48ad614SDennis Dalessandro * hfi1_init - do the actual initialization sequence on the chip 679f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 680f48ad614SDennis Dalessandro * @reinit: re-initializing, so don't allocate new memory 681f48ad614SDennis Dalessandro * 682f48ad614SDennis Dalessandro * Do the actual initialization sequence on the chip. This is done 683f48ad614SDennis Dalessandro * both from the init routine called from the PCI infrastructure, and 684f48ad614SDennis Dalessandro * when we reset the chip, or detect that it was reset internally, 685f48ad614SDennis Dalessandro * or it's administratively re-enabled. 686f48ad614SDennis Dalessandro * 687f48ad614SDennis Dalessandro * Memory allocation here and in called routines is only done in 688f48ad614SDennis Dalessandro * the first case (reinit == 0). We have to be careful, because even 689f48ad614SDennis Dalessandro * without memory allocation, we need to re-write all the chip registers 690f48ad614SDennis Dalessandro * TIDs, etc. after the reset or enable has completed. 691f48ad614SDennis Dalessandro */ 692f48ad614SDennis Dalessandro int hfi1_init(struct hfi1_devdata *dd, int reinit) 693f48ad614SDennis Dalessandro { 694f48ad614SDennis Dalessandro int ret = 0, pidx, lastfail = 0; 695e6f7622dSMichael J. Ruhl unsigned long len; 696e6f7622dSMichael J. Ruhl u16 i; 697f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd; 698f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 699f48ad614SDennis Dalessandro 700f48ad614SDennis Dalessandro /* Set up recv low level handlers */ 701f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] = 702f48ad614SDennis Dalessandro kdeth_process_expected; 703f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] = 704f48ad614SDennis Dalessandro kdeth_process_eager; 705f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib; 706f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] = 707f48ad614SDennis Dalessandro process_receive_error; 708f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] = 709f48ad614SDennis Dalessandro process_receive_bypass; 710f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] = 711f48ad614SDennis Dalessandro process_receive_invalid; 712f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] = 713f48ad614SDennis Dalessandro process_receive_invalid; 714f48ad614SDennis Dalessandro dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] = 715f48ad614SDennis Dalessandro process_receive_invalid; 716f48ad614SDennis Dalessandro dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions; 717f48ad614SDennis Dalessandro 718f48ad614SDennis Dalessandro /* Set up send low level handlers */ 719f48ad614SDennis Dalessandro dd->process_pio_send = hfi1_verbs_send_pio; 720f48ad614SDennis Dalessandro dd->process_dma_send = hfi1_verbs_send_dma; 721f48ad614SDennis Dalessandro dd->pio_inline_send = pio_copy; 72264551edeSVishwanathapura, Niranjana dd->process_vnic_dma_send = hfi1_vnic_send_dma; 723f48ad614SDennis Dalessandro 724f48ad614SDennis Dalessandro if (is_ax(dd)) { 725f48ad614SDennis Dalessandro atomic_set(&dd->drop_packet, DROP_PACKET_ON); 726f48ad614SDennis Dalessandro dd->do_drop = 1; 727f48ad614SDennis Dalessandro } else { 728f48ad614SDennis Dalessandro atomic_set(&dd->drop_packet, DROP_PACKET_OFF); 729f48ad614SDennis Dalessandro dd->do_drop = 0; 730f48ad614SDennis Dalessandro } 731f48ad614SDennis Dalessandro 732f48ad614SDennis Dalessandro /* make sure the link is not "up" */ 733f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 734f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 735f48ad614SDennis Dalessandro ppd->linkup = 0; 736f48ad614SDennis Dalessandro } 737f48ad614SDennis Dalessandro 738f48ad614SDennis Dalessandro if (reinit) 739f48ad614SDennis Dalessandro ret = init_after_reset(dd); 740f48ad614SDennis Dalessandro else 741f48ad614SDennis Dalessandro ret = loadtime_init(dd); 742f48ad614SDennis Dalessandro if (ret) 743f48ad614SDennis Dalessandro goto done; 744f48ad614SDennis Dalessandro 745f48ad614SDennis Dalessandro /* allocate dummy tail memory for all receive contexts */ 746f48ad614SDennis Dalessandro dd->rcvhdrtail_dummy_kvaddr = dma_zalloc_coherent( 747f48ad614SDennis Dalessandro &dd->pcidev->dev, sizeof(u64), 74860368186STymoteusz Kielan &dd->rcvhdrtail_dummy_dma, 749f48ad614SDennis Dalessandro GFP_KERNEL); 750f48ad614SDennis Dalessandro 751f48ad614SDennis Dalessandro if (!dd->rcvhdrtail_dummy_kvaddr) { 752f48ad614SDennis Dalessandro dd_dev_err(dd, "cannot allocate dummy tail memory\n"); 753f48ad614SDennis Dalessandro ret = -ENOMEM; 754f48ad614SDennis Dalessandro goto done; 755f48ad614SDennis Dalessandro } 756f48ad614SDennis Dalessandro 757f48ad614SDennis Dalessandro /* dd->rcd can be NULL if early initialization failed */ 7582280740fSVishwanathapura, Niranjana for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) { 759f48ad614SDennis Dalessandro /* 760f48ad614SDennis Dalessandro * Set up the (kernel) rcvhdr queue and egr TIDs. If doing 761f48ad614SDennis Dalessandro * re-init, the simplest way to handle this is to free 762f48ad614SDennis Dalessandro * existing, and re-allocate. 763f48ad614SDennis Dalessandro * Need to re-create rest of ctxt 0 ctxtdata as well. 764f48ad614SDennis Dalessandro */ 765f48ad614SDennis Dalessandro rcd = dd->rcd[i]; 766f48ad614SDennis Dalessandro if (!rcd) 767f48ad614SDennis Dalessandro continue; 768f48ad614SDennis Dalessandro 769f48ad614SDennis Dalessandro rcd->do_interrupt = &handle_receive_interrupt; 770f48ad614SDennis Dalessandro 771f48ad614SDennis Dalessandro lastfail = hfi1_create_rcvhdrq(dd, rcd); 772f48ad614SDennis Dalessandro if (!lastfail) 773f48ad614SDennis Dalessandro lastfail = hfi1_setup_eagerbufs(rcd); 774f48ad614SDennis Dalessandro if (lastfail) { 775f48ad614SDennis Dalessandro dd_dev_err(dd, 776f48ad614SDennis Dalessandro "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n"); 777f48ad614SDennis Dalessandro ret = lastfail; 778f48ad614SDennis Dalessandro } 779f48ad614SDennis Dalessandro } 780f48ad614SDennis Dalessandro 781f48ad614SDennis Dalessandro /* Allocate enough memory for user event notification. */ 782f48ad614SDennis Dalessandro len = PAGE_ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS * 783f48ad614SDennis Dalessandro sizeof(*dd->events)); 784f48ad614SDennis Dalessandro dd->events = vmalloc_user(len); 785f48ad614SDennis Dalessandro if (!dd->events) 786f48ad614SDennis Dalessandro dd_dev_err(dd, "Failed to allocate user events page\n"); 787f48ad614SDennis Dalessandro /* 788f48ad614SDennis Dalessandro * Allocate a page for device and port status. 789f48ad614SDennis Dalessandro * Page will be shared amongst all user processes. 790f48ad614SDennis Dalessandro */ 791f48ad614SDennis Dalessandro dd->status = vmalloc_user(PAGE_SIZE); 792f48ad614SDennis Dalessandro if (!dd->status) 793f48ad614SDennis Dalessandro dd_dev_err(dd, "Failed to allocate dev status page\n"); 794f48ad614SDennis Dalessandro else 795f48ad614SDennis Dalessandro dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) - 796f48ad614SDennis Dalessandro sizeof(dd->status->freezemsg)); 797f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 798f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 799f48ad614SDennis Dalessandro if (dd->status) 800f48ad614SDennis Dalessandro /* Currently, we only have one port */ 801f48ad614SDennis Dalessandro ppd->statusp = &dd->status->port; 802f48ad614SDennis Dalessandro 803f48ad614SDennis Dalessandro set_mtu(ppd); 804f48ad614SDennis Dalessandro } 805f48ad614SDennis Dalessandro 806f48ad614SDennis Dalessandro /* enable chip even if we have an error, so we can debug cause */ 807f48ad614SDennis Dalessandro enable_chip(dd); 808f48ad614SDennis Dalessandro 809f48ad614SDennis Dalessandro done: 810f48ad614SDennis Dalessandro /* 811f48ad614SDennis Dalessandro * Set status even if port serdes is not initialized 812f48ad614SDennis Dalessandro * so that diags will work. 813f48ad614SDennis Dalessandro */ 814f48ad614SDennis Dalessandro if (dd->status) 815f48ad614SDennis Dalessandro dd->status->dev |= HFI1_STATUS_CHIP_PRESENT | 816f48ad614SDennis Dalessandro HFI1_STATUS_INITTED; 817f48ad614SDennis Dalessandro if (!ret) { 818f48ad614SDennis Dalessandro /* enable all interrupts from the chip */ 819f48ad614SDennis Dalessandro set_intr_state(dd, 1); 820f48ad614SDennis Dalessandro 821f48ad614SDennis Dalessandro /* chip is OK for user apps; mark it as initialized */ 822f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 823f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 824f48ad614SDennis Dalessandro 825f48ad614SDennis Dalessandro /* 826f48ad614SDennis Dalessandro * start the serdes - must be after interrupts are 827f48ad614SDennis Dalessandro * enabled so we are notified when the link goes up 828f48ad614SDennis Dalessandro */ 829f48ad614SDennis Dalessandro lastfail = bringup_serdes(ppd); 830f48ad614SDennis Dalessandro if (lastfail) 831f48ad614SDennis Dalessandro dd_dev_info(dd, 832f48ad614SDennis Dalessandro "Failed to bring up port %u\n", 833f48ad614SDennis Dalessandro ppd->port); 834f48ad614SDennis Dalessandro 835f48ad614SDennis Dalessandro /* 836f48ad614SDennis Dalessandro * Set status even if port serdes is not initialized 837f48ad614SDennis Dalessandro * so that diags will work. 838f48ad614SDennis Dalessandro */ 839f48ad614SDennis Dalessandro if (ppd->statusp) 840f48ad614SDennis Dalessandro *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT | 841f48ad614SDennis Dalessandro HFI1_STATUS_INITTED; 842f48ad614SDennis Dalessandro if (!ppd->link_speed_enabled) 843f48ad614SDennis Dalessandro continue; 844f48ad614SDennis Dalessandro } 845f48ad614SDennis Dalessandro } 846f48ad614SDennis Dalessandro 847f48ad614SDennis Dalessandro /* if ret is non-zero, we probably should do some cleanup here... */ 848f48ad614SDennis Dalessandro return ret; 849f48ad614SDennis Dalessandro } 850f48ad614SDennis Dalessandro 851f48ad614SDennis Dalessandro static inline struct hfi1_devdata *__hfi1_lookup(int unit) 852f48ad614SDennis Dalessandro { 853f48ad614SDennis Dalessandro return idr_find(&hfi1_unit_table, unit); 854f48ad614SDennis Dalessandro } 855f48ad614SDennis Dalessandro 856f48ad614SDennis Dalessandro struct hfi1_devdata *hfi1_lookup(int unit) 857f48ad614SDennis Dalessandro { 858f48ad614SDennis Dalessandro struct hfi1_devdata *dd; 859f48ad614SDennis Dalessandro unsigned long flags; 860f48ad614SDennis Dalessandro 861f48ad614SDennis Dalessandro spin_lock_irqsave(&hfi1_devs_lock, flags); 862f48ad614SDennis Dalessandro dd = __hfi1_lookup(unit); 863f48ad614SDennis Dalessandro spin_unlock_irqrestore(&hfi1_devs_lock, flags); 864f48ad614SDennis Dalessandro 865f48ad614SDennis Dalessandro return dd; 866f48ad614SDennis Dalessandro } 867f48ad614SDennis Dalessandro 868f48ad614SDennis Dalessandro /* 869f48ad614SDennis Dalessandro * Stop the timers during unit shutdown, or after an error late 870f48ad614SDennis Dalessandro * in initialization. 871f48ad614SDennis Dalessandro */ 872f48ad614SDennis Dalessandro static void stop_timers(struct hfi1_devdata *dd) 873f48ad614SDennis Dalessandro { 874f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 875f48ad614SDennis Dalessandro int pidx; 876f48ad614SDennis Dalessandro 877f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 878f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 879f48ad614SDennis Dalessandro if (ppd->led_override_timer.data) { 880f48ad614SDennis Dalessandro del_timer_sync(&ppd->led_override_timer); 881f48ad614SDennis Dalessandro atomic_set(&ppd->led_override_timer_active, 0); 882f48ad614SDennis Dalessandro } 883f48ad614SDennis Dalessandro } 884f48ad614SDennis Dalessandro } 885f48ad614SDennis Dalessandro 886f48ad614SDennis Dalessandro /** 887f48ad614SDennis Dalessandro * shutdown_device - shut down a device 888f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 889f48ad614SDennis Dalessandro * 890f48ad614SDennis Dalessandro * This is called to make the device quiet when we are about to 891f48ad614SDennis Dalessandro * unload the driver, and also when the device is administratively 892f48ad614SDennis Dalessandro * disabled. It does not free any data structures. 893f48ad614SDennis Dalessandro * Everything it does has to be setup again by hfi1_init(dd, 1) 894f48ad614SDennis Dalessandro */ 895f48ad614SDennis Dalessandro static void shutdown_device(struct hfi1_devdata *dd) 896f48ad614SDennis Dalessandro { 897f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 898f48ad614SDennis Dalessandro unsigned pidx; 899f48ad614SDennis Dalessandro int i; 900f48ad614SDennis Dalessandro 901f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 902f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 903f48ad614SDennis Dalessandro 904f48ad614SDennis Dalessandro ppd->linkup = 0; 905f48ad614SDennis Dalessandro if (ppd->statusp) 906f48ad614SDennis Dalessandro *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 907f48ad614SDennis Dalessandro HFI1_STATUS_IB_READY); 908f48ad614SDennis Dalessandro } 909f48ad614SDennis Dalessandro dd->flags &= ~HFI1_INITTED; 910f48ad614SDennis Dalessandro 911f48ad614SDennis Dalessandro /* mask interrupts, but not errors */ 912f48ad614SDennis Dalessandro set_intr_state(dd, 0); 913f48ad614SDennis Dalessandro 914f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 915f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 916f48ad614SDennis Dalessandro for (i = 0; i < dd->num_rcv_contexts; i++) 917f48ad614SDennis Dalessandro hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS | 918f48ad614SDennis Dalessandro HFI1_RCVCTRL_CTXT_DIS | 919f48ad614SDennis Dalessandro HFI1_RCVCTRL_INTRAVAIL_DIS | 920f48ad614SDennis Dalessandro HFI1_RCVCTRL_PKEY_DIS | 921f48ad614SDennis Dalessandro HFI1_RCVCTRL_ONE_PKT_EGR_DIS, i); 922f48ad614SDennis Dalessandro /* 923f48ad614SDennis Dalessandro * Gracefully stop all sends allowing any in progress to 924f48ad614SDennis Dalessandro * trickle out first. 925f48ad614SDennis Dalessandro */ 926f48ad614SDennis Dalessandro for (i = 0; i < dd->num_send_contexts; i++) 927f48ad614SDennis Dalessandro sc_flush(dd->send_contexts[i].sc); 928f48ad614SDennis Dalessandro } 929f48ad614SDennis Dalessandro 930f48ad614SDennis Dalessandro /* 931f48ad614SDennis Dalessandro * Enough for anything that's going to trickle out to have actually 932f48ad614SDennis Dalessandro * done so. 933f48ad614SDennis Dalessandro */ 934f48ad614SDennis Dalessandro udelay(20); 935f48ad614SDennis Dalessandro 936f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 937f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 938f48ad614SDennis Dalessandro 939f48ad614SDennis Dalessandro /* disable all contexts */ 940f48ad614SDennis Dalessandro for (i = 0; i < dd->num_send_contexts; i++) 941f48ad614SDennis Dalessandro sc_disable(dd->send_contexts[i].sc); 942f48ad614SDennis Dalessandro /* disable the send device */ 943f48ad614SDennis Dalessandro pio_send_control(dd, PSC_GLOBAL_DISABLE); 944f48ad614SDennis Dalessandro 945f48ad614SDennis Dalessandro shutdown_led_override(ppd); 946f48ad614SDennis Dalessandro 947f48ad614SDennis Dalessandro /* 948f48ad614SDennis Dalessandro * Clear SerdesEnable. 949f48ad614SDennis Dalessandro * We can't count on interrupts since we are stopping. 950f48ad614SDennis Dalessandro */ 951f48ad614SDennis Dalessandro hfi1_quiet_serdes(ppd); 952f48ad614SDennis Dalessandro 953f48ad614SDennis Dalessandro if (ppd->hfi1_wq) { 954f48ad614SDennis Dalessandro destroy_workqueue(ppd->hfi1_wq); 955f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 956f48ad614SDennis Dalessandro } 957f48ad614SDennis Dalessandro } 958f48ad614SDennis Dalessandro sdma_exit(dd); 959f48ad614SDennis Dalessandro } 960f48ad614SDennis Dalessandro 961f48ad614SDennis Dalessandro /** 962f48ad614SDennis Dalessandro * hfi1_free_ctxtdata - free a context's allocated data 963f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 964f48ad614SDennis Dalessandro * @rcd: the ctxtdata structure 965f48ad614SDennis Dalessandro * 966f48ad614SDennis Dalessandro * free up any allocated data for a context 967f48ad614SDennis Dalessandro * It should never change any chip state, or global driver state. 968f48ad614SDennis Dalessandro */ 969f48ad614SDennis Dalessandro void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 970f48ad614SDennis Dalessandro { 971f683c80cSMichael J. Ruhl u32 e; 972f48ad614SDennis Dalessandro 973f48ad614SDennis Dalessandro if (!rcd) 974f48ad614SDennis Dalessandro return; 975f48ad614SDennis Dalessandro 976f48ad614SDennis Dalessandro if (rcd->rcvhdrq) { 977f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size, 97860368186STymoteusz Kielan rcd->rcvhdrq, rcd->rcvhdrq_dma); 979f48ad614SDennis Dalessandro rcd->rcvhdrq = NULL; 980f48ad614SDennis Dalessandro if (rcd->rcvhdrtail_kvaddr) { 981f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, 982f48ad614SDennis Dalessandro (void *)rcd->rcvhdrtail_kvaddr, 98360368186STymoteusz Kielan rcd->rcvhdrqtailaddr_dma); 984f48ad614SDennis Dalessandro rcd->rcvhdrtail_kvaddr = NULL; 985f48ad614SDennis Dalessandro } 986f48ad614SDennis Dalessandro } 987f48ad614SDennis Dalessandro 988f48ad614SDennis Dalessandro /* all the RcvArray entries should have been cleared by now */ 989f48ad614SDennis Dalessandro kfree(rcd->egrbufs.rcvtids); 990f683c80cSMichael J. Ruhl rcd->egrbufs.rcvtids = NULL; 991f48ad614SDennis Dalessandro 992f48ad614SDennis Dalessandro for (e = 0; e < rcd->egrbufs.alloced; e++) { 99360368186STymoteusz Kielan if (rcd->egrbufs.buffers[e].dma) 994f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, 995f48ad614SDennis Dalessandro rcd->egrbufs.buffers[e].len, 996f48ad614SDennis Dalessandro rcd->egrbufs.buffers[e].addr, 99760368186STymoteusz Kielan rcd->egrbufs.buffers[e].dma); 998f48ad614SDennis Dalessandro } 999f48ad614SDennis Dalessandro kfree(rcd->egrbufs.buffers); 1000f683c80cSMichael J. Ruhl rcd->egrbufs.alloced = 0; 1001f683c80cSMichael J. Ruhl rcd->egrbufs.buffers = NULL; 1002f48ad614SDennis Dalessandro 1003f48ad614SDennis Dalessandro sc_free(rcd->sc); 1004f683c80cSMichael J. Ruhl rcd->sc = NULL; 1005f683c80cSMichael J. Ruhl 1006f48ad614SDennis Dalessandro vfree(rcd->subctxt_uregbase); 1007f48ad614SDennis Dalessandro vfree(rcd->subctxt_rcvegrbuf); 1008f48ad614SDennis Dalessandro vfree(rcd->subctxt_rcvhdr_base); 1009f48ad614SDennis Dalessandro kfree(rcd->opstats); 1010f683c80cSMichael J. Ruhl 1011f683c80cSMichael J. Ruhl rcd->subctxt_uregbase = NULL; 1012f683c80cSMichael J. Ruhl rcd->subctxt_rcvegrbuf = NULL; 1013f683c80cSMichael J. Ruhl rcd->subctxt_rcvhdr_base = NULL; 1014f683c80cSMichael J. Ruhl rcd->opstats = NULL; 1015f48ad614SDennis Dalessandro } 1016f48ad614SDennis Dalessandro 1017f48ad614SDennis Dalessandro /* 1018f48ad614SDennis Dalessandro * Release our hold on the shared asic data. If we are the last one, 1019dba715f0SDean Luick * return the structure to be finalized outside the lock. Must be 1020dba715f0SDean Luick * holding hfi1_devs_lock. 1021f48ad614SDennis Dalessandro */ 1022dba715f0SDean Luick static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd) 1023f48ad614SDennis Dalessandro { 1024dba715f0SDean Luick struct hfi1_asic_data *ad; 1025f48ad614SDennis Dalessandro int other; 1026f48ad614SDennis Dalessandro 1027f48ad614SDennis Dalessandro if (!dd->asic_data) 1028dba715f0SDean Luick return NULL; 1029f48ad614SDennis Dalessandro dd->asic_data->dds[dd->hfi1_id] = NULL; 1030f48ad614SDennis Dalessandro other = dd->hfi1_id ? 0 : 1; 1031dba715f0SDean Luick ad = dd->asic_data; 1032f48ad614SDennis Dalessandro dd->asic_data = NULL; 1033dba715f0SDean Luick /* return NULL if the other dd still has a link */ 1034dba715f0SDean Luick return ad->dds[other] ? NULL : ad; 1035dba715f0SDean Luick } 1036dba715f0SDean Luick 1037dba715f0SDean Luick static void finalize_asic_data(struct hfi1_devdata *dd, 1038dba715f0SDean Luick struct hfi1_asic_data *ad) 1039dba715f0SDean Luick { 1040dba715f0SDean Luick clean_up_i2c(dd, ad); 1041dba715f0SDean Luick kfree(ad); 1042f48ad614SDennis Dalessandro } 1043f48ad614SDennis Dalessandro 1044f48ad614SDennis Dalessandro static void __hfi1_free_devdata(struct kobject *kobj) 1045f48ad614SDennis Dalessandro { 1046f48ad614SDennis Dalessandro struct hfi1_devdata *dd = 1047f48ad614SDennis Dalessandro container_of(kobj, struct hfi1_devdata, kobj); 1048dba715f0SDean Luick struct hfi1_asic_data *ad; 1049f48ad614SDennis Dalessandro unsigned long flags; 1050f48ad614SDennis Dalessandro 1051f48ad614SDennis Dalessandro spin_lock_irqsave(&hfi1_devs_lock, flags); 1052f48ad614SDennis Dalessandro idr_remove(&hfi1_unit_table, dd->unit); 1053f48ad614SDennis Dalessandro list_del(&dd->list); 1054dba715f0SDean Luick ad = release_asic_data(dd); 1055f48ad614SDennis Dalessandro spin_unlock_irqrestore(&hfi1_devs_lock, flags); 1056dba715f0SDean Luick if (ad) 1057dba715f0SDean Luick finalize_asic_data(dd, ad); 1058f48ad614SDennis Dalessandro free_platform_config(dd); 1059f48ad614SDennis Dalessandro rcu_barrier(); /* wait for rcu callbacks to complete */ 1060f48ad614SDennis Dalessandro free_percpu(dd->int_counter); 1061f48ad614SDennis Dalessandro free_percpu(dd->rcv_limit); 1062f48ad614SDennis Dalessandro free_percpu(dd->send_schedule); 1063f48ad614SDennis Dalessandro rvt_dealloc_device(&dd->verbs_dev.rdi); 1064f48ad614SDennis Dalessandro } 1065f48ad614SDennis Dalessandro 1066f48ad614SDennis Dalessandro static struct kobj_type hfi1_devdata_type = { 1067f48ad614SDennis Dalessandro .release = __hfi1_free_devdata, 1068f48ad614SDennis Dalessandro }; 1069f48ad614SDennis Dalessandro 1070f48ad614SDennis Dalessandro void hfi1_free_devdata(struct hfi1_devdata *dd) 1071f48ad614SDennis Dalessandro { 1072f48ad614SDennis Dalessandro kobject_put(&dd->kobj); 1073f48ad614SDennis Dalessandro } 1074f48ad614SDennis Dalessandro 1075f48ad614SDennis Dalessandro /* 1076f48ad614SDennis Dalessandro * Allocate our primary per-unit data structure. Must be done via verbs 1077f48ad614SDennis Dalessandro * allocator, because the verbs cleanup process both does cleanup and 1078f48ad614SDennis Dalessandro * free of the data structure. 1079f48ad614SDennis Dalessandro * "extra" is for chip-specific data. 1080f48ad614SDennis Dalessandro * 1081f48ad614SDennis Dalessandro * Use the idr mechanism to get a unit number for this unit. 1082f48ad614SDennis Dalessandro */ 1083f48ad614SDennis Dalessandro struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra) 1084f48ad614SDennis Dalessandro { 1085f48ad614SDennis Dalessandro unsigned long flags; 1086f48ad614SDennis Dalessandro struct hfi1_devdata *dd; 1087f48ad614SDennis Dalessandro int ret, nports; 1088f48ad614SDennis Dalessandro 1089f48ad614SDennis Dalessandro /* extra is * number of ports */ 1090f48ad614SDennis Dalessandro nports = extra / sizeof(struct hfi1_pportdata); 1091f48ad614SDennis Dalessandro 1092f48ad614SDennis Dalessandro dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra, 1093f48ad614SDennis Dalessandro nports); 1094f48ad614SDennis Dalessandro if (!dd) 1095f48ad614SDennis Dalessandro return ERR_PTR(-ENOMEM); 1096f48ad614SDennis Dalessandro dd->num_pports = nports; 1097f48ad614SDennis Dalessandro dd->pport = (struct hfi1_pportdata *)(dd + 1); 1098f48ad614SDennis Dalessandro 1099f48ad614SDennis Dalessandro INIT_LIST_HEAD(&dd->list); 1100f48ad614SDennis Dalessandro idr_preload(GFP_KERNEL); 1101f48ad614SDennis Dalessandro spin_lock_irqsave(&hfi1_devs_lock, flags); 1102f48ad614SDennis Dalessandro 1103f48ad614SDennis Dalessandro ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT); 1104f48ad614SDennis Dalessandro if (ret >= 0) { 1105f48ad614SDennis Dalessandro dd->unit = ret; 1106f48ad614SDennis Dalessandro list_add(&dd->list, &hfi1_dev_list); 1107f48ad614SDennis Dalessandro } 1108f48ad614SDennis Dalessandro 1109f48ad614SDennis Dalessandro spin_unlock_irqrestore(&hfi1_devs_lock, flags); 1110f48ad614SDennis Dalessandro idr_preload_end(); 1111f48ad614SDennis Dalessandro 1112f48ad614SDennis Dalessandro if (ret < 0) { 1113f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 1114f48ad614SDennis Dalessandro "Could not allocate unit ID: error %d\n", -ret); 1115f48ad614SDennis Dalessandro goto bail; 1116f48ad614SDennis Dalessandro } 1117f48ad614SDennis Dalessandro /* 1118f48ad614SDennis Dalessandro * Initialize all locks for the device. This needs to be as early as 1119f48ad614SDennis Dalessandro * possible so locks are usable. 1120f48ad614SDennis Dalessandro */ 1121f48ad614SDennis Dalessandro spin_lock_init(&dd->sc_lock); 1122f48ad614SDennis Dalessandro spin_lock_init(&dd->sendctrl_lock); 1123f48ad614SDennis Dalessandro spin_lock_init(&dd->rcvctrl_lock); 1124f48ad614SDennis Dalessandro spin_lock_init(&dd->uctxt_lock); 1125f48ad614SDennis Dalessandro spin_lock_init(&dd->hfi1_diag_trans_lock); 1126f48ad614SDennis Dalessandro spin_lock_init(&dd->sc_init_lock); 1127f48ad614SDennis Dalessandro spin_lock_init(&dd->dc8051_memlock); 1128f48ad614SDennis Dalessandro seqlock_init(&dd->sc2vl_lock); 1129f48ad614SDennis Dalessandro spin_lock_init(&dd->sde_map_lock); 1130f48ad614SDennis Dalessandro spin_lock_init(&dd->pio_map_lock); 113122546b74STadeusz Struk mutex_init(&dd->dc8051_lock); 1132f48ad614SDennis Dalessandro init_waitqueue_head(&dd->event_queue); 1133f48ad614SDennis Dalessandro 1134f48ad614SDennis Dalessandro dd->int_counter = alloc_percpu(u64); 1135f48ad614SDennis Dalessandro if (!dd->int_counter) { 1136f48ad614SDennis Dalessandro ret = -ENOMEM; 1137f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 1138f48ad614SDennis Dalessandro "Could not allocate per-cpu int_counter\n"); 1139f48ad614SDennis Dalessandro goto bail; 1140f48ad614SDennis Dalessandro } 1141f48ad614SDennis Dalessandro 1142f48ad614SDennis Dalessandro dd->rcv_limit = alloc_percpu(u64); 1143f48ad614SDennis Dalessandro if (!dd->rcv_limit) { 1144f48ad614SDennis Dalessandro ret = -ENOMEM; 1145f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 1146f48ad614SDennis Dalessandro "Could not allocate per-cpu rcv_limit\n"); 1147f48ad614SDennis Dalessandro goto bail; 1148f48ad614SDennis Dalessandro } 1149f48ad614SDennis Dalessandro 1150f48ad614SDennis Dalessandro dd->send_schedule = alloc_percpu(u64); 1151f48ad614SDennis Dalessandro if (!dd->send_schedule) { 1152f48ad614SDennis Dalessandro ret = -ENOMEM; 1153f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, 1154f48ad614SDennis Dalessandro "Could not allocate per-cpu int_counter\n"); 1155f48ad614SDennis Dalessandro goto bail; 1156f48ad614SDennis Dalessandro } 1157f48ad614SDennis Dalessandro 1158f48ad614SDennis Dalessandro if (!hfi1_cpulist_count) { 1159f48ad614SDennis Dalessandro u32 count = num_online_cpus(); 1160f48ad614SDennis Dalessandro 1161f48ad614SDennis Dalessandro hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long), 1162f48ad614SDennis Dalessandro GFP_KERNEL); 1163f48ad614SDennis Dalessandro if (hfi1_cpulist) 1164f48ad614SDennis Dalessandro hfi1_cpulist_count = count; 1165f48ad614SDennis Dalessandro else 1166f48ad614SDennis Dalessandro hfi1_early_err( 1167f48ad614SDennis Dalessandro &pdev->dev, 1168f48ad614SDennis Dalessandro "Could not alloc cpulist info, cpu affinity might be wrong\n"); 1169f48ad614SDennis Dalessandro } 1170f48ad614SDennis Dalessandro kobject_init(&dd->kobj, &hfi1_devdata_type); 1171f48ad614SDennis Dalessandro return dd; 1172f48ad614SDennis Dalessandro 1173f48ad614SDennis Dalessandro bail: 1174f48ad614SDennis Dalessandro if (!list_empty(&dd->list)) 1175f48ad614SDennis Dalessandro list_del_init(&dd->list); 1176f48ad614SDennis Dalessandro rvt_dealloc_device(&dd->verbs_dev.rdi); 1177f48ad614SDennis Dalessandro return ERR_PTR(ret); 1178f48ad614SDennis Dalessandro } 1179f48ad614SDennis Dalessandro 1180f48ad614SDennis Dalessandro /* 1181f48ad614SDennis Dalessandro * Called from freeze mode handlers, and from PCI error 1182f48ad614SDennis Dalessandro * reporting code. Should be paranoid about state of 1183f48ad614SDennis Dalessandro * system and data structures. 1184f48ad614SDennis Dalessandro */ 1185f48ad614SDennis Dalessandro void hfi1_disable_after_error(struct hfi1_devdata *dd) 1186f48ad614SDennis Dalessandro { 1187f48ad614SDennis Dalessandro if (dd->flags & HFI1_INITTED) { 1188f48ad614SDennis Dalessandro u32 pidx; 1189f48ad614SDennis Dalessandro 1190f48ad614SDennis Dalessandro dd->flags &= ~HFI1_INITTED; 1191f48ad614SDennis Dalessandro if (dd->pport) 1192f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1193f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 1194f48ad614SDennis Dalessandro 1195f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1196f48ad614SDennis Dalessandro if (dd->flags & HFI1_PRESENT) 1197f48ad614SDennis Dalessandro set_link_state(ppd, HLS_DN_DISABLE); 1198f48ad614SDennis Dalessandro 1199f48ad614SDennis Dalessandro if (ppd->statusp) 1200f48ad614SDennis Dalessandro *ppd->statusp &= ~HFI1_STATUS_IB_READY; 1201f48ad614SDennis Dalessandro } 1202f48ad614SDennis Dalessandro } 1203f48ad614SDennis Dalessandro 1204f48ad614SDennis Dalessandro /* 1205f48ad614SDennis Dalessandro * Mark as having had an error for driver, and also 1206f48ad614SDennis Dalessandro * for /sys and status word mapped to user programs. 1207f48ad614SDennis Dalessandro * This marks unit as not usable, until reset. 1208f48ad614SDennis Dalessandro */ 1209f48ad614SDennis Dalessandro if (dd->status) 1210f48ad614SDennis Dalessandro dd->status->dev |= HFI1_STATUS_HWERROR; 1211f48ad614SDennis Dalessandro } 1212f48ad614SDennis Dalessandro 1213f48ad614SDennis Dalessandro static void remove_one(struct pci_dev *); 1214f48ad614SDennis Dalessandro static int init_one(struct pci_dev *, const struct pci_device_id *); 1215f48ad614SDennis Dalessandro 1216f48ad614SDennis Dalessandro #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: " 1217f48ad614SDennis Dalessandro #define PFX DRIVER_NAME ": " 1218f48ad614SDennis Dalessandro 1219d6373019SSebastian Sanchez const struct pci_device_id hfi1_pci_tbl[] = { 1220f48ad614SDennis Dalessandro { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) }, 1221f48ad614SDennis Dalessandro { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) }, 1222f48ad614SDennis Dalessandro { 0, } 1223f48ad614SDennis Dalessandro }; 1224f48ad614SDennis Dalessandro 1225f48ad614SDennis Dalessandro MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl); 1226f48ad614SDennis Dalessandro 1227f48ad614SDennis Dalessandro static struct pci_driver hfi1_pci_driver = { 1228f48ad614SDennis Dalessandro .name = DRIVER_NAME, 1229f48ad614SDennis Dalessandro .probe = init_one, 1230f48ad614SDennis Dalessandro .remove = remove_one, 1231f48ad614SDennis Dalessandro .id_table = hfi1_pci_tbl, 1232f48ad614SDennis Dalessandro .err_handler = &hfi1_pci_err_handler, 1233f48ad614SDennis Dalessandro }; 1234f48ad614SDennis Dalessandro 1235f48ad614SDennis Dalessandro static void __init compute_krcvqs(void) 1236f48ad614SDennis Dalessandro { 1237f48ad614SDennis Dalessandro int i; 1238f48ad614SDennis Dalessandro 1239f48ad614SDennis Dalessandro for (i = 0; i < krcvqsset; i++) 1240f48ad614SDennis Dalessandro n_krcvqs += krcvqs[i]; 1241f48ad614SDennis Dalessandro } 1242f48ad614SDennis Dalessandro 1243f48ad614SDennis Dalessandro /* 1244f48ad614SDennis Dalessandro * Do all the generic driver unit- and chip-independent memory 1245f48ad614SDennis Dalessandro * allocation and initialization. 1246f48ad614SDennis Dalessandro */ 1247f48ad614SDennis Dalessandro static int __init hfi1_mod_init(void) 1248f48ad614SDennis Dalessandro { 1249f48ad614SDennis Dalessandro int ret; 1250f48ad614SDennis Dalessandro 1251f48ad614SDennis Dalessandro ret = dev_init(); 1252f48ad614SDennis Dalessandro if (ret) 1253f48ad614SDennis Dalessandro goto bail; 1254f48ad614SDennis Dalessandro 1255d6373019SSebastian Sanchez ret = node_affinity_init(); 1256d6373019SSebastian Sanchez if (ret) 1257d6373019SSebastian Sanchez goto bail; 12584197344bSDennis Dalessandro 1259f48ad614SDennis Dalessandro /* validate max MTU before any devices start */ 1260f48ad614SDennis Dalessandro if (!valid_opa_max_mtu(hfi1_max_mtu)) { 1261f48ad614SDennis Dalessandro pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n", 1262f48ad614SDennis Dalessandro hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU); 1263f48ad614SDennis Dalessandro hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU; 1264f48ad614SDennis Dalessandro } 1265f48ad614SDennis Dalessandro /* valid CUs run from 1-128 in powers of 2 */ 1266f48ad614SDennis Dalessandro if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu)) 1267f48ad614SDennis Dalessandro hfi1_cu = 1; 1268f48ad614SDennis Dalessandro /* valid credit return threshold is 0-100, variable is unsigned */ 1269f48ad614SDennis Dalessandro if (user_credit_return_threshold > 100) 1270f48ad614SDennis Dalessandro user_credit_return_threshold = 100; 1271f48ad614SDennis Dalessandro 1272f48ad614SDennis Dalessandro compute_krcvqs(); 1273f48ad614SDennis Dalessandro /* 1274f48ad614SDennis Dalessandro * sanitize receive interrupt count, time must wait until after 1275f48ad614SDennis Dalessandro * the hardware type is known 1276f48ad614SDennis Dalessandro */ 1277f48ad614SDennis Dalessandro if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK) 1278f48ad614SDennis Dalessandro rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK; 1279f48ad614SDennis Dalessandro /* reject invalid combinations */ 1280f48ad614SDennis Dalessandro if (rcv_intr_count == 0 && rcv_intr_timeout == 0) { 1281f48ad614SDennis Dalessandro pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n"); 1282f48ad614SDennis Dalessandro rcv_intr_count = 1; 1283f48ad614SDennis Dalessandro } 1284f48ad614SDennis Dalessandro if (rcv_intr_count > 1 && rcv_intr_timeout == 0) { 1285f48ad614SDennis Dalessandro /* 1286f48ad614SDennis Dalessandro * Avoid indefinite packet delivery by requiring a timeout 1287f48ad614SDennis Dalessandro * if count is > 1. 1288f48ad614SDennis Dalessandro */ 1289f48ad614SDennis Dalessandro pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n"); 1290f48ad614SDennis Dalessandro rcv_intr_timeout = 1; 1291f48ad614SDennis Dalessandro } 1292f48ad614SDennis Dalessandro if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) { 1293f48ad614SDennis Dalessandro /* 1294f48ad614SDennis Dalessandro * The dynamic algorithm expects a non-zero timeout 1295f48ad614SDennis Dalessandro * and a count > 1. 1296f48ad614SDennis Dalessandro */ 1297f48ad614SDennis Dalessandro pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n"); 1298f48ad614SDennis Dalessandro rcv_intr_dynamic = 0; 1299f48ad614SDennis Dalessandro } 1300f48ad614SDennis Dalessandro 1301f48ad614SDennis Dalessandro /* sanitize link CRC options */ 1302f48ad614SDennis Dalessandro link_crc_mask &= SUPPORTED_CRCS; 1303f48ad614SDennis Dalessandro 1304f48ad614SDennis Dalessandro /* 1305f48ad614SDennis Dalessandro * These must be called before the driver is registered with 1306f48ad614SDennis Dalessandro * the PCI subsystem. 1307f48ad614SDennis Dalessandro */ 1308f48ad614SDennis Dalessandro idr_init(&hfi1_unit_table); 1309f48ad614SDennis Dalessandro 1310f48ad614SDennis Dalessandro hfi1_dbg_init(); 1311f48ad614SDennis Dalessandro ret = hfi1_wss_init(); 1312f48ad614SDennis Dalessandro if (ret < 0) 1313f48ad614SDennis Dalessandro goto bail_wss; 1314f48ad614SDennis Dalessandro ret = pci_register_driver(&hfi1_pci_driver); 1315f48ad614SDennis Dalessandro if (ret < 0) { 1316f48ad614SDennis Dalessandro pr_err("Unable to register driver: error %d\n", -ret); 1317f48ad614SDennis Dalessandro goto bail_dev; 1318f48ad614SDennis Dalessandro } 1319f48ad614SDennis Dalessandro goto bail; /* all OK */ 1320f48ad614SDennis Dalessandro 1321f48ad614SDennis Dalessandro bail_dev: 1322f48ad614SDennis Dalessandro hfi1_wss_exit(); 1323f48ad614SDennis Dalessandro bail_wss: 1324f48ad614SDennis Dalessandro hfi1_dbg_exit(); 1325f48ad614SDennis Dalessandro idr_destroy(&hfi1_unit_table); 1326f48ad614SDennis Dalessandro dev_cleanup(); 1327f48ad614SDennis Dalessandro bail: 1328f48ad614SDennis Dalessandro return ret; 1329f48ad614SDennis Dalessandro } 1330f48ad614SDennis Dalessandro 1331f48ad614SDennis Dalessandro module_init(hfi1_mod_init); 1332f48ad614SDennis Dalessandro 1333f48ad614SDennis Dalessandro /* 1334f48ad614SDennis Dalessandro * Do the non-unit driver cleanup, memory free, etc. at unload. 1335f48ad614SDennis Dalessandro */ 1336f48ad614SDennis Dalessandro static void __exit hfi1_mod_cleanup(void) 1337f48ad614SDennis Dalessandro { 1338f48ad614SDennis Dalessandro pci_unregister_driver(&hfi1_pci_driver); 13394197344bSDennis Dalessandro node_affinity_destroy(); 1340f48ad614SDennis Dalessandro hfi1_wss_exit(); 1341f48ad614SDennis Dalessandro hfi1_dbg_exit(); 1342f48ad614SDennis Dalessandro hfi1_cpulist_count = 0; 1343f48ad614SDennis Dalessandro kfree(hfi1_cpulist); 1344f48ad614SDennis Dalessandro 1345f48ad614SDennis Dalessandro idr_destroy(&hfi1_unit_table); 1346f48ad614SDennis Dalessandro dispose_firmware(); /* asymmetric with obtain_firmware() */ 1347f48ad614SDennis Dalessandro dev_cleanup(); 1348f48ad614SDennis Dalessandro } 1349f48ad614SDennis Dalessandro 1350f48ad614SDennis Dalessandro module_exit(hfi1_mod_cleanup); 1351f48ad614SDennis Dalessandro 1352f48ad614SDennis Dalessandro /* this can only be called after a successful initialization */ 1353f48ad614SDennis Dalessandro static void cleanup_device_data(struct hfi1_devdata *dd) 1354f48ad614SDennis Dalessandro { 1355f48ad614SDennis Dalessandro int ctxt; 1356f48ad614SDennis Dalessandro int pidx; 1357f48ad614SDennis Dalessandro struct hfi1_ctxtdata **tmp; 1358f48ad614SDennis Dalessandro unsigned long flags; 1359f48ad614SDennis Dalessandro 1360f48ad614SDennis Dalessandro /* users can't do anything more with chip */ 1361f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1362f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd = &dd->pport[pidx]; 1363f48ad614SDennis Dalessandro struct cc_state *cc_state; 1364f48ad614SDennis Dalessandro int i; 1365f48ad614SDennis Dalessandro 1366f48ad614SDennis Dalessandro if (ppd->statusp) 1367f48ad614SDennis Dalessandro *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT; 1368f48ad614SDennis Dalessandro 1369f48ad614SDennis Dalessandro for (i = 0; i < OPA_MAX_SLS; i++) 1370f48ad614SDennis Dalessandro hrtimer_cancel(&ppd->cca_timer[i].hrtimer); 1371f48ad614SDennis Dalessandro 1372f48ad614SDennis Dalessandro spin_lock(&ppd->cc_state_lock); 13738adf71faSJianxin Xiong cc_state = get_cc_state_protected(ppd); 1374f48ad614SDennis Dalessandro RCU_INIT_POINTER(ppd->cc_state, NULL); 1375f48ad614SDennis Dalessandro spin_unlock(&ppd->cc_state_lock); 1376f48ad614SDennis Dalessandro 1377f48ad614SDennis Dalessandro if (cc_state) 1378476d95bdSWei Yongjun kfree_rcu(cc_state, rcu); 1379f48ad614SDennis Dalessandro } 1380f48ad614SDennis Dalessandro 1381f48ad614SDennis Dalessandro free_credit_return(dd); 1382f48ad614SDennis Dalessandro 1383f48ad614SDennis Dalessandro /* 1384f48ad614SDennis Dalessandro * Free any resources still in use (usually just kernel contexts) 1385f48ad614SDennis Dalessandro * at unload; we do for ctxtcnt, because that's what we allocate. 1386f48ad614SDennis Dalessandro * We acquire lock to be really paranoid that rcd isn't being 1387f48ad614SDennis Dalessandro * accessed from some interrupt-related code (that should not happen, 1388f48ad614SDennis Dalessandro * but best to be sure). 1389f48ad614SDennis Dalessandro */ 1390f48ad614SDennis Dalessandro spin_lock_irqsave(&dd->uctxt_lock, flags); 1391f48ad614SDennis Dalessandro tmp = dd->rcd; 1392f48ad614SDennis Dalessandro dd->rcd = NULL; 1393f48ad614SDennis Dalessandro spin_unlock_irqrestore(&dd->uctxt_lock, flags); 1394f48ad614SDennis Dalessandro 1395f48ad614SDennis Dalessandro if (dd->rcvhdrtail_dummy_kvaddr) { 1396f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, sizeof(u64), 1397f48ad614SDennis Dalessandro (void *)dd->rcvhdrtail_dummy_kvaddr, 139860368186STymoteusz Kielan dd->rcvhdrtail_dummy_dma); 1399f48ad614SDennis Dalessandro dd->rcvhdrtail_dummy_kvaddr = NULL; 1400f48ad614SDennis Dalessandro } 1401f48ad614SDennis Dalessandro 1402f48ad614SDennis Dalessandro for (ctxt = 0; tmp && ctxt < dd->num_rcv_contexts; ctxt++) { 1403f48ad614SDennis Dalessandro struct hfi1_ctxtdata *rcd = tmp[ctxt]; 1404f48ad614SDennis Dalessandro 1405f48ad614SDennis Dalessandro tmp[ctxt] = NULL; /* debugging paranoia */ 1406f48ad614SDennis Dalessandro if (rcd) { 1407f48ad614SDennis Dalessandro hfi1_clear_tids(rcd); 1408f683c80cSMichael J. Ruhl hfi1_rcd_put(rcd); 1409f48ad614SDennis Dalessandro } 1410f48ad614SDennis Dalessandro } 1411f48ad614SDennis Dalessandro kfree(tmp); 1412f48ad614SDennis Dalessandro free_pio_map(dd); 1413f48ad614SDennis Dalessandro /* must follow rcv context free - need to remove rcv's hooks */ 1414f48ad614SDennis Dalessandro for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++) 1415f48ad614SDennis Dalessandro sc_free(dd->send_contexts[ctxt].sc); 1416f48ad614SDennis Dalessandro dd->num_send_contexts = 0; 1417f48ad614SDennis Dalessandro kfree(dd->send_contexts); 1418f48ad614SDennis Dalessandro dd->send_contexts = NULL; 1419f48ad614SDennis Dalessandro kfree(dd->hw_to_sw); 1420f48ad614SDennis Dalessandro dd->hw_to_sw = NULL; 1421f48ad614SDennis Dalessandro kfree(dd->boardname); 1422f48ad614SDennis Dalessandro vfree(dd->events); 1423f48ad614SDennis Dalessandro vfree(dd->status); 1424f48ad614SDennis Dalessandro } 1425f48ad614SDennis Dalessandro 1426f48ad614SDennis Dalessandro /* 1427f48ad614SDennis Dalessandro * Clean up on unit shutdown, or error during unit load after 1428f48ad614SDennis Dalessandro * successful initialization. 1429f48ad614SDennis Dalessandro */ 1430f48ad614SDennis Dalessandro static void postinit_cleanup(struct hfi1_devdata *dd) 1431f48ad614SDennis Dalessandro { 1432f48ad614SDennis Dalessandro hfi1_start_cleanup(dd); 1433f48ad614SDennis Dalessandro 1434f48ad614SDennis Dalessandro hfi1_pcie_ddcleanup(dd); 1435f48ad614SDennis Dalessandro hfi1_pcie_cleanup(dd->pcidev); 1436f48ad614SDennis Dalessandro 1437f48ad614SDennis Dalessandro cleanup_device_data(dd); 1438f48ad614SDennis Dalessandro 1439f48ad614SDennis Dalessandro hfi1_free_devdata(dd); 1440f48ad614SDennis Dalessandro } 1441f48ad614SDennis Dalessandro 144211501ab9SKrzysztof Blaszkowski static int init_validate_rcvhdrcnt(struct device *dev, uint thecnt) 144311501ab9SKrzysztof Blaszkowski { 144411501ab9SKrzysztof Blaszkowski if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { 144511501ab9SKrzysztof Blaszkowski hfi1_early_err(dev, "Receive header queue count too small\n"); 144611501ab9SKrzysztof Blaszkowski return -EINVAL; 144711501ab9SKrzysztof Blaszkowski } 144811501ab9SKrzysztof Blaszkowski 144911501ab9SKrzysztof Blaszkowski if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) { 145011501ab9SKrzysztof Blaszkowski hfi1_early_err(dev, 145111501ab9SKrzysztof Blaszkowski "Receive header queue count cannot be greater than %u\n", 145211501ab9SKrzysztof Blaszkowski HFI1_MAX_HDRQ_EGRBUF_CNT); 145311501ab9SKrzysztof Blaszkowski return -EINVAL; 145411501ab9SKrzysztof Blaszkowski } 145511501ab9SKrzysztof Blaszkowski 145611501ab9SKrzysztof Blaszkowski if (thecnt % HDRQ_INCREMENT) { 145711501ab9SKrzysztof Blaszkowski hfi1_early_err(dev, "Receive header queue count %d must be divisible by %lu\n", 145811501ab9SKrzysztof Blaszkowski thecnt, HDRQ_INCREMENT); 145911501ab9SKrzysztof Blaszkowski return -EINVAL; 146011501ab9SKrzysztof Blaszkowski } 146111501ab9SKrzysztof Blaszkowski 146211501ab9SKrzysztof Blaszkowski return 0; 146311501ab9SKrzysztof Blaszkowski } 146411501ab9SKrzysztof Blaszkowski 1465f48ad614SDennis Dalessandro static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1466f48ad614SDennis Dalessandro { 1467f48ad614SDennis Dalessandro int ret = 0, j, pidx, initfail; 146883fb4af6SKrzysztof Blaszkowski struct hfi1_devdata *dd; 1469f48ad614SDennis Dalessandro struct hfi1_pportdata *ppd; 1470f48ad614SDennis Dalessandro 1471f48ad614SDennis Dalessandro /* First, lock the non-writable module parameters */ 1472f48ad614SDennis Dalessandro HFI1_CAP_LOCK(); 1473f48ad614SDennis Dalessandro 14745d6f08afSTadeusz Struk /* Validate dev ids */ 14755d6f08afSTadeusz Struk if (!(ent->device == PCI_DEVICE_ID_INTEL0 || 14765d6f08afSTadeusz Struk ent->device == PCI_DEVICE_ID_INTEL1)) { 14775d6f08afSTadeusz Struk hfi1_early_err(&pdev->dev, 14785d6f08afSTadeusz Struk "Failing on unknown Intel deviceid 0x%x\n", 14795d6f08afSTadeusz Struk ent->device); 14805d6f08afSTadeusz Struk ret = -ENODEV; 14815d6f08afSTadeusz Struk goto bail; 14825d6f08afSTadeusz Struk } 14835d6f08afSTadeusz Struk 1484f48ad614SDennis Dalessandro /* Validate some global module parameters */ 148511501ab9SKrzysztof Blaszkowski ret = init_validate_rcvhdrcnt(&pdev->dev, rcvhdrcnt); 148611501ab9SKrzysztof Blaszkowski if (ret) 1487f48ad614SDennis Dalessandro goto bail; 148811501ab9SKrzysztof Blaszkowski 1489f48ad614SDennis Dalessandro /* use the encoding function as a sanitization check */ 1490f48ad614SDennis Dalessandro if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) { 1491f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n", 1492f48ad614SDennis Dalessandro hfi1_hdrq_entsize); 1493f48ad614SDennis Dalessandro ret = -EINVAL; 1494f48ad614SDennis Dalessandro goto bail; 1495f48ad614SDennis Dalessandro } 1496f48ad614SDennis Dalessandro 1497f48ad614SDennis Dalessandro /* The receive eager buffer size must be set before the receive 1498f48ad614SDennis Dalessandro * contexts are created. 1499f48ad614SDennis Dalessandro * 1500f48ad614SDennis Dalessandro * Set the eager buffer size. Validate that it falls in a range 1501f48ad614SDennis Dalessandro * allowed by the hardware - all powers of 2 between the min and 1502f48ad614SDennis Dalessandro * max. The maximum valid MTU is within the eager buffer range 1503f48ad614SDennis Dalessandro * so we do not need to cap the max_mtu by an eager buffer size 1504f48ad614SDennis Dalessandro * setting. 1505f48ad614SDennis Dalessandro */ 1506f48ad614SDennis Dalessandro if (eager_buffer_size) { 1507f48ad614SDennis Dalessandro if (!is_power_of_2(eager_buffer_size)) 1508f48ad614SDennis Dalessandro eager_buffer_size = 1509f48ad614SDennis Dalessandro roundup_pow_of_two(eager_buffer_size); 1510f48ad614SDennis Dalessandro eager_buffer_size = 1511f48ad614SDennis Dalessandro clamp_val(eager_buffer_size, 1512f48ad614SDennis Dalessandro MIN_EAGER_BUFFER * 8, 1513f48ad614SDennis Dalessandro MAX_EAGER_BUFFER_TOTAL); 1514f48ad614SDennis Dalessandro hfi1_early_info(&pdev->dev, "Eager buffer size %u\n", 1515f48ad614SDennis Dalessandro eager_buffer_size); 1516f48ad614SDennis Dalessandro } else { 1517f48ad614SDennis Dalessandro hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n"); 1518f48ad614SDennis Dalessandro ret = -EINVAL; 1519f48ad614SDennis Dalessandro goto bail; 1520f48ad614SDennis Dalessandro } 1521f48ad614SDennis Dalessandro 1522f48ad614SDennis Dalessandro /* restrict value of hfi1_rcvarr_split */ 1523f48ad614SDennis Dalessandro hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100); 1524f48ad614SDennis Dalessandro 1525f48ad614SDennis Dalessandro ret = hfi1_pcie_init(pdev, ent); 1526f48ad614SDennis Dalessandro if (ret) 1527f48ad614SDennis Dalessandro goto bail; 1528f48ad614SDennis Dalessandro 152983fb4af6SKrzysztof Blaszkowski /* 153083fb4af6SKrzysztof Blaszkowski * Do device-specific initialization, function table setup, dd 153183fb4af6SKrzysztof Blaszkowski * allocation, etc. 153283fb4af6SKrzysztof Blaszkowski */ 153383fb4af6SKrzysztof Blaszkowski dd = hfi1_init_dd(pdev, ent); 153483fb4af6SKrzysztof Blaszkowski 153583fb4af6SKrzysztof Blaszkowski if (IS_ERR(dd)) { 1536f48ad614SDennis Dalessandro ret = PTR_ERR(dd); 1537f48ad614SDennis Dalessandro goto clean_bail; /* error already printed */ 153883fb4af6SKrzysztof Blaszkowski } 1539f48ad614SDennis Dalessandro 1540f48ad614SDennis Dalessandro ret = create_workqueues(dd); 1541f48ad614SDennis Dalessandro if (ret) 1542f48ad614SDennis Dalessandro goto clean_bail; 1543f48ad614SDennis Dalessandro 1544f48ad614SDennis Dalessandro /* do the generic initialization */ 1545f48ad614SDennis Dalessandro initfail = hfi1_init(dd, 0); 1546f48ad614SDennis Dalessandro 1547d4829ea6SVishwanathapura, Niranjana /* setup vnic */ 1548d4829ea6SVishwanathapura, Niranjana hfi1_vnic_setup(dd); 1549d4829ea6SVishwanathapura, Niranjana 1550f48ad614SDennis Dalessandro ret = hfi1_register_ib_device(dd); 1551f48ad614SDennis Dalessandro 1552f48ad614SDennis Dalessandro /* 1553f48ad614SDennis Dalessandro * Now ready for use. this should be cleared whenever we 1554f48ad614SDennis Dalessandro * detect a reset, or initiate one. If earlier failure, 1555f48ad614SDennis Dalessandro * we still create devices, so diags, etc. can be used 1556f48ad614SDennis Dalessandro * to determine cause of problem. 1557f48ad614SDennis Dalessandro */ 1558f48ad614SDennis Dalessandro if (!initfail && !ret) { 1559f48ad614SDennis Dalessandro dd->flags |= HFI1_INITTED; 1560f48ad614SDennis Dalessandro /* create debufs files after init and ib register */ 1561f48ad614SDennis Dalessandro hfi1_dbg_ibdev_init(&dd->verbs_dev); 1562f48ad614SDennis Dalessandro } 1563f48ad614SDennis Dalessandro 1564f48ad614SDennis Dalessandro j = hfi1_device_create(dd); 1565f48ad614SDennis Dalessandro if (j) 1566f48ad614SDennis Dalessandro dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j); 1567f48ad614SDennis Dalessandro 1568f48ad614SDennis Dalessandro if (initfail || ret) { 1569f48ad614SDennis Dalessandro stop_timers(dd); 1570f48ad614SDennis Dalessandro flush_workqueue(ib_wq); 1571f48ad614SDennis Dalessandro for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1572f48ad614SDennis Dalessandro hfi1_quiet_serdes(dd->pport + pidx); 1573f48ad614SDennis Dalessandro ppd = dd->pport + pidx; 1574f48ad614SDennis Dalessandro if (ppd->hfi1_wq) { 1575f48ad614SDennis Dalessandro destroy_workqueue(ppd->hfi1_wq); 1576f48ad614SDennis Dalessandro ppd->hfi1_wq = NULL; 1577f48ad614SDennis Dalessandro } 1578f48ad614SDennis Dalessandro } 1579f48ad614SDennis Dalessandro if (!j) 1580f48ad614SDennis Dalessandro hfi1_device_remove(dd); 1581f48ad614SDennis Dalessandro if (!ret) 1582f48ad614SDennis Dalessandro hfi1_unregister_ib_device(dd); 15832280740fSVishwanathapura, Niranjana hfi1_vnic_cleanup(dd); 1584f48ad614SDennis Dalessandro postinit_cleanup(dd); 1585f48ad614SDennis Dalessandro if (initfail) 1586f48ad614SDennis Dalessandro ret = initfail; 1587f48ad614SDennis Dalessandro goto bail; /* everything already cleaned */ 1588f48ad614SDennis Dalessandro } 1589f48ad614SDennis Dalessandro 1590f48ad614SDennis Dalessandro sdma_start(dd); 1591f48ad614SDennis Dalessandro 1592f48ad614SDennis Dalessandro return 0; 1593f48ad614SDennis Dalessandro 1594f48ad614SDennis Dalessandro clean_bail: 1595f48ad614SDennis Dalessandro hfi1_pcie_cleanup(pdev); 1596f48ad614SDennis Dalessandro bail: 1597f48ad614SDennis Dalessandro return ret; 1598f48ad614SDennis Dalessandro } 1599f48ad614SDennis Dalessandro 1600acd7c8feSTadeusz Struk static void wait_for_clients(struct hfi1_devdata *dd) 1601acd7c8feSTadeusz Struk { 1602acd7c8feSTadeusz Struk /* 1603acd7c8feSTadeusz Struk * Remove the device init value and complete the device if there is 1604acd7c8feSTadeusz Struk * no clients or wait for active clients to finish. 1605acd7c8feSTadeusz Struk */ 1606acd7c8feSTadeusz Struk if (atomic_dec_and_test(&dd->user_refcount)) 1607acd7c8feSTadeusz Struk complete(&dd->user_comp); 1608acd7c8feSTadeusz Struk 1609acd7c8feSTadeusz Struk wait_for_completion(&dd->user_comp); 1610acd7c8feSTadeusz Struk } 1611acd7c8feSTadeusz Struk 1612f48ad614SDennis Dalessandro static void remove_one(struct pci_dev *pdev) 1613f48ad614SDennis Dalessandro { 1614f48ad614SDennis Dalessandro struct hfi1_devdata *dd = pci_get_drvdata(pdev); 1615f48ad614SDennis Dalessandro 1616f48ad614SDennis Dalessandro /* close debugfs files before ib unregister */ 1617f48ad614SDennis Dalessandro hfi1_dbg_ibdev_exit(&dd->verbs_dev); 1618acd7c8feSTadeusz Struk 1619acd7c8feSTadeusz Struk /* remove the /dev hfi1 interface */ 1620acd7c8feSTadeusz Struk hfi1_device_remove(dd); 1621acd7c8feSTadeusz Struk 1622acd7c8feSTadeusz Struk /* wait for existing user space clients to finish */ 1623acd7c8feSTadeusz Struk wait_for_clients(dd); 1624acd7c8feSTadeusz Struk 1625f48ad614SDennis Dalessandro /* unregister from IB core */ 1626f48ad614SDennis Dalessandro hfi1_unregister_ib_device(dd); 1627f48ad614SDennis Dalessandro 1628d4829ea6SVishwanathapura, Niranjana /* cleanup vnic */ 1629d4829ea6SVishwanathapura, Niranjana hfi1_vnic_cleanup(dd); 1630d4829ea6SVishwanathapura, Niranjana 1631f48ad614SDennis Dalessandro /* 1632f48ad614SDennis Dalessandro * Disable the IB link, disable interrupts on the device, 1633f48ad614SDennis Dalessandro * clear dma engines, etc. 1634f48ad614SDennis Dalessandro */ 1635f48ad614SDennis Dalessandro shutdown_device(dd); 1636f48ad614SDennis Dalessandro 1637f48ad614SDennis Dalessandro stop_timers(dd); 1638f48ad614SDennis Dalessandro 1639f48ad614SDennis Dalessandro /* wait until all of our (qsfp) queue_work() calls complete */ 1640f48ad614SDennis Dalessandro flush_workqueue(ib_wq); 1641f48ad614SDennis Dalessandro 1642f48ad614SDennis Dalessandro postinit_cleanup(dd); 1643f48ad614SDennis Dalessandro } 1644f48ad614SDennis Dalessandro 1645f48ad614SDennis Dalessandro /** 1646f48ad614SDennis Dalessandro * hfi1_create_rcvhdrq - create a receive header queue 1647f48ad614SDennis Dalessandro * @dd: the hfi1_ib device 1648f48ad614SDennis Dalessandro * @rcd: the context data 1649f48ad614SDennis Dalessandro * 1650f48ad614SDennis Dalessandro * This must be contiguous memory (from an i/o perspective), and must be 1651f48ad614SDennis Dalessandro * DMA'able (which means for some systems, it will go through an IOMMU, 1652f48ad614SDennis Dalessandro * or be forced into a low address range). 1653f48ad614SDennis Dalessandro */ 1654f48ad614SDennis Dalessandro int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 1655f48ad614SDennis Dalessandro { 1656f48ad614SDennis Dalessandro unsigned amt; 1657f48ad614SDennis Dalessandro u64 reg; 1658f48ad614SDennis Dalessandro 1659f48ad614SDennis Dalessandro if (!rcd->rcvhdrq) { 166060368186STymoteusz Kielan dma_addr_t dma_hdrqtail; 1661f48ad614SDennis Dalessandro gfp_t gfp_flags; 1662f48ad614SDennis Dalessandro 1663f48ad614SDennis Dalessandro /* 1664f48ad614SDennis Dalessandro * rcvhdrqentsize is in DWs, so we have to convert to bytes 1665f48ad614SDennis Dalessandro * (* sizeof(u32)). 1666f48ad614SDennis Dalessandro */ 1667f48ad614SDennis Dalessandro amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize * 1668f48ad614SDennis Dalessandro sizeof(u32)); 1669f48ad614SDennis Dalessandro 16702280740fSVishwanathapura, Niranjana if ((rcd->ctxt < dd->first_dyn_alloc_ctxt) || 16712280740fSVishwanathapura, Niranjana (rcd->sc && (rcd->sc->type == SC_KERNEL))) 16722280740fSVishwanathapura, Niranjana gfp_flags = GFP_KERNEL; 16732280740fSVishwanathapura, Niranjana else 16742280740fSVishwanathapura, Niranjana gfp_flags = GFP_USER; 1675f48ad614SDennis Dalessandro rcd->rcvhdrq = dma_zalloc_coherent( 167660368186STymoteusz Kielan &dd->pcidev->dev, amt, &rcd->rcvhdrq_dma, 1677f48ad614SDennis Dalessandro gfp_flags | __GFP_COMP); 1678f48ad614SDennis Dalessandro 1679f48ad614SDennis Dalessandro if (!rcd->rcvhdrq) { 1680f48ad614SDennis Dalessandro dd_dev_err(dd, 1681f48ad614SDennis Dalessandro "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n", 1682f48ad614SDennis Dalessandro amt, rcd->ctxt); 1683f48ad614SDennis Dalessandro goto bail; 1684f48ad614SDennis Dalessandro } 1685f48ad614SDennis Dalessandro 1686f48ad614SDennis Dalessandro if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) { 1687f48ad614SDennis Dalessandro rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent( 168860368186STymoteusz Kielan &dd->pcidev->dev, PAGE_SIZE, &dma_hdrqtail, 1689f48ad614SDennis Dalessandro gfp_flags); 1690f48ad614SDennis Dalessandro if (!rcd->rcvhdrtail_kvaddr) 1691f48ad614SDennis Dalessandro goto bail_free; 169260368186STymoteusz Kielan rcd->rcvhdrqtailaddr_dma = dma_hdrqtail; 1693f48ad614SDennis Dalessandro } 1694f48ad614SDennis Dalessandro 1695f48ad614SDennis Dalessandro rcd->rcvhdrq_size = amt; 1696f48ad614SDennis Dalessandro } 1697f48ad614SDennis Dalessandro /* 1698f48ad614SDennis Dalessandro * These values are per-context: 1699f48ad614SDennis Dalessandro * RcvHdrCnt 1700f48ad614SDennis Dalessandro * RcvHdrEntSize 1701f48ad614SDennis Dalessandro * RcvHdrSize 1702f48ad614SDennis Dalessandro */ 1703f48ad614SDennis Dalessandro reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT) 1704f48ad614SDennis Dalessandro & RCV_HDR_CNT_CNT_MASK) 1705f48ad614SDennis Dalessandro << RCV_HDR_CNT_CNT_SHIFT; 1706f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg); 1707f48ad614SDennis Dalessandro reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize) 1708f48ad614SDennis Dalessandro & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) 1709f48ad614SDennis Dalessandro << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT; 1710f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg); 1711f48ad614SDennis Dalessandro reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK) 1712f48ad614SDennis Dalessandro << RCV_HDR_SIZE_HDR_SIZE_SHIFT; 1713f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg); 1714f48ad614SDennis Dalessandro 1715f48ad614SDennis Dalessandro /* 1716f48ad614SDennis Dalessandro * Program dummy tail address for every receive context 1717f48ad614SDennis Dalessandro * before enabling any receive context 1718f48ad614SDennis Dalessandro */ 1719f48ad614SDennis Dalessandro write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR, 172060368186STymoteusz Kielan dd->rcvhdrtail_dummy_dma); 1721f48ad614SDennis Dalessandro 1722f48ad614SDennis Dalessandro return 0; 1723f48ad614SDennis Dalessandro 1724f48ad614SDennis Dalessandro bail_free: 1725f48ad614SDennis Dalessandro dd_dev_err(dd, 1726f48ad614SDennis Dalessandro "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n", 1727f48ad614SDennis Dalessandro rcd->ctxt); 1728f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq, 172960368186STymoteusz Kielan rcd->rcvhdrq_dma); 1730f48ad614SDennis Dalessandro rcd->rcvhdrq = NULL; 1731f48ad614SDennis Dalessandro bail: 1732f48ad614SDennis Dalessandro return -ENOMEM; 1733f48ad614SDennis Dalessandro } 1734f48ad614SDennis Dalessandro 1735f48ad614SDennis Dalessandro /** 1736f48ad614SDennis Dalessandro * allocate eager buffers, both kernel and user contexts. 1737f48ad614SDennis Dalessandro * @rcd: the context we are setting up. 1738f48ad614SDennis Dalessandro * 1739f48ad614SDennis Dalessandro * Allocate the eager TID buffers and program them into hip. 1740f48ad614SDennis Dalessandro * They are no longer completely contiguous, we do multiple allocation 1741f48ad614SDennis Dalessandro * calls. Otherwise we get the OOM code involved, by asking for too 1742f48ad614SDennis Dalessandro * much per call, with disastrous results on some kernels. 1743f48ad614SDennis Dalessandro */ 1744f48ad614SDennis Dalessandro int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd) 1745f48ad614SDennis Dalessandro { 1746f48ad614SDennis Dalessandro struct hfi1_devdata *dd = rcd->dd; 1747f48ad614SDennis Dalessandro u32 max_entries, egrtop, alloced_bytes = 0, idx = 0; 1748f48ad614SDennis Dalessandro gfp_t gfp_flags; 1749f48ad614SDennis Dalessandro u16 order; 1750f48ad614SDennis Dalessandro int ret = 0; 1751f48ad614SDennis Dalessandro u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu); 1752f48ad614SDennis Dalessandro 1753f48ad614SDennis Dalessandro /* 1754f48ad614SDennis Dalessandro * GFP_USER, but without GFP_FS, so buffer cache can be 1755f48ad614SDennis Dalessandro * coalesced (we hope); otherwise, even at order 4, 1756f48ad614SDennis Dalessandro * heavy filesystem activity makes these fail, and we can 1757f48ad614SDennis Dalessandro * use compound pages. 1758f48ad614SDennis Dalessandro */ 1759f48ad614SDennis Dalessandro gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP; 1760f48ad614SDennis Dalessandro 1761f48ad614SDennis Dalessandro /* 1762f48ad614SDennis Dalessandro * The minimum size of the eager buffers is a groups of MTU-sized 1763f48ad614SDennis Dalessandro * buffers. 1764f48ad614SDennis Dalessandro * The global eager_buffer_size parameter is checked against the 1765f48ad614SDennis Dalessandro * theoretical lower limit of the value. Here, we check against the 1766f48ad614SDennis Dalessandro * MTU. 1767f48ad614SDennis Dalessandro */ 1768f48ad614SDennis Dalessandro if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size)) 1769f48ad614SDennis Dalessandro rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size; 1770f48ad614SDennis Dalessandro /* 1771f48ad614SDennis Dalessandro * If using one-pkt-per-egr-buffer, lower the eager buffer 1772f48ad614SDennis Dalessandro * size to the max MTU (page-aligned). 1773f48ad614SDennis Dalessandro */ 1774f48ad614SDennis Dalessandro if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) 1775f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = round_mtu; 1776f48ad614SDennis Dalessandro 1777f48ad614SDennis Dalessandro /* 1778f48ad614SDennis Dalessandro * Eager buffers sizes of 1MB or less require smaller TID sizes 1779f48ad614SDennis Dalessandro * to satisfy the "multiple of 8 RcvArray entries" requirement. 1780f48ad614SDennis Dalessandro */ 1781f48ad614SDennis Dalessandro if (rcd->egrbufs.size <= (1 << 20)) 1782f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu, 1783f48ad614SDennis Dalessandro rounddown_pow_of_two(rcd->egrbufs.size / 8)); 1784f48ad614SDennis Dalessandro 1785f48ad614SDennis Dalessandro while (alloced_bytes < rcd->egrbufs.size && 1786f48ad614SDennis Dalessandro rcd->egrbufs.alloced < rcd->egrbufs.count) { 1787f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr = 1788f48ad614SDennis Dalessandro dma_zalloc_coherent(&dd->pcidev->dev, 1789f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size, 179060368186STymoteusz Kielan &rcd->egrbufs.buffers[idx].dma, 1791f48ad614SDennis Dalessandro gfp_flags); 1792f48ad614SDennis Dalessandro if (rcd->egrbufs.buffers[idx].addr) { 1793f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].len = 1794f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size; 1795f48ad614SDennis Dalessandro rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr = 1796f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr; 179760368186STymoteusz Kielan rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].dma = 179860368186STymoteusz Kielan rcd->egrbufs.buffers[idx].dma; 1799f48ad614SDennis Dalessandro rcd->egrbufs.alloced++; 1800f48ad614SDennis Dalessandro alloced_bytes += rcd->egrbufs.rcvtid_size; 1801f48ad614SDennis Dalessandro idx++; 1802f48ad614SDennis Dalessandro } else { 1803f48ad614SDennis Dalessandro u32 new_size, i, j; 1804f48ad614SDennis Dalessandro u64 offset = 0; 1805f48ad614SDennis Dalessandro 1806f48ad614SDennis Dalessandro /* 1807f48ad614SDennis Dalessandro * Fail the eager buffer allocation if: 1808f48ad614SDennis Dalessandro * - we are already using the lowest acceptable size 1809f48ad614SDennis Dalessandro * - we are using one-pkt-per-egr-buffer (this implies 1810f48ad614SDennis Dalessandro * that we are accepting only one size) 1811f48ad614SDennis Dalessandro */ 1812f48ad614SDennis Dalessandro if (rcd->egrbufs.rcvtid_size == round_mtu || 1813f48ad614SDennis Dalessandro !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) { 1814f48ad614SDennis Dalessandro dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n", 1815f48ad614SDennis Dalessandro rcd->ctxt); 181694679061SMichael J. Ruhl ret = -ENOMEM; 1817f48ad614SDennis Dalessandro goto bail_rcvegrbuf_phys; 1818f48ad614SDennis Dalessandro } 1819f48ad614SDennis Dalessandro 1820f48ad614SDennis Dalessandro new_size = rcd->egrbufs.rcvtid_size / 2; 1821f48ad614SDennis Dalessandro 1822f48ad614SDennis Dalessandro /* 1823f48ad614SDennis Dalessandro * If the first attempt to allocate memory failed, don't 1824f48ad614SDennis Dalessandro * fail everything but continue with the next lower 1825f48ad614SDennis Dalessandro * size. 1826f48ad614SDennis Dalessandro */ 1827f48ad614SDennis Dalessandro if (idx == 0) { 1828f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = new_size; 1829f48ad614SDennis Dalessandro continue; 1830f48ad614SDennis Dalessandro } 1831f48ad614SDennis Dalessandro 1832f48ad614SDennis Dalessandro /* 1833f48ad614SDennis Dalessandro * Re-partition already allocated buffers to a smaller 1834f48ad614SDennis Dalessandro * size. 1835f48ad614SDennis Dalessandro */ 1836f48ad614SDennis Dalessandro rcd->egrbufs.alloced = 0; 1837f48ad614SDennis Dalessandro for (i = 0, j = 0, offset = 0; j < idx; i++) { 1838f48ad614SDennis Dalessandro if (i >= rcd->egrbufs.count) 1839f48ad614SDennis Dalessandro break; 184060368186STymoteusz Kielan rcd->egrbufs.rcvtids[i].dma = 184160368186STymoteusz Kielan rcd->egrbufs.buffers[j].dma + offset; 1842f48ad614SDennis Dalessandro rcd->egrbufs.rcvtids[i].addr = 1843f48ad614SDennis Dalessandro rcd->egrbufs.buffers[j].addr + offset; 1844f48ad614SDennis Dalessandro rcd->egrbufs.alloced++; 184560368186STymoteusz Kielan if ((rcd->egrbufs.buffers[j].dma + offset + 1846f48ad614SDennis Dalessandro new_size) == 184760368186STymoteusz Kielan (rcd->egrbufs.buffers[j].dma + 1848f48ad614SDennis Dalessandro rcd->egrbufs.buffers[j].len)) { 1849f48ad614SDennis Dalessandro j++; 1850f48ad614SDennis Dalessandro offset = 0; 1851f48ad614SDennis Dalessandro } else { 1852f48ad614SDennis Dalessandro offset += new_size; 1853f48ad614SDennis Dalessandro } 1854f48ad614SDennis Dalessandro } 1855f48ad614SDennis Dalessandro rcd->egrbufs.rcvtid_size = new_size; 1856f48ad614SDennis Dalessandro } 1857f48ad614SDennis Dalessandro } 1858f48ad614SDennis Dalessandro rcd->egrbufs.numbufs = idx; 1859f48ad614SDennis Dalessandro rcd->egrbufs.size = alloced_bytes; 1860f48ad614SDennis Dalessandro 1861f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 1862f48ad614SDennis Dalessandro "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n", 186323002d5bSGrzegorz Heldt rcd->ctxt, rcd->egrbufs.alloced, 186423002d5bSGrzegorz Heldt rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024); 1865f48ad614SDennis Dalessandro 1866f48ad614SDennis Dalessandro /* 1867f48ad614SDennis Dalessandro * Set the contexts rcv array head update threshold to the closest 1868f48ad614SDennis Dalessandro * power of 2 (so we can use a mask instead of modulo) below half 1869f48ad614SDennis Dalessandro * the allocated entries. 1870f48ad614SDennis Dalessandro */ 1871f48ad614SDennis Dalessandro rcd->egrbufs.threshold = 1872f48ad614SDennis Dalessandro rounddown_pow_of_two(rcd->egrbufs.alloced / 2); 1873f48ad614SDennis Dalessandro /* 1874f48ad614SDennis Dalessandro * Compute the expected RcvArray entry base. This is done after 1875f48ad614SDennis Dalessandro * allocating the eager buffers in order to maximize the 1876f48ad614SDennis Dalessandro * expected RcvArray entries for the context. 1877f48ad614SDennis Dalessandro */ 1878f48ad614SDennis Dalessandro max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size; 1879f48ad614SDennis Dalessandro egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size); 1880f48ad614SDennis Dalessandro rcd->expected_count = max_entries - egrtop; 1881f48ad614SDennis Dalessandro if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2) 1882f48ad614SDennis Dalessandro rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2; 1883f48ad614SDennis Dalessandro 1884f48ad614SDennis Dalessandro rcd->expected_base = rcd->eager_base + egrtop; 1885f48ad614SDennis Dalessandro hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n", 1886f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count, 1887f48ad614SDennis Dalessandro rcd->eager_base, rcd->expected_base); 1888f48ad614SDennis Dalessandro 1889f48ad614SDennis Dalessandro if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) { 1890f48ad614SDennis Dalessandro hfi1_cdbg(PROC, 1891f48ad614SDennis Dalessandro "ctxt%u: current Eager buffer size is invalid %u\n", 1892f48ad614SDennis Dalessandro rcd->ctxt, rcd->egrbufs.rcvtid_size); 1893f48ad614SDennis Dalessandro ret = -EINVAL; 189462239fc6SMichael J. Ruhl goto bail_rcvegrbuf_phys; 1895f48ad614SDennis Dalessandro } 1896f48ad614SDennis Dalessandro 1897f48ad614SDennis Dalessandro for (idx = 0; idx < rcd->egrbufs.alloced; idx++) { 1898f48ad614SDennis Dalessandro hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER, 189960368186STymoteusz Kielan rcd->egrbufs.rcvtids[idx].dma, order); 1900f48ad614SDennis Dalessandro cond_resched(); 1901f48ad614SDennis Dalessandro } 190262239fc6SMichael J. Ruhl 190362239fc6SMichael J. Ruhl return 0; 1904f48ad614SDennis Dalessandro 1905f48ad614SDennis Dalessandro bail_rcvegrbuf_phys: 1906f48ad614SDennis Dalessandro for (idx = 0; idx < rcd->egrbufs.alloced && 1907f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr; 1908f48ad614SDennis Dalessandro idx++) { 1909f48ad614SDennis Dalessandro dma_free_coherent(&dd->pcidev->dev, 1910f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].len, 1911f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr, 191260368186STymoteusz Kielan rcd->egrbufs.buffers[idx].dma); 1913f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].addr = NULL; 191460368186STymoteusz Kielan rcd->egrbufs.buffers[idx].dma = 0; 1915f48ad614SDennis Dalessandro rcd->egrbufs.buffers[idx].len = 0; 1916f48ad614SDennis Dalessandro } 191762239fc6SMichael J. Ruhl 1918f48ad614SDennis Dalessandro return ret; 1919f48ad614SDennis Dalessandro } 1920