1 #ifndef _HFI1_KERNEL_H 2 #define _HFI1_KERNEL_H 3 /* 4 * Copyright(c) 2015-2017 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 #include <linux/interrupt.h> 51 #include <linux/pci.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/mutex.h> 54 #include <linux/list.h> 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/idr.h> 58 #include <linux/io.h> 59 #include <linux/fs.h> 60 #include <linux/completion.h> 61 #include <linux/kref.h> 62 #include <linux/sched.h> 63 #include <linux/cdev.h> 64 #include <linux/delay.h> 65 #include <linux/kthread.h> 66 #include <linux/i2c.h> 67 #include <linux/i2c-algo-bit.h> 68 #include <rdma/ib_hdrs.h> 69 #include <linux/rhashtable.h> 70 #include <linux/netdevice.h> 71 #include <rdma/rdma_vt.h> 72 73 #include "chip_registers.h" 74 #include "common.h" 75 #include "verbs.h" 76 #include "pio.h" 77 #include "chip.h" 78 #include "mad.h" 79 #include "qsfp.h" 80 #include "platform.h" 81 #include "affinity.h" 82 83 /* bumped 1 from s/w major version of TrueScale */ 84 #define HFI1_CHIP_VERS_MAJ 3U 85 86 /* don't care about this except printing */ 87 #define HFI1_CHIP_VERS_MIN 0U 88 89 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 90 #define HFI1_OUI 0x001175 91 #define HFI1_OUI_LSB 40 92 93 #define DROP_PACKET_OFF 0 94 #define DROP_PACKET_ON 1 95 96 extern unsigned long hfi1_cap_mask; 97 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) 98 #define HFI1_CAP_UGET_MASK(mask, cap) \ 99 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) 100 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) 101 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) 102 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) 103 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) 104 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ 105 HFI1_CAP_MISC_MASK) 106 /* Offline Disabled Reason is 4-bits */ 107 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) 108 109 /* 110 * Control context is always 0 and handles the error packets. 111 * It also handles the VL15 and multicast packets. 112 */ 113 #define HFI1_CTRL_CTXT 0 114 115 /* 116 * Driver context will store software counters for each of the events 117 * associated with these status registers 118 */ 119 #define NUM_CCE_ERR_STATUS_COUNTERS 41 120 #define NUM_RCV_ERR_STATUS_COUNTERS 64 121 #define NUM_MISC_ERR_STATUS_COUNTERS 13 122 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 123 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 124 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 125 #define NUM_SEND_ERR_STATUS_COUNTERS 3 126 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 127 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 128 129 /* 130 * per driver stats, either not device nor port-specific, or 131 * summed over all of the devices and ports. 132 * They are described by name via ipathfs filesystem, so layout 133 * and number of elements can change without breaking compatibility. 134 * If members are added or deleted hfi1_statnames[] in debugfs.c must 135 * change to match. 136 */ 137 struct hfi1_ib_stats { 138 __u64 sps_ints; /* number of interrupts handled */ 139 __u64 sps_errints; /* number of error interrupts */ 140 __u64 sps_txerrs; /* tx-related packet errors */ 141 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 142 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 143 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 144 __u64 sps_ctxts; /* number of contexts currently open */ 145 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 146 __u64 sps_buffull; 147 __u64 sps_hdrfull; 148 }; 149 150 extern struct hfi1_ib_stats hfi1_stats; 151 extern const struct pci_error_handlers hfi1_pci_err_handler; 152 153 /* 154 * First-cut criterion for "device is active" is 155 * two thousand dwords combined Tx, Rx traffic per 156 * 5-second interval. SMA packets are 64 dwords, 157 * and occur "a few per second", presumably each way. 158 */ 159 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) 160 161 /* 162 * Below contains all data related to a single context (formerly called port). 163 */ 164 165 #ifdef CONFIG_DEBUG_FS 166 struct hfi1_opcode_stats_perctx; 167 #endif 168 169 struct ctxt_eager_bufs { 170 ssize_t size; /* total size of eager buffers */ 171 u32 count; /* size of buffers array */ 172 u32 numbufs; /* number of buffers allocated */ 173 u32 alloced; /* number of rcvarray entries used */ 174 u32 rcvtid_size; /* size of each eager rcv tid */ 175 u32 threshold; /* head update threshold */ 176 struct eager_buffer { 177 void *addr; 178 dma_addr_t dma; 179 ssize_t len; 180 } *buffers; 181 struct { 182 void *addr; 183 dma_addr_t dma; 184 } *rcvtids; 185 }; 186 187 struct exp_tid_set { 188 struct list_head list; 189 u32 count; 190 }; 191 192 struct hfi1_ctxtdata { 193 /* shadow the ctxt's RcvCtrl register */ 194 u64 rcvctrl; 195 /* rcvhdrq base, needs mmap before useful */ 196 void *rcvhdrq; 197 /* kernel virtual address where hdrqtail is updated */ 198 volatile __le64 *rcvhdrtail_kvaddr; 199 /* when waiting for rcv or pioavail */ 200 wait_queue_head_t wait; 201 /* rcvhdrq size (for freeing) */ 202 size_t rcvhdrq_size; 203 /* number of rcvhdrq entries */ 204 u16 rcvhdrq_cnt; 205 /* size of each of the rcvhdrq entries */ 206 u16 rcvhdrqentsize; 207 /* mmap of hdrq, must fit in 44 bits */ 208 dma_addr_t rcvhdrq_dma; 209 dma_addr_t rcvhdrqtailaddr_dma; 210 struct ctxt_eager_bufs egrbufs; 211 /* this receive context's assigned PIO ACK send context */ 212 struct send_context *sc; 213 214 /* dynamic receive available interrupt timeout */ 215 u32 rcvavail_timeout; 216 /* 217 * number of opens (including slave sub-contexts) on this instance 218 * (ignoring forks, dup, etc. for now) 219 */ 220 int cnt; 221 /* Device context index */ 222 unsigned ctxt; 223 /* 224 * non-zero if ctxt can be shared, and defines the maximum number of 225 * sub-contexts for this device context. 226 */ 227 u16 subctxt_cnt; 228 /* non-zero if ctxt is being shared. */ 229 u16 subctxt_id; 230 u8 uuid[16]; 231 /* job key */ 232 u16 jkey; 233 /* number of RcvArray groups for this context. */ 234 u32 rcv_array_groups; 235 /* index of first eager TID entry. */ 236 u32 eager_base; 237 /* number of expected TID entries */ 238 u32 expected_count; 239 /* index of first expected TID entry. */ 240 u32 expected_base; 241 242 struct exp_tid_set tid_group_list; 243 struct exp_tid_set tid_used_list; 244 struct exp_tid_set tid_full_list; 245 246 /* lock protecting all Expected TID data */ 247 struct mutex exp_lock; 248 /* number of pio bufs for this ctxt (all procs, if shared) */ 249 u32 piocnt; 250 /* first pio buffer for this ctxt */ 251 u32 pio_base; 252 /* chip offset of PIO buffers for this ctxt */ 253 u32 piobufs; 254 /* per-context configuration flags */ 255 unsigned long flags; 256 /* per-context event flags for fileops/intr communication */ 257 unsigned long event_flags; 258 /* WAIT_RCV that timed out, no interrupt */ 259 u32 rcvwait_to; 260 /* WAIT_PIO that timed out, no interrupt */ 261 u32 piowait_to; 262 /* WAIT_RCV already happened, no wait */ 263 u32 rcvnowait; 264 /* WAIT_PIO already happened, no wait */ 265 u32 pionowait; 266 /* total number of polled urgent packets */ 267 u32 urgent; 268 /* saved total number of polled urgent packets for poll edge trigger */ 269 u32 urgent_poll; 270 /* same size as task_struct .comm[], command that opened context */ 271 char comm[TASK_COMM_LEN]; 272 /* so file ops can get at unit */ 273 struct hfi1_devdata *dd; 274 /* so functions that need physical port can get it easily */ 275 struct hfi1_pportdata *ppd; 276 /* associated msix interrupt */ 277 u32 msix_intr; 278 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 279 void *subctxt_uregbase; 280 /* An array of pages for the eager receive buffers * N */ 281 void *subctxt_rcvegrbuf; 282 /* An array of pages for the eager header queue entries * N */ 283 void *subctxt_rcvhdr_base; 284 /* Bitmask of in use context(s) */ 285 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS); 286 /* The version of the library which opened this ctxt */ 287 u32 userversion; 288 /* Type of packets or conditions we want to poll for */ 289 u16 poll_type; 290 /* receive packet sequence counter */ 291 u8 seq_cnt; 292 u8 redirect_seq_cnt; 293 /* ctxt rcvhdrq head offset */ 294 u32 head; 295 u32 pkt_count; 296 /* QPs waiting for context processing */ 297 struct list_head qp_wait_list; 298 /* interrupt handling */ 299 u64 imask; /* clear interrupt mask */ 300 int ireg; /* clear interrupt register */ 301 unsigned numa_id; /* numa node of this context */ 302 /* verbs stats per CTX */ 303 struct hfi1_opcode_stats_perctx *opstats; 304 /* 305 * This is the kernel thread that will keep making 306 * progress on the user sdma requests behind the scenes. 307 * There is one per context (shared contexts use the master's). 308 */ 309 struct task_struct *progress; 310 struct list_head sdma_queues; 311 /* protect sdma queues */ 312 spinlock_t sdma_qlock; 313 314 /* Is ASPM interrupt supported for this context */ 315 bool aspm_intr_supported; 316 /* ASPM state (enabled/disabled) for this context */ 317 bool aspm_enabled; 318 /* Timer for re-enabling ASPM if interrupt activity quietens down */ 319 struct timer_list aspm_timer; 320 /* Lock to serialize between intr, timer intr and user threads */ 321 spinlock_t aspm_lock; 322 /* Is ASPM processing enabled for this context (in intr context) */ 323 bool aspm_intr_enable; 324 /* Last interrupt timestamp */ 325 ktime_t aspm_ts_last_intr; 326 /* Last timestamp at which we scheduled a timer for this context */ 327 ktime_t aspm_ts_timer_sched; 328 329 /* 330 * The interrupt handler for a particular receive context can vary 331 * throughout it's lifetime. This is not a lock protected data member so 332 * it must be updated atomically and the prev and new value must always 333 * be valid. Worst case is we process an extra interrupt and up to 64 334 * packets with the wrong interrupt handler. 335 */ 336 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); 337 338 /* Indicates that this is vnic context */ 339 bool is_vnic; 340 341 /* vnic queue index this context is mapped to */ 342 u8 vnic_q_idx; 343 }; 344 345 /* 346 * Represents a single packet at a high level. Put commonly computed things in 347 * here so we do not have to keep doing them over and over. The rule of thumb is 348 * if something is used one time to derive some value, store that something in 349 * here. If it is used multiple times, then store the result of that derivation 350 * in here. 351 */ 352 struct hfi1_packet { 353 void *ebuf; 354 void *hdr; 355 struct hfi1_ctxtdata *rcd; 356 __le32 *rhf_addr; 357 struct rvt_qp *qp; 358 struct ib_other_headers *ohdr; 359 u64 rhf; 360 u32 maxcnt; 361 u32 rhqoff; 362 u16 tlen; 363 s16 etail; 364 u8 hlen; 365 u8 numpkt; 366 u8 rsize; 367 u8 updegr; 368 u8 rcv_flags; 369 u8 etype; 370 }; 371 372 struct rvt_sge_state; 373 374 /* 375 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 376 * Mostly for MADs that set or query link parameters, also ipath 377 * config interfaces 378 */ 379 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 380 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ 381 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 382 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ 383 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 384 #define HFI1_IB_CFG_SPD 5 /* current Link spd */ 385 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 386 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 387 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 388 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 389 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ 390 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 391 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 392 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 393 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 394 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 395 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ 396 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ 397 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 398 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 399 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ 400 401 /* 402 * HFI or Host Link States 403 * 404 * These describe the states the driver thinks the logical and physical 405 * states are in. Used as an argument to set_link_state(). Implemented 406 * as bits for easy multi-state checking. The actual state can only be 407 * one. 408 */ 409 #define __HLS_UP_INIT_BP 0 410 #define __HLS_UP_ARMED_BP 1 411 #define __HLS_UP_ACTIVE_BP 2 412 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ 413 #define __HLS_DN_POLL_BP 4 414 #define __HLS_DN_DISABLE_BP 5 415 #define __HLS_DN_OFFLINE_BP 6 416 #define __HLS_VERIFY_CAP_BP 7 417 #define __HLS_GOING_UP_BP 8 418 #define __HLS_GOING_OFFLINE_BP 9 419 #define __HLS_LINK_COOLDOWN_BP 10 420 421 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) 422 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) 423 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) 424 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ 425 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) 426 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) 427 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) 428 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) 429 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) 430 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) 431 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) 432 433 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) 434 #define HLS_DOWN ~(HLS_UP) 435 436 /* use this MTU size if none other is given */ 437 #define HFI1_DEFAULT_ACTIVE_MTU 10240 438 /* use this MTU size as the default maximum */ 439 #define HFI1_DEFAULT_MAX_MTU 10240 440 /* default partition key */ 441 #define DEFAULT_PKEY 0xffff 442 443 /* 444 * Possible fabric manager config parameters for fm_{get,set}_table() 445 */ 446 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ 447 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ 448 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ 449 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ 450 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ 451 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ 452 453 /* 454 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 455 * these are bits so they can be combined, e.g. 456 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB 457 */ 458 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 459 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 460 #define HFI1_RCVCTRL_CTXT_ENB 0x04 461 #define HFI1_RCVCTRL_CTXT_DIS 0x08 462 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 463 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 464 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 465 #define HFI1_RCVCTRL_PKEY_DIS 0x80 466 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 467 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 468 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 469 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 470 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 471 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 472 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 473 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 474 475 /* partition enforcement flags */ 476 #define HFI1_PART_ENFORCE_IN 0x1 477 #define HFI1_PART_ENFORCE_OUT 0x2 478 479 /* how often we check for synthetic counter wrap around */ 480 #define SYNTH_CNT_TIME 3 481 482 /* Counter flags */ 483 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ 484 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ 485 #define CNTR_DISABLED 0x2 /* Disable this counter */ 486 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ 487 #define CNTR_VL 0x8 /* Per VL counter */ 488 #define CNTR_SDMA 0x10 489 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ 490 #define CNTR_MODE_W 0x0 491 #define CNTR_MODE_R 0x1 492 493 /* VLs Supported/Operational */ 494 #define HFI1_MIN_VLS_SUPPORTED 1 495 #define HFI1_MAX_VLS_SUPPORTED 8 496 497 #define HFI1_GUIDS_PER_PORT 5 498 #define HFI1_PORT_GUID_INDEX 0 499 500 static inline void incr_cntr64(u64 *cntr) 501 { 502 if (*cntr < (u64)-1LL) 503 (*cntr)++; 504 } 505 506 static inline void incr_cntr32(u32 *cntr) 507 { 508 if (*cntr < (u32)-1LL) 509 (*cntr)++; 510 } 511 512 #define MAX_NAME_SIZE 64 513 struct hfi1_msix_entry { 514 enum irq_type type; 515 struct msix_entry msix; 516 void *arg; 517 char name[MAX_NAME_SIZE]; 518 cpumask_t mask; 519 struct irq_affinity_notify notify; 520 }; 521 522 /* per-SL CCA information */ 523 struct cca_timer { 524 struct hrtimer hrtimer; 525 struct hfi1_pportdata *ppd; /* read-only */ 526 int sl; /* read-only */ 527 u16 ccti; /* read/write - current value of CCTI */ 528 }; 529 530 struct link_down_reason { 531 /* 532 * SMA-facing value. Should be set from .latest when 533 * HLS_UP_* -> HLS_DN_* transition actually occurs. 534 */ 535 u8 sma; 536 u8 latest; 537 }; 538 539 enum { 540 LO_PRIO_TABLE, 541 HI_PRIO_TABLE, 542 MAX_PRIO_TABLE 543 }; 544 545 struct vl_arb_cache { 546 /* protect vl arb cache */ 547 spinlock_t lock; 548 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; 549 }; 550 551 /* 552 * The structure below encapsulates data relevant to a physical IB Port. 553 * Current chips support only one such port, but the separation 554 * clarifies things a bit. Note that to conform to IB conventions, 555 * port-numbers are one-based. The first or only port is port1. 556 */ 557 struct hfi1_pportdata { 558 struct hfi1_ibport ibport_data; 559 560 struct hfi1_devdata *dd; 561 struct kobject pport_cc_kobj; 562 struct kobject sc2vl_kobj; 563 struct kobject sl2sc_kobj; 564 struct kobject vl2mtu_kobj; 565 566 /* PHY support */ 567 struct qsfp_data qsfp_info; 568 /* Values for SI tuning of SerDes */ 569 u32 port_type; 570 u32 tx_preset_eq; 571 u32 tx_preset_noeq; 572 u32 rx_preset; 573 u8 local_atten; 574 u8 remote_atten; 575 u8 default_atten; 576 u8 max_power_class; 577 578 /* GUIDs for this interface, in host order, guids[0] is a port guid */ 579 u64 guids[HFI1_GUIDS_PER_PORT]; 580 581 /* GUID for peer interface, in host order */ 582 u64 neighbor_guid; 583 584 /* up or down physical link state */ 585 u32 linkup; 586 587 /* 588 * this address is mapped read-only into user processes so they can 589 * get status cheaply, whenever they want. One qword of status per port 590 */ 591 u64 *statusp; 592 593 /* SendDMA related entries */ 594 595 struct workqueue_struct *hfi1_wq; 596 597 /* move out of interrupt context */ 598 struct work_struct link_vc_work; 599 struct work_struct link_up_work; 600 struct work_struct link_down_work; 601 struct work_struct sma_message_work; 602 struct work_struct freeze_work; 603 struct work_struct link_downgrade_work; 604 struct work_struct link_bounce_work; 605 struct delayed_work start_link_work; 606 /* host link state variables */ 607 struct mutex hls_lock; 608 u32 host_link_state; 609 610 u32 lstate; /* logical link state */ 611 612 /* these are the "32 bit" regs */ 613 614 u32 ibmtu; /* The MTU programmed for this unit */ 615 /* 616 * Current max size IB packet (in bytes) including IB headers, that 617 * we can send. Changes when ibmtu changes. 618 */ 619 u32 ibmaxlen; 620 u32 current_egress_rate; /* units [10^6 bits/sec] */ 621 /* LID programmed for this instance */ 622 u16 lid; 623 /* list of pkeys programmed; 0 if not set */ 624 u16 pkeys[MAX_PKEY_VALUES]; 625 u16 link_width_supported; 626 u16 link_width_downgrade_supported; 627 u16 link_speed_supported; 628 u16 link_width_enabled; 629 u16 link_width_downgrade_enabled; 630 u16 link_speed_enabled; 631 u16 link_width_active; 632 u16 link_width_downgrade_tx_active; 633 u16 link_width_downgrade_rx_active; 634 u16 link_speed_active; 635 u8 vls_supported; 636 u8 vls_operational; 637 u8 actual_vls_operational; 638 /* LID mask control */ 639 u8 lmc; 640 /* Rx Polarity inversion (compensate for ~tx on partner) */ 641 u8 rx_pol_inv; 642 643 u8 hw_pidx; /* physical port index */ 644 u8 port; /* IB port number and index into dd->pports - 1 */ 645 /* type of neighbor node */ 646 u8 neighbor_type; 647 u8 neighbor_normal; 648 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ 649 u8 neighbor_port_number; 650 u8 is_sm_config_started; 651 u8 offline_disabled_reason; 652 u8 is_active_optimize_enabled; 653 u8 driver_link_ready; /* driver ready for active link */ 654 u8 link_enabled; /* link enabled? */ 655 u8 linkinit_reason; 656 u8 local_tx_rate; /* rate given to 8051 firmware */ 657 u8 last_pstate; /* info only */ 658 u8 qsfp_retry_count; 659 660 /* placeholders for IB MAD packet settings */ 661 u8 overrun_threshold; 662 u8 phy_error_threshold; 663 664 /* Used to override LED behavior for things like maintenance beaconing*/ 665 /* 666 * Alternates per phase of blink 667 * [0] holds LED off duration, [1] holds LED on duration 668 */ 669 unsigned long led_override_vals[2]; 670 u8 led_override_phase; /* LSB picks from vals[] */ 671 atomic_t led_override_timer_active; 672 /* Used to flash LEDs in override mode */ 673 struct timer_list led_override_timer; 674 675 u32 sm_trap_qp; 676 u32 sa_qp; 677 678 /* 679 * cca_timer_lock protects access to the per-SL cca_timer 680 * structures (specifically the ccti member). 681 */ 682 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; 683 struct cca_timer cca_timer[OPA_MAX_SLS]; 684 685 /* List of congestion control table entries */ 686 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; 687 688 /* congestion entries, each entry corresponding to a SL */ 689 struct opa_congestion_setting_entry_shadow 690 congestion_entries[OPA_MAX_SLS]; 691 692 /* 693 * cc_state_lock protects (write) access to the per-port 694 * struct cc_state. 695 */ 696 spinlock_t cc_state_lock ____cacheline_aligned_in_smp; 697 698 struct cc_state __rcu *cc_state; 699 700 /* Total number of congestion control table entries */ 701 u16 total_cct_entry; 702 703 /* Bit map identifying service level */ 704 u32 cc_sl_control_map; 705 706 /* CA's max number of 64 entry units in the congestion control table */ 707 u8 cc_max_table_entries; 708 709 /* 710 * begin congestion log related entries 711 * cc_log_lock protects all congestion log related data 712 */ 713 spinlock_t cc_log_lock ____cacheline_aligned_in_smp; 714 u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; 715 u16 threshold_event_counter; 716 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; 717 int cc_log_idx; /* index for logging events */ 718 int cc_mad_idx; /* index for reporting events */ 719 /* end congestion log related entries */ 720 721 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; 722 723 /* port relative counter buffer */ 724 u64 *cntrs; 725 /* port relative synthetic counter buffer */ 726 u64 *scntrs; 727 /* port_xmit_discards are synthesized from different egress errors */ 728 u64 port_xmit_discards; 729 u64 port_xmit_discards_vl[C_VL_COUNT]; 730 u64 port_xmit_constraint_errors; 731 u64 port_rcv_constraint_errors; 732 /* count of 'link_err' interrupts from DC */ 733 u64 link_downed; 734 /* number of times link retrained successfully */ 735 u64 link_up; 736 /* number of times a link unknown frame was reported */ 737 u64 unknown_frame_count; 738 /* port_ltp_crc_mode is returned in 'portinfo' MADs */ 739 u16 port_ltp_crc_mode; 740 /* port_crc_mode_enabled is the crc we support */ 741 u8 port_crc_mode_enabled; 742 /* mgmt_allowed is also returned in 'portinfo' MADs */ 743 u8 mgmt_allowed; 744 u8 part_enforce; /* partition enforcement flags */ 745 struct link_down_reason local_link_down_reason; 746 struct link_down_reason neigh_link_down_reason; 747 /* Value to be sent to link peer on LinkDown .*/ 748 u8 remote_link_down_reason; 749 /* Error events that will cause a port bounce. */ 750 u32 port_error_action; 751 struct work_struct linkstate_active_work; 752 /* Does this port need to prescan for FECNs */ 753 bool cc_prescan; 754 }; 755 756 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); 757 758 typedef void (*opcode_handler)(struct hfi1_packet *packet); 759 760 /* return values for the RHF receive functions */ 761 #define RHF_RCV_CONTINUE 0 /* keep going */ 762 #define RHF_RCV_DONE 1 /* stop, this packet processed */ 763 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ 764 765 struct rcv_array_data { 766 u8 group_size; 767 u16 ngroups; 768 u16 nctxt_extra; 769 }; 770 771 struct per_vl_data { 772 u16 mtu; 773 struct send_context *sc; 774 }; 775 776 /* 16 to directly index */ 777 #define PER_VL_SEND_CONTEXTS 16 778 779 struct err_info_rcvport { 780 u8 status_and_code; 781 u64 packet_flit1; 782 u64 packet_flit2; 783 }; 784 785 struct err_info_constraint { 786 u8 status; 787 u16 pkey; 788 u32 slid; 789 }; 790 791 struct hfi1_temp { 792 unsigned int curr; /* current temperature */ 793 unsigned int lo_lim; /* low temperature limit */ 794 unsigned int hi_lim; /* high temperature limit */ 795 unsigned int crit_lim; /* critical temperature limit */ 796 u8 triggers; /* temperature triggers */ 797 }; 798 799 struct hfi1_i2c_bus { 800 struct hfi1_devdata *controlling_dd; /* current controlling device */ 801 struct i2c_adapter adapter; /* bus details */ 802 struct i2c_algo_bit_data algo; /* bus algorithm details */ 803 int num; /* bus number, 0 or 1 */ 804 }; 805 806 /* common data between shared ASIC HFIs */ 807 struct hfi1_asic_data { 808 struct hfi1_devdata *dds[2]; /* back pointers */ 809 struct mutex asic_resource_mutex; 810 struct hfi1_i2c_bus *i2c_bus0; 811 struct hfi1_i2c_bus *i2c_bus1; 812 }; 813 814 /* sizes for both the QP and RSM map tables */ 815 #define NUM_MAP_ENTRIES 256 816 #define NUM_MAP_REGS 32 817 818 /* 819 * Number of VNIC contexts used. Ensure it is less than or equal to 820 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE). 821 */ 822 #define HFI1_NUM_VNIC_CTXT 8 823 824 /* Number of VNIC RSM entries */ 825 #define NUM_VNIC_MAP_ENTRIES 8 826 827 /* Virtual NIC information */ 828 struct hfi1_vnic_data { 829 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT]; 830 struct kmem_cache *txreq_cache; 831 u8 num_vports; 832 struct idr vesw_idr; 833 u8 rmt_start; 834 u8 num_ctxt; 835 u32 msix_idx; 836 }; 837 838 struct hfi1_vnic_vport_info; 839 840 /* device data struct now contains only "general per-device" info. 841 * fields related to a physical IB port are in a hfi1_pportdata struct. 842 */ 843 struct sdma_engine; 844 struct sdma_vl_map; 845 846 #define BOARD_VERS_MAX 96 /* how long the version string can be */ 847 #define SERIAL_MAX 16 /* length of the serial number */ 848 849 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); 850 struct hfi1_devdata { 851 struct hfi1_ibdev verbs_dev; /* must be first */ 852 struct list_head list; 853 /* pointers to related structs for this device */ 854 /* pci access data structure */ 855 struct pci_dev *pcidev; 856 struct cdev user_cdev; 857 struct cdev diag_cdev; 858 struct cdev ui_cdev; 859 struct device *user_device; 860 struct device *diag_device; 861 struct device *ui_device; 862 863 /* mem-mapped pointer to base of chip regs */ 864 u8 __iomem *kregbase; 865 /* end of mem-mapped chip space excluding sendbuf and user regs */ 866 u8 __iomem *kregend; 867 /* physical address of chip for io_remap, etc. */ 868 resource_size_t physaddr; 869 /* Per VL data. Enough for all VLs but not all elements are set/used. */ 870 struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; 871 /* send context data */ 872 struct send_context_info *send_contexts; 873 /* map hardware send contexts to software index */ 874 u8 *hw_to_sw; 875 /* spinlock for allocating and releasing send context resources */ 876 spinlock_t sc_lock; 877 /* lock for pio_map */ 878 spinlock_t pio_map_lock; 879 /* Send Context initialization lock. */ 880 spinlock_t sc_init_lock; 881 /* lock for sdma_map */ 882 spinlock_t sde_map_lock; 883 /* array of kernel send contexts */ 884 struct send_context **kernel_send_context; 885 /* array of vl maps */ 886 struct pio_vl_map __rcu *pio_map; 887 /* default flags to last descriptor */ 888 u64 default_desc1; 889 890 /* fields common to all SDMA engines */ 891 892 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ 893 dma_addr_t sdma_heads_phys; 894 void *sdma_pad_dma; /* DMA'ed by chip */ 895 dma_addr_t sdma_pad_phys; 896 /* for deallocation */ 897 size_t sdma_heads_size; 898 /* number from the chip */ 899 u32 chip_sdma_engines; 900 /* num used */ 901 u32 num_sdma; 902 /* array of engines sized by num_sdma */ 903 struct sdma_engine *per_sdma; 904 /* array of vl maps */ 905 struct sdma_vl_map __rcu *sdma_map; 906 /* SPC freeze waitqueue and variable */ 907 wait_queue_head_t sdma_unfreeze_wq; 908 atomic_t sdma_unfreeze_count; 909 910 u32 lcb_access_count; /* count of LCB users */ 911 912 /* common data between shared ASIC HFIs in this OS */ 913 struct hfi1_asic_data *asic_data; 914 915 /* mem-mapped pointer to base of PIO buffers */ 916 void __iomem *piobase; 917 /* 918 * write-combining mem-mapped pointer to base of RcvArray 919 * memory. 920 */ 921 void __iomem *rcvarray_wc; 922 /* 923 * credit return base - a per-NUMA range of DMA address that 924 * the chip will use to update the per-context free counter 925 */ 926 struct credit_return_base *cr_base; 927 928 /* send context numbers and sizes for each type */ 929 struct sc_config_sizes sc_sizes[SC_MAX]; 930 931 char *boardname; /* human readable board info */ 932 933 /* reset value */ 934 u64 z_int_counter; 935 u64 z_rcv_limit; 936 u64 z_send_schedule; 937 938 u64 __percpu *send_schedule; 939 /* number of receive contexts in use by the driver */ 940 u32 num_rcv_contexts; 941 /* number of pio send contexts in use by the driver */ 942 u32 num_send_contexts; 943 /* 944 * number of ctxts available for PSM open 945 */ 946 u32 freectxts; 947 /* total number of available user/PSM contexts */ 948 u32 num_user_contexts; 949 /* base receive interrupt timeout, in CSR units */ 950 u32 rcv_intr_timeout_csr; 951 952 u32 freezelen; /* max length of freezemsg */ 953 u64 __iomem *egrtidbase; 954 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ 955 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ 956 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 957 spinlock_t uctxt_lock; /* rcd and user context changes */ 958 struct mutex dc8051_lock; /* exclusive access to 8051 */ 959 struct workqueue_struct *update_cntr_wq; 960 struct work_struct update_cntr_work; 961 /* exclusive access to 8051 memory */ 962 spinlock_t dc8051_memlock; 963 int dc8051_timed_out; /* remember if the 8051 timed out */ 964 /* 965 * A page that will hold event notification bitmaps for all 966 * contexts. This page will be mapped into all processes. 967 */ 968 unsigned long *events; 969 /* 970 * per unit status, see also portdata statusp 971 * mapped read-only into user processes so they can get unit and 972 * IB link status cheaply 973 */ 974 struct hfi1_status *status; 975 976 /* revision register shadow */ 977 u64 revision; 978 /* Base GUID for device (network order) */ 979 u64 base_guid; 980 981 /* these are the "32 bit" regs */ 982 983 /* value we put in kr_rcvhdrsize */ 984 u32 rcvhdrsize; 985 /* number of receive contexts the chip supports */ 986 u32 chip_rcv_contexts; 987 /* number of receive array entries */ 988 u32 chip_rcv_array_count; 989 /* number of PIO send contexts the chip supports */ 990 u32 chip_send_contexts; 991 /* number of bytes in the PIO memory buffer */ 992 u32 chip_pio_mem_size; 993 /* number of bytes in the SDMA memory buffer */ 994 u32 chip_sdma_mem_size; 995 996 /* size of each rcvegrbuffer */ 997 u32 rcvegrbufsize; 998 /* log2 of above */ 999 u16 rcvegrbufsize_shift; 1000 /* both sides of the PCIe link are gen3 capable */ 1001 u8 link_gen3_capable; 1002 /* default link down value (poll/sleep) */ 1003 u8 link_default; 1004 /* localbus width (1, 2,4,8,16,32) from config space */ 1005 u32 lbus_width; 1006 /* localbus speed in MHz */ 1007 u32 lbus_speed; 1008 int unit; /* unit # of this chip */ 1009 int node; /* home node of this chip */ 1010 1011 /* save these PCI fields to restore after a reset */ 1012 u32 pcibar0; 1013 u32 pcibar1; 1014 u32 pci_rom; 1015 u16 pci_command; 1016 u16 pcie_devctl; 1017 u16 pcie_lnkctl; 1018 u16 pcie_devctl2; 1019 u32 pci_msix0; 1020 u32 pci_lnkctl3; 1021 u32 pci_tph2; 1022 1023 /* 1024 * ASCII serial number, from flash, large enough for original 1025 * all digit strings, and longer serial number format 1026 */ 1027 u8 serial[SERIAL_MAX]; 1028 /* human readable board version */ 1029 u8 boardversion[BOARD_VERS_MAX]; 1030 u8 lbus_info[32]; /* human readable localbus info */ 1031 /* chip major rev, from CceRevision */ 1032 u8 majrev; 1033 /* chip minor rev, from CceRevision */ 1034 u8 minrev; 1035 /* hardware ID */ 1036 u8 hfi1_id; 1037 /* implementation code */ 1038 u8 icode; 1039 /* vAU of this device */ 1040 u8 vau; 1041 /* vCU of this device */ 1042 u8 vcu; 1043 /* link credits of this device */ 1044 u16 link_credits; 1045 /* initial vl15 credits to use */ 1046 u16 vl15_init; 1047 1048 /* Misc small ints */ 1049 u8 n_krcv_queues; 1050 u8 qos_shift; 1051 1052 u16 irev; /* implementation revision */ 1053 u32 dc8051_ver; /* 8051 firmware version */ 1054 1055 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ 1056 struct platform_config platform_config; 1057 struct platform_config_cache pcfg_cache; 1058 1059 struct diag_client *diag_client; 1060 1061 /* MSI-X information */ 1062 struct hfi1_msix_entry *msix_entries; 1063 u32 num_msix_entries; 1064 u32 first_dyn_msix_idx; 1065 1066 /* INTx information */ 1067 u32 requested_intx_irq; /* did we request one? */ 1068 char intx_name[MAX_NAME_SIZE]; /* INTx name */ 1069 1070 /* general interrupt: mask of handled interrupts */ 1071 u64 gi_mask[CCE_NUM_INT_CSRS]; 1072 1073 struct rcv_array_data rcv_entries; 1074 1075 /* cycle length of PS* counters in HW (in picoseconds) */ 1076 u16 psxmitwait_check_rate; 1077 1078 /* 1079 * 64 bit synthetic counters 1080 */ 1081 struct timer_list synth_stats_timer; 1082 1083 /* 1084 * device counters 1085 */ 1086 char *cntrnames; 1087 size_t cntrnameslen; 1088 size_t ndevcntrs; 1089 u64 *cntrs; 1090 u64 *scntrs; 1091 1092 /* 1093 * remembered values for synthetic counters 1094 */ 1095 u64 last_tx; 1096 u64 last_rx; 1097 1098 /* 1099 * per-port counters 1100 */ 1101 size_t nportcntrs; 1102 char *portcntrnames; 1103 size_t portcntrnameslen; 1104 1105 struct err_info_rcvport err_info_rcvport; 1106 struct err_info_constraint err_info_rcv_constraint; 1107 struct err_info_constraint err_info_xmit_constraint; 1108 1109 atomic_t drop_packet; 1110 u8 do_drop; 1111 u8 err_info_uncorrectable; 1112 u8 err_info_fmconfig; 1113 1114 /* 1115 * Software counters for the status bits defined by the 1116 * associated error status registers 1117 */ 1118 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; 1119 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; 1120 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; 1121 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; 1122 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; 1123 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; 1124 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; 1125 1126 /* Software counter that spans all contexts */ 1127 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; 1128 /* Software counter that spans all DMA engines */ 1129 u64 sw_send_dma_eng_err_status_cnt[ 1130 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; 1131 /* Software counter that aggregates all cce_err_status errors */ 1132 u64 sw_cce_err_status_aggregate; 1133 /* Software counter that aggregates all bypass packet rcv errors */ 1134 u64 sw_rcv_bypass_packet_errors; 1135 /* receive interrupt function */ 1136 rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; 1137 1138 /* Save the enabled LCB error bits */ 1139 u64 lcb_err_en; 1140 1141 /* 1142 * Capability to have different send engines simply by changing a 1143 * pointer value. 1144 */ 1145 send_routine process_pio_send ____cacheline_aligned_in_smp; 1146 send_routine process_dma_send; 1147 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1148 u64 pbc, const void *from, size_t count); 1149 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx, 1150 struct hfi1_vnic_vport_info *vinfo, 1151 struct sk_buff *skb, u64 pbc, u8 plen); 1152 /* hfi1_pportdata, points to array of (physical) port-specific 1153 * data structs, indexed by pidx (0..n-1) 1154 */ 1155 struct hfi1_pportdata *pport; 1156 /* receive context data */ 1157 struct hfi1_ctxtdata **rcd; 1158 u64 __percpu *int_counter; 1159 /* device (not port) flags, basically device capabilities */ 1160 u16 flags; 1161 /* Number of physical ports available */ 1162 u8 num_pports; 1163 /* Lowest context number which can be used by user processes or VNIC */ 1164 u8 first_dyn_alloc_ctxt; 1165 /* adding a new field here would make it part of this cacheline */ 1166 1167 /* seqlock for sc2vl */ 1168 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp; 1169 u64 sc2vl[4]; 1170 /* receive interrupt functions */ 1171 rhf_rcv_function_ptr *rhf_rcv_function_map; 1172 u64 __percpu *rcv_limit; 1173 u16 rhf_offset; /* offset of RHF within receive header entry */ 1174 /* adding a new field here would make it part of this cacheline */ 1175 1176 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ 1177 u8 oui1; 1178 u8 oui2; 1179 u8 oui3; 1180 u8 dc_shutdown; 1181 1182 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1183 struct timer_list rcverr_timer; 1184 1185 wait_queue_head_t event_queue; 1186 1187 /* receive context tail dummy address */ 1188 __le64 *rcvhdrtail_dummy_kvaddr; 1189 dma_addr_t rcvhdrtail_dummy_dma; 1190 1191 u32 rcv_ovfl_cnt; 1192 /* Serialize ASPM enable/disable between multiple verbs contexts */ 1193 spinlock_t aspm_lock; 1194 /* Number of verbs contexts which have disabled ASPM */ 1195 atomic_t aspm_disabled_cnt; 1196 /* Keeps track of user space clients */ 1197 atomic_t user_refcount; 1198 /* Used to wait for outstanding user space clients before dev removal */ 1199 struct completion user_comp; 1200 1201 bool eprom_available; /* true if EPROM is available for this device */ 1202 bool aspm_supported; /* Does HW support ASPM */ 1203 bool aspm_enabled; /* ASPM state: enabled/disabled */ 1204 struct rhashtable *sdma_rht; 1205 1206 struct kobject kobj; 1207 1208 /* vnic data */ 1209 struct hfi1_vnic_data vnic; 1210 }; 1211 1212 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare) 1213 { 1214 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES; 1215 } 1216 1217 /* 8051 firmware version helper */ 1218 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c)) 1219 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16) 1220 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8) 1221 #define dc8051_ver_patch(a) ((a) & 0x0000ff) 1222 1223 /* f_put_tid types */ 1224 #define PT_EXPECTED 0 1225 #define PT_EAGER 1 1226 #define PT_INVALID 2 1227 1228 struct tid_rb_node; 1229 struct mmu_rb_node; 1230 struct mmu_rb_handler; 1231 1232 /* Private data for file operations */ 1233 struct hfi1_filedata { 1234 struct hfi1_devdata *dd; 1235 struct hfi1_ctxtdata *uctxt; 1236 struct hfi1_user_sdma_comp_q *cq; 1237 struct hfi1_user_sdma_pkt_q *pq; 1238 u16 subctxt; 1239 /* for cpu affinity; -1 if none */ 1240 int rec_cpu_num; 1241 u32 tid_n_pinned; 1242 struct mmu_rb_handler *handler; 1243 struct tid_rb_node **entry_to_rb; 1244 spinlock_t tid_lock; /* protect tid_[limit,used] counters */ 1245 u32 tid_limit; 1246 u32 tid_used; 1247 u32 *invalid_tids; 1248 u32 invalid_tid_idx; 1249 /* protect invalid_tids array and invalid_tid_idx */ 1250 spinlock_t invalid_lock; 1251 struct mm_struct *mm; 1252 }; 1253 1254 extern struct list_head hfi1_dev_list; 1255 extern spinlock_t hfi1_devs_lock; 1256 struct hfi1_devdata *hfi1_lookup(int unit); 1257 extern u32 hfi1_cpulist_count; 1258 extern unsigned long *hfi1_cpulist; 1259 1260 int hfi1_init(struct hfi1_devdata *dd, int reinit); 1261 int hfi1_count_active_units(void); 1262 1263 int hfi1_diag_add(struct hfi1_devdata *dd); 1264 void hfi1_diag_remove(struct hfi1_devdata *dd); 1265 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); 1266 1267 void handle_user_interrupt(struct hfi1_ctxtdata *rcd); 1268 1269 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); 1270 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd); 1271 int hfi1_create_ctxts(struct hfi1_devdata *dd); 1272 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt, 1273 int numa); 1274 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, 1275 struct hfi1_devdata *dd, u8 hw_pidx, u8 port); 1276 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); 1277 1278 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread); 1279 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread); 1280 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread); 1281 void set_all_slowpath(struct hfi1_devdata *dd); 1282 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd); 1283 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd); 1284 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd); 1285 1286 extern const struct pci_device_id hfi1_pci_tbl[]; 1287 1288 /* receive packet handler dispositions */ 1289 #define RCV_PKT_OK 0x0 /* keep going */ 1290 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ 1291 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ 1292 1293 /* calculate the current RHF address */ 1294 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) 1295 { 1296 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset; 1297 } 1298 1299 int hfi1_reset_device(int); 1300 1301 /* return the driver's idea of the logical OPA port state */ 1302 static inline u32 driver_lstate(struct hfi1_pportdata *ppd) 1303 { 1304 /* 1305 * The driver does some processing from the time the logical 1306 * link state is at INIT to the time the SM can be notified 1307 * as such. Return IB_PORT_DOWN until the software state 1308 * is ready. 1309 */ 1310 if (ppd->lstate == IB_PORT_INIT && !(ppd->host_link_state & HLS_UP)) 1311 return IB_PORT_DOWN; 1312 else 1313 return ppd->lstate; 1314 } 1315 1316 void receive_interrupt_work(struct work_struct *work); 1317 1318 /* extract service channel from header and rhf */ 1319 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf) 1320 { 1321 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4); 1322 } 1323 1324 #define HFI1_JKEY_WIDTH 16 1325 #define HFI1_JKEY_MASK (BIT(16) - 1) 1326 #define HFI1_ADMIN_JKEY_RANGE 32 1327 1328 /* 1329 * J_KEYs are split and allocated in the following groups: 1330 * 0 - 31 - users with administrator privileges 1331 * 32 - 63 - kernel protocols using KDETH packets 1332 * 64 - 65535 - all other users using KDETH packets 1333 */ 1334 static inline u16 generate_jkey(kuid_t uid) 1335 { 1336 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK; 1337 1338 if (capable(CAP_SYS_ADMIN)) 1339 jkey &= HFI1_ADMIN_JKEY_RANGE - 1; 1340 else if (jkey < 64) 1341 jkey |= BIT(HFI1_JKEY_WIDTH - 1); 1342 1343 return jkey; 1344 } 1345 1346 /* 1347 * active_egress_rate 1348 * 1349 * returns the active egress rate in units of [10^6 bits/sec] 1350 */ 1351 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) 1352 { 1353 u16 link_speed = ppd->link_speed_active; 1354 u16 link_width = ppd->link_width_active; 1355 u32 egress_rate; 1356 1357 if (link_speed == OPA_LINK_SPEED_25G) 1358 egress_rate = 25000; 1359 else /* assume OPA_LINK_SPEED_12_5G */ 1360 egress_rate = 12500; 1361 1362 switch (link_width) { 1363 case OPA_LINK_WIDTH_4X: 1364 egress_rate *= 4; 1365 break; 1366 case OPA_LINK_WIDTH_3X: 1367 egress_rate *= 3; 1368 break; 1369 case OPA_LINK_WIDTH_2X: 1370 egress_rate *= 2; 1371 break; 1372 default: 1373 /* assume IB_WIDTH_1X */ 1374 break; 1375 } 1376 1377 return egress_rate; 1378 } 1379 1380 /* 1381 * egress_cycles 1382 * 1383 * Returns the number of 'fabric clock cycles' to egress a packet 1384 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock 1385 * rate is (approximately) 805 MHz, the units of the returned value 1386 * are (1/805 MHz). 1387 */ 1388 static inline u32 egress_cycles(u32 len, u32 rate) 1389 { 1390 u32 cycles; 1391 1392 /* 1393 * cycles is: 1394 * 1395 * (length) [bits] / (rate) [bits/sec] 1396 * --------------------------------------------------- 1397 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] 1398 */ 1399 1400 cycles = len * 8; /* bits */ 1401 cycles *= 805; 1402 cycles /= rate; 1403 1404 return cycles; 1405 } 1406 1407 void set_link_ipg(struct hfi1_pportdata *ppd); 1408 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn, 1409 u32 rqpn, u8 svc_type); 1410 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, 1411 u32 pkey, u32 slid, u32 dlid, u8 sc5, 1412 const struct ib_grh *old_grh); 1413 #define PKEY_CHECK_INVALID -1 1414 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth, 1415 u8 sc5, int8_t s_pkey_index); 1416 1417 #define PACKET_EGRESS_TIMEOUT 350 1418 static inline void pause_for_credit_return(struct hfi1_devdata *dd) 1419 { 1420 /* Pause at least 1us, to ensure chip returns all credits */ 1421 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; 1422 1423 udelay(usec ? usec : 1); 1424 } 1425 1426 /** 1427 * sc_to_vlt() reverse lookup sc to vl 1428 * @dd - devdata 1429 * @sc5 - 5 bit sc 1430 */ 1431 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) 1432 { 1433 unsigned seq; 1434 u8 rval; 1435 1436 if (sc5 >= OPA_MAX_SCS) 1437 return (u8)(0xff); 1438 1439 do { 1440 seq = read_seqbegin(&dd->sc2vl_lock); 1441 rval = *(((u8 *)dd->sc2vl) + sc5); 1442 } while (read_seqretry(&dd->sc2vl_lock, seq)); 1443 1444 return rval; 1445 } 1446 1447 #define PKEY_MEMBER_MASK 0x8000 1448 #define PKEY_LOW_15_MASK 0x7fff 1449 1450 /* 1451 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent 1452 * being an entry from the ingress partition key table), return 0 1453 * otherwise. Use the matching criteria for ingress partition keys 1454 * specified in the OPAv1 spec., section 9.10.14. 1455 */ 1456 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) 1457 { 1458 u16 mkey = pkey & PKEY_LOW_15_MASK; 1459 u16 ment = ent & PKEY_LOW_15_MASK; 1460 1461 if (mkey == ment) { 1462 /* 1463 * If pkey[15] is clear (limited partition member), 1464 * is bit 15 in the corresponding table element 1465 * clear (limited member)? 1466 */ 1467 if (!(pkey & PKEY_MEMBER_MASK)) 1468 return !!(ent & PKEY_MEMBER_MASK); 1469 return 1; 1470 } 1471 return 0; 1472 } 1473 1474 /* 1475 * ingress_pkey_table_search - search the entire pkey table for 1476 * an entry which matches 'pkey'. return 0 if a match is found, 1477 * and 1 otherwise. 1478 */ 1479 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) 1480 { 1481 int i; 1482 1483 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1484 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1485 return 0; 1486 } 1487 return 1; 1488 } 1489 1490 /* 1491 * ingress_pkey_table_fail - record a failure of ingress pkey validation, 1492 * i.e., increment port_rcv_constraint_errors for the port, and record 1493 * the 'error info' for this failure. 1494 */ 1495 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, 1496 u16 slid) 1497 { 1498 struct hfi1_devdata *dd = ppd->dd; 1499 1500 incr_cntr64(&ppd->port_rcv_constraint_errors); 1501 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { 1502 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; 1503 dd->err_info_rcv_constraint.slid = slid; 1504 dd->err_info_rcv_constraint.pkey = pkey; 1505 } 1506 } 1507 1508 /* 1509 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 1510 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx 1511 * is a hint as to the best place in the partition key table to begin 1512 * searching. This function should not be called on the data path because 1513 * of performance reasons. On datapath pkey check is expected to be done 1514 * by HW and rcv_pkey_check function should be called instead. 1515 */ 1516 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1517 u8 sc5, u8 idx, u16 slid) 1518 { 1519 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1520 return 0; 1521 1522 /* If SC15, pkey[0:14] must be 0x7fff */ 1523 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1524 goto bad; 1525 1526 /* Is the pkey = 0x0, or 0x8000? */ 1527 if ((pkey & PKEY_LOW_15_MASK) == 0) 1528 goto bad; 1529 1530 /* The most likely matching pkey has index 'idx' */ 1531 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) 1532 return 0; 1533 1534 /* no match - try the whole table */ 1535 if (!ingress_pkey_table_search(ppd, pkey)) 1536 return 0; 1537 1538 bad: 1539 ingress_pkey_table_fail(ppd, pkey, slid); 1540 return 1; 1541 } 1542 1543 /* 1544 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 1545 * otherwise. It only ensures pkey is vlid for QP0. This function 1546 * should be called on the data path instead of ingress_pkey_check 1547 * as on data path, pkey check is done by HW (except for QP0). 1548 */ 1549 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1550 u8 sc5, u16 slid) 1551 { 1552 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1553 return 0; 1554 1555 /* If SC15, pkey[0:14] must be 0x7fff */ 1556 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1557 goto bad; 1558 1559 return 0; 1560 bad: 1561 ingress_pkey_table_fail(ppd, pkey, slid); 1562 return 1; 1563 } 1564 1565 /* MTU handling */ 1566 1567 /* MTU enumeration, 256-4k match IB */ 1568 #define OPA_MTU_0 0 1569 #define OPA_MTU_256 1 1570 #define OPA_MTU_512 2 1571 #define OPA_MTU_1024 3 1572 #define OPA_MTU_2048 4 1573 #define OPA_MTU_4096 5 1574 1575 u32 lrh_max_header_bytes(struct hfi1_devdata *dd); 1576 int mtu_to_enum(u32 mtu, int default_if_bad); 1577 u16 enum_to_mtu(int mtu); 1578 static inline int valid_ib_mtu(unsigned int mtu) 1579 { 1580 return mtu == 256 || mtu == 512 || 1581 mtu == 1024 || mtu == 2048 || 1582 mtu == 4096; 1583 } 1584 1585 static inline int valid_opa_max_mtu(unsigned int mtu) 1586 { 1587 return mtu >= 2048 && 1588 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); 1589 } 1590 1591 int set_mtu(struct hfi1_pportdata *ppd); 1592 1593 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc); 1594 void hfi1_disable_after_error(struct hfi1_devdata *dd); 1595 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit); 1596 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode); 1597 1598 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t); 1599 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t); 1600 1601 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); 1602 void reset_link_credits(struct hfi1_devdata *dd); 1603 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); 1604 1605 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); 1606 1607 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) 1608 { 1609 return ppd->dd; 1610 } 1611 1612 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) 1613 { 1614 return container_of(dev, struct hfi1_devdata, verbs_dev); 1615 } 1616 1617 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) 1618 { 1619 return dd_from_dev(to_idev(ibdev)); 1620 } 1621 1622 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) 1623 { 1624 return container_of(ibp, struct hfi1_pportdata, ibport_data); 1625 } 1626 1627 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) 1628 { 1629 return container_of(rdi, struct hfi1_ibdev, rdi); 1630 } 1631 1632 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) 1633 { 1634 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1635 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1636 1637 WARN_ON(pidx >= dd->num_pports); 1638 return &dd->pport[pidx].ibport_data; 1639 } 1640 1641 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd) 1642 { 1643 return &rcd->ppd->ibport_data; 1644 } 1645 1646 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt, 1647 bool do_cnp); 1648 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt, 1649 bool do_cnp) 1650 { 1651 struct ib_other_headers *ohdr = pkt->ohdr; 1652 u32 bth1; 1653 1654 bth1 = be32_to_cpu(ohdr->bth[1]); 1655 if (unlikely(bth1 & (IB_BECN_SMASK | IB_FECN_SMASK))) { 1656 hfi1_process_ecn_slowpath(qp, pkt, do_cnp); 1657 return !!(bth1 & IB_FECN_SMASK); 1658 } 1659 return false; 1660 } 1661 1662 /* 1663 * Return the indexed PKEY from the port PKEY table. 1664 */ 1665 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) 1666 { 1667 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1668 u16 ret; 1669 1670 if (index >= ARRAY_SIZE(ppd->pkeys)) 1671 ret = 0; 1672 else 1673 ret = ppd->pkeys[index]; 1674 1675 return ret; 1676 } 1677 1678 /* 1679 * Return the indexed GUID from the port GUIDs table. 1680 */ 1681 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index) 1682 { 1683 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1684 1685 WARN_ON(index >= HFI1_GUIDS_PER_PORT); 1686 return cpu_to_be64(ppd->guids[index]); 1687 } 1688 1689 /* 1690 * Called by readers of cc_state only, must call under rcu_read_lock(). 1691 */ 1692 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) 1693 { 1694 return rcu_dereference(ppd->cc_state); 1695 } 1696 1697 /* 1698 * Called by writers of cc_state only, must call under cc_state_lock. 1699 */ 1700 static inline 1701 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd) 1702 { 1703 return rcu_dereference_protected(ppd->cc_state, 1704 lockdep_is_held(&ppd->cc_state_lock)); 1705 } 1706 1707 /* 1708 * values for dd->flags (_device_ related flags) 1709 */ 1710 #define HFI1_INITTED 0x1 /* chip and driver up and initted */ 1711 #define HFI1_PRESENT 0x2 /* chip accesses can be done */ 1712 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ 1713 #define HFI1_HAS_SDMA_TIMEOUT 0x8 1714 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ 1715 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ 1716 1717 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1718 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) 1719 1720 /* ctxt_flag bit offsets */ 1721 /* base context has not finished initializing */ 1722 #define HFI1_CTXT_BASE_UNINIT 1 1723 /* base context initaliation failed */ 1724 #define HFI1_CTXT_BASE_FAILED 2 1725 /* waiting for a packet to arrive */ 1726 #define HFI1_CTXT_WAITING_RCV 3 1727 /* waiting for an urgent packet to arrive */ 1728 #define HFI1_CTXT_WAITING_URG 4 1729 1730 /* free up any allocated data at closes */ 1731 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, 1732 const struct pci_device_id *ent); 1733 void hfi1_free_devdata(struct hfi1_devdata *dd); 1734 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra); 1735 1736 /* LED beaconing functions */ 1737 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, 1738 unsigned int timeoff); 1739 void shutdown_led_override(struct hfi1_pportdata *ppd); 1740 1741 #define HFI1_CREDIT_RETURN_RATE (100) 1742 1743 /* 1744 * The number of words for the KDETH protocol field. If this is 1745 * larger then the actual field used, then part of the payload 1746 * will be in the header. 1747 * 1748 * Optimally, we want this sized so that a typical case will 1749 * use full cache lines. The typical local KDETH header would 1750 * be: 1751 * 1752 * Bytes Field 1753 * 8 LRH 1754 * 12 BHT 1755 * ?? KDETH 1756 * 8 RHF 1757 * --- 1758 * 28 + KDETH 1759 * 1760 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS 1761 */ 1762 #define DEFAULT_RCVHDRSIZE 9 1763 1764 /* 1765 * Maximal header byte count: 1766 * 1767 * Bytes Field 1768 * 8 LRH 1769 * 40 GRH (optional) 1770 * 12 BTH 1771 * ?? KDETH 1772 * 8 RHF 1773 * --- 1774 * 68 + KDETH 1775 * 1776 * We also want to maintain a cache line alignment to assist DMA'ing 1777 * of the header bytes. Round up to a good size. 1778 */ 1779 #define DEFAULT_RCVHDR_ENTSIZE 32 1780 1781 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm, 1782 u32 nlocked, u32 npages); 1783 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr, 1784 size_t npages, bool writable, struct page **pages); 1785 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p, 1786 size_t npages, bool dirty); 1787 1788 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1789 { 1790 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; 1791 } 1792 1793 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1794 { 1795 /* 1796 * volatile because it's a DMA target from the chip, routine is 1797 * inlined, and don't want register caching or reordering. 1798 */ 1799 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); 1800 } 1801 1802 /* 1803 * sysfs interface. 1804 */ 1805 1806 extern const char ib_hfi1_version[]; 1807 1808 int hfi1_device_create(struct hfi1_devdata *dd); 1809 void hfi1_device_remove(struct hfi1_devdata *dd); 1810 1811 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, 1812 struct kobject *kobj); 1813 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd); 1814 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd); 1815 /* Hook for sysfs read of QSFP */ 1816 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); 1817 1818 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent); 1819 void hfi1_pcie_cleanup(struct pci_dev *pdev); 1820 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev); 1821 void hfi1_pcie_ddcleanup(struct hfi1_devdata *); 1822 int pcie_speeds(struct hfi1_devdata *dd); 1823 void request_msix(struct hfi1_devdata *dd, u32 *nent, 1824 struct hfi1_msix_entry *entry); 1825 void hfi1_enable_intx(struct pci_dev *pdev); 1826 void restore_pci_variables(struct hfi1_devdata *dd); 1827 int do_pcie_gen3_transition(struct hfi1_devdata *dd); 1828 int parse_platform_config(struct hfi1_devdata *dd); 1829 int get_platform_config_field(struct hfi1_devdata *dd, 1830 enum platform_config_table_type_encoding 1831 table_type, int table_index, int field_index, 1832 u32 *data, u32 len); 1833 1834 const char *get_unit_name(int unit); 1835 const char *get_card_name(struct rvt_dev_info *rdi); 1836 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); 1837 1838 /* 1839 * Flush write combining store buffers (if present) and perform a write 1840 * barrier. 1841 */ 1842 static inline void flush_wc(void) 1843 { 1844 asm volatile("sfence" : : : "memory"); 1845 } 1846 1847 void handle_eflags(struct hfi1_packet *packet); 1848 int process_receive_ib(struct hfi1_packet *packet); 1849 int process_receive_bypass(struct hfi1_packet *packet); 1850 int process_receive_error(struct hfi1_packet *packet); 1851 int kdeth_process_expected(struct hfi1_packet *packet); 1852 int kdeth_process_eager(struct hfi1_packet *packet); 1853 int process_receive_invalid(struct hfi1_packet *packet); 1854 1855 /* global module parameter variables */ 1856 extern unsigned int hfi1_max_mtu; 1857 extern unsigned int hfi1_cu; 1858 extern unsigned int user_credit_return_threshold; 1859 extern int num_user_contexts; 1860 extern unsigned long n_krcvqs; 1861 extern uint krcvqs[]; 1862 extern int krcvqsset; 1863 extern uint kdeth_qp; 1864 extern uint loopback; 1865 extern uint quick_linkup; 1866 extern uint rcv_intr_timeout; 1867 extern uint rcv_intr_count; 1868 extern uint rcv_intr_dynamic; 1869 extern ushort link_crc_mask; 1870 1871 extern struct mutex hfi1_mutex; 1872 1873 /* Number of seconds before our card status check... */ 1874 #define STATUS_TIMEOUT 60 1875 1876 #define DRIVER_NAME "hfi1" 1877 #define HFI1_USER_MINOR_BASE 0 1878 #define HFI1_TRACE_MINOR 127 1879 #define HFI1_NMINORS 255 1880 1881 #define PCI_VENDOR_ID_INTEL 0x8086 1882 #define PCI_DEVICE_ID_INTEL0 0x24f0 1883 #define PCI_DEVICE_ID_INTEL1 0x24f1 1884 1885 #define HFI1_PKT_USER_SC_INTEGRITY \ 1886 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ 1887 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \ 1888 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ 1889 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) 1890 1891 #define HFI1_PKT_KERNEL_SC_INTEGRITY \ 1892 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) 1893 1894 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, 1895 u16 ctxt_type) 1896 { 1897 u64 base_sc_integrity; 1898 1899 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ 1900 if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) 1901 return 0; 1902 1903 base_sc_integrity = 1904 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1905 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 1906 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1907 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1908 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1909 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 1910 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1911 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1912 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1913 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 1914 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1915 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1916 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 1917 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 1918 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 1919 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1920 1921 if (ctxt_type == SC_USER) 1922 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY; 1923 else 1924 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; 1925 1926 /* turn on send-side job key checks if !A0 */ 1927 if (!is_ax(dd)) 1928 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1929 1930 return base_sc_integrity; 1931 } 1932 1933 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) 1934 { 1935 u64 base_sdma_integrity; 1936 1937 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ 1938 if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) 1939 return 0; 1940 1941 base_sdma_integrity = 1942 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1943 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1944 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1945 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1946 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1947 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1948 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1949 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 1950 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1951 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1952 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 1953 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 1954 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 1955 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1956 1957 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) 1958 base_sdma_integrity |= 1959 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK; 1960 1961 /* turn on send-side job key checks if !A0 */ 1962 if (!is_ax(dd)) 1963 base_sdma_integrity |= 1964 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1965 1966 return base_sdma_integrity; 1967 } 1968 1969 /* 1970 * hfi1_early_err is used (only!) to print early errors before devdata is 1971 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1972 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is 1973 * the same as dd_dev_err, but is used when the message really needs 1974 * the IB port# to be definitive as to what's happening.. 1975 */ 1976 #define hfi1_early_err(dev, fmt, ...) \ 1977 dev_err(dev, fmt, ##__VA_ARGS__) 1978 1979 #define hfi1_early_info(dev, fmt, ...) \ 1980 dev_info(dev, fmt, ##__VA_ARGS__) 1981 1982 #define dd_dev_emerg(dd, fmt, ...) \ 1983 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ 1984 get_unit_name((dd)->unit), ##__VA_ARGS__) 1985 #define dd_dev_err(dd, fmt, ...) \ 1986 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1987 get_unit_name((dd)->unit), ##__VA_ARGS__) 1988 #define dd_dev_warn(dd, fmt, ...) \ 1989 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1990 get_unit_name((dd)->unit), ##__VA_ARGS__) 1991 1992 #define dd_dev_warn_ratelimited(dd, fmt, ...) \ 1993 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 1994 get_unit_name((dd)->unit), ##__VA_ARGS__) 1995 1996 #define dd_dev_info(dd, fmt, ...) \ 1997 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ 1998 get_unit_name((dd)->unit), ##__VA_ARGS__) 1999 2000 #define dd_dev_info_ratelimited(dd, fmt, ...) \ 2001 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 2002 get_unit_name((dd)->unit), ##__VA_ARGS__) 2003 2004 #define dd_dev_dbg(dd, fmt, ...) \ 2005 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ 2006 get_unit_name((dd)->unit), ##__VA_ARGS__) 2007 2008 #define hfi1_dev_porterr(dd, port, fmt, ...) \ 2009 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ 2010 get_unit_name((dd)->unit), (port), ##__VA_ARGS__) 2011 2012 /* 2013 * this is used for formatting hw error messages... 2014 */ 2015 struct hfi1_hwerror_msgs { 2016 u64 mask; 2017 const char *msg; 2018 size_t sz; 2019 }; 2020 2021 /* in intr.c... */ 2022 void hfi1_format_hwerrors(u64 hwerrs, 2023 const struct hfi1_hwerror_msgs *hwerrmsgs, 2024 size_t nhwerrmsgs, char *msg, size_t lmsg); 2025 2026 #define USER_OPCODE_CHECK_VAL 0xC0 2027 #define USER_OPCODE_CHECK_MASK 0xC0 2028 #define OPCODE_CHECK_VAL_DISABLED 0x0 2029 #define OPCODE_CHECK_MASK_DISABLED 0x0 2030 2031 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) 2032 { 2033 struct hfi1_pportdata *ppd; 2034 int i; 2035 2036 dd->z_int_counter = get_all_cpu_total(dd->int_counter); 2037 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); 2038 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); 2039 2040 ppd = (struct hfi1_pportdata *)(dd + 1); 2041 for (i = 0; i < dd->num_pports; i++, ppd++) { 2042 ppd->ibport_data.rvp.z_rc_acks = 2043 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); 2044 ppd->ibport_data.rvp.z_rc_qacks = 2045 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); 2046 } 2047 } 2048 2049 /* Control LED state */ 2050 static inline void setextled(struct hfi1_devdata *dd, u32 on) 2051 { 2052 if (on) 2053 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); 2054 else 2055 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); 2056 } 2057 2058 /* return the i2c resource given the target */ 2059 static inline u32 i2c_target(u32 target) 2060 { 2061 return target ? CR_I2C2 : CR_I2C1; 2062 } 2063 2064 /* return the i2c chain chip resource that this HFI uses for QSFP */ 2065 static inline u32 qsfp_resource(struct hfi1_devdata *dd) 2066 { 2067 return i2c_target(dd->hfi1_id); 2068 } 2069 2070 /* Is this device integrated or discrete? */ 2071 static inline bool is_integrated(struct hfi1_devdata *dd) 2072 { 2073 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1; 2074 } 2075 2076 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); 2077 2078 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev)) 2079 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev)) 2080 2081 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype } 2082 #define show_packettype(etype) \ 2083 __print_symbolic(etype, \ 2084 packettype_name(EXPECTED), \ 2085 packettype_name(EAGER), \ 2086 packettype_name(IB), \ 2087 packettype_name(ERROR), \ 2088 packettype_name(BYPASS)) 2089 2090 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode } 2091 #define show_ib_opcode(opcode) \ 2092 __print_symbolic(opcode, \ 2093 ib_opcode_name(RC_SEND_FIRST), \ 2094 ib_opcode_name(RC_SEND_MIDDLE), \ 2095 ib_opcode_name(RC_SEND_LAST), \ 2096 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \ 2097 ib_opcode_name(RC_SEND_ONLY), \ 2098 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \ 2099 ib_opcode_name(RC_RDMA_WRITE_FIRST), \ 2100 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \ 2101 ib_opcode_name(RC_RDMA_WRITE_LAST), \ 2102 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ 2103 ib_opcode_name(RC_RDMA_WRITE_ONLY), \ 2104 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ 2105 ib_opcode_name(RC_RDMA_READ_REQUEST), \ 2106 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \ 2107 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \ 2108 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \ 2109 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \ 2110 ib_opcode_name(RC_ACKNOWLEDGE), \ 2111 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \ 2112 ib_opcode_name(RC_COMPARE_SWAP), \ 2113 ib_opcode_name(RC_FETCH_ADD), \ 2114 ib_opcode_name(UC_SEND_FIRST), \ 2115 ib_opcode_name(UC_SEND_MIDDLE), \ 2116 ib_opcode_name(UC_SEND_LAST), \ 2117 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \ 2118 ib_opcode_name(UC_SEND_ONLY), \ 2119 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \ 2120 ib_opcode_name(UC_RDMA_WRITE_FIRST), \ 2121 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \ 2122 ib_opcode_name(UC_RDMA_WRITE_LAST), \ 2123 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ 2124 ib_opcode_name(UC_RDMA_WRITE_ONLY), \ 2125 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ 2126 ib_opcode_name(UD_SEND_ONLY), \ 2127 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \ 2128 ib_opcode_name(CNP)) 2129 #endif /* _HFI1_KERNEL_H */ 2130