1 #ifndef _HFI1_KERNEL_H 2 #define _HFI1_KERNEL_H 3 /* 4 * Copyright(c) 2015, 2016 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 #include <linux/interrupt.h> 51 #include <linux/pci.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/mutex.h> 54 #include <linux/list.h> 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/io.h> 58 #include <linux/fs.h> 59 #include <linux/completion.h> 60 #include <linux/kref.h> 61 #include <linux/sched.h> 62 #include <linux/cdev.h> 63 #include <linux/delay.h> 64 #include <linux/kthread.h> 65 #include <linux/i2c.h> 66 #include <linux/i2c-algo-bit.h> 67 #include <rdma/ib_hdrs.h> 68 #include <linux/rhashtable.h> 69 #include <rdma/rdma_vt.h> 70 71 #include "chip_registers.h" 72 #include "common.h" 73 #include "verbs.h" 74 #include "pio.h" 75 #include "chip.h" 76 #include "mad.h" 77 #include "qsfp.h" 78 #include "platform.h" 79 #include "affinity.h" 80 81 /* bumped 1 from s/w major version of TrueScale */ 82 #define HFI1_CHIP_VERS_MAJ 3U 83 84 /* don't care about this except printing */ 85 #define HFI1_CHIP_VERS_MIN 0U 86 87 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 88 #define HFI1_OUI 0x001175 89 #define HFI1_OUI_LSB 40 90 91 #define DROP_PACKET_OFF 0 92 #define DROP_PACKET_ON 1 93 94 extern unsigned long hfi1_cap_mask; 95 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) 96 #define HFI1_CAP_UGET_MASK(mask, cap) \ 97 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) 98 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) 99 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) 100 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) 101 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) 102 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ 103 HFI1_CAP_MISC_MASK) 104 /* Offline Disabled Reason is 4-bits */ 105 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) 106 107 /* 108 * Control context is always 0 and handles the error packets. 109 * It also handles the VL15 and multicast packets. 110 */ 111 #define HFI1_CTRL_CTXT 0 112 113 /* 114 * Driver context will store software counters for each of the events 115 * associated with these status registers 116 */ 117 #define NUM_CCE_ERR_STATUS_COUNTERS 41 118 #define NUM_RCV_ERR_STATUS_COUNTERS 64 119 #define NUM_MISC_ERR_STATUS_COUNTERS 13 120 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 121 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 122 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 123 #define NUM_SEND_ERR_STATUS_COUNTERS 3 124 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 125 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 126 127 /* 128 * per driver stats, either not device nor port-specific, or 129 * summed over all of the devices and ports. 130 * They are described by name via ipathfs filesystem, so layout 131 * and number of elements can change without breaking compatibility. 132 * If members are added or deleted hfi1_statnames[] in debugfs.c must 133 * change to match. 134 */ 135 struct hfi1_ib_stats { 136 __u64 sps_ints; /* number of interrupts handled */ 137 __u64 sps_errints; /* number of error interrupts */ 138 __u64 sps_txerrs; /* tx-related packet errors */ 139 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 140 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 141 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 142 __u64 sps_ctxts; /* number of contexts currently open */ 143 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 144 __u64 sps_buffull; 145 __u64 sps_hdrfull; 146 }; 147 148 extern struct hfi1_ib_stats hfi1_stats; 149 extern const struct pci_error_handlers hfi1_pci_err_handler; 150 151 /* 152 * First-cut criterion for "device is active" is 153 * two thousand dwords combined Tx, Rx traffic per 154 * 5-second interval. SMA packets are 64 dwords, 155 * and occur "a few per second", presumably each way. 156 */ 157 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) 158 159 /* 160 * Below contains all data related to a single context (formerly called port). 161 */ 162 163 #ifdef CONFIG_DEBUG_FS 164 struct hfi1_opcode_stats_perctx; 165 #endif 166 167 struct ctxt_eager_bufs { 168 ssize_t size; /* total size of eager buffers */ 169 u32 count; /* size of buffers array */ 170 u32 numbufs; /* number of buffers allocated */ 171 u32 alloced; /* number of rcvarray entries used */ 172 u32 rcvtid_size; /* size of each eager rcv tid */ 173 u32 threshold; /* head update threshold */ 174 struct eager_buffer { 175 void *addr; 176 dma_addr_t dma; 177 ssize_t len; 178 } *buffers; 179 struct { 180 void *addr; 181 dma_addr_t dma; 182 } *rcvtids; 183 }; 184 185 struct exp_tid_set { 186 struct list_head list; 187 u32 count; 188 }; 189 190 struct hfi1_ctxtdata { 191 /* shadow the ctxt's RcvCtrl register */ 192 u64 rcvctrl; 193 /* rcvhdrq base, needs mmap before useful */ 194 void *rcvhdrq; 195 /* kernel virtual address where hdrqtail is updated */ 196 volatile __le64 *rcvhdrtail_kvaddr; 197 /* 198 * Shared page for kernel to signal user processes that send buffers 199 * need disarming. The process should call HFI1_CMD_DISARM_BUFS 200 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 201 */ 202 unsigned long *user_event_mask; 203 /* when waiting for rcv or pioavail */ 204 wait_queue_head_t wait; 205 /* rcvhdrq size (for freeing) */ 206 size_t rcvhdrq_size; 207 /* number of rcvhdrq entries */ 208 u16 rcvhdrq_cnt; 209 /* size of each of the rcvhdrq entries */ 210 u16 rcvhdrqentsize; 211 /* mmap of hdrq, must fit in 44 bits */ 212 dma_addr_t rcvhdrq_dma; 213 dma_addr_t rcvhdrqtailaddr_dma; 214 struct ctxt_eager_bufs egrbufs; 215 /* this receive context's assigned PIO ACK send context */ 216 struct send_context *sc; 217 218 /* dynamic receive available interrupt timeout */ 219 u32 rcvavail_timeout; 220 /* 221 * number of opens (including slave sub-contexts) on this instance 222 * (ignoring forks, dup, etc. for now) 223 */ 224 int cnt; 225 /* 226 * how much space to leave at start of eager TID entries for 227 * protocol use, on each TID 228 */ 229 /* instead of calculating it */ 230 unsigned ctxt; 231 /* non-zero if ctxt is being shared. */ 232 u16 subctxt_cnt; 233 /* non-zero if ctxt is being shared. */ 234 u16 subctxt_id; 235 u8 uuid[16]; 236 /* job key */ 237 u16 jkey; 238 /* number of RcvArray groups for this context. */ 239 u32 rcv_array_groups; 240 /* index of first eager TID entry. */ 241 u32 eager_base; 242 /* number of expected TID entries */ 243 u32 expected_count; 244 /* index of first expected TID entry. */ 245 u32 expected_base; 246 247 struct exp_tid_set tid_group_list; 248 struct exp_tid_set tid_used_list; 249 struct exp_tid_set tid_full_list; 250 251 /* lock protecting all Expected TID data */ 252 struct mutex exp_lock; 253 /* number of pio bufs for this ctxt (all procs, if shared) */ 254 u32 piocnt; 255 /* first pio buffer for this ctxt */ 256 u32 pio_base; 257 /* chip offset of PIO buffers for this ctxt */ 258 u32 piobufs; 259 /* per-context configuration flags */ 260 unsigned long flags; 261 /* per-context event flags for fileops/intr communication */ 262 unsigned long event_flags; 263 /* WAIT_RCV that timed out, no interrupt */ 264 u32 rcvwait_to; 265 /* WAIT_PIO that timed out, no interrupt */ 266 u32 piowait_to; 267 /* WAIT_RCV already happened, no wait */ 268 u32 rcvnowait; 269 /* WAIT_PIO already happened, no wait */ 270 u32 pionowait; 271 /* total number of polled urgent packets */ 272 u32 urgent; 273 /* saved total number of polled urgent packets for poll edge trigger */ 274 u32 urgent_poll; 275 /* same size as task_struct .comm[], command that opened context */ 276 char comm[TASK_COMM_LEN]; 277 /* so file ops can get at unit */ 278 struct hfi1_devdata *dd; 279 /* so functions that need physical port can get it easily */ 280 struct hfi1_pportdata *ppd; 281 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 282 void *subctxt_uregbase; 283 /* An array of pages for the eager receive buffers * N */ 284 void *subctxt_rcvegrbuf; 285 /* An array of pages for the eager header queue entries * N */ 286 void *subctxt_rcvhdr_base; 287 /* The version of the library which opened this ctxt */ 288 u32 userversion; 289 /* Bitmask of active slaves */ 290 u32 active_slaves; 291 /* Type of packets or conditions we want to poll for */ 292 u16 poll_type; 293 /* receive packet sequence counter */ 294 u8 seq_cnt; 295 u8 redirect_seq_cnt; 296 /* ctxt rcvhdrq head offset */ 297 u32 head; 298 u32 pkt_count; 299 /* QPs waiting for context processing */ 300 struct list_head qp_wait_list; 301 /* interrupt handling */ 302 u64 imask; /* clear interrupt mask */ 303 int ireg; /* clear interrupt register */ 304 unsigned numa_id; /* numa node of this context */ 305 /* verbs stats per CTX */ 306 struct hfi1_opcode_stats_perctx *opstats; 307 /* 308 * This is the kernel thread that will keep making 309 * progress on the user sdma requests behind the scenes. 310 * There is one per context (shared contexts use the master's). 311 */ 312 struct task_struct *progress; 313 struct list_head sdma_queues; 314 /* protect sdma queues */ 315 spinlock_t sdma_qlock; 316 317 /* Is ASPM interrupt supported for this context */ 318 bool aspm_intr_supported; 319 /* ASPM state (enabled/disabled) for this context */ 320 bool aspm_enabled; 321 /* Timer for re-enabling ASPM if interrupt activity quietens down */ 322 struct timer_list aspm_timer; 323 /* Lock to serialize between intr, timer intr and user threads */ 324 spinlock_t aspm_lock; 325 /* Is ASPM processing enabled for this context (in intr context) */ 326 bool aspm_intr_enable; 327 /* Last interrupt timestamp */ 328 ktime_t aspm_ts_last_intr; 329 /* Last timestamp at which we scheduled a timer for this context */ 330 ktime_t aspm_ts_timer_sched; 331 332 /* 333 * The interrupt handler for a particular receive context can vary 334 * throughout it's lifetime. This is not a lock protected data member so 335 * it must be updated atomically and the prev and new value must always 336 * be valid. Worst case is we process an extra interrupt and up to 64 337 * packets with the wrong interrupt handler. 338 */ 339 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); 340 }; 341 342 /* 343 * Represents a single packet at a high level. Put commonly computed things in 344 * here so we do not have to keep doing them over and over. The rule of thumb is 345 * if something is used one time to derive some value, store that something in 346 * here. If it is used multiple times, then store the result of that derivation 347 * in here. 348 */ 349 struct hfi1_packet { 350 void *ebuf; 351 void *hdr; 352 struct hfi1_ctxtdata *rcd; 353 __le32 *rhf_addr; 354 struct rvt_qp *qp; 355 struct ib_other_headers *ohdr; 356 u64 rhf; 357 u32 maxcnt; 358 u32 rhqoff; 359 u32 hdrqtail; 360 int numpkt; 361 u16 tlen; 362 u16 hlen; 363 s16 etail; 364 u16 rsize; 365 u8 updegr; 366 u8 rcv_flags; 367 u8 etype; 368 }; 369 370 /* 371 * Private data for snoop/capture support. 372 */ 373 struct hfi1_snoop_data { 374 int mode_flag; 375 struct cdev cdev; 376 struct device *class_dev; 377 /* protect snoop data */ 378 spinlock_t snoop_lock; 379 struct list_head queue; 380 wait_queue_head_t waitq; 381 void *filter_value; 382 int (*filter_callback)(void *hdr, void *data, void *value); 383 u64 dcc_cfg; /* saved value of DCC Cfg register */ 384 }; 385 386 /* snoop mode_flag values */ 387 #define HFI1_PORT_SNOOP_MODE 1U 388 #define HFI1_PORT_CAPTURE_MODE 2U 389 390 struct rvt_sge_state; 391 392 /* 393 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 394 * Mostly for MADs that set or query link parameters, also ipath 395 * config interfaces 396 */ 397 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 398 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ 399 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 400 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ 401 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 402 #define HFI1_IB_CFG_SPD 5 /* current Link spd */ 403 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 404 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 405 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 406 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 407 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ 408 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 409 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 410 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 411 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 412 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 413 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ 414 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ 415 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 416 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 417 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ 418 419 /* 420 * HFI or Host Link States 421 * 422 * These describe the states the driver thinks the logical and physical 423 * states are in. Used as an argument to set_link_state(). Implemented 424 * as bits for easy multi-state checking. The actual state can only be 425 * one. 426 */ 427 #define __HLS_UP_INIT_BP 0 428 #define __HLS_UP_ARMED_BP 1 429 #define __HLS_UP_ACTIVE_BP 2 430 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ 431 #define __HLS_DN_POLL_BP 4 432 #define __HLS_DN_DISABLE_BP 5 433 #define __HLS_DN_OFFLINE_BP 6 434 #define __HLS_VERIFY_CAP_BP 7 435 #define __HLS_GOING_UP_BP 8 436 #define __HLS_GOING_OFFLINE_BP 9 437 #define __HLS_LINK_COOLDOWN_BP 10 438 439 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) 440 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) 441 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) 442 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ 443 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) 444 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) 445 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) 446 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) 447 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) 448 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) 449 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) 450 451 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) 452 #define HLS_DOWN ~(HLS_UP) 453 454 /* use this MTU size if none other is given */ 455 #define HFI1_DEFAULT_ACTIVE_MTU 10240 456 /* use this MTU size as the default maximum */ 457 #define HFI1_DEFAULT_MAX_MTU 10240 458 /* default partition key */ 459 #define DEFAULT_PKEY 0xffff 460 461 /* 462 * Possible fabric manager config parameters for fm_{get,set}_table() 463 */ 464 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ 465 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ 466 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ 467 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ 468 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ 469 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ 470 471 /* 472 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 473 * these are bits so they can be combined, e.g. 474 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB 475 */ 476 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 477 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 478 #define HFI1_RCVCTRL_CTXT_ENB 0x04 479 #define HFI1_RCVCTRL_CTXT_DIS 0x08 480 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 481 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 482 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 483 #define HFI1_RCVCTRL_PKEY_DIS 0x80 484 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 485 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 486 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 487 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 488 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 489 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 490 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 491 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 492 493 /* partition enforcement flags */ 494 #define HFI1_PART_ENFORCE_IN 0x1 495 #define HFI1_PART_ENFORCE_OUT 0x2 496 497 /* how often we check for synthetic counter wrap around */ 498 #define SYNTH_CNT_TIME 2 499 500 /* Counter flags */ 501 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ 502 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ 503 #define CNTR_DISABLED 0x2 /* Disable this counter */ 504 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ 505 #define CNTR_VL 0x8 /* Per VL counter */ 506 #define CNTR_SDMA 0x10 507 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ 508 #define CNTR_MODE_W 0x0 509 #define CNTR_MODE_R 0x1 510 511 /* VLs Supported/Operational */ 512 #define HFI1_MIN_VLS_SUPPORTED 1 513 #define HFI1_MAX_VLS_SUPPORTED 8 514 515 static inline void incr_cntr64(u64 *cntr) 516 { 517 if (*cntr < (u64)-1LL) 518 (*cntr)++; 519 } 520 521 static inline void incr_cntr32(u32 *cntr) 522 { 523 if (*cntr < (u32)-1LL) 524 (*cntr)++; 525 } 526 527 #define MAX_NAME_SIZE 64 528 struct hfi1_msix_entry { 529 enum irq_type type; 530 struct msix_entry msix; 531 void *arg; 532 char name[MAX_NAME_SIZE]; 533 cpumask_t mask; 534 struct irq_affinity_notify notify; 535 }; 536 537 /* per-SL CCA information */ 538 struct cca_timer { 539 struct hrtimer hrtimer; 540 struct hfi1_pportdata *ppd; /* read-only */ 541 int sl; /* read-only */ 542 u16 ccti; /* read/write - current value of CCTI */ 543 }; 544 545 struct link_down_reason { 546 /* 547 * SMA-facing value. Should be set from .latest when 548 * HLS_UP_* -> HLS_DN_* transition actually occurs. 549 */ 550 u8 sma; 551 u8 latest; 552 }; 553 554 enum { 555 LO_PRIO_TABLE, 556 HI_PRIO_TABLE, 557 MAX_PRIO_TABLE 558 }; 559 560 struct vl_arb_cache { 561 /* protect vl arb cache */ 562 spinlock_t lock; 563 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; 564 }; 565 566 /* 567 * The structure below encapsulates data relevant to a physical IB Port. 568 * Current chips support only one such port, but the separation 569 * clarifies things a bit. Note that to conform to IB conventions, 570 * port-numbers are one-based. The first or only port is port1. 571 */ 572 struct hfi1_pportdata { 573 struct hfi1_ibport ibport_data; 574 575 struct hfi1_devdata *dd; 576 struct kobject pport_cc_kobj; 577 struct kobject sc2vl_kobj; 578 struct kobject sl2sc_kobj; 579 struct kobject vl2mtu_kobj; 580 581 /* PHY support */ 582 u32 port_type; 583 struct qsfp_data qsfp_info; 584 585 /* GUID for this interface, in host order */ 586 u64 guid; 587 /* GUID for peer interface, in host order */ 588 u64 neighbor_guid; 589 590 /* up or down physical link state */ 591 u32 linkup; 592 593 /* 594 * this address is mapped read-only into user processes so they can 595 * get status cheaply, whenever they want. One qword of status per port 596 */ 597 u64 *statusp; 598 599 /* SendDMA related entries */ 600 601 struct workqueue_struct *hfi1_wq; 602 603 /* move out of interrupt context */ 604 struct work_struct link_vc_work; 605 struct work_struct link_up_work; 606 struct work_struct link_down_work; 607 struct work_struct sma_message_work; 608 struct work_struct freeze_work; 609 struct work_struct link_downgrade_work; 610 struct work_struct link_bounce_work; 611 struct delayed_work start_link_work; 612 /* host link state variables */ 613 struct mutex hls_lock; 614 u32 host_link_state; 615 616 spinlock_t sdma_alllock ____cacheline_aligned_in_smp; 617 618 u32 lstate; /* logical link state */ 619 620 /* these are the "32 bit" regs */ 621 622 u32 ibmtu; /* The MTU programmed for this unit */ 623 /* 624 * Current max size IB packet (in bytes) including IB headers, that 625 * we can send. Changes when ibmtu changes. 626 */ 627 u32 ibmaxlen; 628 u32 current_egress_rate; /* units [10^6 bits/sec] */ 629 /* LID programmed for this instance */ 630 u16 lid; 631 /* list of pkeys programmed; 0 if not set */ 632 u16 pkeys[MAX_PKEY_VALUES]; 633 u16 link_width_supported; 634 u16 link_width_downgrade_supported; 635 u16 link_speed_supported; 636 u16 link_width_enabled; 637 u16 link_width_downgrade_enabled; 638 u16 link_speed_enabled; 639 u16 link_width_active; 640 u16 link_width_downgrade_tx_active; 641 u16 link_width_downgrade_rx_active; 642 u16 link_speed_active; 643 u8 vls_supported; 644 u8 vls_operational; 645 u8 actual_vls_operational; 646 /* LID mask control */ 647 u8 lmc; 648 /* Rx Polarity inversion (compensate for ~tx on partner) */ 649 u8 rx_pol_inv; 650 651 u8 hw_pidx; /* physical port index */ 652 u8 port; /* IB port number and index into dd->pports - 1 */ 653 /* type of neighbor node */ 654 u8 neighbor_type; 655 u8 neighbor_normal; 656 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ 657 u8 neighbor_port_number; 658 u8 is_sm_config_started; 659 u8 offline_disabled_reason; 660 u8 is_active_optimize_enabled; 661 u8 driver_link_ready; /* driver ready for active link */ 662 u8 link_enabled; /* link enabled? */ 663 u8 linkinit_reason; 664 u8 local_tx_rate; /* rate given to 8051 firmware */ 665 u8 last_pstate; /* info only */ 666 u8 qsfp_retry_count; 667 668 /* placeholders for IB MAD packet settings */ 669 u8 overrun_threshold; 670 u8 phy_error_threshold; 671 672 /* Used to override LED behavior for things like maintenance beaconing*/ 673 /* 674 * Alternates per phase of blink 675 * [0] holds LED off duration, [1] holds LED on duration 676 */ 677 unsigned long led_override_vals[2]; 678 u8 led_override_phase; /* LSB picks from vals[] */ 679 atomic_t led_override_timer_active; 680 /* Used to flash LEDs in override mode */ 681 struct timer_list led_override_timer; 682 683 u32 sm_trap_qp; 684 u32 sa_qp; 685 686 /* 687 * cca_timer_lock protects access to the per-SL cca_timer 688 * structures (specifically the ccti member). 689 */ 690 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; 691 struct cca_timer cca_timer[OPA_MAX_SLS]; 692 693 /* List of congestion control table entries */ 694 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; 695 696 /* congestion entries, each entry corresponding to a SL */ 697 struct opa_congestion_setting_entry_shadow 698 congestion_entries[OPA_MAX_SLS]; 699 700 /* 701 * cc_state_lock protects (write) access to the per-port 702 * struct cc_state. 703 */ 704 spinlock_t cc_state_lock ____cacheline_aligned_in_smp; 705 706 struct cc_state __rcu *cc_state; 707 708 /* Total number of congestion control table entries */ 709 u16 total_cct_entry; 710 711 /* Bit map identifying service level */ 712 u32 cc_sl_control_map; 713 714 /* CA's max number of 64 entry units in the congestion control table */ 715 u8 cc_max_table_entries; 716 717 /* 718 * begin congestion log related entries 719 * cc_log_lock protects all congestion log related data 720 */ 721 spinlock_t cc_log_lock ____cacheline_aligned_in_smp; 722 u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; 723 u16 threshold_event_counter; 724 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; 725 int cc_log_idx; /* index for logging events */ 726 int cc_mad_idx; /* index for reporting events */ 727 /* end congestion log related entries */ 728 729 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; 730 731 /* port relative counter buffer */ 732 u64 *cntrs; 733 /* port relative synthetic counter buffer */ 734 u64 *scntrs; 735 /* port_xmit_discards are synthesized from different egress errors */ 736 u64 port_xmit_discards; 737 u64 port_xmit_discards_vl[C_VL_COUNT]; 738 u64 port_xmit_constraint_errors; 739 u64 port_rcv_constraint_errors; 740 /* count of 'link_err' interrupts from DC */ 741 u64 link_downed; 742 /* number of times link retrained successfully */ 743 u64 link_up; 744 /* number of times a link unknown frame was reported */ 745 u64 unknown_frame_count; 746 /* port_ltp_crc_mode is returned in 'portinfo' MADs */ 747 u16 port_ltp_crc_mode; 748 /* port_crc_mode_enabled is the crc we support */ 749 u8 port_crc_mode_enabled; 750 /* mgmt_allowed is also returned in 'portinfo' MADs */ 751 u8 mgmt_allowed; 752 u8 part_enforce; /* partition enforcement flags */ 753 struct link_down_reason local_link_down_reason; 754 struct link_down_reason neigh_link_down_reason; 755 /* Value to be sent to link peer on LinkDown .*/ 756 u8 remote_link_down_reason; 757 /* Error events that will cause a port bounce. */ 758 u32 port_error_action; 759 struct work_struct linkstate_active_work; 760 /* Does this port need to prescan for FECNs */ 761 bool cc_prescan; 762 }; 763 764 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); 765 766 typedef void (*opcode_handler)(struct hfi1_packet *packet); 767 768 /* return values for the RHF receive functions */ 769 #define RHF_RCV_CONTINUE 0 /* keep going */ 770 #define RHF_RCV_DONE 1 /* stop, this packet processed */ 771 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ 772 773 struct rcv_array_data { 774 u8 group_size; 775 u16 ngroups; 776 u16 nctxt_extra; 777 }; 778 779 struct per_vl_data { 780 u16 mtu; 781 struct send_context *sc; 782 }; 783 784 /* 16 to directly index */ 785 #define PER_VL_SEND_CONTEXTS 16 786 787 struct err_info_rcvport { 788 u8 status_and_code; 789 u64 packet_flit1; 790 u64 packet_flit2; 791 }; 792 793 struct err_info_constraint { 794 u8 status; 795 u16 pkey; 796 u32 slid; 797 }; 798 799 struct hfi1_temp { 800 unsigned int curr; /* current temperature */ 801 unsigned int lo_lim; /* low temperature limit */ 802 unsigned int hi_lim; /* high temperature limit */ 803 unsigned int crit_lim; /* critical temperature limit */ 804 u8 triggers; /* temperature triggers */ 805 }; 806 807 struct hfi1_i2c_bus { 808 struct hfi1_devdata *controlling_dd; /* current controlling device */ 809 struct i2c_adapter adapter; /* bus details */ 810 struct i2c_algo_bit_data algo; /* bus algorithm details */ 811 int num; /* bus number, 0 or 1 */ 812 }; 813 814 /* common data between shared ASIC HFIs */ 815 struct hfi1_asic_data { 816 struct hfi1_devdata *dds[2]; /* back pointers */ 817 struct mutex asic_resource_mutex; 818 struct hfi1_i2c_bus *i2c_bus0; 819 struct hfi1_i2c_bus *i2c_bus1; 820 }; 821 822 /* device data struct now contains only "general per-device" info. 823 * fields related to a physical IB port are in a hfi1_pportdata struct. 824 */ 825 struct sdma_engine; 826 struct sdma_vl_map; 827 828 #define BOARD_VERS_MAX 96 /* how long the version string can be */ 829 #define SERIAL_MAX 16 /* length of the serial number */ 830 831 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); 832 struct hfi1_devdata { 833 struct hfi1_ibdev verbs_dev; /* must be first */ 834 struct list_head list; 835 /* pointers to related structs for this device */ 836 /* pci access data structure */ 837 struct pci_dev *pcidev; 838 struct cdev user_cdev; 839 struct cdev diag_cdev; 840 struct cdev ui_cdev; 841 struct device *user_device; 842 struct device *diag_device; 843 struct device *ui_device; 844 845 /* mem-mapped pointer to base of chip regs */ 846 u8 __iomem *kregbase; 847 /* end of mem-mapped chip space excluding sendbuf and user regs */ 848 u8 __iomem *kregend; 849 /* physical address of chip for io_remap, etc. */ 850 resource_size_t physaddr; 851 /* receive context data */ 852 struct hfi1_ctxtdata **rcd; 853 /* send context data */ 854 struct send_context_info *send_contexts; 855 /* map hardware send contexts to software index */ 856 u8 *hw_to_sw; 857 /* spinlock for allocating and releasing send context resources */ 858 spinlock_t sc_lock; 859 /* Per VL data. Enough for all VLs but not all elements are set/used. */ 860 struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; 861 /* lock for pio_map */ 862 spinlock_t pio_map_lock; 863 /* array of kernel send contexts */ 864 struct send_context **kernel_send_context; 865 /* array of vl maps */ 866 struct pio_vl_map __rcu *pio_map; 867 /* seqlock for sc2vl */ 868 seqlock_t sc2vl_lock; 869 u64 sc2vl[4]; 870 /* Send Context initialization lock. */ 871 spinlock_t sc_init_lock; 872 873 /* fields common to all SDMA engines */ 874 875 /* default flags to last descriptor */ 876 u64 default_desc1; 877 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ 878 dma_addr_t sdma_heads_phys; 879 void *sdma_pad_dma; /* DMA'ed by chip */ 880 dma_addr_t sdma_pad_phys; 881 /* for deallocation */ 882 size_t sdma_heads_size; 883 /* number from the chip */ 884 u32 chip_sdma_engines; 885 /* num used */ 886 u32 num_sdma; 887 /* lock for sdma_map */ 888 spinlock_t sde_map_lock; 889 /* array of engines sized by num_sdma */ 890 struct sdma_engine *per_sdma; 891 /* array of vl maps */ 892 struct sdma_vl_map __rcu *sdma_map; 893 /* SPC freeze waitqueue and variable */ 894 wait_queue_head_t sdma_unfreeze_wq; 895 atomic_t sdma_unfreeze_count; 896 897 /* common data between shared ASIC HFIs in this OS */ 898 struct hfi1_asic_data *asic_data; 899 900 /* hfi1_pportdata, points to array of (physical) port-specific 901 * data structs, indexed by pidx (0..n-1) 902 */ 903 struct hfi1_pportdata *pport; 904 905 /* mem-mapped pointer to base of PIO buffers */ 906 void __iomem *piobase; 907 /* 908 * write-combining mem-mapped pointer to base of RcvArray 909 * memory. 910 */ 911 void __iomem *rcvarray_wc; 912 /* 913 * credit return base - a per-NUMA range of DMA address that 914 * the chip will use to update the per-context free counter 915 */ 916 struct credit_return_base *cr_base; 917 918 /* send context numbers and sizes for each type */ 919 struct sc_config_sizes sc_sizes[SC_MAX]; 920 921 u32 lcb_access_count; /* count of LCB users */ 922 923 char *boardname; /* human readable board info */ 924 925 /* device (not port) flags, basically device capabilities */ 926 u32 flags; 927 928 /* reset value */ 929 u64 z_int_counter; 930 u64 z_rcv_limit; 931 u64 z_send_schedule; 932 /* percpu int_counter */ 933 u64 __percpu *int_counter; 934 u64 __percpu *rcv_limit; 935 u64 __percpu *send_schedule; 936 /* number of receive contexts in use by the driver */ 937 u32 num_rcv_contexts; 938 /* number of pio send contexts in use by the driver */ 939 u32 num_send_contexts; 940 /* 941 * number of ctxts available for PSM open 942 */ 943 u32 freectxts; 944 /* total number of available user/PSM contexts */ 945 u32 num_user_contexts; 946 /* base receive interrupt timeout, in CSR units */ 947 u32 rcv_intr_timeout_csr; 948 949 u64 __iomem *egrtidbase; 950 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ 951 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ 952 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 953 spinlock_t uctxt_lock; /* rcd and user context changes */ 954 /* exclusive access to 8051 */ 955 spinlock_t dc8051_lock; 956 /* exclusive access to 8051 memory */ 957 spinlock_t dc8051_memlock; 958 int dc8051_timed_out; /* remember if the 8051 timed out */ 959 /* 960 * A page that will hold event notification bitmaps for all 961 * contexts. This page will be mapped into all processes. 962 */ 963 unsigned long *events; 964 /* 965 * per unit status, see also portdata statusp 966 * mapped read-only into user processes so they can get unit and 967 * IB link status cheaply 968 */ 969 struct hfi1_status *status; 970 u32 freezelen; /* max length of freezemsg */ 971 972 /* revision register shadow */ 973 u64 revision; 974 /* Base GUID for device (network order) */ 975 u64 base_guid; 976 977 /* these are the "32 bit" regs */ 978 979 /* value we put in kr_rcvhdrsize */ 980 u32 rcvhdrsize; 981 /* number of receive contexts the chip supports */ 982 u32 chip_rcv_contexts; 983 /* number of receive array entries */ 984 u32 chip_rcv_array_count; 985 /* number of PIO send contexts the chip supports */ 986 u32 chip_send_contexts; 987 /* number of bytes in the PIO memory buffer */ 988 u32 chip_pio_mem_size; 989 /* number of bytes in the SDMA memory buffer */ 990 u32 chip_sdma_mem_size; 991 992 /* size of each rcvegrbuffer */ 993 u32 rcvegrbufsize; 994 /* log2 of above */ 995 u16 rcvegrbufsize_shift; 996 /* both sides of the PCIe link are gen3 capable */ 997 u8 link_gen3_capable; 998 /* localbus width (1, 2,4,8,16,32) from config space */ 999 u32 lbus_width; 1000 /* localbus speed in MHz */ 1001 u32 lbus_speed; 1002 int unit; /* unit # of this chip */ 1003 int node; /* home node of this chip */ 1004 1005 /* save these PCI fields to restore after a reset */ 1006 u32 pcibar0; 1007 u32 pcibar1; 1008 u32 pci_rom; 1009 u16 pci_command; 1010 u16 pcie_devctl; 1011 u16 pcie_lnkctl; 1012 u16 pcie_devctl2; 1013 u32 pci_msix0; 1014 u32 pci_lnkctl3; 1015 u32 pci_tph2; 1016 1017 /* 1018 * ASCII serial number, from flash, large enough for original 1019 * all digit strings, and longer serial number format 1020 */ 1021 u8 serial[SERIAL_MAX]; 1022 /* human readable board version */ 1023 u8 boardversion[BOARD_VERS_MAX]; 1024 u8 lbus_info[32]; /* human readable localbus info */ 1025 /* chip major rev, from CceRevision */ 1026 u8 majrev; 1027 /* chip minor rev, from CceRevision */ 1028 u8 minrev; 1029 /* hardware ID */ 1030 u8 hfi1_id; 1031 /* implementation code */ 1032 u8 icode; 1033 /* default link down value (poll/sleep) */ 1034 u8 link_default; 1035 /* vAU of this device */ 1036 u8 vau; 1037 /* vCU of this device */ 1038 u8 vcu; 1039 /* link credits of this device */ 1040 u16 link_credits; 1041 /* initial vl15 credits to use */ 1042 u16 vl15_init; 1043 1044 /* Misc small ints */ 1045 /* Number of physical ports available */ 1046 u8 num_pports; 1047 /* Lowest context number which can be used by user processes */ 1048 u8 first_user_ctxt; 1049 u8 n_krcv_queues; 1050 u8 qos_shift; 1051 u8 qpn_mask; 1052 1053 u16 rhf_offset; /* offset of RHF within receive header entry */ 1054 u16 irev; /* implementation revision */ 1055 u16 dc8051_ver; /* 8051 firmware version */ 1056 1057 struct platform_config platform_config; 1058 struct platform_config_cache pcfg_cache; 1059 1060 struct diag_client *diag_client; 1061 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ 1062 1063 u8 psxmitwait_supported; 1064 /* cycle length of PS* counters in HW (in picoseconds) */ 1065 u16 psxmitwait_check_rate; 1066 1067 /* MSI-X information */ 1068 struct hfi1_msix_entry *msix_entries; 1069 u32 num_msix_entries; 1070 1071 /* INTx information */ 1072 u32 requested_intx_irq; /* did we request one? */ 1073 char intx_name[MAX_NAME_SIZE]; /* INTx name */ 1074 1075 /* general interrupt: mask of handled interrupts */ 1076 u64 gi_mask[CCE_NUM_INT_CSRS]; 1077 1078 struct rcv_array_data rcv_entries; 1079 1080 /* 1081 * 64 bit synthetic counters 1082 */ 1083 struct timer_list synth_stats_timer; 1084 1085 /* 1086 * device counters 1087 */ 1088 char *cntrnames; 1089 size_t cntrnameslen; 1090 size_t ndevcntrs; 1091 u64 *cntrs; 1092 u64 *scntrs; 1093 1094 /* 1095 * remembered values for synthetic counters 1096 */ 1097 u64 last_tx; 1098 u64 last_rx; 1099 1100 /* 1101 * per-port counters 1102 */ 1103 size_t nportcntrs; 1104 char *portcntrnames; 1105 size_t portcntrnameslen; 1106 1107 struct hfi1_snoop_data hfi1_snoop; 1108 1109 struct err_info_rcvport err_info_rcvport; 1110 struct err_info_constraint err_info_rcv_constraint; 1111 struct err_info_constraint err_info_xmit_constraint; 1112 u8 err_info_uncorrectable; 1113 u8 err_info_fmconfig; 1114 1115 atomic_t drop_packet; 1116 u8 do_drop; 1117 1118 /* 1119 * Software counters for the status bits defined by the 1120 * associated error status registers 1121 */ 1122 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; 1123 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; 1124 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; 1125 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; 1126 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; 1127 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; 1128 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; 1129 1130 /* Software counter that spans all contexts */ 1131 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; 1132 /* Software counter that spans all DMA engines */ 1133 u64 sw_send_dma_eng_err_status_cnt[ 1134 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; 1135 /* Software counter that aggregates all cce_err_status errors */ 1136 u64 sw_cce_err_status_aggregate; 1137 /* Software counter that aggregates all bypass packet rcv errors */ 1138 u64 sw_rcv_bypass_packet_errors; 1139 /* receive interrupt functions */ 1140 rhf_rcv_function_ptr *rhf_rcv_function_map; 1141 rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; 1142 1143 /* 1144 * Handlers for outgoing data so that snoop/capture does not 1145 * have to have its hooks in the send path 1146 */ 1147 send_routine process_pio_send; 1148 send_routine process_dma_send; 1149 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1150 u64 pbc, const void *from, size_t count); 1151 1152 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ 1153 u8 oui1; 1154 u8 oui2; 1155 u8 oui3; 1156 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1157 struct timer_list rcverr_timer; 1158 u32 rcv_ovfl_cnt; 1159 1160 wait_queue_head_t event_queue; 1161 1162 /* Save the enabled LCB error bits */ 1163 u64 lcb_err_en; 1164 u8 dc_shutdown; 1165 1166 /* receive context tail dummy address */ 1167 __le64 *rcvhdrtail_dummy_kvaddr; 1168 dma_addr_t rcvhdrtail_dummy_dma; 1169 1170 bool eprom_available; /* true if EPROM is available for this device */ 1171 bool aspm_supported; /* Does HW support ASPM */ 1172 bool aspm_enabled; /* ASPM state: enabled/disabled */ 1173 /* Serialize ASPM enable/disable between multiple verbs contexts */ 1174 spinlock_t aspm_lock; 1175 /* Number of verbs contexts which have disabled ASPM */ 1176 atomic_t aspm_disabled_cnt; 1177 1178 struct hfi1_affinity *affinity; 1179 struct rhashtable sdma_rht; 1180 struct kobject kobj; 1181 }; 1182 1183 /* 8051 firmware version helper */ 1184 #define dc8051_ver(a, b) ((a) << 8 | (b)) 1185 #define dc8051_ver_maj(a) ((a & 0xff00) >> 8) 1186 #define dc8051_ver_min(a) (a & 0x00ff) 1187 1188 /* f_put_tid types */ 1189 #define PT_EXPECTED 0 1190 #define PT_EAGER 1 1191 #define PT_INVALID 2 1192 1193 struct tid_rb_node; 1194 struct mmu_rb_node; 1195 struct mmu_rb_handler; 1196 1197 /* Private data for file operations */ 1198 struct hfi1_filedata { 1199 struct hfi1_ctxtdata *uctxt; 1200 unsigned subctxt; 1201 struct hfi1_user_sdma_comp_q *cq; 1202 struct hfi1_user_sdma_pkt_q *pq; 1203 /* for cpu affinity; -1 if none */ 1204 int rec_cpu_num; 1205 u32 tid_n_pinned; 1206 struct mmu_rb_handler *handler; 1207 struct tid_rb_node **entry_to_rb; 1208 spinlock_t tid_lock; /* protect tid_[limit,used] counters */ 1209 u32 tid_limit; 1210 u32 tid_used; 1211 u32 *invalid_tids; 1212 u32 invalid_tid_idx; 1213 /* protect invalid_tids array and invalid_tid_idx */ 1214 spinlock_t invalid_lock; 1215 struct mm_struct *mm; 1216 }; 1217 1218 extern struct list_head hfi1_dev_list; 1219 extern spinlock_t hfi1_devs_lock; 1220 struct hfi1_devdata *hfi1_lookup(int unit); 1221 extern u32 hfi1_cpulist_count; 1222 extern unsigned long *hfi1_cpulist; 1223 1224 extern unsigned int snoop_drop_send; 1225 extern unsigned int snoop_force_capture; 1226 int hfi1_init(struct hfi1_devdata *, int); 1227 int hfi1_count_units(int *npresentp, int *nupp); 1228 int hfi1_count_active_units(void); 1229 1230 int hfi1_diag_add(struct hfi1_devdata *); 1231 void hfi1_diag_remove(struct hfi1_devdata *); 1232 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); 1233 1234 void handle_user_interrupt(struct hfi1_ctxtdata *rcd); 1235 1236 int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *); 1237 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *); 1238 int hfi1_create_ctxts(struct hfi1_devdata *dd); 1239 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int); 1240 void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *, 1241 struct hfi1_devdata *, u8, u8); 1242 void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *); 1243 1244 int handle_receive_interrupt(struct hfi1_ctxtdata *, int); 1245 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int); 1246 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int); 1247 void set_all_slowpath(struct hfi1_devdata *dd); 1248 1249 extern const struct pci_device_id hfi1_pci_tbl[]; 1250 1251 /* receive packet handler dispositions */ 1252 #define RCV_PKT_OK 0x0 /* keep going */ 1253 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ 1254 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ 1255 1256 /* calculate the current RHF address */ 1257 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) 1258 { 1259 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset; 1260 } 1261 1262 int hfi1_reset_device(int); 1263 1264 /* return the driver's idea of the logical OPA port state */ 1265 static inline u32 driver_lstate(struct hfi1_pportdata *ppd) 1266 { 1267 return ppd->lstate; /* use the cached value */ 1268 } 1269 1270 void receive_interrupt_work(struct work_struct *work); 1271 1272 /* extract service channel from header and rhf */ 1273 static inline int hdr2sc(struct ib_header *hdr, u64 rhf) 1274 { 1275 return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) | 1276 ((!!(rhf_dc_info(rhf))) << 4); 1277 } 1278 1279 #define HFI1_JKEY_WIDTH 16 1280 #define HFI1_JKEY_MASK (BIT(16) - 1) 1281 #define HFI1_ADMIN_JKEY_RANGE 32 1282 1283 /* 1284 * J_KEYs are split and allocated in the following groups: 1285 * 0 - 31 - users with administrator privileges 1286 * 32 - 63 - kernel protocols using KDETH packets 1287 * 64 - 65535 - all other users using KDETH packets 1288 */ 1289 static inline u16 generate_jkey(kuid_t uid) 1290 { 1291 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK; 1292 1293 if (capable(CAP_SYS_ADMIN)) 1294 jkey &= HFI1_ADMIN_JKEY_RANGE - 1; 1295 else if (jkey < 64) 1296 jkey |= BIT(HFI1_JKEY_WIDTH - 1); 1297 1298 return jkey; 1299 } 1300 1301 /* 1302 * active_egress_rate 1303 * 1304 * returns the active egress rate in units of [10^6 bits/sec] 1305 */ 1306 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) 1307 { 1308 u16 link_speed = ppd->link_speed_active; 1309 u16 link_width = ppd->link_width_active; 1310 u32 egress_rate; 1311 1312 if (link_speed == OPA_LINK_SPEED_25G) 1313 egress_rate = 25000; 1314 else /* assume OPA_LINK_SPEED_12_5G */ 1315 egress_rate = 12500; 1316 1317 switch (link_width) { 1318 case OPA_LINK_WIDTH_4X: 1319 egress_rate *= 4; 1320 break; 1321 case OPA_LINK_WIDTH_3X: 1322 egress_rate *= 3; 1323 break; 1324 case OPA_LINK_WIDTH_2X: 1325 egress_rate *= 2; 1326 break; 1327 default: 1328 /* assume IB_WIDTH_1X */ 1329 break; 1330 } 1331 1332 return egress_rate; 1333 } 1334 1335 /* 1336 * egress_cycles 1337 * 1338 * Returns the number of 'fabric clock cycles' to egress a packet 1339 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock 1340 * rate is (approximately) 805 MHz, the units of the returned value 1341 * are (1/805 MHz). 1342 */ 1343 static inline u32 egress_cycles(u32 len, u32 rate) 1344 { 1345 u32 cycles; 1346 1347 /* 1348 * cycles is: 1349 * 1350 * (length) [bits] / (rate) [bits/sec] 1351 * --------------------------------------------------- 1352 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] 1353 */ 1354 1355 cycles = len * 8; /* bits */ 1356 cycles *= 805; 1357 cycles /= rate; 1358 1359 return cycles; 1360 } 1361 1362 void set_link_ipg(struct hfi1_pportdata *ppd); 1363 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn, 1364 u32 rqpn, u8 svc_type); 1365 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, 1366 u32 pkey, u32 slid, u32 dlid, u8 sc5, 1367 const struct ib_grh *old_grh); 1368 #define PKEY_CHECK_INVALID -1 1369 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth, 1370 u8 sc5, int8_t s_pkey_index); 1371 1372 #define PACKET_EGRESS_TIMEOUT 350 1373 static inline void pause_for_credit_return(struct hfi1_devdata *dd) 1374 { 1375 /* Pause at least 1us, to ensure chip returns all credits */ 1376 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; 1377 1378 udelay(usec ? usec : 1); 1379 } 1380 1381 /** 1382 * sc_to_vlt() reverse lookup sc to vl 1383 * @dd - devdata 1384 * @sc5 - 5 bit sc 1385 */ 1386 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) 1387 { 1388 unsigned seq; 1389 u8 rval; 1390 1391 if (sc5 >= OPA_MAX_SCS) 1392 return (u8)(0xff); 1393 1394 do { 1395 seq = read_seqbegin(&dd->sc2vl_lock); 1396 rval = *(((u8 *)dd->sc2vl) + sc5); 1397 } while (read_seqretry(&dd->sc2vl_lock, seq)); 1398 1399 return rval; 1400 } 1401 1402 #define PKEY_MEMBER_MASK 0x8000 1403 #define PKEY_LOW_15_MASK 0x7fff 1404 1405 /* 1406 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent 1407 * being an entry from the ingress partition key table), return 0 1408 * otherwise. Use the matching criteria for ingress partition keys 1409 * specified in the OPAv1 spec., section 9.10.14. 1410 */ 1411 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) 1412 { 1413 u16 mkey = pkey & PKEY_LOW_15_MASK; 1414 u16 ment = ent & PKEY_LOW_15_MASK; 1415 1416 if (mkey == ment) { 1417 /* 1418 * If pkey[15] is clear (limited partition member), 1419 * is bit 15 in the corresponding table element 1420 * clear (limited member)? 1421 */ 1422 if (!(pkey & PKEY_MEMBER_MASK)) 1423 return !!(ent & PKEY_MEMBER_MASK); 1424 return 1; 1425 } 1426 return 0; 1427 } 1428 1429 /* 1430 * ingress_pkey_table_search - search the entire pkey table for 1431 * an entry which matches 'pkey'. return 0 if a match is found, 1432 * and 1 otherwise. 1433 */ 1434 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) 1435 { 1436 int i; 1437 1438 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1439 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1440 return 0; 1441 } 1442 return 1; 1443 } 1444 1445 /* 1446 * ingress_pkey_table_fail - record a failure of ingress pkey validation, 1447 * i.e., increment port_rcv_constraint_errors for the port, and record 1448 * the 'error info' for this failure. 1449 */ 1450 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, 1451 u16 slid) 1452 { 1453 struct hfi1_devdata *dd = ppd->dd; 1454 1455 incr_cntr64(&ppd->port_rcv_constraint_errors); 1456 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { 1457 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; 1458 dd->err_info_rcv_constraint.slid = slid; 1459 dd->err_info_rcv_constraint.pkey = pkey; 1460 } 1461 } 1462 1463 /* 1464 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 1465 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx 1466 * is a hint as to the best place in the partition key table to begin 1467 * searching. This function should not be called on the data path because 1468 * of performance reasons. On datapath pkey check is expected to be done 1469 * by HW and rcv_pkey_check function should be called instead. 1470 */ 1471 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1472 u8 sc5, u8 idx, u16 slid) 1473 { 1474 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1475 return 0; 1476 1477 /* If SC15, pkey[0:14] must be 0x7fff */ 1478 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1479 goto bad; 1480 1481 /* Is the pkey = 0x0, or 0x8000? */ 1482 if ((pkey & PKEY_LOW_15_MASK) == 0) 1483 goto bad; 1484 1485 /* The most likely matching pkey has index 'idx' */ 1486 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) 1487 return 0; 1488 1489 /* no match - try the whole table */ 1490 if (!ingress_pkey_table_search(ppd, pkey)) 1491 return 0; 1492 1493 bad: 1494 ingress_pkey_table_fail(ppd, pkey, slid); 1495 return 1; 1496 } 1497 1498 /* 1499 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 1500 * otherwise. It only ensures pkey is vlid for QP0. This function 1501 * should be called on the data path instead of ingress_pkey_check 1502 * as on data path, pkey check is done by HW (except for QP0). 1503 */ 1504 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1505 u8 sc5, u16 slid) 1506 { 1507 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1508 return 0; 1509 1510 /* If SC15, pkey[0:14] must be 0x7fff */ 1511 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1512 goto bad; 1513 1514 return 0; 1515 bad: 1516 ingress_pkey_table_fail(ppd, pkey, slid); 1517 return 1; 1518 } 1519 1520 /* MTU handling */ 1521 1522 /* MTU enumeration, 256-4k match IB */ 1523 #define OPA_MTU_0 0 1524 #define OPA_MTU_256 1 1525 #define OPA_MTU_512 2 1526 #define OPA_MTU_1024 3 1527 #define OPA_MTU_2048 4 1528 #define OPA_MTU_4096 5 1529 1530 u32 lrh_max_header_bytes(struct hfi1_devdata *dd); 1531 int mtu_to_enum(u32 mtu, int default_if_bad); 1532 u16 enum_to_mtu(int); 1533 static inline int valid_ib_mtu(unsigned int mtu) 1534 { 1535 return mtu == 256 || mtu == 512 || 1536 mtu == 1024 || mtu == 2048 || 1537 mtu == 4096; 1538 } 1539 1540 static inline int valid_opa_max_mtu(unsigned int mtu) 1541 { 1542 return mtu >= 2048 && 1543 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); 1544 } 1545 1546 int set_mtu(struct hfi1_pportdata *); 1547 1548 int hfi1_set_lid(struct hfi1_pportdata *, u32, u8); 1549 void hfi1_disable_after_error(struct hfi1_devdata *); 1550 int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int); 1551 int hfi1_rcvbuf_validate(u32, u8, u16 *); 1552 1553 int fm_get_table(struct hfi1_pportdata *, int, void *); 1554 int fm_set_table(struct hfi1_pportdata *, int, void *); 1555 1556 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); 1557 void reset_link_credits(struct hfi1_devdata *dd); 1558 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); 1559 1560 int snoop_recv_handler(struct hfi1_packet *packet); 1561 int snoop_send_dma_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 1562 u64 pbc); 1563 int snoop_send_pio_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 1564 u64 pbc); 1565 void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1566 u64 pbc, const void *from, size_t count); 1567 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); 1568 1569 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) 1570 { 1571 return ppd->dd; 1572 } 1573 1574 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) 1575 { 1576 return container_of(dev, struct hfi1_devdata, verbs_dev); 1577 } 1578 1579 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) 1580 { 1581 return dd_from_dev(to_idev(ibdev)); 1582 } 1583 1584 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) 1585 { 1586 return container_of(ibp, struct hfi1_pportdata, ibport_data); 1587 } 1588 1589 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) 1590 { 1591 return container_of(rdi, struct hfi1_ibdev, rdi); 1592 } 1593 1594 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) 1595 { 1596 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1597 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1598 1599 WARN_ON(pidx >= dd->num_pports); 1600 return &dd->pport[pidx].ibport_data; 1601 } 1602 1603 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt, 1604 bool do_cnp); 1605 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt, 1606 bool do_cnp) 1607 { 1608 struct ib_other_headers *ohdr = pkt->ohdr; 1609 u32 bth1; 1610 1611 bth1 = be32_to_cpu(ohdr->bth[1]); 1612 if (unlikely(bth1 & (HFI1_BECN_SMASK | HFI1_FECN_SMASK))) { 1613 hfi1_process_ecn_slowpath(qp, pkt, do_cnp); 1614 return bth1 & HFI1_FECN_SMASK; 1615 } 1616 return false; 1617 } 1618 1619 /* 1620 * Return the indexed PKEY from the port PKEY table. 1621 */ 1622 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) 1623 { 1624 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1625 u16 ret; 1626 1627 if (index >= ARRAY_SIZE(ppd->pkeys)) 1628 ret = 0; 1629 else 1630 ret = ppd->pkeys[index]; 1631 1632 return ret; 1633 } 1634 1635 /* 1636 * Called by readers of cc_state only, must call under rcu_read_lock(). 1637 */ 1638 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) 1639 { 1640 return rcu_dereference(ppd->cc_state); 1641 } 1642 1643 /* 1644 * Called by writers of cc_state only, must call under cc_state_lock. 1645 */ 1646 static inline 1647 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd) 1648 { 1649 return rcu_dereference_protected(ppd->cc_state, 1650 lockdep_is_held(&ppd->cc_state_lock)); 1651 } 1652 1653 /* 1654 * values for dd->flags (_device_ related flags) 1655 */ 1656 #define HFI1_INITTED 0x1 /* chip and driver up and initted */ 1657 #define HFI1_PRESENT 0x2 /* chip accesses can be done */ 1658 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ 1659 #define HFI1_HAS_SDMA_TIMEOUT 0x8 1660 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ 1661 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ 1662 1663 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1664 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) 1665 1666 /* ctxt_flag bit offsets */ 1667 /* context has been setup */ 1668 #define HFI1_CTXT_SETUP_DONE 1 1669 /* waiting for a packet to arrive */ 1670 #define HFI1_CTXT_WAITING_RCV 2 1671 /* master has not finished initializing */ 1672 #define HFI1_CTXT_MASTER_UNINIT 4 1673 /* waiting for an urgent packet to arrive */ 1674 #define HFI1_CTXT_WAITING_URG 5 1675 1676 /* free up any allocated data at closes */ 1677 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *, 1678 const struct pci_device_id *); 1679 void hfi1_free_devdata(struct hfi1_devdata *); 1680 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra); 1681 1682 /* LED beaconing functions */ 1683 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, 1684 unsigned int timeoff); 1685 void shutdown_led_override(struct hfi1_pportdata *ppd); 1686 1687 #define HFI1_CREDIT_RETURN_RATE (100) 1688 1689 /* 1690 * The number of words for the KDETH protocol field. If this is 1691 * larger then the actual field used, then part of the payload 1692 * will be in the header. 1693 * 1694 * Optimally, we want this sized so that a typical case will 1695 * use full cache lines. The typical local KDETH header would 1696 * be: 1697 * 1698 * Bytes Field 1699 * 8 LRH 1700 * 12 BHT 1701 * ?? KDETH 1702 * 8 RHF 1703 * --- 1704 * 28 + KDETH 1705 * 1706 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS 1707 */ 1708 #define DEFAULT_RCVHDRSIZE 9 1709 1710 /* 1711 * Maximal header byte count: 1712 * 1713 * Bytes Field 1714 * 8 LRH 1715 * 40 GRH (optional) 1716 * 12 BTH 1717 * ?? KDETH 1718 * 8 RHF 1719 * --- 1720 * 68 + KDETH 1721 * 1722 * We also want to maintain a cache line alignment to assist DMA'ing 1723 * of the header bytes. Round up to a good size. 1724 */ 1725 #define DEFAULT_RCVHDR_ENTSIZE 32 1726 1727 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm, 1728 u32 nlocked, u32 npages); 1729 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr, 1730 size_t npages, bool writable, struct page **pages); 1731 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p, 1732 size_t npages, bool dirty); 1733 1734 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1735 { 1736 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; 1737 } 1738 1739 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1740 { 1741 /* 1742 * volatile because it's a DMA target from the chip, routine is 1743 * inlined, and don't want register caching or reordering. 1744 */ 1745 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); 1746 } 1747 1748 /* 1749 * sysfs interface. 1750 */ 1751 1752 extern const char ib_hfi1_version[]; 1753 1754 int hfi1_device_create(struct hfi1_devdata *); 1755 void hfi1_device_remove(struct hfi1_devdata *); 1756 1757 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, 1758 struct kobject *kobj); 1759 int hfi1_verbs_register_sysfs(struct hfi1_devdata *); 1760 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *); 1761 /* Hook for sysfs read of QSFP */ 1762 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); 1763 1764 int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *); 1765 void hfi1_pcie_cleanup(struct pci_dev *); 1766 int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *, 1767 const struct pci_device_id *); 1768 void hfi1_pcie_ddcleanup(struct hfi1_devdata *); 1769 void hfi1_pcie_flr(struct hfi1_devdata *); 1770 int pcie_speeds(struct hfi1_devdata *); 1771 void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *); 1772 void hfi1_enable_intx(struct pci_dev *); 1773 void restore_pci_variables(struct hfi1_devdata *dd); 1774 int do_pcie_gen3_transition(struct hfi1_devdata *dd); 1775 int parse_platform_config(struct hfi1_devdata *dd); 1776 int get_platform_config_field(struct hfi1_devdata *dd, 1777 enum platform_config_table_type_encoding 1778 table_type, int table_index, int field_index, 1779 u32 *data, u32 len); 1780 1781 const char *get_unit_name(int unit); 1782 const char *get_card_name(struct rvt_dev_info *rdi); 1783 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); 1784 1785 /* 1786 * Flush write combining store buffers (if present) and perform a write 1787 * barrier. 1788 */ 1789 static inline void flush_wc(void) 1790 { 1791 asm volatile("sfence" : : : "memory"); 1792 } 1793 1794 void handle_eflags(struct hfi1_packet *packet); 1795 int process_receive_ib(struct hfi1_packet *packet); 1796 int process_receive_bypass(struct hfi1_packet *packet); 1797 int process_receive_error(struct hfi1_packet *packet); 1798 int kdeth_process_expected(struct hfi1_packet *packet); 1799 int kdeth_process_eager(struct hfi1_packet *packet); 1800 int process_receive_invalid(struct hfi1_packet *packet); 1801 1802 extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8]; 1803 1804 void update_sge(struct rvt_sge_state *ss, u32 length); 1805 1806 /* global module parameter variables */ 1807 extern unsigned int hfi1_max_mtu; 1808 extern unsigned int hfi1_cu; 1809 extern unsigned int user_credit_return_threshold; 1810 extern int num_user_contexts; 1811 extern unsigned long n_krcvqs; 1812 extern uint krcvqs[]; 1813 extern int krcvqsset; 1814 extern uint kdeth_qp; 1815 extern uint loopback; 1816 extern uint quick_linkup; 1817 extern uint rcv_intr_timeout; 1818 extern uint rcv_intr_count; 1819 extern uint rcv_intr_dynamic; 1820 extern ushort link_crc_mask; 1821 1822 extern struct mutex hfi1_mutex; 1823 1824 /* Number of seconds before our card status check... */ 1825 #define STATUS_TIMEOUT 60 1826 1827 #define DRIVER_NAME "hfi1" 1828 #define HFI1_USER_MINOR_BASE 0 1829 #define HFI1_TRACE_MINOR 127 1830 #define HFI1_DIAGPKT_MINOR 128 1831 #define HFI1_DIAG_MINOR_BASE 129 1832 #define HFI1_SNOOP_CAPTURE_BASE 200 1833 #define HFI1_NMINORS 255 1834 1835 #define PCI_VENDOR_ID_INTEL 0x8086 1836 #define PCI_DEVICE_ID_INTEL0 0x24f0 1837 #define PCI_DEVICE_ID_INTEL1 0x24f1 1838 1839 #define HFI1_PKT_USER_SC_INTEGRITY \ 1840 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ 1841 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \ 1842 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ 1843 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) 1844 1845 #define HFI1_PKT_KERNEL_SC_INTEGRITY \ 1846 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) 1847 1848 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, 1849 u16 ctxt_type) 1850 { 1851 u64 base_sc_integrity = 1852 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1853 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 1854 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1855 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1856 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1857 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 1858 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1859 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1860 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1861 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 1862 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1863 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1864 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 1865 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 1866 | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 1867 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 1868 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1869 1870 if (ctxt_type == SC_USER) 1871 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY; 1872 else 1873 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; 1874 1875 if (is_ax(dd)) 1876 /* turn off send-side job key checks - A0 */ 1877 return base_sc_integrity & 1878 ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1879 return base_sc_integrity; 1880 } 1881 1882 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) 1883 { 1884 u64 base_sdma_integrity = 1885 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1886 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 1887 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1888 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1889 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1890 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1891 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1892 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1893 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 1894 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1895 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1896 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 1897 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 1898 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 1899 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 1900 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1901 1902 if (is_ax(dd)) 1903 /* turn off send-side job key checks - A0 */ 1904 return base_sdma_integrity & 1905 ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1906 return base_sdma_integrity; 1907 } 1908 1909 /* 1910 * hfi1_early_err is used (only!) to print early errors before devdata is 1911 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1912 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is 1913 * the same as dd_dev_err, but is used when the message really needs 1914 * the IB port# to be definitive as to what's happening.. 1915 */ 1916 #define hfi1_early_err(dev, fmt, ...) \ 1917 dev_err(dev, fmt, ##__VA_ARGS__) 1918 1919 #define hfi1_early_info(dev, fmt, ...) \ 1920 dev_info(dev, fmt, ##__VA_ARGS__) 1921 1922 #define dd_dev_emerg(dd, fmt, ...) \ 1923 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ 1924 get_unit_name((dd)->unit), ##__VA_ARGS__) 1925 #define dd_dev_err(dd, fmt, ...) \ 1926 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1927 get_unit_name((dd)->unit), ##__VA_ARGS__) 1928 #define dd_dev_warn(dd, fmt, ...) \ 1929 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1930 get_unit_name((dd)->unit), ##__VA_ARGS__) 1931 1932 #define dd_dev_warn_ratelimited(dd, fmt, ...) \ 1933 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 1934 get_unit_name((dd)->unit), ##__VA_ARGS__) 1935 1936 #define dd_dev_info(dd, fmt, ...) \ 1937 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ 1938 get_unit_name((dd)->unit), ##__VA_ARGS__) 1939 1940 #define dd_dev_dbg(dd, fmt, ...) \ 1941 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ 1942 get_unit_name((dd)->unit), ##__VA_ARGS__) 1943 1944 #define hfi1_dev_porterr(dd, port, fmt, ...) \ 1945 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ 1946 get_unit_name((dd)->unit), (port), ##__VA_ARGS__) 1947 1948 /* 1949 * this is used for formatting hw error messages... 1950 */ 1951 struct hfi1_hwerror_msgs { 1952 u64 mask; 1953 const char *msg; 1954 size_t sz; 1955 }; 1956 1957 /* in intr.c... */ 1958 void hfi1_format_hwerrors(u64 hwerrs, 1959 const struct hfi1_hwerror_msgs *hwerrmsgs, 1960 size_t nhwerrmsgs, char *msg, size_t lmsg); 1961 1962 #define USER_OPCODE_CHECK_VAL 0xC0 1963 #define USER_OPCODE_CHECK_MASK 0xC0 1964 #define OPCODE_CHECK_VAL_DISABLED 0x0 1965 #define OPCODE_CHECK_MASK_DISABLED 0x0 1966 1967 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) 1968 { 1969 struct hfi1_pportdata *ppd; 1970 int i; 1971 1972 dd->z_int_counter = get_all_cpu_total(dd->int_counter); 1973 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); 1974 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); 1975 1976 ppd = (struct hfi1_pportdata *)(dd + 1); 1977 for (i = 0; i < dd->num_pports; i++, ppd++) { 1978 ppd->ibport_data.rvp.z_rc_acks = 1979 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); 1980 ppd->ibport_data.rvp.z_rc_qacks = 1981 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); 1982 } 1983 } 1984 1985 /* Control LED state */ 1986 static inline void setextled(struct hfi1_devdata *dd, u32 on) 1987 { 1988 if (on) 1989 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); 1990 else 1991 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); 1992 } 1993 1994 /* return the i2c resource given the target */ 1995 static inline u32 i2c_target(u32 target) 1996 { 1997 return target ? CR_I2C2 : CR_I2C1; 1998 } 1999 2000 /* return the i2c chain chip resource that this HFI uses for QSFP */ 2001 static inline u32 qsfp_resource(struct hfi1_devdata *dd) 2002 { 2003 return i2c_target(dd->hfi1_id); 2004 } 2005 2006 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); 2007 2008 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev)) 2009 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev)) 2010 2011 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype } 2012 #define show_packettype(etype) \ 2013 __print_symbolic(etype, \ 2014 packettype_name(EXPECTED), \ 2015 packettype_name(EAGER), \ 2016 packettype_name(IB), \ 2017 packettype_name(ERROR), \ 2018 packettype_name(BYPASS)) 2019 2020 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode } 2021 #define show_ib_opcode(opcode) \ 2022 __print_symbolic(opcode, \ 2023 ib_opcode_name(RC_SEND_FIRST), \ 2024 ib_opcode_name(RC_SEND_MIDDLE), \ 2025 ib_opcode_name(RC_SEND_LAST), \ 2026 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \ 2027 ib_opcode_name(RC_SEND_ONLY), \ 2028 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \ 2029 ib_opcode_name(RC_RDMA_WRITE_FIRST), \ 2030 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \ 2031 ib_opcode_name(RC_RDMA_WRITE_LAST), \ 2032 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ 2033 ib_opcode_name(RC_RDMA_WRITE_ONLY), \ 2034 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ 2035 ib_opcode_name(RC_RDMA_READ_REQUEST), \ 2036 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \ 2037 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \ 2038 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \ 2039 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \ 2040 ib_opcode_name(RC_ACKNOWLEDGE), \ 2041 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \ 2042 ib_opcode_name(RC_COMPARE_SWAP), \ 2043 ib_opcode_name(RC_FETCH_ADD), \ 2044 ib_opcode_name(UC_SEND_FIRST), \ 2045 ib_opcode_name(UC_SEND_MIDDLE), \ 2046 ib_opcode_name(UC_SEND_LAST), \ 2047 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \ 2048 ib_opcode_name(UC_SEND_ONLY), \ 2049 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \ 2050 ib_opcode_name(UC_RDMA_WRITE_FIRST), \ 2051 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \ 2052 ib_opcode_name(UC_RDMA_WRITE_LAST), \ 2053 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ 2054 ib_opcode_name(UC_RDMA_WRITE_ONLY), \ 2055 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ 2056 ib_opcode_name(UD_SEND_ONLY), \ 2057 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \ 2058 ib_opcode_name(CNP)) 2059 #endif /* _HFI1_KERNEL_H */ 2060