1 #ifndef _HFI1_KERNEL_H 2 #define _HFI1_KERNEL_H 3 /* 4 * Copyright(c) 2015, 2016 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 #include <linux/interrupt.h> 51 #include <linux/pci.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/mutex.h> 54 #include <linux/list.h> 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/io.h> 58 #include <linux/fs.h> 59 #include <linux/completion.h> 60 #include <linux/kref.h> 61 #include <linux/sched.h> 62 #include <linux/cdev.h> 63 #include <linux/delay.h> 64 #include <linux/kthread.h> 65 #include <linux/i2c.h> 66 #include <linux/i2c-algo-bit.h> 67 #include <rdma/ib_hdrs.h> 68 #include <linux/rhashtable.h> 69 #include <rdma/rdma_vt.h> 70 71 #include "chip_registers.h" 72 #include "common.h" 73 #include "verbs.h" 74 #include "pio.h" 75 #include "chip.h" 76 #include "mad.h" 77 #include "qsfp.h" 78 #include "platform.h" 79 #include "affinity.h" 80 81 /* bumped 1 from s/w major version of TrueScale */ 82 #define HFI1_CHIP_VERS_MAJ 3U 83 84 /* don't care about this except printing */ 85 #define HFI1_CHIP_VERS_MIN 0U 86 87 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 88 #define HFI1_OUI 0x001175 89 #define HFI1_OUI_LSB 40 90 91 #define DROP_PACKET_OFF 0 92 #define DROP_PACKET_ON 1 93 94 extern unsigned long hfi1_cap_mask; 95 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) 96 #define HFI1_CAP_UGET_MASK(mask, cap) \ 97 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) 98 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) 99 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) 100 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) 101 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) 102 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ 103 HFI1_CAP_MISC_MASK) 104 /* Offline Disabled Reason is 4-bits */ 105 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) 106 107 /* 108 * Control context is always 0 and handles the error packets. 109 * It also handles the VL15 and multicast packets. 110 */ 111 #define HFI1_CTRL_CTXT 0 112 113 /* 114 * Driver context will store software counters for each of the events 115 * associated with these status registers 116 */ 117 #define NUM_CCE_ERR_STATUS_COUNTERS 41 118 #define NUM_RCV_ERR_STATUS_COUNTERS 64 119 #define NUM_MISC_ERR_STATUS_COUNTERS 13 120 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 121 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 122 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 123 #define NUM_SEND_ERR_STATUS_COUNTERS 3 124 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 125 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 126 127 /* 128 * per driver stats, either not device nor port-specific, or 129 * summed over all of the devices and ports. 130 * They are described by name via ipathfs filesystem, so layout 131 * and number of elements can change without breaking compatibility. 132 * If members are added or deleted hfi1_statnames[] in debugfs.c must 133 * change to match. 134 */ 135 struct hfi1_ib_stats { 136 __u64 sps_ints; /* number of interrupts handled */ 137 __u64 sps_errints; /* number of error interrupts */ 138 __u64 sps_txerrs; /* tx-related packet errors */ 139 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 140 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 141 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 142 __u64 sps_ctxts; /* number of contexts currently open */ 143 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 144 __u64 sps_buffull; 145 __u64 sps_hdrfull; 146 }; 147 148 extern struct hfi1_ib_stats hfi1_stats; 149 extern const struct pci_error_handlers hfi1_pci_err_handler; 150 151 /* 152 * First-cut criterion for "device is active" is 153 * two thousand dwords combined Tx, Rx traffic per 154 * 5-second interval. SMA packets are 64 dwords, 155 * and occur "a few per second", presumably each way. 156 */ 157 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) 158 159 /* 160 * Below contains all data related to a single context (formerly called port). 161 */ 162 163 #ifdef CONFIG_DEBUG_FS 164 struct hfi1_opcode_stats_perctx; 165 #endif 166 167 struct ctxt_eager_bufs { 168 ssize_t size; /* total size of eager buffers */ 169 u32 count; /* size of buffers array */ 170 u32 numbufs; /* number of buffers allocated */ 171 u32 alloced; /* number of rcvarray entries used */ 172 u32 rcvtid_size; /* size of each eager rcv tid */ 173 u32 threshold; /* head update threshold */ 174 struct eager_buffer { 175 void *addr; 176 dma_addr_t dma; 177 ssize_t len; 178 } *buffers; 179 struct { 180 void *addr; 181 dma_addr_t dma; 182 } *rcvtids; 183 }; 184 185 struct exp_tid_set { 186 struct list_head list; 187 u32 count; 188 }; 189 190 struct hfi1_ctxtdata { 191 /* shadow the ctxt's RcvCtrl register */ 192 u64 rcvctrl; 193 /* rcvhdrq base, needs mmap before useful */ 194 void *rcvhdrq; 195 /* kernel virtual address where hdrqtail is updated */ 196 volatile __le64 *rcvhdrtail_kvaddr; 197 /* 198 * Shared page for kernel to signal user processes that send buffers 199 * need disarming. The process should call HFI1_CMD_DISARM_BUFS 200 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 201 */ 202 unsigned long *user_event_mask; 203 /* when waiting for rcv or pioavail */ 204 wait_queue_head_t wait; 205 /* rcvhdrq size (for freeing) */ 206 size_t rcvhdrq_size; 207 /* number of rcvhdrq entries */ 208 u16 rcvhdrq_cnt; 209 /* size of each of the rcvhdrq entries */ 210 u16 rcvhdrqentsize; 211 /* mmap of hdrq, must fit in 44 bits */ 212 dma_addr_t rcvhdrq_dma; 213 dma_addr_t rcvhdrqtailaddr_dma; 214 struct ctxt_eager_bufs egrbufs; 215 /* this receive context's assigned PIO ACK send context */ 216 struct send_context *sc; 217 218 /* dynamic receive available interrupt timeout */ 219 u32 rcvavail_timeout; 220 /* 221 * number of opens (including slave sub-contexts) on this instance 222 * (ignoring forks, dup, etc. for now) 223 */ 224 int cnt; 225 /* 226 * how much space to leave at start of eager TID entries for 227 * protocol use, on each TID 228 */ 229 /* instead of calculating it */ 230 unsigned ctxt; 231 /* non-zero if ctxt is being shared. */ 232 u16 subctxt_cnt; 233 /* non-zero if ctxt is being shared. */ 234 u16 subctxt_id; 235 u8 uuid[16]; 236 /* job key */ 237 u16 jkey; 238 /* number of RcvArray groups for this context. */ 239 u32 rcv_array_groups; 240 /* index of first eager TID entry. */ 241 u32 eager_base; 242 /* number of expected TID entries */ 243 u32 expected_count; 244 /* index of first expected TID entry. */ 245 u32 expected_base; 246 247 struct exp_tid_set tid_group_list; 248 struct exp_tid_set tid_used_list; 249 struct exp_tid_set tid_full_list; 250 251 /* lock protecting all Expected TID data */ 252 struct mutex exp_lock; 253 /* number of pio bufs for this ctxt (all procs, if shared) */ 254 u32 piocnt; 255 /* first pio buffer for this ctxt */ 256 u32 pio_base; 257 /* chip offset of PIO buffers for this ctxt */ 258 u32 piobufs; 259 /* per-context configuration flags */ 260 unsigned long flags; 261 /* per-context event flags for fileops/intr communication */ 262 unsigned long event_flags; 263 /* WAIT_RCV that timed out, no interrupt */ 264 u32 rcvwait_to; 265 /* WAIT_PIO that timed out, no interrupt */ 266 u32 piowait_to; 267 /* WAIT_RCV already happened, no wait */ 268 u32 rcvnowait; 269 /* WAIT_PIO already happened, no wait */ 270 u32 pionowait; 271 /* total number of polled urgent packets */ 272 u32 urgent; 273 /* saved total number of polled urgent packets for poll edge trigger */ 274 u32 urgent_poll; 275 /* same size as task_struct .comm[], command that opened context */ 276 char comm[TASK_COMM_LEN]; 277 /* so file ops can get at unit */ 278 struct hfi1_devdata *dd; 279 /* so functions that need physical port can get it easily */ 280 struct hfi1_pportdata *ppd; 281 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 282 void *subctxt_uregbase; 283 /* An array of pages for the eager receive buffers * N */ 284 void *subctxt_rcvegrbuf; 285 /* An array of pages for the eager header queue entries * N */ 286 void *subctxt_rcvhdr_base; 287 /* The version of the library which opened this ctxt */ 288 u32 userversion; 289 /* Bitmask of active slaves */ 290 u32 active_slaves; 291 /* Type of packets or conditions we want to poll for */ 292 u16 poll_type; 293 /* receive packet sequence counter */ 294 u8 seq_cnt; 295 u8 redirect_seq_cnt; 296 /* ctxt rcvhdrq head offset */ 297 u32 head; 298 u32 pkt_count; 299 /* QPs waiting for context processing */ 300 struct list_head qp_wait_list; 301 /* interrupt handling */ 302 u64 imask; /* clear interrupt mask */ 303 int ireg; /* clear interrupt register */ 304 unsigned numa_id; /* numa node of this context */ 305 /* verbs stats per CTX */ 306 struct hfi1_opcode_stats_perctx *opstats; 307 /* 308 * This is the kernel thread that will keep making 309 * progress on the user sdma requests behind the scenes. 310 * There is one per context (shared contexts use the master's). 311 */ 312 struct task_struct *progress; 313 struct list_head sdma_queues; 314 /* protect sdma queues */ 315 spinlock_t sdma_qlock; 316 317 /* Is ASPM interrupt supported for this context */ 318 bool aspm_intr_supported; 319 /* ASPM state (enabled/disabled) for this context */ 320 bool aspm_enabled; 321 /* Timer for re-enabling ASPM if interrupt activity quietens down */ 322 struct timer_list aspm_timer; 323 /* Lock to serialize between intr, timer intr and user threads */ 324 spinlock_t aspm_lock; 325 /* Is ASPM processing enabled for this context (in intr context) */ 326 bool aspm_intr_enable; 327 /* Last interrupt timestamp */ 328 ktime_t aspm_ts_last_intr; 329 /* Last timestamp at which we scheduled a timer for this context */ 330 ktime_t aspm_ts_timer_sched; 331 332 /* 333 * The interrupt handler for a particular receive context can vary 334 * throughout it's lifetime. This is not a lock protected data member so 335 * it must be updated atomically and the prev and new value must always 336 * be valid. Worst case is we process an extra interrupt and up to 64 337 * packets with the wrong interrupt handler. 338 */ 339 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); 340 }; 341 342 /* 343 * Represents a single packet at a high level. Put commonly computed things in 344 * here so we do not have to keep doing them over and over. The rule of thumb is 345 * if something is used one time to derive some value, store that something in 346 * here. If it is used multiple times, then store the result of that derivation 347 * in here. 348 */ 349 struct hfi1_packet { 350 void *ebuf; 351 void *hdr; 352 struct hfi1_ctxtdata *rcd; 353 __le32 *rhf_addr; 354 struct rvt_qp *qp; 355 struct ib_other_headers *ohdr; 356 u64 rhf; 357 u32 maxcnt; 358 u32 rhqoff; 359 u16 tlen; 360 s16 etail; 361 u8 hlen; 362 u8 numpkt; 363 u8 rsize; 364 u8 updegr; 365 u8 rcv_flags; 366 u8 etype; 367 }; 368 369 struct rvt_sge_state; 370 371 /* 372 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 373 * Mostly for MADs that set or query link parameters, also ipath 374 * config interfaces 375 */ 376 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 377 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ 378 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 379 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ 380 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 381 #define HFI1_IB_CFG_SPD 5 /* current Link spd */ 382 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 383 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 384 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 385 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 386 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ 387 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 388 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 389 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 390 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 391 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 392 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ 393 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ 394 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 395 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 396 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ 397 398 /* 399 * HFI or Host Link States 400 * 401 * These describe the states the driver thinks the logical and physical 402 * states are in. Used as an argument to set_link_state(). Implemented 403 * as bits for easy multi-state checking. The actual state can only be 404 * one. 405 */ 406 #define __HLS_UP_INIT_BP 0 407 #define __HLS_UP_ARMED_BP 1 408 #define __HLS_UP_ACTIVE_BP 2 409 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ 410 #define __HLS_DN_POLL_BP 4 411 #define __HLS_DN_DISABLE_BP 5 412 #define __HLS_DN_OFFLINE_BP 6 413 #define __HLS_VERIFY_CAP_BP 7 414 #define __HLS_GOING_UP_BP 8 415 #define __HLS_GOING_OFFLINE_BP 9 416 #define __HLS_LINK_COOLDOWN_BP 10 417 418 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) 419 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) 420 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) 421 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ 422 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) 423 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) 424 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) 425 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) 426 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) 427 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) 428 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) 429 430 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) 431 #define HLS_DOWN ~(HLS_UP) 432 433 /* use this MTU size if none other is given */ 434 #define HFI1_DEFAULT_ACTIVE_MTU 10240 435 /* use this MTU size as the default maximum */ 436 #define HFI1_DEFAULT_MAX_MTU 10240 437 /* default partition key */ 438 #define DEFAULT_PKEY 0xffff 439 440 /* 441 * Possible fabric manager config parameters for fm_{get,set}_table() 442 */ 443 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ 444 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ 445 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ 446 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ 447 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ 448 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ 449 450 /* 451 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 452 * these are bits so they can be combined, e.g. 453 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB 454 */ 455 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 456 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 457 #define HFI1_RCVCTRL_CTXT_ENB 0x04 458 #define HFI1_RCVCTRL_CTXT_DIS 0x08 459 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 460 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 461 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 462 #define HFI1_RCVCTRL_PKEY_DIS 0x80 463 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 464 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 465 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 466 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 467 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 468 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 469 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 470 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 471 472 /* partition enforcement flags */ 473 #define HFI1_PART_ENFORCE_IN 0x1 474 #define HFI1_PART_ENFORCE_OUT 0x2 475 476 /* how often we check for synthetic counter wrap around */ 477 #define SYNTH_CNT_TIME 2 478 479 /* Counter flags */ 480 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ 481 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ 482 #define CNTR_DISABLED 0x2 /* Disable this counter */ 483 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ 484 #define CNTR_VL 0x8 /* Per VL counter */ 485 #define CNTR_SDMA 0x10 486 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ 487 #define CNTR_MODE_W 0x0 488 #define CNTR_MODE_R 0x1 489 490 /* VLs Supported/Operational */ 491 #define HFI1_MIN_VLS_SUPPORTED 1 492 #define HFI1_MAX_VLS_SUPPORTED 8 493 494 #define HFI1_GUIDS_PER_PORT 5 495 #define HFI1_PORT_GUID_INDEX 0 496 497 static inline void incr_cntr64(u64 *cntr) 498 { 499 if (*cntr < (u64)-1LL) 500 (*cntr)++; 501 } 502 503 static inline void incr_cntr32(u32 *cntr) 504 { 505 if (*cntr < (u32)-1LL) 506 (*cntr)++; 507 } 508 509 #define MAX_NAME_SIZE 64 510 struct hfi1_msix_entry { 511 enum irq_type type; 512 struct msix_entry msix; 513 void *arg; 514 char name[MAX_NAME_SIZE]; 515 cpumask_t mask; 516 struct irq_affinity_notify notify; 517 }; 518 519 /* per-SL CCA information */ 520 struct cca_timer { 521 struct hrtimer hrtimer; 522 struct hfi1_pportdata *ppd; /* read-only */ 523 int sl; /* read-only */ 524 u16 ccti; /* read/write - current value of CCTI */ 525 }; 526 527 struct link_down_reason { 528 /* 529 * SMA-facing value. Should be set from .latest when 530 * HLS_UP_* -> HLS_DN_* transition actually occurs. 531 */ 532 u8 sma; 533 u8 latest; 534 }; 535 536 enum { 537 LO_PRIO_TABLE, 538 HI_PRIO_TABLE, 539 MAX_PRIO_TABLE 540 }; 541 542 struct vl_arb_cache { 543 /* protect vl arb cache */ 544 spinlock_t lock; 545 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; 546 }; 547 548 /* 549 * The structure below encapsulates data relevant to a physical IB Port. 550 * Current chips support only one such port, but the separation 551 * clarifies things a bit. Note that to conform to IB conventions, 552 * port-numbers are one-based. The first or only port is port1. 553 */ 554 struct hfi1_pportdata { 555 struct hfi1_ibport ibport_data; 556 557 struct hfi1_devdata *dd; 558 struct kobject pport_cc_kobj; 559 struct kobject sc2vl_kobj; 560 struct kobject sl2sc_kobj; 561 struct kobject vl2mtu_kobj; 562 563 /* PHY support */ 564 struct qsfp_data qsfp_info; 565 /* Values for SI tuning of SerDes */ 566 u32 port_type; 567 u32 tx_preset_eq; 568 u32 tx_preset_noeq; 569 u32 rx_preset; 570 u8 local_atten; 571 u8 remote_atten; 572 u8 default_atten; 573 u8 max_power_class; 574 575 /* GUIDs for this interface, in host order, guids[0] is a port guid */ 576 u64 guids[HFI1_GUIDS_PER_PORT]; 577 578 /* GUID for peer interface, in host order */ 579 u64 neighbor_guid; 580 581 /* up or down physical link state */ 582 u32 linkup; 583 584 /* 585 * this address is mapped read-only into user processes so they can 586 * get status cheaply, whenever they want. One qword of status per port 587 */ 588 u64 *statusp; 589 590 /* SendDMA related entries */ 591 592 struct workqueue_struct *hfi1_wq; 593 594 /* move out of interrupt context */ 595 struct work_struct link_vc_work; 596 struct work_struct link_up_work; 597 struct work_struct link_down_work; 598 struct work_struct sma_message_work; 599 struct work_struct freeze_work; 600 struct work_struct link_downgrade_work; 601 struct work_struct link_bounce_work; 602 struct delayed_work start_link_work; 603 /* host link state variables */ 604 struct mutex hls_lock; 605 u32 host_link_state; 606 607 u32 lstate; /* logical link state */ 608 609 /* these are the "32 bit" regs */ 610 611 u32 ibmtu; /* The MTU programmed for this unit */ 612 /* 613 * Current max size IB packet (in bytes) including IB headers, that 614 * we can send. Changes when ibmtu changes. 615 */ 616 u32 ibmaxlen; 617 u32 current_egress_rate; /* units [10^6 bits/sec] */ 618 /* LID programmed for this instance */ 619 u16 lid; 620 /* list of pkeys programmed; 0 if not set */ 621 u16 pkeys[MAX_PKEY_VALUES]; 622 u16 link_width_supported; 623 u16 link_width_downgrade_supported; 624 u16 link_speed_supported; 625 u16 link_width_enabled; 626 u16 link_width_downgrade_enabled; 627 u16 link_speed_enabled; 628 u16 link_width_active; 629 u16 link_width_downgrade_tx_active; 630 u16 link_width_downgrade_rx_active; 631 u16 link_speed_active; 632 u8 vls_supported; 633 u8 vls_operational; 634 u8 actual_vls_operational; 635 /* LID mask control */ 636 u8 lmc; 637 /* Rx Polarity inversion (compensate for ~tx on partner) */ 638 u8 rx_pol_inv; 639 640 u8 hw_pidx; /* physical port index */ 641 u8 port; /* IB port number and index into dd->pports - 1 */ 642 /* type of neighbor node */ 643 u8 neighbor_type; 644 u8 neighbor_normal; 645 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ 646 u8 neighbor_port_number; 647 u8 is_sm_config_started; 648 u8 offline_disabled_reason; 649 u8 is_active_optimize_enabled; 650 u8 driver_link_ready; /* driver ready for active link */ 651 u8 link_enabled; /* link enabled? */ 652 u8 linkinit_reason; 653 u8 local_tx_rate; /* rate given to 8051 firmware */ 654 u8 last_pstate; /* info only */ 655 u8 qsfp_retry_count; 656 657 /* placeholders for IB MAD packet settings */ 658 u8 overrun_threshold; 659 u8 phy_error_threshold; 660 661 /* Used to override LED behavior for things like maintenance beaconing*/ 662 /* 663 * Alternates per phase of blink 664 * [0] holds LED off duration, [1] holds LED on duration 665 */ 666 unsigned long led_override_vals[2]; 667 u8 led_override_phase; /* LSB picks from vals[] */ 668 atomic_t led_override_timer_active; 669 /* Used to flash LEDs in override mode */ 670 struct timer_list led_override_timer; 671 672 u32 sm_trap_qp; 673 u32 sa_qp; 674 675 /* 676 * cca_timer_lock protects access to the per-SL cca_timer 677 * structures (specifically the ccti member). 678 */ 679 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; 680 struct cca_timer cca_timer[OPA_MAX_SLS]; 681 682 /* List of congestion control table entries */ 683 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; 684 685 /* congestion entries, each entry corresponding to a SL */ 686 struct opa_congestion_setting_entry_shadow 687 congestion_entries[OPA_MAX_SLS]; 688 689 /* 690 * cc_state_lock protects (write) access to the per-port 691 * struct cc_state. 692 */ 693 spinlock_t cc_state_lock ____cacheline_aligned_in_smp; 694 695 struct cc_state __rcu *cc_state; 696 697 /* Total number of congestion control table entries */ 698 u16 total_cct_entry; 699 700 /* Bit map identifying service level */ 701 u32 cc_sl_control_map; 702 703 /* CA's max number of 64 entry units in the congestion control table */ 704 u8 cc_max_table_entries; 705 706 /* 707 * begin congestion log related entries 708 * cc_log_lock protects all congestion log related data 709 */ 710 spinlock_t cc_log_lock ____cacheline_aligned_in_smp; 711 u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; 712 u16 threshold_event_counter; 713 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; 714 int cc_log_idx; /* index for logging events */ 715 int cc_mad_idx; /* index for reporting events */ 716 /* end congestion log related entries */ 717 718 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; 719 720 /* port relative counter buffer */ 721 u64 *cntrs; 722 /* port relative synthetic counter buffer */ 723 u64 *scntrs; 724 /* port_xmit_discards are synthesized from different egress errors */ 725 u64 port_xmit_discards; 726 u64 port_xmit_discards_vl[C_VL_COUNT]; 727 u64 port_xmit_constraint_errors; 728 u64 port_rcv_constraint_errors; 729 /* count of 'link_err' interrupts from DC */ 730 u64 link_downed; 731 /* number of times link retrained successfully */ 732 u64 link_up; 733 /* number of times a link unknown frame was reported */ 734 u64 unknown_frame_count; 735 /* port_ltp_crc_mode is returned in 'portinfo' MADs */ 736 u16 port_ltp_crc_mode; 737 /* port_crc_mode_enabled is the crc we support */ 738 u8 port_crc_mode_enabled; 739 /* mgmt_allowed is also returned in 'portinfo' MADs */ 740 u8 mgmt_allowed; 741 u8 part_enforce; /* partition enforcement flags */ 742 struct link_down_reason local_link_down_reason; 743 struct link_down_reason neigh_link_down_reason; 744 /* Value to be sent to link peer on LinkDown .*/ 745 u8 remote_link_down_reason; 746 /* Error events that will cause a port bounce. */ 747 u32 port_error_action; 748 struct work_struct linkstate_active_work; 749 /* Does this port need to prescan for FECNs */ 750 bool cc_prescan; 751 }; 752 753 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); 754 755 typedef void (*opcode_handler)(struct hfi1_packet *packet); 756 757 /* return values for the RHF receive functions */ 758 #define RHF_RCV_CONTINUE 0 /* keep going */ 759 #define RHF_RCV_DONE 1 /* stop, this packet processed */ 760 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ 761 762 struct rcv_array_data { 763 u8 group_size; 764 u16 ngroups; 765 u16 nctxt_extra; 766 }; 767 768 struct per_vl_data { 769 u16 mtu; 770 struct send_context *sc; 771 }; 772 773 /* 16 to directly index */ 774 #define PER_VL_SEND_CONTEXTS 16 775 776 struct err_info_rcvport { 777 u8 status_and_code; 778 u64 packet_flit1; 779 u64 packet_flit2; 780 }; 781 782 struct err_info_constraint { 783 u8 status; 784 u16 pkey; 785 u32 slid; 786 }; 787 788 struct hfi1_temp { 789 unsigned int curr; /* current temperature */ 790 unsigned int lo_lim; /* low temperature limit */ 791 unsigned int hi_lim; /* high temperature limit */ 792 unsigned int crit_lim; /* critical temperature limit */ 793 u8 triggers; /* temperature triggers */ 794 }; 795 796 struct hfi1_i2c_bus { 797 struct hfi1_devdata *controlling_dd; /* current controlling device */ 798 struct i2c_adapter adapter; /* bus details */ 799 struct i2c_algo_bit_data algo; /* bus algorithm details */ 800 int num; /* bus number, 0 or 1 */ 801 }; 802 803 /* common data between shared ASIC HFIs */ 804 struct hfi1_asic_data { 805 struct hfi1_devdata *dds[2]; /* back pointers */ 806 struct mutex asic_resource_mutex; 807 struct hfi1_i2c_bus *i2c_bus0; 808 struct hfi1_i2c_bus *i2c_bus1; 809 }; 810 811 /* device data struct now contains only "general per-device" info. 812 * fields related to a physical IB port are in a hfi1_pportdata struct. 813 */ 814 struct sdma_engine; 815 struct sdma_vl_map; 816 817 #define BOARD_VERS_MAX 96 /* how long the version string can be */ 818 #define SERIAL_MAX 16 /* length of the serial number */ 819 820 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); 821 struct hfi1_devdata { 822 struct hfi1_ibdev verbs_dev; /* must be first */ 823 struct list_head list; 824 /* pointers to related structs for this device */ 825 /* pci access data structure */ 826 struct pci_dev *pcidev; 827 struct cdev user_cdev; 828 struct cdev diag_cdev; 829 struct cdev ui_cdev; 830 struct device *user_device; 831 struct device *diag_device; 832 struct device *ui_device; 833 834 /* mem-mapped pointer to base of chip regs */ 835 u8 __iomem *kregbase; 836 /* end of mem-mapped chip space excluding sendbuf and user regs */ 837 u8 __iomem *kregend; 838 /* physical address of chip for io_remap, etc. */ 839 resource_size_t physaddr; 840 /* Per VL data. Enough for all VLs but not all elements are set/used. */ 841 struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; 842 /* send context data */ 843 struct send_context_info *send_contexts; 844 /* map hardware send contexts to software index */ 845 u8 *hw_to_sw; 846 /* spinlock for allocating and releasing send context resources */ 847 spinlock_t sc_lock; 848 /* lock for pio_map */ 849 spinlock_t pio_map_lock; 850 /* Send Context initialization lock. */ 851 spinlock_t sc_init_lock; 852 /* lock for sdma_map */ 853 spinlock_t sde_map_lock; 854 /* array of kernel send contexts */ 855 struct send_context **kernel_send_context; 856 /* array of vl maps */ 857 struct pio_vl_map __rcu *pio_map; 858 /* default flags to last descriptor */ 859 u64 default_desc1; 860 861 /* fields common to all SDMA engines */ 862 863 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ 864 dma_addr_t sdma_heads_phys; 865 void *sdma_pad_dma; /* DMA'ed by chip */ 866 dma_addr_t sdma_pad_phys; 867 /* for deallocation */ 868 size_t sdma_heads_size; 869 /* number from the chip */ 870 u32 chip_sdma_engines; 871 /* num used */ 872 u32 num_sdma; 873 /* array of engines sized by num_sdma */ 874 struct sdma_engine *per_sdma; 875 /* array of vl maps */ 876 struct sdma_vl_map __rcu *sdma_map; 877 /* SPC freeze waitqueue and variable */ 878 wait_queue_head_t sdma_unfreeze_wq; 879 atomic_t sdma_unfreeze_count; 880 881 u32 lcb_access_count; /* count of LCB users */ 882 883 /* common data between shared ASIC HFIs in this OS */ 884 struct hfi1_asic_data *asic_data; 885 886 /* mem-mapped pointer to base of PIO buffers */ 887 void __iomem *piobase; 888 /* 889 * write-combining mem-mapped pointer to base of RcvArray 890 * memory. 891 */ 892 void __iomem *rcvarray_wc; 893 /* 894 * credit return base - a per-NUMA range of DMA address that 895 * the chip will use to update the per-context free counter 896 */ 897 struct credit_return_base *cr_base; 898 899 /* send context numbers and sizes for each type */ 900 struct sc_config_sizes sc_sizes[SC_MAX]; 901 902 char *boardname; /* human readable board info */ 903 904 /* reset value */ 905 u64 z_int_counter; 906 u64 z_rcv_limit; 907 u64 z_send_schedule; 908 909 u64 __percpu *send_schedule; 910 /* number of receive contexts in use by the driver */ 911 u32 num_rcv_contexts; 912 /* number of pio send contexts in use by the driver */ 913 u32 num_send_contexts; 914 /* 915 * number of ctxts available for PSM open 916 */ 917 u32 freectxts; 918 /* total number of available user/PSM contexts */ 919 u32 num_user_contexts; 920 /* base receive interrupt timeout, in CSR units */ 921 u32 rcv_intr_timeout_csr; 922 923 u32 freezelen; /* max length of freezemsg */ 924 u64 __iomem *egrtidbase; 925 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ 926 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ 927 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 928 spinlock_t uctxt_lock; /* rcd and user context changes */ 929 /* exclusive access to 8051 */ 930 spinlock_t dc8051_lock; 931 /* exclusive access to 8051 memory */ 932 spinlock_t dc8051_memlock; 933 int dc8051_timed_out; /* remember if the 8051 timed out */ 934 /* 935 * A page that will hold event notification bitmaps for all 936 * contexts. This page will be mapped into all processes. 937 */ 938 unsigned long *events; 939 /* 940 * per unit status, see also portdata statusp 941 * mapped read-only into user processes so they can get unit and 942 * IB link status cheaply 943 */ 944 struct hfi1_status *status; 945 946 /* revision register shadow */ 947 u64 revision; 948 /* Base GUID for device (network order) */ 949 u64 base_guid; 950 951 /* these are the "32 bit" regs */ 952 953 /* value we put in kr_rcvhdrsize */ 954 u32 rcvhdrsize; 955 /* number of receive contexts the chip supports */ 956 u32 chip_rcv_contexts; 957 /* number of receive array entries */ 958 u32 chip_rcv_array_count; 959 /* number of PIO send contexts the chip supports */ 960 u32 chip_send_contexts; 961 /* number of bytes in the PIO memory buffer */ 962 u32 chip_pio_mem_size; 963 /* number of bytes in the SDMA memory buffer */ 964 u32 chip_sdma_mem_size; 965 966 /* size of each rcvegrbuffer */ 967 u32 rcvegrbufsize; 968 /* log2 of above */ 969 u16 rcvegrbufsize_shift; 970 /* both sides of the PCIe link are gen3 capable */ 971 u8 link_gen3_capable; 972 /* default link down value (poll/sleep) */ 973 u8 link_default; 974 /* localbus width (1, 2,4,8,16,32) from config space */ 975 u32 lbus_width; 976 /* localbus speed in MHz */ 977 u32 lbus_speed; 978 int unit; /* unit # of this chip */ 979 int node; /* home node of this chip */ 980 981 /* save these PCI fields to restore after a reset */ 982 u32 pcibar0; 983 u32 pcibar1; 984 u32 pci_rom; 985 u16 pci_command; 986 u16 pcie_devctl; 987 u16 pcie_lnkctl; 988 u16 pcie_devctl2; 989 u32 pci_msix0; 990 u32 pci_lnkctl3; 991 u32 pci_tph2; 992 993 /* 994 * ASCII serial number, from flash, large enough for original 995 * all digit strings, and longer serial number format 996 */ 997 u8 serial[SERIAL_MAX]; 998 /* human readable board version */ 999 u8 boardversion[BOARD_VERS_MAX]; 1000 u8 lbus_info[32]; /* human readable localbus info */ 1001 /* chip major rev, from CceRevision */ 1002 u8 majrev; 1003 /* chip minor rev, from CceRevision */ 1004 u8 minrev; 1005 /* hardware ID */ 1006 u8 hfi1_id; 1007 /* implementation code */ 1008 u8 icode; 1009 /* vAU of this device */ 1010 u8 vau; 1011 /* vCU of this device */ 1012 u8 vcu; 1013 /* link credits of this device */ 1014 u16 link_credits; 1015 /* initial vl15 credits to use */ 1016 u16 vl15_init; 1017 1018 /* Misc small ints */ 1019 u8 n_krcv_queues; 1020 u8 qos_shift; 1021 1022 u16 irev; /* implementation revision */ 1023 u16 dc8051_ver; /* 8051 firmware version */ 1024 1025 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ 1026 struct platform_config platform_config; 1027 struct platform_config_cache pcfg_cache; 1028 1029 struct diag_client *diag_client; 1030 1031 /* MSI-X information */ 1032 struct hfi1_msix_entry *msix_entries; 1033 u32 num_msix_entries; 1034 1035 /* INTx information */ 1036 u32 requested_intx_irq; /* did we request one? */ 1037 char intx_name[MAX_NAME_SIZE]; /* INTx name */ 1038 1039 /* general interrupt: mask of handled interrupts */ 1040 u64 gi_mask[CCE_NUM_INT_CSRS]; 1041 1042 struct rcv_array_data rcv_entries; 1043 1044 /* cycle length of PS* counters in HW (in picoseconds) */ 1045 u16 psxmitwait_check_rate; 1046 1047 /* 1048 * 64 bit synthetic counters 1049 */ 1050 struct timer_list synth_stats_timer; 1051 1052 /* 1053 * device counters 1054 */ 1055 char *cntrnames; 1056 size_t cntrnameslen; 1057 size_t ndevcntrs; 1058 u64 *cntrs; 1059 u64 *scntrs; 1060 1061 /* 1062 * remembered values for synthetic counters 1063 */ 1064 u64 last_tx; 1065 u64 last_rx; 1066 1067 /* 1068 * per-port counters 1069 */ 1070 size_t nportcntrs; 1071 char *portcntrnames; 1072 size_t portcntrnameslen; 1073 1074 struct err_info_rcvport err_info_rcvport; 1075 struct err_info_constraint err_info_rcv_constraint; 1076 struct err_info_constraint err_info_xmit_constraint; 1077 1078 atomic_t drop_packet; 1079 u8 do_drop; 1080 u8 err_info_uncorrectable; 1081 u8 err_info_fmconfig; 1082 1083 /* 1084 * Software counters for the status bits defined by the 1085 * associated error status registers 1086 */ 1087 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; 1088 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; 1089 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; 1090 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; 1091 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; 1092 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; 1093 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; 1094 1095 /* Software counter that spans all contexts */ 1096 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; 1097 /* Software counter that spans all DMA engines */ 1098 u64 sw_send_dma_eng_err_status_cnt[ 1099 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; 1100 /* Software counter that aggregates all cce_err_status errors */ 1101 u64 sw_cce_err_status_aggregate; 1102 /* Software counter that aggregates all bypass packet rcv errors */ 1103 u64 sw_rcv_bypass_packet_errors; 1104 /* receive interrupt function */ 1105 rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; 1106 1107 /* Save the enabled LCB error bits */ 1108 u64 lcb_err_en; 1109 1110 /* 1111 * Capability to have different send engines simply by changing a 1112 * pointer value. 1113 */ 1114 send_routine process_pio_send ____cacheline_aligned_in_smp; 1115 send_routine process_dma_send; 1116 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1117 u64 pbc, const void *from, size_t count); 1118 /* hfi1_pportdata, points to array of (physical) port-specific 1119 * data structs, indexed by pidx (0..n-1) 1120 */ 1121 struct hfi1_pportdata *pport; 1122 /* receive context data */ 1123 struct hfi1_ctxtdata **rcd; 1124 u64 __percpu *int_counter; 1125 /* device (not port) flags, basically device capabilities */ 1126 u16 flags; 1127 /* Number of physical ports available */ 1128 u8 num_pports; 1129 /* Lowest context number which can be used by user processes */ 1130 u8 first_user_ctxt; 1131 /* adding a new field here would make it part of this cacheline */ 1132 1133 /* seqlock for sc2vl */ 1134 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp; 1135 u64 sc2vl[4]; 1136 /* receive interrupt functions */ 1137 rhf_rcv_function_ptr *rhf_rcv_function_map; 1138 u64 __percpu *rcv_limit; 1139 u16 rhf_offset; /* offset of RHF within receive header entry */ 1140 /* adding a new field here would make it part of this cacheline */ 1141 1142 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ 1143 u8 oui1; 1144 u8 oui2; 1145 u8 oui3; 1146 u8 dc_shutdown; 1147 1148 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1149 struct timer_list rcverr_timer; 1150 1151 wait_queue_head_t event_queue; 1152 1153 /* receive context tail dummy address */ 1154 __le64 *rcvhdrtail_dummy_kvaddr; 1155 dma_addr_t rcvhdrtail_dummy_dma; 1156 1157 u32 rcv_ovfl_cnt; 1158 /* Serialize ASPM enable/disable between multiple verbs contexts */ 1159 spinlock_t aspm_lock; 1160 /* Number of verbs contexts which have disabled ASPM */ 1161 atomic_t aspm_disabled_cnt; 1162 /* Keeps track of user space clients */ 1163 atomic_t user_refcount; 1164 /* Used to wait for outstanding user space clients before dev removal */ 1165 struct completion user_comp; 1166 1167 bool eprom_available; /* true if EPROM is available for this device */ 1168 bool aspm_supported; /* Does HW support ASPM */ 1169 bool aspm_enabled; /* ASPM state: enabled/disabled */ 1170 struct rhashtable sdma_rht; 1171 1172 struct kobject kobj; 1173 }; 1174 1175 /* 8051 firmware version helper */ 1176 #define dc8051_ver(a, b) ((a) << 8 | (b)) 1177 #define dc8051_ver_maj(a) ((a & 0xff00) >> 8) 1178 #define dc8051_ver_min(a) (a & 0x00ff) 1179 1180 /* f_put_tid types */ 1181 #define PT_EXPECTED 0 1182 #define PT_EAGER 1 1183 #define PT_INVALID 2 1184 1185 struct tid_rb_node; 1186 struct mmu_rb_node; 1187 struct mmu_rb_handler; 1188 1189 /* Private data for file operations */ 1190 struct hfi1_filedata { 1191 struct hfi1_ctxtdata *uctxt; 1192 unsigned subctxt; 1193 struct hfi1_user_sdma_comp_q *cq; 1194 struct hfi1_user_sdma_pkt_q *pq; 1195 /* for cpu affinity; -1 if none */ 1196 int rec_cpu_num; 1197 u32 tid_n_pinned; 1198 struct mmu_rb_handler *handler; 1199 struct tid_rb_node **entry_to_rb; 1200 spinlock_t tid_lock; /* protect tid_[limit,used] counters */ 1201 u32 tid_limit; 1202 u32 tid_used; 1203 u32 *invalid_tids; 1204 u32 invalid_tid_idx; 1205 /* protect invalid_tids array and invalid_tid_idx */ 1206 spinlock_t invalid_lock; 1207 struct mm_struct *mm; 1208 }; 1209 1210 extern struct list_head hfi1_dev_list; 1211 extern spinlock_t hfi1_devs_lock; 1212 struct hfi1_devdata *hfi1_lookup(int unit); 1213 extern u32 hfi1_cpulist_count; 1214 extern unsigned long *hfi1_cpulist; 1215 1216 int hfi1_init(struct hfi1_devdata *, int); 1217 int hfi1_count_units(int *npresentp, int *nupp); 1218 int hfi1_count_active_units(void); 1219 1220 int hfi1_diag_add(struct hfi1_devdata *); 1221 void hfi1_diag_remove(struct hfi1_devdata *); 1222 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); 1223 1224 void handle_user_interrupt(struct hfi1_ctxtdata *rcd); 1225 1226 int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *); 1227 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *); 1228 int hfi1_create_ctxts(struct hfi1_devdata *dd); 1229 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int); 1230 void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *, 1231 struct hfi1_devdata *, u8, u8); 1232 void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *); 1233 1234 int handle_receive_interrupt(struct hfi1_ctxtdata *, int); 1235 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int); 1236 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int); 1237 void set_all_slowpath(struct hfi1_devdata *dd); 1238 1239 extern const struct pci_device_id hfi1_pci_tbl[]; 1240 1241 /* receive packet handler dispositions */ 1242 #define RCV_PKT_OK 0x0 /* keep going */ 1243 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ 1244 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ 1245 1246 /* calculate the current RHF address */ 1247 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) 1248 { 1249 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset; 1250 } 1251 1252 int hfi1_reset_device(int); 1253 1254 /* return the driver's idea of the logical OPA port state */ 1255 static inline u32 driver_lstate(struct hfi1_pportdata *ppd) 1256 { 1257 return ppd->lstate; /* use the cached value */ 1258 } 1259 1260 void receive_interrupt_work(struct work_struct *work); 1261 1262 /* extract service channel from header and rhf */ 1263 static inline int hdr2sc(struct ib_header *hdr, u64 rhf) 1264 { 1265 return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) | 1266 ((!!(rhf_dc_info(rhf))) << 4); 1267 } 1268 1269 #define HFI1_JKEY_WIDTH 16 1270 #define HFI1_JKEY_MASK (BIT(16) - 1) 1271 #define HFI1_ADMIN_JKEY_RANGE 32 1272 1273 /* 1274 * J_KEYs are split and allocated in the following groups: 1275 * 0 - 31 - users with administrator privileges 1276 * 32 - 63 - kernel protocols using KDETH packets 1277 * 64 - 65535 - all other users using KDETH packets 1278 */ 1279 static inline u16 generate_jkey(kuid_t uid) 1280 { 1281 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK; 1282 1283 if (capable(CAP_SYS_ADMIN)) 1284 jkey &= HFI1_ADMIN_JKEY_RANGE - 1; 1285 else if (jkey < 64) 1286 jkey |= BIT(HFI1_JKEY_WIDTH - 1); 1287 1288 return jkey; 1289 } 1290 1291 /* 1292 * active_egress_rate 1293 * 1294 * returns the active egress rate in units of [10^6 bits/sec] 1295 */ 1296 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) 1297 { 1298 u16 link_speed = ppd->link_speed_active; 1299 u16 link_width = ppd->link_width_active; 1300 u32 egress_rate; 1301 1302 if (link_speed == OPA_LINK_SPEED_25G) 1303 egress_rate = 25000; 1304 else /* assume OPA_LINK_SPEED_12_5G */ 1305 egress_rate = 12500; 1306 1307 switch (link_width) { 1308 case OPA_LINK_WIDTH_4X: 1309 egress_rate *= 4; 1310 break; 1311 case OPA_LINK_WIDTH_3X: 1312 egress_rate *= 3; 1313 break; 1314 case OPA_LINK_WIDTH_2X: 1315 egress_rate *= 2; 1316 break; 1317 default: 1318 /* assume IB_WIDTH_1X */ 1319 break; 1320 } 1321 1322 return egress_rate; 1323 } 1324 1325 /* 1326 * egress_cycles 1327 * 1328 * Returns the number of 'fabric clock cycles' to egress a packet 1329 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock 1330 * rate is (approximately) 805 MHz, the units of the returned value 1331 * are (1/805 MHz). 1332 */ 1333 static inline u32 egress_cycles(u32 len, u32 rate) 1334 { 1335 u32 cycles; 1336 1337 /* 1338 * cycles is: 1339 * 1340 * (length) [bits] / (rate) [bits/sec] 1341 * --------------------------------------------------- 1342 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] 1343 */ 1344 1345 cycles = len * 8; /* bits */ 1346 cycles *= 805; 1347 cycles /= rate; 1348 1349 return cycles; 1350 } 1351 1352 void set_link_ipg(struct hfi1_pportdata *ppd); 1353 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn, 1354 u32 rqpn, u8 svc_type); 1355 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, 1356 u32 pkey, u32 slid, u32 dlid, u8 sc5, 1357 const struct ib_grh *old_grh); 1358 #define PKEY_CHECK_INVALID -1 1359 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth, 1360 u8 sc5, int8_t s_pkey_index); 1361 1362 #define PACKET_EGRESS_TIMEOUT 350 1363 static inline void pause_for_credit_return(struct hfi1_devdata *dd) 1364 { 1365 /* Pause at least 1us, to ensure chip returns all credits */ 1366 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; 1367 1368 udelay(usec ? usec : 1); 1369 } 1370 1371 /** 1372 * sc_to_vlt() reverse lookup sc to vl 1373 * @dd - devdata 1374 * @sc5 - 5 bit sc 1375 */ 1376 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) 1377 { 1378 unsigned seq; 1379 u8 rval; 1380 1381 if (sc5 >= OPA_MAX_SCS) 1382 return (u8)(0xff); 1383 1384 do { 1385 seq = read_seqbegin(&dd->sc2vl_lock); 1386 rval = *(((u8 *)dd->sc2vl) + sc5); 1387 } while (read_seqretry(&dd->sc2vl_lock, seq)); 1388 1389 return rval; 1390 } 1391 1392 #define PKEY_MEMBER_MASK 0x8000 1393 #define PKEY_LOW_15_MASK 0x7fff 1394 1395 /* 1396 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent 1397 * being an entry from the ingress partition key table), return 0 1398 * otherwise. Use the matching criteria for ingress partition keys 1399 * specified in the OPAv1 spec., section 9.10.14. 1400 */ 1401 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) 1402 { 1403 u16 mkey = pkey & PKEY_LOW_15_MASK; 1404 u16 ment = ent & PKEY_LOW_15_MASK; 1405 1406 if (mkey == ment) { 1407 /* 1408 * If pkey[15] is clear (limited partition member), 1409 * is bit 15 in the corresponding table element 1410 * clear (limited member)? 1411 */ 1412 if (!(pkey & PKEY_MEMBER_MASK)) 1413 return !!(ent & PKEY_MEMBER_MASK); 1414 return 1; 1415 } 1416 return 0; 1417 } 1418 1419 /* 1420 * ingress_pkey_table_search - search the entire pkey table for 1421 * an entry which matches 'pkey'. return 0 if a match is found, 1422 * and 1 otherwise. 1423 */ 1424 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) 1425 { 1426 int i; 1427 1428 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1429 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1430 return 0; 1431 } 1432 return 1; 1433 } 1434 1435 /* 1436 * ingress_pkey_table_fail - record a failure of ingress pkey validation, 1437 * i.e., increment port_rcv_constraint_errors for the port, and record 1438 * the 'error info' for this failure. 1439 */ 1440 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, 1441 u16 slid) 1442 { 1443 struct hfi1_devdata *dd = ppd->dd; 1444 1445 incr_cntr64(&ppd->port_rcv_constraint_errors); 1446 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { 1447 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; 1448 dd->err_info_rcv_constraint.slid = slid; 1449 dd->err_info_rcv_constraint.pkey = pkey; 1450 } 1451 } 1452 1453 /* 1454 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 1455 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx 1456 * is a hint as to the best place in the partition key table to begin 1457 * searching. This function should not be called on the data path because 1458 * of performance reasons. On datapath pkey check is expected to be done 1459 * by HW and rcv_pkey_check function should be called instead. 1460 */ 1461 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1462 u8 sc5, u8 idx, u16 slid) 1463 { 1464 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1465 return 0; 1466 1467 /* If SC15, pkey[0:14] must be 0x7fff */ 1468 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1469 goto bad; 1470 1471 /* Is the pkey = 0x0, or 0x8000? */ 1472 if ((pkey & PKEY_LOW_15_MASK) == 0) 1473 goto bad; 1474 1475 /* The most likely matching pkey has index 'idx' */ 1476 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) 1477 return 0; 1478 1479 /* no match - try the whole table */ 1480 if (!ingress_pkey_table_search(ppd, pkey)) 1481 return 0; 1482 1483 bad: 1484 ingress_pkey_table_fail(ppd, pkey, slid); 1485 return 1; 1486 } 1487 1488 /* 1489 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 1490 * otherwise. It only ensures pkey is vlid for QP0. This function 1491 * should be called on the data path instead of ingress_pkey_check 1492 * as on data path, pkey check is done by HW (except for QP0). 1493 */ 1494 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1495 u8 sc5, u16 slid) 1496 { 1497 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1498 return 0; 1499 1500 /* If SC15, pkey[0:14] must be 0x7fff */ 1501 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1502 goto bad; 1503 1504 return 0; 1505 bad: 1506 ingress_pkey_table_fail(ppd, pkey, slid); 1507 return 1; 1508 } 1509 1510 /* MTU handling */ 1511 1512 /* MTU enumeration, 256-4k match IB */ 1513 #define OPA_MTU_0 0 1514 #define OPA_MTU_256 1 1515 #define OPA_MTU_512 2 1516 #define OPA_MTU_1024 3 1517 #define OPA_MTU_2048 4 1518 #define OPA_MTU_4096 5 1519 1520 u32 lrh_max_header_bytes(struct hfi1_devdata *dd); 1521 int mtu_to_enum(u32 mtu, int default_if_bad); 1522 u16 enum_to_mtu(int); 1523 static inline int valid_ib_mtu(unsigned int mtu) 1524 { 1525 return mtu == 256 || mtu == 512 || 1526 mtu == 1024 || mtu == 2048 || 1527 mtu == 4096; 1528 } 1529 1530 static inline int valid_opa_max_mtu(unsigned int mtu) 1531 { 1532 return mtu >= 2048 && 1533 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); 1534 } 1535 1536 int set_mtu(struct hfi1_pportdata *); 1537 1538 int hfi1_set_lid(struct hfi1_pportdata *, u32, u8); 1539 void hfi1_disable_after_error(struct hfi1_devdata *); 1540 int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int); 1541 int hfi1_rcvbuf_validate(u32, u8, u16 *); 1542 1543 int fm_get_table(struct hfi1_pportdata *, int, void *); 1544 int fm_set_table(struct hfi1_pportdata *, int, void *); 1545 1546 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); 1547 void reset_link_credits(struct hfi1_devdata *dd); 1548 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); 1549 1550 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); 1551 1552 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) 1553 { 1554 return ppd->dd; 1555 } 1556 1557 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) 1558 { 1559 return container_of(dev, struct hfi1_devdata, verbs_dev); 1560 } 1561 1562 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) 1563 { 1564 return dd_from_dev(to_idev(ibdev)); 1565 } 1566 1567 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) 1568 { 1569 return container_of(ibp, struct hfi1_pportdata, ibport_data); 1570 } 1571 1572 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) 1573 { 1574 return container_of(rdi, struct hfi1_ibdev, rdi); 1575 } 1576 1577 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) 1578 { 1579 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1580 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1581 1582 WARN_ON(pidx >= dd->num_pports); 1583 return &dd->pport[pidx].ibport_data; 1584 } 1585 1586 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd) 1587 { 1588 return &rcd->ppd->ibport_data; 1589 } 1590 1591 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt, 1592 bool do_cnp); 1593 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt, 1594 bool do_cnp) 1595 { 1596 struct ib_other_headers *ohdr = pkt->ohdr; 1597 u32 bth1; 1598 1599 bth1 = be32_to_cpu(ohdr->bth[1]); 1600 if (unlikely(bth1 & (HFI1_BECN_SMASK | HFI1_FECN_SMASK))) { 1601 hfi1_process_ecn_slowpath(qp, pkt, do_cnp); 1602 return bth1 & HFI1_FECN_SMASK; 1603 } 1604 return false; 1605 } 1606 1607 /* 1608 * Return the indexed PKEY from the port PKEY table. 1609 */ 1610 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) 1611 { 1612 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1613 u16 ret; 1614 1615 if (index >= ARRAY_SIZE(ppd->pkeys)) 1616 ret = 0; 1617 else 1618 ret = ppd->pkeys[index]; 1619 1620 return ret; 1621 } 1622 1623 /* 1624 * Return the indexed GUID from the port GUIDs table. 1625 */ 1626 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index) 1627 { 1628 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1629 1630 WARN_ON(index >= HFI1_GUIDS_PER_PORT); 1631 return cpu_to_be64(ppd->guids[index]); 1632 } 1633 1634 /* 1635 * Called by readers of cc_state only, must call under rcu_read_lock(). 1636 */ 1637 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) 1638 { 1639 return rcu_dereference(ppd->cc_state); 1640 } 1641 1642 /* 1643 * Called by writers of cc_state only, must call under cc_state_lock. 1644 */ 1645 static inline 1646 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd) 1647 { 1648 return rcu_dereference_protected(ppd->cc_state, 1649 lockdep_is_held(&ppd->cc_state_lock)); 1650 } 1651 1652 /* 1653 * values for dd->flags (_device_ related flags) 1654 */ 1655 #define HFI1_INITTED 0x1 /* chip and driver up and initted */ 1656 #define HFI1_PRESENT 0x2 /* chip accesses can be done */ 1657 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ 1658 #define HFI1_HAS_SDMA_TIMEOUT 0x8 1659 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ 1660 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ 1661 1662 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1663 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) 1664 1665 /* ctxt_flag bit offsets */ 1666 /* context has been setup */ 1667 #define HFI1_CTXT_SETUP_DONE 1 1668 /* waiting for a packet to arrive */ 1669 #define HFI1_CTXT_WAITING_RCV 2 1670 /* master has not finished initializing */ 1671 #define HFI1_CTXT_MASTER_UNINIT 4 1672 /* waiting for an urgent packet to arrive */ 1673 #define HFI1_CTXT_WAITING_URG 5 1674 1675 /* free up any allocated data at closes */ 1676 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *, 1677 const struct pci_device_id *); 1678 void hfi1_free_devdata(struct hfi1_devdata *); 1679 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra); 1680 1681 /* LED beaconing functions */ 1682 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, 1683 unsigned int timeoff); 1684 void shutdown_led_override(struct hfi1_pportdata *ppd); 1685 1686 #define HFI1_CREDIT_RETURN_RATE (100) 1687 1688 /* 1689 * The number of words for the KDETH protocol field. If this is 1690 * larger then the actual field used, then part of the payload 1691 * will be in the header. 1692 * 1693 * Optimally, we want this sized so that a typical case will 1694 * use full cache lines. The typical local KDETH header would 1695 * be: 1696 * 1697 * Bytes Field 1698 * 8 LRH 1699 * 12 BHT 1700 * ?? KDETH 1701 * 8 RHF 1702 * --- 1703 * 28 + KDETH 1704 * 1705 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS 1706 */ 1707 #define DEFAULT_RCVHDRSIZE 9 1708 1709 /* 1710 * Maximal header byte count: 1711 * 1712 * Bytes Field 1713 * 8 LRH 1714 * 40 GRH (optional) 1715 * 12 BTH 1716 * ?? KDETH 1717 * 8 RHF 1718 * --- 1719 * 68 + KDETH 1720 * 1721 * We also want to maintain a cache line alignment to assist DMA'ing 1722 * of the header bytes. Round up to a good size. 1723 */ 1724 #define DEFAULT_RCVHDR_ENTSIZE 32 1725 1726 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm, 1727 u32 nlocked, u32 npages); 1728 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr, 1729 size_t npages, bool writable, struct page **pages); 1730 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p, 1731 size_t npages, bool dirty); 1732 1733 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1734 { 1735 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; 1736 } 1737 1738 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1739 { 1740 /* 1741 * volatile because it's a DMA target from the chip, routine is 1742 * inlined, and don't want register caching or reordering. 1743 */ 1744 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); 1745 } 1746 1747 /* 1748 * sysfs interface. 1749 */ 1750 1751 extern const char ib_hfi1_version[]; 1752 1753 int hfi1_device_create(struct hfi1_devdata *); 1754 void hfi1_device_remove(struct hfi1_devdata *); 1755 1756 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, 1757 struct kobject *kobj); 1758 int hfi1_verbs_register_sysfs(struct hfi1_devdata *); 1759 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *); 1760 /* Hook for sysfs read of QSFP */ 1761 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); 1762 1763 int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *); 1764 void hfi1_pcie_cleanup(struct pci_dev *); 1765 int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *); 1766 void hfi1_pcie_ddcleanup(struct hfi1_devdata *); 1767 void hfi1_pcie_flr(struct hfi1_devdata *); 1768 int pcie_speeds(struct hfi1_devdata *); 1769 void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *); 1770 void hfi1_enable_intx(struct pci_dev *); 1771 void restore_pci_variables(struct hfi1_devdata *dd); 1772 int do_pcie_gen3_transition(struct hfi1_devdata *dd); 1773 int parse_platform_config(struct hfi1_devdata *dd); 1774 int get_platform_config_field(struct hfi1_devdata *dd, 1775 enum platform_config_table_type_encoding 1776 table_type, int table_index, int field_index, 1777 u32 *data, u32 len); 1778 1779 const char *get_unit_name(int unit); 1780 const char *get_card_name(struct rvt_dev_info *rdi); 1781 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); 1782 1783 /* 1784 * Flush write combining store buffers (if present) and perform a write 1785 * barrier. 1786 */ 1787 static inline void flush_wc(void) 1788 { 1789 asm volatile("sfence" : : : "memory"); 1790 } 1791 1792 void handle_eflags(struct hfi1_packet *packet); 1793 int process_receive_ib(struct hfi1_packet *packet); 1794 int process_receive_bypass(struct hfi1_packet *packet); 1795 int process_receive_error(struct hfi1_packet *packet); 1796 int kdeth_process_expected(struct hfi1_packet *packet); 1797 int kdeth_process_eager(struct hfi1_packet *packet); 1798 int process_receive_invalid(struct hfi1_packet *packet); 1799 1800 /* global module parameter variables */ 1801 extern unsigned int hfi1_max_mtu; 1802 extern unsigned int hfi1_cu; 1803 extern unsigned int user_credit_return_threshold; 1804 extern int num_user_contexts; 1805 extern unsigned long n_krcvqs; 1806 extern uint krcvqs[]; 1807 extern int krcvqsset; 1808 extern uint kdeth_qp; 1809 extern uint loopback; 1810 extern uint quick_linkup; 1811 extern uint rcv_intr_timeout; 1812 extern uint rcv_intr_count; 1813 extern uint rcv_intr_dynamic; 1814 extern ushort link_crc_mask; 1815 1816 extern struct mutex hfi1_mutex; 1817 1818 /* Number of seconds before our card status check... */ 1819 #define STATUS_TIMEOUT 60 1820 1821 #define DRIVER_NAME "hfi1" 1822 #define HFI1_USER_MINOR_BASE 0 1823 #define HFI1_TRACE_MINOR 127 1824 #define HFI1_NMINORS 255 1825 1826 #define PCI_VENDOR_ID_INTEL 0x8086 1827 #define PCI_DEVICE_ID_INTEL0 0x24f0 1828 #define PCI_DEVICE_ID_INTEL1 0x24f1 1829 1830 #define HFI1_PKT_USER_SC_INTEGRITY \ 1831 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ 1832 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \ 1833 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ 1834 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) 1835 1836 #define HFI1_PKT_KERNEL_SC_INTEGRITY \ 1837 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) 1838 1839 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, 1840 u16 ctxt_type) 1841 { 1842 u64 base_sc_integrity; 1843 1844 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ 1845 if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) 1846 return 0; 1847 1848 base_sc_integrity = 1849 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1850 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 1851 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1852 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1853 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1854 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 1855 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1856 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1857 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1858 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 1859 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1860 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1861 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 1862 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 1863 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 1864 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1865 1866 if (ctxt_type == SC_USER) 1867 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY; 1868 else 1869 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; 1870 1871 /* turn on send-side job key checks if !A0 */ 1872 if (!is_ax(dd)) 1873 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1874 1875 return base_sc_integrity; 1876 } 1877 1878 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) 1879 { 1880 u64 base_sdma_integrity; 1881 1882 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ 1883 if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) 1884 return 0; 1885 1886 base_sdma_integrity = 1887 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1888 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1889 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1890 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1891 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1892 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1893 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1894 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 1895 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1896 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1897 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 1898 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 1899 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 1900 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1901 1902 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) 1903 base_sdma_integrity |= 1904 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK; 1905 1906 /* turn on send-side job key checks if !A0 */ 1907 if (!is_ax(dd)) 1908 base_sdma_integrity |= 1909 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1910 1911 return base_sdma_integrity; 1912 } 1913 1914 /* 1915 * hfi1_early_err is used (only!) to print early errors before devdata is 1916 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1917 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is 1918 * the same as dd_dev_err, but is used when the message really needs 1919 * the IB port# to be definitive as to what's happening.. 1920 */ 1921 #define hfi1_early_err(dev, fmt, ...) \ 1922 dev_err(dev, fmt, ##__VA_ARGS__) 1923 1924 #define hfi1_early_info(dev, fmt, ...) \ 1925 dev_info(dev, fmt, ##__VA_ARGS__) 1926 1927 #define dd_dev_emerg(dd, fmt, ...) \ 1928 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ 1929 get_unit_name((dd)->unit), ##__VA_ARGS__) 1930 #define dd_dev_err(dd, fmt, ...) \ 1931 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1932 get_unit_name((dd)->unit), ##__VA_ARGS__) 1933 #define dd_dev_warn(dd, fmt, ...) \ 1934 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1935 get_unit_name((dd)->unit), ##__VA_ARGS__) 1936 1937 #define dd_dev_warn_ratelimited(dd, fmt, ...) \ 1938 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 1939 get_unit_name((dd)->unit), ##__VA_ARGS__) 1940 1941 #define dd_dev_info(dd, fmt, ...) \ 1942 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ 1943 get_unit_name((dd)->unit), ##__VA_ARGS__) 1944 1945 #define dd_dev_info_ratelimited(dd, fmt, ...) \ 1946 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 1947 get_unit_name((dd)->unit), ##__VA_ARGS__) 1948 1949 #define dd_dev_dbg(dd, fmt, ...) \ 1950 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ 1951 get_unit_name((dd)->unit), ##__VA_ARGS__) 1952 1953 #define hfi1_dev_porterr(dd, port, fmt, ...) \ 1954 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ 1955 get_unit_name((dd)->unit), (port), ##__VA_ARGS__) 1956 1957 /* 1958 * this is used for formatting hw error messages... 1959 */ 1960 struct hfi1_hwerror_msgs { 1961 u64 mask; 1962 const char *msg; 1963 size_t sz; 1964 }; 1965 1966 /* in intr.c... */ 1967 void hfi1_format_hwerrors(u64 hwerrs, 1968 const struct hfi1_hwerror_msgs *hwerrmsgs, 1969 size_t nhwerrmsgs, char *msg, size_t lmsg); 1970 1971 #define USER_OPCODE_CHECK_VAL 0xC0 1972 #define USER_OPCODE_CHECK_MASK 0xC0 1973 #define OPCODE_CHECK_VAL_DISABLED 0x0 1974 #define OPCODE_CHECK_MASK_DISABLED 0x0 1975 1976 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) 1977 { 1978 struct hfi1_pportdata *ppd; 1979 int i; 1980 1981 dd->z_int_counter = get_all_cpu_total(dd->int_counter); 1982 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); 1983 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); 1984 1985 ppd = (struct hfi1_pportdata *)(dd + 1); 1986 for (i = 0; i < dd->num_pports; i++, ppd++) { 1987 ppd->ibport_data.rvp.z_rc_acks = 1988 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); 1989 ppd->ibport_data.rvp.z_rc_qacks = 1990 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); 1991 } 1992 } 1993 1994 /* Control LED state */ 1995 static inline void setextled(struct hfi1_devdata *dd, u32 on) 1996 { 1997 if (on) 1998 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); 1999 else 2000 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); 2001 } 2002 2003 /* return the i2c resource given the target */ 2004 static inline u32 i2c_target(u32 target) 2005 { 2006 return target ? CR_I2C2 : CR_I2C1; 2007 } 2008 2009 /* return the i2c chain chip resource that this HFI uses for QSFP */ 2010 static inline u32 qsfp_resource(struct hfi1_devdata *dd) 2011 { 2012 return i2c_target(dd->hfi1_id); 2013 } 2014 2015 /* Is this device integrated or discrete? */ 2016 static inline bool is_integrated(struct hfi1_devdata *dd) 2017 { 2018 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1; 2019 } 2020 2021 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); 2022 2023 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev)) 2024 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev)) 2025 2026 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype } 2027 #define show_packettype(etype) \ 2028 __print_symbolic(etype, \ 2029 packettype_name(EXPECTED), \ 2030 packettype_name(EAGER), \ 2031 packettype_name(IB), \ 2032 packettype_name(ERROR), \ 2033 packettype_name(BYPASS)) 2034 2035 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode } 2036 #define show_ib_opcode(opcode) \ 2037 __print_symbolic(opcode, \ 2038 ib_opcode_name(RC_SEND_FIRST), \ 2039 ib_opcode_name(RC_SEND_MIDDLE), \ 2040 ib_opcode_name(RC_SEND_LAST), \ 2041 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \ 2042 ib_opcode_name(RC_SEND_ONLY), \ 2043 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \ 2044 ib_opcode_name(RC_RDMA_WRITE_FIRST), \ 2045 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \ 2046 ib_opcode_name(RC_RDMA_WRITE_LAST), \ 2047 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ 2048 ib_opcode_name(RC_RDMA_WRITE_ONLY), \ 2049 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ 2050 ib_opcode_name(RC_RDMA_READ_REQUEST), \ 2051 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \ 2052 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \ 2053 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \ 2054 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \ 2055 ib_opcode_name(RC_ACKNOWLEDGE), \ 2056 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \ 2057 ib_opcode_name(RC_COMPARE_SWAP), \ 2058 ib_opcode_name(RC_FETCH_ADD), \ 2059 ib_opcode_name(UC_SEND_FIRST), \ 2060 ib_opcode_name(UC_SEND_MIDDLE), \ 2061 ib_opcode_name(UC_SEND_LAST), \ 2062 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \ 2063 ib_opcode_name(UC_SEND_ONLY), \ 2064 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \ 2065 ib_opcode_name(UC_RDMA_WRITE_FIRST), \ 2066 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \ 2067 ib_opcode_name(UC_RDMA_WRITE_LAST), \ 2068 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \ 2069 ib_opcode_name(UC_RDMA_WRITE_ONLY), \ 2070 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \ 2071 ib_opcode_name(UD_SEND_ONLY), \ 2072 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \ 2073 ib_opcode_name(CNP)) 2074 #endif /* _HFI1_KERNEL_H */ 2075