1 #ifndef _HFI1_KERNEL_H 2 #define _HFI1_KERNEL_H 3 /* 4 * Copyright(c) 2015-2018 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 #include <linux/interrupt.h> 51 #include <linux/pci.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/mutex.h> 54 #include <linux/list.h> 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/idr.h> 58 #include <linux/io.h> 59 #include <linux/fs.h> 60 #include <linux/completion.h> 61 #include <linux/kref.h> 62 #include <linux/sched.h> 63 #include <linux/cdev.h> 64 #include <linux/delay.h> 65 #include <linux/kthread.h> 66 #include <linux/i2c.h> 67 #include <linux/i2c-algo-bit.h> 68 #include <rdma/ib_hdrs.h> 69 #include <rdma/opa_addr.h> 70 #include <linux/rhashtable.h> 71 #include <linux/netdevice.h> 72 #include <rdma/rdma_vt.h> 73 74 #include "chip_registers.h" 75 #include "common.h" 76 #include "verbs.h" 77 #include "pio.h" 78 #include "chip.h" 79 #include "mad.h" 80 #include "qsfp.h" 81 #include "platform.h" 82 #include "affinity.h" 83 #include "msix.h" 84 85 /* bumped 1 from s/w major version of TrueScale */ 86 #define HFI1_CHIP_VERS_MAJ 3U 87 88 /* don't care about this except printing */ 89 #define HFI1_CHIP_VERS_MIN 0U 90 91 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 92 #define HFI1_OUI 0x001175 93 #define HFI1_OUI_LSB 40 94 95 #define DROP_PACKET_OFF 0 96 #define DROP_PACKET_ON 1 97 98 #define NEIGHBOR_TYPE_HFI 0 99 #define NEIGHBOR_TYPE_SWITCH 1 100 101 extern unsigned long hfi1_cap_mask; 102 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) 103 #define HFI1_CAP_UGET_MASK(mask, cap) \ 104 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) 105 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) 106 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) 107 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) 108 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) 109 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ 110 HFI1_CAP_MISC_MASK) 111 /* Offline Disabled Reason is 4-bits */ 112 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) 113 114 /* 115 * Control context is always 0 and handles the error packets. 116 * It also handles the VL15 and multicast packets. 117 */ 118 #define HFI1_CTRL_CTXT 0 119 120 /* 121 * Driver context will store software counters for each of the events 122 * associated with these status registers 123 */ 124 #define NUM_CCE_ERR_STATUS_COUNTERS 41 125 #define NUM_RCV_ERR_STATUS_COUNTERS 64 126 #define NUM_MISC_ERR_STATUS_COUNTERS 13 127 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 128 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 129 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 130 #define NUM_SEND_ERR_STATUS_COUNTERS 3 131 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 132 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 133 134 /* 135 * per driver stats, either not device nor port-specific, or 136 * summed over all of the devices and ports. 137 * They are described by name via ipathfs filesystem, so layout 138 * and number of elements can change without breaking compatibility. 139 * If members are added or deleted hfi1_statnames[] in debugfs.c must 140 * change to match. 141 */ 142 struct hfi1_ib_stats { 143 __u64 sps_ints; /* number of interrupts handled */ 144 __u64 sps_errints; /* number of error interrupts */ 145 __u64 sps_txerrs; /* tx-related packet errors */ 146 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 147 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 148 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 149 __u64 sps_ctxts; /* number of contexts currently open */ 150 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 151 __u64 sps_buffull; 152 __u64 sps_hdrfull; 153 }; 154 155 extern struct hfi1_ib_stats hfi1_stats; 156 extern const struct pci_error_handlers hfi1_pci_err_handler; 157 158 /* 159 * First-cut criterion for "device is active" is 160 * two thousand dwords combined Tx, Rx traffic per 161 * 5-second interval. SMA packets are 64 dwords, 162 * and occur "a few per second", presumably each way. 163 */ 164 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) 165 166 /* 167 * Below contains all data related to a single context (formerly called port). 168 */ 169 170 struct hfi1_opcode_stats_perctx; 171 172 struct ctxt_eager_bufs { 173 struct eager_buffer { 174 void *addr; 175 dma_addr_t dma; 176 ssize_t len; 177 } *buffers; 178 struct { 179 void *addr; 180 dma_addr_t dma; 181 } *rcvtids; 182 u32 size; /* total size of eager buffers */ 183 u32 rcvtid_size; /* size of each eager rcv tid */ 184 u16 count; /* size of buffers array */ 185 u16 numbufs; /* number of buffers allocated */ 186 u16 alloced; /* number of rcvarray entries used */ 187 u16 threshold; /* head update threshold */ 188 }; 189 190 struct exp_tid_set { 191 struct list_head list; 192 u32 count; 193 }; 194 195 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); 196 struct hfi1_ctxtdata { 197 /* rcvhdrq base, needs mmap before useful */ 198 void *rcvhdrq; 199 /* kernel virtual address where hdrqtail is updated */ 200 volatile __le64 *rcvhdrtail_kvaddr; 201 /* so functions that need physical port can get it easily */ 202 struct hfi1_pportdata *ppd; 203 /* so file ops can get at unit */ 204 struct hfi1_devdata *dd; 205 /* this receive context's assigned PIO ACK send context */ 206 struct send_context *sc; 207 /* per context recv functions */ 208 const rhf_rcv_function_ptr *rhf_rcv_function_map; 209 /* 210 * The interrupt handler for a particular receive context can vary 211 * throughout it's lifetime. This is not a lock protected data member so 212 * it must be updated atomically and the prev and new value must always 213 * be valid. Worst case is we process an extra interrupt and up to 64 214 * packets with the wrong interrupt handler. 215 */ 216 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); 217 /* verbs rx_stats per rcd */ 218 struct hfi1_opcode_stats_perctx *opstats; 219 /* clear interrupt mask */ 220 u64 imask; 221 /* ctxt rcvhdrq head offset */ 222 u32 head; 223 /* number of rcvhdrq entries */ 224 u16 rcvhdrq_cnt; 225 u8 ireg; /* clear interrupt register */ 226 /* receive packet sequence counter */ 227 u8 seq_cnt; 228 /* size of each of the rcvhdrq entries */ 229 u8 rcvhdrqentsize; 230 /* offset of RHF within receive header entry */ 231 u8 rhf_offset; 232 /* dynamic receive available interrupt timeout */ 233 u8 rcvavail_timeout; 234 /* Indicates that this is vnic context */ 235 bool is_vnic; 236 /* vnic queue index this context is mapped to */ 237 u8 vnic_q_idx; 238 /* Is ASPM interrupt supported for this context */ 239 bool aspm_intr_supported; 240 /* ASPM state (enabled/disabled) for this context */ 241 bool aspm_enabled; 242 /* Is ASPM processing enabled for this context (in intr context) */ 243 bool aspm_intr_enable; 244 struct ctxt_eager_bufs egrbufs; 245 /* QPs waiting for context processing */ 246 struct list_head qp_wait_list; 247 /* tid allocation lists */ 248 struct exp_tid_set tid_group_list; 249 struct exp_tid_set tid_used_list; 250 struct exp_tid_set tid_full_list; 251 252 /* Timer for re-enabling ASPM if interrupt activity quiets down */ 253 struct timer_list aspm_timer; 254 /* per-context configuration flags */ 255 unsigned long flags; 256 /* array of tid_groups */ 257 struct tid_group *groups; 258 /* mmap of hdrq, must fit in 44 bits */ 259 dma_addr_t rcvhdrq_dma; 260 dma_addr_t rcvhdrqtailaddr_dma; 261 /* Last interrupt timestamp */ 262 ktime_t aspm_ts_last_intr; 263 /* Last timestamp at which we scheduled a timer for this context */ 264 ktime_t aspm_ts_timer_sched; 265 /* Lock to serialize between intr, timer intr and user threads */ 266 spinlock_t aspm_lock; 267 /* Reference count the base context usage */ 268 struct kref kref; 269 /* numa node of this context */ 270 int numa_id; 271 /* associated msix interrupt. */ 272 s16 msix_intr; 273 /* job key */ 274 u16 jkey; 275 /* number of RcvArray groups for this context. */ 276 u16 rcv_array_groups; 277 /* index of first eager TID entry. */ 278 u16 eager_base; 279 /* number of expected TID entries */ 280 u16 expected_count; 281 /* index of first expected TID entry. */ 282 u16 expected_base; 283 /* Device context index */ 284 u8 ctxt; 285 286 /* PSM Specific fields */ 287 /* lock protecting all Expected TID data */ 288 struct mutex exp_mutex; 289 /* when waiting for rcv or pioavail */ 290 wait_queue_head_t wait; 291 /* uuid from PSM */ 292 u8 uuid[16]; 293 /* same size as task_struct .comm[], command that opened context */ 294 char comm[TASK_COMM_LEN]; 295 /* Bitmask of in use context(s) */ 296 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS); 297 /* per-context event flags for fileops/intr communication */ 298 unsigned long event_flags; 299 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 300 void *subctxt_uregbase; 301 /* An array of pages for the eager receive buffers * N */ 302 void *subctxt_rcvegrbuf; 303 /* An array of pages for the eager header queue entries * N */ 304 void *subctxt_rcvhdr_base; 305 /* total number of polled urgent packets */ 306 u32 urgent; 307 /* saved total number of polled urgent packets for poll edge trigger */ 308 u32 urgent_poll; 309 /* Type of packets or conditions we want to poll for */ 310 u16 poll_type; 311 /* non-zero if ctxt is being shared. */ 312 u16 subctxt_id; 313 /* The version of the library which opened this ctxt */ 314 u32 userversion; 315 /* 316 * non-zero if ctxt can be shared, and defines the maximum number of 317 * sub-contexts for this device context. 318 */ 319 u8 subctxt_cnt; 320 321 }; 322 323 /** 324 * rcvhdrq_size - return total size in bytes for header queue 325 * @rcd: the receive context 326 * 327 * rcvhdrqentsize is in DWs, so we have to convert to bytes 328 * 329 */ 330 static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd) 331 { 332 return PAGE_ALIGN(rcd->rcvhdrq_cnt * 333 rcd->rcvhdrqentsize * sizeof(u32)); 334 } 335 336 /* 337 * Represents a single packet at a high level. Put commonly computed things in 338 * here so we do not have to keep doing them over and over. The rule of thumb is 339 * if something is used one time to derive some value, store that something in 340 * here. If it is used multiple times, then store the result of that derivation 341 * in here. 342 */ 343 struct hfi1_packet { 344 void *ebuf; 345 void *hdr; 346 void *payload; 347 struct hfi1_ctxtdata *rcd; 348 __le32 *rhf_addr; 349 struct rvt_qp *qp; 350 struct ib_other_headers *ohdr; 351 struct ib_grh *grh; 352 struct opa_16b_mgmt *mgmt; 353 u64 rhf; 354 u32 maxcnt; 355 u32 rhqoff; 356 u32 dlid; 357 u32 slid; 358 u16 tlen; 359 s16 etail; 360 u16 pkey; 361 u8 hlen; 362 u8 numpkt; 363 u8 rsize; 364 u8 updegr; 365 u8 etype; 366 u8 extra_byte; 367 u8 pad; 368 u8 sc; 369 u8 sl; 370 u8 opcode; 371 bool migrated; 372 }; 373 374 /* Packet types */ 375 #define HFI1_PKT_TYPE_9B 0 376 #define HFI1_PKT_TYPE_16B 1 377 378 /* 379 * OPA 16B Header 380 */ 381 #define OPA_16B_L4_MASK 0xFFull 382 #define OPA_16B_SC_MASK 0x1F00000ull 383 #define OPA_16B_SC_SHIFT 20 384 #define OPA_16B_LID_MASK 0xFFFFFull 385 #define OPA_16B_DLID_MASK 0xF000ull 386 #define OPA_16B_DLID_SHIFT 20 387 #define OPA_16B_DLID_HIGH_SHIFT 12 388 #define OPA_16B_SLID_MASK 0xF00ull 389 #define OPA_16B_SLID_SHIFT 20 390 #define OPA_16B_SLID_HIGH_SHIFT 8 391 #define OPA_16B_BECN_MASK 0x80000000ull 392 #define OPA_16B_BECN_SHIFT 31 393 #define OPA_16B_FECN_MASK 0x10000000ull 394 #define OPA_16B_FECN_SHIFT 28 395 #define OPA_16B_L2_MASK 0x60000000ull 396 #define OPA_16B_L2_SHIFT 29 397 #define OPA_16B_PKEY_MASK 0xFFFF0000ull 398 #define OPA_16B_PKEY_SHIFT 16 399 #define OPA_16B_LEN_MASK 0x7FF00000ull 400 #define OPA_16B_LEN_SHIFT 20 401 #define OPA_16B_RC_MASK 0xE000000ull 402 #define OPA_16B_RC_SHIFT 25 403 #define OPA_16B_AGE_MASK 0xFF0000ull 404 #define OPA_16B_AGE_SHIFT 16 405 #define OPA_16B_ENTROPY_MASK 0xFFFFull 406 407 /* 408 * OPA 16B L2/L4 Encodings 409 */ 410 #define OPA_16B_L4_9B 0x00 411 #define OPA_16B_L2_TYPE 0x02 412 #define OPA_16B_L4_FM 0x08 413 #define OPA_16B_L4_IB_LOCAL 0x09 414 #define OPA_16B_L4_IB_GLOBAL 0x0A 415 #define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR 416 417 /* 418 * OPA 16B Management 419 */ 420 #define OPA_16B_L4_FM_PAD 3 /* fixed 3B pad */ 421 #define OPA_16B_L4_FM_HLEN 24 /* 16B(16) + L4_FM(8) */ 422 423 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr) 424 { 425 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK); 426 } 427 428 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr) 429 { 430 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT); 431 } 432 433 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr) 434 { 435 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) | 436 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >> 437 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT)); 438 } 439 440 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr) 441 { 442 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) | 443 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >> 444 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT)); 445 } 446 447 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr) 448 { 449 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT); 450 } 451 452 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr) 453 { 454 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT); 455 } 456 457 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr) 458 { 459 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT); 460 } 461 462 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr) 463 { 464 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT); 465 } 466 467 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr) 468 { 469 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT); 470 } 471 472 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr) 473 { 474 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT); 475 } 476 477 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr) 478 { 479 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT); 480 } 481 482 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr) 483 { 484 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK); 485 } 486 487 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw)) 488 489 /* 490 * BTH 491 */ 492 #define OPA_16B_BTH_PAD_MASK 7 493 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr) 494 { 495 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) & 496 OPA_16B_BTH_PAD_MASK); 497 } 498 499 /* 500 * 16B Management 501 */ 502 #define OPA_16B_MGMT_QPN_MASK 0xFFFFFF 503 static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt) 504 { 505 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK; 506 } 507 508 static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt) 509 { 510 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK; 511 } 512 513 static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt, 514 u32 dest_qp, u32 src_qp) 515 { 516 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK); 517 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK); 518 } 519 520 struct rvt_sge_state; 521 522 /* 523 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 524 * Mostly for MADs that set or query link parameters, also ipath 525 * config interfaces 526 */ 527 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 528 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ 529 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 530 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ 531 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 532 #define HFI1_IB_CFG_SPD 5 /* current Link spd */ 533 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 534 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 535 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 536 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 537 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ 538 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 539 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 540 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 541 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 542 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 543 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ 544 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ 545 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 546 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 547 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ 548 549 /* 550 * HFI or Host Link States 551 * 552 * These describe the states the driver thinks the logical and physical 553 * states are in. Used as an argument to set_link_state(). Implemented 554 * as bits for easy multi-state checking. The actual state can only be 555 * one. 556 */ 557 #define __HLS_UP_INIT_BP 0 558 #define __HLS_UP_ARMED_BP 1 559 #define __HLS_UP_ACTIVE_BP 2 560 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ 561 #define __HLS_DN_POLL_BP 4 562 #define __HLS_DN_DISABLE_BP 5 563 #define __HLS_DN_OFFLINE_BP 6 564 #define __HLS_VERIFY_CAP_BP 7 565 #define __HLS_GOING_UP_BP 8 566 #define __HLS_GOING_OFFLINE_BP 9 567 #define __HLS_LINK_COOLDOWN_BP 10 568 569 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) 570 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) 571 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) 572 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ 573 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) 574 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) 575 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) 576 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) 577 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) 578 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) 579 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) 580 581 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) 582 #define HLS_DOWN ~(HLS_UP) 583 584 #define HLS_DEFAULT HLS_DN_POLL 585 586 /* use this MTU size if none other is given */ 587 #define HFI1_DEFAULT_ACTIVE_MTU 10240 588 /* use this MTU size as the default maximum */ 589 #define HFI1_DEFAULT_MAX_MTU 10240 590 /* default partition key */ 591 #define DEFAULT_PKEY 0xffff 592 593 /* 594 * Possible fabric manager config parameters for fm_{get,set}_table() 595 */ 596 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ 597 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ 598 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ 599 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ 600 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ 601 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ 602 603 /* 604 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 605 * these are bits so they can be combined, e.g. 606 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB 607 */ 608 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 609 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 610 #define HFI1_RCVCTRL_CTXT_ENB 0x04 611 #define HFI1_RCVCTRL_CTXT_DIS 0x08 612 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 613 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 614 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 615 #define HFI1_RCVCTRL_PKEY_DIS 0x80 616 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 617 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 618 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 619 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 620 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 621 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 622 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 623 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 624 #define HFI1_RCVCTRL_URGENT_ENB 0x40000 625 #define HFI1_RCVCTRL_URGENT_DIS 0x80000 626 627 /* partition enforcement flags */ 628 #define HFI1_PART_ENFORCE_IN 0x1 629 #define HFI1_PART_ENFORCE_OUT 0x2 630 631 /* how often we check for synthetic counter wrap around */ 632 #define SYNTH_CNT_TIME 3 633 634 /* Counter flags */ 635 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ 636 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ 637 #define CNTR_DISABLED 0x2 /* Disable this counter */ 638 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ 639 #define CNTR_VL 0x8 /* Per VL counter */ 640 #define CNTR_SDMA 0x10 641 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ 642 #define CNTR_MODE_W 0x0 643 #define CNTR_MODE_R 0x1 644 645 /* VLs Supported/Operational */ 646 #define HFI1_MIN_VLS_SUPPORTED 1 647 #define HFI1_MAX_VLS_SUPPORTED 8 648 649 #define HFI1_GUIDS_PER_PORT 5 650 #define HFI1_PORT_GUID_INDEX 0 651 652 static inline void incr_cntr64(u64 *cntr) 653 { 654 if (*cntr < (u64)-1LL) 655 (*cntr)++; 656 } 657 658 static inline void incr_cntr32(u32 *cntr) 659 { 660 if (*cntr < (u32)-1LL) 661 (*cntr)++; 662 } 663 664 #define MAX_NAME_SIZE 64 665 struct hfi1_msix_entry { 666 enum irq_type type; 667 int irq; 668 void *arg; 669 cpumask_t mask; 670 struct irq_affinity_notify notify; 671 }; 672 673 struct hfi1_msix_info { 674 /* lock to synchronize in_use_msix access */ 675 spinlock_t msix_lock; 676 DECLARE_BITMAP(in_use_msix, CCE_NUM_MSIX_VECTORS); 677 struct hfi1_msix_entry *msix_entries; 678 u16 max_requested; 679 }; 680 681 /* per-SL CCA information */ 682 struct cca_timer { 683 struct hrtimer hrtimer; 684 struct hfi1_pportdata *ppd; /* read-only */ 685 int sl; /* read-only */ 686 u16 ccti; /* read/write - current value of CCTI */ 687 }; 688 689 struct link_down_reason { 690 /* 691 * SMA-facing value. Should be set from .latest when 692 * HLS_UP_* -> HLS_DN_* transition actually occurs. 693 */ 694 u8 sma; 695 u8 latest; 696 }; 697 698 enum { 699 LO_PRIO_TABLE, 700 HI_PRIO_TABLE, 701 MAX_PRIO_TABLE 702 }; 703 704 struct vl_arb_cache { 705 /* protect vl arb cache */ 706 spinlock_t lock; 707 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; 708 }; 709 710 /* 711 * The structure below encapsulates data relevant to a physical IB Port. 712 * Current chips support only one such port, but the separation 713 * clarifies things a bit. Note that to conform to IB conventions, 714 * port-numbers are one-based. The first or only port is port1. 715 */ 716 struct hfi1_pportdata { 717 struct hfi1_ibport ibport_data; 718 719 struct hfi1_devdata *dd; 720 struct kobject pport_cc_kobj; 721 struct kobject sc2vl_kobj; 722 struct kobject sl2sc_kobj; 723 struct kobject vl2mtu_kobj; 724 725 /* PHY support */ 726 struct qsfp_data qsfp_info; 727 /* Values for SI tuning of SerDes */ 728 u32 port_type; 729 u32 tx_preset_eq; 730 u32 tx_preset_noeq; 731 u32 rx_preset; 732 u8 local_atten; 733 u8 remote_atten; 734 u8 default_atten; 735 u8 max_power_class; 736 737 /* did we read platform config from scratch registers? */ 738 bool config_from_scratch; 739 740 /* GUIDs for this interface, in host order, guids[0] is a port guid */ 741 u64 guids[HFI1_GUIDS_PER_PORT]; 742 743 /* GUID for peer interface, in host order */ 744 u64 neighbor_guid; 745 746 /* up or down physical link state */ 747 u32 linkup; 748 749 /* 750 * this address is mapped read-only into user processes so they can 751 * get status cheaply, whenever they want. One qword of status per port 752 */ 753 u64 *statusp; 754 755 /* SendDMA related entries */ 756 757 struct workqueue_struct *hfi1_wq; 758 struct workqueue_struct *link_wq; 759 760 /* move out of interrupt context */ 761 struct work_struct link_vc_work; 762 struct work_struct link_up_work; 763 struct work_struct link_down_work; 764 struct work_struct sma_message_work; 765 struct work_struct freeze_work; 766 struct work_struct link_downgrade_work; 767 struct work_struct link_bounce_work; 768 struct delayed_work start_link_work; 769 /* host link state variables */ 770 struct mutex hls_lock; 771 u32 host_link_state; 772 773 /* these are the "32 bit" regs */ 774 775 u32 ibmtu; /* The MTU programmed for this unit */ 776 /* 777 * Current max size IB packet (in bytes) including IB headers, that 778 * we can send. Changes when ibmtu changes. 779 */ 780 u32 ibmaxlen; 781 u32 current_egress_rate; /* units [10^6 bits/sec] */ 782 /* LID programmed for this instance */ 783 u32 lid; 784 /* list of pkeys programmed; 0 if not set */ 785 u16 pkeys[MAX_PKEY_VALUES]; 786 u16 link_width_supported; 787 u16 link_width_downgrade_supported; 788 u16 link_speed_supported; 789 u16 link_width_enabled; 790 u16 link_width_downgrade_enabled; 791 u16 link_speed_enabled; 792 u16 link_width_active; 793 u16 link_width_downgrade_tx_active; 794 u16 link_width_downgrade_rx_active; 795 u16 link_speed_active; 796 u8 vls_supported; 797 u8 vls_operational; 798 u8 actual_vls_operational; 799 /* LID mask control */ 800 u8 lmc; 801 /* Rx Polarity inversion (compensate for ~tx on partner) */ 802 u8 rx_pol_inv; 803 804 u8 hw_pidx; /* physical port index */ 805 u8 port; /* IB port number and index into dd->pports - 1 */ 806 /* type of neighbor node */ 807 u8 neighbor_type; 808 u8 neighbor_normal; 809 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ 810 u8 neighbor_port_number; 811 u8 is_sm_config_started; 812 u8 offline_disabled_reason; 813 u8 is_active_optimize_enabled; 814 u8 driver_link_ready; /* driver ready for active link */ 815 u8 link_enabled; /* link enabled? */ 816 u8 linkinit_reason; 817 u8 local_tx_rate; /* rate given to 8051 firmware */ 818 u8 qsfp_retry_count; 819 820 /* placeholders for IB MAD packet settings */ 821 u8 overrun_threshold; 822 u8 phy_error_threshold; 823 unsigned int is_link_down_queued; 824 825 /* Used to override LED behavior for things like maintenance beaconing*/ 826 /* 827 * Alternates per phase of blink 828 * [0] holds LED off duration, [1] holds LED on duration 829 */ 830 unsigned long led_override_vals[2]; 831 u8 led_override_phase; /* LSB picks from vals[] */ 832 atomic_t led_override_timer_active; 833 /* Used to flash LEDs in override mode */ 834 struct timer_list led_override_timer; 835 836 u32 sm_trap_qp; 837 u32 sa_qp; 838 839 /* 840 * cca_timer_lock protects access to the per-SL cca_timer 841 * structures (specifically the ccti member). 842 */ 843 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; 844 struct cca_timer cca_timer[OPA_MAX_SLS]; 845 846 /* List of congestion control table entries */ 847 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; 848 849 /* congestion entries, each entry corresponding to a SL */ 850 struct opa_congestion_setting_entry_shadow 851 congestion_entries[OPA_MAX_SLS]; 852 853 /* 854 * cc_state_lock protects (write) access to the per-port 855 * struct cc_state. 856 */ 857 spinlock_t cc_state_lock ____cacheline_aligned_in_smp; 858 859 struct cc_state __rcu *cc_state; 860 861 /* Total number of congestion control table entries */ 862 u16 total_cct_entry; 863 864 /* Bit map identifying service level */ 865 u32 cc_sl_control_map; 866 867 /* CA's max number of 64 entry units in the congestion control table */ 868 u8 cc_max_table_entries; 869 870 /* 871 * begin congestion log related entries 872 * cc_log_lock protects all congestion log related data 873 */ 874 spinlock_t cc_log_lock ____cacheline_aligned_in_smp; 875 u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; 876 u16 threshold_event_counter; 877 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; 878 int cc_log_idx; /* index for logging events */ 879 int cc_mad_idx; /* index for reporting events */ 880 /* end congestion log related entries */ 881 882 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; 883 884 /* port relative counter buffer */ 885 u64 *cntrs; 886 /* port relative synthetic counter buffer */ 887 u64 *scntrs; 888 /* port_xmit_discards are synthesized from different egress errors */ 889 u64 port_xmit_discards; 890 u64 port_xmit_discards_vl[C_VL_COUNT]; 891 u64 port_xmit_constraint_errors; 892 u64 port_rcv_constraint_errors; 893 /* count of 'link_err' interrupts from DC */ 894 u64 link_downed; 895 /* number of times link retrained successfully */ 896 u64 link_up; 897 /* number of times a link unknown frame was reported */ 898 u64 unknown_frame_count; 899 /* port_ltp_crc_mode is returned in 'portinfo' MADs */ 900 u16 port_ltp_crc_mode; 901 /* port_crc_mode_enabled is the crc we support */ 902 u8 port_crc_mode_enabled; 903 /* mgmt_allowed is also returned in 'portinfo' MADs */ 904 u8 mgmt_allowed; 905 u8 part_enforce; /* partition enforcement flags */ 906 struct link_down_reason local_link_down_reason; 907 struct link_down_reason neigh_link_down_reason; 908 /* Value to be sent to link peer on LinkDown .*/ 909 u8 remote_link_down_reason; 910 /* Error events that will cause a port bounce. */ 911 u32 port_error_action; 912 struct work_struct linkstate_active_work; 913 /* Does this port need to prescan for FECNs */ 914 bool cc_prescan; 915 /* 916 * Sample sendWaitCnt & sendWaitVlCnt during link transition 917 * and counter request. 918 */ 919 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1]; 920 u16 prev_link_width; 921 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1]; 922 }; 923 924 typedef void (*opcode_handler)(struct hfi1_packet *packet); 925 typedef void (*hfi1_make_req)(struct rvt_qp *qp, 926 struct hfi1_pkt_state *ps, 927 struct rvt_swqe *wqe); 928 extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[]; 929 930 931 /* return values for the RHF receive functions */ 932 #define RHF_RCV_CONTINUE 0 /* keep going */ 933 #define RHF_RCV_DONE 1 /* stop, this packet processed */ 934 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ 935 936 struct rcv_array_data { 937 u16 ngroups; 938 u16 nctxt_extra; 939 u8 group_size; 940 }; 941 942 struct per_vl_data { 943 u16 mtu; 944 struct send_context *sc; 945 }; 946 947 /* 16 to directly index */ 948 #define PER_VL_SEND_CONTEXTS 16 949 950 struct err_info_rcvport { 951 u8 status_and_code; 952 u64 packet_flit1; 953 u64 packet_flit2; 954 }; 955 956 struct err_info_constraint { 957 u8 status; 958 u16 pkey; 959 u32 slid; 960 }; 961 962 struct hfi1_temp { 963 unsigned int curr; /* current temperature */ 964 unsigned int lo_lim; /* low temperature limit */ 965 unsigned int hi_lim; /* high temperature limit */ 966 unsigned int crit_lim; /* critical temperature limit */ 967 u8 triggers; /* temperature triggers */ 968 }; 969 970 struct hfi1_i2c_bus { 971 struct hfi1_devdata *controlling_dd; /* current controlling device */ 972 struct i2c_adapter adapter; /* bus details */ 973 struct i2c_algo_bit_data algo; /* bus algorithm details */ 974 int num; /* bus number, 0 or 1 */ 975 }; 976 977 /* common data between shared ASIC HFIs */ 978 struct hfi1_asic_data { 979 struct hfi1_devdata *dds[2]; /* back pointers */ 980 struct mutex asic_resource_mutex; 981 struct hfi1_i2c_bus *i2c_bus0; 982 struct hfi1_i2c_bus *i2c_bus1; 983 }; 984 985 /* sizes for both the QP and RSM map tables */ 986 #define NUM_MAP_ENTRIES 256 987 #define NUM_MAP_REGS 32 988 989 /* 990 * Number of VNIC contexts used. Ensure it is less than or equal to 991 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE). 992 */ 993 #define HFI1_NUM_VNIC_CTXT 8 994 995 /* Number of VNIC RSM entries */ 996 #define NUM_VNIC_MAP_ENTRIES 8 997 998 /* Virtual NIC information */ 999 struct hfi1_vnic_data { 1000 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT]; 1001 struct kmem_cache *txreq_cache; 1002 u8 num_vports; 1003 struct idr vesw_idr; 1004 u8 rmt_start; 1005 u8 num_ctxt; 1006 }; 1007 1008 struct hfi1_vnic_vport_info; 1009 1010 /* device data struct now contains only "general per-device" info. 1011 * fields related to a physical IB port are in a hfi1_pportdata struct. 1012 */ 1013 struct sdma_engine; 1014 struct sdma_vl_map; 1015 1016 #define BOARD_VERS_MAX 96 /* how long the version string can be */ 1017 #define SERIAL_MAX 16 /* length of the serial number */ 1018 1019 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); 1020 struct hfi1_devdata { 1021 struct hfi1_ibdev verbs_dev; /* must be first */ 1022 struct list_head list; 1023 /* pointers to related structs for this device */ 1024 /* pci access data structure */ 1025 struct pci_dev *pcidev; 1026 struct cdev user_cdev; 1027 struct cdev diag_cdev; 1028 struct cdev ui_cdev; 1029 struct device *user_device; 1030 struct device *diag_device; 1031 struct device *ui_device; 1032 1033 /* first mapping up to RcvArray */ 1034 u8 __iomem *kregbase1; 1035 resource_size_t physaddr; 1036 1037 /* second uncached mapping from RcvArray to pio send buffers */ 1038 u8 __iomem *kregbase2; 1039 /* for detecting offset above kregbase2 address */ 1040 u32 base2_start; 1041 1042 /* Per VL data. Enough for all VLs but not all elements are set/used. */ 1043 struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; 1044 /* send context data */ 1045 struct send_context_info *send_contexts; 1046 /* map hardware send contexts to software index */ 1047 u8 *hw_to_sw; 1048 /* spinlock for allocating and releasing send context resources */ 1049 spinlock_t sc_lock; 1050 /* lock for pio_map */ 1051 spinlock_t pio_map_lock; 1052 /* Send Context initialization lock. */ 1053 spinlock_t sc_init_lock; 1054 /* lock for sdma_map */ 1055 spinlock_t sde_map_lock; 1056 /* array of kernel send contexts */ 1057 struct send_context **kernel_send_context; 1058 /* array of vl maps */ 1059 struct pio_vl_map __rcu *pio_map; 1060 /* default flags to last descriptor */ 1061 u64 default_desc1; 1062 1063 /* fields common to all SDMA engines */ 1064 1065 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ 1066 dma_addr_t sdma_heads_phys; 1067 void *sdma_pad_dma; /* DMA'ed by chip */ 1068 dma_addr_t sdma_pad_phys; 1069 /* for deallocation */ 1070 size_t sdma_heads_size; 1071 /* num used */ 1072 u32 num_sdma; 1073 /* array of engines sized by num_sdma */ 1074 struct sdma_engine *per_sdma; 1075 /* array of vl maps */ 1076 struct sdma_vl_map __rcu *sdma_map; 1077 /* SPC freeze waitqueue and variable */ 1078 wait_queue_head_t sdma_unfreeze_wq; 1079 atomic_t sdma_unfreeze_count; 1080 1081 u32 lcb_access_count; /* count of LCB users */ 1082 1083 /* common data between shared ASIC HFIs in this OS */ 1084 struct hfi1_asic_data *asic_data; 1085 1086 /* mem-mapped pointer to base of PIO buffers */ 1087 void __iomem *piobase; 1088 /* 1089 * write-combining mem-mapped pointer to base of RcvArray 1090 * memory. 1091 */ 1092 void __iomem *rcvarray_wc; 1093 /* 1094 * credit return base - a per-NUMA range of DMA address that 1095 * the chip will use to update the per-context free counter 1096 */ 1097 struct credit_return_base *cr_base; 1098 1099 /* send context numbers and sizes for each type */ 1100 struct sc_config_sizes sc_sizes[SC_MAX]; 1101 1102 char *boardname; /* human readable board info */ 1103 1104 /* reset value */ 1105 u64 z_int_counter; 1106 u64 z_rcv_limit; 1107 u64 z_send_schedule; 1108 1109 u64 __percpu *send_schedule; 1110 /* number of reserved contexts for VNIC usage */ 1111 u16 num_vnic_contexts; 1112 /* number of receive contexts in use by the driver */ 1113 u32 num_rcv_contexts; 1114 /* number of pio send contexts in use by the driver */ 1115 u32 num_send_contexts; 1116 /* 1117 * number of ctxts available for PSM open 1118 */ 1119 u32 freectxts; 1120 /* total number of available user/PSM contexts */ 1121 u32 num_user_contexts; 1122 /* base receive interrupt timeout, in CSR units */ 1123 u32 rcv_intr_timeout_csr; 1124 1125 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ 1126 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ 1127 spinlock_t uctxt_lock; /* protect rcd changes */ 1128 struct mutex dc8051_lock; /* exclusive access to 8051 */ 1129 struct workqueue_struct *update_cntr_wq; 1130 struct work_struct update_cntr_work; 1131 /* exclusive access to 8051 memory */ 1132 spinlock_t dc8051_memlock; 1133 int dc8051_timed_out; /* remember if the 8051 timed out */ 1134 /* 1135 * A page that will hold event notification bitmaps for all 1136 * contexts. This page will be mapped into all processes. 1137 */ 1138 unsigned long *events; 1139 /* 1140 * per unit status, see also portdata statusp 1141 * mapped read-only into user processes so they can get unit and 1142 * IB link status cheaply 1143 */ 1144 struct hfi1_status *status; 1145 1146 /* revision register shadow */ 1147 u64 revision; 1148 /* Base GUID for device (network order) */ 1149 u64 base_guid; 1150 1151 /* both sides of the PCIe link are gen3 capable */ 1152 u8 link_gen3_capable; 1153 u8 dc_shutdown; 1154 /* localbus width (1, 2,4,8,16,32) from config space */ 1155 u32 lbus_width; 1156 /* localbus speed in MHz */ 1157 u32 lbus_speed; 1158 int unit; /* unit # of this chip */ 1159 int node; /* home node of this chip */ 1160 1161 /* save these PCI fields to restore after a reset */ 1162 u32 pcibar0; 1163 u32 pcibar1; 1164 u32 pci_rom; 1165 u16 pci_command; 1166 u16 pcie_devctl; 1167 u16 pcie_lnkctl; 1168 u16 pcie_devctl2; 1169 u32 pci_msix0; 1170 u32 pci_tph2; 1171 1172 /* 1173 * ASCII serial number, from flash, large enough for original 1174 * all digit strings, and longer serial number format 1175 */ 1176 u8 serial[SERIAL_MAX]; 1177 /* human readable board version */ 1178 u8 boardversion[BOARD_VERS_MAX]; 1179 u8 lbus_info[32]; /* human readable localbus info */ 1180 /* chip major rev, from CceRevision */ 1181 u8 majrev; 1182 /* chip minor rev, from CceRevision */ 1183 u8 minrev; 1184 /* hardware ID */ 1185 u8 hfi1_id; 1186 /* implementation code */ 1187 u8 icode; 1188 /* vAU of this device */ 1189 u8 vau; 1190 /* vCU of this device */ 1191 u8 vcu; 1192 /* link credits of this device */ 1193 u16 link_credits; 1194 /* initial vl15 credits to use */ 1195 u16 vl15_init; 1196 1197 /* 1198 * Cached value for vl15buf, read during verify cap interrupt. VL15 1199 * credits are to be kept at 0 and set when handling the link-up 1200 * interrupt. This removes the possibility of receiving VL15 MAD 1201 * packets before this HFI is ready. 1202 */ 1203 u16 vl15buf_cached; 1204 1205 /* Misc small ints */ 1206 u8 n_krcv_queues; 1207 u8 qos_shift; 1208 1209 u16 irev; /* implementation revision */ 1210 u32 dc8051_ver; /* 8051 firmware version */ 1211 1212 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ 1213 struct platform_config platform_config; 1214 struct platform_config_cache pcfg_cache; 1215 1216 struct diag_client *diag_client; 1217 1218 /* general interrupt: mask of handled interrupts */ 1219 u64 gi_mask[CCE_NUM_INT_CSRS]; 1220 1221 struct rcv_array_data rcv_entries; 1222 1223 /* cycle length of PS* counters in HW (in picoseconds) */ 1224 u16 psxmitwait_check_rate; 1225 1226 /* 1227 * 64 bit synthetic counters 1228 */ 1229 struct timer_list synth_stats_timer; 1230 1231 /* MSI-X information */ 1232 struct hfi1_msix_info msix_info; 1233 1234 /* 1235 * device counters 1236 */ 1237 char *cntrnames; 1238 size_t cntrnameslen; 1239 size_t ndevcntrs; 1240 u64 *cntrs; 1241 u64 *scntrs; 1242 1243 /* 1244 * remembered values for synthetic counters 1245 */ 1246 u64 last_tx; 1247 u64 last_rx; 1248 1249 /* 1250 * per-port counters 1251 */ 1252 size_t nportcntrs; 1253 char *portcntrnames; 1254 size_t portcntrnameslen; 1255 1256 struct err_info_rcvport err_info_rcvport; 1257 struct err_info_constraint err_info_rcv_constraint; 1258 struct err_info_constraint err_info_xmit_constraint; 1259 1260 atomic_t drop_packet; 1261 u8 do_drop; 1262 u8 err_info_uncorrectable; 1263 u8 err_info_fmconfig; 1264 1265 /* 1266 * Software counters for the status bits defined by the 1267 * associated error status registers 1268 */ 1269 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; 1270 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; 1271 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; 1272 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; 1273 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; 1274 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; 1275 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; 1276 1277 /* Software counter that spans all contexts */ 1278 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; 1279 /* Software counter that spans all DMA engines */ 1280 u64 sw_send_dma_eng_err_status_cnt[ 1281 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; 1282 /* Software counter that aggregates all cce_err_status errors */ 1283 u64 sw_cce_err_status_aggregate; 1284 /* Software counter that aggregates all bypass packet rcv errors */ 1285 u64 sw_rcv_bypass_packet_errors; 1286 1287 /* Save the enabled LCB error bits */ 1288 u64 lcb_err_en; 1289 struct cpu_mask_set *comp_vect; 1290 int *comp_vect_mappings; 1291 u32 comp_vect_possible_cpus; 1292 1293 /* 1294 * Capability to have different send engines simply by changing a 1295 * pointer value. 1296 */ 1297 send_routine process_pio_send ____cacheline_aligned_in_smp; 1298 send_routine process_dma_send; 1299 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1300 u64 pbc, const void *from, size_t count); 1301 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx, 1302 struct hfi1_vnic_vport_info *vinfo, 1303 struct sk_buff *skb, u64 pbc, u8 plen); 1304 /* hfi1_pportdata, points to array of (physical) port-specific 1305 * data structs, indexed by pidx (0..n-1) 1306 */ 1307 struct hfi1_pportdata *pport; 1308 /* receive context data */ 1309 struct hfi1_ctxtdata **rcd; 1310 u64 __percpu *int_counter; 1311 /* verbs tx opcode stats */ 1312 struct hfi1_opcode_stats_perctx __percpu *tx_opstats; 1313 /* device (not port) flags, basically device capabilities */ 1314 u16 flags; 1315 /* Number of physical ports available */ 1316 u8 num_pports; 1317 /* Lowest context number which can be used by user processes or VNIC */ 1318 u8 first_dyn_alloc_ctxt; 1319 /* adding a new field here would make it part of this cacheline */ 1320 1321 /* seqlock for sc2vl */ 1322 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp; 1323 u64 sc2vl[4]; 1324 u64 __percpu *rcv_limit; 1325 /* adding a new field here would make it part of this cacheline */ 1326 1327 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ 1328 u8 oui1; 1329 u8 oui2; 1330 u8 oui3; 1331 1332 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1333 struct timer_list rcverr_timer; 1334 1335 wait_queue_head_t event_queue; 1336 1337 /* receive context tail dummy address */ 1338 __le64 *rcvhdrtail_dummy_kvaddr; 1339 dma_addr_t rcvhdrtail_dummy_dma; 1340 1341 u32 rcv_ovfl_cnt; 1342 /* Serialize ASPM enable/disable between multiple verbs contexts */ 1343 spinlock_t aspm_lock; 1344 /* Number of verbs contexts which have disabled ASPM */ 1345 atomic_t aspm_disabled_cnt; 1346 /* Keeps track of user space clients */ 1347 atomic_t user_refcount; 1348 /* Used to wait for outstanding user space clients before dev removal */ 1349 struct completion user_comp; 1350 1351 bool eprom_available; /* true if EPROM is available for this device */ 1352 bool aspm_supported; /* Does HW support ASPM */ 1353 bool aspm_enabled; /* ASPM state: enabled/disabled */ 1354 struct rhashtable *sdma_rht; 1355 1356 struct kobject kobj; 1357 1358 /* vnic data */ 1359 struct hfi1_vnic_data vnic; 1360 /* Lock to protect IRQ SRC register access */ 1361 spinlock_t irq_src_lock; 1362 }; 1363 1364 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare) 1365 { 1366 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES; 1367 } 1368 1369 /* 8051 firmware version helper */ 1370 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c)) 1371 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16) 1372 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8) 1373 #define dc8051_ver_patch(a) ((a) & 0x0000ff) 1374 1375 /* f_put_tid types */ 1376 #define PT_EXPECTED 0 1377 #define PT_EAGER 1 1378 #define PT_INVALID_FLUSH 2 1379 #define PT_INVALID 3 1380 1381 struct tid_rb_node; 1382 struct mmu_rb_node; 1383 struct mmu_rb_handler; 1384 1385 /* Private data for file operations */ 1386 struct hfi1_filedata { 1387 struct hfi1_devdata *dd; 1388 struct hfi1_ctxtdata *uctxt; 1389 struct hfi1_user_sdma_comp_q *cq; 1390 struct hfi1_user_sdma_pkt_q *pq; 1391 u16 subctxt; 1392 /* for cpu affinity; -1 if none */ 1393 int rec_cpu_num; 1394 u32 tid_n_pinned; 1395 struct mmu_rb_handler *handler; 1396 struct tid_rb_node **entry_to_rb; 1397 spinlock_t tid_lock; /* protect tid_[limit,used] counters */ 1398 u32 tid_limit; 1399 u32 tid_used; 1400 u32 *invalid_tids; 1401 u32 invalid_tid_idx; 1402 /* protect invalid_tids array and invalid_tid_idx */ 1403 spinlock_t invalid_lock; 1404 struct mm_struct *mm; 1405 }; 1406 1407 extern struct list_head hfi1_dev_list; 1408 extern spinlock_t hfi1_devs_lock; 1409 struct hfi1_devdata *hfi1_lookup(int unit); 1410 1411 static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt) 1412 { 1413 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) * 1414 HFI1_MAX_SHARED_CTXTS; 1415 } 1416 1417 int hfi1_init(struct hfi1_devdata *dd, int reinit); 1418 int hfi1_count_active_units(void); 1419 1420 int hfi1_diag_add(struct hfi1_devdata *dd); 1421 void hfi1_diag_remove(struct hfi1_devdata *dd); 1422 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); 1423 1424 void handle_user_interrupt(struct hfi1_ctxtdata *rcd); 1425 1426 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); 1427 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd); 1428 int hfi1_create_kctxts(struct hfi1_devdata *dd); 1429 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa, 1430 struct hfi1_ctxtdata **rcd); 1431 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd); 1432 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, 1433 struct hfi1_devdata *dd, u8 hw_pidx, u8 port); 1434 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); 1435 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd); 1436 void hfi1_rcd_get(struct hfi1_ctxtdata *rcd); 1437 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd, 1438 u16 ctxt); 1439 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt); 1440 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread); 1441 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread); 1442 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread); 1443 void set_all_slowpath(struct hfi1_devdata *dd); 1444 1445 extern const struct pci_device_id hfi1_pci_tbl[]; 1446 void hfi1_make_ud_req_9B(struct rvt_qp *qp, 1447 struct hfi1_pkt_state *ps, 1448 struct rvt_swqe *wqe); 1449 1450 void hfi1_make_ud_req_16B(struct rvt_qp *qp, 1451 struct hfi1_pkt_state *ps, 1452 struct rvt_swqe *wqe); 1453 1454 /* receive packet handler dispositions */ 1455 #define RCV_PKT_OK 0x0 /* keep going */ 1456 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ 1457 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ 1458 1459 /* calculate the current RHF address */ 1460 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) 1461 { 1462 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset; 1463 } 1464 1465 int hfi1_reset_device(int); 1466 1467 void receive_interrupt_work(struct work_struct *work); 1468 1469 /* extract service channel from header and rhf */ 1470 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf) 1471 { 1472 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4); 1473 } 1474 1475 #define HFI1_JKEY_WIDTH 16 1476 #define HFI1_JKEY_MASK (BIT(16) - 1) 1477 #define HFI1_ADMIN_JKEY_RANGE 32 1478 1479 /* 1480 * J_KEYs are split and allocated in the following groups: 1481 * 0 - 31 - users with administrator privileges 1482 * 32 - 63 - kernel protocols using KDETH packets 1483 * 64 - 65535 - all other users using KDETH packets 1484 */ 1485 static inline u16 generate_jkey(kuid_t uid) 1486 { 1487 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK; 1488 1489 if (capable(CAP_SYS_ADMIN)) 1490 jkey &= HFI1_ADMIN_JKEY_RANGE - 1; 1491 else if (jkey < 64) 1492 jkey |= BIT(HFI1_JKEY_WIDTH - 1); 1493 1494 return jkey; 1495 } 1496 1497 /* 1498 * active_egress_rate 1499 * 1500 * returns the active egress rate in units of [10^6 bits/sec] 1501 */ 1502 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) 1503 { 1504 u16 link_speed = ppd->link_speed_active; 1505 u16 link_width = ppd->link_width_active; 1506 u32 egress_rate; 1507 1508 if (link_speed == OPA_LINK_SPEED_25G) 1509 egress_rate = 25000; 1510 else /* assume OPA_LINK_SPEED_12_5G */ 1511 egress_rate = 12500; 1512 1513 switch (link_width) { 1514 case OPA_LINK_WIDTH_4X: 1515 egress_rate *= 4; 1516 break; 1517 case OPA_LINK_WIDTH_3X: 1518 egress_rate *= 3; 1519 break; 1520 case OPA_LINK_WIDTH_2X: 1521 egress_rate *= 2; 1522 break; 1523 default: 1524 /* assume IB_WIDTH_1X */ 1525 break; 1526 } 1527 1528 return egress_rate; 1529 } 1530 1531 /* 1532 * egress_cycles 1533 * 1534 * Returns the number of 'fabric clock cycles' to egress a packet 1535 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock 1536 * rate is (approximately) 805 MHz, the units of the returned value 1537 * are (1/805 MHz). 1538 */ 1539 static inline u32 egress_cycles(u32 len, u32 rate) 1540 { 1541 u32 cycles; 1542 1543 /* 1544 * cycles is: 1545 * 1546 * (length) [bits] / (rate) [bits/sec] 1547 * --------------------------------------------------- 1548 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] 1549 */ 1550 1551 cycles = len * 8; /* bits */ 1552 cycles *= 805; 1553 cycles /= rate; 1554 1555 return cycles; 1556 } 1557 1558 void set_link_ipg(struct hfi1_pportdata *ppd); 1559 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn, 1560 u32 rqpn, u8 svc_type); 1561 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, 1562 u16 pkey, u32 slid, u32 dlid, u8 sc5, 1563 const struct ib_grh *old_grh); 1564 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp, 1565 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid, 1566 u8 sc5, const struct ib_grh *old_grh); 1567 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp, 1568 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid, 1569 u8 sc5, const struct ib_grh *old_grh); 1570 1571 #define PKEY_CHECK_INVALID -1 1572 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey, 1573 u8 sc5, int8_t s_pkey_index); 1574 1575 #define PACKET_EGRESS_TIMEOUT 350 1576 static inline void pause_for_credit_return(struct hfi1_devdata *dd) 1577 { 1578 /* Pause at least 1us, to ensure chip returns all credits */ 1579 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; 1580 1581 udelay(usec ? usec : 1); 1582 } 1583 1584 /** 1585 * sc_to_vlt() reverse lookup sc to vl 1586 * @dd - devdata 1587 * @sc5 - 5 bit sc 1588 */ 1589 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) 1590 { 1591 unsigned seq; 1592 u8 rval; 1593 1594 if (sc5 >= OPA_MAX_SCS) 1595 return (u8)(0xff); 1596 1597 do { 1598 seq = read_seqbegin(&dd->sc2vl_lock); 1599 rval = *(((u8 *)dd->sc2vl) + sc5); 1600 } while (read_seqretry(&dd->sc2vl_lock, seq)); 1601 1602 return rval; 1603 } 1604 1605 #define PKEY_MEMBER_MASK 0x8000 1606 #define PKEY_LOW_15_MASK 0x7fff 1607 1608 /* 1609 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent 1610 * being an entry from the ingress partition key table), return 0 1611 * otherwise. Use the matching criteria for ingress partition keys 1612 * specified in the OPAv1 spec., section 9.10.14. 1613 */ 1614 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) 1615 { 1616 u16 mkey = pkey & PKEY_LOW_15_MASK; 1617 u16 ment = ent & PKEY_LOW_15_MASK; 1618 1619 if (mkey == ment) { 1620 /* 1621 * If pkey[15] is clear (limited partition member), 1622 * is bit 15 in the corresponding table element 1623 * clear (limited member)? 1624 */ 1625 if (!(pkey & PKEY_MEMBER_MASK)) 1626 return !!(ent & PKEY_MEMBER_MASK); 1627 return 1; 1628 } 1629 return 0; 1630 } 1631 1632 /* 1633 * ingress_pkey_table_search - search the entire pkey table for 1634 * an entry which matches 'pkey'. return 0 if a match is found, 1635 * and 1 otherwise. 1636 */ 1637 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) 1638 { 1639 int i; 1640 1641 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1642 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1643 return 0; 1644 } 1645 return 1; 1646 } 1647 1648 /* 1649 * ingress_pkey_table_fail - record a failure of ingress pkey validation, 1650 * i.e., increment port_rcv_constraint_errors for the port, and record 1651 * the 'error info' for this failure. 1652 */ 1653 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, 1654 u32 slid) 1655 { 1656 struct hfi1_devdata *dd = ppd->dd; 1657 1658 incr_cntr64(&ppd->port_rcv_constraint_errors); 1659 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { 1660 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; 1661 dd->err_info_rcv_constraint.slid = slid; 1662 dd->err_info_rcv_constraint.pkey = pkey; 1663 } 1664 } 1665 1666 /* 1667 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 1668 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx 1669 * is a hint as to the best place in the partition key table to begin 1670 * searching. This function should not be called on the data path because 1671 * of performance reasons. On datapath pkey check is expected to be done 1672 * by HW and rcv_pkey_check function should be called instead. 1673 */ 1674 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1675 u8 sc5, u8 idx, u32 slid, bool force) 1676 { 1677 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1678 return 0; 1679 1680 /* If SC15, pkey[0:14] must be 0x7fff */ 1681 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1682 goto bad; 1683 1684 /* Is the pkey = 0x0, or 0x8000? */ 1685 if ((pkey & PKEY_LOW_15_MASK) == 0) 1686 goto bad; 1687 1688 /* The most likely matching pkey has index 'idx' */ 1689 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) 1690 return 0; 1691 1692 /* no match - try the whole table */ 1693 if (!ingress_pkey_table_search(ppd, pkey)) 1694 return 0; 1695 1696 bad: 1697 ingress_pkey_table_fail(ppd, pkey, slid); 1698 return 1; 1699 } 1700 1701 /* 1702 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 1703 * otherwise. It only ensures pkey is vlid for QP0. This function 1704 * should be called on the data path instead of ingress_pkey_check 1705 * as on data path, pkey check is done by HW (except for QP0). 1706 */ 1707 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1708 u8 sc5, u16 slid) 1709 { 1710 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1711 return 0; 1712 1713 /* If SC15, pkey[0:14] must be 0x7fff */ 1714 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1715 goto bad; 1716 1717 return 0; 1718 bad: 1719 ingress_pkey_table_fail(ppd, pkey, slid); 1720 return 1; 1721 } 1722 1723 /* MTU handling */ 1724 1725 /* MTU enumeration, 256-4k match IB */ 1726 #define OPA_MTU_0 0 1727 #define OPA_MTU_256 1 1728 #define OPA_MTU_512 2 1729 #define OPA_MTU_1024 3 1730 #define OPA_MTU_2048 4 1731 #define OPA_MTU_4096 5 1732 1733 u32 lrh_max_header_bytes(struct hfi1_devdata *dd); 1734 int mtu_to_enum(u32 mtu, int default_if_bad); 1735 u16 enum_to_mtu(int mtu); 1736 static inline int valid_ib_mtu(unsigned int mtu) 1737 { 1738 return mtu == 256 || mtu == 512 || 1739 mtu == 1024 || mtu == 2048 || 1740 mtu == 4096; 1741 } 1742 1743 static inline int valid_opa_max_mtu(unsigned int mtu) 1744 { 1745 return mtu >= 2048 && 1746 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); 1747 } 1748 1749 int set_mtu(struct hfi1_pportdata *ppd); 1750 1751 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc); 1752 void hfi1_disable_after_error(struct hfi1_devdata *dd); 1753 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit); 1754 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode); 1755 1756 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t); 1757 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t); 1758 1759 void set_up_vau(struct hfi1_devdata *dd, u8 vau); 1760 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf); 1761 void reset_link_credits(struct hfi1_devdata *dd); 1762 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); 1763 1764 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); 1765 1766 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) 1767 { 1768 return ppd->dd; 1769 } 1770 1771 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) 1772 { 1773 return container_of(dev, struct hfi1_devdata, verbs_dev); 1774 } 1775 1776 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) 1777 { 1778 return dd_from_dev(to_idev(ibdev)); 1779 } 1780 1781 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) 1782 { 1783 return container_of(ibp, struct hfi1_pportdata, ibport_data); 1784 } 1785 1786 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) 1787 { 1788 return container_of(rdi, struct hfi1_ibdev, rdi); 1789 } 1790 1791 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) 1792 { 1793 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1794 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1795 1796 WARN_ON(pidx >= dd->num_pports); 1797 return &dd->pport[pidx].ibport_data; 1798 } 1799 1800 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd) 1801 { 1802 return &rcd->ppd->ibport_data; 1803 } 1804 1805 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt, 1806 bool do_cnp); 1807 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt, 1808 bool do_cnp) 1809 { 1810 bool becn; 1811 bool fecn; 1812 1813 if (pkt->etype == RHF_RCV_TYPE_BYPASS) { 1814 fecn = hfi1_16B_get_fecn(pkt->hdr); 1815 becn = hfi1_16B_get_becn(pkt->hdr); 1816 } else { 1817 fecn = ib_bth_get_fecn(pkt->ohdr); 1818 becn = ib_bth_get_becn(pkt->ohdr); 1819 } 1820 if (unlikely(fecn || becn)) { 1821 hfi1_process_ecn_slowpath(qp, pkt, do_cnp); 1822 return fecn; 1823 } 1824 return false; 1825 } 1826 1827 /* 1828 * Return the indexed PKEY from the port PKEY table. 1829 */ 1830 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) 1831 { 1832 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1833 u16 ret; 1834 1835 if (index >= ARRAY_SIZE(ppd->pkeys)) 1836 ret = 0; 1837 else 1838 ret = ppd->pkeys[index]; 1839 1840 return ret; 1841 } 1842 1843 /* 1844 * Return the indexed GUID from the port GUIDs table. 1845 */ 1846 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index) 1847 { 1848 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1849 1850 WARN_ON(index >= HFI1_GUIDS_PER_PORT); 1851 return cpu_to_be64(ppd->guids[index]); 1852 } 1853 1854 /* 1855 * Called by readers of cc_state only, must call under rcu_read_lock(). 1856 */ 1857 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) 1858 { 1859 return rcu_dereference(ppd->cc_state); 1860 } 1861 1862 /* 1863 * Called by writers of cc_state only, must call under cc_state_lock. 1864 */ 1865 static inline 1866 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd) 1867 { 1868 return rcu_dereference_protected(ppd->cc_state, 1869 lockdep_is_held(&ppd->cc_state_lock)); 1870 } 1871 1872 /* 1873 * values for dd->flags (_device_ related flags) 1874 */ 1875 #define HFI1_INITTED 0x1 /* chip and driver up and initted */ 1876 #define HFI1_PRESENT 0x2 /* chip accesses can be done */ 1877 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ 1878 #define HFI1_HAS_SDMA_TIMEOUT 0x8 1879 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ 1880 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ 1881 #define HFI1_SHUTDOWN 0x100 /* device is shutting down */ 1882 1883 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1884 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) 1885 1886 /* ctxt_flag bit offsets */ 1887 /* base context has not finished initializing */ 1888 #define HFI1_CTXT_BASE_UNINIT 1 1889 /* base context initaliation failed */ 1890 #define HFI1_CTXT_BASE_FAILED 2 1891 /* waiting for a packet to arrive */ 1892 #define HFI1_CTXT_WAITING_RCV 3 1893 /* waiting for an urgent packet to arrive */ 1894 #define HFI1_CTXT_WAITING_URG 4 1895 1896 /* free up any allocated data at closes */ 1897 int hfi1_init_dd(struct hfi1_devdata *dd); 1898 void hfi1_free_devdata(struct hfi1_devdata *dd); 1899 1900 /* LED beaconing functions */ 1901 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, 1902 unsigned int timeoff); 1903 void shutdown_led_override(struct hfi1_pportdata *ppd); 1904 1905 #define HFI1_CREDIT_RETURN_RATE (100) 1906 1907 /* 1908 * The number of words for the KDETH protocol field. If this is 1909 * larger then the actual field used, then part of the payload 1910 * will be in the header. 1911 * 1912 * Optimally, we want this sized so that a typical case will 1913 * use full cache lines. The typical local KDETH header would 1914 * be: 1915 * 1916 * Bytes Field 1917 * 8 LRH 1918 * 12 BHT 1919 * ?? KDETH 1920 * 8 RHF 1921 * --- 1922 * 28 + KDETH 1923 * 1924 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS 1925 */ 1926 #define DEFAULT_RCVHDRSIZE 9 1927 1928 /* 1929 * Maximal header byte count: 1930 * 1931 * Bytes Field 1932 * 8 LRH 1933 * 40 GRH (optional) 1934 * 12 BTH 1935 * ?? KDETH 1936 * 8 RHF 1937 * --- 1938 * 68 + KDETH 1939 * 1940 * We also want to maintain a cache line alignment to assist DMA'ing 1941 * of the header bytes. Round up to a good size. 1942 */ 1943 #define DEFAULT_RCVHDR_ENTSIZE 32 1944 1945 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm, 1946 u32 nlocked, u32 npages); 1947 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr, 1948 size_t npages, bool writable, struct page **pages); 1949 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p, 1950 size_t npages, bool dirty); 1951 1952 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1953 { 1954 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; 1955 } 1956 1957 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1958 { 1959 /* 1960 * volatile because it's a DMA target from the chip, routine is 1961 * inlined, and don't want register caching or reordering. 1962 */ 1963 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); 1964 } 1965 1966 /* 1967 * sysfs interface. 1968 */ 1969 1970 extern const char ib_hfi1_version[]; 1971 extern const struct attribute_group ib_hfi1_attr_group; 1972 1973 int hfi1_device_create(struct hfi1_devdata *dd); 1974 void hfi1_device_remove(struct hfi1_devdata *dd); 1975 1976 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, 1977 struct kobject *kobj); 1978 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd); 1979 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd); 1980 /* Hook for sysfs read of QSFP */ 1981 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); 1982 1983 int hfi1_pcie_init(struct hfi1_devdata *dd); 1984 void hfi1_pcie_cleanup(struct pci_dev *pdev); 1985 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev); 1986 void hfi1_pcie_ddcleanup(struct hfi1_devdata *); 1987 int pcie_speeds(struct hfi1_devdata *dd); 1988 int restore_pci_variables(struct hfi1_devdata *dd); 1989 int save_pci_variables(struct hfi1_devdata *dd); 1990 int do_pcie_gen3_transition(struct hfi1_devdata *dd); 1991 void tune_pcie_caps(struct hfi1_devdata *dd); 1992 int parse_platform_config(struct hfi1_devdata *dd); 1993 int get_platform_config_field(struct hfi1_devdata *dd, 1994 enum platform_config_table_type_encoding 1995 table_type, int table_index, int field_index, 1996 u32 *data, u32 len); 1997 1998 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); 1999 2000 /* 2001 * Flush write combining store buffers (if present) and perform a write 2002 * barrier. 2003 */ 2004 static inline void flush_wc(void) 2005 { 2006 asm volatile("sfence" : : : "memory"); 2007 } 2008 2009 void handle_eflags(struct hfi1_packet *packet); 2010 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd); 2011 2012 /* global module parameter variables */ 2013 extern unsigned int hfi1_max_mtu; 2014 extern unsigned int hfi1_cu; 2015 extern unsigned int user_credit_return_threshold; 2016 extern int num_user_contexts; 2017 extern unsigned long n_krcvqs; 2018 extern uint krcvqs[]; 2019 extern int krcvqsset; 2020 extern uint kdeth_qp; 2021 extern uint loopback; 2022 extern uint quick_linkup; 2023 extern uint rcv_intr_timeout; 2024 extern uint rcv_intr_count; 2025 extern uint rcv_intr_dynamic; 2026 extern ushort link_crc_mask; 2027 2028 extern struct mutex hfi1_mutex; 2029 2030 /* Number of seconds before our card status check... */ 2031 #define STATUS_TIMEOUT 60 2032 2033 #define DRIVER_NAME "hfi1" 2034 #define HFI1_USER_MINOR_BASE 0 2035 #define HFI1_TRACE_MINOR 127 2036 #define HFI1_NMINORS 255 2037 2038 #define PCI_VENDOR_ID_INTEL 0x8086 2039 #define PCI_DEVICE_ID_INTEL0 0x24f0 2040 #define PCI_DEVICE_ID_INTEL1 0x24f1 2041 2042 #define HFI1_PKT_USER_SC_INTEGRITY \ 2043 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ 2044 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \ 2045 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ 2046 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) 2047 2048 #define HFI1_PKT_KERNEL_SC_INTEGRITY \ 2049 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) 2050 2051 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, 2052 u16 ctxt_type) 2053 { 2054 u64 base_sc_integrity; 2055 2056 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ 2057 if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) 2058 return 0; 2059 2060 base_sc_integrity = 2061 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 2062 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 2063 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 2064 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 2065 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 2066 #ifndef CONFIG_FAULT_INJECTION 2067 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 2068 #endif 2069 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 2070 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 2071 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 2072 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 2073 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 2074 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 2075 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 2076 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 2077 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 2078 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; 2079 2080 if (ctxt_type == SC_USER) 2081 base_sc_integrity |= 2082 #ifndef CONFIG_FAULT_INJECTION 2083 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK | 2084 #endif 2085 HFI1_PKT_USER_SC_INTEGRITY; 2086 else 2087 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; 2088 2089 /* turn on send-side job key checks if !A0 */ 2090 if (!is_ax(dd)) 2091 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 2092 2093 return base_sc_integrity; 2094 } 2095 2096 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) 2097 { 2098 u64 base_sdma_integrity; 2099 2100 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ 2101 if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) 2102 return 0; 2103 2104 base_sdma_integrity = 2105 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 2106 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 2107 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 2108 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 2109 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 2110 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 2111 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 2112 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 2113 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 2114 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 2115 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 2116 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 2117 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 2118 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; 2119 2120 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) 2121 base_sdma_integrity |= 2122 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK; 2123 2124 /* turn on send-side job key checks if !A0 */ 2125 if (!is_ax(dd)) 2126 base_sdma_integrity |= 2127 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 2128 2129 return base_sdma_integrity; 2130 } 2131 2132 #define dd_dev_emerg(dd, fmt, ...) \ 2133 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ 2134 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 2135 2136 #define dd_dev_err(dd, fmt, ...) \ 2137 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 2138 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 2139 2140 #define dd_dev_err_ratelimited(dd, fmt, ...) \ 2141 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 2142 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \ 2143 ##__VA_ARGS__) 2144 2145 #define dd_dev_warn(dd, fmt, ...) \ 2146 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 2147 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 2148 2149 #define dd_dev_warn_ratelimited(dd, fmt, ...) \ 2150 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 2151 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \ 2152 ##__VA_ARGS__) 2153 2154 #define dd_dev_info(dd, fmt, ...) \ 2155 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ 2156 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 2157 2158 #define dd_dev_info_ratelimited(dd, fmt, ...) \ 2159 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 2160 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \ 2161 ##__VA_ARGS__) 2162 2163 #define dd_dev_dbg(dd, fmt, ...) \ 2164 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ 2165 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 2166 2167 #define hfi1_dev_porterr(dd, port, fmt, ...) \ 2168 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ 2169 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__) 2170 2171 /* 2172 * this is used for formatting hw error messages... 2173 */ 2174 struct hfi1_hwerror_msgs { 2175 u64 mask; 2176 const char *msg; 2177 size_t sz; 2178 }; 2179 2180 /* in intr.c... */ 2181 void hfi1_format_hwerrors(u64 hwerrs, 2182 const struct hfi1_hwerror_msgs *hwerrmsgs, 2183 size_t nhwerrmsgs, char *msg, size_t lmsg); 2184 2185 #define USER_OPCODE_CHECK_VAL 0xC0 2186 #define USER_OPCODE_CHECK_MASK 0xC0 2187 #define OPCODE_CHECK_VAL_DISABLED 0x0 2188 #define OPCODE_CHECK_MASK_DISABLED 0x0 2189 2190 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) 2191 { 2192 struct hfi1_pportdata *ppd; 2193 int i; 2194 2195 dd->z_int_counter = get_all_cpu_total(dd->int_counter); 2196 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); 2197 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); 2198 2199 ppd = (struct hfi1_pportdata *)(dd + 1); 2200 for (i = 0; i < dd->num_pports; i++, ppd++) { 2201 ppd->ibport_data.rvp.z_rc_acks = 2202 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); 2203 ppd->ibport_data.rvp.z_rc_qacks = 2204 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); 2205 } 2206 } 2207 2208 /* Control LED state */ 2209 static inline void setextled(struct hfi1_devdata *dd, u32 on) 2210 { 2211 if (on) 2212 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); 2213 else 2214 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); 2215 } 2216 2217 /* return the i2c resource given the target */ 2218 static inline u32 i2c_target(u32 target) 2219 { 2220 return target ? CR_I2C2 : CR_I2C1; 2221 } 2222 2223 /* return the i2c chain chip resource that this HFI uses for QSFP */ 2224 static inline u32 qsfp_resource(struct hfi1_devdata *dd) 2225 { 2226 return i2c_target(dd->hfi1_id); 2227 } 2228 2229 /* Is this device integrated or discrete? */ 2230 static inline bool is_integrated(struct hfi1_devdata *dd) 2231 { 2232 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1; 2233 } 2234 2235 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); 2236 2237 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev)) 2238 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev)) 2239 2240 static inline void hfi1_update_ah_attr(struct ib_device *ibdev, 2241 struct rdma_ah_attr *attr) 2242 { 2243 struct hfi1_pportdata *ppd; 2244 struct hfi1_ibport *ibp; 2245 u32 dlid = rdma_ah_get_dlid(attr); 2246 2247 /* 2248 * Kernel clients may not have setup GRH information 2249 * Set that here. 2250 */ 2251 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr)); 2252 ppd = ppd_from_ibp(ibp); 2253 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) || 2254 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) && 2255 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) && 2256 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) && 2257 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) || 2258 (rdma_ah_get_make_grd(attr))) { 2259 rdma_ah_set_ah_flags(attr, IB_AH_GRH); 2260 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid)); 2261 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix); 2262 } 2263 } 2264 2265 /* 2266 * hfi1_check_mcast- Check if the given lid is 2267 * in the OPA multicast range. 2268 * 2269 * The LID might either reside in ah.dlid or might be 2270 * in the GRH of the address handle as DGID if extended 2271 * addresses are in use. 2272 */ 2273 static inline bool hfi1_check_mcast(u32 lid) 2274 { 2275 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) && 2276 (lid != be32_to_cpu(OPA_LID_PERMISSIVE))); 2277 } 2278 2279 #define opa_get_lid(lid, format) \ 2280 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format) 2281 2282 /* Convert a lid to a specific lid space */ 2283 static inline u32 __opa_get_lid(u32 lid, u8 format) 2284 { 2285 bool is_mcast = hfi1_check_mcast(lid); 2286 2287 switch (format) { 2288 case OPA_PORT_PACKET_FORMAT_8B: 2289 case OPA_PORT_PACKET_FORMAT_10B: 2290 if (is_mcast) 2291 return (lid - opa_get_mcast_base(OPA_MCAST_NR) + 2292 0xF0000); 2293 return lid & 0xFFFFF; 2294 case OPA_PORT_PACKET_FORMAT_16B: 2295 if (is_mcast) 2296 return (lid - opa_get_mcast_base(OPA_MCAST_NR) + 2297 0xF00000); 2298 return lid & 0xFFFFFF; 2299 case OPA_PORT_PACKET_FORMAT_9B: 2300 if (is_mcast) 2301 return (lid - 2302 opa_get_mcast_base(OPA_MCAST_NR) + 2303 be16_to_cpu(IB_MULTICAST_LID_BASE)); 2304 else 2305 return lid & 0xFFFF; 2306 default: 2307 return lid; 2308 } 2309 } 2310 2311 /* Return true if the given lid is the OPA 16B multicast range */ 2312 static inline bool hfi1_is_16B_mcast(u32 lid) 2313 { 2314 return ((lid >= 2315 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) && 2316 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))); 2317 } 2318 2319 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr) 2320 { 2321 const struct ib_global_route *grh = rdma_ah_read_grh(attr); 2322 u32 dlid = rdma_ah_get_dlid(attr); 2323 2324 /* Modify ah_attr.dlid to be in the 32 bit LID space. 2325 * This is how the address will be laid out: 2326 * Assuming MCAST_NR to be 4, 2327 * 32 bit permissive LID = 0xFFFFFFFF 2328 * Multicast LID range = 0xFFFFFFFE to 0xF0000000 2329 * Unicast LID range = 0xEFFFFFFF to 1 2330 * Invalid LID = 0 2331 */ 2332 if (ib_is_opa_gid(&grh->dgid)) 2333 dlid = opa_get_lid_from_gid(&grh->dgid); 2334 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) && 2335 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) && 2336 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE))) 2337 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) + 2338 opa_get_mcast_base(OPA_MCAST_NR); 2339 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE)) 2340 dlid = be32_to_cpu(OPA_LID_PERMISSIVE); 2341 2342 rdma_ah_set_dlid(attr, dlid); 2343 } 2344 2345 static inline u8 hfi1_get_packet_type(u32 lid) 2346 { 2347 /* 9B if lid > 0xF0000000 */ 2348 if (lid >= opa_get_mcast_base(OPA_MCAST_NR)) 2349 return HFI1_PKT_TYPE_9B; 2350 2351 /* 16B if lid > 0xC000 */ 2352 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B)) 2353 return HFI1_PKT_TYPE_16B; 2354 2355 return HFI1_PKT_TYPE_9B; 2356 } 2357 2358 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr) 2359 { 2360 /* 2361 * If there was an incoming 16B packet with permissive 2362 * LIDs, OPA GIDs would have been programmed when those 2363 * packets were received. A 16B packet will have to 2364 * be sent in response to that packet. Return a 16B 2365 * header type if that's the case. 2366 */ 2367 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE)) 2368 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ? 2369 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B; 2370 2371 /* 2372 * Return a 16B header type if either the the destination 2373 * or source lid is extended. 2374 */ 2375 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B) 2376 return HFI1_PKT_TYPE_16B; 2377 2378 return hfi1_get_packet_type(lid); 2379 } 2380 2381 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet, 2382 struct ib_grh *grh, u32 slid, 2383 u32 dlid) 2384 { 2385 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data; 2386 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 2387 2388 if (!ibp) 2389 return; 2390 2391 grh->hop_limit = 1; 2392 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix; 2393 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)) 2394 grh->sgid.global.interface_id = 2395 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE)); 2396 else 2397 grh->sgid.global.interface_id = OPA_MAKE_ID(slid); 2398 2399 /* 2400 * Upper layers (like mad) may compare the dgid in the 2401 * wc that is obtained here with the sgid_index in 2402 * the wr. Since sgid_index in wr is always 0 for 2403 * extended lids, set the dgid here to the default 2404 * IB gid. 2405 */ 2406 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix; 2407 grh->dgid.global.interface_id = 2408 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]); 2409 } 2410 2411 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload) 2412 { 2413 return -(hdr_size + payload + (SIZE_OF_CRC << 2) + 2414 SIZE_OF_LT) & 0x7; 2415 } 2416 2417 static inline void hfi1_make_ib_hdr(struct ib_header *hdr, 2418 u16 lrh0, u16 len, 2419 u16 dlid, u16 slid) 2420 { 2421 hdr->lrh[0] = cpu_to_be16(lrh0); 2422 hdr->lrh[1] = cpu_to_be16(dlid); 2423 hdr->lrh[2] = cpu_to_be16(len); 2424 hdr->lrh[3] = cpu_to_be16(slid); 2425 } 2426 2427 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr, 2428 u32 slid, u32 dlid, 2429 u16 len, u16 pkey, 2430 bool becn, bool fecn, u8 l4, 2431 u8 sc) 2432 { 2433 u32 lrh0 = 0; 2434 u32 lrh1 = 0x40000000; 2435 u32 lrh2 = 0; 2436 u32 lrh3 = 0; 2437 2438 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT); 2439 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT); 2440 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK); 2441 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT); 2442 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT); 2443 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK); 2444 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) | 2445 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT); 2446 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) | 2447 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT); 2448 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT); 2449 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4; 2450 2451 hdr->lrh[0] = lrh0; 2452 hdr->lrh[1] = lrh1; 2453 hdr->lrh[2] = lrh2; 2454 hdr->lrh[3] = lrh3; 2455 } 2456 #endif /* _HFI1_KERNEL_H */ 2457