1 /*
2  * Copyright(c) 2015 - 2018 Intel Corporation.
3  *
4  * This file is provided under a dual BSD/GPLv2 license.  When using or
5  * redistributing this file, you may do so under either license.
6  *
7  * GPL LICENSE SUMMARY
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * BSD LICENSE
19  *
20  * Redistribution and use in source and binary forms, with or without
21  * modification, are permitted provided that the following conditions
22  * are met:
23  *
24  *  - Redistributions of source code must retain the above copyright
25  *    notice, this list of conditions and the following disclaimer.
26  *  - Redistributions in binary form must reproduce the above copyright
27  *    notice, this list of conditions and the following disclaimer in
28  *    the documentation and/or other materials provided with the
29  *    distribution.
30  *  - Neither the name of Intel Corporation nor the names of its
31  *    contributors may be used to endorse or promote products derived
32  *    from this software without specific prior written permission.
33  *
34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45  *
46  */
47 
48 #ifndef _COMMON_H
49 #define _COMMON_H
50 
51 #include <rdma/hfi/hfi1_user.h>
52 
53 /*
54  * This file contains defines, structures, etc. that are used
55  * to communicate between kernel and user code.
56  */
57 
58 /* version of protocol header (known to chip also). In the long run,
59  * we should be able to generate and accept a range of version numbers;
60  * for now we only accept one, and it's compiled in.
61  */
62 #define IPS_PROTO_VERSION 2
63 
64 /*
65  * These are compile time constants that you may want to enable or disable
66  * if you are trying to debug problems with code or performance.
67  * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
68  * fast path code
69  * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
70  * traced in fast path code
71  * _HFI1_TRACING define as 0 if you want to remove all tracing in a
72  * compilation unit
73  */
74 
75 /*
76  * If a packet's QP[23:16] bits match this value, then it is
77  * a PSM packet and the hardware will expect a KDETH header
78  * following the BTH.
79  */
80 #define DEFAULT_KDETH_QP 0x80
81 
82 /* driver/hw feature set bitmask */
83 #define HFI1_CAP_USER_SHIFT      24
84 #define HFI1_CAP_MASK            ((1UL << HFI1_CAP_USER_SHIFT) - 1)
85 /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
86 #define HFI1_CAP_LOCKED_SHIFT    63
87 #define HFI1_CAP_LOCKED_MASK     0x1ULL
88 #define HFI1_CAP_LOCKED_SMASK    (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
89 /* extra bits used between kernel and user processes */
90 #define HFI1_CAP_MISC_SHIFT      (HFI1_CAP_USER_SHIFT * 2)
91 #define HFI1_CAP_MISC_MASK       ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
92 					   HFI1_CAP_MISC_SHIFT)) - 1)
93 
94 #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
95 #define HFI1_CAP_KCLEAR(cap)						\
96 	({								\
97 		hfi1_cap_mask &= ~HFI1_CAP_##cap;			\
98 		hfi1_cap_mask;						\
99 	})
100 #define HFI1_CAP_USET(cap)						\
101 	({								\
102 		hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
103 		hfi1_cap_mask;						\
104 		})
105 #define HFI1_CAP_UCLEAR(cap)						\
106 	({								\
107 		hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
108 		hfi1_cap_mask;						\
109 	})
110 #define HFI1_CAP_SET(cap)						\
111 	({								\
112 		hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap <<	\
113 						  HFI1_CAP_USER_SHIFT)); \
114 		hfi1_cap_mask;						\
115 	})
116 #define HFI1_CAP_CLEAR(cap)						\
117 	({								\
118 		hfi1_cap_mask &= ~(HFI1_CAP_##cap |			\
119 				  (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
120 		hfi1_cap_mask;						\
121 	})
122 #define HFI1_CAP_LOCK()							\
123 	({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
124 #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
125 /*
126  * The set of capability bits that can be changed after initial load
127  * This set is the same for kernel and user contexts. However, for
128  * user contexts, the set can be further filtered by using the
129  * HFI1_CAP_RESERVED_MASK bits.
130  */
131 #define HFI1_CAP_WRITABLE_MASK   (HFI1_CAP_SDMA_AHG |			\
132 				  HFI1_CAP_HDRSUPP |			\
133 				  HFI1_CAP_MULTI_PKT_EGR |		\
134 				  HFI1_CAP_NODROP_RHQ_FULL |		\
135 				  HFI1_CAP_NODROP_EGR_FULL |		\
136 				  HFI1_CAP_ALLOW_PERM_JKEY |		\
137 				  HFI1_CAP_STATIC_RATE_CTRL |		\
138 				  HFI1_CAP_PRINT_UNIMPL |		\
139 				  HFI1_CAP_TID_UNMAP |			\
140 				  HFI1_CAP_OPFN)
141 /*
142  * A set of capability bits that are "global" and are not allowed to be
143  * set in the user bitmask.
144  */
145 #define HFI1_CAP_RESERVED_MASK   ((HFI1_CAP_SDMA |			\
146 				   HFI1_CAP_USE_SDMA_HEAD |		\
147 				   HFI1_CAP_EXTENDED_PSN |		\
148 				   HFI1_CAP_PRINT_UNIMPL |		\
149 				   HFI1_CAP_NO_INTEGRITY |		\
150 				   HFI1_CAP_PKEY_CHECK |		\
151 				   HFI1_CAP_TID_RDMA |			\
152 				   HFI1_CAP_OPFN) <<			\
153 				  HFI1_CAP_USER_SHIFT)
154 /*
155  * Set of capabilities that need to be enabled for kernel context in
156  * order to be allowed for user contexts, as well.
157  */
158 #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
159 /* Default enabled capabilities (both kernel and user) */
160 #define HFI1_CAP_MASK_DEFAULT    (HFI1_CAP_HDRSUPP |			\
161 				 HFI1_CAP_NODROP_RHQ_FULL |		\
162 				 HFI1_CAP_NODROP_EGR_FULL |		\
163 				 HFI1_CAP_SDMA |			\
164 				 HFI1_CAP_PRINT_UNIMPL |		\
165 				 HFI1_CAP_STATIC_RATE_CTRL |		\
166 				 HFI1_CAP_PKEY_CHECK |			\
167 				 HFI1_CAP_MULTI_PKT_EGR |		\
168 				 HFI1_CAP_EXTENDED_PSN |		\
169 				 ((HFI1_CAP_HDRSUPP |			\
170 				   HFI1_CAP_MULTI_PKT_EGR |		\
171 				   HFI1_CAP_STATIC_RATE_CTRL |		\
172 				   HFI1_CAP_PKEY_CHECK |		\
173 				   HFI1_CAP_EARLY_CREDIT_RETURN) <<	\
174 				  HFI1_CAP_USER_SHIFT))
175 /*
176  * A bitmask of kernel/global capabilities that should be communicated
177  * to user level processes.
178  */
179 #define HFI1_CAP_K2U (HFI1_CAP_SDMA |			\
180 		     HFI1_CAP_EXTENDED_PSN |		\
181 		     HFI1_CAP_PKEY_CHECK |		\
182 		     HFI1_CAP_NO_INTEGRITY)
183 
184 #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
185 			     HFI1_USER_SWMINOR)
186 
187 #ifndef HFI1_KERN_TYPE
188 #define HFI1_KERN_TYPE 0
189 #endif
190 
191 /*
192  * Similarly, this is the kernel version going back to the user.  It's
193  * slightly different, in that we want to tell if the driver was built as
194  * part of a Intel release, or from the driver from openfabrics.org,
195  * kernel.org, or a standard distribution, for support reasons.
196  * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
197  *
198  * It's returned by the driver to the user code during initialization in the
199  * spi_sw_version field of hfi1_base_info, so the user code can in turn
200  * check for compatibility with the kernel.
201 */
202 #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
203 
204 /*
205  * Define the driver version number.  This is something that refers only
206  * to the driver itself, not the software interfaces it supports.
207  */
208 #ifndef HFI1_DRIVER_VERSION_BASE
209 #define HFI1_DRIVER_VERSION_BASE "0.9-294"
210 #endif
211 
212 /* create the final driver version string */
213 #ifdef HFI1_IDSTR
214 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
215 #else
216 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
217 #endif
218 
219 /*
220  * Diagnostics can send a packet by writing the following
221  * struct to the diag packet special file.
222  *
223  * This allows a custom PBC qword, so that special modes and deliberate
224  * changes to CRCs can be used.
225  */
226 #define _DIAG_PKT_VERS 1
227 struct diag_pkt {
228 	__u16 version;		/* structure version */
229 	__u16 unit;		/* which device */
230 	__u16 sw_index;		/* send sw index to use */
231 	__u16 len;		/* data length, in bytes */
232 	__u16 port;		/* port number */
233 	__u16 unused;
234 	__u32 flags;		/* call flags */
235 	__u64 data;		/* user data pointer */
236 	__u64 pbc;		/* PBC for the packet */
237 };
238 
239 /* diag_pkt flags */
240 #define F_DIAGPKT_WAIT 0x1	/* wait until packet is sent */
241 
242 /*
243  * The next set of defines are for packet headers, and chip register
244  * and memory bits that are visible to and/or used by user-mode software.
245  */
246 
247 /*
248  * Receive Header Flags
249  */
250 #define RHF_PKT_LEN_SHIFT	0
251 #define RHF_PKT_LEN_MASK	0xfffull
252 #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
253 
254 #define RHF_RCV_TYPE_SHIFT	12
255 #define RHF_RCV_TYPE_MASK	0x7ull
256 #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
257 
258 #define RHF_USE_EGR_BFR_SHIFT	15
259 #define RHF_USE_EGR_BFR_MASK	0x1ull
260 #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
261 
262 #define RHF_EGR_INDEX_SHIFT	16
263 #define RHF_EGR_INDEX_MASK	0x7ffull
264 #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
265 
266 #define RHF_DC_INFO_SHIFT	27
267 #define RHF_DC_INFO_MASK	0x1ull
268 #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
269 
270 #define RHF_RCV_SEQ_SHIFT	28
271 #define RHF_RCV_SEQ_MASK	0xfull
272 #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
273 
274 #define RHF_EGR_OFFSET_SHIFT	32
275 #define RHF_EGR_OFFSET_MASK	0xfffull
276 #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
277 #define RHF_HDRQ_OFFSET_SHIFT	44
278 #define RHF_HDRQ_OFFSET_MASK	0x1ffull
279 #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
280 #define RHF_K_HDR_LEN_ERR	(0x1ull << 53)
281 #define RHF_DC_UNC_ERR		(0x1ull << 54)
282 #define RHF_DC_ERR		(0x1ull << 55)
283 #define RHF_RCV_TYPE_ERR_SHIFT	56
284 #define RHF_RCV_TYPE_ERR_MASK	0x7ul
285 #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
286 #define RHF_TID_ERR		(0x1ull << 59)
287 #define RHF_LEN_ERR		(0x1ull << 60)
288 #define RHF_ECC_ERR		(0x1ull << 61)
289 #define RHF_RESERVED		(0x1ull << 62)
290 #define RHF_ICRC_ERR		(0x1ull << 63)
291 
292 #define RHF_ERROR_SMASK 0xffe0000000000000ull		/* bits 63:53 */
293 
294 /* RHF receive types */
295 #define RHF_RCV_TYPE_EXPECTED 0
296 #define RHF_RCV_TYPE_EAGER    1
297 #define RHF_RCV_TYPE_IB       2 /* normal IB, IB Raw, or IPv6 */
298 #define RHF_RCV_TYPE_ERROR    3
299 #define RHF_RCV_TYPE_BYPASS   4
300 #define RHF_RCV_TYPE_INVALID5 5
301 #define RHF_RCV_TYPE_INVALID6 6
302 #define RHF_RCV_TYPE_INVALID7 7
303 
304 /* RHF receive type error - expected packet errors */
305 #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR	0x2
306 #define RHF_RTE_EXPECTED_FLOW_GEN_ERR	0x4
307 
308 /* RHF receive type error - eager packet errors */
309 #define RHF_RTE_EAGER_NO_ERR		0x0
310 
311 /* RHF receive type error - IB packet errors */
312 #define RHF_RTE_IB_NO_ERR		0x0
313 
314 /* RHF receive type error - error packet errors */
315 #define RHF_RTE_ERROR_NO_ERR		0x0
316 #define RHF_RTE_ERROR_OP_CODE_ERR	0x1
317 #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR	0x2
318 #define RHF_RTE_ERROR_KHDR_HCRC_ERR	0x3
319 #define RHF_RTE_ERROR_KHDR_KVER_ERR	0x4
320 #define RHF_RTE_ERROR_CONTEXT_ERR	0x5
321 #define RHF_RTE_ERROR_KHDR_TID_ERR	0x6
322 
323 /* RHF receive type error - bypass packet errors */
324 #define RHF_RTE_BYPASS_NO_ERR		0x0
325 
326 /* IB - LRH header constants */
327 #define HFI1_LRH_GRH 0x0003      /* 1. word of IB LRH - next header: GRH */
328 #define HFI1_LRH_BTH 0x0002      /* 1. word of IB LRH - next header: BTH */
329 
330 /* misc. */
331 #define SC15_PACKET 0xF
332 #define SIZE_OF_CRC 1
333 #define SIZE_OF_LT 1
334 #define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
335 
336 #define LIM_MGMT_P_KEY       0x7FFF
337 #define FULL_MGMT_P_KEY      0xFFFF
338 
339 #define DEFAULT_P_KEY LIM_MGMT_P_KEY
340 
341 #define HFI1_PSM_IOC_BASE_SEQ 0x0
342 
343 /* Number of BTH.PSN bits used for sequence number in expected rcvs */
344 #define HFI1_KDETH_BTH_SEQ_SHIFT 11
345 #define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
346 
347 static inline __u64 rhf_to_cpu(const __le32 *rbuf)
348 {
349 	return __le64_to_cpu(*((__le64 *)rbuf));
350 }
351 
352 static inline u64 rhf_err_flags(u64 rhf)
353 {
354 	return rhf & RHF_ERROR_SMASK;
355 }
356 
357 static inline u32 rhf_rcv_type(u64 rhf)
358 {
359 	return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
360 }
361 
362 static inline u32 rhf_rcv_type_err(u64 rhf)
363 {
364 	return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
365 }
366 
367 /* return size is in bytes, not DWORDs */
368 static inline u32 rhf_pkt_len(u64 rhf)
369 {
370 	return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
371 }
372 
373 static inline u32 rhf_egr_index(u64 rhf)
374 {
375 	return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
376 }
377 
378 static inline u32 rhf_rcv_seq(u64 rhf)
379 {
380 	return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
381 }
382 
383 /* returned offset is in DWORDS */
384 static inline u32 rhf_hdrq_offset(u64 rhf)
385 {
386 	return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
387 }
388 
389 static inline u64 rhf_use_egr_bfr(u64 rhf)
390 {
391 	return rhf & RHF_USE_EGR_BFR_SMASK;
392 }
393 
394 static inline u64 rhf_dc_info(u64 rhf)
395 {
396 	return rhf & RHF_DC_INFO_SMASK;
397 }
398 
399 static inline u32 rhf_egr_buf_offset(u64 rhf)
400 {
401 	return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
402 }
403 #endif /* _COMMON_H */
404