1f48ad614SDennis Dalessandro /* 2d2e9ace4SKaike Wan * Copyright(c) 2015 - 2018 Intel Corporation. 3f48ad614SDennis Dalessandro * 4f48ad614SDennis Dalessandro * This file is provided under a dual BSD/GPLv2 license. When using or 5f48ad614SDennis Dalessandro * redistributing this file, you may do so under either license. 6f48ad614SDennis Dalessandro * 7f48ad614SDennis Dalessandro * GPL LICENSE SUMMARY 8f48ad614SDennis Dalessandro * 9f48ad614SDennis Dalessandro * This program is free software; you can redistribute it and/or modify 10f48ad614SDennis Dalessandro * it under the terms of version 2 of the GNU General Public License as 11f48ad614SDennis Dalessandro * published by the Free Software Foundation. 12f48ad614SDennis Dalessandro * 13f48ad614SDennis Dalessandro * This program is distributed in the hope that it will be useful, but 14f48ad614SDennis Dalessandro * WITHOUT ANY WARRANTY; without even the implied warranty of 15f48ad614SDennis Dalessandro * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16f48ad614SDennis Dalessandro * General Public License for more details. 17f48ad614SDennis Dalessandro * 18f48ad614SDennis Dalessandro * BSD LICENSE 19f48ad614SDennis Dalessandro * 20f48ad614SDennis Dalessandro * Redistribution and use in source and binary forms, with or without 21f48ad614SDennis Dalessandro * modification, are permitted provided that the following conditions 22f48ad614SDennis Dalessandro * are met: 23f48ad614SDennis Dalessandro * 24f48ad614SDennis Dalessandro * - Redistributions of source code must retain the above copyright 25f48ad614SDennis Dalessandro * notice, this list of conditions and the following disclaimer. 26f48ad614SDennis Dalessandro * - Redistributions in binary form must reproduce the above copyright 27f48ad614SDennis Dalessandro * notice, this list of conditions and the following disclaimer in 28f48ad614SDennis Dalessandro * the documentation and/or other materials provided with the 29f48ad614SDennis Dalessandro * distribution. 30f48ad614SDennis Dalessandro * - Neither the name of Intel Corporation nor the names of its 31f48ad614SDennis Dalessandro * contributors may be used to endorse or promote products derived 32f48ad614SDennis Dalessandro * from this software without specific prior written permission. 33f48ad614SDennis Dalessandro * 34f48ad614SDennis Dalessandro * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35f48ad614SDennis Dalessandro * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36f48ad614SDennis Dalessandro * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37f48ad614SDennis Dalessandro * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38f48ad614SDennis Dalessandro * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39f48ad614SDennis Dalessandro * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40f48ad614SDennis Dalessandro * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41f48ad614SDennis Dalessandro * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42f48ad614SDennis Dalessandro * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43f48ad614SDennis Dalessandro * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44f48ad614SDennis Dalessandro * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45f48ad614SDennis Dalessandro * 46f48ad614SDennis Dalessandro */ 47f48ad614SDennis Dalessandro 48f48ad614SDennis Dalessandro #ifndef _COMMON_H 49f48ad614SDennis Dalessandro #define _COMMON_H 50f48ad614SDennis Dalessandro 51f48ad614SDennis Dalessandro #include <rdma/hfi/hfi1_user.h> 52f48ad614SDennis Dalessandro 53f48ad614SDennis Dalessandro /* 54f48ad614SDennis Dalessandro * This file contains defines, structures, etc. that are used 55f48ad614SDennis Dalessandro * to communicate between kernel and user code. 56f48ad614SDennis Dalessandro */ 57f48ad614SDennis Dalessandro 58f48ad614SDennis Dalessandro /* version of protocol header (known to chip also). In the long run, 59f48ad614SDennis Dalessandro * we should be able to generate and accept a range of version numbers; 60f48ad614SDennis Dalessandro * for now we only accept one, and it's compiled in. 61f48ad614SDennis Dalessandro */ 62f48ad614SDennis Dalessandro #define IPS_PROTO_VERSION 2 63f48ad614SDennis Dalessandro 64f48ad614SDennis Dalessandro /* 65f48ad614SDennis Dalessandro * These are compile time constants that you may want to enable or disable 66f48ad614SDennis Dalessandro * if you are trying to debug problems with code or performance. 67f48ad614SDennis Dalessandro * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in 68f48ad614SDennis Dalessandro * fast path code 69f48ad614SDennis Dalessandro * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be 70f48ad614SDennis Dalessandro * traced in fast path code 71f48ad614SDennis Dalessandro * _HFI1_TRACING define as 0 if you want to remove all tracing in a 72f48ad614SDennis Dalessandro * compilation unit 73f48ad614SDennis Dalessandro */ 74f48ad614SDennis Dalessandro 75f48ad614SDennis Dalessandro /* 76f48ad614SDennis Dalessandro * If a packet's QP[23:16] bits match this value, then it is 77f48ad614SDennis Dalessandro * a PSM packet and the hardware will expect a KDETH header 78f48ad614SDennis Dalessandro * following the BTH. 79f48ad614SDennis Dalessandro */ 80f48ad614SDennis Dalessandro #define DEFAULT_KDETH_QP 0x80 81f48ad614SDennis Dalessandro 82f48ad614SDennis Dalessandro /* driver/hw feature set bitmask */ 83f48ad614SDennis Dalessandro #define HFI1_CAP_USER_SHIFT 24 84f48ad614SDennis Dalessandro #define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1) 85f48ad614SDennis Dalessandro /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */ 86f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED_SHIFT 63 87f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED_MASK 0x1ULL 88f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT) 89f48ad614SDennis Dalessandro /* extra bits used between kernel and user processes */ 90f48ad614SDennis Dalessandro #define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2) 91f48ad614SDennis Dalessandro #define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \ 92f48ad614SDennis Dalessandro HFI1_CAP_MISC_SHIFT)) - 1) 93f48ad614SDennis Dalessandro 94f48ad614SDennis Dalessandro #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; }) 95f48ad614SDennis Dalessandro #define HFI1_CAP_KCLEAR(cap) \ 96f48ad614SDennis Dalessandro ({ \ 97f48ad614SDennis Dalessandro hfi1_cap_mask &= ~HFI1_CAP_##cap; \ 98f48ad614SDennis Dalessandro hfi1_cap_mask; \ 99f48ad614SDennis Dalessandro }) 100f48ad614SDennis Dalessandro #define HFI1_CAP_USET(cap) \ 101f48ad614SDennis Dalessandro ({ \ 102f48ad614SDennis Dalessandro hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \ 103f48ad614SDennis Dalessandro hfi1_cap_mask; \ 104f48ad614SDennis Dalessandro }) 105f48ad614SDennis Dalessandro #define HFI1_CAP_UCLEAR(cap) \ 106f48ad614SDennis Dalessandro ({ \ 107f48ad614SDennis Dalessandro hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \ 108f48ad614SDennis Dalessandro hfi1_cap_mask; \ 109f48ad614SDennis Dalessandro }) 110f48ad614SDennis Dalessandro #define HFI1_CAP_SET(cap) \ 111f48ad614SDennis Dalessandro ({ \ 112f48ad614SDennis Dalessandro hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \ 113f48ad614SDennis Dalessandro HFI1_CAP_USER_SHIFT)); \ 114f48ad614SDennis Dalessandro hfi1_cap_mask; \ 115f48ad614SDennis Dalessandro }) 116f48ad614SDennis Dalessandro #define HFI1_CAP_CLEAR(cap) \ 117f48ad614SDennis Dalessandro ({ \ 118f48ad614SDennis Dalessandro hfi1_cap_mask &= ~(HFI1_CAP_##cap | \ 119f48ad614SDennis Dalessandro (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \ 120f48ad614SDennis Dalessandro hfi1_cap_mask; \ 121f48ad614SDennis Dalessandro }) 122f48ad614SDennis Dalessandro #define HFI1_CAP_LOCK() \ 123f48ad614SDennis Dalessandro ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; }) 124f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK)) 125f48ad614SDennis Dalessandro /* 126f48ad614SDennis Dalessandro * The set of capability bits that can be changed after initial load 127f48ad614SDennis Dalessandro * This set is the same for kernel and user contexts. However, for 128f48ad614SDennis Dalessandro * user contexts, the set can be further filtered by using the 129f48ad614SDennis Dalessandro * HFI1_CAP_RESERVED_MASK bits. 130f48ad614SDennis Dalessandro */ 131f48ad614SDennis Dalessandro #define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \ 132f48ad614SDennis Dalessandro HFI1_CAP_HDRSUPP | \ 133f48ad614SDennis Dalessandro HFI1_CAP_MULTI_PKT_EGR | \ 134f48ad614SDennis Dalessandro HFI1_CAP_NODROP_RHQ_FULL | \ 135f48ad614SDennis Dalessandro HFI1_CAP_NODROP_EGR_FULL | \ 136f48ad614SDennis Dalessandro HFI1_CAP_ALLOW_PERM_JKEY | \ 137f48ad614SDennis Dalessandro HFI1_CAP_STATIC_RATE_CTRL | \ 138f48ad614SDennis Dalessandro HFI1_CAP_PRINT_UNIMPL | \ 139d2e9ace4SKaike Wan HFI1_CAP_TID_UNMAP | \ 140d2e9ace4SKaike Wan HFI1_CAP_OPFN) 141f48ad614SDennis Dalessandro /* 142f48ad614SDennis Dalessandro * A set of capability bits that are "global" and are not allowed to be 143f48ad614SDennis Dalessandro * set in the user bitmask. 144f48ad614SDennis Dalessandro */ 145f48ad614SDennis Dalessandro #define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \ 146f48ad614SDennis Dalessandro HFI1_CAP_USE_SDMA_HEAD | \ 147f48ad614SDennis Dalessandro HFI1_CAP_EXTENDED_PSN | \ 148f48ad614SDennis Dalessandro HFI1_CAP_PRINT_UNIMPL | \ 149f48ad614SDennis Dalessandro HFI1_CAP_NO_INTEGRITY | \ 150d2e9ace4SKaike Wan HFI1_CAP_PKEY_CHECK | \ 151d2e9ace4SKaike Wan HFI1_CAP_TID_RDMA | \ 152d2e9ace4SKaike Wan HFI1_CAP_OPFN) << \ 153f48ad614SDennis Dalessandro HFI1_CAP_USER_SHIFT) 154f48ad614SDennis Dalessandro /* 155f48ad614SDennis Dalessandro * Set of capabilities that need to be enabled for kernel context in 156f48ad614SDennis Dalessandro * order to be allowed for user contexts, as well. 157f48ad614SDennis Dalessandro */ 158f48ad614SDennis Dalessandro #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL) 159f48ad614SDennis Dalessandro /* Default enabled capabilities (both kernel and user) */ 160f48ad614SDennis Dalessandro #define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \ 161f48ad614SDennis Dalessandro HFI1_CAP_NODROP_RHQ_FULL | \ 162f48ad614SDennis Dalessandro HFI1_CAP_NODROP_EGR_FULL | \ 163f48ad614SDennis Dalessandro HFI1_CAP_SDMA | \ 164f48ad614SDennis Dalessandro HFI1_CAP_PRINT_UNIMPL | \ 165f48ad614SDennis Dalessandro HFI1_CAP_STATIC_RATE_CTRL | \ 166f48ad614SDennis Dalessandro HFI1_CAP_PKEY_CHECK | \ 167f48ad614SDennis Dalessandro HFI1_CAP_MULTI_PKT_EGR | \ 168f48ad614SDennis Dalessandro HFI1_CAP_EXTENDED_PSN | \ 169f48ad614SDennis Dalessandro ((HFI1_CAP_HDRSUPP | \ 170f48ad614SDennis Dalessandro HFI1_CAP_MULTI_PKT_EGR | \ 171f48ad614SDennis Dalessandro HFI1_CAP_STATIC_RATE_CTRL | \ 172f48ad614SDennis Dalessandro HFI1_CAP_PKEY_CHECK | \ 173f48ad614SDennis Dalessandro HFI1_CAP_EARLY_CREDIT_RETURN) << \ 174f48ad614SDennis Dalessandro HFI1_CAP_USER_SHIFT)) 175f48ad614SDennis Dalessandro /* 176f48ad614SDennis Dalessandro * A bitmask of kernel/global capabilities that should be communicated 177f48ad614SDennis Dalessandro * to user level processes. 178f48ad614SDennis Dalessandro */ 179f48ad614SDennis Dalessandro #define HFI1_CAP_K2U (HFI1_CAP_SDMA | \ 180f48ad614SDennis Dalessandro HFI1_CAP_EXTENDED_PSN | \ 181f48ad614SDennis Dalessandro HFI1_CAP_PKEY_CHECK | \ 182f48ad614SDennis Dalessandro HFI1_CAP_NO_INTEGRITY) 183f48ad614SDennis Dalessandro 184f48ad614SDennis Dalessandro #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \ 185f48ad614SDennis Dalessandro HFI1_USER_SWMINOR) 186f48ad614SDennis Dalessandro 187f48ad614SDennis Dalessandro #ifndef HFI1_KERN_TYPE 188f48ad614SDennis Dalessandro #define HFI1_KERN_TYPE 0 189f48ad614SDennis Dalessandro #endif 190f48ad614SDennis Dalessandro 191f48ad614SDennis Dalessandro /* 192f48ad614SDennis Dalessandro * Similarly, this is the kernel version going back to the user. It's 193f48ad614SDennis Dalessandro * slightly different, in that we want to tell if the driver was built as 194f48ad614SDennis Dalessandro * part of a Intel release, or from the driver from openfabrics.org, 195f48ad614SDennis Dalessandro * kernel.org, or a standard distribution, for support reasons. 196f48ad614SDennis Dalessandro * The high bit is 0 for non-Intel and 1 for Intel-built/supplied. 197f48ad614SDennis Dalessandro * 198f48ad614SDennis Dalessandro * It's returned by the driver to the user code during initialization in the 199f48ad614SDennis Dalessandro * spi_sw_version field of hfi1_base_info, so the user code can in turn 200f48ad614SDennis Dalessandro * check for compatibility with the kernel. 201f48ad614SDennis Dalessandro */ 202f48ad614SDennis Dalessandro #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION) 203f48ad614SDennis Dalessandro 204f48ad614SDennis Dalessandro /* 205f48ad614SDennis Dalessandro * Define the driver version number. This is something that refers only 206f48ad614SDennis Dalessandro * to the driver itself, not the software interfaces it supports. 207f48ad614SDennis Dalessandro */ 208f48ad614SDennis Dalessandro #ifndef HFI1_DRIVER_VERSION_BASE 209f48ad614SDennis Dalessandro #define HFI1_DRIVER_VERSION_BASE "0.9-294" 210f48ad614SDennis Dalessandro #endif 211f48ad614SDennis Dalessandro 212f48ad614SDennis Dalessandro /* create the final driver version string */ 213f48ad614SDennis Dalessandro #ifdef HFI1_IDSTR 214f48ad614SDennis Dalessandro #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR 215f48ad614SDennis Dalessandro #else 216f48ad614SDennis Dalessandro #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE 217f48ad614SDennis Dalessandro #endif 218f48ad614SDennis Dalessandro 219f48ad614SDennis Dalessandro /* 220f48ad614SDennis Dalessandro * Diagnostics can send a packet by writing the following 221f48ad614SDennis Dalessandro * struct to the diag packet special file. 222f48ad614SDennis Dalessandro * 223f48ad614SDennis Dalessandro * This allows a custom PBC qword, so that special modes and deliberate 224f48ad614SDennis Dalessandro * changes to CRCs can be used. 225f48ad614SDennis Dalessandro */ 226f48ad614SDennis Dalessandro #define _DIAG_PKT_VERS 1 227f48ad614SDennis Dalessandro struct diag_pkt { 228f48ad614SDennis Dalessandro __u16 version; /* structure version */ 229f48ad614SDennis Dalessandro __u16 unit; /* which device */ 230f48ad614SDennis Dalessandro __u16 sw_index; /* send sw index to use */ 231f48ad614SDennis Dalessandro __u16 len; /* data length, in bytes */ 232f48ad614SDennis Dalessandro __u16 port; /* port number */ 233f48ad614SDennis Dalessandro __u16 unused; 234f48ad614SDennis Dalessandro __u32 flags; /* call flags */ 235f48ad614SDennis Dalessandro __u64 data; /* user data pointer */ 236f48ad614SDennis Dalessandro __u64 pbc; /* PBC for the packet */ 237f48ad614SDennis Dalessandro }; 238f48ad614SDennis Dalessandro 239f48ad614SDennis Dalessandro /* diag_pkt flags */ 240f48ad614SDennis Dalessandro #define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */ 241f48ad614SDennis Dalessandro 242f48ad614SDennis Dalessandro /* 243f48ad614SDennis Dalessandro * The next set of defines are for packet headers, and chip register 244f48ad614SDennis Dalessandro * and memory bits that are visible to and/or used by user-mode software. 245f48ad614SDennis Dalessandro */ 246f48ad614SDennis Dalessandro 247f48ad614SDennis Dalessandro /* 248f48ad614SDennis Dalessandro * Receive Header Flags 249f48ad614SDennis Dalessandro */ 250f48ad614SDennis Dalessandro #define RHF_PKT_LEN_SHIFT 0 251f48ad614SDennis Dalessandro #define RHF_PKT_LEN_MASK 0xfffull 252f48ad614SDennis Dalessandro #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT) 253f48ad614SDennis Dalessandro 254f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_SHIFT 12 255f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_MASK 0x7ull 256f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT) 257f48ad614SDennis Dalessandro 258f48ad614SDennis Dalessandro #define RHF_USE_EGR_BFR_SHIFT 15 259f48ad614SDennis Dalessandro #define RHF_USE_EGR_BFR_MASK 0x1ull 260f48ad614SDennis Dalessandro #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT) 261f48ad614SDennis Dalessandro 262f48ad614SDennis Dalessandro #define RHF_EGR_INDEX_SHIFT 16 263f48ad614SDennis Dalessandro #define RHF_EGR_INDEX_MASK 0x7ffull 264f48ad614SDennis Dalessandro #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT) 265f48ad614SDennis Dalessandro 266f48ad614SDennis Dalessandro #define RHF_DC_INFO_SHIFT 27 267f48ad614SDennis Dalessandro #define RHF_DC_INFO_MASK 0x1ull 268f48ad614SDennis Dalessandro #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT) 269f48ad614SDennis Dalessandro 270f48ad614SDennis Dalessandro #define RHF_RCV_SEQ_SHIFT 28 271f48ad614SDennis Dalessandro #define RHF_RCV_SEQ_MASK 0xfull 272f48ad614SDennis Dalessandro #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT) 273f48ad614SDennis Dalessandro 274f48ad614SDennis Dalessandro #define RHF_EGR_OFFSET_SHIFT 32 275f48ad614SDennis Dalessandro #define RHF_EGR_OFFSET_MASK 0xfffull 276f48ad614SDennis Dalessandro #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT) 277f48ad614SDennis Dalessandro #define RHF_HDRQ_OFFSET_SHIFT 44 278f48ad614SDennis Dalessandro #define RHF_HDRQ_OFFSET_MASK 0x1ffull 279f48ad614SDennis Dalessandro #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT) 280f48ad614SDennis Dalessandro #define RHF_K_HDR_LEN_ERR (0x1ull << 53) 281f48ad614SDennis Dalessandro #define RHF_DC_UNC_ERR (0x1ull << 54) 282f48ad614SDennis Dalessandro #define RHF_DC_ERR (0x1ull << 55) 283f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERR_SHIFT 56 284f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERR_MASK 0x7ul 285f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT) 286f48ad614SDennis Dalessandro #define RHF_TID_ERR (0x1ull << 59) 287f48ad614SDennis Dalessandro #define RHF_LEN_ERR (0x1ull << 60) 288f48ad614SDennis Dalessandro #define RHF_ECC_ERR (0x1ull << 61) 289f48ad614SDennis Dalessandro #define RHF_VCRC_ERR (0x1ull << 62) 290f48ad614SDennis Dalessandro #define RHF_ICRC_ERR (0x1ull << 63) 291f48ad614SDennis Dalessandro 292f48ad614SDennis Dalessandro #define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */ 293f48ad614SDennis Dalessandro 294f48ad614SDennis Dalessandro /* RHF receive types */ 295f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_EXPECTED 0 296f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_EAGER 1 297f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */ 298f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERROR 3 299f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_BYPASS 4 300f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_INVALID5 5 301f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_INVALID6 6 302f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_INVALID7 7 303f48ad614SDennis Dalessandro 304f48ad614SDennis Dalessandro /* RHF receive type error - expected packet errors */ 305f48ad614SDennis Dalessandro #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2 306f48ad614SDennis Dalessandro #define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4 307f48ad614SDennis Dalessandro 308f48ad614SDennis Dalessandro /* RHF receive type error - eager packet errors */ 309f48ad614SDennis Dalessandro #define RHF_RTE_EAGER_NO_ERR 0x0 310f48ad614SDennis Dalessandro 311f48ad614SDennis Dalessandro /* RHF receive type error - IB packet errors */ 312f48ad614SDennis Dalessandro #define RHF_RTE_IB_NO_ERR 0x0 313f48ad614SDennis Dalessandro 314f48ad614SDennis Dalessandro /* RHF receive type error - error packet errors */ 315f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_NO_ERR 0x0 316f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_OP_CODE_ERR 0x1 317f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2 318f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3 319f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4 320f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_CONTEXT_ERR 0x5 321f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_TID_ERR 0x6 322f48ad614SDennis Dalessandro 323f48ad614SDennis Dalessandro /* RHF receive type error - bypass packet errors */ 324f48ad614SDennis Dalessandro #define RHF_RTE_BYPASS_NO_ERR 0x0 325f48ad614SDennis Dalessandro 326f48ad614SDennis Dalessandro /* IB - LRH header constants */ 327f48ad614SDennis Dalessandro #define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */ 328f48ad614SDennis Dalessandro #define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */ 329f48ad614SDennis Dalessandro 330f48ad614SDennis Dalessandro /* misc. */ 3319039746cSDon Hiatt #define SC15_PACKET 0xF 332f48ad614SDennis Dalessandro #define SIZE_OF_CRC 1 33372c07e2bSDon Hiatt #define SIZE_OF_LT 1 334f8195f3bSDon Hiatt #define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */ 335f48ad614SDennis Dalessandro 336f48ad614SDennis Dalessandro #define LIM_MGMT_P_KEY 0x7FFF 337f48ad614SDennis Dalessandro #define FULL_MGMT_P_KEY 0xFFFF 338f48ad614SDennis Dalessandro 339f48ad614SDennis Dalessandro #define DEFAULT_P_KEY LIM_MGMT_P_KEY 340f48ad614SDennis Dalessandro 341f48ad614SDennis Dalessandro #define HFI1_PSM_IOC_BASE_SEQ 0x0 342f48ad614SDennis Dalessandro 343f48ad614SDennis Dalessandro static inline __u64 rhf_to_cpu(const __le32 *rbuf) 344f48ad614SDennis Dalessandro { 345f48ad614SDennis Dalessandro return __le64_to_cpu(*((__le64 *)rbuf)); 346f48ad614SDennis Dalessandro } 347f48ad614SDennis Dalessandro 348f48ad614SDennis Dalessandro static inline u64 rhf_err_flags(u64 rhf) 349f48ad614SDennis Dalessandro { 350f48ad614SDennis Dalessandro return rhf & RHF_ERROR_SMASK; 351f48ad614SDennis Dalessandro } 352f48ad614SDennis Dalessandro 353f48ad614SDennis Dalessandro static inline u32 rhf_rcv_type(u64 rhf) 354f48ad614SDennis Dalessandro { 355f48ad614SDennis Dalessandro return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK; 356f48ad614SDennis Dalessandro } 357f48ad614SDennis Dalessandro 358f48ad614SDennis Dalessandro static inline u32 rhf_rcv_type_err(u64 rhf) 359f48ad614SDennis Dalessandro { 360f48ad614SDennis Dalessandro return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK; 361f48ad614SDennis Dalessandro } 362f48ad614SDennis Dalessandro 363f48ad614SDennis Dalessandro /* return size is in bytes, not DWORDs */ 364f48ad614SDennis Dalessandro static inline u32 rhf_pkt_len(u64 rhf) 365f48ad614SDennis Dalessandro { 366f48ad614SDennis Dalessandro return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2; 367f48ad614SDennis Dalessandro } 368f48ad614SDennis Dalessandro 369f48ad614SDennis Dalessandro static inline u32 rhf_egr_index(u64 rhf) 370f48ad614SDennis Dalessandro { 371f48ad614SDennis Dalessandro return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK; 372f48ad614SDennis Dalessandro } 373f48ad614SDennis Dalessandro 374f48ad614SDennis Dalessandro static inline u32 rhf_rcv_seq(u64 rhf) 375f48ad614SDennis Dalessandro { 376f48ad614SDennis Dalessandro return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK; 377f48ad614SDennis Dalessandro } 378f48ad614SDennis Dalessandro 379f48ad614SDennis Dalessandro /* returned offset is in DWORDS */ 380f48ad614SDennis Dalessandro static inline u32 rhf_hdrq_offset(u64 rhf) 381f48ad614SDennis Dalessandro { 382f48ad614SDennis Dalessandro return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK; 383f48ad614SDennis Dalessandro } 384f48ad614SDennis Dalessandro 385f48ad614SDennis Dalessandro static inline u64 rhf_use_egr_bfr(u64 rhf) 386f48ad614SDennis Dalessandro { 387f48ad614SDennis Dalessandro return rhf & RHF_USE_EGR_BFR_SMASK; 388f48ad614SDennis Dalessandro } 389f48ad614SDennis Dalessandro 390f48ad614SDennis Dalessandro static inline u64 rhf_dc_info(u64 rhf) 391f48ad614SDennis Dalessandro { 392f48ad614SDennis Dalessandro return rhf & RHF_DC_INFO_SMASK; 393f48ad614SDennis Dalessandro } 394f48ad614SDennis Dalessandro 395f48ad614SDennis Dalessandro static inline u32 rhf_egr_buf_offset(u64 rhf) 396f48ad614SDennis Dalessandro { 397f48ad614SDennis Dalessandro return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK; 398f48ad614SDennis Dalessandro } 399f48ad614SDennis Dalessandro #endif /* _COMMON_H */ 400