1*145eba1aSCai Huoqing /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2f48ad614SDennis Dalessandro /*
3fe810b50SKaike Wan * Copyright(c) 2015 - 2020 Intel Corporation.
4f48ad614SDennis Dalessandro */
5f48ad614SDennis Dalessandro
6f48ad614SDennis Dalessandro #ifndef _COMMON_H
7f48ad614SDennis Dalessandro #define _COMMON_H
8f48ad614SDennis Dalessandro
9f48ad614SDennis Dalessandro #include <rdma/hfi/hfi1_user.h>
10f48ad614SDennis Dalessandro
11f48ad614SDennis Dalessandro /*
12f48ad614SDennis Dalessandro * This file contains defines, structures, etc. that are used
13f48ad614SDennis Dalessandro * to communicate between kernel and user code.
14f48ad614SDennis Dalessandro */
15f48ad614SDennis Dalessandro
16f48ad614SDennis Dalessandro /* version of protocol header (known to chip also). In the long run,
17f48ad614SDennis Dalessandro * we should be able to generate and accept a range of version numbers;
18f48ad614SDennis Dalessandro * for now we only accept one, and it's compiled in.
19f48ad614SDennis Dalessandro */
20f48ad614SDennis Dalessandro #define IPS_PROTO_VERSION 2
21f48ad614SDennis Dalessandro
22f48ad614SDennis Dalessandro /*
23f48ad614SDennis Dalessandro * These are compile time constants that you may want to enable or disable
24f48ad614SDennis Dalessandro * if you are trying to debug problems with code or performance.
25f48ad614SDennis Dalessandro * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
26f48ad614SDennis Dalessandro * fast path code
27f48ad614SDennis Dalessandro * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
28f48ad614SDennis Dalessandro * traced in fast path code
29f48ad614SDennis Dalessandro * _HFI1_TRACING define as 0 if you want to remove all tracing in a
30f48ad614SDennis Dalessandro * compilation unit
31f48ad614SDennis Dalessandro */
32f48ad614SDennis Dalessandro
33f48ad614SDennis Dalessandro /* driver/hw feature set bitmask */
34f48ad614SDennis Dalessandro #define HFI1_CAP_USER_SHIFT 24
35f48ad614SDennis Dalessandro #define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
36f48ad614SDennis Dalessandro /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
37f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED_SHIFT 63
38f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED_MASK 0x1ULL
39f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
40f48ad614SDennis Dalessandro /* extra bits used between kernel and user processes */
41f48ad614SDennis Dalessandro #define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
42f48ad614SDennis Dalessandro #define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
43f48ad614SDennis Dalessandro HFI1_CAP_MISC_SHIFT)) - 1)
44f48ad614SDennis Dalessandro
45f48ad614SDennis Dalessandro #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
46f48ad614SDennis Dalessandro #define HFI1_CAP_KCLEAR(cap) \
47f48ad614SDennis Dalessandro ({ \
48f48ad614SDennis Dalessandro hfi1_cap_mask &= ~HFI1_CAP_##cap; \
49f48ad614SDennis Dalessandro hfi1_cap_mask; \
50f48ad614SDennis Dalessandro })
51f48ad614SDennis Dalessandro #define HFI1_CAP_USET(cap) \
52f48ad614SDennis Dalessandro ({ \
53f48ad614SDennis Dalessandro hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
54f48ad614SDennis Dalessandro hfi1_cap_mask; \
55f48ad614SDennis Dalessandro })
56f48ad614SDennis Dalessandro #define HFI1_CAP_UCLEAR(cap) \
57f48ad614SDennis Dalessandro ({ \
58f48ad614SDennis Dalessandro hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
59f48ad614SDennis Dalessandro hfi1_cap_mask; \
60f48ad614SDennis Dalessandro })
61f48ad614SDennis Dalessandro #define HFI1_CAP_SET(cap) \
62f48ad614SDennis Dalessandro ({ \
63f48ad614SDennis Dalessandro hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
64f48ad614SDennis Dalessandro HFI1_CAP_USER_SHIFT)); \
65f48ad614SDennis Dalessandro hfi1_cap_mask; \
66f48ad614SDennis Dalessandro })
67f48ad614SDennis Dalessandro #define HFI1_CAP_CLEAR(cap) \
68f48ad614SDennis Dalessandro ({ \
69f48ad614SDennis Dalessandro hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
70f48ad614SDennis Dalessandro (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
71f48ad614SDennis Dalessandro hfi1_cap_mask; \
72f48ad614SDennis Dalessandro })
73f48ad614SDennis Dalessandro #define HFI1_CAP_LOCK() \
74f48ad614SDennis Dalessandro ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
75f48ad614SDennis Dalessandro #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
76f48ad614SDennis Dalessandro /*
77f48ad614SDennis Dalessandro * The set of capability bits that can be changed after initial load
78f48ad614SDennis Dalessandro * This set is the same for kernel and user contexts. However, for
79f48ad614SDennis Dalessandro * user contexts, the set can be further filtered by using the
80f48ad614SDennis Dalessandro * HFI1_CAP_RESERVED_MASK bits.
81f48ad614SDennis Dalessandro */
82f48ad614SDennis Dalessandro #define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
83f48ad614SDennis Dalessandro HFI1_CAP_HDRSUPP | \
84f48ad614SDennis Dalessandro HFI1_CAP_MULTI_PKT_EGR | \
85f48ad614SDennis Dalessandro HFI1_CAP_NODROP_RHQ_FULL | \
86f48ad614SDennis Dalessandro HFI1_CAP_NODROP_EGR_FULL | \
87f48ad614SDennis Dalessandro HFI1_CAP_ALLOW_PERM_JKEY | \
88f48ad614SDennis Dalessandro HFI1_CAP_STATIC_RATE_CTRL | \
89f48ad614SDennis Dalessandro HFI1_CAP_PRINT_UNIMPL | \
90d2e9ace4SKaike Wan HFI1_CAP_TID_UNMAP | \
91d2e9ace4SKaike Wan HFI1_CAP_OPFN)
92f48ad614SDennis Dalessandro /*
93f48ad614SDennis Dalessandro * A set of capability bits that are "global" and are not allowed to be
94f48ad614SDennis Dalessandro * set in the user bitmask.
95f48ad614SDennis Dalessandro */
96f48ad614SDennis Dalessandro #define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
97f48ad614SDennis Dalessandro HFI1_CAP_USE_SDMA_HEAD | \
98f48ad614SDennis Dalessandro HFI1_CAP_EXTENDED_PSN | \
99f48ad614SDennis Dalessandro HFI1_CAP_PRINT_UNIMPL | \
100f48ad614SDennis Dalessandro HFI1_CAP_NO_INTEGRITY | \
101d2e9ace4SKaike Wan HFI1_CAP_PKEY_CHECK | \
102d2e9ace4SKaike Wan HFI1_CAP_TID_RDMA | \
103fe810b50SKaike Wan HFI1_CAP_OPFN | \
104fe810b50SKaike Wan HFI1_CAP_AIP) << \
105f48ad614SDennis Dalessandro HFI1_CAP_USER_SHIFT)
106f48ad614SDennis Dalessandro /*
107f48ad614SDennis Dalessandro * Set of capabilities that need to be enabled for kernel context in
108f48ad614SDennis Dalessandro * order to be allowed for user contexts, as well.
109f48ad614SDennis Dalessandro */
110f48ad614SDennis Dalessandro #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
111f48ad614SDennis Dalessandro /* Default enabled capabilities (both kernel and user) */
112f48ad614SDennis Dalessandro #define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
113f48ad614SDennis Dalessandro HFI1_CAP_NODROP_RHQ_FULL | \
114f48ad614SDennis Dalessandro HFI1_CAP_NODROP_EGR_FULL | \
115f48ad614SDennis Dalessandro HFI1_CAP_SDMA | \
116f48ad614SDennis Dalessandro HFI1_CAP_PRINT_UNIMPL | \
117f48ad614SDennis Dalessandro HFI1_CAP_STATIC_RATE_CTRL | \
118f48ad614SDennis Dalessandro HFI1_CAP_PKEY_CHECK | \
119f48ad614SDennis Dalessandro HFI1_CAP_MULTI_PKT_EGR | \
120f48ad614SDennis Dalessandro HFI1_CAP_EXTENDED_PSN | \
1210ad45e5fSPiotr Stankiewicz HFI1_CAP_AIP | \
122f48ad614SDennis Dalessandro ((HFI1_CAP_HDRSUPP | \
123f48ad614SDennis Dalessandro HFI1_CAP_MULTI_PKT_EGR | \
124f48ad614SDennis Dalessandro HFI1_CAP_STATIC_RATE_CTRL | \
125f48ad614SDennis Dalessandro HFI1_CAP_PKEY_CHECK | \
126f48ad614SDennis Dalessandro HFI1_CAP_EARLY_CREDIT_RETURN) << \
127f48ad614SDennis Dalessandro HFI1_CAP_USER_SHIFT))
128f48ad614SDennis Dalessandro /*
129f48ad614SDennis Dalessandro * A bitmask of kernel/global capabilities that should be communicated
130f48ad614SDennis Dalessandro * to user level processes.
131f48ad614SDennis Dalessandro */
132f48ad614SDennis Dalessandro #define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
133f48ad614SDennis Dalessandro HFI1_CAP_EXTENDED_PSN | \
134f48ad614SDennis Dalessandro HFI1_CAP_PKEY_CHECK | \
135f48ad614SDennis Dalessandro HFI1_CAP_NO_INTEGRITY)
136f48ad614SDennis Dalessandro
137f48ad614SDennis Dalessandro #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
138f48ad614SDennis Dalessandro HFI1_USER_SWMINOR)
139f48ad614SDennis Dalessandro
140f48ad614SDennis Dalessandro /*
141f48ad614SDennis Dalessandro * The next set of defines are for packet headers, and chip register
142f48ad614SDennis Dalessandro * and memory bits that are visible to and/or used by user-mode software.
143f48ad614SDennis Dalessandro */
144f48ad614SDennis Dalessandro
145f48ad614SDennis Dalessandro /*
146f48ad614SDennis Dalessandro * Receive Header Flags
147f48ad614SDennis Dalessandro */
148f48ad614SDennis Dalessandro #define RHF_PKT_LEN_SHIFT 0
149f48ad614SDennis Dalessandro #define RHF_PKT_LEN_MASK 0xfffull
150f48ad614SDennis Dalessandro #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
151f48ad614SDennis Dalessandro
152f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_SHIFT 12
153f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_MASK 0x7ull
154f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
155f48ad614SDennis Dalessandro
156f48ad614SDennis Dalessandro #define RHF_USE_EGR_BFR_SHIFT 15
157f48ad614SDennis Dalessandro #define RHF_USE_EGR_BFR_MASK 0x1ull
158f48ad614SDennis Dalessandro #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
159f48ad614SDennis Dalessandro
160f48ad614SDennis Dalessandro #define RHF_EGR_INDEX_SHIFT 16
161f48ad614SDennis Dalessandro #define RHF_EGR_INDEX_MASK 0x7ffull
162f48ad614SDennis Dalessandro #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
163f48ad614SDennis Dalessandro
164f48ad614SDennis Dalessandro #define RHF_DC_INFO_SHIFT 27
165f48ad614SDennis Dalessandro #define RHF_DC_INFO_MASK 0x1ull
166f48ad614SDennis Dalessandro #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
167f48ad614SDennis Dalessandro
168f48ad614SDennis Dalessandro #define RHF_RCV_SEQ_SHIFT 28
169f48ad614SDennis Dalessandro #define RHF_RCV_SEQ_MASK 0xfull
170f48ad614SDennis Dalessandro #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
171f48ad614SDennis Dalessandro
172f48ad614SDennis Dalessandro #define RHF_EGR_OFFSET_SHIFT 32
173f48ad614SDennis Dalessandro #define RHF_EGR_OFFSET_MASK 0xfffull
174f48ad614SDennis Dalessandro #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
175f48ad614SDennis Dalessandro #define RHF_HDRQ_OFFSET_SHIFT 44
176f48ad614SDennis Dalessandro #define RHF_HDRQ_OFFSET_MASK 0x1ffull
177f48ad614SDennis Dalessandro #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
178f48ad614SDennis Dalessandro #define RHF_K_HDR_LEN_ERR (0x1ull << 53)
179f48ad614SDennis Dalessandro #define RHF_DC_UNC_ERR (0x1ull << 54)
180f48ad614SDennis Dalessandro #define RHF_DC_ERR (0x1ull << 55)
181f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERR_SHIFT 56
182f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERR_MASK 0x7ul
183f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
184f48ad614SDennis Dalessandro #define RHF_TID_ERR (0x1ull << 59)
185f48ad614SDennis Dalessandro #define RHF_LEN_ERR (0x1ull << 60)
186f48ad614SDennis Dalessandro #define RHF_ECC_ERR (0x1ull << 61)
1873c176c9dSJohn Fleck #define RHF_RESERVED (0x1ull << 62)
188f48ad614SDennis Dalessandro #define RHF_ICRC_ERR (0x1ull << 63)
189f48ad614SDennis Dalessandro
190f48ad614SDennis Dalessandro #define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
191f48ad614SDennis Dalessandro
192f48ad614SDennis Dalessandro /* RHF receive types */
193f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_EXPECTED 0
194f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_EAGER 1
195f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
196f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_ERROR 3
197f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_BYPASS 4
198f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_INVALID5 5
199f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_INVALID6 6
200f48ad614SDennis Dalessandro #define RHF_RCV_TYPE_INVALID7 7
201f48ad614SDennis Dalessandro
202f48ad614SDennis Dalessandro /* RHF receive type error - expected packet errors */
203f48ad614SDennis Dalessandro #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
204f48ad614SDennis Dalessandro #define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
205f48ad614SDennis Dalessandro
206f48ad614SDennis Dalessandro /* RHF receive type error - eager packet errors */
207f48ad614SDennis Dalessandro #define RHF_RTE_EAGER_NO_ERR 0x0
208f48ad614SDennis Dalessandro
209f48ad614SDennis Dalessandro /* RHF receive type error - IB packet errors */
210f48ad614SDennis Dalessandro #define RHF_RTE_IB_NO_ERR 0x0
211f48ad614SDennis Dalessandro
212f48ad614SDennis Dalessandro /* RHF receive type error - error packet errors */
213f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_NO_ERR 0x0
214f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_OP_CODE_ERR 0x1
215f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
216f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
217f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
218f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_CONTEXT_ERR 0x5
219f48ad614SDennis Dalessandro #define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
220f48ad614SDennis Dalessandro
221f48ad614SDennis Dalessandro /* RHF receive type error - bypass packet errors */
222f48ad614SDennis Dalessandro #define RHF_RTE_BYPASS_NO_ERR 0x0
223f48ad614SDennis Dalessandro
2242fb3b5aeSMike Marciniszyn /* MAX RcvSEQ */
2252fb3b5aeSMike Marciniszyn #define RHF_MAX_SEQ 13
2262fb3b5aeSMike Marciniszyn
227f48ad614SDennis Dalessandro /* IB - LRH header constants */
228f48ad614SDennis Dalessandro #define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
229f48ad614SDennis Dalessandro #define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
230f48ad614SDennis Dalessandro
231f48ad614SDennis Dalessandro /* misc. */
2329039746cSDon Hiatt #define SC15_PACKET 0xF
233f48ad614SDennis Dalessandro #define SIZE_OF_CRC 1
23472c07e2bSDon Hiatt #define SIZE_OF_LT 1
235f8195f3bSDon Hiatt #define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
236f48ad614SDennis Dalessandro
237f48ad614SDennis Dalessandro #define LIM_MGMT_P_KEY 0x7FFF
238f48ad614SDennis Dalessandro #define FULL_MGMT_P_KEY 0xFFFF
239f48ad614SDennis Dalessandro
240f48ad614SDennis Dalessandro #define DEFAULT_P_KEY LIM_MGMT_P_KEY
241f48ad614SDennis Dalessandro
242f48ad614SDennis Dalessandro #define HFI1_PSM_IOC_BASE_SEQ 0x0
243f48ad614SDennis Dalessandro
24437356e78SKaike Wan /* Number of BTH.PSN bits used for sequence number in expected rcvs */
24537356e78SKaike Wan #define HFI1_KDETH_BTH_SEQ_SHIFT 11
24637356e78SKaike Wan #define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
24737356e78SKaike Wan
rhf_to_cpu(const __le32 * rbuf)248f48ad614SDennis Dalessandro static inline __u64 rhf_to_cpu(const __le32 *rbuf)
249f48ad614SDennis Dalessandro {
250f48ad614SDennis Dalessandro return __le64_to_cpu(*((__le64 *)rbuf));
251f48ad614SDennis Dalessandro }
252f48ad614SDennis Dalessandro
rhf_err_flags(u64 rhf)253f48ad614SDennis Dalessandro static inline u64 rhf_err_flags(u64 rhf)
254f48ad614SDennis Dalessandro {
255f48ad614SDennis Dalessandro return rhf & RHF_ERROR_SMASK;
256f48ad614SDennis Dalessandro }
257f48ad614SDennis Dalessandro
rhf_rcv_type(u64 rhf)258f48ad614SDennis Dalessandro static inline u32 rhf_rcv_type(u64 rhf)
259f48ad614SDennis Dalessandro {
260f48ad614SDennis Dalessandro return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
261f48ad614SDennis Dalessandro }
262f48ad614SDennis Dalessandro
rhf_rcv_type_err(u64 rhf)263f48ad614SDennis Dalessandro static inline u32 rhf_rcv_type_err(u64 rhf)
264f48ad614SDennis Dalessandro {
265f48ad614SDennis Dalessandro return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
266f48ad614SDennis Dalessandro }
267f48ad614SDennis Dalessandro
268f48ad614SDennis Dalessandro /* return size is in bytes, not DWORDs */
rhf_pkt_len(u64 rhf)269f48ad614SDennis Dalessandro static inline u32 rhf_pkt_len(u64 rhf)
270f48ad614SDennis Dalessandro {
271f48ad614SDennis Dalessandro return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
272f48ad614SDennis Dalessandro }
273f48ad614SDennis Dalessandro
rhf_egr_index(u64 rhf)274f48ad614SDennis Dalessandro static inline u32 rhf_egr_index(u64 rhf)
275f48ad614SDennis Dalessandro {
276f48ad614SDennis Dalessandro return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
277f48ad614SDennis Dalessandro }
278f48ad614SDennis Dalessandro
rhf_rcv_seq(u64 rhf)279f48ad614SDennis Dalessandro static inline u32 rhf_rcv_seq(u64 rhf)
280f48ad614SDennis Dalessandro {
281f48ad614SDennis Dalessandro return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
282f48ad614SDennis Dalessandro }
283f48ad614SDennis Dalessandro
284f48ad614SDennis Dalessandro /* returned offset is in DWORDS */
rhf_hdrq_offset(u64 rhf)285f48ad614SDennis Dalessandro static inline u32 rhf_hdrq_offset(u64 rhf)
286f48ad614SDennis Dalessandro {
287f48ad614SDennis Dalessandro return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
288f48ad614SDennis Dalessandro }
289f48ad614SDennis Dalessandro
rhf_use_egr_bfr(u64 rhf)290f48ad614SDennis Dalessandro static inline u64 rhf_use_egr_bfr(u64 rhf)
291f48ad614SDennis Dalessandro {
292f48ad614SDennis Dalessandro return rhf & RHF_USE_EGR_BFR_SMASK;
293f48ad614SDennis Dalessandro }
294f48ad614SDennis Dalessandro
rhf_dc_info(u64 rhf)295f48ad614SDennis Dalessandro static inline u64 rhf_dc_info(u64 rhf)
296f48ad614SDennis Dalessandro {
297f48ad614SDennis Dalessandro return rhf & RHF_DC_INFO_SMASK;
298f48ad614SDennis Dalessandro }
299f48ad614SDennis Dalessandro
rhf_egr_buf_offset(u64 rhf)300f48ad614SDennis Dalessandro static inline u32 rhf_egr_buf_offset(u64 rhf)
301f48ad614SDennis Dalessandro {
302f48ad614SDennis Dalessandro return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
303f48ad614SDennis Dalessandro }
304f48ad614SDennis Dalessandro #endif /* _COMMON_H */
305