1*145eba1aSCai Huoqing /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2f48ad614SDennis Dalessandro /* 3f48ad614SDennis Dalessandro * Copyright(c) 2015, 2016 Intel Corporation. 4f48ad614SDennis Dalessandro */ 5f48ad614SDennis Dalessandro 6*145eba1aSCai Huoqing #ifndef DEF_CHIP_REG 7*145eba1aSCai Huoqing #define DEF_CHIP_REG 8*145eba1aSCai Huoqing 9f48ad614SDennis Dalessandro #define CORE 0x000000000000 10f48ad614SDennis Dalessandro #define CCE (CORE + 0x000000000000) 11f48ad614SDennis Dalessandro #define ASIC (CORE + 0x000000400000) 12f48ad614SDennis Dalessandro #define MISC (CORE + 0x000000500000) 13f48ad614SDennis Dalessandro #define DC_TOP_CSRS (CORE + 0x000000600000) 14f48ad614SDennis Dalessandro #define CHIP_DEBUG (CORE + 0x000000700000) 15f48ad614SDennis Dalessandro #define RXE (CORE + 0x000001000000) 16f48ad614SDennis Dalessandro #define TXE (CORE + 0x000001800000) 17f48ad614SDennis Dalessandro #define DCC_CSRS (DC_TOP_CSRS + 0x000000000000) 18f48ad614SDennis Dalessandro #define DC_LCB_CSRS (DC_TOP_CSRS + 0x000000001000) 19f48ad614SDennis Dalessandro #define DC_8051_CSRS (DC_TOP_CSRS + 0x000000002000) 20f48ad614SDennis Dalessandro #define PCIE 0 21f48ad614SDennis Dalessandro 22f48ad614SDennis Dalessandro #define ASIC_NUM_SCRATCH 4 23f48ad614SDennis Dalessandro #define CCE_ERR_INT_CNT 0 24f48ad614SDennis Dalessandro #define CCE_MISC_INT_CNT 2 25f48ad614SDennis Dalessandro #define CCE_NUM_32_BIT_COUNTERS 3 26f48ad614SDennis Dalessandro #define CCE_NUM_32_BIT_INT_COUNTERS 6 27f48ad614SDennis Dalessandro #define CCE_NUM_INT_CSRS 12 28f48ad614SDennis Dalessandro #define CCE_NUM_INT_MAP_CSRS 96 29f48ad614SDennis Dalessandro #define CCE_NUM_MSIX_PBAS 4 30f48ad614SDennis Dalessandro #define CCE_NUM_MSIX_VECTORS 256 31f48ad614SDennis Dalessandro #define CCE_NUM_SCRATCH 4 32f48ad614SDennis Dalessandro #define CCE_PCIE_POSTED_CRDT_STALL_CNT 2 33f48ad614SDennis Dalessandro #define CCE_PCIE_TRGT_STALL_CNT 0 34f48ad614SDennis Dalessandro #define CCE_PIO_WR_STALL_CNT 1 35f48ad614SDennis Dalessandro #define CCE_RCV_AVAIL_INT_CNT 3 36f48ad614SDennis Dalessandro #define CCE_RCV_URGENT_INT_CNT 4 37f48ad614SDennis Dalessandro #define CCE_SDMA_INT_CNT 1 38f48ad614SDennis Dalessandro #define CCE_SEND_CREDIT_INT_CNT 5 39f48ad614SDennis Dalessandro #define DCC_CFG_LED_CNTRL (DCC_CSRS + 0x000000000040) 40f48ad614SDennis Dalessandro #define DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK 0x10ull 41f48ad614SDennis Dalessandro #define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SHIFT 0 42f48ad614SDennis Dalessandro #define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK 0xFull 43f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG (DCC_CSRS + 0x000000000008) 44f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1 (DCC_CSRS + 0x000000000010) 45f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK 0xFFFFull 46f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT 16 47f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK 0xFFFF0000ull 48f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK 0xFFFFull 49f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT 0 50f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 0xFFFFull 51f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG_LINK_STATE_MASK 0x7ull 52f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT 48 53f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK 0x7000000000000ull 54f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG_MTU_CAP_MASK 0x7ull 55f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT 32 56f48ad614SDennis Dalessandro #define DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK 0x700000000ull 57f48ad614SDennis Dalessandro #define DCC_CFG_RESET (DCC_CSRS + 0x000000000000) 58254361c1SSebastian Sanchez #define DCC_CFG_RESET_RESET_LCB BIT_ULL(0) 59254361c1SSebastian Sanchez #define DCC_CFG_RESET_RESET_TX_FPE BIT_ULL(1) 60254361c1SSebastian Sanchez #define DCC_CFG_RESET_RESET_RX_FPE BIT_ULL(2) 61254361c1SSebastian Sanchez #define DCC_CFG_RESET_RESET_8051 BIT_ULL(3) 62254361c1SSebastian Sanchez #define DCC_CFG_RESET_ENABLE_CCLK_BCC BIT_ULL(4) 63f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0 (DCC_CSRS + 0x000000000028) 64f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY0_SHIFT 0 65f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY10_SHIFT 40 66f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY11_SHIFT 44 67f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY12_SHIFT 48 68f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY13_SHIFT 52 69f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY14_SHIFT 56 70f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY15_SHIFT 60 71f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY1_SHIFT 4 72f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY2_SHIFT 8 73f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY3_SHIFT 12 74f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY4_SHIFT 16 75f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY5_SHIFT 20 76f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY6_SHIFT 24 77f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY7_SHIFT 28 78f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY8_SHIFT 32 79f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_15_0_ENTRY9_SHIFT 36 80f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16 (DCC_CSRS + 0x000000000030) 81f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY16_SHIFT 0 82f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY17_SHIFT 4 83f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY18_SHIFT 8 84f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY19_SHIFT 12 85f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY20_SHIFT 16 86f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY21_SHIFT 20 87f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY22_SHIFT 24 88f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY23_SHIFT 28 89f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY24_SHIFT 32 90f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY25_SHIFT 36 91f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY26_SHIFT 40 92f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY27_SHIFT 44 93f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY28_SHIFT 48 94f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY29_SHIFT 52 95f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY30_SHIFT 56 96f48ad614SDennis Dalessandro #define DCC_CFG_SC_VL_TABLE_31_16_ENTRY31_SHIFT 60 97f48ad614SDennis Dalessandro #define DCC_ERR_DROPPED_PKT_CNT (DCC_CSRS + 0x000000000120) 98f48ad614SDennis Dalessandro #define DCC_ERR_FLG (DCC_CSRS + 0x000000000050) 99f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_CRDT_ACK_ERR_SMASK 0x4000ull 100f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_CTRL_DIST_ERR_SMASK 0x200000ull 101f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_CTRL_FLIT_ERR_SMASK 0x10000ull 102f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_DLID_TARGET_ERR_SMASK 0x200ull 103f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_HEAD_DIST_ERR_SMASK 0x800000ull 104f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_L2_ERR_SMASK 0x2ull 105f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_LVER_ERR_SMASK 0x400ull 106f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_MID_TAIL_ERR_SMASK 0x8ull 107f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_PKT_LENGTH_ERR_SMASK 0x4000000ull 108f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_PREEMPTION_ERR_SMASK 0x10ull 109f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_SC_ERR_SMASK 0x4ull 110f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_TAIL_DIST_ERR_SMASK 0x400000ull 111f48ad614SDennis Dalessandro #define DCC_ERR_FLG_BAD_VL_MARKER_ERR_SMASK 0x80ull 112f48ad614SDennis Dalessandro #define DCC_ERR_FLG_CLR (DCC_CSRS + 0x000000000060) 113f48ad614SDennis Dalessandro #define DCC_ERR_FLG_CSR_ACCESS_BLOCKED_HOST_SMASK 0x8000000000ull 114f48ad614SDennis Dalessandro #define DCC_ERR_FLG_CSR_ACCESS_BLOCKED_UC_SMASK 0x10000000000ull 115f48ad614SDennis Dalessandro #define DCC_ERR_FLG_CSR_INVAL_ADDR_SMASK 0x400000000000ull 116f48ad614SDennis Dalessandro #define DCC_ERR_FLG_CSR_PARITY_ERR_SMASK 0x200000000000ull 117f48ad614SDennis Dalessandro #define DCC_ERR_FLG_DLID_ZERO_ERR_SMASK 0x40000000ull 118f48ad614SDennis Dalessandro #define DCC_ERR_FLG_EN (DCC_CSRS + 0x000000000058) 119f48ad614SDennis Dalessandro #define DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK 0x8000000000ull 120f48ad614SDennis Dalessandro #define DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK 0x10000000000ull 121f48ad614SDennis Dalessandro #define DCC_ERR_FLG_EVENT_CNTR_PARITY_ERR_SMASK 0x20000ull 122f48ad614SDennis Dalessandro #define DCC_ERR_FLG_EVENT_CNTR_ROLLOVER_ERR_SMASK 0x40000ull 123f48ad614SDennis Dalessandro #define DCC_ERR_FLG_FMCONFIG_ERR_SMASK 0x40000000000000ull 124f48ad614SDennis Dalessandro #define DCC_ERR_FLG_FPE_TX_FIFO_OVFLW_ERR_SMASK 0x2000000000ull 125f48ad614SDennis Dalessandro #define DCC_ERR_FLG_FPE_TX_FIFO_UNFLW_ERR_SMASK 0x4000000000ull 126f48ad614SDennis Dalessandro #define DCC_ERR_FLG_LATE_EBP_ERR_SMASK 0x1000000000ull 127f48ad614SDennis Dalessandro #define DCC_ERR_FLG_LATE_LONG_ERR_SMASK 0x800000000ull 128f48ad614SDennis Dalessandro #define DCC_ERR_FLG_LATE_SHORT_ERR_SMASK 0x400000000ull 129f48ad614SDennis Dalessandro #define DCC_ERR_FLG_LENGTH_MTU_ERR_SMASK 0x80000000ull 130f48ad614SDennis Dalessandro #define DCC_ERR_FLG_LINK_ERR_SMASK 0x80000ull 131f48ad614SDennis Dalessandro #define DCC_ERR_FLG_MISC_CNTR_ROLLOVER_ERR_SMASK 0x100000ull 132f48ad614SDennis Dalessandro #define DCC_ERR_FLG_NONVL15_STATE_ERR_SMASK 0x1000000ull 133f48ad614SDennis Dalessandro #define DCC_ERR_FLG_PERM_NVL15_ERR_SMASK 0x10000000ull 134f48ad614SDennis Dalessandro #define DCC_ERR_FLG_PREEMPTION_ERR_SMASK 0x20ull 135f48ad614SDennis Dalessandro #define DCC_ERR_FLG_PREEMPTIONVL15_ERR_SMASK 0x40ull 136f48ad614SDennis Dalessandro #define DCC_ERR_FLG_RCVPORT_ERR_SMASK 0x80000000000000ull 137f48ad614SDennis Dalessandro #define DCC_ERR_FLG_RX_BYTE_SHFT_PARITY_ERR_SMASK 0x1000000000000ull 138f48ad614SDennis Dalessandro #define DCC_ERR_FLG_RX_CTRL_PARITY_MBE_ERR_SMASK 0x100000000000ull 139f48ad614SDennis Dalessandro #define DCC_ERR_FLG_RX_EARLY_DROP_ERR_SMASK 0x200000000ull 140f48ad614SDennis Dalessandro #define DCC_ERR_FLG_SLID_ZERO_ERR_SMASK 0x20000000ull 141f48ad614SDennis Dalessandro #define DCC_ERR_FLG_TX_BYTE_SHFT_PARITY_ERR_SMASK 0x800000000000ull 142f48ad614SDennis Dalessandro #define DCC_ERR_FLG_TX_CTRL_PARITY_ERR_SMASK 0x20000000000ull 143f48ad614SDennis Dalessandro #define DCC_ERR_FLG_TX_CTRL_PARITY_MBE_ERR_SMASK 0x40000000000ull 144f48ad614SDennis Dalessandro #define DCC_ERR_FLG_TX_SC_PARITY_ERR_SMASK 0x80000000000ull 145f48ad614SDennis Dalessandro #define DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK 0x2000ull 146f48ad614SDennis Dalessandro #define DCC_ERR_FLG_UNSUP_PKT_TYPE_SMASK 0x8000ull 147f48ad614SDennis Dalessandro #define DCC_ERR_FLG_UNSUP_VL_ERR_SMASK 0x8000000ull 148f48ad614SDennis Dalessandro #define DCC_ERR_FLG_VL15_MULTI_ERR_SMASK 0x2000000ull 149f48ad614SDennis Dalessandro #define DCC_ERR_FMCONFIG_ERR_CNT (DCC_CSRS + 0x000000000110) 150f48ad614SDennis Dalessandro #define DCC_ERR_INFO_FMCONFIG (DCC_CSRS + 0x000000000090) 151f48ad614SDennis Dalessandro #define DCC_ERR_INFO_PORTRCV (DCC_CSRS + 0x000000000078) 152f48ad614SDennis Dalessandro #define DCC_ERR_INFO_PORTRCV_HDR0 (DCC_CSRS + 0x000000000080) 153f48ad614SDennis Dalessandro #define DCC_ERR_INFO_PORTRCV_HDR1 (DCC_CSRS + 0x000000000088) 154f48ad614SDennis Dalessandro #define DCC_ERR_INFO_UNCORRECTABLE (DCC_CSRS + 0x000000000098) 155f48ad614SDennis Dalessandro #define DCC_ERR_PORTRCV_ERR_CNT (DCC_CSRS + 0x000000000108) 156f48ad614SDennis Dalessandro #define DCC_ERR_RCVREMOTE_PHY_ERR_CNT (DCC_CSRS + 0x000000000118) 157f48ad614SDennis Dalessandro #define DCC_ERR_UNCORRECTABLE_CNT (DCC_CSRS + 0x000000000100) 158f48ad614SDennis Dalessandro #define DCC_PRF_PORT_MARK_FECN_CNT (DCC_CSRS + 0x000000000330) 159f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_BECN_CNT (DCC_CSRS + 0x000000000290) 160f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_BUBBLE_CNT (DCC_CSRS + 0x0000000002E0) 161f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_CORRECTABLE_CNT (DCC_CSRS + 0x000000000140) 162f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_DATA_CNT (DCC_CSRS + 0x000000000198) 163f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_FECN_CNT (DCC_CSRS + 0x000000000240) 164f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT (DCC_CSRS + 0x000000000130) 165f48ad614SDennis Dalessandro #define DCC_PRF_PORT_RCV_PKTS_CNT (DCC_CSRS + 0x0000000001A8) 166f48ad614SDennis Dalessandro #define DCC_PRF_PORT_VL_MARK_FECN_CNT (DCC_CSRS + 0x000000000338) 167f48ad614SDennis Dalessandro #define DCC_PRF_PORT_VL_RCV_BECN_CNT (DCC_CSRS + 0x000000000298) 168f48ad614SDennis Dalessandro #define DCC_PRF_PORT_VL_RCV_BUBBLE_CNT (DCC_CSRS + 0x0000000002E8) 169f48ad614SDennis Dalessandro #define DCC_PRF_PORT_VL_RCV_DATA_CNT (DCC_CSRS + 0x0000000001B0) 170f48ad614SDennis Dalessandro #define DCC_PRF_PORT_VL_RCV_FECN_CNT (DCC_CSRS + 0x000000000248) 171f48ad614SDennis Dalessandro #define DCC_PRF_PORT_VL_RCV_PKTS_CNT (DCC_CSRS + 0x0000000001F8) 172f48ad614SDennis Dalessandro #define DCC_PRF_PORT_XMIT_CORRECTABLE_CNT (DCC_CSRS + 0x000000000138) 173f48ad614SDennis Dalessandro #define DCC_PRF_PORT_XMIT_DATA_CNT (DCC_CSRS + 0x000000000190) 174f48ad614SDennis Dalessandro #define DCC_PRF_PORT_XMIT_MULTICAST_CNT (DCC_CSRS + 0x000000000128) 175f48ad614SDennis Dalessandro #define DCC_PRF_PORT_XMIT_PKTS_CNT (DCC_CSRS + 0x0000000001A0) 176f48ad614SDennis Dalessandro #define DCC_PRF_RX_FLOW_CRTL_CNT (DCC_CSRS + 0x000000000180) 177f48ad614SDennis Dalessandro #define DCC_PRF_TX_FLOW_CRTL_CNT (DCC_CSRS + 0x000000000188) 178f48ad614SDennis Dalessandro #define DC_DC8051_CFG_CSR_ACCESS_SEL (DC_8051_CSRS + 0x000000000110) 179f48ad614SDennis Dalessandro #define DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK 0x2ull 180f48ad614SDennis Dalessandro #define DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK 0x1ull 181f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_0 (DC_8051_CSRS + 0x000000000118) 182f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK 0x1ull 183f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT 8 184f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT 16 185f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1 (DC_8051_CSRS + 0x000000000120) 186f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK 0xFFFFull 187f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT 16 188f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK 0xFFFF0000ull 189f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK 0x1ull 190f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK 0xFFull 191f48ad614SDennis Dalessandro #define DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT 8 192f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_0 (DC_8051_CSRS + 0x000000000028) 193f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK 0xFFFFFFFFFFFFull 194f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT 16 195f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK 0x1ull 196f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK 0xFFull 197f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8 198f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_1 (DC_8051_CSRS + 0x000000000030) 199f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK 0x1ull 200f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK 0xFFull 201f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT 8 202f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK 0xFFFFFFFFFFFFull 203f48ad614SDennis Dalessandro #define DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT 16 204f48ad614SDennis Dalessandro #define DC_DC8051_CFG_LOCAL_GUID (DC_8051_CSRS + 0x000000000038) 205f48ad614SDennis Dalessandro #define DC_DC8051_CFG_MODE (DC_8051_CSRS + 0x000000000070) 206f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_CTRL (DC_8051_CSRS + 0x000000000008) 207f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK 0x7FFFull 208f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT 0 209f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK 0x1000000ull 210f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK 0x10000ull 211f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_SETUP (DC_8051_CSRS + 0x000000000000) 212f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK 0x100ull 213f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK 0x1ull 214f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_STATUS (DC_8051_CSRS + 0x000000000018) 215f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK 0x10000ull 216f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_WR_DATA (DC_8051_CSRS + 0x000000000010) 217f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RAM_ACCESS_RD_DATA (DC_8051_CSRS + 0x000000000020) 218f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RST (DC_8051_CSRS + 0x000000000068) 219f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RST_CRAM_SMASK 0x2ull 220f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RST_DRAM_SMASK 0x4ull 221f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RST_IRAM_SMASK 0x8ull 222f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RST_M8051W_SMASK 0x1ull 223f48ad614SDennis Dalessandro #define DC_DC8051_CFG_RST_SFR_SMASK 0x10ull 224f48ad614SDennis Dalessandro #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051 (DC_8051_CSRS + 0x0000000000D8) 225f48ad614SDennis Dalessandro #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK 0xFFFFFFFFull 226f48ad614SDennis Dalessandro #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT 16 227f48ad614SDennis Dalessandro #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK 0xFFFFull 228f48ad614SDennis Dalessandro #define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT 0 229f48ad614SDennis Dalessandro #define DC_DC8051_ERR_CLR (DC_8051_CSRS + 0x0000000000E8) 230f48ad614SDennis Dalessandro #define DC_DC8051_ERR_EN (DC_8051_CSRS + 0x0000000000F0) 231f48ad614SDennis Dalessandro #define DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK 0x2ull 232f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG (DC_8051_CSRS + 0x0000000000E0) 233f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_CRAM_MBE_SMASK 0x4ull 234f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_CRAM_SBE_SMASK 0x8ull 235f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_DRAM_MBE_SMASK 0x10ull 236f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_DRAM_SBE_SMASK 0x20ull 237f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_INVALID_CSR_ADDR_SMASK 0x400ull 238f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_IRAM_MBE_SMASK 0x40ull 239f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_IRAM_SBE_SMASK 0x80ull 240f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK 0x2ull 241f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_SET_BY_8051_SMASK 0x1ull 242f48ad614SDennis Dalessandro #define DC_DC8051_ERR_FLG_UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES_SMASK 0x100ull 243f48ad614SDennis Dalessandro #define DC_DC8051_STS_CUR_STATE (DC_8051_CSRS + 0x000000000060) 244f48ad614SDennis Dalessandro #define DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK 0xFFull 245f48ad614SDennis Dalessandro #define DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT 16 246f48ad614SDennis Dalessandro #define DC_DC8051_STS_CUR_STATE_PORT_MASK 0xFFull 247f48ad614SDennis Dalessandro #define DC_DC8051_STS_CUR_STATE_PORT_SHIFT 0 248f48ad614SDennis Dalessandro #define DC_DC8051_STS_LOCAL_FM_SECURITY (DC_8051_CSRS + 0x000000000050) 249f48ad614SDennis Dalessandro #define DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK 0x1ull 250f48ad614SDennis Dalessandro #define DC_DC8051_STS_REMOTE_FM_SECURITY (DC_8051_CSRS + 0x000000000058) 251f48ad614SDennis Dalessandro #define DC_DC8051_STS_REMOTE_GUID (DC_8051_CSRS + 0x000000000040) 252f48ad614SDennis Dalessandro #define DC_DC8051_STS_REMOTE_NODE_TYPE (DC_8051_CSRS + 0x000000000048) 253f48ad614SDennis Dalessandro #define DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK 0x3ull 254f48ad614SDennis Dalessandro #define DC_DC8051_STS_REMOTE_PORT_NO (DC_8051_CSRS + 0x000000000130) 255f48ad614SDennis Dalessandro #define DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK 0xFFull 256f48ad614SDennis Dalessandro #define DC_LCB_CFG_ALLOW_LINK_UP (DC_LCB_CSRS + 0x000000000128) 257f48ad614SDennis Dalessandro #define DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT 0 258f48ad614SDennis Dalessandro #define DC_LCB_CFG_CRC_MODE (DC_LCB_CSRS + 0x000000000058) 259f48ad614SDennis Dalessandro #define DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT 0 260f48ad614SDennis Dalessandro #define DC_LCB_CFG_IGNORE_LOST_RCLK (DC_LCB_CSRS + 0x000000000020) 261f48ad614SDennis Dalessandro #define DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK 0x1ull 262f48ad614SDennis Dalessandro #define DC_LCB_CFG_LANE_WIDTH (DC_LCB_CSRS + 0x000000000100) 263f48ad614SDennis Dalessandro #define DC_LCB_CFG_LINK_KILL_EN (DC_LCB_CSRS + 0x000000000120) 264f48ad614SDennis Dalessandro #define DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK 0x100000ull 265f48ad614SDennis Dalessandro #define DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 0x400000ull 266f48ad614SDennis Dalessandro #define DC_LCB_CFG_LN_DCLK (DC_LCB_CSRS + 0x000000000060) 267f48ad614SDennis Dalessandro #define DC_LCB_CFG_LOOPBACK (DC_LCB_CSRS + 0x0000000000F8) 268f48ad614SDennis Dalessandro #define DC_LCB_CFG_LOOPBACK_VAL_SHIFT 0 269f48ad614SDennis Dalessandro #define DC_LCB_CFG_RUN (DC_LCB_CSRS + 0x000000000000) 270f48ad614SDennis Dalessandro #define DC_LCB_CFG_RUN_EN_SHIFT 0 271f48ad614SDennis Dalessandro #define DC_LCB_CFG_RX_FIFOS_RADR (DC_LCB_CSRS + 0x000000000018) 272f48ad614SDennis Dalessandro #define DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 8 273f48ad614SDennis Dalessandro #define DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 4 274f48ad614SDennis Dalessandro #define DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT 0 275f48ad614SDennis Dalessandro #define DC_LCB_CFG_TX_FIFOS_RADR (DC_LCB_CSRS + 0x000000000010) 276f48ad614SDennis Dalessandro #define DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT 0 277f48ad614SDennis Dalessandro #define DC_LCB_CFG_TX_FIFOS_RESET (DC_LCB_CSRS + 0x000000000008) 278f48ad614SDennis Dalessandro #define DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT 0 279f48ad614SDennis Dalessandro #define DC_LCB_CFG_REINIT_AS_SLAVE (DC_LCB_CSRS + 0x000000000030) 280f48ad614SDennis Dalessandro #define DC_LCB_CFG_CNT_FOR_SKIP_STALL (DC_LCB_CSRS + 0x000000000040) 281f48ad614SDennis Dalessandro #define DC_LCB_CFG_CLK_CNTR (DC_LCB_CSRS + 0x000000000110) 282f48ad614SDennis Dalessandro #define DC_LCB_ERR_CLR (DC_LCB_CSRS + 0x000000000308) 283f48ad614SDennis Dalessandro #define DC_LCB_ERR_EN (DC_LCB_CSRS + 0x000000000310) 284f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG (DC_LCB_CSRS + 0x000000000300) 285f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_REDUNDANT_FLIT_PARITY_ERR_SMASK 0x20000000ull 286f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_NEG_EDGE_LINK_TRANSFER_ACTIVE_SMASK 0x10000000ull 287f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_HOLD_REINIT_SMASK 0x8000000ull 288f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_RST_FOR_INCOMPLT_RND_TRIP_SMASK 0x4000000ull 289f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_RST_FOR_LINK_TIMEOUT_SMASK 0x2000000ull 290f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_CREDIT_RETURN_FLIT_MBE_SMASK 0x1000000ull 291f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_REPLAY_BUF_SBE_SMASK 0x800000ull 292f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_REPLAY_BUF_MBE_SMASK 0x400000ull 293f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_SBE_SMASK 0x200000ull 294f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_MBE_SMASK 0x100000ull 295f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_VL_ACK_INPUT_WRONG_CRC_MODE_SMASK 0x80000ull 296f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_VL_ACK_INPUT_PARITY_ERR_SMASK 0x40000ull 297f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_VL_ACK_INPUT_BUF_OFLW_SMASK 0x20000ull 298f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_OFLW_SMASK 0x10000ull 299f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_ILLEGAL_FLIT_ENCODING_SMASK 0x8000ull 300f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_ILLEGAL_NULL_LTP_SMASK 0x4000ull 301f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_UNEXPECTED_ROUND_TRIP_MARKER_SMASK 0x2000ull 302f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_UNEXPECTED_REPLAY_MARKER_SMASK 0x1000ull 303f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_RCLK_STOPPED_SMASK 0x800ull 304f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_CRC_ERR_CNT_HIT_LIMIT_SMASK 0x400ull 305f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_REINIT_FOR_LN_DEGRADE_SMASK 0x200ull 306f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_REINIT_FROM_PEER_SMASK 0x100ull 307f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_SEQ_CRC_ERR_SMASK 0x80ull 308f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_RX_LESS_THAN_FOUR_LNS_SMASK 0x40ull 309f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_TX_LESS_THAN_FOUR_LNS_SMASK 0x20ull 310f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_LOST_REINIT_STALL_OR_TOS_SMASK 0x10ull 311f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_ALL_LNS_FAILED_REINIT_TEST_SMASK 0x8ull 312f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_RST_FOR_FAILED_DESKEW_SMASK 0x4ull 313f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_INVALID_CSR_ADDR_SMASK 0x2ull 314f48ad614SDennis Dalessandro #define DC_LCB_ERR_FLG_CSR_PARITY_ERR_SMASK 0x1ull 315f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_CRC_ERR_LN0 (DC_LCB_CSRS + 0x000000000328) 316f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_CRC_ERR_LN1 (DC_LCB_CSRS + 0x000000000330) 317f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_CRC_ERR_LN2 (DC_LCB_CSRS + 0x000000000338) 318f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_CRC_ERR_LN3 (DC_LCB_CSRS + 0x000000000340) 319f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN (DC_LCB_CSRS + 0x000000000348) 320f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT (DC_LCB_CSRS + 0x000000000368) 321f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT (DC_LCB_CSRS + 0x000000000370) 322f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT (DC_LCB_CSRS + 0x000000000378) 323f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_MISC_FLG_CNT (DC_LCB_CSRS + 0x000000000390) 324f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT (DC_LCB_CSRS + 0x000000000380) 325f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_RX_REPLAY_CNT (DC_LCB_CSRS + 0x000000000358) 326f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_SBE_CNT (DC_LCB_CSRS + 0x000000000388) 327f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_SEQ_CRC_CNT (DC_LCB_CSRS + 0x000000000360) 328f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_TOTAL_CRC_ERR (DC_LCB_CSRS + 0x000000000320) 329f48ad614SDennis Dalessandro #define DC_LCB_ERR_INFO_TX_REPLAY_CNT (DC_LCB_CSRS + 0x000000000350) 330f48ad614SDennis Dalessandro #define DC_LCB_PG_DBG_FLIT_CRDTS_CNT (DC_LCB_CSRS + 0x000000000580) 331f48ad614SDennis Dalessandro #define DC_LCB_PG_STS_PAUSE_COMPLETE_CNT (DC_LCB_CSRS + 0x0000000005F8) 332f48ad614SDennis Dalessandro #define DC_LCB_PG_STS_TX_MBE_CNT (DC_LCB_CSRS + 0x000000000608) 333f48ad614SDennis Dalessandro #define DC_LCB_PG_STS_TX_SBE_CNT (DC_LCB_CSRS + 0x000000000600) 334f48ad614SDennis Dalessandro #define DC_LCB_PRF_ACCEPTED_LTP_CNT (DC_LCB_CSRS + 0x000000000408) 335f48ad614SDennis Dalessandro #define DC_LCB_PRF_CLK_CNTR (DC_LCB_CSRS + 0x000000000420) 336f48ad614SDennis Dalessandro #define DC_LCB_PRF_GOOD_LTP_CNT (DC_LCB_CSRS + 0x000000000400) 337f48ad614SDennis Dalessandro #define DC_LCB_PRF_RX_FLIT_CNT (DC_LCB_CSRS + 0x000000000410) 338f48ad614SDennis Dalessandro #define DC_LCB_PRF_TX_FLIT_CNT (DC_LCB_CSRS + 0x000000000418) 339f48ad614SDennis Dalessandro #define DC_LCB_STS_LINK_TRANSFER_ACTIVE (DC_LCB_CSRS + 0x000000000468) 340f48ad614SDennis Dalessandro #define DC_LCB_STS_ROUND_TRIP_LTP_CNT (DC_LCB_CSRS + 0x0000000004B0) 341a9c62e00SMike Marciniszyn #define RCV_LENGTH_ERR_CNT 0 3422c9d4e26SMike Marciniszyn #define RCV_SHORT_ERR_CNT 2 343a9c62e00SMike Marciniszyn #define RCV_ICRC_ERR_CNT 6 344a9c62e00SMike Marciniszyn #define RCV_EBP_CNT 9 345f48ad614SDennis Dalessandro #define RCV_BUF_OVFL_CNT 10 346f48ad614SDennis Dalessandro #define RCV_CONTEXT_EGR_STALL 22 347f48ad614SDennis Dalessandro #define RCV_DATA_PKT_CNT 0 348f48ad614SDennis Dalessandro #define RCV_DWORD_CNT 1 349f48ad614SDennis Dalessandro #define RCV_TID_FLOW_GEN_MISMATCH_CNT 20 350f48ad614SDennis Dalessandro #define RCV_TID_FLOW_SEQ_MISMATCH_CNT 23 351f48ad614SDennis Dalessandro #define RCV_TID_FULL_ERR_CNT 18 352f48ad614SDennis Dalessandro #define RCV_TID_VALID_ERR_CNT 19 353f48ad614SDennis Dalessandro #define RXE_NUM_32_BIT_COUNTERS 24 354f48ad614SDennis Dalessandro #define RXE_NUM_64_BIT_COUNTERS 2 355f48ad614SDennis Dalessandro #define RXE_NUM_RSM_INSTANCES 4 356f48ad614SDennis Dalessandro #define RXE_NUM_TID_FLOWS 32 357f48ad614SDennis Dalessandro #define RXE_PER_CONTEXT_OFFSET 0x0300000 358f48ad614SDennis Dalessandro #define SEND_DATA_PKT_CNT 0 359f48ad614SDennis Dalessandro #define SEND_DATA_PKT_VL0_CNT 12 360f48ad614SDennis Dalessandro #define SEND_DATA_VL0_CNT 3 361f48ad614SDennis Dalessandro #define SEND_DROPPED_PKT_CNT 5 362f48ad614SDennis Dalessandro #define SEND_DWORD_CNT 1 363f48ad614SDennis Dalessandro #define SEND_FLOW_STALL_CNT 4 364f48ad614SDennis Dalessandro #define SEND_HEADERS_ERR_CNT 6 365f48ad614SDennis Dalessandro #define SEND_LEN_ERR_CNT 1 366f48ad614SDennis Dalessandro #define SEND_MAX_MIN_LEN_ERR_CNT 2 367f48ad614SDennis Dalessandro #define SEND_UNDERRUN_CNT 3 368f48ad614SDennis Dalessandro #define SEND_UNSUP_VL_ERR_CNT 0 369f48ad614SDennis Dalessandro #define SEND_WAIT_CNT 2 370f48ad614SDennis Dalessandro #define SEND_WAIT_VL0_CNT 21 371f48ad614SDennis Dalessandro #define TXE_PIO_SEND_OFFSET 0x0800000 372f48ad614SDennis Dalessandro #define ASIC_CFG_DRV_STR (ASIC + 0x000000000048) 373f48ad614SDennis Dalessandro #define ASIC_CFG_MUTEX (ASIC + 0x000000000040) 374f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_EXECUTE (ASIC + 0x000000000008) 375f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK 0x1ull 376f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK 0x2ull 377f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_REQUEST (ASIC + 0x000000000000) 378f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT 16 379f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT 8 380f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT 32 381f48ad614SDennis Dalessandro #define ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT 0 382f48ad614SDennis Dalessandro #define ASIC_CFG_SCRATCH (ASIC + 0x000000000020) 383fe4d9243SEaswar Hariharan #define ASIC_CFG_SCRATCH_1 (ASIC_CFG_SCRATCH + 0x08) 384fe4d9243SEaswar Hariharan #define ASIC_CFG_SCRATCH_2 (ASIC_CFG_SCRATCH + 0x10) 385fe4d9243SEaswar Hariharan #define ASIC_CFG_SCRATCH_3 (ASIC_CFG_SCRATCH + 0x18) 386f48ad614SDennis Dalessandro #define ASIC_CFG_THERM_POLL_EN (ASIC + 0x000000000050) 387f48ad614SDennis Dalessandro #define ASIC_EEP_ADDR_CMD (ASIC + 0x000000000308) 388f48ad614SDennis Dalessandro #define ASIC_EEP_ADDR_CMD_EP_ADDR_MASK 0xFFFFFFull 389f48ad614SDennis Dalessandro #define ASIC_EEP_CTL_STAT (ASIC + 0x000000000300) 390f48ad614SDennis Dalessandro #define ASIC_EEP_CTL_STAT_EP_RESET_SMASK 0x4ull 391f48ad614SDennis Dalessandro #define ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT 8 392f48ad614SDennis Dalessandro #define ASIC_EEP_CTL_STAT_RESETCSR 0x0000000083818000ull 393f48ad614SDennis Dalessandro #define ASIC_EEP_DATA (ASIC + 0x000000000310) 394f48ad614SDennis Dalessandro #define ASIC_GPIO_CLEAR (ASIC + 0x000000000230) 395f48ad614SDennis Dalessandro #define ASIC_GPIO_FORCE (ASIC + 0x000000000238) 396f48ad614SDennis Dalessandro #define ASIC_GPIO_IN (ASIC + 0x000000000200) 397f48ad614SDennis Dalessandro #define ASIC_GPIO_INVERT (ASIC + 0x000000000210) 398f48ad614SDennis Dalessandro #define ASIC_GPIO_MASK (ASIC + 0x000000000220) 399f48ad614SDennis Dalessandro #define ASIC_GPIO_OE (ASIC + 0x000000000208) 400f48ad614SDennis Dalessandro #define ASIC_GPIO_OUT (ASIC + 0x000000000218) 401f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_CMD (ASIC + 0x000000000100) 402f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT 0 403f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK 0x400ull 404f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT 2 405f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_CMD_TIMER_MASK 0xFFFFFull 406f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT 12 407f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_STATUS (ASIC + 0x000000000108) 408f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK 0x7ull 409f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT 2 410f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK 0x3ull 411f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT 0 412f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_INTRPT_DATA_CODE (ASIC + 0x000000000110) 413f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_INTRPT_ENABLE (ASIC + 0x000000000118) 414f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_INTRPT_LIST (ASIC + 0x000000000180) 415f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT 16 416f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT 0 417f48ad614SDennis Dalessandro #define ASIC_PCIE_SD_INTRPT_STATUS (ASIC + 0x000000000128) 418f48ad614SDennis Dalessandro #define ASIC_QSFP1_CLEAR (ASIC + 0x000000000270) 419f48ad614SDennis Dalessandro #define ASIC_QSFP1_FORCE (ASIC + 0x000000000278) 420f48ad614SDennis Dalessandro #define ASIC_QSFP1_IN (ASIC + 0x000000000240) 421f48ad614SDennis Dalessandro #define ASIC_QSFP1_INVERT (ASIC + 0x000000000250) 422f48ad614SDennis Dalessandro #define ASIC_QSFP1_MASK (ASIC + 0x000000000260) 423f48ad614SDennis Dalessandro #define ASIC_QSFP1_OE (ASIC + 0x000000000248) 424f48ad614SDennis Dalessandro #define ASIC_QSFP1_OUT (ASIC + 0x000000000258) 425f48ad614SDennis Dalessandro #define ASIC_QSFP1_STATUS (ASIC + 0x000000000268) 426f48ad614SDennis Dalessandro #define ASIC_QSFP2_CLEAR (ASIC + 0x0000000002B0) 427f48ad614SDennis Dalessandro #define ASIC_QSFP2_FORCE (ASIC + 0x0000000002B8) 428f48ad614SDennis Dalessandro #define ASIC_QSFP2_IN (ASIC + 0x000000000280) 429f48ad614SDennis Dalessandro #define ASIC_QSFP2_INVERT (ASIC + 0x000000000290) 430f48ad614SDennis Dalessandro #define ASIC_QSFP2_MASK (ASIC + 0x0000000002A0) 431f48ad614SDennis Dalessandro #define ASIC_QSFP2_OE (ASIC + 0x000000000288) 432f48ad614SDennis Dalessandro #define ASIC_QSFP2_OUT (ASIC + 0x000000000298) 433f48ad614SDennis Dalessandro #define ASIC_QSFP2_STATUS (ASIC + 0x0000000002A8) 434f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_COUNTERS (ASIC + 0x000000000018) 435f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_MASK 0xFFFFull 436f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_SHIFT 0 437f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_MASK 0xFFFFull 438f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_SHIFT 16 439f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_RESULT (ASIC + 0x000000000010) 440f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_RESULT_DONE_SMASK 0x1ull 441f48ad614SDennis Dalessandro #define ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK 0x2ull 442b3bf270bSDean Luick #define ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT 2 443b3bf270bSDean Luick #define ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK 0x7ull 444b3bf270bSDean Luick #define ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT 32 445b3bf270bSDean Luick #define ASIC_STS_SBUS_RESULT_DATA_OUT_MASK 0xFFFFFFFFull 446f48ad614SDennis Dalessandro #define ASIC_STS_THERM (ASIC + 0x000000000058) 447f48ad614SDennis Dalessandro #define ASIC_STS_THERM_CRIT_TEMP_MASK 0x7FFull 448f48ad614SDennis Dalessandro #define ASIC_STS_THERM_CRIT_TEMP_SHIFT 18 449f48ad614SDennis Dalessandro #define ASIC_STS_THERM_CURR_TEMP_MASK 0x7FFull 450f48ad614SDennis Dalessandro #define ASIC_STS_THERM_CURR_TEMP_SHIFT 2 451f48ad614SDennis Dalessandro #define ASIC_STS_THERM_HI_TEMP_MASK 0x7FFull 452f48ad614SDennis Dalessandro #define ASIC_STS_THERM_HI_TEMP_SHIFT 50 453f48ad614SDennis Dalessandro #define ASIC_STS_THERM_LO_TEMP_MASK 0x7FFull 454f48ad614SDennis Dalessandro #define ASIC_STS_THERM_LO_TEMP_SHIFT 34 455f48ad614SDennis Dalessandro #define ASIC_STS_THERM_LOW_SHIFT 13 456f48ad614SDennis Dalessandro #define CCE_COUNTER_ARRAY32 (CCE + 0x000000000060) 457f48ad614SDennis Dalessandro #define CCE_CTRL (CCE + 0x000000000010) 458f48ad614SDennis Dalessandro #define CCE_CTRL_RXE_RESUME_SMASK 0x800ull 459f48ad614SDennis Dalessandro #define CCE_CTRL_SPC_FREEZE_SMASK 0x100ull 460f48ad614SDennis Dalessandro #define CCE_CTRL_SPC_UNFREEZE_SMASK 0x200ull 461f48ad614SDennis Dalessandro #define CCE_CTRL_TXE_RESUME_SMASK 0x2000ull 462f48ad614SDennis Dalessandro #define CCE_DC_CTRL (CCE + 0x0000000000B8) 463f48ad614SDennis Dalessandro #define CCE_DC_CTRL_DC_RESET_SMASK 0x1ull 464f48ad614SDennis Dalessandro #define CCE_DC_CTRL_RESETCSR 0x0000000000000001ull 465f48ad614SDennis Dalessandro #define CCE_ERR_CLEAR (CCE + 0x000000000050) 466f48ad614SDennis Dalessandro #define CCE_ERR_MASK (CCE + 0x000000000048) 467f48ad614SDennis Dalessandro #define CCE_ERR_STATUS (CCE + 0x000000000040) 468f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK 0x40ull 469f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK 0x1000ull 470f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK \ 471f48ad614SDennis Dalessandro 0x200ull 472f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK \ 473f48ad614SDennis Dalessandro 0x800ull 474f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK \ 475f48ad614SDennis Dalessandro 0x400ull 476f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK 0x100ull 477f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK 0x80ull 478f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK 0x1ull 479f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull 480f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull 481f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK 0x4000000000ull 482f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK 0x8000000000ull 483f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK 0x10000000000ull 484f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK 0x1000000000ull 485f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK 0x2000000000ull 486f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK 0x400000000ull 487f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK 0x20ull 488f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK 0x800000000ull 489f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK 0x100000000ull 490f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK 0x200000000ull 491f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK 0x10ull 492f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK 0x8ull 493f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK 0x40000000ull 494f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_LA_TRIGGERED_SMASK 0x80000000ull 495f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK 0x40000ull 496f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK 0x4000000ull 497f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK 0x20000ull 498f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK 0x2000000ull 499f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK 0x100000ull 500f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK 0x80000ull 501f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK 0x10000ull 502f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK 0x1000000ull 503f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK 0x8000ull 504f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK 0x800000ull 505f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK 0x20000000ull 506f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK 0x2000ull 507f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK 0x200000ull 508f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK 0x4000ull 509f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK 0x400000ull 510f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK 0x10000000ull 511f48ad614SDennis Dalessandro #define CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK 0x8000000ull 512f48ad614SDennis Dalessandro #define CCE_INT_CLEAR (CCE + 0x000000110A00) 513f48ad614SDennis Dalessandro #define CCE_INT_COUNTER_ARRAY32 (CCE + 0x000000110D00) 514f48ad614SDennis Dalessandro #define CCE_INT_FORCE (CCE + 0x000000110B00) 515f48ad614SDennis Dalessandro #define CCE_INT_MAP (CCE + 0x000000110500) 516f48ad614SDennis Dalessandro #define CCE_INT_MASK (CCE + 0x000000110900) 517f48ad614SDennis Dalessandro #define CCE_INT_STATUS (CCE + 0x000000110800) 518f48ad614SDennis Dalessandro #define CCE_MSIX_INT_GRANTED (CCE + 0x000000110200) 519f48ad614SDennis Dalessandro #define CCE_MSIX_TABLE_LOWER (CCE + 0x000000100000) 520f48ad614SDennis Dalessandro #define CCE_MSIX_TABLE_UPPER (CCE + 0x000000100008) 521f48ad614SDennis Dalessandro #define CCE_MSIX_TABLE_UPPER_RESETCSR 0x0000000100000000ull 522f48ad614SDennis Dalessandro #define CCE_MSIX_VEC_CLR_WITHOUT_INT (CCE + 0x000000110400) 523f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL (CCE + 0x0000000000C0) 524f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 0x3ull 525f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 0 526f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 0xFull 527f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 2 528f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 8 529f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 9 530f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 0x1ull 531f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 12 532f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 0x7ull 533f48ad614SDennis Dalessandro #define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 13 534f48ad614SDennis Dalessandro #define CCE_REVISION (CCE + 0x000000000000) 535f48ad614SDennis Dalessandro #define CCE_REVISION2 (CCE + 0x000000000008) 536f48ad614SDennis Dalessandro #define CCE_REVISION2_HFI_ID_MASK 0x1ull 537f48ad614SDennis Dalessandro #define CCE_REVISION2_HFI_ID_SHIFT 0 538f48ad614SDennis Dalessandro #define CCE_REVISION2_IMPL_CODE_SHIFT 8 539f48ad614SDennis Dalessandro #define CCE_REVISION2_IMPL_REVISION_SHIFT 16 540f48ad614SDennis Dalessandro #define CCE_REVISION_BOARD_ID_LOWER_NIBBLE_MASK 0xFull 541f48ad614SDennis Dalessandro #define CCE_REVISION_BOARD_ID_LOWER_NIBBLE_SHIFT 32 542f48ad614SDennis Dalessandro #define CCE_REVISION_CHIP_REV_MAJOR_MASK 0xFFull 543f48ad614SDennis Dalessandro #define CCE_REVISION_CHIP_REV_MAJOR_SHIFT 8 544f48ad614SDennis Dalessandro #define CCE_REVISION_CHIP_REV_MINOR_MASK 0xFFull 545f48ad614SDennis Dalessandro #define CCE_REVISION_CHIP_REV_MINOR_SHIFT 0 546f48ad614SDennis Dalessandro #define CCE_REVISION_SW_MASK 0xFFull 547f48ad614SDennis Dalessandro #define CCE_REVISION_SW_SHIFT 24 548f48ad614SDennis Dalessandro #define CCE_SCRATCH (CCE + 0x000000000020) 549f48ad614SDennis Dalessandro #define CCE_STATUS (CCE + 0x000000000018) 550f48ad614SDennis Dalessandro #define CCE_STATUS_RXE_FROZE_SMASK 0x2ull 551f48ad614SDennis Dalessandro #define CCE_STATUS_RXE_PAUSED_SMASK 0x20ull 552f48ad614SDennis Dalessandro #define CCE_STATUS_SDMA_FROZE_SMASK 0x1ull 553f48ad614SDennis Dalessandro #define CCE_STATUS_SDMA_PAUSED_SMASK 0x10ull 554f48ad614SDennis Dalessandro #define CCE_STATUS_TXE_FROZE_SMASK 0x4ull 555f48ad614SDennis Dalessandro #define CCE_STATUS_TXE_PAUSED_SMASK 0x40ull 556f48ad614SDennis Dalessandro #define CCE_STATUS_TXE_PIO_FROZE_SMASK 0x8ull 557f48ad614SDennis Dalessandro #define CCE_STATUS_TXE_PIO_PAUSED_SMASK 0x80ull 558f48ad614SDennis Dalessandro #define MISC_CFG_FW_CTRL (MISC + 0x000000001000) 559f48ad614SDennis Dalessandro #define MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK 0x2ull 560f48ad614SDennis Dalessandro #define MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT 2 561f48ad614SDennis Dalessandro #define MISC_CFG_FW_CTRL_RSA_STATUS_SMASK 0xCull 562f48ad614SDennis Dalessandro #define MISC_CFG_RSA_CMD (MISC + 0x000000000A08) 563f48ad614SDennis Dalessandro #define MISC_CFG_RSA_MODULUS (MISC + 0x000000000400) 564f48ad614SDennis Dalessandro #define MISC_CFG_RSA_MU (MISC + 0x000000000A10) 565f48ad614SDennis Dalessandro #define MISC_CFG_RSA_R2 (MISC + 0x000000000000) 566f48ad614SDennis Dalessandro #define MISC_CFG_RSA_SIGNATURE (MISC + 0x000000000200) 567f48ad614SDennis Dalessandro #define MISC_CFG_SHA_PRELOAD (MISC + 0x000000000A00) 568f48ad614SDennis Dalessandro #define MISC_ERR_CLEAR (MISC + 0x000000002010) 569f48ad614SDennis Dalessandro #define MISC_ERR_MASK (MISC + 0x000000002008) 570f48ad614SDennis Dalessandro #define MISC_ERR_STATUS (MISC + 0x000000002000) 571f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_PLL_LOCK_FAIL_ERR_SMASK 0x1000ull 572f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_MBIST_FAIL_ERR_SMASK 0x800ull 573f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_INVALID_EEP_CMD_ERR_SMASK 0x400ull 574f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_EFUSE_DONE_PARITY_ERR_SMASK 0x200ull 575f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_EFUSE_WRITE_ERR_SMASK 0x100ull 576f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_EFUSE_READ_BAD_ADDR_ERR_SMASK 0x80ull 577f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_EFUSE_CSR_PARITY_ERR_SMASK 0x40ull 578f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK 0x20ull 579f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK 0x10ull 580f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_SBUS_WRITE_FAILED_ERR_SMASK 0x8ull 581f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull 582f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull 583f48ad614SDennis Dalessandro #define MISC_ERR_STATUS_MISC_CSR_PARITY_ERR_SMASK 0x1ull 584f48ad614SDennis Dalessandro #define PCI_CFG_MSIX0 (PCIE + 0x0000000000B0) 585f48ad614SDennis Dalessandro #define PCI_CFG_REG1 (PCIE + 0x000000000004) 586f48ad614SDennis Dalessandro #define PCI_CFG_REG11 (PCIE + 0x00000000002C) 587f48ad614SDennis Dalessandro #define PCIE_CFG_SPCIE1 (PCIE + 0x00000000014C) 588f48ad614SDennis Dalessandro #define PCIE_CFG_SPCIE2 (PCIE + 0x000000000150) 589f48ad614SDennis Dalessandro #define PCIE_CFG_TPH2 (PCIE + 0x000000000180) 590f48ad614SDennis Dalessandro #define RCV_ARRAY (RXE + 0x000000200000) 591f48ad614SDennis Dalessandro #define RCV_ARRAY_CNT (RXE + 0x000000000018) 592f48ad614SDennis Dalessandro #define RCV_ARRAY_RT_ADDR_MASK 0xFFFFFFFFFull 593f48ad614SDennis Dalessandro #define RCV_ARRAY_RT_ADDR_SHIFT 0 594f48ad614SDennis Dalessandro #define RCV_ARRAY_RT_BUF_SIZE_SHIFT 36 595f48ad614SDennis Dalessandro #define RCV_ARRAY_RT_WRITE_ENABLE_SMASK 0x8000000000000000ull 596f48ad614SDennis Dalessandro #define RCV_AVAIL_TIME_OUT (RXE + 0x000000100050) 597f48ad614SDennis Dalessandro #define RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK 0xFFull 598f48ad614SDennis Dalessandro #define RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT 0 599f48ad614SDennis Dalessandro #define RCV_BTH_QP (RXE + 0x000000000028) 600f48ad614SDennis Dalessandro #define RCV_BTH_QP_KDETH_QP_MASK 0xFFull 601f48ad614SDennis Dalessandro #define RCV_BTH_QP_KDETH_QP_SHIFT 16 602f48ad614SDennis Dalessandro #define RCV_BYPASS (RXE + 0x000000000038) 603dc2b2a91SMike Marciniszyn #define RCV_BYPASS_HDR_SIZE_SHIFT 16 604dc2b2a91SMike Marciniszyn #define RCV_BYPASS_HDR_SIZE_MASK 0x1Full 605dc2b2a91SMike Marciniszyn #define RCV_BYPASS_HDR_SIZE_SMASK 0x1F0000ull 606dc2b2a91SMike Marciniszyn #define RCV_BYPASS_BYPASS_CONTEXT_SHIFT 0 607dc2b2a91SMike Marciniszyn #define RCV_BYPASS_BYPASS_CONTEXT_MASK 0xFFull 608dc2b2a91SMike Marciniszyn #define RCV_BYPASS_BYPASS_CONTEXT_SMASK 0xFFull 609f48ad614SDennis Dalessandro #define RCV_CONTEXTS (RXE + 0x000000000010) 610f48ad614SDennis Dalessandro #define RCV_COUNTER_ARRAY32 (RXE + 0x000000000400) 611f48ad614SDennis Dalessandro #define RCV_COUNTER_ARRAY64 (RXE + 0x000000000500) 612f48ad614SDennis Dalessandro #define RCV_CTRL (RXE + 0x000000000000) 613f48ad614SDennis Dalessandro #define RCV_CTRL_RCV_BYPASS_ENABLE_SMASK 0x10ull 614f48ad614SDennis Dalessandro #define RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK 0x40ull 615f48ad614SDennis Dalessandro #define RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK 0x4ull 616f48ad614SDennis Dalessandro #define RCV_CTRL_RCV_PORT_ENABLE_SMASK 0x1ull 617f48ad614SDennis Dalessandro #define RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 0x2ull 618f48ad614SDennis Dalessandro #define RCV_CTRL_RCV_RSM_ENABLE_SMASK 0x20ull 619f48ad614SDennis Dalessandro #define RCV_CTRL_RX_RBUF_INIT_SMASK 0x200ull 620f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL (RXE + 0x000000100000) 621f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK 0x4ull 622f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK 0x8ull 623f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK 0x7ull 624f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT 8 625f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK 0x700ull 626f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_ENABLE_SMASK 0x1ull 627f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_INTR_AVAIL_SMASK 0x20ull 628f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK 0x2ull 629f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_TAIL_UPD_SMASK 0x40ull 630f48ad614SDennis Dalessandro #define RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK 0x10ull 631f48ad614SDennis Dalessandro #define RCV_CTXT_STATUS (RXE + 0x000000100008) 632f48ad614SDennis Dalessandro #define RCV_EGR_CTRL (RXE + 0x000000100010) 633f48ad614SDennis Dalessandro #define RCV_EGR_CTRL_EGR_BASE_INDEX_MASK 0x1FFFull 634f48ad614SDennis Dalessandro #define RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT 0 635f48ad614SDennis Dalessandro #define RCV_EGR_CTRL_EGR_CNT_MASK 0x1FFull 636f48ad614SDennis Dalessandro #define RCV_EGR_CTRL_EGR_CNT_SHIFT 32 637f48ad614SDennis Dalessandro #define RCV_EGR_INDEX_HEAD (RXE + 0x000000300018) 638f48ad614SDennis Dalessandro #define RCV_EGR_INDEX_HEAD_HEAD_MASK 0x7FFull 639f48ad614SDennis Dalessandro #define RCV_EGR_INDEX_HEAD_HEAD_SHIFT 0 640f48ad614SDennis Dalessandro #define RCV_ERR_CLEAR (RXE + 0x000000000070) 641f48ad614SDennis Dalessandro #define RCV_ERR_INFO (RXE + 0x000000000050) 642f48ad614SDennis Dalessandro #define RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SC_SMASK 0x1Full 643f48ad614SDennis Dalessandro #define RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK 0x20ull 644f48ad614SDennis Dalessandro #define RCV_ERR_MASK (RXE + 0x000000000068) 645f48ad614SDennis Dalessandro #define RCV_ERR_STATUS (RXE + 0x000000000060) 646f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK 0x8000000000000000ull 647f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_CSR_READ_BAD_ADDR_ERR_SMASK 0x2000000000000000ull 648f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_CSR_WRITE_BAD_ADDR_ERR_SMASK \ 649f48ad614SDennis Dalessandro 0x4000000000000000ull 650f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DC_INTF_PARITY_ERR_SMASK 0x2ull 651f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DC_SOP_EOP_PARITY_ERR_SMASK 0x200ull 652f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_CSR_COR_ERR_SMASK 0x1ull 653f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK 0x200000000000000ull 654f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK 0x1000000000000000ull 655f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_COR_ERR_SMASK \ 656f48ad614SDennis Dalessandro 0x40000000000000ull 657f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 658f48ad614SDennis Dalessandro 0x20000000000000ull 659f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 660f48ad614SDennis Dalessandro 0x800000000000000ull 661f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 662f48ad614SDennis Dalessandro 0x400000000000000ull 663f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_FLAG_COR_ERR_SMASK 0x800ull 664f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK 0x400ull 665f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_COR_ERR_SMASK 0x10000000000000ull 666f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK 0x8000000000000ull 667f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK 0x200000000000ull 668f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK 0x400000000000ull 669f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK 0x100000000000ull 670f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 671f48ad614SDennis Dalessandro 0x10000000000ull 672f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK 0x8000000000ull 673f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 674f48ad614SDennis Dalessandro 0x20000000000ull 675f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_COR_ERR_SMASK 0x80000000000ull 676f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK 0x40000000000ull 677f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK 0x40000000ull 678f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_COR_ERR_SMASK 0x100000ull 679f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK 0x80000ull 680f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK 0x400000ull 681f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK 0x10000000ull 682f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK 0x2000000ull 683f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 684f48ad614SDennis Dalessandro 0x200000ull 685f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK 0x800000ull 686f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 687f48ad614SDennis Dalessandro 0x8000000ull 688f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK 0x4000000ull 689f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK 0x1000000ull 690f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK 0x20000000ull 691f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_DATA_COR_ERR_SMASK 0x100000000000000ull 692f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK 0x80000000000000ull 693f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK 0x1000000000000ull 694f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK 0x800000000000ull 695f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_DESC_PART2_COR_ERR_SMASK 0x4000000000000ull 696f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK 0x2000000000000ull 697f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK 0x100000000ull 698f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK 0x800000000ull 699f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 700f48ad614SDennis Dalessandro 0x1000000000ull 701f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK 0x200000000ull 702f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK 0x400000000ull 703f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FREE_LIST_COR_ERR_SMASK 0x4000ull 704f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK 0x2000ull 705f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK 0x80000000ull 706f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_COR_ERR_SMASK 0x40000ull 707f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK 0x10000ull 708f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK 0x8000ull 709f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK 0x20000ull 710f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_COR_ERR_SMASK 0x4000000000ull 711f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK 0x2000000000ull 712f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK 0x100ull 713f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_DATA_COR_ERR_SMASK 0x20ull 714f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_DATA_UNC_ERR_SMASK 0x10ull 715f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK 0x1000ull 716f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_HDR_COR_ERR_SMASK 0x8ull 717f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_HDR_UNC_ERR_SMASK 0x4ull 718f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_COR_ERR_SMASK 0x80ull 719f48ad614SDennis Dalessandro #define RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK 0x40ull 720f48ad614SDennis Dalessandro #define RCV_HDR_ADDR (RXE + 0x000000100028) 721f48ad614SDennis Dalessandro #define RCV_HDR_CNT (RXE + 0x000000100030) 722f48ad614SDennis Dalessandro #define RCV_HDR_CNT_CNT_MASK 0x1FFull 723f48ad614SDennis Dalessandro #define RCV_HDR_CNT_CNT_SHIFT 0 724f48ad614SDennis Dalessandro #define RCV_HDR_ENT_SIZE (RXE + 0x000000100038) 725f48ad614SDennis Dalessandro #define RCV_HDR_ENT_SIZE_ENT_SIZE_MASK 0x7ull 726f48ad614SDennis Dalessandro #define RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT 0 727f48ad614SDennis Dalessandro #define RCV_HDR_HEAD (RXE + 0x000000300008) 728f48ad614SDennis Dalessandro #define RCV_HDR_HEAD_COUNTER_MASK 0xFFull 729f48ad614SDennis Dalessandro #define RCV_HDR_HEAD_COUNTER_SHIFT 32 730f48ad614SDennis Dalessandro #define RCV_HDR_HEAD_HEAD_MASK 0x7FFFFull 731f48ad614SDennis Dalessandro #define RCV_HDR_HEAD_HEAD_SHIFT 0 732f48ad614SDennis Dalessandro #define RCV_HDR_HEAD_HEAD_SMASK 0x7FFFFull 733f48ad614SDennis Dalessandro #define RCV_HDR_OVFL_CNT (RXE + 0x000000100058) 734f48ad614SDennis Dalessandro #define RCV_HDR_SIZE (RXE + 0x000000100040) 735f48ad614SDennis Dalessandro #define RCV_HDR_SIZE_HDR_SIZE_MASK 0x1Full 736f48ad614SDennis Dalessandro #define RCV_HDR_SIZE_HDR_SIZE_SHIFT 0 737f48ad614SDennis Dalessandro #define RCV_HDR_TAIL (RXE + 0x000000300000) 738f48ad614SDennis Dalessandro #define RCV_HDR_TAIL_ADDR (RXE + 0x000000100048) 739f48ad614SDennis Dalessandro #define RCV_KEY_CTRL (RXE + 0x000000100020) 740f48ad614SDennis Dalessandro #define RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK 0x200000000ull 741f48ad614SDennis Dalessandro #define RCV_KEY_CTRL_JOB_KEY_VALUE_MASK 0xFFFFull 742f48ad614SDennis Dalessandro #define RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT 0 743f48ad614SDennis Dalessandro #define RCV_MULTICAST (RXE + 0x000000000030) 744f48ad614SDennis Dalessandro #define RCV_PARTITION_KEY (RXE + 0x000000000200) 745f48ad614SDennis Dalessandro #define RCV_PARTITION_KEY_PARTITION_KEY_A_MASK 0xFFFFull 746f48ad614SDennis Dalessandro #define RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT 16 747f48ad614SDennis Dalessandro #define RCV_QP_MAP_TABLE (RXE + 0x000000000100) 748f48ad614SDennis Dalessandro #define RCV_RSM_CFG (RXE + 0x000000000600) 749f48ad614SDennis Dalessandro #define RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_MASK 0x1ull 750f48ad614SDennis Dalessandro #define RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_SHIFT 0 751f48ad614SDennis Dalessandro #define RCV_RSM_CFG_PACKET_TYPE_SHIFT 60 752f48ad614SDennis Dalessandro #define RCV_RSM_CFG_OFFSET_SHIFT 32 753f48ad614SDennis Dalessandro #define RCV_RSM_MAP_TABLE (RXE + 0x000000000900) 754f48ad614SDennis Dalessandro #define RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 0xFFull 755f48ad614SDennis Dalessandro #define RCV_RSM_MATCH (RXE + 0x000000000800) 756f48ad614SDennis Dalessandro #define RCV_RSM_MATCH_MASK1_SHIFT 0 757f48ad614SDennis Dalessandro #define RCV_RSM_MATCH_MASK2_SHIFT 16 758f48ad614SDennis Dalessandro #define RCV_RSM_MATCH_VALUE1_SHIFT 8 759f48ad614SDennis Dalessandro #define RCV_RSM_MATCH_VALUE2_SHIFT 24 760f48ad614SDennis Dalessandro #define RCV_RSM_SELECT (RXE + 0x000000000700) 761f48ad614SDennis Dalessandro #define RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT 0 762f48ad614SDennis Dalessandro #define RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT 16 763f48ad614SDennis Dalessandro #define RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT 32 764f48ad614SDennis Dalessandro #define RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT 44 765f48ad614SDennis Dalessandro #define RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT 48 766f48ad614SDennis Dalessandro #define RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT 60 767f48ad614SDennis Dalessandro #define RCV_STATUS (RXE + 0x000000000008) 768f48ad614SDennis Dalessandro #define RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK 0x1ull 769f48ad614SDennis Dalessandro #define RCV_STATUS_RX_RBUF_INIT_DONE_SMASK 0x200ull 770f48ad614SDennis Dalessandro #define RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 0x40ull 771f48ad614SDennis Dalessandro #define RCV_TID_CTRL (RXE + 0x000000100018) 772f48ad614SDennis Dalessandro #define RCV_TID_CTRL_TID_BASE_INDEX_MASK 0x1FFFull 773f48ad614SDennis Dalessandro #define RCV_TID_CTRL_TID_BASE_INDEX_SHIFT 0 774f48ad614SDennis Dalessandro #define RCV_TID_CTRL_TID_PAIR_CNT_MASK 0x1FFull 775f48ad614SDennis Dalessandro #define RCV_TID_CTRL_TID_PAIR_CNT_SHIFT 32 776f48ad614SDennis Dalessandro #define RCV_TID_FLOW_TABLE (RXE + 0x000000300800) 777f48ad614SDennis Dalessandro #define RCV_VL15 (RXE + 0x000000000048) 778f48ad614SDennis Dalessandro #define SEND_BTH_QP (TXE + 0x0000000000A0) 779f48ad614SDennis Dalessandro #define SEND_BTH_QP_KDETH_QP_MASK 0xFFull 780f48ad614SDennis Dalessandro #define SEND_BTH_QP_KDETH_QP_SHIFT 16 781f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS (TXE + 0x000000000510) 782f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK \ 783f48ad614SDennis Dalessandro 0x1000000000000ull 784f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK \ 785f48ad614SDennis Dalessandro 0x8000000000000000ull 786f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK \ 787f48ad614SDennis Dalessandro 0x2000000000000ull 788f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK \ 789f48ad614SDennis Dalessandro 0x4000000000000ull 790f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK \ 791f48ad614SDennis Dalessandro 0x8000000000000ull 792f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK \ 793f48ad614SDennis Dalessandro 0x10000000000000ull 794f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK \ 795f48ad614SDennis Dalessandro 0x20000000000000ull 796f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK \ 797f48ad614SDennis Dalessandro 0x40000000000000ull 798f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK \ 799f48ad614SDennis Dalessandro 0x80000000000000ull 800f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL (TXE + 0x000000000600) 801f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL15 (TXE + 0x000000000678) 802f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT 0 803f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK 0xFFFFull 804f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT 0 805f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK 0xFFFFull 806f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK 0xFFFFull 807f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT 16 808f48ad614SDennis Dalessandro #define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK 0xFFFF0000ull 809f48ad614SDennis Dalessandro #define SEND_CM_CTRL (TXE + 0x000000000500) 810f48ad614SDennis Dalessandro #define SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK 0x8ull 811f48ad614SDennis Dalessandro #define SEND_CM_CTRL_RESETCSR 0x0000000000000020ull 812f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT (TXE + 0x000000000508) 813b3e6b4bdSByczkowski, Jakub #define SEND_CM_GLOBAL_CREDIT_AU_MASK 0x7ull 814f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_AU_SHIFT 16 815b3e6b4bdSByczkowski, Jakub #define SEND_CM_GLOBAL_CREDIT_AU_SMASK 0x70000ull 816f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_RESETCSR 0x0000094000030000ull 817f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK 0xFFFFull 818f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT 0 819f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK 0xFFFFull 820f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK 0xFFFFull 821f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT 32 822f48ad614SDennis Dalessandro #define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK 0xFFFF00000000ull 823f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE0_TO3 (TXE + 0x000000000520) 824f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT 0 825f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT 16 826f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT 32 827f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT 48 828f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE4_TO7 (TXE + 0x000000000528) 829f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT 0 830f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT 16 831f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT 32 832f48ad614SDennis Dalessandro #define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT 48 833f48ad614SDennis Dalessandro #define SEND_CM_REMOTE_AU_TABLE0_TO3 (TXE + 0x000000000530) 834f48ad614SDennis Dalessandro #define SEND_CM_REMOTE_AU_TABLE4_TO7 (TXE + 0x000000000538) 835f48ad614SDennis Dalessandro #define SEND_CM_TIMER_CTRL (TXE + 0x000000000518) 836f48ad614SDennis Dalessandro #define SEND_CONTEXTS (TXE + 0x000000000010) 837f48ad614SDennis Dalessandro #define SEND_CONTEXT_SET_CTRL (TXE + 0x000000000200) 838f48ad614SDennis Dalessandro #define SEND_COUNTER_ARRAY32 (TXE + 0x000000000300) 839f48ad614SDennis Dalessandro #define SEND_COUNTER_ARRAY64 (TXE + 0x000000000400) 840f48ad614SDennis Dalessandro #define SEND_CTRL (TXE + 0x000000000000) 841f48ad614SDennis Dalessandro #define SEND_CTRL_CM_RESET_SMASK 0x4ull 842f48ad614SDennis Dalessandro #define SEND_CTRL_SEND_ENABLE_SMASK 0x1ull 843e04951ebSMichael J. Ruhl #define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3 844e04951ebSMichael J. Ruhl #define SEND_CTRL_UNSUPPORTED_VL_MASK 0xFFull 845e04951ebSMichael J. Ruhl #define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \ 846e04951ebSMichael J. Ruhl << SEND_CTRL_UNSUPPORTED_VL_SHIFT) 847f48ad614SDennis Dalessandro #define SEND_CTRL_VL_ARBITER_ENABLE_SMASK 0x2ull 848f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE (TXE + 0x000000100080) 849f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull 850f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK 0x1ull 851f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 0x4ull 852f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 0x20ull 853f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK 0x8ull 854f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 0x10ull 855f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 0x40ull 856f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 0x2ull 857f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 0x20000ull 858f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK \ 859f48ad614SDennis Dalessandro 0x200000ull 860f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK 0x800ull 861f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK 0x400ull 862f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK 0x1000ull 863f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK 0x2000ull 864f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK \ 865f48ad614SDennis Dalessandro 0x100000ull 866f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 0x10000ull 867f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 0x200ull 868f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 0x100ull 869f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK \ 870f48ad614SDennis Dalessandro 0x80000ull 871f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK \ 872f48ad614SDennis Dalessandro 0x40000ull 873f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK \ 874f48ad614SDennis Dalessandro 0x8000ull 875f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK \ 876f48ad614SDennis Dalessandro 0x4000ull 877f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_JOB_KEY (TXE + 0x000000100090) 878f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK 0x100000000ull 879f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK 0xFFFF0000ull 880f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK 0xFFFFull 881f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT 0 882f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_OPCODE (TXE + 0x0000001000A8) 883f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_OPCODE_MASK_SHIFT 8 884f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT 0 885f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_PARTITION_KEY (TXE + 0x000000100098) 886f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK 0xFFFFull 887f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT 0 888f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_SLID (TXE + 0x0000001000A0) 889f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_SLID_MASK_MASK 0xFFFFull 890f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_SLID_MASK_SHIFT 16 891f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_SLID_VALUE_MASK 0xFFFFull 892f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_SLID_VALUE_SHIFT 0 893f48ad614SDennis Dalessandro #define SEND_CTXT_CHECK_VL (TXE + 0x000000100088) 894f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_CTRL (TXE + 0x000000100010) 895f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_CTRL_CREDIT_INTR_SMASK 0x20000ull 896f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_CTRL_EARLY_RETURN_SMASK 0x10000ull 897f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_MASK 0x7FFull 898f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SHIFT 0 899f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SMASK 0x7FFull 900937488a8SKaike Wan #define SEND_CTXT_CREDIT_STATUS (TXE + 0x000000100018) 901937488a8SKaike Wan #define SEND_CTXT_CREDIT_STATUS_CURRENT_FREE_COUNTER_MASK 0x7FFull 902937488a8SKaike Wan #define SEND_CTXT_CREDIT_STATUS_CURRENT_FREE_COUNTER_SHIFT 32 903937488a8SKaike Wan #define SEND_CTXT_CREDIT_STATUS_LAST_RETURNED_COUNTER_SMASK 0x7FFull 904f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_FORCE (TXE + 0x000000100028) 905f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_FORCE_FORCE_RETURN_SMASK 0x1ull 906f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_RETURN_ADDR (TXE + 0x000000100020) 907f48ad614SDennis Dalessandro #define SEND_CTXT_CREDIT_RETURN_ADDR_ADDRESS_SMASK 0xFFFFFFFFFFC0ull 908f48ad614SDennis Dalessandro #define SEND_CTXT_CTRL (TXE + 0x000000100000) 909f48ad614SDennis Dalessandro #define SEND_CTXT_CTRL_CTXT_BASE_MASK 0x3FFFull 910f48ad614SDennis Dalessandro #define SEND_CTXT_CTRL_CTXT_BASE_SHIFT 32 911f48ad614SDennis Dalessandro #define SEND_CTXT_CTRL_CTXT_DEPTH_MASK 0x7FFull 912f48ad614SDennis Dalessandro #define SEND_CTXT_CTRL_CTXT_DEPTH_SHIFT 48 913f48ad614SDennis Dalessandro #define SEND_CTXT_CTRL_CTXT_ENABLE_SMASK 0x1ull 914f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_CLEAR (TXE + 0x000000100050) 915f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_MASK (TXE + 0x000000100048) 916f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_STATUS (TXE + 0x000000100040) 917f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK 0x2ull 918f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK 0x1ull 919f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK 0x4ull 920f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK 0x10ull 921f48ad614SDennis Dalessandro #define SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK 0x8ull 922f48ad614SDennis Dalessandro #define SEND_CTXT_STATUS (TXE + 0x000000100008) 923f48ad614SDennis Dalessandro #define SEND_CTXT_STATUS_CTXT_HALTED_SMASK 0x1ull 924f48ad614SDennis Dalessandro #define SEND_DMA_BASE_ADDR (TXE + 0x000000200010) 925f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE (TXE + 0x000000200080) 926f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull 927f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK 0x1ull 928f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 0x4ull 929f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 0x20ull 930f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK 0x8ull 931f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 0x10ull 932f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 0x40ull 933f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 0x2ull 934f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 0x20000ull 935f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 0x200000ull 936f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK \ 937f48ad614SDennis Dalessandro 0x100000ull 938f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 0x200ull 939f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 0x100ull 940f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK \ 941f48ad614SDennis Dalessandro 0x80000ull 942f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 0x40000ull 943f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK \ 944f48ad614SDennis Dalessandro 0x8000ull 945f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 0x4000ull 946f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_JOB_KEY (TXE + 0x000000200090) 947f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_OPCODE (TXE + 0x0000002000A8) 948f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_PARTITION_KEY (TXE + 0x000000200098) 949f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_SLID (TXE + 0x0000002000A0) 950f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_SLID_MASK_MASK 0xFFFFull 951f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_SLID_MASK_SHIFT 16 952f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_SLID_VALUE_MASK 0xFFFFull 953f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_SLID_VALUE_SHIFT 0 954f48ad614SDennis Dalessandro #define SEND_DMA_CHECK_VL (TXE + 0x000000200088) 955f48ad614SDennis Dalessandro #define SEND_DMA_CTRL (TXE + 0x000000200000) 956f48ad614SDennis Dalessandro #define SEND_DMA_CTRL_SDMA_CLEANUP_SMASK 0x4ull 957f48ad614SDennis Dalessandro #define SEND_DMA_CTRL_SDMA_ENABLE_SMASK 0x1ull 958f48ad614SDennis Dalessandro #define SEND_DMA_CTRL_SDMA_HALT_SMASK 0x2ull 959f48ad614SDennis Dalessandro #define SEND_DMA_CTRL_SDMA_INT_ENABLE_SMASK 0x8ull 960f48ad614SDennis Dalessandro #define SEND_DMA_DESC_CNT (TXE + 0x000000200050) 961f48ad614SDennis Dalessandro #define SEND_DMA_DESC_CNT_CNT_MASK 0xFFFFull 962f48ad614SDennis Dalessandro #define SEND_DMA_DESC_CNT_CNT_SHIFT 0 963f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_CLEAR (TXE + 0x000000200070) 964f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK 0x1ull 965f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT 18 966f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_MASK (TXE + 0x000000200068) 967f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS (TXE + 0x000000200060) 968f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK 0x8000ull 969f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK 0x4000ull 970f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK 0x10ull 971f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK 0x2ull 972f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK 0x40ull 973f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK 0x800ull 974f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK 0x1000ull 975f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK \ 976f48ad614SDennis Dalessandro 0x40000ull 977f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK 0x400ull 978f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK \ 979f48ad614SDennis Dalessandro 0x20000ull 980f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK 0x80ull 981f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK 0x20ull 982f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK \ 983f48ad614SDennis Dalessandro 0x100ull 984f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK \ 985f48ad614SDennis Dalessandro 0x10000ull 986f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK 0x8ull 987f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK 0x2000ull 988f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK 0x4ull 989f48ad614SDennis Dalessandro #define SEND_DMA_ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK 0x1ull 990f48ad614SDennis Dalessandro #define SEND_DMA_ENGINES (TXE + 0x000000000018) 991f48ad614SDennis Dalessandro #define SEND_DMA_ERR_CLEAR (TXE + 0x000000000070) 992f48ad614SDennis Dalessandro #define SEND_DMA_ERR_MASK (TXE + 0x000000000068) 993f48ad614SDennis Dalessandro #define SEND_DMA_ERR_STATUS (TXE + 0x000000000060) 994f48ad614SDennis Dalessandro #define SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK 0x2ull 995f48ad614SDennis Dalessandro #define SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK 0x8ull 996f48ad614SDennis Dalessandro #define SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK 0x4ull 997f48ad614SDennis Dalessandro #define SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK 0x1ull 998f48ad614SDennis Dalessandro #define SEND_DMA_HEAD (TXE + 0x000000200028) 999f48ad614SDennis Dalessandro #define SEND_DMA_HEAD_ADDR (TXE + 0x000000200030) 1000f48ad614SDennis Dalessandro #define SEND_DMA_LEN_GEN (TXE + 0x000000200018) 1001f48ad614SDennis Dalessandro #define SEND_DMA_LEN_GEN_GENERATION_SHIFT 16 1002f48ad614SDennis Dalessandro #define SEND_DMA_LEN_GEN_LENGTH_SHIFT 6 1003f48ad614SDennis Dalessandro #define SEND_DMA_MEMORY (TXE + 0x0000002000B0) 1004f48ad614SDennis Dalessandro #define SEND_DMA_MEMORY_SDMA_MEMORY_CNT_SHIFT 16 1005f48ad614SDennis Dalessandro #define SEND_DMA_MEMORY_SDMA_MEMORY_INDEX_SHIFT 0 1006f48ad614SDennis Dalessandro #define SEND_DMA_MEM_SIZE (TXE + 0x000000000028) 1007f48ad614SDennis Dalessandro #define SEND_DMA_PRIORITY_THLD (TXE + 0x000000200038) 1008f48ad614SDennis Dalessandro #define SEND_DMA_RELOAD_CNT (TXE + 0x000000200048) 1009f48ad614SDennis Dalessandro #define SEND_DMA_STATUS (TXE + 0x000000200008) 1010f48ad614SDennis Dalessandro #define SEND_DMA_STATUS_ENG_CLEANED_UP_SMASK 0x200000000000000ull 1011f48ad614SDennis Dalessandro #define SEND_DMA_STATUS_ENG_HALTED_SMASK 0x100000000000000ull 1012f48ad614SDennis Dalessandro #define SEND_DMA_TAIL (TXE + 0x000000200020) 1013f48ad614SDennis Dalessandro #define SEND_EGRESS_CTXT_STATUS (TXE + 0x000000000800) 1014f48ad614SDennis Dalessandro #define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK 0x10000ull 1015f48ad614SDennis Dalessandro #define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT 0 1016f48ad614SDennis Dalessandro #define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK \ 1017f48ad614SDennis Dalessandro 0x3FFFull 1018f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_CLEAR (TXE + 0x000000000090) 1019f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO (TXE + 0x000000000F00) 1020f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_BAD_PKT_LEN_ERR_SMASK 0x20000ull 1021f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_BYPASS_ERR_SMASK 0x800ull 1022f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_GRH_ERR_SMASK 0x400ull 1023f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_JOB_KEY_ERR_SMASK 0x4ull 1024f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_KDETH_PACKETS_ERR_SMASK 0x1000ull 1025f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_NON_KDETH_PACKETS_ERR_SMASK 0x2000ull 1026f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_OPCODE_ERR_SMASK 0x20ull 1027f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_PARTITION_KEY_ERR_SMASK 0x8ull 1028f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_PBC_STATIC_RATE_CONTROL_ERR_SMASK 0x100000ull 1029f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_PBC_TEST_ERR_SMASK 0x10000ull 1030f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_RAW_ERR_SMASK 0x100ull 1031f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_RAW_IPV6_ERR_SMASK 0x200ull 1032f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_SLID_ERR_SMASK 0x10ull 1033f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_TOO_LONG_BYPASS_PACKETS_ERR_SMASK 0x80000ull 1034f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK 0x40000ull 1035f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_TOO_SMALL_BYPASS_PACKETS_ERR_SMASK 0x8000ull 1036f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_TOO_SMALL_IB_PACKETS_ERR_SMASK 0x4000ull 1037f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_VL_ERR_SMASK 0x2ull 1038f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK 0x40ull 1039f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_MASK (TXE + 0x000000000088) 1040f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_SOURCE (TXE + 0x000000000F08) 1041f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS (TXE + 0x000000000080) 1042f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_CONFIG_PARITY_ERR_SMASK 0x8000ull 1043f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_CREDIT_OVERRUN_ERR_SMASK \ 1044f48ad614SDennis Dalessandro 0x200000000000000ull 1045f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_PARITY_ERR_SMASK \ 1046f48ad614SDennis Dalessandro 0x20000000000ull 1047f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK \ 1048f48ad614SDennis Dalessandro 0x800000000000ull 1049f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_COR_ERR_SMASK \ 1050f48ad614SDennis Dalessandro 0x2000000000000000ull 1051f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_UNC_ERR_SMASK \ 1052f48ad614SDennis Dalessandro 0x200000000000ull 1053f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR_SMASK \ 1054f48ad614SDennis Dalessandro 0x8ull 1055f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_HCRC_INSERTION_ERR_SMASK \ 1056f48ad614SDennis Dalessandro 0x400000000000ull 1057f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_ILLEGAL_VL_ERR_SMASK 0x1000ull 1058f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_INCORRECT_LINK_STATE_ERR_SMASK 0x20ull 1059f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_CSR_PARITY_ERR_SMASK 0x2000ull 1060f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO0_COR_ERR_SMASK \ 1061f48ad614SDennis Dalessandro 0x1000000000000ull 1062f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR_SMASK \ 1063f48ad614SDennis Dalessandro 0x100000000ull 1064f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO1_COR_ERR_SMASK \ 1065f48ad614SDennis Dalessandro 0x2000000000000ull 1066f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR_SMASK \ 1067f48ad614SDennis Dalessandro 0x200000000ull 1068f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO2_COR_ERR_SMASK \ 1069f48ad614SDennis Dalessandro 0x4000000000000ull 1070f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR_SMASK \ 1071f48ad614SDennis Dalessandro 0x400000000ull 1072f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO3_COR_ERR_SMASK \ 1073f48ad614SDennis Dalessandro 0x8000000000000ull 1074f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR_SMASK \ 1075f48ad614SDennis Dalessandro 0x800000000ull 1076f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO4_COR_ERR_SMASK \ 1077f48ad614SDennis Dalessandro 0x10000000000000ull 1078f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR_SMASK \ 1079f48ad614SDennis Dalessandro 0x1000000000ull 1080f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO5_COR_ERR_SMASK \ 1081f48ad614SDennis Dalessandro 0x20000000000000ull 1082f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR_SMASK \ 1083f48ad614SDennis Dalessandro 0x2000000000ull 1084f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO6_COR_ERR_SMASK \ 1085f48ad614SDennis Dalessandro 0x40000000000000ull 1086f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR_SMASK \ 1087f48ad614SDennis Dalessandro 0x4000000000ull 1088f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO7_COR_ERR_SMASK \ 1089f48ad614SDennis Dalessandro 0x80000000000000ull 1090f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR_SMASK \ 1091f48ad614SDennis Dalessandro 0x8000000000ull 1092f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO8_COR_ERR_SMASK \ 1093f48ad614SDennis Dalessandro 0x100000000000000ull 1094f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR_SMASK \ 1095f48ad614SDennis Dalessandro 0x10000000000ull 1096f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_LINKDOWN_ERR_SMASK 0x10ull 1097f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_PIO_LAUNCH_INTF_PARITY_ERR_SMASK 0x80ull 1098f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_PKT_INTEGRITY_MEM_COR_ERR_SMASK 0x1ull 1099f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_PKT_INTEGRITY_MEM_UNC_ERR_SMASK 0x2ull 1100f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_COR_ERR_SMASK \ 1101f48ad614SDennis Dalessandro 0x1000000000000000ull 1102f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_CSR_UNC_ERR_SMASK \ 1103f48ad614SDennis Dalessandro 0x8000000000000000ull 1104f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_UNC_ERR_SMASK \ 1105f48ad614SDennis Dalessandro 0x100000000000ull 1106f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_COR_ERR_SMASK \ 1107f48ad614SDennis Dalessandro 0x800000000000000ull 1108f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_CSR_UNC_ERR_SMASK \ 1109f48ad614SDennis Dalessandro 0x4000000000000000ull 1110f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_UNC_ERR_SMASK \ 1111f48ad614SDennis Dalessandro 0x80000000000ull 1112f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SB_HDR_COR_ERR_SMASK 0x400000000000000ull 1113f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SB_HDR_UNC_ERR_SMASK 0x40000000000ull 1114f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SBRD_CTL_CSR_PARITY_ERR_SMASK 0x4000ull 1115f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR_SMASK \ 1116f48ad614SDennis Dalessandro 0x800ull 1117f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA0_DISALLOWED_PACKET_ERR_SMASK \ 1118f48ad614SDennis Dalessandro 0x10000ull 1119f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA10_DISALLOWED_PACKET_ERR_SMASK \ 1120f48ad614SDennis Dalessandro 0x4000000ull 1121f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA11_DISALLOWED_PACKET_ERR_SMASK \ 1122f48ad614SDennis Dalessandro 0x8000000ull 1123f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA12_DISALLOWED_PACKET_ERR_SMASK \ 1124f48ad614SDennis Dalessandro 0x10000000ull 1125f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA13_DISALLOWED_PACKET_ERR_SMASK \ 1126f48ad614SDennis Dalessandro 0x20000000ull 1127f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA14_DISALLOWED_PACKET_ERR_SMASK \ 1128f48ad614SDennis Dalessandro 0x40000000ull 1129f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA15_DISALLOWED_PACKET_ERR_SMASK \ 1130f48ad614SDennis Dalessandro 0x80000000ull 1131f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA1_DISALLOWED_PACKET_ERR_SMASK \ 1132f48ad614SDennis Dalessandro 0x20000ull 1133f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA2_DISALLOWED_PACKET_ERR_SMASK \ 1134f48ad614SDennis Dalessandro 0x40000ull 1135f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA3_DISALLOWED_PACKET_ERR_SMASK \ 1136f48ad614SDennis Dalessandro 0x80000ull 1137f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA4_DISALLOWED_PACKET_ERR_SMASK \ 1138f48ad614SDennis Dalessandro 0x100000ull 1139f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA5_DISALLOWED_PACKET_ERR_SMASK \ 1140f48ad614SDennis Dalessandro 0x200000ull 1141f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA6_DISALLOWED_PACKET_ERR_SMASK \ 1142f48ad614SDennis Dalessandro 0x400000ull 1143f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA7_DISALLOWED_PACKET_ERR_SMASK \ 1144f48ad614SDennis Dalessandro 0x800000ull 1145f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA8_DISALLOWED_PACKET_ERR_SMASK \ 1146f48ad614SDennis Dalessandro 0x1000000ull 1147f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA9_DISALLOWED_PACKET_ERR_SMASK \ 1148f48ad614SDennis Dalessandro 0x2000000ull 1149f48ad614SDennis Dalessandro #define SEND_EGRESS_ERR_STATUS_TX_SDMA_LAUNCH_INTF_PARITY_ERR_SMASK \ 1150f48ad614SDennis Dalessandro 0x100ull 1151f48ad614SDennis Dalessandro #define SEND_EGRESS_SEND_DMA_STATUS (TXE + 0x000000000E00) 1152f48ad614SDennis Dalessandro #define SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT 0 1153f48ad614SDennis Dalessandro #define SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \ 1154f48ad614SDennis Dalessandro 0x3FFFull 1155f48ad614SDennis Dalessandro #define SEND_ERR_CLEAR (TXE + 0x0000000000F0) 1156f48ad614SDennis Dalessandro #define SEND_ERR_MASK (TXE + 0x0000000000E8) 1157f48ad614SDennis Dalessandro #define SEND_ERR_STATUS (TXE + 0x0000000000E0) 1158f48ad614SDennis Dalessandro #define SEND_ERR_STATUS_SEND_CSR_PARITY_ERR_SMASK 0x1ull 1159f48ad614SDennis Dalessandro #define SEND_ERR_STATUS_SEND_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull 1160f48ad614SDennis Dalessandro #define SEND_ERR_STATUS_SEND_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull 1161f48ad614SDennis Dalessandro #define SEND_HIGH_PRIORITY_LIMIT (TXE + 0x000000000030) 1162f48ad614SDennis Dalessandro #define SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK 0x3FFFull 1163f48ad614SDennis Dalessandro #define SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT 0 1164f48ad614SDennis Dalessandro #define SEND_HIGH_PRIORITY_LIST (TXE + 0x000000000180) 1165f48ad614SDennis Dalessandro #define SEND_LEN_CHECK0 (TXE + 0x0000000000D0) 1166f48ad614SDennis Dalessandro #define SEND_LEN_CHECK0_LEN_VL0_MASK 0xFFFull 1167f48ad614SDennis Dalessandro #define SEND_LEN_CHECK0_LEN_VL1_SHIFT 12 1168f48ad614SDennis Dalessandro #define SEND_LEN_CHECK1 (TXE + 0x0000000000D8) 1169f48ad614SDennis Dalessandro #define SEND_LEN_CHECK1_LEN_VL15_MASK 0xFFFull 1170f48ad614SDennis Dalessandro #define SEND_LEN_CHECK1_LEN_VL15_SHIFT 48 1171f48ad614SDennis Dalessandro #define SEND_LEN_CHECK1_LEN_VL4_MASK 0xFFFull 1172f48ad614SDennis Dalessandro #define SEND_LEN_CHECK1_LEN_VL5_SHIFT 12 1173f48ad614SDennis Dalessandro #define SEND_LOW_PRIORITY_LIST (TXE + 0x000000000100) 1174f48ad614SDennis Dalessandro #define SEND_LOW_PRIORITY_LIST_VL_MASK 0x7ull 1175f48ad614SDennis Dalessandro #define SEND_LOW_PRIORITY_LIST_VL_SHIFT 16 1176f48ad614SDennis Dalessandro #define SEND_LOW_PRIORITY_LIST_WEIGHT_MASK 0xFFull 1177f48ad614SDennis Dalessandro #define SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT 0 1178f48ad614SDennis Dalessandro #define SEND_PIO_ERR_CLEAR (TXE + 0x000000000050) 1179f48ad614SDennis Dalessandro #define SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK 0x20000ull 1180f48ad614SDennis Dalessandro #define SEND_PIO_ERR_MASK (TXE + 0x000000000048) 1181f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS (TXE + 0x000000000040) 1182f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 1183f48ad614SDennis Dalessandro 0x1000000ull 1184f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK 0x8000ull 1185f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK 0x4ull 1186f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 1187f48ad614SDennis Dalessandro 0x100000000ull 1188f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK 0x100000ull 1189f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK 0x80000ull 1190f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK 0x20000ull 1191f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 1192f48ad614SDennis Dalessandro 0x200000000ull 1193f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK 0x20ull 1194f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 1195f48ad614SDennis Dalessandro 0x400000000ull 1196f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK 0x40ull 1197f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK \ 1198f48ad614SDennis Dalessandro 0x800000000ull 1199f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK 0x200ull 1200f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK 0x40000ull 1201f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK 0x10000000ull 1202f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK 0x10000ull 1203f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK 0x20000000ull 1204f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK 0x8ull 1205f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK 0x10ull 1206f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK 0x80ull 1207f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 1208f48ad614SDennis Dalessandro 0x100ull 1209f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK 0x400ull 1210f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK 0x400000ull 1211f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK 0x8000000ull 1212f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK 0x4000000ull 1213f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK 0x2000000ull 1214f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK 0x2000ull 1215f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK 0x800ull 1216f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK 0x4000ull 1217f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK 0x1000ull 1218f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK 0x2ull 1219f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK 0x1ull 1220f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK 0x200000ull 1221f48ad614SDennis Dalessandro #define SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK 0x800000ull 1222f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT (TXE + 0x000000000038) 1223f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK 0x1ull 1224f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK 0xFFull 1225f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT 8 1226f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK 0x8ull 1227f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK 0x4ull 1228f48ad614SDennis Dalessandro #define SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK 0x2ull 1229f48ad614SDennis Dalessandro #define SEND_PIO_MEM_SIZE (TXE + 0x000000000020) 1230f48ad614SDennis Dalessandro #define SEND_SC2VLT0 (TXE + 0x0000000000B0) 1231f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC0_SHIFT 0 1232f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC1_SHIFT 8 1233f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC2_SHIFT 16 1234f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC3_SHIFT 24 1235f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC4_SHIFT 32 1236f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC5_SHIFT 40 1237f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC6_SHIFT 48 1238f48ad614SDennis Dalessandro #define SEND_SC2VLT0_SC7_SHIFT 56 1239f48ad614SDennis Dalessandro #define SEND_SC2VLT1 (TXE + 0x0000000000B8) 1240f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC10_SHIFT 16 1241f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC11_SHIFT 24 1242f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC12_SHIFT 32 1243f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC13_SHIFT 40 1244f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC14_SHIFT 48 1245f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC15_SHIFT 56 1246f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC8_SHIFT 0 1247f48ad614SDennis Dalessandro #define SEND_SC2VLT1_SC9_SHIFT 8 1248f48ad614SDennis Dalessandro #define SEND_SC2VLT2 (TXE + 0x0000000000C0) 1249f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC16_SHIFT 0 1250f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC17_SHIFT 8 1251f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC18_SHIFT 16 1252f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC19_SHIFT 24 1253f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC20_SHIFT 32 1254f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC21_SHIFT 40 1255f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC22_SHIFT 48 1256f48ad614SDennis Dalessandro #define SEND_SC2VLT2_SC23_SHIFT 56 1257f48ad614SDennis Dalessandro #define SEND_SC2VLT3 (TXE + 0x0000000000C8) 1258f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC24_SHIFT 0 1259f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC25_SHIFT 8 1260f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC26_SHIFT 16 1261f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC27_SHIFT 24 1262f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC28_SHIFT 32 1263f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC29_SHIFT 40 1264f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC30_SHIFT 48 1265f48ad614SDennis Dalessandro #define SEND_SC2VLT3_SC31_SHIFT 56 1266f48ad614SDennis Dalessandro #define SEND_STATIC_RATE_CONTROL (TXE + 0x0000000000A8) 1267f48ad614SDennis Dalessandro #define SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT 0 1268f48ad614SDennis Dalessandro #define SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK 0xFFFFull 1269f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL2 (PCIE + 0x000000000708) 1270f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL3 (PCIE + 0x00000000070C) 1271f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT 27 1272f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK 0x38000000 1273f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL102 (PCIE + 0x000000000898) 1274f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT 12 1275f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT 6 1276f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT 0 1277f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL103 (PCIE + 0x00000000089C) 1278f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL105 (PCIE + 0x0000000008A4) 1279f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK 0x1ull 1280f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT 24 1281f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL100 (PCIE + 0x000000000890) 1282f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK 0x400ull 1283f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL101 (PCIE + 0x000000000894) 1284f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT 6 1285f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT 0 1286f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL106 (PCIE + 0x0000000008A8) 1287f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT 8 1288f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK 0x20ull 1289f48ad614SDennis Dalessandro #define PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK 0x10ull 1290f48ad614SDennis Dalessandro #define CCE_INT_BLOCKED (CCE + 0x000000110C00) 1291f48ad614SDennis Dalessandro #define SEND_DMA_IDLE_CNT (TXE + 0x000000200040) 1292f48ad614SDennis Dalessandro #define SEND_DMA_DESC_FETCHED_CNT (TXE + 0x000000200058) 1293f48ad614SDennis Dalessandro #define CCE_MSIX_PBA_OFFSET 0X0110000 1294f48ad614SDennis Dalessandro 1295f48ad614SDennis Dalessandro #endif /* DEF_CHIP_REG */ 1296