1 /* 2 * Copyright(c) 2015 - 2018 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 /* 49 * This file contains all of the code that is specific to the HFI chip 50 */ 51 52 #include <linux/pci.h> 53 #include <linux/delay.h> 54 #include <linux/interrupt.h> 55 #include <linux/module.h> 56 57 #include "hfi.h" 58 #include "trace.h" 59 #include "mad.h" 60 #include "pio.h" 61 #include "sdma.h" 62 #include "eprom.h" 63 #include "efivar.h" 64 #include "platform.h" 65 #include "aspm.h" 66 #include "affinity.h" 67 #include "debugfs.h" 68 #include "fault.h" 69 70 #define NUM_IB_PORTS 1 71 72 uint kdeth_qp; 73 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO); 74 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix"); 75 76 uint num_vls = HFI1_MAX_VLS_SUPPORTED; 77 module_param(num_vls, uint, S_IRUGO); 78 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 79 80 /* 81 * Default time to aggregate two 10K packets from the idle state 82 * (timer not running). The timer starts at the end of the first packet, 83 * so only the time for one 10K packet and header plus a bit extra is needed. 84 * 10 * 1024 + 64 header byte = 10304 byte 85 * 10304 byte / 12.5 GB/s = 824.32ns 86 */ 87 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */ 88 module_param(rcv_intr_timeout, uint, S_IRUGO); 89 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns"); 90 91 uint rcv_intr_count = 16; /* same as qib */ 92 module_param(rcv_intr_count, uint, S_IRUGO); 93 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count"); 94 95 ushort link_crc_mask = SUPPORTED_CRCS; 96 module_param(link_crc_mask, ushort, S_IRUGO); 97 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link"); 98 99 uint loopback; 100 module_param_named(loopback, loopback, uint, S_IRUGO); 101 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable"); 102 103 /* Other driver tunables */ 104 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/ 105 static ushort crc_14b_sideband = 1; 106 static uint use_flr = 1; 107 uint quick_linkup; /* skip LNI */ 108 109 struct flag_table { 110 u64 flag; /* the flag */ 111 char *str; /* description string */ 112 u16 extra; /* extra information */ 113 u16 unused0; 114 u32 unused1; 115 }; 116 117 /* str must be a string constant */ 118 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra} 119 #define FLAG_ENTRY0(str, flag) {flag, str, 0} 120 121 /* Send Error Consequences */ 122 #define SEC_WRITE_DROPPED 0x1 123 #define SEC_PACKET_DROPPED 0x2 124 #define SEC_SC_HALTED 0x4 /* per-context only */ 125 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */ 126 127 #define DEFAULT_KRCVQS 2 128 #define MIN_KERNEL_KCTXTS 2 129 #define FIRST_KERNEL_KCTXT 1 130 131 /* 132 * RSM instance allocation 133 * 0 - Verbs 134 * 1 - User Fecn Handling 135 * 2 - Vnic 136 */ 137 #define RSM_INS_VERBS 0 138 #define RSM_INS_FECN 1 139 #define RSM_INS_VNIC 2 140 141 /* Bit offset into the GUID which carries HFI id information */ 142 #define GUID_HFI_INDEX_SHIFT 39 143 144 /* extract the emulation revision */ 145 #define emulator_rev(dd) ((dd)->irev >> 8) 146 /* parallel and serial emulation versions are 3 and 4 respectively */ 147 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3) 148 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4) 149 150 /* RSM fields for Verbs */ 151 /* packet type */ 152 #define IB_PACKET_TYPE 2ull 153 #define QW_SHIFT 6ull 154 /* QPN[7..1] */ 155 #define QPN_WIDTH 7ull 156 157 /* LRH.BTH: QW 0, OFFSET 48 - for match */ 158 #define LRH_BTH_QW 0ull 159 #define LRH_BTH_BIT_OFFSET 48ull 160 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off)) 161 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET) 162 #define LRH_BTH_SELECT 163 #define LRH_BTH_MASK 3ull 164 #define LRH_BTH_VALUE 2ull 165 166 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */ 167 #define LRH_SC_QW 0ull 168 #define LRH_SC_BIT_OFFSET 56ull 169 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off)) 170 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET) 171 #define LRH_SC_MASK 128ull 172 #define LRH_SC_VALUE 0ull 173 174 /* SC[n..0] QW 0, OFFSET 60 - for select */ 175 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull)) 176 177 /* QPN[m+n:1] QW 1, OFFSET 1 */ 178 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull)) 179 180 /* RSM fields for Vnic */ 181 /* L2_TYPE: QW 0, OFFSET 61 - for match */ 182 #define L2_TYPE_QW 0ull 183 #define L2_TYPE_BIT_OFFSET 61ull 184 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off)) 185 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET) 186 #define L2_TYPE_MASK 3ull 187 #define L2_16B_VALUE 2ull 188 189 /* L4_TYPE QW 1, OFFSET 0 - for match */ 190 #define L4_TYPE_QW 1ull 191 #define L4_TYPE_BIT_OFFSET 0ull 192 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off)) 193 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET) 194 #define L4_16B_TYPE_MASK 0xFFull 195 #define L4_16B_ETH_VALUE 0x78ull 196 197 /* 16B VESWID - for select */ 198 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull)) 199 /* 16B ENTROPY - for select */ 200 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull)) 201 202 /* defines to build power on SC2VL table */ 203 #define SC2VL_VAL( \ 204 num, \ 205 sc0, sc0val, \ 206 sc1, sc1val, \ 207 sc2, sc2val, \ 208 sc3, sc3val, \ 209 sc4, sc4val, \ 210 sc5, sc5val, \ 211 sc6, sc6val, \ 212 sc7, sc7val) \ 213 ( \ 214 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \ 215 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \ 216 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \ 217 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \ 218 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \ 219 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \ 220 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \ 221 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \ 222 ) 223 224 #define DC_SC_VL_VAL( \ 225 range, \ 226 e0, e0val, \ 227 e1, e1val, \ 228 e2, e2val, \ 229 e3, e3val, \ 230 e4, e4val, \ 231 e5, e5val, \ 232 e6, e6val, \ 233 e7, e7val, \ 234 e8, e8val, \ 235 e9, e9val, \ 236 e10, e10val, \ 237 e11, e11val, \ 238 e12, e12val, \ 239 e13, e13val, \ 240 e14, e14val, \ 241 e15, e15val) \ 242 ( \ 243 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \ 244 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \ 245 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \ 246 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \ 247 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \ 248 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \ 249 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \ 250 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \ 251 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \ 252 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \ 253 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \ 254 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \ 255 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \ 256 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \ 257 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \ 258 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \ 259 ) 260 261 /* all CceStatus sub-block freeze bits */ 262 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \ 263 | CCE_STATUS_RXE_FROZE_SMASK \ 264 | CCE_STATUS_TXE_FROZE_SMASK \ 265 | CCE_STATUS_TXE_PIO_FROZE_SMASK) 266 /* all CceStatus sub-block TXE pause bits */ 267 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \ 268 | CCE_STATUS_TXE_PAUSED_SMASK \ 269 | CCE_STATUS_SDMA_PAUSED_SMASK) 270 /* all CceStatus sub-block RXE pause bits */ 271 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK 272 273 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL 274 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF 275 276 /* 277 * CCE Error flags. 278 */ 279 static struct flag_table cce_err_status_flags[] = { 280 /* 0*/ FLAG_ENTRY0("CceCsrParityErr", 281 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK), 282 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr", 283 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK), 284 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr", 285 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK), 286 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr", 287 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK), 288 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr", 289 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK), 290 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr", 291 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK), 292 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr", 293 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK), 294 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr", 295 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK), 296 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr", 297 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK), 298 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 299 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK), 300 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 301 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK), 302 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError", 303 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK), 304 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError", 305 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK), 306 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr", 307 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK), 308 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr", 309 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK), 310 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr", 311 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK), 312 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr", 313 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK), 314 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr", 315 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK), 316 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr", 317 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK), 318 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr", 319 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK), 320 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr", 321 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK), 322 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr", 323 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK), 324 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr", 325 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK), 326 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr", 327 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK), 328 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr", 329 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK), 330 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr", 331 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK), 332 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr", 333 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK), 334 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr", 335 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK), 336 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr", 337 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK), 338 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr", 339 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK), 340 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr", 341 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK), 342 /*31*/ FLAG_ENTRY0("LATriggered", 343 CCE_ERR_STATUS_LA_TRIGGERED_SMASK), 344 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr", 345 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK), 346 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr", 347 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK), 348 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr", 349 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK), 350 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr", 351 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK), 352 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr", 353 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK), 354 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr", 355 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK), 356 /*38*/ FLAG_ENTRY0("CceIntMapCorErr", 357 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK), 358 /*39*/ FLAG_ENTRY0("CceIntMapUncErr", 359 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK), 360 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr", 361 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK), 362 /*41-63 reserved*/ 363 }; 364 365 /* 366 * Misc Error flags 367 */ 368 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK 369 static struct flag_table misc_err_status_flags[] = { 370 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)), 371 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)), 372 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)), 373 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)), 374 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)), 375 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)), 376 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)), 377 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)), 378 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)), 379 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)), 380 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)), 381 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)), 382 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL)) 383 }; 384 385 /* 386 * TXE PIO Error flags and consequences 387 */ 388 static struct flag_table pio_err_status_flags[] = { 389 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt", 390 SEC_WRITE_DROPPED, 391 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK), 392 /* 1*/ FLAG_ENTRY("PioWriteAddrParity", 393 SEC_SPC_FREEZE, 394 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK), 395 /* 2*/ FLAG_ENTRY("PioCsrParity", 396 SEC_SPC_FREEZE, 397 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK), 398 /* 3*/ FLAG_ENTRY("PioSbMemFifo0", 399 SEC_SPC_FREEZE, 400 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK), 401 /* 4*/ FLAG_ENTRY("PioSbMemFifo1", 402 SEC_SPC_FREEZE, 403 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK), 404 /* 5*/ FLAG_ENTRY("PioPccFifoParity", 405 SEC_SPC_FREEZE, 406 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK), 407 /* 6*/ FLAG_ENTRY("PioPecFifoParity", 408 SEC_SPC_FREEZE, 409 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK), 410 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity", 411 SEC_SPC_FREEZE, 412 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK), 413 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity", 414 SEC_SPC_FREEZE, 415 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK), 416 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr", 417 SEC_SPC_FREEZE, 418 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK), 419 /*10*/ FLAG_ENTRY("PioSmPktResetParity", 420 SEC_SPC_FREEZE, 421 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK), 422 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc", 423 SEC_SPC_FREEZE, 424 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK), 425 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc", 426 SEC_SPC_FREEZE, 427 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK), 428 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor", 429 0, 430 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK), 431 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor", 432 0, 433 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK), 434 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity", 435 SEC_SPC_FREEZE, 436 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK), 437 /*16*/ FLAG_ENTRY("PioPpmcPblFifo", 438 SEC_SPC_FREEZE, 439 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK), 440 /*17*/ FLAG_ENTRY("PioInitSmIn", 441 0, 442 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK), 443 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm", 444 SEC_SPC_FREEZE, 445 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK), 446 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc", 447 SEC_SPC_FREEZE, 448 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK), 449 /*20*/ FLAG_ENTRY("PioHostAddrMemCor", 450 0, 451 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK), 452 /*21*/ FLAG_ENTRY("PioWriteDataParity", 453 SEC_SPC_FREEZE, 454 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK), 455 /*22*/ FLAG_ENTRY("PioStateMachine", 456 SEC_SPC_FREEZE, 457 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK), 458 /*23*/ FLAG_ENTRY("PioWriteQwValidParity", 459 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 460 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK), 461 /*24*/ FLAG_ENTRY("PioBlockQwCountParity", 462 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 463 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK), 464 /*25*/ FLAG_ENTRY("PioVlfVlLenParity", 465 SEC_SPC_FREEZE, 466 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK), 467 /*26*/ FLAG_ENTRY("PioVlfSopParity", 468 SEC_SPC_FREEZE, 469 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK), 470 /*27*/ FLAG_ENTRY("PioVlFifoParity", 471 SEC_SPC_FREEZE, 472 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK), 473 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity", 474 SEC_SPC_FREEZE, 475 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK), 476 /*29*/ FLAG_ENTRY("PioPpmcSopLen", 477 SEC_SPC_FREEZE, 478 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK), 479 /*30-31 reserved*/ 480 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity", 481 SEC_SPC_FREEZE, 482 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK), 483 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity", 484 SEC_SPC_FREEZE, 485 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK), 486 /*34*/ FLAG_ENTRY("PioPccSopHeadParity", 487 SEC_SPC_FREEZE, 488 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK), 489 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr", 490 SEC_SPC_FREEZE, 491 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK), 492 /*36-63 reserved*/ 493 }; 494 495 /* TXE PIO errors that cause an SPC freeze */ 496 #define ALL_PIO_FREEZE_ERR \ 497 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \ 498 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \ 499 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \ 500 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \ 501 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \ 502 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \ 503 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \ 504 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 505 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \ 506 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \ 507 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \ 508 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \ 509 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \ 510 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \ 511 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \ 512 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \ 513 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \ 514 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \ 515 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \ 516 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 517 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \ 518 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \ 519 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \ 520 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \ 521 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \ 522 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 523 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 524 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 525 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK) 526 527 /* 528 * TXE SDMA Error flags 529 */ 530 static struct flag_table sdma_err_status_flags[] = { 531 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr", 532 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK), 533 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr", 534 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK), 535 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr", 536 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK), 537 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr", 538 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK), 539 /*04-63 reserved*/ 540 }; 541 542 /* TXE SDMA errors that cause an SPC freeze */ 543 #define ALL_SDMA_FREEZE_ERR \ 544 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \ 545 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \ 546 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK) 547 548 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */ 549 #define PORT_DISCARD_EGRESS_ERRS \ 550 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \ 551 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \ 552 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK) 553 554 /* 555 * TXE Egress Error flags 556 */ 557 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK 558 static struct flag_table egress_err_status_flags[] = { 559 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)), 560 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)), 561 /* 2 reserved */ 562 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr", 563 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)), 564 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)), 565 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)), 566 /* 6 reserved */ 567 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr", 568 SEES(TX_PIO_LAUNCH_INTF_PARITY)), 569 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr", 570 SEES(TX_SDMA_LAUNCH_INTF_PARITY)), 571 /* 9-10 reserved */ 572 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr", 573 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)), 574 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)), 575 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)), 576 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)), 577 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)), 578 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr", 579 SEES(TX_SDMA0_DISALLOWED_PACKET)), 580 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr", 581 SEES(TX_SDMA1_DISALLOWED_PACKET)), 582 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr", 583 SEES(TX_SDMA2_DISALLOWED_PACKET)), 584 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr", 585 SEES(TX_SDMA3_DISALLOWED_PACKET)), 586 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr", 587 SEES(TX_SDMA4_DISALLOWED_PACKET)), 588 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr", 589 SEES(TX_SDMA5_DISALLOWED_PACKET)), 590 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr", 591 SEES(TX_SDMA6_DISALLOWED_PACKET)), 592 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr", 593 SEES(TX_SDMA7_DISALLOWED_PACKET)), 594 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr", 595 SEES(TX_SDMA8_DISALLOWED_PACKET)), 596 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr", 597 SEES(TX_SDMA9_DISALLOWED_PACKET)), 598 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr", 599 SEES(TX_SDMA10_DISALLOWED_PACKET)), 600 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr", 601 SEES(TX_SDMA11_DISALLOWED_PACKET)), 602 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr", 603 SEES(TX_SDMA12_DISALLOWED_PACKET)), 604 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr", 605 SEES(TX_SDMA13_DISALLOWED_PACKET)), 606 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr", 607 SEES(TX_SDMA14_DISALLOWED_PACKET)), 608 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr", 609 SEES(TX_SDMA15_DISALLOWED_PACKET)), 610 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr", 611 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)), 612 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr", 613 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)), 614 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr", 615 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)), 616 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr", 617 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)), 618 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr", 619 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)), 620 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr", 621 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)), 622 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr", 623 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)), 624 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr", 625 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)), 626 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr", 627 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)), 628 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)), 629 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)), 630 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)), 631 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)), 632 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)), 633 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)), 634 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)), 635 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)), 636 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)), 637 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)), 638 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)), 639 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)), 640 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)), 641 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)), 642 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)), 643 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)), 644 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)), 645 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)), 646 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)), 647 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)), 648 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)), 649 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr", 650 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)), 651 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr", 652 SEES(TX_READ_PIO_MEMORY_CSR_UNC)), 653 }; 654 655 /* 656 * TXE Egress Error Info flags 657 */ 658 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK 659 static struct flag_table egress_err_info_flags[] = { 660 /* 0*/ FLAG_ENTRY0("Reserved", 0ull), 661 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)), 662 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 663 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 664 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)), 665 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)), 666 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)), 667 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)), 668 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)), 669 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)), 670 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)), 671 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)), 672 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)), 673 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)), 674 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)), 675 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)), 676 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)), 677 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)), 678 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)), 679 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)), 680 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)), 681 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)), 682 }; 683 684 /* TXE Egress errors that cause an SPC freeze */ 685 #define ALL_TXE_EGRESS_FREEZE_ERR \ 686 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \ 687 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \ 688 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \ 689 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \ 690 | SEES(TX_LAUNCH_CSR_PARITY) \ 691 | SEES(TX_SBRD_CTL_CSR_PARITY) \ 692 | SEES(TX_CONFIG_PARITY) \ 693 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \ 694 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \ 695 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \ 696 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \ 697 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \ 698 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \ 699 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \ 700 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \ 701 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \ 702 | SEES(TX_CREDIT_RETURN_PARITY)) 703 704 /* 705 * TXE Send error flags 706 */ 707 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK 708 static struct flag_table send_err_status_flags[] = { 709 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)), 710 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)), 711 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR)) 712 }; 713 714 /* 715 * TXE Send Context Error flags and consequences 716 */ 717 static struct flag_table sc_err_status_flags[] = { 718 /* 0*/ FLAG_ENTRY("InconsistentSop", 719 SEC_PACKET_DROPPED | SEC_SC_HALTED, 720 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK), 721 /* 1*/ FLAG_ENTRY("DisallowedPacket", 722 SEC_PACKET_DROPPED | SEC_SC_HALTED, 723 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK), 724 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary", 725 SEC_WRITE_DROPPED | SEC_SC_HALTED, 726 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK), 727 /* 3*/ FLAG_ENTRY("WriteOverflow", 728 SEC_WRITE_DROPPED | SEC_SC_HALTED, 729 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK), 730 /* 4*/ FLAG_ENTRY("WriteOutOfBounds", 731 SEC_WRITE_DROPPED | SEC_SC_HALTED, 732 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK), 733 /* 5-63 reserved*/ 734 }; 735 736 /* 737 * RXE Receive Error flags 738 */ 739 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK 740 static struct flag_table rxe_err_status_flags[] = { 741 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)), 742 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)), 743 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)), 744 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)), 745 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)), 746 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)), 747 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)), 748 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)), 749 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)), 750 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)), 751 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)), 752 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)), 753 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)), 754 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)), 755 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)), 756 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)), 757 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr", 758 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)), 759 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)), 760 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)), 761 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr", 762 RXES(RBUF_BLOCK_LIST_READ_UNC)), 763 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr", 764 RXES(RBUF_BLOCK_LIST_READ_COR)), 765 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr", 766 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)), 767 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr", 768 RXES(RBUF_CSR_QENT_CNT_PARITY)), 769 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr", 770 RXES(RBUF_CSR_QNEXT_BUF_PARITY)), 771 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr", 772 RXES(RBUF_CSR_QVLD_BIT_PARITY)), 773 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)), 774 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)), 775 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr", 776 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)), 777 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)), 778 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)), 779 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)), 780 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)), 781 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)), 782 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)), 783 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)), 784 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr", 785 RXES(RBUF_FL_INITDONE_PARITY)), 786 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr", 787 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)), 788 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)), 789 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)), 790 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)), 791 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr", 792 RXES(LOOKUP_DES_PART1_UNC_COR)), 793 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr", 794 RXES(LOOKUP_DES_PART2_PARITY)), 795 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)), 796 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)), 797 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)), 798 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)), 799 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)), 800 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)), 801 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)), 802 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)), 803 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)), 804 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)), 805 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)), 806 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)), 807 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)), 808 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)), 809 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)), 810 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)), 811 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)), 812 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)), 813 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)), 814 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)), 815 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)), 816 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY)) 817 }; 818 819 /* RXE errors that will trigger an SPC freeze */ 820 #define ALL_RXE_FREEZE_ERR \ 821 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \ 822 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \ 823 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \ 824 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \ 825 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \ 826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \ 827 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \ 828 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \ 829 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \ 830 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 831 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \ 832 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \ 833 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \ 834 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \ 835 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \ 836 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 837 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \ 838 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \ 839 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \ 840 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \ 841 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \ 842 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \ 843 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \ 844 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \ 845 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 846 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \ 847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \ 848 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 849 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 850 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \ 851 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \ 852 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \ 853 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \ 854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \ 855 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \ 856 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \ 857 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \ 858 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 859 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \ 860 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \ 861 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 862 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 863 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \ 864 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK) 865 866 #define RXE_FREEZE_ABORT_MASK \ 867 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \ 868 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \ 869 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK) 870 871 /* 872 * DCC Error Flags 873 */ 874 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK 875 static struct flag_table dcc_err_flags[] = { 876 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)), 877 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)), 878 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)), 879 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)), 880 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)), 881 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)), 882 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)), 883 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)), 884 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)), 885 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)), 886 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)), 887 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)), 888 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)), 889 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)), 890 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)), 891 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)), 892 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)), 893 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)), 894 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)), 895 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)), 896 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)), 897 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)), 898 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)), 899 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)), 900 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)), 901 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)), 902 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)), 903 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)), 904 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)), 905 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)), 906 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)), 907 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)), 908 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)), 909 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)), 910 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)), 911 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)), 912 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)), 913 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)), 914 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)), 915 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)), 916 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)), 917 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)), 918 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)), 919 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)), 920 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)), 921 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)), 922 }; 923 924 /* 925 * LCB error flags 926 */ 927 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK 928 static struct flag_table lcb_err_flags[] = { 929 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)), 930 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)), 931 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)), 932 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST", 933 LCBE(ALL_LNS_FAILED_REINIT_TEST)), 934 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)), 935 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)), 936 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)), 937 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)), 938 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)), 939 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)), 940 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)), 941 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)), 942 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)), 943 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER", 944 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)), 945 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)), 946 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)), 947 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)), 948 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)), 949 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)), 950 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE", 951 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)), 952 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)), 953 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)), 954 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)), 955 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)), 956 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)), 957 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)), 958 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP", 959 LCBE(RST_FOR_INCOMPLT_RND_TRIP)), 960 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)), 961 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE", 962 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)), 963 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR", 964 LCBE(REDUNDANT_FLIT_PARITY_ERR)) 965 }; 966 967 /* 968 * DC8051 Error Flags 969 */ 970 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK 971 static struct flag_table dc8051_err_flags[] = { 972 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)), 973 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)), 974 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)), 975 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)), 976 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)), 977 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)), 978 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)), 979 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)), 980 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES", 981 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)), 982 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)), 983 }; 984 985 /* 986 * DC8051 Information Error flags 987 * 988 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field. 989 */ 990 static struct flag_table dc8051_info_err_flags[] = { 991 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED), 992 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME), 993 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET), 994 FLAG_ENTRY0("Serdes internal loopback failure", 995 FAILED_SERDES_INTERNAL_LOOPBACK), 996 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT), 997 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING), 998 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE), 999 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM), 1000 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ), 1001 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1), 1002 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2), 1003 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT), 1004 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT), 1005 FLAG_ENTRY0("External Device Request Timeout", 1006 EXTERNAL_DEVICE_REQ_TIMEOUT), 1007 }; 1008 1009 /* 1010 * DC8051 Information Host Information flags 1011 * 1012 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field. 1013 */ 1014 static struct flag_table dc8051_info_host_msg_flags[] = { 1015 FLAG_ENTRY0("Host request done", 0x0001), 1016 FLAG_ENTRY0("BC PWR_MGM message", 0x0002), 1017 FLAG_ENTRY0("BC SMA message", 0x0004), 1018 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008), 1019 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010), 1020 FLAG_ENTRY0("External device config request", 0x0020), 1021 FLAG_ENTRY0("VerifyCap all frames received", 0x0040), 1022 FLAG_ENTRY0("LinkUp achieved", 0x0080), 1023 FLAG_ENTRY0("Link going down", 0x0100), 1024 FLAG_ENTRY0("Link width downgraded", 0x0200), 1025 }; 1026 1027 static u32 encoded_size(u32 size); 1028 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate); 1029 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state); 1030 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 1031 u8 *continuous); 1032 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 1033 u8 *vcu, u16 *vl15buf, u8 *crc_sizes); 1034 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 1035 u8 *remote_tx_rate, u16 *link_widths); 1036 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 1037 u8 *flag_bits, u16 *link_widths); 1038 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 1039 u8 *device_rev); 1040 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx); 1041 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx, 1042 u8 *tx_polarity_inversion, 1043 u8 *rx_polarity_inversion, u8 *max_rate); 1044 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 1045 unsigned int context, u64 err_status); 1046 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg); 1047 static void handle_dcc_err(struct hfi1_devdata *dd, 1048 unsigned int context, u64 err_status); 1049 static void handle_lcb_err(struct hfi1_devdata *dd, 1050 unsigned int context, u64 err_status); 1051 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg); 1052 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1053 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1054 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1055 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1056 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1057 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1058 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1059 static void set_partition_keys(struct hfi1_pportdata *ppd); 1060 static const char *link_state_name(u32 state); 1061 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, 1062 u32 state); 1063 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 1064 u64 *out_data); 1065 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data); 1066 static int thermal_init(struct hfi1_devdata *dd); 1067 1068 static void update_statusp(struct hfi1_pportdata *ppd, u32 state); 1069 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 1070 int msecs); 1071 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1072 int msecs); 1073 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state); 1074 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state); 1075 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1076 int msecs); 1077 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc); 1078 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr); 1079 static void handle_temp_err(struct hfi1_devdata *dd); 1080 static void dc_shutdown(struct hfi1_devdata *dd); 1081 static void dc_start(struct hfi1_devdata *dd); 1082 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 1083 unsigned int *np); 1084 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd); 1085 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms); 1086 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index); 1087 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width); 1088 1089 /* 1090 * Error interrupt table entry. This is used as input to the interrupt 1091 * "clear down" routine used for all second tier error interrupt register. 1092 * Second tier interrupt registers have a single bit representing them 1093 * in the top-level CceIntStatus. 1094 */ 1095 struct err_reg_info { 1096 u32 status; /* status CSR offset */ 1097 u32 clear; /* clear CSR offset */ 1098 u32 mask; /* mask CSR offset */ 1099 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg); 1100 const char *desc; 1101 }; 1102 1103 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START) 1104 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START) 1105 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START) 1106 1107 /* 1108 * Helpers for building HFI and DC error interrupt table entries. Different 1109 * helpers are needed because of inconsistent register names. 1110 */ 1111 #define EE(reg, handler, desc) \ 1112 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ 1113 handler, desc } 1114 #define DC_EE1(reg, handler, desc) \ 1115 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc } 1116 #define DC_EE2(reg, handler, desc) \ 1117 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc } 1118 1119 /* 1120 * Table of the "misc" grouping of error interrupts. Each entry refers to 1121 * another register containing more information. 1122 */ 1123 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = { 1124 /* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"), 1125 /* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"), 1126 /* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"), 1127 /* 3*/ { 0, 0, 0, NULL }, /* reserved */ 1128 /* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"), 1129 /* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"), 1130 /* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"), 1131 /* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr") 1132 /* the rest are reserved */ 1133 }; 1134 1135 /* 1136 * Index into the Various section of the interrupt sources 1137 * corresponding to the Critical Temperature interrupt. 1138 */ 1139 #define TCRIT_INT_SOURCE 4 1140 1141 /* 1142 * SDMA error interrupt entry - refers to another register containing more 1143 * information. 1144 */ 1145 static const struct err_reg_info sdma_eng_err = 1146 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr"); 1147 1148 static const struct err_reg_info various_err[NUM_VARIOUS] = { 1149 /* 0*/ { 0, 0, 0, NULL }, /* PbcInt */ 1150 /* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */ 1151 /* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"), 1152 /* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"), 1153 /* 4*/ { 0, 0, 0, NULL }, /* TCritInt */ 1154 /* rest are reserved */ 1155 }; 1156 1157 /* 1158 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG 1159 * register can not be derived from the MTU value because 10K is not 1160 * a power of 2. Therefore, we need a constant. Everything else can 1161 * be calculated. 1162 */ 1163 #define DCC_CFG_PORT_MTU_CAP_10240 7 1164 1165 /* 1166 * Table of the DC grouping of error interrupts. Each entry refers to 1167 * another register containing more information. 1168 */ 1169 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = { 1170 /* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"), 1171 /* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"), 1172 /* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"), 1173 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */ 1174 /* the rest are reserved */ 1175 }; 1176 1177 struct cntr_entry { 1178 /* 1179 * counter name 1180 */ 1181 char *name; 1182 1183 /* 1184 * csr to read for name (if applicable) 1185 */ 1186 u64 csr; 1187 1188 /* 1189 * offset into dd or ppd to store the counter's value 1190 */ 1191 int offset; 1192 1193 /* 1194 * flags 1195 */ 1196 u8 flags; 1197 1198 /* 1199 * accessor for stat element, context either dd or ppd 1200 */ 1201 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl, 1202 int mode, u64 data); 1203 }; 1204 1205 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0 1206 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159 1207 1208 #define CNTR_ELEM(name, csr, offset, flags, accessor) \ 1209 { \ 1210 name, \ 1211 csr, \ 1212 offset, \ 1213 flags, \ 1214 accessor \ 1215 } 1216 1217 /* 32bit RXE */ 1218 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1219 CNTR_ELEM(#name, \ 1220 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1221 0, flags | CNTR_32BIT, \ 1222 port_access_u32_csr) 1223 1224 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \ 1225 CNTR_ELEM(#name, \ 1226 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1227 0, flags | CNTR_32BIT, \ 1228 dev_access_u32_csr) 1229 1230 /* 64bit RXE */ 1231 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1232 CNTR_ELEM(#name, \ 1233 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1234 0, flags, \ 1235 port_access_u64_csr) 1236 1237 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \ 1238 CNTR_ELEM(#name, \ 1239 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1240 0, flags, \ 1241 dev_access_u64_csr) 1242 1243 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx 1244 #define OVR_ELM(ctx) \ 1245 CNTR_ELEM("RcvHdrOvr" #ctx, \ 1246 (RCV_HDR_OVFL_CNT + ctx * 0x100), \ 1247 0, CNTR_NORMAL, port_access_u64_csr) 1248 1249 /* 32bit TXE */ 1250 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1251 CNTR_ELEM(#name, \ 1252 (counter * 8 + SEND_COUNTER_ARRAY32), \ 1253 0, flags | CNTR_32BIT, \ 1254 port_access_u32_csr) 1255 1256 /* 64bit TXE */ 1257 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1258 CNTR_ELEM(#name, \ 1259 (counter * 8 + SEND_COUNTER_ARRAY64), \ 1260 0, flags, \ 1261 port_access_u64_csr) 1262 1263 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \ 1264 CNTR_ELEM(#name,\ 1265 counter * 8 + SEND_COUNTER_ARRAY64, \ 1266 0, \ 1267 flags, \ 1268 dev_access_u64_csr) 1269 1270 /* CCE */ 1271 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \ 1272 CNTR_ELEM(#name, \ 1273 (counter * 8 + CCE_COUNTER_ARRAY32), \ 1274 0, flags | CNTR_32BIT, \ 1275 dev_access_u32_csr) 1276 1277 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \ 1278 CNTR_ELEM(#name, \ 1279 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \ 1280 0, flags | CNTR_32BIT, \ 1281 dev_access_u32_csr) 1282 1283 /* DC */ 1284 #define DC_PERF_CNTR(name, counter, flags) \ 1285 CNTR_ELEM(#name, \ 1286 counter, \ 1287 0, \ 1288 flags, \ 1289 dev_access_u64_csr) 1290 1291 #define DC_PERF_CNTR_LCB(name, counter, flags) \ 1292 CNTR_ELEM(#name, \ 1293 counter, \ 1294 0, \ 1295 flags, \ 1296 dc_access_lcb_cntr) 1297 1298 /* ibp counters */ 1299 #define SW_IBP_CNTR(name, cntr) \ 1300 CNTR_ELEM(#name, \ 1301 0, \ 1302 0, \ 1303 CNTR_SYNTH, \ 1304 access_ibp_##cntr) 1305 1306 /** 1307 * hfi_addr_from_offset - return addr for readq/writeq 1308 * @dd - the dd device 1309 * @offset - the offset of the CSR within bar0 1310 * 1311 * This routine selects the appropriate base address 1312 * based on the indicated offset. 1313 */ 1314 static inline void __iomem *hfi1_addr_from_offset( 1315 const struct hfi1_devdata *dd, 1316 u32 offset) 1317 { 1318 if (offset >= dd->base2_start) 1319 return dd->kregbase2 + (offset - dd->base2_start); 1320 return dd->kregbase1 + offset; 1321 } 1322 1323 /** 1324 * read_csr - read CSR at the indicated offset 1325 * @dd - the dd device 1326 * @offset - the offset of the CSR within bar0 1327 * 1328 * Return: the value read or all FF's if there 1329 * is no mapping 1330 */ 1331 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) 1332 { 1333 if (dd->flags & HFI1_PRESENT) 1334 return readq(hfi1_addr_from_offset(dd, offset)); 1335 return -1; 1336 } 1337 1338 /** 1339 * write_csr - write CSR at the indicated offset 1340 * @dd - the dd device 1341 * @offset - the offset of the CSR within bar0 1342 * @value - value to write 1343 */ 1344 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) 1345 { 1346 if (dd->flags & HFI1_PRESENT) { 1347 void __iomem *base = hfi1_addr_from_offset(dd, offset); 1348 1349 /* avoid write to RcvArray */ 1350 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start)) 1351 return; 1352 writeq(value, base); 1353 } 1354 } 1355 1356 /** 1357 * get_csr_addr - return te iomem address for offset 1358 * @dd - the dd device 1359 * @offset - the offset of the CSR within bar0 1360 * 1361 * Return: The iomem address to use in subsequent 1362 * writeq/readq operations. 1363 */ 1364 void __iomem *get_csr_addr( 1365 const struct hfi1_devdata *dd, 1366 u32 offset) 1367 { 1368 if (dd->flags & HFI1_PRESENT) 1369 return hfi1_addr_from_offset(dd, offset); 1370 return NULL; 1371 } 1372 1373 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr, 1374 int mode, u64 value) 1375 { 1376 u64 ret; 1377 1378 if (mode == CNTR_MODE_R) { 1379 ret = read_csr(dd, csr); 1380 } else if (mode == CNTR_MODE_W) { 1381 write_csr(dd, csr, value); 1382 ret = value; 1383 } else { 1384 dd_dev_err(dd, "Invalid cntr register access mode"); 1385 return 0; 1386 } 1387 1388 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode); 1389 return ret; 1390 } 1391 1392 /* Dev Access */ 1393 static u64 dev_access_u32_csr(const struct cntr_entry *entry, 1394 void *context, int vl, int mode, u64 data) 1395 { 1396 struct hfi1_devdata *dd = context; 1397 u64 csr = entry->csr; 1398 1399 if (entry->flags & CNTR_SDMA) { 1400 if (vl == CNTR_INVALID_VL) 1401 return 0; 1402 csr += 0x100 * vl; 1403 } else { 1404 if (vl != CNTR_INVALID_VL) 1405 return 0; 1406 } 1407 return read_write_csr(dd, csr, mode, data); 1408 } 1409 1410 static u64 access_sde_err_cnt(const struct cntr_entry *entry, 1411 void *context, int idx, int mode, u64 data) 1412 { 1413 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1414 1415 if (dd->per_sdma && idx < dd->num_sdma) 1416 return dd->per_sdma[idx].err_cnt; 1417 return 0; 1418 } 1419 1420 static u64 access_sde_int_cnt(const struct cntr_entry *entry, 1421 void *context, int idx, int mode, u64 data) 1422 { 1423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1424 1425 if (dd->per_sdma && idx < dd->num_sdma) 1426 return dd->per_sdma[idx].sdma_int_cnt; 1427 return 0; 1428 } 1429 1430 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry, 1431 void *context, int idx, int mode, u64 data) 1432 { 1433 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1434 1435 if (dd->per_sdma && idx < dd->num_sdma) 1436 return dd->per_sdma[idx].idle_int_cnt; 1437 return 0; 1438 } 1439 1440 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry, 1441 void *context, int idx, int mode, 1442 u64 data) 1443 { 1444 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1445 1446 if (dd->per_sdma && idx < dd->num_sdma) 1447 return dd->per_sdma[idx].progress_int_cnt; 1448 return 0; 1449 } 1450 1451 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context, 1452 int vl, int mode, u64 data) 1453 { 1454 struct hfi1_devdata *dd = context; 1455 1456 u64 val = 0; 1457 u64 csr = entry->csr; 1458 1459 if (entry->flags & CNTR_VL) { 1460 if (vl == CNTR_INVALID_VL) 1461 return 0; 1462 csr += 8 * vl; 1463 } else { 1464 if (vl != CNTR_INVALID_VL) 1465 return 0; 1466 } 1467 1468 val = read_write_csr(dd, csr, mode, data); 1469 return val; 1470 } 1471 1472 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context, 1473 int vl, int mode, u64 data) 1474 { 1475 struct hfi1_devdata *dd = context; 1476 u32 csr = entry->csr; 1477 int ret = 0; 1478 1479 if (vl != CNTR_INVALID_VL) 1480 return 0; 1481 if (mode == CNTR_MODE_R) 1482 ret = read_lcb_csr(dd, csr, &data); 1483 else if (mode == CNTR_MODE_W) 1484 ret = write_lcb_csr(dd, csr, data); 1485 1486 if (ret) { 1487 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr); 1488 return 0; 1489 } 1490 1491 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode); 1492 return data; 1493 } 1494 1495 /* Port Access */ 1496 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context, 1497 int vl, int mode, u64 data) 1498 { 1499 struct hfi1_pportdata *ppd = context; 1500 1501 if (vl != CNTR_INVALID_VL) 1502 return 0; 1503 return read_write_csr(ppd->dd, entry->csr, mode, data); 1504 } 1505 1506 static u64 port_access_u64_csr(const struct cntr_entry *entry, 1507 void *context, int vl, int mode, u64 data) 1508 { 1509 struct hfi1_pportdata *ppd = context; 1510 u64 val; 1511 u64 csr = entry->csr; 1512 1513 if (entry->flags & CNTR_VL) { 1514 if (vl == CNTR_INVALID_VL) 1515 return 0; 1516 csr += 8 * vl; 1517 } else { 1518 if (vl != CNTR_INVALID_VL) 1519 return 0; 1520 } 1521 val = read_write_csr(ppd->dd, csr, mode, data); 1522 return val; 1523 } 1524 1525 /* Software defined */ 1526 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode, 1527 u64 data) 1528 { 1529 u64 ret; 1530 1531 if (mode == CNTR_MODE_R) { 1532 ret = *cntr; 1533 } else if (mode == CNTR_MODE_W) { 1534 *cntr = data; 1535 ret = data; 1536 } else { 1537 dd_dev_err(dd, "Invalid cntr sw access mode"); 1538 return 0; 1539 } 1540 1541 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode); 1542 1543 return ret; 1544 } 1545 1546 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context, 1547 int vl, int mode, u64 data) 1548 { 1549 struct hfi1_pportdata *ppd = context; 1550 1551 if (vl != CNTR_INVALID_VL) 1552 return 0; 1553 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data); 1554 } 1555 1556 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context, 1557 int vl, int mode, u64 data) 1558 { 1559 struct hfi1_pportdata *ppd = context; 1560 1561 if (vl != CNTR_INVALID_VL) 1562 return 0; 1563 return read_write_sw(ppd->dd, &ppd->link_up, mode, data); 1564 } 1565 1566 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry, 1567 void *context, int vl, int mode, 1568 u64 data) 1569 { 1570 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1571 1572 if (vl != CNTR_INVALID_VL) 1573 return 0; 1574 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data); 1575 } 1576 1577 static u64 access_sw_xmit_discards(const struct cntr_entry *entry, 1578 void *context, int vl, int mode, u64 data) 1579 { 1580 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1581 u64 zero = 0; 1582 u64 *counter; 1583 1584 if (vl == CNTR_INVALID_VL) 1585 counter = &ppd->port_xmit_discards; 1586 else if (vl >= 0 && vl < C_VL_COUNT) 1587 counter = &ppd->port_xmit_discards_vl[vl]; 1588 else 1589 counter = &zero; 1590 1591 return read_write_sw(ppd->dd, counter, mode, data); 1592 } 1593 1594 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry, 1595 void *context, int vl, int mode, 1596 u64 data) 1597 { 1598 struct hfi1_pportdata *ppd = context; 1599 1600 if (vl != CNTR_INVALID_VL) 1601 return 0; 1602 1603 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors, 1604 mode, data); 1605 } 1606 1607 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry, 1608 void *context, int vl, int mode, u64 data) 1609 { 1610 struct hfi1_pportdata *ppd = context; 1611 1612 if (vl != CNTR_INVALID_VL) 1613 return 0; 1614 1615 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors, 1616 mode, data); 1617 } 1618 1619 u64 get_all_cpu_total(u64 __percpu *cntr) 1620 { 1621 int cpu; 1622 u64 counter = 0; 1623 1624 for_each_possible_cpu(cpu) 1625 counter += *per_cpu_ptr(cntr, cpu); 1626 return counter; 1627 } 1628 1629 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val, 1630 u64 __percpu *cntr, 1631 int vl, int mode, u64 data) 1632 { 1633 u64 ret = 0; 1634 1635 if (vl != CNTR_INVALID_VL) 1636 return 0; 1637 1638 if (mode == CNTR_MODE_R) { 1639 ret = get_all_cpu_total(cntr) - *z_val; 1640 } else if (mode == CNTR_MODE_W) { 1641 /* A write can only zero the counter */ 1642 if (data == 0) 1643 *z_val = get_all_cpu_total(cntr); 1644 else 1645 dd_dev_err(dd, "Per CPU cntrs can only be zeroed"); 1646 } else { 1647 dd_dev_err(dd, "Invalid cntr sw cpu access mode"); 1648 return 0; 1649 } 1650 1651 return ret; 1652 } 1653 1654 static u64 access_sw_cpu_intr(const struct cntr_entry *entry, 1655 void *context, int vl, int mode, u64 data) 1656 { 1657 struct hfi1_devdata *dd = context; 1658 1659 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl, 1660 mode, data); 1661 } 1662 1663 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry, 1664 void *context, int vl, int mode, u64 data) 1665 { 1666 struct hfi1_devdata *dd = context; 1667 1668 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl, 1669 mode, data); 1670 } 1671 1672 static u64 access_sw_pio_wait(const struct cntr_entry *entry, 1673 void *context, int vl, int mode, u64 data) 1674 { 1675 struct hfi1_devdata *dd = context; 1676 1677 return dd->verbs_dev.n_piowait; 1678 } 1679 1680 static u64 access_sw_pio_drain(const struct cntr_entry *entry, 1681 void *context, int vl, int mode, u64 data) 1682 { 1683 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1684 1685 return dd->verbs_dev.n_piodrain; 1686 } 1687 1688 static u64 access_sw_vtx_wait(const struct cntr_entry *entry, 1689 void *context, int vl, int mode, u64 data) 1690 { 1691 struct hfi1_devdata *dd = context; 1692 1693 return dd->verbs_dev.n_txwait; 1694 } 1695 1696 static u64 access_sw_kmem_wait(const struct cntr_entry *entry, 1697 void *context, int vl, int mode, u64 data) 1698 { 1699 struct hfi1_devdata *dd = context; 1700 1701 return dd->verbs_dev.n_kmem_wait; 1702 } 1703 1704 static u64 access_sw_send_schedule(const struct cntr_entry *entry, 1705 void *context, int vl, int mode, u64 data) 1706 { 1707 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1708 1709 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl, 1710 mode, data); 1711 } 1712 1713 /* Software counters for the error status bits within MISC_ERR_STATUS */ 1714 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry, 1715 void *context, int vl, int mode, 1716 u64 data) 1717 { 1718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1719 1720 return dd->misc_err_status_cnt[12]; 1721 } 1722 1723 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry, 1724 void *context, int vl, int mode, 1725 u64 data) 1726 { 1727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1728 1729 return dd->misc_err_status_cnt[11]; 1730 } 1731 1732 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry, 1733 void *context, int vl, int mode, 1734 u64 data) 1735 { 1736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1737 1738 return dd->misc_err_status_cnt[10]; 1739 } 1740 1741 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry, 1742 void *context, int vl, 1743 int mode, u64 data) 1744 { 1745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1746 1747 return dd->misc_err_status_cnt[9]; 1748 } 1749 1750 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry, 1751 void *context, int vl, int mode, 1752 u64 data) 1753 { 1754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1755 1756 return dd->misc_err_status_cnt[8]; 1757 } 1758 1759 static u64 access_misc_efuse_read_bad_addr_err_cnt( 1760 const struct cntr_entry *entry, 1761 void *context, int vl, int mode, u64 data) 1762 { 1763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1764 1765 return dd->misc_err_status_cnt[7]; 1766 } 1767 1768 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry, 1769 void *context, int vl, 1770 int mode, u64 data) 1771 { 1772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1773 1774 return dd->misc_err_status_cnt[6]; 1775 } 1776 1777 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry, 1778 void *context, int vl, int mode, 1779 u64 data) 1780 { 1781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1782 1783 return dd->misc_err_status_cnt[5]; 1784 } 1785 1786 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry, 1787 void *context, int vl, int mode, 1788 u64 data) 1789 { 1790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1791 1792 return dd->misc_err_status_cnt[4]; 1793 } 1794 1795 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry, 1796 void *context, int vl, 1797 int mode, u64 data) 1798 { 1799 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1800 1801 return dd->misc_err_status_cnt[3]; 1802 } 1803 1804 static u64 access_misc_csr_write_bad_addr_err_cnt( 1805 const struct cntr_entry *entry, 1806 void *context, int vl, int mode, u64 data) 1807 { 1808 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1809 1810 return dd->misc_err_status_cnt[2]; 1811 } 1812 1813 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1814 void *context, int vl, 1815 int mode, u64 data) 1816 { 1817 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1818 1819 return dd->misc_err_status_cnt[1]; 1820 } 1821 1822 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry, 1823 void *context, int vl, int mode, 1824 u64 data) 1825 { 1826 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1827 1828 return dd->misc_err_status_cnt[0]; 1829 } 1830 1831 /* 1832 * Software counter for the aggregate of 1833 * individual CceErrStatus counters 1834 */ 1835 static u64 access_sw_cce_err_status_aggregated_cnt( 1836 const struct cntr_entry *entry, 1837 void *context, int vl, int mode, u64 data) 1838 { 1839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1840 1841 return dd->sw_cce_err_status_aggregate; 1842 } 1843 1844 /* 1845 * Software counters corresponding to each of the 1846 * error status bits within CceErrStatus 1847 */ 1848 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry, 1849 void *context, int vl, int mode, 1850 u64 data) 1851 { 1852 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1853 1854 return dd->cce_err_status_cnt[40]; 1855 } 1856 1857 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry, 1858 void *context, int vl, int mode, 1859 u64 data) 1860 { 1861 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1862 1863 return dd->cce_err_status_cnt[39]; 1864 } 1865 1866 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry, 1867 void *context, int vl, int mode, 1868 u64 data) 1869 { 1870 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1871 1872 return dd->cce_err_status_cnt[38]; 1873 } 1874 1875 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry, 1876 void *context, int vl, int mode, 1877 u64 data) 1878 { 1879 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1880 1881 return dd->cce_err_status_cnt[37]; 1882 } 1883 1884 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry, 1885 void *context, int vl, int mode, 1886 u64 data) 1887 { 1888 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1889 1890 return dd->cce_err_status_cnt[36]; 1891 } 1892 1893 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt( 1894 const struct cntr_entry *entry, 1895 void *context, int vl, int mode, u64 data) 1896 { 1897 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1898 1899 return dd->cce_err_status_cnt[35]; 1900 } 1901 1902 static u64 access_cce_rcpl_async_fifo_parity_err_cnt( 1903 const struct cntr_entry *entry, 1904 void *context, int vl, int mode, u64 data) 1905 { 1906 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1907 1908 return dd->cce_err_status_cnt[34]; 1909 } 1910 1911 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry, 1912 void *context, int vl, 1913 int mode, u64 data) 1914 { 1915 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1916 1917 return dd->cce_err_status_cnt[33]; 1918 } 1919 1920 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1921 void *context, int vl, int mode, 1922 u64 data) 1923 { 1924 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1925 1926 return dd->cce_err_status_cnt[32]; 1927 } 1928 1929 static u64 access_la_triggered_cnt(const struct cntr_entry *entry, 1930 void *context, int vl, int mode, u64 data) 1931 { 1932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1933 1934 return dd->cce_err_status_cnt[31]; 1935 } 1936 1937 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry, 1938 void *context, int vl, int mode, 1939 u64 data) 1940 { 1941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1942 1943 return dd->cce_err_status_cnt[30]; 1944 } 1945 1946 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry, 1947 void *context, int vl, int mode, 1948 u64 data) 1949 { 1950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1951 1952 return dd->cce_err_status_cnt[29]; 1953 } 1954 1955 static u64 access_pcic_transmit_back_parity_err_cnt( 1956 const struct cntr_entry *entry, 1957 void *context, int vl, int mode, u64 data) 1958 { 1959 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1960 1961 return dd->cce_err_status_cnt[28]; 1962 } 1963 1964 static u64 access_pcic_transmit_front_parity_err_cnt( 1965 const struct cntr_entry *entry, 1966 void *context, int vl, int mode, u64 data) 1967 { 1968 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1969 1970 return dd->cce_err_status_cnt[27]; 1971 } 1972 1973 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry, 1974 void *context, int vl, int mode, 1975 u64 data) 1976 { 1977 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1978 1979 return dd->cce_err_status_cnt[26]; 1980 } 1981 1982 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry, 1983 void *context, int vl, int mode, 1984 u64 data) 1985 { 1986 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1987 1988 return dd->cce_err_status_cnt[25]; 1989 } 1990 1991 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry, 1992 void *context, int vl, int mode, 1993 u64 data) 1994 { 1995 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1996 1997 return dd->cce_err_status_cnt[24]; 1998 } 1999 2000 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2001 void *context, int vl, int mode, 2002 u64 data) 2003 { 2004 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2005 2006 return dd->cce_err_status_cnt[23]; 2007 } 2008 2009 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry, 2010 void *context, int vl, 2011 int mode, u64 data) 2012 { 2013 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2014 2015 return dd->cce_err_status_cnt[22]; 2016 } 2017 2018 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry, 2019 void *context, int vl, int mode, 2020 u64 data) 2021 { 2022 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2023 2024 return dd->cce_err_status_cnt[21]; 2025 } 2026 2027 static u64 access_pcic_n_post_dat_q_parity_err_cnt( 2028 const struct cntr_entry *entry, 2029 void *context, int vl, int mode, u64 data) 2030 { 2031 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2032 2033 return dd->cce_err_status_cnt[20]; 2034 } 2035 2036 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry, 2037 void *context, int vl, 2038 int mode, u64 data) 2039 { 2040 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2041 2042 return dd->cce_err_status_cnt[19]; 2043 } 2044 2045 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2046 void *context, int vl, int mode, 2047 u64 data) 2048 { 2049 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2050 2051 return dd->cce_err_status_cnt[18]; 2052 } 2053 2054 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2055 void *context, int vl, int mode, 2056 u64 data) 2057 { 2058 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2059 2060 return dd->cce_err_status_cnt[17]; 2061 } 2062 2063 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2064 void *context, int vl, int mode, 2065 u64 data) 2066 { 2067 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2068 2069 return dd->cce_err_status_cnt[16]; 2070 } 2071 2072 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2073 void *context, int vl, int mode, 2074 u64 data) 2075 { 2076 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2077 2078 return dd->cce_err_status_cnt[15]; 2079 } 2080 2081 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry, 2082 void *context, int vl, 2083 int mode, u64 data) 2084 { 2085 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2086 2087 return dd->cce_err_status_cnt[14]; 2088 } 2089 2090 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry, 2091 void *context, int vl, int mode, 2092 u64 data) 2093 { 2094 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2095 2096 return dd->cce_err_status_cnt[13]; 2097 } 2098 2099 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt( 2100 const struct cntr_entry *entry, 2101 void *context, int vl, int mode, u64 data) 2102 { 2103 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2104 2105 return dd->cce_err_status_cnt[12]; 2106 } 2107 2108 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt( 2109 const struct cntr_entry *entry, 2110 void *context, int vl, int mode, u64 data) 2111 { 2112 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2113 2114 return dd->cce_err_status_cnt[11]; 2115 } 2116 2117 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt( 2118 const struct cntr_entry *entry, 2119 void *context, int vl, int mode, u64 data) 2120 { 2121 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2122 2123 return dd->cce_err_status_cnt[10]; 2124 } 2125 2126 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt( 2127 const struct cntr_entry *entry, 2128 void *context, int vl, int mode, u64 data) 2129 { 2130 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2131 2132 return dd->cce_err_status_cnt[9]; 2133 } 2134 2135 static u64 access_cce_cli2_async_fifo_parity_err_cnt( 2136 const struct cntr_entry *entry, 2137 void *context, int vl, int mode, u64 data) 2138 { 2139 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2140 2141 return dd->cce_err_status_cnt[8]; 2142 } 2143 2144 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry, 2145 void *context, int vl, 2146 int mode, u64 data) 2147 { 2148 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2149 2150 return dd->cce_err_status_cnt[7]; 2151 } 2152 2153 static u64 access_cce_cli0_async_fifo_parity_err_cnt( 2154 const struct cntr_entry *entry, 2155 void *context, int vl, int mode, u64 data) 2156 { 2157 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2158 2159 return dd->cce_err_status_cnt[6]; 2160 } 2161 2162 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry, 2163 void *context, int vl, int mode, 2164 u64 data) 2165 { 2166 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2167 2168 return dd->cce_err_status_cnt[5]; 2169 } 2170 2171 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry, 2172 void *context, int vl, int mode, 2173 u64 data) 2174 { 2175 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2176 2177 return dd->cce_err_status_cnt[4]; 2178 } 2179 2180 static u64 access_cce_trgt_async_fifo_parity_err_cnt( 2181 const struct cntr_entry *entry, 2182 void *context, int vl, int mode, u64 data) 2183 { 2184 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2185 2186 return dd->cce_err_status_cnt[3]; 2187 } 2188 2189 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2190 void *context, int vl, 2191 int mode, u64 data) 2192 { 2193 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2194 2195 return dd->cce_err_status_cnt[2]; 2196 } 2197 2198 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2199 void *context, int vl, 2200 int mode, u64 data) 2201 { 2202 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2203 2204 return dd->cce_err_status_cnt[1]; 2205 } 2206 2207 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry, 2208 void *context, int vl, int mode, 2209 u64 data) 2210 { 2211 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2212 2213 return dd->cce_err_status_cnt[0]; 2214 } 2215 2216 /* 2217 * Software counters corresponding to each of the 2218 * error status bits within RcvErrStatus 2219 */ 2220 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry, 2221 void *context, int vl, int mode, 2222 u64 data) 2223 { 2224 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2225 2226 return dd->rcv_err_status_cnt[63]; 2227 } 2228 2229 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2230 void *context, int vl, 2231 int mode, u64 data) 2232 { 2233 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2234 2235 return dd->rcv_err_status_cnt[62]; 2236 } 2237 2238 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2239 void *context, int vl, int mode, 2240 u64 data) 2241 { 2242 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2243 2244 return dd->rcv_err_status_cnt[61]; 2245 } 2246 2247 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry, 2248 void *context, int vl, int mode, 2249 u64 data) 2250 { 2251 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2252 2253 return dd->rcv_err_status_cnt[60]; 2254 } 2255 2256 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2257 void *context, int vl, 2258 int mode, u64 data) 2259 { 2260 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2261 2262 return dd->rcv_err_status_cnt[59]; 2263 } 2264 2265 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2266 void *context, int vl, 2267 int mode, u64 data) 2268 { 2269 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2270 2271 return dd->rcv_err_status_cnt[58]; 2272 } 2273 2274 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry, 2275 void *context, int vl, int mode, 2276 u64 data) 2277 { 2278 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2279 2280 return dd->rcv_err_status_cnt[57]; 2281 } 2282 2283 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry, 2284 void *context, int vl, int mode, 2285 u64 data) 2286 { 2287 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2288 2289 return dd->rcv_err_status_cnt[56]; 2290 } 2291 2292 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry, 2293 void *context, int vl, int mode, 2294 u64 data) 2295 { 2296 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2297 2298 return dd->rcv_err_status_cnt[55]; 2299 } 2300 2301 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt( 2302 const struct cntr_entry *entry, 2303 void *context, int vl, int mode, u64 data) 2304 { 2305 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2306 2307 return dd->rcv_err_status_cnt[54]; 2308 } 2309 2310 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt( 2311 const struct cntr_entry *entry, 2312 void *context, int vl, int mode, u64 data) 2313 { 2314 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2315 2316 return dd->rcv_err_status_cnt[53]; 2317 } 2318 2319 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry, 2320 void *context, int vl, 2321 int mode, u64 data) 2322 { 2323 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2324 2325 return dd->rcv_err_status_cnt[52]; 2326 } 2327 2328 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry, 2329 void *context, int vl, 2330 int mode, u64 data) 2331 { 2332 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2333 2334 return dd->rcv_err_status_cnt[51]; 2335 } 2336 2337 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry, 2338 void *context, int vl, 2339 int mode, u64 data) 2340 { 2341 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2342 2343 return dd->rcv_err_status_cnt[50]; 2344 } 2345 2346 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry, 2347 void *context, int vl, 2348 int mode, u64 data) 2349 { 2350 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2351 2352 return dd->rcv_err_status_cnt[49]; 2353 } 2354 2355 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry, 2356 void *context, int vl, 2357 int mode, u64 data) 2358 { 2359 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2360 2361 return dd->rcv_err_status_cnt[48]; 2362 } 2363 2364 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry, 2365 void *context, int vl, 2366 int mode, u64 data) 2367 { 2368 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2369 2370 return dd->rcv_err_status_cnt[47]; 2371 } 2372 2373 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry, 2374 void *context, int vl, int mode, 2375 u64 data) 2376 { 2377 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2378 2379 return dd->rcv_err_status_cnt[46]; 2380 } 2381 2382 static u64 access_rx_hq_intr_csr_parity_err_cnt( 2383 const struct cntr_entry *entry, 2384 void *context, int vl, int mode, u64 data) 2385 { 2386 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2387 2388 return dd->rcv_err_status_cnt[45]; 2389 } 2390 2391 static u64 access_rx_lookup_csr_parity_err_cnt( 2392 const struct cntr_entry *entry, 2393 void *context, int vl, int mode, u64 data) 2394 { 2395 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2396 2397 return dd->rcv_err_status_cnt[44]; 2398 } 2399 2400 static u64 access_rx_lookup_rcv_array_cor_err_cnt( 2401 const struct cntr_entry *entry, 2402 void *context, int vl, int mode, u64 data) 2403 { 2404 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2405 2406 return dd->rcv_err_status_cnt[43]; 2407 } 2408 2409 static u64 access_rx_lookup_rcv_array_unc_err_cnt( 2410 const struct cntr_entry *entry, 2411 void *context, int vl, int mode, u64 data) 2412 { 2413 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2414 2415 return dd->rcv_err_status_cnt[42]; 2416 } 2417 2418 static u64 access_rx_lookup_des_part2_parity_err_cnt( 2419 const struct cntr_entry *entry, 2420 void *context, int vl, int mode, u64 data) 2421 { 2422 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2423 2424 return dd->rcv_err_status_cnt[41]; 2425 } 2426 2427 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt( 2428 const struct cntr_entry *entry, 2429 void *context, int vl, int mode, u64 data) 2430 { 2431 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2432 2433 return dd->rcv_err_status_cnt[40]; 2434 } 2435 2436 static u64 access_rx_lookup_des_part1_unc_err_cnt( 2437 const struct cntr_entry *entry, 2438 void *context, int vl, int mode, u64 data) 2439 { 2440 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2441 2442 return dd->rcv_err_status_cnt[39]; 2443 } 2444 2445 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt( 2446 const struct cntr_entry *entry, 2447 void *context, int vl, int mode, u64 data) 2448 { 2449 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2450 2451 return dd->rcv_err_status_cnt[38]; 2452 } 2453 2454 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt( 2455 const struct cntr_entry *entry, 2456 void *context, int vl, int mode, u64 data) 2457 { 2458 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2459 2460 return dd->rcv_err_status_cnt[37]; 2461 } 2462 2463 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt( 2464 const struct cntr_entry *entry, 2465 void *context, int vl, int mode, u64 data) 2466 { 2467 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2468 2469 return dd->rcv_err_status_cnt[36]; 2470 } 2471 2472 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt( 2473 const struct cntr_entry *entry, 2474 void *context, int vl, int mode, u64 data) 2475 { 2476 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2477 2478 return dd->rcv_err_status_cnt[35]; 2479 } 2480 2481 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt( 2482 const struct cntr_entry *entry, 2483 void *context, int vl, int mode, u64 data) 2484 { 2485 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2486 2487 return dd->rcv_err_status_cnt[34]; 2488 } 2489 2490 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt( 2491 const struct cntr_entry *entry, 2492 void *context, int vl, int mode, u64 data) 2493 { 2494 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2495 2496 return dd->rcv_err_status_cnt[33]; 2497 } 2498 2499 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry, 2500 void *context, int vl, int mode, 2501 u64 data) 2502 { 2503 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2504 2505 return dd->rcv_err_status_cnt[32]; 2506 } 2507 2508 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry, 2509 void *context, int vl, int mode, 2510 u64 data) 2511 { 2512 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2513 2514 return dd->rcv_err_status_cnt[31]; 2515 } 2516 2517 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry, 2518 void *context, int vl, int mode, 2519 u64 data) 2520 { 2521 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2522 2523 return dd->rcv_err_status_cnt[30]; 2524 } 2525 2526 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry, 2527 void *context, int vl, int mode, 2528 u64 data) 2529 { 2530 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2531 2532 return dd->rcv_err_status_cnt[29]; 2533 } 2534 2535 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry, 2536 void *context, int vl, 2537 int mode, u64 data) 2538 { 2539 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2540 2541 return dd->rcv_err_status_cnt[28]; 2542 } 2543 2544 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt( 2545 const struct cntr_entry *entry, 2546 void *context, int vl, int mode, u64 data) 2547 { 2548 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2549 2550 return dd->rcv_err_status_cnt[27]; 2551 } 2552 2553 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt( 2554 const struct cntr_entry *entry, 2555 void *context, int vl, int mode, u64 data) 2556 { 2557 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2558 2559 return dd->rcv_err_status_cnt[26]; 2560 } 2561 2562 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt( 2563 const struct cntr_entry *entry, 2564 void *context, int vl, int mode, u64 data) 2565 { 2566 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2567 2568 return dd->rcv_err_status_cnt[25]; 2569 } 2570 2571 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt( 2572 const struct cntr_entry *entry, 2573 void *context, int vl, int mode, u64 data) 2574 { 2575 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2576 2577 return dd->rcv_err_status_cnt[24]; 2578 } 2579 2580 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt( 2581 const struct cntr_entry *entry, 2582 void *context, int vl, int mode, u64 data) 2583 { 2584 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2585 2586 return dd->rcv_err_status_cnt[23]; 2587 } 2588 2589 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt( 2590 const struct cntr_entry *entry, 2591 void *context, int vl, int mode, u64 data) 2592 { 2593 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2594 2595 return dd->rcv_err_status_cnt[22]; 2596 } 2597 2598 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt( 2599 const struct cntr_entry *entry, 2600 void *context, int vl, int mode, u64 data) 2601 { 2602 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2603 2604 return dd->rcv_err_status_cnt[21]; 2605 } 2606 2607 static u64 access_rx_rbuf_block_list_read_cor_err_cnt( 2608 const struct cntr_entry *entry, 2609 void *context, int vl, int mode, u64 data) 2610 { 2611 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2612 2613 return dd->rcv_err_status_cnt[20]; 2614 } 2615 2616 static u64 access_rx_rbuf_block_list_read_unc_err_cnt( 2617 const struct cntr_entry *entry, 2618 void *context, int vl, int mode, u64 data) 2619 { 2620 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2621 2622 return dd->rcv_err_status_cnt[19]; 2623 } 2624 2625 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry, 2626 void *context, int vl, 2627 int mode, u64 data) 2628 { 2629 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2630 2631 return dd->rcv_err_status_cnt[18]; 2632 } 2633 2634 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry, 2635 void *context, int vl, 2636 int mode, u64 data) 2637 { 2638 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2639 2640 return dd->rcv_err_status_cnt[17]; 2641 } 2642 2643 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt( 2644 const struct cntr_entry *entry, 2645 void *context, int vl, int mode, u64 data) 2646 { 2647 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2648 2649 return dd->rcv_err_status_cnt[16]; 2650 } 2651 2652 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt( 2653 const struct cntr_entry *entry, 2654 void *context, int vl, int mode, u64 data) 2655 { 2656 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2657 2658 return dd->rcv_err_status_cnt[15]; 2659 } 2660 2661 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry, 2662 void *context, int vl, 2663 int mode, u64 data) 2664 { 2665 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2666 2667 return dd->rcv_err_status_cnt[14]; 2668 } 2669 2670 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry, 2671 void *context, int vl, 2672 int mode, u64 data) 2673 { 2674 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2675 2676 return dd->rcv_err_status_cnt[13]; 2677 } 2678 2679 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2680 void *context, int vl, int mode, 2681 u64 data) 2682 { 2683 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2684 2685 return dd->rcv_err_status_cnt[12]; 2686 } 2687 2688 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry, 2689 void *context, int vl, int mode, 2690 u64 data) 2691 { 2692 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2693 2694 return dd->rcv_err_status_cnt[11]; 2695 } 2696 2697 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry, 2698 void *context, int vl, int mode, 2699 u64 data) 2700 { 2701 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2702 2703 return dd->rcv_err_status_cnt[10]; 2704 } 2705 2706 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry, 2707 void *context, int vl, int mode, 2708 u64 data) 2709 { 2710 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2711 2712 return dd->rcv_err_status_cnt[9]; 2713 } 2714 2715 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry, 2716 void *context, int vl, int mode, 2717 u64 data) 2718 { 2719 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2720 2721 return dd->rcv_err_status_cnt[8]; 2722 } 2723 2724 static u64 access_rx_rcv_qp_map_table_cor_err_cnt( 2725 const struct cntr_entry *entry, 2726 void *context, int vl, int mode, u64 data) 2727 { 2728 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2729 2730 return dd->rcv_err_status_cnt[7]; 2731 } 2732 2733 static u64 access_rx_rcv_qp_map_table_unc_err_cnt( 2734 const struct cntr_entry *entry, 2735 void *context, int vl, int mode, u64 data) 2736 { 2737 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2738 2739 return dd->rcv_err_status_cnt[6]; 2740 } 2741 2742 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry, 2743 void *context, int vl, int mode, 2744 u64 data) 2745 { 2746 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2747 2748 return dd->rcv_err_status_cnt[5]; 2749 } 2750 2751 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry, 2752 void *context, int vl, int mode, 2753 u64 data) 2754 { 2755 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2756 2757 return dd->rcv_err_status_cnt[4]; 2758 } 2759 2760 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry, 2761 void *context, int vl, int mode, 2762 u64 data) 2763 { 2764 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2765 2766 return dd->rcv_err_status_cnt[3]; 2767 } 2768 2769 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry, 2770 void *context, int vl, int mode, 2771 u64 data) 2772 { 2773 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2774 2775 return dd->rcv_err_status_cnt[2]; 2776 } 2777 2778 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry, 2779 void *context, int vl, int mode, 2780 u64 data) 2781 { 2782 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2783 2784 return dd->rcv_err_status_cnt[1]; 2785 } 2786 2787 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry, 2788 void *context, int vl, int mode, 2789 u64 data) 2790 { 2791 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2792 2793 return dd->rcv_err_status_cnt[0]; 2794 } 2795 2796 /* 2797 * Software counters corresponding to each of the 2798 * error status bits within SendPioErrStatus 2799 */ 2800 static u64 access_pio_pec_sop_head_parity_err_cnt( 2801 const struct cntr_entry *entry, 2802 void *context, int vl, int mode, u64 data) 2803 { 2804 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2805 2806 return dd->send_pio_err_status_cnt[35]; 2807 } 2808 2809 static u64 access_pio_pcc_sop_head_parity_err_cnt( 2810 const struct cntr_entry *entry, 2811 void *context, int vl, int mode, u64 data) 2812 { 2813 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2814 2815 return dd->send_pio_err_status_cnt[34]; 2816 } 2817 2818 static u64 access_pio_last_returned_cnt_parity_err_cnt( 2819 const struct cntr_entry *entry, 2820 void *context, int vl, int mode, u64 data) 2821 { 2822 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2823 2824 return dd->send_pio_err_status_cnt[33]; 2825 } 2826 2827 static u64 access_pio_current_free_cnt_parity_err_cnt( 2828 const struct cntr_entry *entry, 2829 void *context, int vl, int mode, u64 data) 2830 { 2831 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2832 2833 return dd->send_pio_err_status_cnt[32]; 2834 } 2835 2836 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry, 2837 void *context, int vl, int mode, 2838 u64 data) 2839 { 2840 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2841 2842 return dd->send_pio_err_status_cnt[31]; 2843 } 2844 2845 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry, 2846 void *context, int vl, int mode, 2847 u64 data) 2848 { 2849 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2850 2851 return dd->send_pio_err_status_cnt[30]; 2852 } 2853 2854 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry, 2855 void *context, int vl, int mode, 2856 u64 data) 2857 { 2858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2859 2860 return dd->send_pio_err_status_cnt[29]; 2861 } 2862 2863 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt( 2864 const struct cntr_entry *entry, 2865 void *context, int vl, int mode, u64 data) 2866 { 2867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2868 2869 return dd->send_pio_err_status_cnt[28]; 2870 } 2871 2872 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry, 2873 void *context, int vl, int mode, 2874 u64 data) 2875 { 2876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2877 2878 return dd->send_pio_err_status_cnt[27]; 2879 } 2880 2881 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry, 2882 void *context, int vl, int mode, 2883 u64 data) 2884 { 2885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2886 2887 return dd->send_pio_err_status_cnt[26]; 2888 } 2889 2890 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry, 2891 void *context, int vl, 2892 int mode, u64 data) 2893 { 2894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2895 2896 return dd->send_pio_err_status_cnt[25]; 2897 } 2898 2899 static u64 access_pio_block_qw_count_parity_err_cnt( 2900 const struct cntr_entry *entry, 2901 void *context, int vl, int mode, u64 data) 2902 { 2903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2904 2905 return dd->send_pio_err_status_cnt[24]; 2906 } 2907 2908 static u64 access_pio_write_qw_valid_parity_err_cnt( 2909 const struct cntr_entry *entry, 2910 void *context, int vl, int mode, u64 data) 2911 { 2912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2913 2914 return dd->send_pio_err_status_cnt[23]; 2915 } 2916 2917 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry, 2918 void *context, int vl, int mode, 2919 u64 data) 2920 { 2921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2922 2923 return dd->send_pio_err_status_cnt[22]; 2924 } 2925 2926 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry, 2927 void *context, int vl, 2928 int mode, u64 data) 2929 { 2930 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2931 2932 return dd->send_pio_err_status_cnt[21]; 2933 } 2934 2935 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry, 2936 void *context, int vl, 2937 int mode, u64 data) 2938 { 2939 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2940 2941 return dd->send_pio_err_status_cnt[20]; 2942 } 2943 2944 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry, 2945 void *context, int vl, 2946 int mode, u64 data) 2947 { 2948 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2949 2950 return dd->send_pio_err_status_cnt[19]; 2951 } 2952 2953 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt( 2954 const struct cntr_entry *entry, 2955 void *context, int vl, int mode, u64 data) 2956 { 2957 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2958 2959 return dd->send_pio_err_status_cnt[18]; 2960 } 2961 2962 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry, 2963 void *context, int vl, int mode, 2964 u64 data) 2965 { 2966 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2967 2968 return dd->send_pio_err_status_cnt[17]; 2969 } 2970 2971 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry, 2972 void *context, int vl, int mode, 2973 u64 data) 2974 { 2975 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2976 2977 return dd->send_pio_err_status_cnt[16]; 2978 } 2979 2980 static u64 access_pio_credit_ret_fifo_parity_err_cnt( 2981 const struct cntr_entry *entry, 2982 void *context, int vl, int mode, u64 data) 2983 { 2984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2985 2986 return dd->send_pio_err_status_cnt[15]; 2987 } 2988 2989 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt( 2990 const struct cntr_entry *entry, 2991 void *context, int vl, int mode, u64 data) 2992 { 2993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2994 2995 return dd->send_pio_err_status_cnt[14]; 2996 } 2997 2998 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt( 2999 const struct cntr_entry *entry, 3000 void *context, int vl, int mode, u64 data) 3001 { 3002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3003 3004 return dd->send_pio_err_status_cnt[13]; 3005 } 3006 3007 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt( 3008 const struct cntr_entry *entry, 3009 void *context, int vl, int mode, u64 data) 3010 { 3011 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3012 3013 return dd->send_pio_err_status_cnt[12]; 3014 } 3015 3016 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt( 3017 const struct cntr_entry *entry, 3018 void *context, int vl, int mode, u64 data) 3019 { 3020 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3021 3022 return dd->send_pio_err_status_cnt[11]; 3023 } 3024 3025 static u64 access_pio_sm_pkt_reset_parity_err_cnt( 3026 const struct cntr_entry *entry, 3027 void *context, int vl, int mode, u64 data) 3028 { 3029 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3030 3031 return dd->send_pio_err_status_cnt[10]; 3032 } 3033 3034 static u64 access_pio_pkt_evict_fifo_parity_err_cnt( 3035 const struct cntr_entry *entry, 3036 void *context, int vl, int mode, u64 data) 3037 { 3038 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3039 3040 return dd->send_pio_err_status_cnt[9]; 3041 } 3042 3043 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt( 3044 const struct cntr_entry *entry, 3045 void *context, int vl, int mode, u64 data) 3046 { 3047 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3048 3049 return dd->send_pio_err_status_cnt[8]; 3050 } 3051 3052 static u64 access_pio_sbrdctl_crrel_parity_err_cnt( 3053 const struct cntr_entry *entry, 3054 void *context, int vl, int mode, u64 data) 3055 { 3056 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3057 3058 return dd->send_pio_err_status_cnt[7]; 3059 } 3060 3061 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry, 3062 void *context, int vl, int mode, 3063 u64 data) 3064 { 3065 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3066 3067 return dd->send_pio_err_status_cnt[6]; 3068 } 3069 3070 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry, 3071 void *context, int vl, int mode, 3072 u64 data) 3073 { 3074 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3075 3076 return dd->send_pio_err_status_cnt[5]; 3077 } 3078 3079 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry, 3080 void *context, int vl, int mode, 3081 u64 data) 3082 { 3083 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3084 3085 return dd->send_pio_err_status_cnt[4]; 3086 } 3087 3088 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry, 3089 void *context, int vl, int mode, 3090 u64 data) 3091 { 3092 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3093 3094 return dd->send_pio_err_status_cnt[3]; 3095 } 3096 3097 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry, 3098 void *context, int vl, int mode, 3099 u64 data) 3100 { 3101 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3102 3103 return dd->send_pio_err_status_cnt[2]; 3104 } 3105 3106 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry, 3107 void *context, int vl, 3108 int mode, u64 data) 3109 { 3110 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3111 3112 return dd->send_pio_err_status_cnt[1]; 3113 } 3114 3115 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry, 3116 void *context, int vl, int mode, 3117 u64 data) 3118 { 3119 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3120 3121 return dd->send_pio_err_status_cnt[0]; 3122 } 3123 3124 /* 3125 * Software counters corresponding to each of the 3126 * error status bits within SendDmaErrStatus 3127 */ 3128 static u64 access_sdma_pcie_req_tracking_cor_err_cnt( 3129 const struct cntr_entry *entry, 3130 void *context, int vl, int mode, u64 data) 3131 { 3132 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3133 3134 return dd->send_dma_err_status_cnt[3]; 3135 } 3136 3137 static u64 access_sdma_pcie_req_tracking_unc_err_cnt( 3138 const struct cntr_entry *entry, 3139 void *context, int vl, int mode, u64 data) 3140 { 3141 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3142 3143 return dd->send_dma_err_status_cnt[2]; 3144 } 3145 3146 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry, 3147 void *context, int vl, int mode, 3148 u64 data) 3149 { 3150 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3151 3152 return dd->send_dma_err_status_cnt[1]; 3153 } 3154 3155 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry, 3156 void *context, int vl, int mode, 3157 u64 data) 3158 { 3159 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3160 3161 return dd->send_dma_err_status_cnt[0]; 3162 } 3163 3164 /* 3165 * Software counters corresponding to each of the 3166 * error status bits within SendEgressErrStatus 3167 */ 3168 static u64 access_tx_read_pio_memory_csr_unc_err_cnt( 3169 const struct cntr_entry *entry, 3170 void *context, int vl, int mode, u64 data) 3171 { 3172 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3173 3174 return dd->send_egress_err_status_cnt[63]; 3175 } 3176 3177 static u64 access_tx_read_sdma_memory_csr_err_cnt( 3178 const struct cntr_entry *entry, 3179 void *context, int vl, int mode, u64 data) 3180 { 3181 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3182 3183 return dd->send_egress_err_status_cnt[62]; 3184 } 3185 3186 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry, 3187 void *context, int vl, int mode, 3188 u64 data) 3189 { 3190 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3191 3192 return dd->send_egress_err_status_cnt[61]; 3193 } 3194 3195 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry, 3196 void *context, int vl, 3197 int mode, u64 data) 3198 { 3199 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3200 3201 return dd->send_egress_err_status_cnt[60]; 3202 } 3203 3204 static u64 access_tx_read_sdma_memory_cor_err_cnt( 3205 const struct cntr_entry *entry, 3206 void *context, int vl, int mode, u64 data) 3207 { 3208 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3209 3210 return dd->send_egress_err_status_cnt[59]; 3211 } 3212 3213 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry, 3214 void *context, int vl, int mode, 3215 u64 data) 3216 { 3217 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3218 3219 return dd->send_egress_err_status_cnt[58]; 3220 } 3221 3222 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry, 3223 void *context, int vl, int mode, 3224 u64 data) 3225 { 3226 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3227 3228 return dd->send_egress_err_status_cnt[57]; 3229 } 3230 3231 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry, 3232 void *context, int vl, int mode, 3233 u64 data) 3234 { 3235 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3236 3237 return dd->send_egress_err_status_cnt[56]; 3238 } 3239 3240 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry, 3241 void *context, int vl, int mode, 3242 u64 data) 3243 { 3244 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3245 3246 return dd->send_egress_err_status_cnt[55]; 3247 } 3248 3249 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry, 3250 void *context, int vl, int mode, 3251 u64 data) 3252 { 3253 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3254 3255 return dd->send_egress_err_status_cnt[54]; 3256 } 3257 3258 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry, 3259 void *context, int vl, int mode, 3260 u64 data) 3261 { 3262 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3263 3264 return dd->send_egress_err_status_cnt[53]; 3265 } 3266 3267 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry, 3268 void *context, int vl, int mode, 3269 u64 data) 3270 { 3271 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3272 3273 return dd->send_egress_err_status_cnt[52]; 3274 } 3275 3276 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry, 3277 void *context, int vl, int mode, 3278 u64 data) 3279 { 3280 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3281 3282 return dd->send_egress_err_status_cnt[51]; 3283 } 3284 3285 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry, 3286 void *context, int vl, int mode, 3287 u64 data) 3288 { 3289 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3290 3291 return dd->send_egress_err_status_cnt[50]; 3292 } 3293 3294 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry, 3295 void *context, int vl, int mode, 3296 u64 data) 3297 { 3298 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3299 3300 return dd->send_egress_err_status_cnt[49]; 3301 } 3302 3303 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry, 3304 void *context, int vl, int mode, 3305 u64 data) 3306 { 3307 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3308 3309 return dd->send_egress_err_status_cnt[48]; 3310 } 3311 3312 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry, 3313 void *context, int vl, int mode, 3314 u64 data) 3315 { 3316 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3317 3318 return dd->send_egress_err_status_cnt[47]; 3319 } 3320 3321 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry, 3322 void *context, int vl, int mode, 3323 u64 data) 3324 { 3325 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3326 3327 return dd->send_egress_err_status_cnt[46]; 3328 } 3329 3330 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry, 3331 void *context, int vl, int mode, 3332 u64 data) 3333 { 3334 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3335 3336 return dd->send_egress_err_status_cnt[45]; 3337 } 3338 3339 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry, 3340 void *context, int vl, 3341 int mode, u64 data) 3342 { 3343 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3344 3345 return dd->send_egress_err_status_cnt[44]; 3346 } 3347 3348 static u64 access_tx_read_sdma_memory_unc_err_cnt( 3349 const struct cntr_entry *entry, 3350 void *context, int vl, int mode, u64 data) 3351 { 3352 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3353 3354 return dd->send_egress_err_status_cnt[43]; 3355 } 3356 3357 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry, 3358 void *context, int vl, int mode, 3359 u64 data) 3360 { 3361 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3362 3363 return dd->send_egress_err_status_cnt[42]; 3364 } 3365 3366 static u64 access_tx_credit_return_partiy_err_cnt( 3367 const struct cntr_entry *entry, 3368 void *context, int vl, int mode, u64 data) 3369 { 3370 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3371 3372 return dd->send_egress_err_status_cnt[41]; 3373 } 3374 3375 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt( 3376 const struct cntr_entry *entry, 3377 void *context, int vl, int mode, u64 data) 3378 { 3379 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3380 3381 return dd->send_egress_err_status_cnt[40]; 3382 } 3383 3384 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt( 3385 const struct cntr_entry *entry, 3386 void *context, int vl, int mode, u64 data) 3387 { 3388 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3389 3390 return dd->send_egress_err_status_cnt[39]; 3391 } 3392 3393 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt( 3394 const struct cntr_entry *entry, 3395 void *context, int vl, int mode, u64 data) 3396 { 3397 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3398 3399 return dd->send_egress_err_status_cnt[38]; 3400 } 3401 3402 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt( 3403 const struct cntr_entry *entry, 3404 void *context, int vl, int mode, u64 data) 3405 { 3406 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3407 3408 return dd->send_egress_err_status_cnt[37]; 3409 } 3410 3411 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt( 3412 const struct cntr_entry *entry, 3413 void *context, int vl, int mode, u64 data) 3414 { 3415 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3416 3417 return dd->send_egress_err_status_cnt[36]; 3418 } 3419 3420 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt( 3421 const struct cntr_entry *entry, 3422 void *context, int vl, int mode, u64 data) 3423 { 3424 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3425 3426 return dd->send_egress_err_status_cnt[35]; 3427 } 3428 3429 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt( 3430 const struct cntr_entry *entry, 3431 void *context, int vl, int mode, u64 data) 3432 { 3433 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3434 3435 return dd->send_egress_err_status_cnt[34]; 3436 } 3437 3438 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt( 3439 const struct cntr_entry *entry, 3440 void *context, int vl, int mode, u64 data) 3441 { 3442 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3443 3444 return dd->send_egress_err_status_cnt[33]; 3445 } 3446 3447 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt( 3448 const struct cntr_entry *entry, 3449 void *context, int vl, int mode, u64 data) 3450 { 3451 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3452 3453 return dd->send_egress_err_status_cnt[32]; 3454 } 3455 3456 static u64 access_tx_sdma15_disallowed_packet_err_cnt( 3457 const struct cntr_entry *entry, 3458 void *context, int vl, int mode, u64 data) 3459 { 3460 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3461 3462 return dd->send_egress_err_status_cnt[31]; 3463 } 3464 3465 static u64 access_tx_sdma14_disallowed_packet_err_cnt( 3466 const struct cntr_entry *entry, 3467 void *context, int vl, int mode, u64 data) 3468 { 3469 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3470 3471 return dd->send_egress_err_status_cnt[30]; 3472 } 3473 3474 static u64 access_tx_sdma13_disallowed_packet_err_cnt( 3475 const struct cntr_entry *entry, 3476 void *context, int vl, int mode, u64 data) 3477 { 3478 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3479 3480 return dd->send_egress_err_status_cnt[29]; 3481 } 3482 3483 static u64 access_tx_sdma12_disallowed_packet_err_cnt( 3484 const struct cntr_entry *entry, 3485 void *context, int vl, int mode, u64 data) 3486 { 3487 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3488 3489 return dd->send_egress_err_status_cnt[28]; 3490 } 3491 3492 static u64 access_tx_sdma11_disallowed_packet_err_cnt( 3493 const struct cntr_entry *entry, 3494 void *context, int vl, int mode, u64 data) 3495 { 3496 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3497 3498 return dd->send_egress_err_status_cnt[27]; 3499 } 3500 3501 static u64 access_tx_sdma10_disallowed_packet_err_cnt( 3502 const struct cntr_entry *entry, 3503 void *context, int vl, int mode, u64 data) 3504 { 3505 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3506 3507 return dd->send_egress_err_status_cnt[26]; 3508 } 3509 3510 static u64 access_tx_sdma9_disallowed_packet_err_cnt( 3511 const struct cntr_entry *entry, 3512 void *context, int vl, int mode, u64 data) 3513 { 3514 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3515 3516 return dd->send_egress_err_status_cnt[25]; 3517 } 3518 3519 static u64 access_tx_sdma8_disallowed_packet_err_cnt( 3520 const struct cntr_entry *entry, 3521 void *context, int vl, int mode, u64 data) 3522 { 3523 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3524 3525 return dd->send_egress_err_status_cnt[24]; 3526 } 3527 3528 static u64 access_tx_sdma7_disallowed_packet_err_cnt( 3529 const struct cntr_entry *entry, 3530 void *context, int vl, int mode, u64 data) 3531 { 3532 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3533 3534 return dd->send_egress_err_status_cnt[23]; 3535 } 3536 3537 static u64 access_tx_sdma6_disallowed_packet_err_cnt( 3538 const struct cntr_entry *entry, 3539 void *context, int vl, int mode, u64 data) 3540 { 3541 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3542 3543 return dd->send_egress_err_status_cnt[22]; 3544 } 3545 3546 static u64 access_tx_sdma5_disallowed_packet_err_cnt( 3547 const struct cntr_entry *entry, 3548 void *context, int vl, int mode, u64 data) 3549 { 3550 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3551 3552 return dd->send_egress_err_status_cnt[21]; 3553 } 3554 3555 static u64 access_tx_sdma4_disallowed_packet_err_cnt( 3556 const struct cntr_entry *entry, 3557 void *context, int vl, int mode, u64 data) 3558 { 3559 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3560 3561 return dd->send_egress_err_status_cnt[20]; 3562 } 3563 3564 static u64 access_tx_sdma3_disallowed_packet_err_cnt( 3565 const struct cntr_entry *entry, 3566 void *context, int vl, int mode, u64 data) 3567 { 3568 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3569 3570 return dd->send_egress_err_status_cnt[19]; 3571 } 3572 3573 static u64 access_tx_sdma2_disallowed_packet_err_cnt( 3574 const struct cntr_entry *entry, 3575 void *context, int vl, int mode, u64 data) 3576 { 3577 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3578 3579 return dd->send_egress_err_status_cnt[18]; 3580 } 3581 3582 static u64 access_tx_sdma1_disallowed_packet_err_cnt( 3583 const struct cntr_entry *entry, 3584 void *context, int vl, int mode, u64 data) 3585 { 3586 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3587 3588 return dd->send_egress_err_status_cnt[17]; 3589 } 3590 3591 static u64 access_tx_sdma0_disallowed_packet_err_cnt( 3592 const struct cntr_entry *entry, 3593 void *context, int vl, int mode, u64 data) 3594 { 3595 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3596 3597 return dd->send_egress_err_status_cnt[16]; 3598 } 3599 3600 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry, 3601 void *context, int vl, int mode, 3602 u64 data) 3603 { 3604 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3605 3606 return dd->send_egress_err_status_cnt[15]; 3607 } 3608 3609 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry, 3610 void *context, int vl, 3611 int mode, u64 data) 3612 { 3613 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3614 3615 return dd->send_egress_err_status_cnt[14]; 3616 } 3617 3618 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry, 3619 void *context, int vl, int mode, 3620 u64 data) 3621 { 3622 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3623 3624 return dd->send_egress_err_status_cnt[13]; 3625 } 3626 3627 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry, 3628 void *context, int vl, int mode, 3629 u64 data) 3630 { 3631 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3632 3633 return dd->send_egress_err_status_cnt[12]; 3634 } 3635 3636 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt( 3637 const struct cntr_entry *entry, 3638 void *context, int vl, int mode, u64 data) 3639 { 3640 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3641 3642 return dd->send_egress_err_status_cnt[11]; 3643 } 3644 3645 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry, 3646 void *context, int vl, int mode, 3647 u64 data) 3648 { 3649 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3650 3651 return dd->send_egress_err_status_cnt[10]; 3652 } 3653 3654 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry, 3655 void *context, int vl, int mode, 3656 u64 data) 3657 { 3658 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3659 3660 return dd->send_egress_err_status_cnt[9]; 3661 } 3662 3663 static u64 access_tx_sdma_launch_intf_parity_err_cnt( 3664 const struct cntr_entry *entry, 3665 void *context, int vl, int mode, u64 data) 3666 { 3667 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3668 3669 return dd->send_egress_err_status_cnt[8]; 3670 } 3671 3672 static u64 access_tx_pio_launch_intf_parity_err_cnt( 3673 const struct cntr_entry *entry, 3674 void *context, int vl, int mode, u64 data) 3675 { 3676 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3677 3678 return dd->send_egress_err_status_cnt[7]; 3679 } 3680 3681 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry, 3682 void *context, int vl, int mode, 3683 u64 data) 3684 { 3685 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3686 3687 return dd->send_egress_err_status_cnt[6]; 3688 } 3689 3690 static u64 access_tx_incorrect_link_state_err_cnt( 3691 const struct cntr_entry *entry, 3692 void *context, int vl, int mode, u64 data) 3693 { 3694 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3695 3696 return dd->send_egress_err_status_cnt[5]; 3697 } 3698 3699 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry, 3700 void *context, int vl, int mode, 3701 u64 data) 3702 { 3703 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3704 3705 return dd->send_egress_err_status_cnt[4]; 3706 } 3707 3708 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt( 3709 const struct cntr_entry *entry, 3710 void *context, int vl, int mode, u64 data) 3711 { 3712 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3713 3714 return dd->send_egress_err_status_cnt[3]; 3715 } 3716 3717 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry, 3718 void *context, int vl, int mode, 3719 u64 data) 3720 { 3721 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3722 3723 return dd->send_egress_err_status_cnt[2]; 3724 } 3725 3726 static u64 access_tx_pkt_integrity_mem_unc_err_cnt( 3727 const struct cntr_entry *entry, 3728 void *context, int vl, int mode, u64 data) 3729 { 3730 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3731 3732 return dd->send_egress_err_status_cnt[1]; 3733 } 3734 3735 static u64 access_tx_pkt_integrity_mem_cor_err_cnt( 3736 const struct cntr_entry *entry, 3737 void *context, int vl, int mode, u64 data) 3738 { 3739 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3740 3741 return dd->send_egress_err_status_cnt[0]; 3742 } 3743 3744 /* 3745 * Software counters corresponding to each of the 3746 * error status bits within SendErrStatus 3747 */ 3748 static u64 access_send_csr_write_bad_addr_err_cnt( 3749 const struct cntr_entry *entry, 3750 void *context, int vl, int mode, u64 data) 3751 { 3752 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3753 3754 return dd->send_err_status_cnt[2]; 3755 } 3756 3757 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 3758 void *context, int vl, 3759 int mode, u64 data) 3760 { 3761 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3762 3763 return dd->send_err_status_cnt[1]; 3764 } 3765 3766 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry, 3767 void *context, int vl, int mode, 3768 u64 data) 3769 { 3770 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3771 3772 return dd->send_err_status_cnt[0]; 3773 } 3774 3775 /* 3776 * Software counters corresponding to each of the 3777 * error status bits within SendCtxtErrStatus 3778 */ 3779 static u64 access_pio_write_out_of_bounds_err_cnt( 3780 const struct cntr_entry *entry, 3781 void *context, int vl, int mode, u64 data) 3782 { 3783 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3784 3785 return dd->sw_ctxt_err_status_cnt[4]; 3786 } 3787 3788 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry, 3789 void *context, int vl, int mode, 3790 u64 data) 3791 { 3792 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3793 3794 return dd->sw_ctxt_err_status_cnt[3]; 3795 } 3796 3797 static u64 access_pio_write_crosses_boundary_err_cnt( 3798 const struct cntr_entry *entry, 3799 void *context, int vl, int mode, u64 data) 3800 { 3801 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3802 3803 return dd->sw_ctxt_err_status_cnt[2]; 3804 } 3805 3806 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry, 3807 void *context, int vl, 3808 int mode, u64 data) 3809 { 3810 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3811 3812 return dd->sw_ctxt_err_status_cnt[1]; 3813 } 3814 3815 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry, 3816 void *context, int vl, int mode, 3817 u64 data) 3818 { 3819 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3820 3821 return dd->sw_ctxt_err_status_cnt[0]; 3822 } 3823 3824 /* 3825 * Software counters corresponding to each of the 3826 * error status bits within SendDmaEngErrStatus 3827 */ 3828 static u64 access_sdma_header_request_fifo_cor_err_cnt( 3829 const struct cntr_entry *entry, 3830 void *context, int vl, int mode, u64 data) 3831 { 3832 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3833 3834 return dd->sw_send_dma_eng_err_status_cnt[23]; 3835 } 3836 3837 static u64 access_sdma_header_storage_cor_err_cnt( 3838 const struct cntr_entry *entry, 3839 void *context, int vl, int mode, u64 data) 3840 { 3841 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3842 3843 return dd->sw_send_dma_eng_err_status_cnt[22]; 3844 } 3845 3846 static u64 access_sdma_packet_tracking_cor_err_cnt( 3847 const struct cntr_entry *entry, 3848 void *context, int vl, int mode, u64 data) 3849 { 3850 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3851 3852 return dd->sw_send_dma_eng_err_status_cnt[21]; 3853 } 3854 3855 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry, 3856 void *context, int vl, int mode, 3857 u64 data) 3858 { 3859 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3860 3861 return dd->sw_send_dma_eng_err_status_cnt[20]; 3862 } 3863 3864 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry, 3865 void *context, int vl, int mode, 3866 u64 data) 3867 { 3868 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3869 3870 return dd->sw_send_dma_eng_err_status_cnt[19]; 3871 } 3872 3873 static u64 access_sdma_header_request_fifo_unc_err_cnt( 3874 const struct cntr_entry *entry, 3875 void *context, int vl, int mode, u64 data) 3876 { 3877 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3878 3879 return dd->sw_send_dma_eng_err_status_cnt[18]; 3880 } 3881 3882 static u64 access_sdma_header_storage_unc_err_cnt( 3883 const struct cntr_entry *entry, 3884 void *context, int vl, int mode, u64 data) 3885 { 3886 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3887 3888 return dd->sw_send_dma_eng_err_status_cnt[17]; 3889 } 3890 3891 static u64 access_sdma_packet_tracking_unc_err_cnt( 3892 const struct cntr_entry *entry, 3893 void *context, int vl, int mode, u64 data) 3894 { 3895 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3896 3897 return dd->sw_send_dma_eng_err_status_cnt[16]; 3898 } 3899 3900 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry, 3901 void *context, int vl, int mode, 3902 u64 data) 3903 { 3904 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3905 3906 return dd->sw_send_dma_eng_err_status_cnt[15]; 3907 } 3908 3909 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry, 3910 void *context, int vl, int mode, 3911 u64 data) 3912 { 3913 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3914 3915 return dd->sw_send_dma_eng_err_status_cnt[14]; 3916 } 3917 3918 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry, 3919 void *context, int vl, int mode, 3920 u64 data) 3921 { 3922 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3923 3924 return dd->sw_send_dma_eng_err_status_cnt[13]; 3925 } 3926 3927 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry, 3928 void *context, int vl, int mode, 3929 u64 data) 3930 { 3931 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3932 3933 return dd->sw_send_dma_eng_err_status_cnt[12]; 3934 } 3935 3936 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry, 3937 void *context, int vl, int mode, 3938 u64 data) 3939 { 3940 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3941 3942 return dd->sw_send_dma_eng_err_status_cnt[11]; 3943 } 3944 3945 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry, 3946 void *context, int vl, int mode, 3947 u64 data) 3948 { 3949 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3950 3951 return dd->sw_send_dma_eng_err_status_cnt[10]; 3952 } 3953 3954 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry, 3955 void *context, int vl, int mode, 3956 u64 data) 3957 { 3958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3959 3960 return dd->sw_send_dma_eng_err_status_cnt[9]; 3961 } 3962 3963 static u64 access_sdma_packet_desc_overflow_err_cnt( 3964 const struct cntr_entry *entry, 3965 void *context, int vl, int mode, u64 data) 3966 { 3967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3968 3969 return dd->sw_send_dma_eng_err_status_cnt[8]; 3970 } 3971 3972 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry, 3973 void *context, int vl, 3974 int mode, u64 data) 3975 { 3976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3977 3978 return dd->sw_send_dma_eng_err_status_cnt[7]; 3979 } 3980 3981 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry, 3982 void *context, int vl, int mode, u64 data) 3983 { 3984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3985 3986 return dd->sw_send_dma_eng_err_status_cnt[6]; 3987 } 3988 3989 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry, 3990 void *context, int vl, int mode, 3991 u64 data) 3992 { 3993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3994 3995 return dd->sw_send_dma_eng_err_status_cnt[5]; 3996 } 3997 3998 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry, 3999 void *context, int vl, int mode, 4000 u64 data) 4001 { 4002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4003 4004 return dd->sw_send_dma_eng_err_status_cnt[4]; 4005 } 4006 4007 static u64 access_sdma_tail_out_of_bounds_err_cnt( 4008 const struct cntr_entry *entry, 4009 void *context, int vl, int mode, u64 data) 4010 { 4011 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4012 4013 return dd->sw_send_dma_eng_err_status_cnt[3]; 4014 } 4015 4016 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry, 4017 void *context, int vl, int mode, 4018 u64 data) 4019 { 4020 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4021 4022 return dd->sw_send_dma_eng_err_status_cnt[2]; 4023 } 4024 4025 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry, 4026 void *context, int vl, int mode, 4027 u64 data) 4028 { 4029 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4030 4031 return dd->sw_send_dma_eng_err_status_cnt[1]; 4032 } 4033 4034 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry, 4035 void *context, int vl, int mode, 4036 u64 data) 4037 { 4038 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4039 4040 return dd->sw_send_dma_eng_err_status_cnt[0]; 4041 } 4042 4043 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry, 4044 void *context, int vl, int mode, 4045 u64 data) 4046 { 4047 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4048 4049 u64 val = 0; 4050 u64 csr = entry->csr; 4051 4052 val = read_write_csr(dd, csr, mode, data); 4053 if (mode == CNTR_MODE_R) { 4054 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ? 4055 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors; 4056 } else if (mode == CNTR_MODE_W) { 4057 dd->sw_rcv_bypass_packet_errors = 0; 4058 } else { 4059 dd_dev_err(dd, "Invalid cntr register access mode"); 4060 return 0; 4061 } 4062 return val; 4063 } 4064 4065 #define def_access_sw_cpu(cntr) \ 4066 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \ 4067 void *context, int vl, int mode, u64 data) \ 4068 { \ 4069 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4070 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \ 4071 ppd->ibport_data.rvp.cntr, vl, \ 4072 mode, data); \ 4073 } 4074 4075 def_access_sw_cpu(rc_acks); 4076 def_access_sw_cpu(rc_qacks); 4077 def_access_sw_cpu(rc_delayed_comp); 4078 4079 #define def_access_ibp_counter(cntr) \ 4080 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \ 4081 void *context, int vl, int mode, u64 data) \ 4082 { \ 4083 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4084 \ 4085 if (vl != CNTR_INVALID_VL) \ 4086 return 0; \ 4087 \ 4088 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \ 4089 mode, data); \ 4090 } 4091 4092 def_access_ibp_counter(loop_pkts); 4093 def_access_ibp_counter(rc_resends); 4094 def_access_ibp_counter(rnr_naks); 4095 def_access_ibp_counter(other_naks); 4096 def_access_ibp_counter(rc_timeouts); 4097 def_access_ibp_counter(pkt_drops); 4098 def_access_ibp_counter(dmawait); 4099 def_access_ibp_counter(rc_seqnak); 4100 def_access_ibp_counter(rc_dupreq); 4101 def_access_ibp_counter(rdma_seq); 4102 def_access_ibp_counter(unaligned); 4103 def_access_ibp_counter(seq_naks); 4104 4105 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = { 4106 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH), 4107 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT, 4108 CNTR_NORMAL), 4109 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT, 4110 CNTR_NORMAL), 4111 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs, 4112 RCV_TID_FLOW_GEN_MISMATCH_CNT, 4113 CNTR_NORMAL), 4114 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL, 4115 CNTR_NORMAL), 4116 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs, 4117 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL), 4118 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt, 4119 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL), 4120 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT, 4121 CNTR_NORMAL), 4122 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT, 4123 CNTR_NORMAL), 4124 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT, 4125 CNTR_NORMAL), 4126 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT, 4127 CNTR_NORMAL), 4128 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT, 4129 CNTR_NORMAL), 4130 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT, 4131 CNTR_NORMAL), 4132 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt, 4133 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL), 4134 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt, 4135 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL), 4136 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT, 4137 CNTR_SYNTH), 4138 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH, 4139 access_dc_rcv_err_cnt), 4140 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT, 4141 CNTR_SYNTH), 4142 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT, 4143 CNTR_SYNTH), 4144 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT, 4145 CNTR_SYNTH), 4146 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts, 4147 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH), 4148 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts, 4149 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT, 4150 CNTR_SYNTH), 4151 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr, 4152 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH), 4153 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT, 4154 CNTR_SYNTH), 4155 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT, 4156 CNTR_SYNTH), 4157 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT, 4158 CNTR_SYNTH), 4159 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT, 4160 CNTR_SYNTH), 4161 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT, 4162 CNTR_SYNTH), 4163 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT, 4164 CNTR_SYNTH), 4165 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT, 4166 CNTR_SYNTH), 4167 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT, 4168 CNTR_SYNTH | CNTR_VL), 4169 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT, 4170 CNTR_SYNTH | CNTR_VL), 4171 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH), 4172 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT, 4173 CNTR_SYNTH | CNTR_VL), 4174 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH), 4175 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT, 4176 CNTR_SYNTH | CNTR_VL), 4177 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT, 4178 CNTR_SYNTH), 4179 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT, 4180 CNTR_SYNTH | CNTR_VL), 4181 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT, 4182 CNTR_SYNTH), 4183 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT, 4184 CNTR_SYNTH | CNTR_VL), 4185 [C_DC_TOTAL_CRC] = 4186 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR, 4187 CNTR_SYNTH), 4188 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0, 4189 CNTR_SYNTH), 4190 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1, 4191 CNTR_SYNTH), 4192 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2, 4193 CNTR_SYNTH), 4194 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3, 4195 CNTR_SYNTH), 4196 [C_DC_CRC_MULT_LN] = 4197 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN, 4198 CNTR_SYNTH), 4199 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT, 4200 CNTR_SYNTH), 4201 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT, 4202 CNTR_SYNTH), 4203 [C_DC_SEQ_CRC_CNT] = 4204 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT, 4205 CNTR_SYNTH), 4206 [C_DC_ESC0_ONLY_CNT] = 4207 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT, 4208 CNTR_SYNTH), 4209 [C_DC_ESC0_PLUS1_CNT] = 4210 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT, 4211 CNTR_SYNTH), 4212 [C_DC_ESC0_PLUS2_CNT] = 4213 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT, 4214 CNTR_SYNTH), 4215 [C_DC_REINIT_FROM_PEER_CNT] = 4216 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 4217 CNTR_SYNTH), 4218 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT, 4219 CNTR_SYNTH), 4220 [C_DC_MISC_FLG_CNT] = 4221 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT, 4222 CNTR_SYNTH), 4223 [C_DC_PRF_GOOD_LTP_CNT] = 4224 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH), 4225 [C_DC_PRF_ACCEPTED_LTP_CNT] = 4226 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT, 4227 CNTR_SYNTH), 4228 [C_DC_PRF_RX_FLIT_CNT] = 4229 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH), 4230 [C_DC_PRF_TX_FLIT_CNT] = 4231 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH), 4232 [C_DC_PRF_CLK_CNTR] = 4233 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH), 4234 [C_DC_PG_DBG_FLIT_CRDTS_CNT] = 4235 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH), 4236 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] = 4237 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT, 4238 CNTR_SYNTH), 4239 [C_DC_PG_STS_TX_SBE_CNT] = 4240 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH), 4241 [C_DC_PG_STS_TX_MBE_CNT] = 4242 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT, 4243 CNTR_SYNTH), 4244 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL, 4245 access_sw_cpu_intr), 4246 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL, 4247 access_sw_cpu_rcv_limit), 4248 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL, 4249 access_sw_vtx_wait), 4250 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL, 4251 access_sw_pio_wait), 4252 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL, 4253 access_sw_pio_drain), 4254 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL, 4255 access_sw_kmem_wait), 4256 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL, 4257 access_sw_send_schedule), 4258 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn", 4259 SEND_DMA_DESC_FETCHED_CNT, 0, 4260 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4261 dev_access_u32_csr), 4262 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0, 4263 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4264 access_sde_int_cnt), 4265 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0, 4266 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4267 access_sde_err_cnt), 4268 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0, 4269 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4270 access_sde_idle_int_cnt), 4271 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0, 4272 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4273 access_sde_progress_int_cnt), 4274 /* MISC_ERR_STATUS */ 4275 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0, 4276 CNTR_NORMAL, 4277 access_misc_pll_lock_fail_err_cnt), 4278 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0, 4279 CNTR_NORMAL, 4280 access_misc_mbist_fail_err_cnt), 4281 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0, 4282 CNTR_NORMAL, 4283 access_misc_invalid_eep_cmd_err_cnt), 4284 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0, 4285 CNTR_NORMAL, 4286 access_misc_efuse_done_parity_err_cnt), 4287 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0, 4288 CNTR_NORMAL, 4289 access_misc_efuse_write_err_cnt), 4290 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0, 4291 0, CNTR_NORMAL, 4292 access_misc_efuse_read_bad_addr_err_cnt), 4293 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0, 4294 CNTR_NORMAL, 4295 access_misc_efuse_csr_parity_err_cnt), 4296 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0, 4297 CNTR_NORMAL, 4298 access_misc_fw_auth_failed_err_cnt), 4299 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0, 4300 CNTR_NORMAL, 4301 access_misc_key_mismatch_err_cnt), 4302 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0, 4303 CNTR_NORMAL, 4304 access_misc_sbus_write_failed_err_cnt), 4305 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0, 4306 CNTR_NORMAL, 4307 access_misc_csr_write_bad_addr_err_cnt), 4308 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0, 4309 CNTR_NORMAL, 4310 access_misc_csr_read_bad_addr_err_cnt), 4311 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0, 4312 CNTR_NORMAL, 4313 access_misc_csr_parity_err_cnt), 4314 /* CceErrStatus */ 4315 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0, 4316 CNTR_NORMAL, 4317 access_sw_cce_err_status_aggregated_cnt), 4318 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0, 4319 CNTR_NORMAL, 4320 access_cce_msix_csr_parity_err_cnt), 4321 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0, 4322 CNTR_NORMAL, 4323 access_cce_int_map_unc_err_cnt), 4324 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0, 4325 CNTR_NORMAL, 4326 access_cce_int_map_cor_err_cnt), 4327 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0, 4328 CNTR_NORMAL, 4329 access_cce_msix_table_unc_err_cnt), 4330 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0, 4331 CNTR_NORMAL, 4332 access_cce_msix_table_cor_err_cnt), 4333 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0, 4334 0, CNTR_NORMAL, 4335 access_cce_rxdma_conv_fifo_parity_err_cnt), 4336 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0, 4337 0, CNTR_NORMAL, 4338 access_cce_rcpl_async_fifo_parity_err_cnt), 4339 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0, 4340 CNTR_NORMAL, 4341 access_cce_seg_write_bad_addr_err_cnt), 4342 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0, 4343 CNTR_NORMAL, 4344 access_cce_seg_read_bad_addr_err_cnt), 4345 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0, 4346 CNTR_NORMAL, 4347 access_la_triggered_cnt), 4348 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0, 4349 CNTR_NORMAL, 4350 access_cce_trgt_cpl_timeout_err_cnt), 4351 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0, 4352 CNTR_NORMAL, 4353 access_pcic_receive_parity_err_cnt), 4354 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0, 4355 CNTR_NORMAL, 4356 access_pcic_transmit_back_parity_err_cnt), 4357 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0, 4358 0, CNTR_NORMAL, 4359 access_pcic_transmit_front_parity_err_cnt), 4360 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0, 4361 CNTR_NORMAL, 4362 access_pcic_cpl_dat_q_unc_err_cnt), 4363 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0, 4364 CNTR_NORMAL, 4365 access_pcic_cpl_hd_q_unc_err_cnt), 4366 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0, 4367 CNTR_NORMAL, 4368 access_pcic_post_dat_q_unc_err_cnt), 4369 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0, 4370 CNTR_NORMAL, 4371 access_pcic_post_hd_q_unc_err_cnt), 4372 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0, 4373 CNTR_NORMAL, 4374 access_pcic_retry_sot_mem_unc_err_cnt), 4375 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0, 4376 CNTR_NORMAL, 4377 access_pcic_retry_mem_unc_err), 4378 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0, 4379 CNTR_NORMAL, 4380 access_pcic_n_post_dat_q_parity_err_cnt), 4381 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0, 4382 CNTR_NORMAL, 4383 access_pcic_n_post_h_q_parity_err_cnt), 4384 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0, 4385 CNTR_NORMAL, 4386 access_pcic_cpl_dat_q_cor_err_cnt), 4387 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0, 4388 CNTR_NORMAL, 4389 access_pcic_cpl_hd_q_cor_err_cnt), 4390 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0, 4391 CNTR_NORMAL, 4392 access_pcic_post_dat_q_cor_err_cnt), 4393 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0, 4394 CNTR_NORMAL, 4395 access_pcic_post_hd_q_cor_err_cnt), 4396 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0, 4397 CNTR_NORMAL, 4398 access_pcic_retry_sot_mem_cor_err_cnt), 4399 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0, 4400 CNTR_NORMAL, 4401 access_pcic_retry_mem_cor_err_cnt), 4402 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM( 4403 "CceCli1AsyncFifoDbgParityError", 0, 0, 4404 CNTR_NORMAL, 4405 access_cce_cli1_async_fifo_dbg_parity_err_cnt), 4406 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM( 4407 "CceCli1AsyncFifoRxdmaParityError", 0, 0, 4408 CNTR_NORMAL, 4409 access_cce_cli1_async_fifo_rxdma_parity_err_cnt 4410 ), 4411 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM( 4412 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0, 4413 CNTR_NORMAL, 4414 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt), 4415 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM( 4416 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0, 4417 CNTR_NORMAL, 4418 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt), 4419 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0, 4420 0, CNTR_NORMAL, 4421 access_cce_cli2_async_fifo_parity_err_cnt), 4422 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0, 4423 CNTR_NORMAL, 4424 access_cce_csr_cfg_bus_parity_err_cnt), 4425 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0, 4426 0, CNTR_NORMAL, 4427 access_cce_cli0_async_fifo_parity_err_cnt), 4428 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0, 4429 CNTR_NORMAL, 4430 access_cce_rspd_data_parity_err_cnt), 4431 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0, 4432 CNTR_NORMAL, 4433 access_cce_trgt_access_err_cnt), 4434 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0, 4435 0, CNTR_NORMAL, 4436 access_cce_trgt_async_fifo_parity_err_cnt), 4437 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0, 4438 CNTR_NORMAL, 4439 access_cce_csr_write_bad_addr_err_cnt), 4440 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0, 4441 CNTR_NORMAL, 4442 access_cce_csr_read_bad_addr_err_cnt), 4443 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0, 4444 CNTR_NORMAL, 4445 access_ccs_csr_parity_err_cnt), 4446 4447 /* RcvErrStatus */ 4448 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0, 4449 CNTR_NORMAL, 4450 access_rx_csr_parity_err_cnt), 4451 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0, 4452 CNTR_NORMAL, 4453 access_rx_csr_write_bad_addr_err_cnt), 4454 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0, 4455 CNTR_NORMAL, 4456 access_rx_csr_read_bad_addr_err_cnt), 4457 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0, 4458 CNTR_NORMAL, 4459 access_rx_dma_csr_unc_err_cnt), 4460 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0, 4461 CNTR_NORMAL, 4462 access_rx_dma_dq_fsm_encoding_err_cnt), 4463 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0, 4464 CNTR_NORMAL, 4465 access_rx_dma_eq_fsm_encoding_err_cnt), 4466 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0, 4467 CNTR_NORMAL, 4468 access_rx_dma_csr_parity_err_cnt), 4469 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0, 4470 CNTR_NORMAL, 4471 access_rx_rbuf_data_cor_err_cnt), 4472 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0, 4473 CNTR_NORMAL, 4474 access_rx_rbuf_data_unc_err_cnt), 4475 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0, 4476 CNTR_NORMAL, 4477 access_rx_dma_data_fifo_rd_cor_err_cnt), 4478 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0, 4479 CNTR_NORMAL, 4480 access_rx_dma_data_fifo_rd_unc_err_cnt), 4481 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0, 4482 CNTR_NORMAL, 4483 access_rx_dma_hdr_fifo_rd_cor_err_cnt), 4484 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0, 4485 CNTR_NORMAL, 4486 access_rx_dma_hdr_fifo_rd_unc_err_cnt), 4487 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0, 4488 CNTR_NORMAL, 4489 access_rx_rbuf_desc_part2_cor_err_cnt), 4490 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0, 4491 CNTR_NORMAL, 4492 access_rx_rbuf_desc_part2_unc_err_cnt), 4493 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0, 4494 CNTR_NORMAL, 4495 access_rx_rbuf_desc_part1_cor_err_cnt), 4496 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0, 4497 CNTR_NORMAL, 4498 access_rx_rbuf_desc_part1_unc_err_cnt), 4499 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0, 4500 CNTR_NORMAL, 4501 access_rx_hq_intr_fsm_err_cnt), 4502 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0, 4503 CNTR_NORMAL, 4504 access_rx_hq_intr_csr_parity_err_cnt), 4505 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0, 4506 CNTR_NORMAL, 4507 access_rx_lookup_csr_parity_err_cnt), 4508 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0, 4509 CNTR_NORMAL, 4510 access_rx_lookup_rcv_array_cor_err_cnt), 4511 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0, 4512 CNTR_NORMAL, 4513 access_rx_lookup_rcv_array_unc_err_cnt), 4514 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0, 4515 0, CNTR_NORMAL, 4516 access_rx_lookup_des_part2_parity_err_cnt), 4517 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0, 4518 0, CNTR_NORMAL, 4519 access_rx_lookup_des_part1_unc_cor_err_cnt), 4520 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0, 4521 CNTR_NORMAL, 4522 access_rx_lookup_des_part1_unc_err_cnt), 4523 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0, 4524 CNTR_NORMAL, 4525 access_rx_rbuf_next_free_buf_cor_err_cnt), 4526 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0, 4527 CNTR_NORMAL, 4528 access_rx_rbuf_next_free_buf_unc_err_cnt), 4529 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM( 4530 "RxRbufFlInitWrAddrParityErr", 0, 0, 4531 CNTR_NORMAL, 4532 access_rbuf_fl_init_wr_addr_parity_err_cnt), 4533 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0, 4534 0, CNTR_NORMAL, 4535 access_rx_rbuf_fl_initdone_parity_err_cnt), 4536 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0, 4537 0, CNTR_NORMAL, 4538 access_rx_rbuf_fl_write_addr_parity_err_cnt), 4539 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0, 4540 CNTR_NORMAL, 4541 access_rx_rbuf_fl_rd_addr_parity_err_cnt), 4542 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0, 4543 CNTR_NORMAL, 4544 access_rx_rbuf_empty_err_cnt), 4545 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0, 4546 CNTR_NORMAL, 4547 access_rx_rbuf_full_err_cnt), 4548 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0, 4549 CNTR_NORMAL, 4550 access_rbuf_bad_lookup_err_cnt), 4551 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0, 4552 CNTR_NORMAL, 4553 access_rbuf_ctx_id_parity_err_cnt), 4554 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0, 4555 CNTR_NORMAL, 4556 access_rbuf_csr_qeopdw_parity_err_cnt), 4557 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM( 4558 "RxRbufCsrQNumOfPktParityErr", 0, 0, 4559 CNTR_NORMAL, 4560 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt), 4561 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM( 4562 "RxRbufCsrQTlPtrParityErr", 0, 0, 4563 CNTR_NORMAL, 4564 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt), 4565 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0, 4566 0, CNTR_NORMAL, 4567 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt), 4568 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0, 4569 0, CNTR_NORMAL, 4570 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt), 4571 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr", 4572 0, 0, CNTR_NORMAL, 4573 access_rx_rbuf_csr_q_next_buf_parity_err_cnt), 4574 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0, 4575 0, CNTR_NORMAL, 4576 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt), 4577 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM( 4578 "RxRbufCsrQHeadBufNumParityErr", 0, 0, 4579 CNTR_NORMAL, 4580 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt), 4581 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0, 4582 0, CNTR_NORMAL, 4583 access_rx_rbuf_block_list_read_cor_err_cnt), 4584 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0, 4585 0, CNTR_NORMAL, 4586 access_rx_rbuf_block_list_read_unc_err_cnt), 4587 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0, 4588 CNTR_NORMAL, 4589 access_rx_rbuf_lookup_des_cor_err_cnt), 4590 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0, 4591 CNTR_NORMAL, 4592 access_rx_rbuf_lookup_des_unc_err_cnt), 4593 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM( 4594 "RxRbufLookupDesRegUncCorErr", 0, 0, 4595 CNTR_NORMAL, 4596 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt), 4597 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0, 4598 CNTR_NORMAL, 4599 access_rx_rbuf_lookup_des_reg_unc_err_cnt), 4600 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0, 4601 CNTR_NORMAL, 4602 access_rx_rbuf_free_list_cor_err_cnt), 4603 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0, 4604 CNTR_NORMAL, 4605 access_rx_rbuf_free_list_unc_err_cnt), 4606 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0, 4607 CNTR_NORMAL, 4608 access_rx_rcv_fsm_encoding_err_cnt), 4609 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0, 4610 CNTR_NORMAL, 4611 access_rx_dma_flag_cor_err_cnt), 4612 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0, 4613 CNTR_NORMAL, 4614 access_rx_dma_flag_unc_err_cnt), 4615 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0, 4616 CNTR_NORMAL, 4617 access_rx_dc_sop_eop_parity_err_cnt), 4618 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0, 4619 CNTR_NORMAL, 4620 access_rx_rcv_csr_parity_err_cnt), 4621 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0, 4622 CNTR_NORMAL, 4623 access_rx_rcv_qp_map_table_cor_err_cnt), 4624 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0, 4625 CNTR_NORMAL, 4626 access_rx_rcv_qp_map_table_unc_err_cnt), 4627 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0, 4628 CNTR_NORMAL, 4629 access_rx_rcv_data_cor_err_cnt), 4630 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0, 4631 CNTR_NORMAL, 4632 access_rx_rcv_data_unc_err_cnt), 4633 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0, 4634 CNTR_NORMAL, 4635 access_rx_rcv_hdr_cor_err_cnt), 4636 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0, 4637 CNTR_NORMAL, 4638 access_rx_rcv_hdr_unc_err_cnt), 4639 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0, 4640 CNTR_NORMAL, 4641 access_rx_dc_intf_parity_err_cnt), 4642 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0, 4643 CNTR_NORMAL, 4644 access_rx_dma_csr_cor_err_cnt), 4645 /* SendPioErrStatus */ 4646 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0, 4647 CNTR_NORMAL, 4648 access_pio_pec_sop_head_parity_err_cnt), 4649 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0, 4650 CNTR_NORMAL, 4651 access_pio_pcc_sop_head_parity_err_cnt), 4652 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr", 4653 0, 0, CNTR_NORMAL, 4654 access_pio_last_returned_cnt_parity_err_cnt), 4655 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0, 4656 0, CNTR_NORMAL, 4657 access_pio_current_free_cnt_parity_err_cnt), 4658 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0, 4659 CNTR_NORMAL, 4660 access_pio_reserved_31_err_cnt), 4661 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0, 4662 CNTR_NORMAL, 4663 access_pio_reserved_30_err_cnt), 4664 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0, 4665 CNTR_NORMAL, 4666 access_pio_ppmc_sop_len_err_cnt), 4667 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0, 4668 CNTR_NORMAL, 4669 access_pio_ppmc_bqc_mem_parity_err_cnt), 4670 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0, 4671 CNTR_NORMAL, 4672 access_pio_vl_fifo_parity_err_cnt), 4673 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0, 4674 CNTR_NORMAL, 4675 access_pio_vlf_sop_parity_err_cnt), 4676 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0, 4677 CNTR_NORMAL, 4678 access_pio_vlf_v1_len_parity_err_cnt), 4679 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0, 4680 CNTR_NORMAL, 4681 access_pio_block_qw_count_parity_err_cnt), 4682 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0, 4683 CNTR_NORMAL, 4684 access_pio_write_qw_valid_parity_err_cnt), 4685 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0, 4686 CNTR_NORMAL, 4687 access_pio_state_machine_err_cnt), 4688 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0, 4689 CNTR_NORMAL, 4690 access_pio_write_data_parity_err_cnt), 4691 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0, 4692 CNTR_NORMAL, 4693 access_pio_host_addr_mem_cor_err_cnt), 4694 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0, 4695 CNTR_NORMAL, 4696 access_pio_host_addr_mem_unc_err_cnt), 4697 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0, 4698 CNTR_NORMAL, 4699 access_pio_pkt_evict_sm_or_arb_sm_err_cnt), 4700 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0, 4701 CNTR_NORMAL, 4702 access_pio_init_sm_in_err_cnt), 4703 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0, 4704 CNTR_NORMAL, 4705 access_pio_ppmc_pbl_fifo_err_cnt), 4706 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0, 4707 0, CNTR_NORMAL, 4708 access_pio_credit_ret_fifo_parity_err_cnt), 4709 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0, 4710 CNTR_NORMAL, 4711 access_pio_v1_len_mem_bank1_cor_err_cnt), 4712 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0, 4713 CNTR_NORMAL, 4714 access_pio_v1_len_mem_bank0_cor_err_cnt), 4715 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0, 4716 CNTR_NORMAL, 4717 access_pio_v1_len_mem_bank1_unc_err_cnt), 4718 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0, 4719 CNTR_NORMAL, 4720 access_pio_v1_len_mem_bank0_unc_err_cnt), 4721 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0, 4722 CNTR_NORMAL, 4723 access_pio_sm_pkt_reset_parity_err_cnt), 4724 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0, 4725 CNTR_NORMAL, 4726 access_pio_pkt_evict_fifo_parity_err_cnt), 4727 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM( 4728 "PioSbrdctrlCrrelFifoParityErr", 0, 0, 4729 CNTR_NORMAL, 4730 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt), 4731 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0, 4732 CNTR_NORMAL, 4733 access_pio_sbrdctl_crrel_parity_err_cnt), 4734 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0, 4735 CNTR_NORMAL, 4736 access_pio_pec_fifo_parity_err_cnt), 4737 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0, 4738 CNTR_NORMAL, 4739 access_pio_pcc_fifo_parity_err_cnt), 4740 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0, 4741 CNTR_NORMAL, 4742 access_pio_sb_mem_fifo1_err_cnt), 4743 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0, 4744 CNTR_NORMAL, 4745 access_pio_sb_mem_fifo0_err_cnt), 4746 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0, 4747 CNTR_NORMAL, 4748 access_pio_csr_parity_err_cnt), 4749 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0, 4750 CNTR_NORMAL, 4751 access_pio_write_addr_parity_err_cnt), 4752 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0, 4753 CNTR_NORMAL, 4754 access_pio_write_bad_ctxt_err_cnt), 4755 /* SendDmaErrStatus */ 4756 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0, 4757 0, CNTR_NORMAL, 4758 access_sdma_pcie_req_tracking_cor_err_cnt), 4759 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0, 4760 0, CNTR_NORMAL, 4761 access_sdma_pcie_req_tracking_unc_err_cnt), 4762 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0, 4763 CNTR_NORMAL, 4764 access_sdma_csr_parity_err_cnt), 4765 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0, 4766 CNTR_NORMAL, 4767 access_sdma_rpy_tag_err_cnt), 4768 /* SendEgressErrStatus */ 4769 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0, 4770 CNTR_NORMAL, 4771 access_tx_read_pio_memory_csr_unc_err_cnt), 4772 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0, 4773 0, CNTR_NORMAL, 4774 access_tx_read_sdma_memory_csr_err_cnt), 4775 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0, 4776 CNTR_NORMAL, 4777 access_tx_egress_fifo_cor_err_cnt), 4778 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0, 4779 CNTR_NORMAL, 4780 access_tx_read_pio_memory_cor_err_cnt), 4781 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0, 4782 CNTR_NORMAL, 4783 access_tx_read_sdma_memory_cor_err_cnt), 4784 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0, 4785 CNTR_NORMAL, 4786 access_tx_sb_hdr_cor_err_cnt), 4787 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0, 4788 CNTR_NORMAL, 4789 access_tx_credit_overrun_err_cnt), 4790 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0, 4791 CNTR_NORMAL, 4792 access_tx_launch_fifo8_cor_err_cnt), 4793 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0, 4794 CNTR_NORMAL, 4795 access_tx_launch_fifo7_cor_err_cnt), 4796 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0, 4797 CNTR_NORMAL, 4798 access_tx_launch_fifo6_cor_err_cnt), 4799 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0, 4800 CNTR_NORMAL, 4801 access_tx_launch_fifo5_cor_err_cnt), 4802 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0, 4803 CNTR_NORMAL, 4804 access_tx_launch_fifo4_cor_err_cnt), 4805 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0, 4806 CNTR_NORMAL, 4807 access_tx_launch_fifo3_cor_err_cnt), 4808 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0, 4809 CNTR_NORMAL, 4810 access_tx_launch_fifo2_cor_err_cnt), 4811 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0, 4812 CNTR_NORMAL, 4813 access_tx_launch_fifo1_cor_err_cnt), 4814 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0, 4815 CNTR_NORMAL, 4816 access_tx_launch_fifo0_cor_err_cnt), 4817 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0, 4818 CNTR_NORMAL, 4819 access_tx_credit_return_vl_err_cnt), 4820 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0, 4821 CNTR_NORMAL, 4822 access_tx_hcrc_insertion_err_cnt), 4823 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0, 4824 CNTR_NORMAL, 4825 access_tx_egress_fifo_unc_err_cnt), 4826 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0, 4827 CNTR_NORMAL, 4828 access_tx_read_pio_memory_unc_err_cnt), 4829 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0, 4830 CNTR_NORMAL, 4831 access_tx_read_sdma_memory_unc_err_cnt), 4832 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0, 4833 CNTR_NORMAL, 4834 access_tx_sb_hdr_unc_err_cnt), 4835 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0, 4836 CNTR_NORMAL, 4837 access_tx_credit_return_partiy_err_cnt), 4838 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr", 4839 0, 0, CNTR_NORMAL, 4840 access_tx_launch_fifo8_unc_or_parity_err_cnt), 4841 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr", 4842 0, 0, CNTR_NORMAL, 4843 access_tx_launch_fifo7_unc_or_parity_err_cnt), 4844 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr", 4845 0, 0, CNTR_NORMAL, 4846 access_tx_launch_fifo6_unc_or_parity_err_cnt), 4847 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr", 4848 0, 0, CNTR_NORMAL, 4849 access_tx_launch_fifo5_unc_or_parity_err_cnt), 4850 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr", 4851 0, 0, CNTR_NORMAL, 4852 access_tx_launch_fifo4_unc_or_parity_err_cnt), 4853 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr", 4854 0, 0, CNTR_NORMAL, 4855 access_tx_launch_fifo3_unc_or_parity_err_cnt), 4856 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr", 4857 0, 0, CNTR_NORMAL, 4858 access_tx_launch_fifo2_unc_or_parity_err_cnt), 4859 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr", 4860 0, 0, CNTR_NORMAL, 4861 access_tx_launch_fifo1_unc_or_parity_err_cnt), 4862 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr", 4863 0, 0, CNTR_NORMAL, 4864 access_tx_launch_fifo0_unc_or_parity_err_cnt), 4865 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr", 4866 0, 0, CNTR_NORMAL, 4867 access_tx_sdma15_disallowed_packet_err_cnt), 4868 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr", 4869 0, 0, CNTR_NORMAL, 4870 access_tx_sdma14_disallowed_packet_err_cnt), 4871 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr", 4872 0, 0, CNTR_NORMAL, 4873 access_tx_sdma13_disallowed_packet_err_cnt), 4874 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr", 4875 0, 0, CNTR_NORMAL, 4876 access_tx_sdma12_disallowed_packet_err_cnt), 4877 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr", 4878 0, 0, CNTR_NORMAL, 4879 access_tx_sdma11_disallowed_packet_err_cnt), 4880 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr", 4881 0, 0, CNTR_NORMAL, 4882 access_tx_sdma10_disallowed_packet_err_cnt), 4883 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr", 4884 0, 0, CNTR_NORMAL, 4885 access_tx_sdma9_disallowed_packet_err_cnt), 4886 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr", 4887 0, 0, CNTR_NORMAL, 4888 access_tx_sdma8_disallowed_packet_err_cnt), 4889 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr", 4890 0, 0, CNTR_NORMAL, 4891 access_tx_sdma7_disallowed_packet_err_cnt), 4892 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr", 4893 0, 0, CNTR_NORMAL, 4894 access_tx_sdma6_disallowed_packet_err_cnt), 4895 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr", 4896 0, 0, CNTR_NORMAL, 4897 access_tx_sdma5_disallowed_packet_err_cnt), 4898 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr", 4899 0, 0, CNTR_NORMAL, 4900 access_tx_sdma4_disallowed_packet_err_cnt), 4901 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr", 4902 0, 0, CNTR_NORMAL, 4903 access_tx_sdma3_disallowed_packet_err_cnt), 4904 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr", 4905 0, 0, CNTR_NORMAL, 4906 access_tx_sdma2_disallowed_packet_err_cnt), 4907 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr", 4908 0, 0, CNTR_NORMAL, 4909 access_tx_sdma1_disallowed_packet_err_cnt), 4910 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr", 4911 0, 0, CNTR_NORMAL, 4912 access_tx_sdma0_disallowed_packet_err_cnt), 4913 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0, 4914 CNTR_NORMAL, 4915 access_tx_config_parity_err_cnt), 4916 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0, 4917 CNTR_NORMAL, 4918 access_tx_sbrd_ctl_csr_parity_err_cnt), 4919 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0, 4920 CNTR_NORMAL, 4921 access_tx_launch_csr_parity_err_cnt), 4922 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0, 4923 CNTR_NORMAL, 4924 access_tx_illegal_vl_err_cnt), 4925 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM( 4926 "TxSbrdCtlStateMachineParityErr", 0, 0, 4927 CNTR_NORMAL, 4928 access_tx_sbrd_ctl_state_machine_parity_err_cnt), 4929 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0, 4930 CNTR_NORMAL, 4931 access_egress_reserved_10_err_cnt), 4932 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0, 4933 CNTR_NORMAL, 4934 access_egress_reserved_9_err_cnt), 4935 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr", 4936 0, 0, CNTR_NORMAL, 4937 access_tx_sdma_launch_intf_parity_err_cnt), 4938 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0, 4939 CNTR_NORMAL, 4940 access_tx_pio_launch_intf_parity_err_cnt), 4941 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0, 4942 CNTR_NORMAL, 4943 access_egress_reserved_6_err_cnt), 4944 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0, 4945 CNTR_NORMAL, 4946 access_tx_incorrect_link_state_err_cnt), 4947 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0, 4948 CNTR_NORMAL, 4949 access_tx_linkdown_err_cnt), 4950 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM( 4951 "EgressFifoUnderrunOrParityErr", 0, 0, 4952 CNTR_NORMAL, 4953 access_tx_egress_fifi_underrun_or_parity_err_cnt), 4954 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0, 4955 CNTR_NORMAL, 4956 access_egress_reserved_2_err_cnt), 4957 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0, 4958 CNTR_NORMAL, 4959 access_tx_pkt_integrity_mem_unc_err_cnt), 4960 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0, 4961 CNTR_NORMAL, 4962 access_tx_pkt_integrity_mem_cor_err_cnt), 4963 /* SendErrStatus */ 4964 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0, 4965 CNTR_NORMAL, 4966 access_send_csr_write_bad_addr_err_cnt), 4967 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0, 4968 CNTR_NORMAL, 4969 access_send_csr_read_bad_addr_err_cnt), 4970 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0, 4971 CNTR_NORMAL, 4972 access_send_csr_parity_cnt), 4973 /* SendCtxtErrStatus */ 4974 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0, 4975 CNTR_NORMAL, 4976 access_pio_write_out_of_bounds_err_cnt), 4977 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0, 4978 CNTR_NORMAL, 4979 access_pio_write_overflow_err_cnt), 4980 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr", 4981 0, 0, CNTR_NORMAL, 4982 access_pio_write_crosses_boundary_err_cnt), 4983 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0, 4984 CNTR_NORMAL, 4985 access_pio_disallowed_packet_err_cnt), 4986 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0, 4987 CNTR_NORMAL, 4988 access_pio_inconsistent_sop_err_cnt), 4989 /* SendDmaEngErrStatus */ 4990 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr", 4991 0, 0, CNTR_NORMAL, 4992 access_sdma_header_request_fifo_cor_err_cnt), 4993 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0, 4994 CNTR_NORMAL, 4995 access_sdma_header_storage_cor_err_cnt), 4996 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0, 4997 CNTR_NORMAL, 4998 access_sdma_packet_tracking_cor_err_cnt), 4999 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0, 5000 CNTR_NORMAL, 5001 access_sdma_assembly_cor_err_cnt), 5002 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0, 5003 CNTR_NORMAL, 5004 access_sdma_desc_table_cor_err_cnt), 5005 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr", 5006 0, 0, CNTR_NORMAL, 5007 access_sdma_header_request_fifo_unc_err_cnt), 5008 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0, 5009 CNTR_NORMAL, 5010 access_sdma_header_storage_unc_err_cnt), 5011 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0, 5012 CNTR_NORMAL, 5013 access_sdma_packet_tracking_unc_err_cnt), 5014 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0, 5015 CNTR_NORMAL, 5016 access_sdma_assembly_unc_err_cnt), 5017 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0, 5018 CNTR_NORMAL, 5019 access_sdma_desc_table_unc_err_cnt), 5020 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0, 5021 CNTR_NORMAL, 5022 access_sdma_timeout_err_cnt), 5023 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0, 5024 CNTR_NORMAL, 5025 access_sdma_header_length_err_cnt), 5026 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0, 5027 CNTR_NORMAL, 5028 access_sdma_header_address_err_cnt), 5029 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0, 5030 CNTR_NORMAL, 5031 access_sdma_header_select_err_cnt), 5032 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0, 5033 CNTR_NORMAL, 5034 access_sdma_reserved_9_err_cnt), 5035 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0, 5036 CNTR_NORMAL, 5037 access_sdma_packet_desc_overflow_err_cnt), 5038 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0, 5039 CNTR_NORMAL, 5040 access_sdma_length_mismatch_err_cnt), 5041 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0, 5042 CNTR_NORMAL, 5043 access_sdma_halt_err_cnt), 5044 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0, 5045 CNTR_NORMAL, 5046 access_sdma_mem_read_err_cnt), 5047 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0, 5048 CNTR_NORMAL, 5049 access_sdma_first_desc_err_cnt), 5050 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0, 5051 CNTR_NORMAL, 5052 access_sdma_tail_out_of_bounds_err_cnt), 5053 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0, 5054 CNTR_NORMAL, 5055 access_sdma_too_long_err_cnt), 5056 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0, 5057 CNTR_NORMAL, 5058 access_sdma_gen_mismatch_err_cnt), 5059 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0, 5060 CNTR_NORMAL, 5061 access_sdma_wrong_dw_err_cnt), 5062 }; 5063 5064 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = { 5065 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT, 5066 CNTR_NORMAL), 5067 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT, 5068 CNTR_NORMAL), 5069 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT, 5070 CNTR_NORMAL), 5071 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT, 5072 CNTR_NORMAL), 5073 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT, 5074 CNTR_NORMAL), 5075 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT, 5076 CNTR_NORMAL), 5077 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT, 5078 CNTR_NORMAL), 5079 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL), 5080 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL), 5081 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH), 5082 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT, 5083 CNTR_SYNTH | CNTR_VL), 5084 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT, 5085 CNTR_SYNTH | CNTR_VL), 5086 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT, 5087 CNTR_SYNTH | CNTR_VL), 5088 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL), 5089 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL), 5090 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5091 access_sw_link_dn_cnt), 5092 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5093 access_sw_link_up_cnt), 5094 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL, 5095 access_sw_unknown_frame_cnt), 5096 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5097 access_sw_xmit_discards), 5098 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0, 5099 CNTR_SYNTH | CNTR_32BIT | CNTR_VL, 5100 access_sw_xmit_discards), 5101 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH, 5102 access_xmit_constraint_errs), 5103 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH, 5104 access_rcv_constraint_errs), 5105 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts), 5106 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends), 5107 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks), 5108 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks), 5109 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts), 5110 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops), 5111 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait), 5112 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak), 5113 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq), 5114 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq), 5115 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned), 5116 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks), 5117 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL, 5118 access_sw_cpu_rc_acks), 5119 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL, 5120 access_sw_cpu_rc_qacks), 5121 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL, 5122 access_sw_cpu_rc_delayed_comp), 5123 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1), 5124 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3), 5125 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5), 5126 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7), 5127 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9), 5128 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11), 5129 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13), 5130 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15), 5131 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17), 5132 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19), 5133 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21), 5134 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23), 5135 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25), 5136 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27), 5137 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29), 5138 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31), 5139 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33), 5140 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35), 5141 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37), 5142 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39), 5143 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41), 5144 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43), 5145 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45), 5146 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47), 5147 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49), 5148 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51), 5149 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53), 5150 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55), 5151 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57), 5152 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59), 5153 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61), 5154 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63), 5155 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65), 5156 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67), 5157 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69), 5158 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71), 5159 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73), 5160 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75), 5161 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77), 5162 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79), 5163 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81), 5164 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83), 5165 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85), 5166 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87), 5167 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89), 5168 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91), 5169 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93), 5170 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95), 5171 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97), 5172 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99), 5173 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101), 5174 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103), 5175 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105), 5176 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107), 5177 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109), 5178 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111), 5179 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113), 5180 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115), 5181 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117), 5182 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119), 5183 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121), 5184 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123), 5185 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125), 5186 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127), 5187 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129), 5188 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131), 5189 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133), 5190 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135), 5191 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137), 5192 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139), 5193 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141), 5194 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143), 5195 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145), 5196 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147), 5197 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149), 5198 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151), 5199 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153), 5200 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155), 5201 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157), 5202 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159), 5203 }; 5204 5205 /* ======================================================================== */ 5206 5207 /* return true if this is chip revision revision a */ 5208 int is_ax(struct hfi1_devdata *dd) 5209 { 5210 u8 chip_rev_minor = 5211 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5212 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5213 return (chip_rev_minor & 0xf0) == 0; 5214 } 5215 5216 /* return true if this is chip revision revision b */ 5217 int is_bx(struct hfi1_devdata *dd) 5218 { 5219 u8 chip_rev_minor = 5220 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5221 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5222 return (chip_rev_minor & 0xF0) == 0x10; 5223 } 5224 5225 /* 5226 * Append string s to buffer buf. Arguments curp and len are the current 5227 * position and remaining length, respectively. 5228 * 5229 * return 0 on success, 1 on out of room 5230 */ 5231 static int append_str(char *buf, char **curp, int *lenp, const char *s) 5232 { 5233 char *p = *curp; 5234 int len = *lenp; 5235 int result = 0; /* success */ 5236 char c; 5237 5238 /* add a comma, if first in the buffer */ 5239 if (p != buf) { 5240 if (len == 0) { 5241 result = 1; /* out of room */ 5242 goto done; 5243 } 5244 *p++ = ','; 5245 len--; 5246 } 5247 5248 /* copy the string */ 5249 while ((c = *s++) != 0) { 5250 if (len == 0) { 5251 result = 1; /* out of room */ 5252 goto done; 5253 } 5254 *p++ = c; 5255 len--; 5256 } 5257 5258 done: 5259 /* write return values */ 5260 *curp = p; 5261 *lenp = len; 5262 5263 return result; 5264 } 5265 5266 /* 5267 * Using the given flag table, print a comma separated string into 5268 * the buffer. End in '*' if the buffer is too short. 5269 */ 5270 static char *flag_string(char *buf, int buf_len, u64 flags, 5271 struct flag_table *table, int table_size) 5272 { 5273 char extra[32]; 5274 char *p = buf; 5275 int len = buf_len; 5276 int no_room = 0; 5277 int i; 5278 5279 /* make sure there is at least 2 so we can form "*" */ 5280 if (len < 2) 5281 return ""; 5282 5283 len--; /* leave room for a nul */ 5284 for (i = 0; i < table_size; i++) { 5285 if (flags & table[i].flag) { 5286 no_room = append_str(buf, &p, &len, table[i].str); 5287 if (no_room) 5288 break; 5289 flags &= ~table[i].flag; 5290 } 5291 } 5292 5293 /* any undocumented bits left? */ 5294 if (!no_room && flags) { 5295 snprintf(extra, sizeof(extra), "bits 0x%llx", flags); 5296 no_room = append_str(buf, &p, &len, extra); 5297 } 5298 5299 /* add * if ran out of room */ 5300 if (no_room) { 5301 /* may need to back up to add space for a '*' */ 5302 if (len == 0) 5303 --p; 5304 *p++ = '*'; 5305 } 5306 5307 /* add final nul - space already allocated above */ 5308 *p = 0; 5309 return buf; 5310 } 5311 5312 /* first 8 CCE error interrupt source names */ 5313 static const char * const cce_misc_names[] = { 5314 "CceErrInt", /* 0 */ 5315 "RxeErrInt", /* 1 */ 5316 "MiscErrInt", /* 2 */ 5317 "Reserved3", /* 3 */ 5318 "PioErrInt", /* 4 */ 5319 "SDmaErrInt", /* 5 */ 5320 "EgressErrInt", /* 6 */ 5321 "TxeErrInt" /* 7 */ 5322 }; 5323 5324 /* 5325 * Return the miscellaneous error interrupt name. 5326 */ 5327 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source) 5328 { 5329 if (source < ARRAY_SIZE(cce_misc_names)) 5330 strncpy(buf, cce_misc_names[source], bsize); 5331 else 5332 snprintf(buf, bsize, "Reserved%u", 5333 source + IS_GENERAL_ERR_START); 5334 5335 return buf; 5336 } 5337 5338 /* 5339 * Return the SDMA engine error interrupt name. 5340 */ 5341 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source) 5342 { 5343 snprintf(buf, bsize, "SDmaEngErrInt%u", source); 5344 return buf; 5345 } 5346 5347 /* 5348 * Return the send context error interrupt name. 5349 */ 5350 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source) 5351 { 5352 snprintf(buf, bsize, "SendCtxtErrInt%u", source); 5353 return buf; 5354 } 5355 5356 static const char * const various_names[] = { 5357 "PbcInt", 5358 "GpioAssertInt", 5359 "Qsfp1Int", 5360 "Qsfp2Int", 5361 "TCritInt" 5362 }; 5363 5364 /* 5365 * Return the various interrupt name. 5366 */ 5367 static char *is_various_name(char *buf, size_t bsize, unsigned int source) 5368 { 5369 if (source < ARRAY_SIZE(various_names)) 5370 strncpy(buf, various_names[source], bsize); 5371 else 5372 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START); 5373 return buf; 5374 } 5375 5376 /* 5377 * Return the DC interrupt name. 5378 */ 5379 static char *is_dc_name(char *buf, size_t bsize, unsigned int source) 5380 { 5381 static const char * const dc_int_names[] = { 5382 "common", 5383 "lcb", 5384 "8051", 5385 "lbm" /* local block merge */ 5386 }; 5387 5388 if (source < ARRAY_SIZE(dc_int_names)) 5389 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]); 5390 else 5391 snprintf(buf, bsize, "DCInt%u", source); 5392 return buf; 5393 } 5394 5395 static const char * const sdma_int_names[] = { 5396 "SDmaInt", 5397 "SdmaIdleInt", 5398 "SdmaProgressInt", 5399 }; 5400 5401 /* 5402 * Return the SDMA engine interrupt name. 5403 */ 5404 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source) 5405 { 5406 /* what interrupt */ 5407 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 5408 /* which engine */ 5409 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 5410 5411 if (likely(what < 3)) 5412 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which); 5413 else 5414 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source); 5415 return buf; 5416 } 5417 5418 /* 5419 * Return the receive available interrupt name. 5420 */ 5421 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source) 5422 { 5423 snprintf(buf, bsize, "RcvAvailInt%u", source); 5424 return buf; 5425 } 5426 5427 /* 5428 * Return the receive urgent interrupt name. 5429 */ 5430 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source) 5431 { 5432 snprintf(buf, bsize, "RcvUrgentInt%u", source); 5433 return buf; 5434 } 5435 5436 /* 5437 * Return the send credit interrupt name. 5438 */ 5439 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source) 5440 { 5441 snprintf(buf, bsize, "SendCreditInt%u", source); 5442 return buf; 5443 } 5444 5445 /* 5446 * Return the reserved interrupt name. 5447 */ 5448 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source) 5449 { 5450 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START); 5451 return buf; 5452 } 5453 5454 static char *cce_err_status_string(char *buf, int buf_len, u64 flags) 5455 { 5456 return flag_string(buf, buf_len, flags, 5457 cce_err_status_flags, 5458 ARRAY_SIZE(cce_err_status_flags)); 5459 } 5460 5461 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags) 5462 { 5463 return flag_string(buf, buf_len, flags, 5464 rxe_err_status_flags, 5465 ARRAY_SIZE(rxe_err_status_flags)); 5466 } 5467 5468 static char *misc_err_status_string(char *buf, int buf_len, u64 flags) 5469 { 5470 return flag_string(buf, buf_len, flags, misc_err_status_flags, 5471 ARRAY_SIZE(misc_err_status_flags)); 5472 } 5473 5474 static char *pio_err_status_string(char *buf, int buf_len, u64 flags) 5475 { 5476 return flag_string(buf, buf_len, flags, 5477 pio_err_status_flags, 5478 ARRAY_SIZE(pio_err_status_flags)); 5479 } 5480 5481 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags) 5482 { 5483 return flag_string(buf, buf_len, flags, 5484 sdma_err_status_flags, 5485 ARRAY_SIZE(sdma_err_status_flags)); 5486 } 5487 5488 static char *egress_err_status_string(char *buf, int buf_len, u64 flags) 5489 { 5490 return flag_string(buf, buf_len, flags, 5491 egress_err_status_flags, 5492 ARRAY_SIZE(egress_err_status_flags)); 5493 } 5494 5495 static char *egress_err_info_string(char *buf, int buf_len, u64 flags) 5496 { 5497 return flag_string(buf, buf_len, flags, 5498 egress_err_info_flags, 5499 ARRAY_SIZE(egress_err_info_flags)); 5500 } 5501 5502 static char *send_err_status_string(char *buf, int buf_len, u64 flags) 5503 { 5504 return flag_string(buf, buf_len, flags, 5505 send_err_status_flags, 5506 ARRAY_SIZE(send_err_status_flags)); 5507 } 5508 5509 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5510 { 5511 char buf[96]; 5512 int i = 0; 5513 5514 /* 5515 * For most these errors, there is nothing that can be done except 5516 * report or record it. 5517 */ 5518 dd_dev_info(dd, "CCE Error: %s\n", 5519 cce_err_status_string(buf, sizeof(buf), reg)); 5520 5521 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) && 5522 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) { 5523 /* this error requires a manual drop into SPC freeze mode */ 5524 /* then a fix up */ 5525 start_freeze_handling(dd->pport, FREEZE_SELF); 5526 } 5527 5528 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) { 5529 if (reg & (1ull << i)) { 5530 incr_cntr64(&dd->cce_err_status_cnt[i]); 5531 /* maintain a counter over all cce_err_status errors */ 5532 incr_cntr64(&dd->sw_cce_err_status_aggregate); 5533 } 5534 } 5535 } 5536 5537 /* 5538 * Check counters for receive errors that do not have an interrupt 5539 * associated with them. 5540 */ 5541 #define RCVERR_CHECK_TIME 10 5542 static void update_rcverr_timer(struct timer_list *t) 5543 { 5544 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer); 5545 struct hfi1_pportdata *ppd = dd->pport; 5546 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL); 5547 5548 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt && 5549 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) { 5550 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__); 5551 set_link_down_reason( 5552 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0, 5553 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN); 5554 queue_work(ppd->link_wq, &ppd->link_bounce_work); 5555 } 5556 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt; 5557 5558 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5559 } 5560 5561 static int init_rcverr(struct hfi1_devdata *dd) 5562 { 5563 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0); 5564 /* Assume the hardware counter has been reset */ 5565 dd->rcv_ovfl_cnt = 0; 5566 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5567 } 5568 5569 static void free_rcverr(struct hfi1_devdata *dd) 5570 { 5571 if (dd->rcverr_timer.function) 5572 del_timer_sync(&dd->rcverr_timer); 5573 } 5574 5575 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5576 { 5577 char buf[96]; 5578 int i = 0; 5579 5580 dd_dev_info(dd, "Receive Error: %s\n", 5581 rxe_err_status_string(buf, sizeof(buf), reg)); 5582 5583 if (reg & ALL_RXE_FREEZE_ERR) { 5584 int flags = 0; 5585 5586 /* 5587 * Freeze mode recovery is disabled for the errors 5588 * in RXE_FREEZE_ABORT_MASK 5589 */ 5590 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK)) 5591 flags = FREEZE_ABORT; 5592 5593 start_freeze_handling(dd->pport, flags); 5594 } 5595 5596 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) { 5597 if (reg & (1ull << i)) 5598 incr_cntr64(&dd->rcv_err_status_cnt[i]); 5599 } 5600 } 5601 5602 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5603 { 5604 char buf[96]; 5605 int i = 0; 5606 5607 dd_dev_info(dd, "Misc Error: %s", 5608 misc_err_status_string(buf, sizeof(buf), reg)); 5609 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) { 5610 if (reg & (1ull << i)) 5611 incr_cntr64(&dd->misc_err_status_cnt[i]); 5612 } 5613 } 5614 5615 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5616 { 5617 char buf[96]; 5618 int i = 0; 5619 5620 dd_dev_info(dd, "PIO Error: %s\n", 5621 pio_err_status_string(buf, sizeof(buf), reg)); 5622 5623 if (reg & ALL_PIO_FREEZE_ERR) 5624 start_freeze_handling(dd->pport, 0); 5625 5626 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) { 5627 if (reg & (1ull << i)) 5628 incr_cntr64(&dd->send_pio_err_status_cnt[i]); 5629 } 5630 } 5631 5632 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5633 { 5634 char buf[96]; 5635 int i = 0; 5636 5637 dd_dev_info(dd, "SDMA Error: %s\n", 5638 sdma_err_status_string(buf, sizeof(buf), reg)); 5639 5640 if (reg & ALL_SDMA_FREEZE_ERR) 5641 start_freeze_handling(dd->pport, 0); 5642 5643 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) { 5644 if (reg & (1ull << i)) 5645 incr_cntr64(&dd->send_dma_err_status_cnt[i]); 5646 } 5647 } 5648 5649 static inline void __count_port_discards(struct hfi1_pportdata *ppd) 5650 { 5651 incr_cntr64(&ppd->port_xmit_discards); 5652 } 5653 5654 static void count_port_inactive(struct hfi1_devdata *dd) 5655 { 5656 __count_port_discards(dd->pport); 5657 } 5658 5659 /* 5660 * We have had a "disallowed packet" error during egress. Determine the 5661 * integrity check which failed, and update relevant error counter, etc. 5662 * 5663 * Note that the SEND_EGRESS_ERR_INFO register has only a single 5664 * bit of state per integrity check, and so we can miss the reason for an 5665 * egress error if more than one packet fails the same integrity check 5666 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO. 5667 */ 5668 static void handle_send_egress_err_info(struct hfi1_devdata *dd, 5669 int vl) 5670 { 5671 struct hfi1_pportdata *ppd = dd->pport; 5672 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ 5673 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); 5674 char buf[96]; 5675 5676 /* clear down all observed info as quickly as possible after read */ 5677 write_csr(dd, SEND_EGRESS_ERR_INFO, info); 5678 5679 dd_dev_info(dd, 5680 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n", 5681 info, egress_err_info_string(buf, sizeof(buf), info), src); 5682 5683 /* Eventually add other counters for each bit */ 5684 if (info & PORT_DISCARD_EGRESS_ERRS) { 5685 int weight, i; 5686 5687 /* 5688 * Count all applicable bits as individual errors and 5689 * attribute them to the packet that triggered this handler. 5690 * This may not be completely accurate due to limitations 5691 * on the available hardware error information. There is 5692 * a single information register and any number of error 5693 * packets may have occurred and contributed to it before 5694 * this routine is called. This means that: 5695 * a) If multiple packets with the same error occur before 5696 * this routine is called, earlier packets are missed. 5697 * There is only a single bit for each error type. 5698 * b) Errors may not be attributed to the correct VL. 5699 * The driver is attributing all bits in the info register 5700 * to the packet that triggered this call, but bits 5701 * could be an accumulation of different packets with 5702 * different VLs. 5703 * c) A single error packet may have multiple counts attached 5704 * to it. There is no way for the driver to know if 5705 * multiple bits set in the info register are due to a 5706 * single packet or multiple packets. The driver assumes 5707 * multiple packets. 5708 */ 5709 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS); 5710 for (i = 0; i < weight; i++) { 5711 __count_port_discards(ppd); 5712 if (vl >= 0 && vl < TXE_NUM_DATA_VL) 5713 incr_cntr64(&ppd->port_xmit_discards_vl[vl]); 5714 else if (vl == 15) 5715 incr_cntr64(&ppd->port_xmit_discards_vl 5716 [C_VL_15]); 5717 } 5718 } 5719 } 5720 5721 /* 5722 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5723 * register. Does it represent a 'port inactive' error? 5724 */ 5725 static inline int port_inactive_err(u64 posn) 5726 { 5727 return (posn >= SEES(TX_LINKDOWN) && 5728 posn <= SEES(TX_INCORRECT_LINK_STATE)); 5729 } 5730 5731 /* 5732 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5733 * register. Does it represent a 'disallowed packet' error? 5734 */ 5735 static inline int disallowed_pkt_err(int posn) 5736 { 5737 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) && 5738 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET)); 5739 } 5740 5741 /* 5742 * Input value is a bit position of one of the SDMA engine disallowed 5743 * packet errors. Return which engine. Use of this must be guarded by 5744 * disallowed_pkt_err(). 5745 */ 5746 static inline int disallowed_pkt_engine(int posn) 5747 { 5748 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET); 5749 } 5750 5751 /* 5752 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot 5753 * be done. 5754 */ 5755 static int engine_to_vl(struct hfi1_devdata *dd, int engine) 5756 { 5757 struct sdma_vl_map *m; 5758 int vl; 5759 5760 /* range check */ 5761 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES) 5762 return -1; 5763 5764 rcu_read_lock(); 5765 m = rcu_dereference(dd->sdma_map); 5766 vl = m->engine_to_vl[engine]; 5767 rcu_read_unlock(); 5768 5769 return vl; 5770 } 5771 5772 /* 5773 * Translate the send context (sofware index) into a VL. Return -1 if the 5774 * translation cannot be done. 5775 */ 5776 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index) 5777 { 5778 struct send_context_info *sci; 5779 struct send_context *sc; 5780 int i; 5781 5782 sci = &dd->send_contexts[sw_index]; 5783 5784 /* there is no information for user (PSM) and ack contexts */ 5785 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15)) 5786 return -1; 5787 5788 sc = sci->sc; 5789 if (!sc) 5790 return -1; 5791 if (dd->vld[15].sc == sc) 5792 return 15; 5793 for (i = 0; i < num_vls; i++) 5794 if (dd->vld[i].sc == sc) 5795 return i; 5796 5797 return -1; 5798 } 5799 5800 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5801 { 5802 u64 reg_copy = reg, handled = 0; 5803 char buf[96]; 5804 int i = 0; 5805 5806 if (reg & ALL_TXE_EGRESS_FREEZE_ERR) 5807 start_freeze_handling(dd->pport, 0); 5808 else if (is_ax(dd) && 5809 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) && 5810 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) 5811 start_freeze_handling(dd->pport, 0); 5812 5813 while (reg_copy) { 5814 int posn = fls64(reg_copy); 5815 /* fls64() returns a 1-based offset, we want it zero based */ 5816 int shift = posn - 1; 5817 u64 mask = 1ULL << shift; 5818 5819 if (port_inactive_err(shift)) { 5820 count_port_inactive(dd); 5821 handled |= mask; 5822 } else if (disallowed_pkt_err(shift)) { 5823 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift)); 5824 5825 handle_send_egress_err_info(dd, vl); 5826 handled |= mask; 5827 } 5828 reg_copy &= ~mask; 5829 } 5830 5831 reg &= ~handled; 5832 5833 if (reg) 5834 dd_dev_info(dd, "Egress Error: %s\n", 5835 egress_err_status_string(buf, sizeof(buf), reg)); 5836 5837 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) { 5838 if (reg & (1ull << i)) 5839 incr_cntr64(&dd->send_egress_err_status_cnt[i]); 5840 } 5841 } 5842 5843 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5844 { 5845 char buf[96]; 5846 int i = 0; 5847 5848 dd_dev_info(dd, "Send Error: %s\n", 5849 send_err_status_string(buf, sizeof(buf), reg)); 5850 5851 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) { 5852 if (reg & (1ull << i)) 5853 incr_cntr64(&dd->send_err_status_cnt[i]); 5854 } 5855 } 5856 5857 /* 5858 * The maximum number of times the error clear down will loop before 5859 * blocking a repeating error. This value is arbitrary. 5860 */ 5861 #define MAX_CLEAR_COUNT 20 5862 5863 /* 5864 * Clear and handle an error register. All error interrupts are funneled 5865 * through here to have a central location to correctly handle single- 5866 * or multi-shot errors. 5867 * 5868 * For non per-context registers, call this routine with a context value 5869 * of 0 so the per-context offset is zero. 5870 * 5871 * If the handler loops too many times, assume that something is wrong 5872 * and can't be fixed, so mask the error bits. 5873 */ 5874 static void interrupt_clear_down(struct hfi1_devdata *dd, 5875 u32 context, 5876 const struct err_reg_info *eri) 5877 { 5878 u64 reg; 5879 u32 count; 5880 5881 /* read in a loop until no more errors are seen */ 5882 count = 0; 5883 while (1) { 5884 reg = read_kctxt_csr(dd, context, eri->status); 5885 if (reg == 0) 5886 break; 5887 write_kctxt_csr(dd, context, eri->clear, reg); 5888 if (likely(eri->handler)) 5889 eri->handler(dd, context, reg); 5890 count++; 5891 if (count > MAX_CLEAR_COUNT) { 5892 u64 mask; 5893 5894 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n", 5895 eri->desc, reg); 5896 /* 5897 * Read-modify-write so any other masked bits 5898 * remain masked. 5899 */ 5900 mask = read_kctxt_csr(dd, context, eri->mask); 5901 mask &= ~reg; 5902 write_kctxt_csr(dd, context, eri->mask, mask); 5903 break; 5904 } 5905 } 5906 } 5907 5908 /* 5909 * CCE block "misc" interrupt. Source is < 16. 5910 */ 5911 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source) 5912 { 5913 const struct err_reg_info *eri = &misc_errs[source]; 5914 5915 if (eri->handler) { 5916 interrupt_clear_down(dd, 0, eri); 5917 } else { 5918 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n", 5919 source); 5920 } 5921 } 5922 5923 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags) 5924 { 5925 return flag_string(buf, buf_len, flags, 5926 sc_err_status_flags, 5927 ARRAY_SIZE(sc_err_status_flags)); 5928 } 5929 5930 /* 5931 * Send context error interrupt. Source (hw_context) is < 160. 5932 * 5933 * All send context errors cause the send context to halt. The normal 5934 * clear-down mechanism cannot be used because we cannot clear the 5935 * error bits until several other long-running items are done first. 5936 * This is OK because with the context halted, nothing else is going 5937 * to happen on it anyway. 5938 */ 5939 static void is_sendctxt_err_int(struct hfi1_devdata *dd, 5940 unsigned int hw_context) 5941 { 5942 struct send_context_info *sci; 5943 struct send_context *sc; 5944 char flags[96]; 5945 u64 status; 5946 u32 sw_index; 5947 int i = 0; 5948 unsigned long irq_flags; 5949 5950 sw_index = dd->hw_to_sw[hw_context]; 5951 if (sw_index >= dd->num_send_contexts) { 5952 dd_dev_err(dd, 5953 "out of range sw index %u for send context %u\n", 5954 sw_index, hw_context); 5955 return; 5956 } 5957 sci = &dd->send_contexts[sw_index]; 5958 spin_lock_irqsave(&dd->sc_lock, irq_flags); 5959 sc = sci->sc; 5960 if (!sc) { 5961 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__, 5962 sw_index, hw_context); 5963 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 5964 return; 5965 } 5966 5967 /* tell the software that a halt has begun */ 5968 sc_stop(sc, SCF_HALTED); 5969 5970 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS); 5971 5972 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context, 5973 send_context_err_status_string(flags, sizeof(flags), 5974 status)); 5975 5976 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK) 5977 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index)); 5978 5979 /* 5980 * Automatically restart halted kernel contexts out of interrupt 5981 * context. User contexts must ask the driver to restart the context. 5982 */ 5983 if (sc->type != SC_USER) 5984 queue_work(dd->pport->hfi1_wq, &sc->halt_work); 5985 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 5986 5987 /* 5988 * Update the counters for the corresponding status bits. 5989 * Note that these particular counters are aggregated over all 5990 * 160 contexts. 5991 */ 5992 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) { 5993 if (status & (1ull << i)) 5994 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]); 5995 } 5996 } 5997 5998 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 5999 unsigned int source, u64 status) 6000 { 6001 struct sdma_engine *sde; 6002 int i = 0; 6003 6004 sde = &dd->per_sdma[source]; 6005 #ifdef CONFIG_SDMA_VERBOSITY 6006 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6007 slashstrip(__FILE__), __LINE__, __func__); 6008 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n", 6009 sde->this_idx, source, (unsigned long long)status); 6010 #endif 6011 sde->err_cnt++; 6012 sdma_engine_error(sde, status); 6013 6014 /* 6015 * Update the counters for the corresponding status bits. 6016 * Note that these particular counters are aggregated over 6017 * all 16 DMA engines. 6018 */ 6019 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) { 6020 if (status & (1ull << i)) 6021 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]); 6022 } 6023 } 6024 6025 /* 6026 * CCE block SDMA error interrupt. Source is < 16. 6027 */ 6028 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source) 6029 { 6030 #ifdef CONFIG_SDMA_VERBOSITY 6031 struct sdma_engine *sde = &dd->per_sdma[source]; 6032 6033 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6034 slashstrip(__FILE__), __LINE__, __func__); 6035 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx, 6036 source); 6037 sdma_dumpstate(sde); 6038 #endif 6039 interrupt_clear_down(dd, source, &sdma_eng_err); 6040 } 6041 6042 /* 6043 * CCE block "various" interrupt. Source is < 8. 6044 */ 6045 static void is_various_int(struct hfi1_devdata *dd, unsigned int source) 6046 { 6047 const struct err_reg_info *eri = &various_err[source]; 6048 6049 /* 6050 * TCritInt cannot go through interrupt_clear_down() 6051 * because it is not a second tier interrupt. The handler 6052 * should be called directly. 6053 */ 6054 if (source == TCRIT_INT_SOURCE) 6055 handle_temp_err(dd); 6056 else if (eri->handler) 6057 interrupt_clear_down(dd, 0, eri); 6058 else 6059 dd_dev_info(dd, 6060 "%s: Unimplemented/reserved interrupt %d\n", 6061 __func__, source); 6062 } 6063 6064 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg) 6065 { 6066 /* src_ctx is always zero */ 6067 struct hfi1_pportdata *ppd = dd->pport; 6068 unsigned long flags; 6069 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 6070 6071 if (reg & QSFP_HFI0_MODPRST_N) { 6072 if (!qsfp_mod_present(ppd)) { 6073 dd_dev_info(dd, "%s: QSFP module removed\n", 6074 __func__); 6075 6076 ppd->driver_link_ready = 0; 6077 /* 6078 * Cable removed, reset all our information about the 6079 * cache and cable capabilities 6080 */ 6081 6082 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6083 /* 6084 * We don't set cache_refresh_required here as we expect 6085 * an interrupt when a cable is inserted 6086 */ 6087 ppd->qsfp_info.cache_valid = 0; 6088 ppd->qsfp_info.reset_needed = 0; 6089 ppd->qsfp_info.limiting_active = 0; 6090 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6091 flags); 6092 /* Invert the ModPresent pin now to detect plug-in */ 6093 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6094 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6095 6096 if ((ppd->offline_disabled_reason > 6097 HFI1_ODR_MASK( 6098 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) || 6099 (ppd->offline_disabled_reason == 6100 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))) 6101 ppd->offline_disabled_reason = 6102 HFI1_ODR_MASK( 6103 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED); 6104 6105 if (ppd->host_link_state == HLS_DN_POLL) { 6106 /* 6107 * The link is still in POLL. This means 6108 * that the normal link down processing 6109 * will not happen. We have to do it here 6110 * before turning the DC off. 6111 */ 6112 queue_work(ppd->link_wq, &ppd->link_down_work); 6113 } 6114 } else { 6115 dd_dev_info(dd, "%s: QSFP module inserted\n", 6116 __func__); 6117 6118 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6119 ppd->qsfp_info.cache_valid = 0; 6120 ppd->qsfp_info.cache_refresh_required = 1; 6121 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6122 flags); 6123 6124 /* 6125 * Stop inversion of ModPresent pin to detect 6126 * removal of the cable 6127 */ 6128 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N; 6129 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6130 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6131 6132 ppd->offline_disabled_reason = 6133 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 6134 } 6135 } 6136 6137 if (reg & QSFP_HFI0_INT_N) { 6138 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n", 6139 __func__); 6140 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6141 ppd->qsfp_info.check_interrupt_flags = 1; 6142 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags); 6143 } 6144 6145 /* Schedule the QSFP work only if there is a cable attached. */ 6146 if (qsfp_mod_present(ppd)) 6147 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work); 6148 } 6149 6150 static int request_host_lcb_access(struct hfi1_devdata *dd) 6151 { 6152 int ret; 6153 6154 ret = do_8051_command(dd, HCMD_MISC, 6155 (u64)HCMD_MISC_REQUEST_LCB_ACCESS << 6156 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6157 if (ret != HCMD_SUCCESS) { 6158 dd_dev_err(dd, "%s: command failed with error %d\n", 6159 __func__, ret); 6160 } 6161 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6162 } 6163 6164 static int request_8051_lcb_access(struct hfi1_devdata *dd) 6165 { 6166 int ret; 6167 6168 ret = do_8051_command(dd, HCMD_MISC, 6169 (u64)HCMD_MISC_GRANT_LCB_ACCESS << 6170 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6171 if (ret != HCMD_SUCCESS) { 6172 dd_dev_err(dd, "%s: command failed with error %d\n", 6173 __func__, ret); 6174 } 6175 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6176 } 6177 6178 /* 6179 * Set the LCB selector - allow host access. The DCC selector always 6180 * points to the host. 6181 */ 6182 static inline void set_host_lcb_access(struct hfi1_devdata *dd) 6183 { 6184 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6185 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK | 6186 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK); 6187 } 6188 6189 /* 6190 * Clear the LCB selector - allow 8051 access. The DCC selector always 6191 * points to the host. 6192 */ 6193 static inline void set_8051_lcb_access(struct hfi1_devdata *dd) 6194 { 6195 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6196 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK); 6197 } 6198 6199 /* 6200 * Acquire LCB access from the 8051. If the host already has access, 6201 * just increment a counter. Otherwise, inform the 8051 that the 6202 * host is taking access. 6203 * 6204 * Returns: 6205 * 0 on success 6206 * -EBUSY if the 8051 has control and cannot be disturbed 6207 * -errno if unable to acquire access from the 8051 6208 */ 6209 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6210 { 6211 struct hfi1_pportdata *ppd = dd->pport; 6212 int ret = 0; 6213 6214 /* 6215 * Use the host link state lock so the operation of this routine 6216 * { link state check, selector change, count increment } can occur 6217 * as a unit against a link state change. Otherwise there is a 6218 * race between the state change and the count increment. 6219 */ 6220 if (sleep_ok) { 6221 mutex_lock(&ppd->hls_lock); 6222 } else { 6223 while (!mutex_trylock(&ppd->hls_lock)) 6224 udelay(1); 6225 } 6226 6227 /* this access is valid only when the link is up */ 6228 if (ppd->host_link_state & HLS_DOWN) { 6229 dd_dev_info(dd, "%s: link state %s not up\n", 6230 __func__, link_state_name(ppd->host_link_state)); 6231 ret = -EBUSY; 6232 goto done; 6233 } 6234 6235 if (dd->lcb_access_count == 0) { 6236 ret = request_host_lcb_access(dd); 6237 if (ret) { 6238 dd_dev_err(dd, 6239 "%s: unable to acquire LCB access, err %d\n", 6240 __func__, ret); 6241 goto done; 6242 } 6243 set_host_lcb_access(dd); 6244 } 6245 dd->lcb_access_count++; 6246 done: 6247 mutex_unlock(&ppd->hls_lock); 6248 return ret; 6249 } 6250 6251 /* 6252 * Release LCB access by decrementing the use count. If the count is moving 6253 * from 1 to 0, inform 8051 that it has control back. 6254 * 6255 * Returns: 6256 * 0 on success 6257 * -errno if unable to release access to the 8051 6258 */ 6259 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6260 { 6261 int ret = 0; 6262 6263 /* 6264 * Use the host link state lock because the acquire needed it. 6265 * Here, we only need to keep { selector change, count decrement } 6266 * as a unit. 6267 */ 6268 if (sleep_ok) { 6269 mutex_lock(&dd->pport->hls_lock); 6270 } else { 6271 while (!mutex_trylock(&dd->pport->hls_lock)) 6272 udelay(1); 6273 } 6274 6275 if (dd->lcb_access_count == 0) { 6276 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n", 6277 __func__); 6278 goto done; 6279 } 6280 6281 if (dd->lcb_access_count == 1) { 6282 set_8051_lcb_access(dd); 6283 ret = request_8051_lcb_access(dd); 6284 if (ret) { 6285 dd_dev_err(dd, 6286 "%s: unable to release LCB access, err %d\n", 6287 __func__, ret); 6288 /* restore host access if the grant didn't work */ 6289 set_host_lcb_access(dd); 6290 goto done; 6291 } 6292 } 6293 dd->lcb_access_count--; 6294 done: 6295 mutex_unlock(&dd->pport->hls_lock); 6296 return ret; 6297 } 6298 6299 /* 6300 * Initialize LCB access variables and state. Called during driver load, 6301 * after most of the initialization is finished. 6302 * 6303 * The DC default is LCB access on for the host. The driver defaults to 6304 * leaving access to the 8051. Assign access now - this constrains the call 6305 * to this routine to be after all LCB set-up is done. In particular, after 6306 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts() 6307 */ 6308 static void init_lcb_access(struct hfi1_devdata *dd) 6309 { 6310 dd->lcb_access_count = 0; 6311 } 6312 6313 /* 6314 * Write a response back to a 8051 request. 6315 */ 6316 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data) 6317 { 6318 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 6319 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK | 6320 (u64)return_code << 6321 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT | 6322 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 6323 } 6324 6325 /* 6326 * Handle host requests from the 8051. 6327 */ 6328 static void handle_8051_request(struct hfi1_pportdata *ppd) 6329 { 6330 struct hfi1_devdata *dd = ppd->dd; 6331 u64 reg; 6332 u16 data = 0; 6333 u8 type; 6334 6335 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); 6336 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0) 6337 return; /* no request */ 6338 6339 /* zero out COMPLETED so the response is seen */ 6340 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); 6341 6342 /* extract request details */ 6343 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT) 6344 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK; 6345 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT) 6346 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK; 6347 6348 switch (type) { 6349 case HREQ_LOAD_CONFIG: 6350 case HREQ_SAVE_CONFIG: 6351 case HREQ_READ_CONFIG: 6352 case HREQ_SET_TX_EQ_ABS: 6353 case HREQ_SET_TX_EQ_REL: 6354 case HREQ_ENABLE: 6355 dd_dev_info(dd, "8051 request: request 0x%x not supported\n", 6356 type); 6357 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6358 break; 6359 case HREQ_LCB_RESET: 6360 /* Put the LCB, RX FPE and TX FPE into reset */ 6361 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); 6362 /* Make sure the write completed */ 6363 (void)read_csr(dd, DCC_CFG_RESET); 6364 /* Hold the reset long enough to take effect */ 6365 udelay(1); 6366 /* Take the LCB, RX FPE and TX FPE out of reset */ 6367 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6368 hreq_response(dd, HREQ_SUCCESS, 0); 6369 6370 break; 6371 case HREQ_CONFIG_DONE: 6372 hreq_response(dd, HREQ_SUCCESS, 0); 6373 break; 6374 6375 case HREQ_INTERFACE_TEST: 6376 hreq_response(dd, HREQ_SUCCESS, data); 6377 break; 6378 default: 6379 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type); 6380 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6381 break; 6382 } 6383 } 6384 6385 /* 6386 * Set up allocation unit vaulue. 6387 */ 6388 void set_up_vau(struct hfi1_devdata *dd, u8 vau) 6389 { 6390 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6391 6392 /* do not modify other values in the register */ 6393 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK; 6394 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT; 6395 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6396 } 6397 6398 /* 6399 * Set up initial VL15 credits of the remote. Assumes the rest of 6400 * the CM credit registers are zero from a previous global or credit reset. 6401 * Shared limit for VL15 will always be 0. 6402 */ 6403 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf) 6404 { 6405 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6406 6407 /* set initial values for total and shared credit limit */ 6408 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK | 6409 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK); 6410 6411 /* 6412 * Set total limit to be equal to VL15 credits. 6413 * Leave shared limit at 0. 6414 */ 6415 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 6416 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6417 6418 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf 6419 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); 6420 } 6421 6422 /* 6423 * Zero all credit details from the previous connection and 6424 * reset the CM manager's internal counters. 6425 */ 6426 void reset_link_credits(struct hfi1_devdata *dd) 6427 { 6428 int i; 6429 6430 /* remove all previous VL credit limits */ 6431 for (i = 0; i < TXE_NUM_DATA_VL; i++) 6432 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 6433 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 6434 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); 6435 /* reset the CM block */ 6436 pio_send_control(dd, PSC_CM_RESET); 6437 /* reset cached value */ 6438 dd->vl15buf_cached = 0; 6439 } 6440 6441 /* convert a vCU to a CU */ 6442 static u32 vcu_to_cu(u8 vcu) 6443 { 6444 return 1 << vcu; 6445 } 6446 6447 /* convert a CU to a vCU */ 6448 static u8 cu_to_vcu(u32 cu) 6449 { 6450 return ilog2(cu); 6451 } 6452 6453 /* convert a vAU to an AU */ 6454 static u32 vau_to_au(u8 vau) 6455 { 6456 return 8 * (1 << vau); 6457 } 6458 6459 static void set_linkup_defaults(struct hfi1_pportdata *ppd) 6460 { 6461 ppd->sm_trap_qp = 0x0; 6462 ppd->sa_qp = 0x1; 6463 } 6464 6465 /* 6466 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset. 6467 */ 6468 static void lcb_shutdown(struct hfi1_devdata *dd, int abort) 6469 { 6470 u64 reg; 6471 6472 /* clear lcb run: LCB_CFG_RUN.EN = 0 */ 6473 write_csr(dd, DC_LCB_CFG_RUN, 0); 6474 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */ 6475 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 6476 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT); 6477 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */ 6478 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); 6479 reg = read_csr(dd, DCC_CFG_RESET); 6480 write_csr(dd, DCC_CFG_RESET, reg | 6481 DCC_CFG_RESET_RESET_LCB | DCC_CFG_RESET_RESET_RX_FPE); 6482 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ 6483 if (!abort) { 6484 udelay(1); /* must hold for the longer of 16cclks or 20ns */ 6485 write_csr(dd, DCC_CFG_RESET, reg); 6486 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6487 } 6488 } 6489 6490 /* 6491 * This routine should be called after the link has been transitioned to 6492 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into 6493 * reset). 6494 * 6495 * The expectation is that the caller of this routine would have taken 6496 * care of properly transitioning the link into the correct state. 6497 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6498 * before calling this function. 6499 */ 6500 static void _dc_shutdown(struct hfi1_devdata *dd) 6501 { 6502 lockdep_assert_held(&dd->dc8051_lock); 6503 6504 if (dd->dc_shutdown) 6505 return; 6506 6507 dd->dc_shutdown = 1; 6508 /* Shutdown the LCB */ 6509 lcb_shutdown(dd, 1); 6510 /* 6511 * Going to OFFLINE would have causes the 8051 to put the 6512 * SerDes into reset already. Just need to shut down the 8051, 6513 * itself. 6514 */ 6515 write_csr(dd, DC_DC8051_CFG_RST, 0x1); 6516 } 6517 6518 static void dc_shutdown(struct hfi1_devdata *dd) 6519 { 6520 mutex_lock(&dd->dc8051_lock); 6521 _dc_shutdown(dd); 6522 mutex_unlock(&dd->dc8051_lock); 6523 } 6524 6525 /* 6526 * Calling this after the DC has been brought out of reset should not 6527 * do any damage. 6528 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6529 * before calling this function. 6530 */ 6531 static void _dc_start(struct hfi1_devdata *dd) 6532 { 6533 lockdep_assert_held(&dd->dc8051_lock); 6534 6535 if (!dd->dc_shutdown) 6536 return; 6537 6538 /* Take the 8051 out of reset */ 6539 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 6540 /* Wait until 8051 is ready */ 6541 if (wait_fm_ready(dd, TIMEOUT_8051_START)) 6542 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n", 6543 __func__); 6544 6545 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */ 6546 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6547 /* lcb_shutdown() with abort=1 does not restore these */ 6548 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6549 dd->dc_shutdown = 0; 6550 } 6551 6552 static void dc_start(struct hfi1_devdata *dd) 6553 { 6554 mutex_lock(&dd->dc8051_lock); 6555 _dc_start(dd); 6556 mutex_unlock(&dd->dc8051_lock); 6557 } 6558 6559 /* 6560 * These LCB adjustments are for the Aurora SerDes core in the FPGA. 6561 */ 6562 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd) 6563 { 6564 u64 rx_radr, tx_radr; 6565 u32 version; 6566 6567 if (dd->icode != ICODE_FPGA_EMULATION) 6568 return; 6569 6570 /* 6571 * These LCB defaults on emulator _s are good, nothing to do here: 6572 * LCB_CFG_TX_FIFOS_RADR 6573 * LCB_CFG_RX_FIFOS_RADR 6574 * LCB_CFG_LN_DCLK 6575 * LCB_CFG_IGNORE_LOST_RCLK 6576 */ 6577 if (is_emulator_s(dd)) 6578 return; 6579 /* else this is _p */ 6580 6581 version = emulator_rev(dd); 6582 if (!is_ax(dd)) 6583 version = 0x2d; /* all B0 use 0x2d or higher settings */ 6584 6585 if (version <= 0x12) { 6586 /* release 0x12 and below */ 6587 6588 /* 6589 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9 6590 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9 6591 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa 6592 */ 6593 rx_radr = 6594 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6595 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6596 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6597 /* 6598 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default) 6599 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6 6600 */ 6601 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6602 } else if (version <= 0x18) { 6603 /* release 0x13 up to 0x18 */ 6604 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6605 rx_radr = 6606 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6607 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6608 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6609 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6610 } else if (version == 0x19) { 6611 /* release 0x19 */ 6612 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */ 6613 rx_radr = 6614 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6615 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6616 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6617 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6618 } else if (version == 0x1a) { 6619 /* release 0x1a */ 6620 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6621 rx_radr = 6622 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6623 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6624 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6625 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6626 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); 6627 } else { 6628 /* release 0x1b and higher */ 6629 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */ 6630 rx_radr = 6631 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6632 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6633 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6634 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6635 } 6636 6637 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); 6638 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */ 6639 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 6640 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 6641 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); 6642 } 6643 6644 /* 6645 * Handle a SMA idle message 6646 * 6647 * This is a work-queue function outside of the interrupt. 6648 */ 6649 void handle_sma_message(struct work_struct *work) 6650 { 6651 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6652 sma_message_work); 6653 struct hfi1_devdata *dd = ppd->dd; 6654 u64 msg; 6655 int ret; 6656 6657 /* 6658 * msg is bytes 1-4 of the 40-bit idle message - the command code 6659 * is stripped off 6660 */ 6661 ret = read_idle_sma(dd, &msg); 6662 if (ret) 6663 return; 6664 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg); 6665 /* 6666 * React to the SMA message. Byte[1] (0 for us) is the command. 6667 */ 6668 switch (msg & 0xff) { 6669 case SMA_IDLE_ARM: 6670 /* 6671 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6672 * State Transitions 6673 * 6674 * Only expected in INIT or ARMED, discard otherwise. 6675 */ 6676 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED)) 6677 ppd->neighbor_normal = 1; 6678 break; 6679 case SMA_IDLE_ACTIVE: 6680 /* 6681 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6682 * State Transitions 6683 * 6684 * Can activate the node. Discard otherwise. 6685 */ 6686 if (ppd->host_link_state == HLS_UP_ARMED && 6687 ppd->is_active_optimize_enabled) { 6688 ppd->neighbor_normal = 1; 6689 ret = set_link_state(ppd, HLS_UP_ACTIVE); 6690 if (ret) 6691 dd_dev_err( 6692 dd, 6693 "%s: received Active SMA idle message, couldn't set link to Active\n", 6694 __func__); 6695 } 6696 break; 6697 default: 6698 dd_dev_err(dd, 6699 "%s: received unexpected SMA idle message 0x%llx\n", 6700 __func__, msg); 6701 break; 6702 } 6703 } 6704 6705 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear) 6706 { 6707 u64 rcvctrl; 6708 unsigned long flags; 6709 6710 spin_lock_irqsave(&dd->rcvctrl_lock, flags); 6711 rcvctrl = read_csr(dd, RCV_CTRL); 6712 rcvctrl |= add; 6713 rcvctrl &= ~clear; 6714 write_csr(dd, RCV_CTRL, rcvctrl); 6715 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags); 6716 } 6717 6718 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add) 6719 { 6720 adjust_rcvctrl(dd, add, 0); 6721 } 6722 6723 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear) 6724 { 6725 adjust_rcvctrl(dd, 0, clear); 6726 } 6727 6728 /* 6729 * Called from all interrupt handlers to start handling an SPC freeze. 6730 */ 6731 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags) 6732 { 6733 struct hfi1_devdata *dd = ppd->dd; 6734 struct send_context *sc; 6735 int i; 6736 6737 if (flags & FREEZE_SELF) 6738 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6739 6740 /* enter frozen mode */ 6741 dd->flags |= HFI1_FROZEN; 6742 6743 /* notify all SDMA engines that they are going into a freeze */ 6744 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN)); 6745 6746 /* do halt pre-handling on all enabled send contexts */ 6747 for (i = 0; i < dd->num_send_contexts; i++) { 6748 sc = dd->send_contexts[i].sc; 6749 if (sc && (sc->flags & SCF_ENABLED)) 6750 sc_stop(sc, SCF_FROZEN | SCF_HALTED); 6751 } 6752 6753 /* Send context are frozen. Notify user space */ 6754 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT); 6755 6756 if (flags & FREEZE_ABORT) { 6757 dd_dev_err(dd, 6758 "Aborted freeze recovery. Please REBOOT system\n"); 6759 return; 6760 } 6761 /* queue non-interrupt handler */ 6762 queue_work(ppd->hfi1_wq, &ppd->freeze_work); 6763 } 6764 6765 /* 6766 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen, 6767 * depending on the "freeze" parameter. 6768 * 6769 * No need to return an error if it times out, our only option 6770 * is to proceed anyway. 6771 */ 6772 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze) 6773 { 6774 unsigned long timeout; 6775 u64 reg; 6776 6777 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT); 6778 while (1) { 6779 reg = read_csr(dd, CCE_STATUS); 6780 if (freeze) { 6781 /* waiting until all indicators are set */ 6782 if ((reg & ALL_FROZE) == ALL_FROZE) 6783 return; /* all done */ 6784 } else { 6785 /* waiting until all indicators are clear */ 6786 if ((reg & ALL_FROZE) == 0) 6787 return; /* all done */ 6788 } 6789 6790 if (time_after(jiffies, timeout)) { 6791 dd_dev_err(dd, 6792 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing", 6793 freeze ? "" : "un", reg & ALL_FROZE, 6794 freeze ? ALL_FROZE : 0ull); 6795 return; 6796 } 6797 usleep_range(80, 120); 6798 } 6799 } 6800 6801 /* 6802 * Do all freeze handling for the RXE block. 6803 */ 6804 static void rxe_freeze(struct hfi1_devdata *dd) 6805 { 6806 int i; 6807 struct hfi1_ctxtdata *rcd; 6808 6809 /* disable port */ 6810 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6811 6812 /* disable all receive contexts */ 6813 for (i = 0; i < dd->num_rcv_contexts; i++) { 6814 rcd = hfi1_rcd_get_by_index(dd, i); 6815 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd); 6816 hfi1_rcd_put(rcd); 6817 } 6818 } 6819 6820 /* 6821 * Unfreeze handling for the RXE block - kernel contexts only. 6822 * This will also enable the port. User contexts will do unfreeze 6823 * handling on a per-context basis as they call into the driver. 6824 * 6825 */ 6826 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd) 6827 { 6828 u32 rcvmask; 6829 u16 i; 6830 struct hfi1_ctxtdata *rcd; 6831 6832 /* enable all kernel contexts */ 6833 for (i = 0; i < dd->num_rcv_contexts; i++) { 6834 rcd = hfi1_rcd_get_by_index(dd, i); 6835 6836 /* Ensure all non-user contexts(including vnic) are enabled */ 6837 if (!rcd || 6838 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) { 6839 hfi1_rcd_put(rcd); 6840 continue; 6841 } 6842 rcvmask = HFI1_RCVCTRL_CTXT_ENB; 6843 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */ 6844 rcvmask |= rcd->rcvhdrtail_kvaddr ? 6845 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 6846 hfi1_rcvctrl(dd, rcvmask, rcd); 6847 hfi1_rcd_put(rcd); 6848 } 6849 6850 /* enable port */ 6851 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6852 } 6853 6854 /* 6855 * Non-interrupt SPC freeze handling. 6856 * 6857 * This is a work-queue function outside of the triggering interrupt. 6858 */ 6859 void handle_freeze(struct work_struct *work) 6860 { 6861 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6862 freeze_work); 6863 struct hfi1_devdata *dd = ppd->dd; 6864 6865 /* wait for freeze indicators on all affected blocks */ 6866 wait_for_freeze_status(dd, 1); 6867 6868 /* SPC is now frozen */ 6869 6870 /* do send PIO freeze steps */ 6871 pio_freeze(dd); 6872 6873 /* do send DMA freeze steps */ 6874 sdma_freeze(dd); 6875 6876 /* do send egress freeze steps - nothing to do */ 6877 6878 /* do receive freeze steps */ 6879 rxe_freeze(dd); 6880 6881 /* 6882 * Unfreeze the hardware - clear the freeze, wait for each 6883 * block's frozen bit to clear, then clear the frozen flag. 6884 */ 6885 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6886 wait_for_freeze_status(dd, 0); 6887 6888 if (is_ax(dd)) { 6889 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6890 wait_for_freeze_status(dd, 1); 6891 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6892 wait_for_freeze_status(dd, 0); 6893 } 6894 6895 /* do send PIO unfreeze steps for kernel contexts */ 6896 pio_kernel_unfreeze(dd); 6897 6898 /* do send DMA unfreeze steps */ 6899 sdma_unfreeze(dd); 6900 6901 /* do send egress unfreeze steps - nothing to do */ 6902 6903 /* do receive unfreeze steps for kernel contexts */ 6904 rxe_kernel_unfreeze(dd); 6905 6906 /* 6907 * The unfreeze procedure touches global device registers when 6908 * it disables and re-enables RXE. Mark the device unfrozen 6909 * after all that is done so other parts of the driver waiting 6910 * for the device to unfreeze don't do things out of order. 6911 * 6912 * The above implies that the meaning of HFI1_FROZEN flag is 6913 * "Device has gone into freeze mode and freeze mode handling 6914 * is still in progress." 6915 * 6916 * The flag will be removed when freeze mode processing has 6917 * completed. 6918 */ 6919 dd->flags &= ~HFI1_FROZEN; 6920 wake_up(&dd->event_queue); 6921 6922 /* no longer frozen */ 6923 } 6924 6925 /** 6926 * update_xmit_counters - update PortXmitWait/PortVlXmitWait 6927 * counters. 6928 * @ppd: info of physical Hfi port 6929 * @link_width: new link width after link up or downgrade 6930 * 6931 * Update the PortXmitWait and PortVlXmitWait counters after 6932 * a link up or downgrade event to reflect a link width change. 6933 */ 6934 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width) 6935 { 6936 int i; 6937 u16 tx_width; 6938 u16 link_speed; 6939 6940 tx_width = tx_link_width(link_width); 6941 link_speed = get_link_speed(ppd->link_speed_active); 6942 6943 /* 6944 * There are C_VL_COUNT number of PortVLXmitWait counters. 6945 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter. 6946 */ 6947 for (i = 0; i < C_VL_COUNT + 1; i++) 6948 get_xmit_wait_counters(ppd, tx_width, link_speed, i); 6949 } 6950 6951 /* 6952 * Handle a link up interrupt from the 8051. 6953 * 6954 * This is a work-queue function outside of the interrupt. 6955 */ 6956 void handle_link_up(struct work_struct *work) 6957 { 6958 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6959 link_up_work); 6960 struct hfi1_devdata *dd = ppd->dd; 6961 6962 set_link_state(ppd, HLS_UP_INIT); 6963 6964 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */ 6965 read_ltp_rtt(dd); 6966 /* 6967 * OPA specifies that certain counters are cleared on a transition 6968 * to link up, so do that. 6969 */ 6970 clear_linkup_counters(dd); 6971 /* 6972 * And (re)set link up default values. 6973 */ 6974 set_linkup_defaults(ppd); 6975 6976 /* 6977 * Set VL15 credits. Use cached value from verify cap interrupt. 6978 * In case of quick linkup or simulator, vl15 value will be set by 6979 * handle_linkup_change. VerifyCap interrupt handler will not be 6980 * called in those scenarios. 6981 */ 6982 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) 6983 set_up_vl15(dd, dd->vl15buf_cached); 6984 6985 /* enforce link speed enabled */ 6986 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) { 6987 /* oops - current speed is not enabled, bounce */ 6988 dd_dev_err(dd, 6989 "Link speed active 0x%x is outside enabled 0x%x, downing link\n", 6990 ppd->link_speed_active, ppd->link_speed_enabled); 6991 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0, 6992 OPA_LINKDOWN_REASON_SPEED_POLICY); 6993 set_link_state(ppd, HLS_DN_OFFLINE); 6994 start_link(ppd); 6995 } 6996 } 6997 6998 /* 6999 * Several pieces of LNI information were cached for SMA in ppd. 7000 * Reset these on link down 7001 */ 7002 static void reset_neighbor_info(struct hfi1_pportdata *ppd) 7003 { 7004 ppd->neighbor_guid = 0; 7005 ppd->neighbor_port_number = 0; 7006 ppd->neighbor_type = 0; 7007 ppd->neighbor_fm_security = 0; 7008 } 7009 7010 static const char * const link_down_reason_strs[] = { 7011 [OPA_LINKDOWN_REASON_NONE] = "None", 7012 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0", 7013 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length", 7014 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long", 7015 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short", 7016 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID", 7017 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID", 7018 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2", 7019 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC", 7020 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8", 7021 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail", 7022 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10", 7023 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error", 7024 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15", 7025 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker", 7026 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14", 7027 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15", 7028 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance", 7029 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance", 7030 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance", 7031 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack", 7032 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker", 7033 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt", 7034 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit", 7035 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit", 7036 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24", 7037 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25", 7038 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26", 7039 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27", 7040 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28", 7041 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29", 7042 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30", 7043 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] = 7044 "Excessive buffer overrun", 7045 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown", 7046 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot", 7047 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown", 7048 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce", 7049 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy", 7050 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy", 7051 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected", 7052 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] = 7053 "Local media not installed", 7054 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed", 7055 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config", 7056 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] = 7057 "End to end not installed", 7058 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy", 7059 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy", 7060 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy", 7061 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management", 7062 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled", 7063 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient" 7064 }; 7065 7066 /* return the neighbor link down reason string */ 7067 static const char *link_down_reason_str(u8 reason) 7068 { 7069 const char *str = NULL; 7070 7071 if (reason < ARRAY_SIZE(link_down_reason_strs)) 7072 str = link_down_reason_strs[reason]; 7073 if (!str) 7074 str = "(invalid)"; 7075 7076 return str; 7077 } 7078 7079 /* 7080 * Handle a link down interrupt from the 8051. 7081 * 7082 * This is a work-queue function outside of the interrupt. 7083 */ 7084 void handle_link_down(struct work_struct *work) 7085 { 7086 u8 lcl_reason, neigh_reason = 0; 7087 u8 link_down_reason; 7088 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7089 link_down_work); 7090 int was_up; 7091 static const char ldr_str[] = "Link down reason: "; 7092 7093 if ((ppd->host_link_state & 7094 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) && 7095 ppd->port_type == PORT_TYPE_FIXED) 7096 ppd->offline_disabled_reason = 7097 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED); 7098 7099 /* Go offline first, then deal with reading/writing through 8051 */ 7100 was_up = !!(ppd->host_link_state & HLS_UP); 7101 set_link_state(ppd, HLS_DN_OFFLINE); 7102 xchg(&ppd->is_link_down_queued, 0); 7103 7104 if (was_up) { 7105 lcl_reason = 0; 7106 /* link down reason is only valid if the link was up */ 7107 read_link_down_reason(ppd->dd, &link_down_reason); 7108 switch (link_down_reason) { 7109 case LDR_LINK_TRANSFER_ACTIVE_LOW: 7110 /* the link went down, no idle message reason */ 7111 dd_dev_info(ppd->dd, "%sUnexpected link down\n", 7112 ldr_str); 7113 break; 7114 case LDR_RECEIVED_LINKDOWN_IDLE_MSG: 7115 /* 7116 * The neighbor reason is only valid if an idle message 7117 * was received for it. 7118 */ 7119 read_planned_down_reason_code(ppd->dd, &neigh_reason); 7120 dd_dev_info(ppd->dd, 7121 "%sNeighbor link down message %d, %s\n", 7122 ldr_str, neigh_reason, 7123 link_down_reason_str(neigh_reason)); 7124 break; 7125 case LDR_RECEIVED_HOST_OFFLINE_REQ: 7126 dd_dev_info(ppd->dd, 7127 "%sHost requested link to go offline\n", 7128 ldr_str); 7129 break; 7130 default: 7131 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n", 7132 ldr_str, link_down_reason); 7133 break; 7134 } 7135 7136 /* 7137 * If no reason, assume peer-initiated but missed 7138 * LinkGoingDown idle flits. 7139 */ 7140 if (neigh_reason == 0) 7141 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN; 7142 } else { 7143 /* went down while polling or going up */ 7144 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT; 7145 } 7146 7147 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0); 7148 7149 /* inform the SMA when the link transitions from up to down */ 7150 if (was_up && ppd->local_link_down_reason.sma == 0 && 7151 ppd->neigh_link_down_reason.sma == 0) { 7152 ppd->local_link_down_reason.sma = 7153 ppd->local_link_down_reason.latest; 7154 ppd->neigh_link_down_reason.sma = 7155 ppd->neigh_link_down_reason.latest; 7156 } 7157 7158 reset_neighbor_info(ppd); 7159 7160 /* disable the port */ 7161 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 7162 7163 /* 7164 * If there is no cable attached, turn the DC off. Otherwise, 7165 * start the link bring up. 7166 */ 7167 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) 7168 dc_shutdown(ppd->dd); 7169 else 7170 start_link(ppd); 7171 } 7172 7173 void handle_link_bounce(struct work_struct *work) 7174 { 7175 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7176 link_bounce_work); 7177 7178 /* 7179 * Only do something if the link is currently up. 7180 */ 7181 if (ppd->host_link_state & HLS_UP) { 7182 set_link_state(ppd, HLS_DN_OFFLINE); 7183 start_link(ppd); 7184 } else { 7185 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n", 7186 __func__, link_state_name(ppd->host_link_state)); 7187 } 7188 } 7189 7190 /* 7191 * Mask conversion: Capability exchange to Port LTP. The capability 7192 * exchange has an implicit 16b CRC that is mandatory. 7193 */ 7194 static int cap_to_port_ltp(int cap) 7195 { 7196 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */ 7197 7198 if (cap & CAP_CRC_14B) 7199 port_ltp |= PORT_LTP_CRC_MODE_14; 7200 if (cap & CAP_CRC_48B) 7201 port_ltp |= PORT_LTP_CRC_MODE_48; 7202 if (cap & CAP_CRC_12B_16B_PER_LANE) 7203 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE; 7204 7205 return port_ltp; 7206 } 7207 7208 /* 7209 * Convert an OPA Port LTP mask to capability mask 7210 */ 7211 int port_ltp_to_cap(int port_ltp) 7212 { 7213 int cap_mask = 0; 7214 7215 if (port_ltp & PORT_LTP_CRC_MODE_14) 7216 cap_mask |= CAP_CRC_14B; 7217 if (port_ltp & PORT_LTP_CRC_MODE_48) 7218 cap_mask |= CAP_CRC_48B; 7219 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE) 7220 cap_mask |= CAP_CRC_12B_16B_PER_LANE; 7221 7222 return cap_mask; 7223 } 7224 7225 /* 7226 * Convert a single DC LCB CRC mode to an OPA Port LTP mask. 7227 */ 7228 static int lcb_to_port_ltp(int lcb_crc) 7229 { 7230 int port_ltp = 0; 7231 7232 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE) 7233 port_ltp = PORT_LTP_CRC_MODE_PER_LANE; 7234 else if (lcb_crc == LCB_CRC_48B) 7235 port_ltp = PORT_LTP_CRC_MODE_48; 7236 else if (lcb_crc == LCB_CRC_14B) 7237 port_ltp = PORT_LTP_CRC_MODE_14; 7238 else 7239 port_ltp = PORT_LTP_CRC_MODE_16; 7240 7241 return port_ltp; 7242 } 7243 7244 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd) 7245 { 7246 if (ppd->pkeys[2] != 0) { 7247 ppd->pkeys[2] = 0; 7248 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0); 7249 hfi1_event_pkey_change(ppd->dd, ppd->port); 7250 } 7251 } 7252 7253 /* 7254 * Convert the given link width to the OPA link width bitmask. 7255 */ 7256 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width) 7257 { 7258 switch (width) { 7259 case 0: 7260 /* 7261 * Simulator and quick linkup do not set the width. 7262 * Just set it to 4x without complaint. 7263 */ 7264 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup) 7265 return OPA_LINK_WIDTH_4X; 7266 return 0; /* no lanes up */ 7267 case 1: return OPA_LINK_WIDTH_1X; 7268 case 2: return OPA_LINK_WIDTH_2X; 7269 case 3: return OPA_LINK_WIDTH_3X; 7270 default: 7271 dd_dev_info(dd, "%s: invalid width %d, using 4\n", 7272 __func__, width); 7273 /* fall through */ 7274 case 4: return OPA_LINK_WIDTH_4X; 7275 } 7276 } 7277 7278 /* 7279 * Do a population count on the bottom nibble. 7280 */ 7281 static const u8 bit_counts[16] = { 7282 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 7283 }; 7284 7285 static inline u8 nibble_to_count(u8 nibble) 7286 { 7287 return bit_counts[nibble & 0xf]; 7288 } 7289 7290 /* 7291 * Read the active lane information from the 8051 registers and return 7292 * their widths. 7293 * 7294 * Active lane information is found in these 8051 registers: 7295 * enable_lane_tx 7296 * enable_lane_rx 7297 */ 7298 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width, 7299 u16 *rx_width) 7300 { 7301 u16 tx, rx; 7302 u8 enable_lane_rx; 7303 u8 enable_lane_tx; 7304 u8 tx_polarity_inversion; 7305 u8 rx_polarity_inversion; 7306 u8 max_rate; 7307 7308 /* read the active lanes */ 7309 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 7310 &rx_polarity_inversion, &max_rate); 7311 read_local_lni(dd, &enable_lane_rx); 7312 7313 /* convert to counts */ 7314 tx = nibble_to_count(enable_lane_tx); 7315 rx = nibble_to_count(enable_lane_rx); 7316 7317 /* 7318 * Set link_speed_active here, overriding what was set in 7319 * handle_verify_cap(). The ASIC 8051 firmware does not correctly 7320 * set the max_rate field in handle_verify_cap until v0.19. 7321 */ 7322 if ((dd->icode == ICODE_RTL_SILICON) && 7323 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) { 7324 /* max_rate: 0 = 12.5G, 1 = 25G */ 7325 switch (max_rate) { 7326 case 0: 7327 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G; 7328 break; 7329 default: 7330 dd_dev_err(dd, 7331 "%s: unexpected max rate %d, using 25Gb\n", 7332 __func__, (int)max_rate); 7333 /* fall through */ 7334 case 1: 7335 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G; 7336 break; 7337 } 7338 } 7339 7340 dd_dev_info(dd, 7341 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n", 7342 enable_lane_tx, tx, enable_lane_rx, rx); 7343 *tx_width = link_width_to_bits(dd, tx); 7344 *rx_width = link_width_to_bits(dd, rx); 7345 } 7346 7347 /* 7348 * Read verify_cap_local_fm_link_width[1] to obtain the link widths. 7349 * Valid after the end of VerifyCap and during LinkUp. Does not change 7350 * after link up. I.e. look elsewhere for downgrade information. 7351 * 7352 * Bits are: 7353 * + bits [7:4] contain the number of active transmitters 7354 * + bits [3:0] contain the number of active receivers 7355 * These are numbers 1 through 4 and can be different values if the 7356 * link is asymmetric. 7357 * 7358 * verify_cap_local_fm_link_width[0] retains its original value. 7359 */ 7360 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width, 7361 u16 *rx_width) 7362 { 7363 u16 widths, tx, rx; 7364 u8 misc_bits, local_flags; 7365 u16 active_tx, active_rx; 7366 7367 read_vc_local_link_mode(dd, &misc_bits, &local_flags, &widths); 7368 tx = widths >> 12; 7369 rx = (widths >> 8) & 0xf; 7370 7371 *tx_width = link_width_to_bits(dd, tx); 7372 *rx_width = link_width_to_bits(dd, rx); 7373 7374 /* print the active widths */ 7375 get_link_widths(dd, &active_tx, &active_rx); 7376 } 7377 7378 /* 7379 * Set ppd->link_width_active and ppd->link_width_downgrade_active using 7380 * hardware information when the link first comes up. 7381 * 7382 * The link width is not available until after VerifyCap.AllFramesReceived 7383 * (the trigger for handle_verify_cap), so this is outside that routine 7384 * and should be called when the 8051 signals linkup. 7385 */ 7386 void get_linkup_link_widths(struct hfi1_pportdata *ppd) 7387 { 7388 u16 tx_width, rx_width; 7389 7390 /* get end-of-LNI link widths */ 7391 get_linkup_widths(ppd->dd, &tx_width, &rx_width); 7392 7393 /* use tx_width as the link is supposed to be symmetric on link up */ 7394 ppd->link_width_active = tx_width; 7395 /* link width downgrade active (LWD.A) starts out matching LW.A */ 7396 ppd->link_width_downgrade_tx_active = ppd->link_width_active; 7397 ppd->link_width_downgrade_rx_active = ppd->link_width_active; 7398 /* per OPA spec, on link up LWD.E resets to LWD.S */ 7399 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported; 7400 /* cache the active egress rate (units {10^6 bits/sec]) */ 7401 ppd->current_egress_rate = active_egress_rate(ppd); 7402 } 7403 7404 /* 7405 * Handle a verify capabilities interrupt from the 8051. 7406 * 7407 * This is a work-queue function outside of the interrupt. 7408 */ 7409 void handle_verify_cap(struct work_struct *work) 7410 { 7411 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7412 link_vc_work); 7413 struct hfi1_devdata *dd = ppd->dd; 7414 u64 reg; 7415 u8 power_management; 7416 u8 continuous; 7417 u8 vcu; 7418 u8 vau; 7419 u8 z; 7420 u16 vl15buf; 7421 u16 link_widths; 7422 u16 crc_mask; 7423 u16 crc_val; 7424 u16 device_id; 7425 u16 active_tx, active_rx; 7426 u8 partner_supported_crc; 7427 u8 remote_tx_rate; 7428 u8 device_rev; 7429 7430 set_link_state(ppd, HLS_VERIFY_CAP); 7431 7432 lcb_shutdown(dd, 0); 7433 adjust_lcb_for_fpga_serdes(dd); 7434 7435 read_vc_remote_phy(dd, &power_management, &continuous); 7436 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf, 7437 &partner_supported_crc); 7438 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths); 7439 read_remote_device_id(dd, &device_id, &device_rev); 7440 7441 /* print the active widths */ 7442 get_link_widths(dd, &active_tx, &active_rx); 7443 dd_dev_info(dd, 7444 "Peer PHY: power management 0x%x, continuous updates 0x%x\n", 7445 (int)power_management, (int)continuous); 7446 dd_dev_info(dd, 7447 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n", 7448 (int)vau, (int)z, (int)vcu, (int)vl15buf, 7449 (int)partner_supported_crc); 7450 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n", 7451 (u32)remote_tx_rate, (u32)link_widths); 7452 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n", 7453 (u32)device_id, (u32)device_rev); 7454 /* 7455 * The peer vAU value just read is the peer receiver value. HFI does 7456 * not support a transmit vAU of 0 (AU == 8). We advertised that 7457 * with Z=1 in the fabric capabilities sent to the peer. The peer 7458 * will see our Z=1, and, if it advertised a vAU of 0, will move its 7459 * receive to vAU of 1 (AU == 16). Do the same here. We do not care 7460 * about the peer Z value - our sent vAU is 3 (hardwired) and is not 7461 * subject to the Z value exception. 7462 */ 7463 if (vau == 0) 7464 vau = 1; 7465 set_up_vau(dd, vau); 7466 7467 /* 7468 * Set VL15 credits to 0 in global credit register. Cache remote VL15 7469 * credits value and wait for link-up interrupt ot set it. 7470 */ 7471 set_up_vl15(dd, 0); 7472 dd->vl15buf_cached = vl15buf; 7473 7474 /* set up the LCB CRC mode */ 7475 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc; 7476 7477 /* order is important: use the lowest bit in common */ 7478 if (crc_mask & CAP_CRC_14B) 7479 crc_val = LCB_CRC_14B; 7480 else if (crc_mask & CAP_CRC_48B) 7481 crc_val = LCB_CRC_48B; 7482 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE) 7483 crc_val = LCB_CRC_12B_16B_PER_LANE; 7484 else 7485 crc_val = LCB_CRC_16B; 7486 7487 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val); 7488 write_csr(dd, DC_LCB_CFG_CRC_MODE, 7489 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT); 7490 7491 /* set (14b only) or clear sideband credit */ 7492 reg = read_csr(dd, SEND_CM_CTRL); 7493 if (crc_val == LCB_CRC_14B && crc_14b_sideband) { 7494 write_csr(dd, SEND_CM_CTRL, 7495 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7496 } else { 7497 write_csr(dd, SEND_CM_CTRL, 7498 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7499 } 7500 7501 ppd->link_speed_active = 0; /* invalid value */ 7502 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 7503 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */ 7504 switch (remote_tx_rate) { 7505 case 0: 7506 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7507 break; 7508 case 1: 7509 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7510 break; 7511 } 7512 } else { 7513 /* actual rate is highest bit of the ANDed rates */ 7514 u8 rate = remote_tx_rate & ppd->local_tx_rate; 7515 7516 if (rate & 2) 7517 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7518 else if (rate & 1) 7519 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7520 } 7521 if (ppd->link_speed_active == 0) { 7522 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n", 7523 __func__, (int)remote_tx_rate); 7524 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7525 } 7526 7527 /* 7528 * Cache the values of the supported, enabled, and active 7529 * LTP CRC modes to return in 'portinfo' queries. But the bit 7530 * flags that are returned in the portinfo query differ from 7531 * what's in the link_crc_mask, crc_sizes, and crc_val 7532 * variables. Convert these here. 7533 */ 7534 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 7535 /* supported crc modes */ 7536 ppd->port_ltp_crc_mode |= 7537 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4; 7538 /* enabled crc modes */ 7539 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val); 7540 /* active crc mode */ 7541 7542 /* set up the remote credit return table */ 7543 assign_remote_cm_au_table(dd, vcu); 7544 7545 /* 7546 * The LCB is reset on entry to handle_verify_cap(), so this must 7547 * be applied on every link up. 7548 * 7549 * Adjust LCB error kill enable to kill the link if 7550 * these RBUF errors are seen: 7551 * REPLAY_BUF_MBE_SMASK 7552 * FLIT_INPUT_BUF_MBE_SMASK 7553 */ 7554 if (is_ax(dd)) { /* fixed in B0 */ 7555 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); 7556 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 7557 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK; 7558 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); 7559 } 7560 7561 /* pull LCB fifos out of reset - all fifo clocks must be stable */ 7562 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 7563 7564 /* give 8051 access to the LCB CSRs */ 7565 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 7566 set_8051_lcb_access(dd); 7567 7568 /* tell the 8051 to go to LinkUp */ 7569 set_link_state(ppd, HLS_GOING_UP); 7570 } 7571 7572 /** 7573 * apply_link_downgrade_policy - Apply the link width downgrade enabled 7574 * policy against the current active link widths. 7575 * @ppd: info of physical Hfi port 7576 * @refresh_widths: True indicates link downgrade event 7577 * @return: True indicates a successful link downgrade. False indicates 7578 * link downgrade event failed and the link will bounce back to 7579 * default link width. 7580 * 7581 * Called when the enabled policy changes or the active link widths 7582 * change. 7583 * Refresh_widths indicates that a link downgrade occurred. The 7584 * link_downgraded variable is set by refresh_widths and 7585 * determines the success/failure of the policy application. 7586 */ 7587 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, 7588 bool refresh_widths) 7589 { 7590 int do_bounce = 0; 7591 int tries; 7592 u16 lwde; 7593 u16 tx, rx; 7594 bool link_downgraded = refresh_widths; 7595 7596 /* use the hls lock to avoid a race with actual link up */ 7597 tries = 0; 7598 retry: 7599 mutex_lock(&ppd->hls_lock); 7600 /* only apply if the link is up */ 7601 if (ppd->host_link_state & HLS_DOWN) { 7602 /* still going up..wait and retry */ 7603 if (ppd->host_link_state & HLS_GOING_UP) { 7604 if (++tries < 1000) { 7605 mutex_unlock(&ppd->hls_lock); 7606 usleep_range(100, 120); /* arbitrary */ 7607 goto retry; 7608 } 7609 dd_dev_err(ppd->dd, 7610 "%s: giving up waiting for link state change\n", 7611 __func__); 7612 } 7613 goto done; 7614 } 7615 7616 lwde = ppd->link_width_downgrade_enabled; 7617 7618 if (refresh_widths) { 7619 get_link_widths(ppd->dd, &tx, &rx); 7620 ppd->link_width_downgrade_tx_active = tx; 7621 ppd->link_width_downgrade_rx_active = rx; 7622 } 7623 7624 if (ppd->link_width_downgrade_tx_active == 0 || 7625 ppd->link_width_downgrade_rx_active == 0) { 7626 /* the 8051 reported a dead link as a downgrade */ 7627 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n"); 7628 link_downgraded = false; 7629 } else if (lwde == 0) { 7630 /* downgrade is disabled */ 7631 7632 /* bounce if not at starting active width */ 7633 if ((ppd->link_width_active != 7634 ppd->link_width_downgrade_tx_active) || 7635 (ppd->link_width_active != 7636 ppd->link_width_downgrade_rx_active)) { 7637 dd_dev_err(ppd->dd, 7638 "Link downgrade is disabled and link has downgraded, downing link\n"); 7639 dd_dev_err(ppd->dd, 7640 " original 0x%x, tx active 0x%x, rx active 0x%x\n", 7641 ppd->link_width_active, 7642 ppd->link_width_downgrade_tx_active, 7643 ppd->link_width_downgrade_rx_active); 7644 do_bounce = 1; 7645 link_downgraded = false; 7646 } 7647 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 || 7648 (lwde & ppd->link_width_downgrade_rx_active) == 0) { 7649 /* Tx or Rx is outside the enabled policy */ 7650 dd_dev_err(ppd->dd, 7651 "Link is outside of downgrade allowed, downing link\n"); 7652 dd_dev_err(ppd->dd, 7653 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n", 7654 lwde, ppd->link_width_downgrade_tx_active, 7655 ppd->link_width_downgrade_rx_active); 7656 do_bounce = 1; 7657 link_downgraded = false; 7658 } 7659 7660 done: 7661 mutex_unlock(&ppd->hls_lock); 7662 7663 if (do_bounce) { 7664 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0, 7665 OPA_LINKDOWN_REASON_WIDTH_POLICY); 7666 set_link_state(ppd, HLS_DN_OFFLINE); 7667 start_link(ppd); 7668 } 7669 7670 return link_downgraded; 7671 } 7672 7673 /* 7674 * Handle a link downgrade interrupt from the 8051. 7675 * 7676 * This is a work-queue function outside of the interrupt. 7677 */ 7678 void handle_link_downgrade(struct work_struct *work) 7679 { 7680 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7681 link_downgrade_work); 7682 7683 dd_dev_info(ppd->dd, "8051: Link width downgrade\n"); 7684 if (apply_link_downgrade_policy(ppd, true)) 7685 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active); 7686 } 7687 7688 static char *dcc_err_string(char *buf, int buf_len, u64 flags) 7689 { 7690 return flag_string(buf, buf_len, flags, dcc_err_flags, 7691 ARRAY_SIZE(dcc_err_flags)); 7692 } 7693 7694 static char *lcb_err_string(char *buf, int buf_len, u64 flags) 7695 { 7696 return flag_string(buf, buf_len, flags, lcb_err_flags, 7697 ARRAY_SIZE(lcb_err_flags)); 7698 } 7699 7700 static char *dc8051_err_string(char *buf, int buf_len, u64 flags) 7701 { 7702 return flag_string(buf, buf_len, flags, dc8051_err_flags, 7703 ARRAY_SIZE(dc8051_err_flags)); 7704 } 7705 7706 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags) 7707 { 7708 return flag_string(buf, buf_len, flags, dc8051_info_err_flags, 7709 ARRAY_SIZE(dc8051_info_err_flags)); 7710 } 7711 7712 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags) 7713 { 7714 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags, 7715 ARRAY_SIZE(dc8051_info_host_msg_flags)); 7716 } 7717 7718 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg) 7719 { 7720 struct hfi1_pportdata *ppd = dd->pport; 7721 u64 info, err, host_msg; 7722 int queue_link_down = 0; 7723 char buf[96]; 7724 7725 /* look at the flags */ 7726 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) { 7727 /* 8051 information set by firmware */ 7728 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */ 7729 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); 7730 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT) 7731 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK; 7732 host_msg = (info >> 7733 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT) 7734 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK; 7735 7736 /* 7737 * Handle error flags. 7738 */ 7739 if (err & FAILED_LNI) { 7740 /* 7741 * LNI error indications are cleared by the 8051 7742 * only when starting polling. Only pay attention 7743 * to them when in the states that occur during 7744 * LNI. 7745 */ 7746 if (ppd->host_link_state 7747 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 7748 queue_link_down = 1; 7749 dd_dev_info(dd, "Link error: %s\n", 7750 dc8051_info_err_string(buf, 7751 sizeof(buf), 7752 err & 7753 FAILED_LNI)); 7754 } 7755 err &= ~(u64)FAILED_LNI; 7756 } 7757 /* unknown frames can happen durning LNI, just count */ 7758 if (err & UNKNOWN_FRAME) { 7759 ppd->unknown_frame_count++; 7760 err &= ~(u64)UNKNOWN_FRAME; 7761 } 7762 if (err) { 7763 /* report remaining errors, but do not do anything */ 7764 dd_dev_err(dd, "8051 info error: %s\n", 7765 dc8051_info_err_string(buf, sizeof(buf), 7766 err)); 7767 } 7768 7769 /* 7770 * Handle host message flags. 7771 */ 7772 if (host_msg & HOST_REQ_DONE) { 7773 /* 7774 * Presently, the driver does a busy wait for 7775 * host requests to complete. This is only an 7776 * informational message. 7777 * NOTE: The 8051 clears the host message 7778 * information *on the next 8051 command*. 7779 * Therefore, when linkup is achieved, 7780 * this flag will still be set. 7781 */ 7782 host_msg &= ~(u64)HOST_REQ_DONE; 7783 } 7784 if (host_msg & BC_SMA_MSG) { 7785 queue_work(ppd->link_wq, &ppd->sma_message_work); 7786 host_msg &= ~(u64)BC_SMA_MSG; 7787 } 7788 if (host_msg & LINKUP_ACHIEVED) { 7789 dd_dev_info(dd, "8051: Link up\n"); 7790 queue_work(ppd->link_wq, &ppd->link_up_work); 7791 host_msg &= ~(u64)LINKUP_ACHIEVED; 7792 } 7793 if (host_msg & EXT_DEVICE_CFG_REQ) { 7794 handle_8051_request(ppd); 7795 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ; 7796 } 7797 if (host_msg & VERIFY_CAP_FRAME) { 7798 queue_work(ppd->link_wq, &ppd->link_vc_work); 7799 host_msg &= ~(u64)VERIFY_CAP_FRAME; 7800 } 7801 if (host_msg & LINK_GOING_DOWN) { 7802 const char *extra = ""; 7803 /* no downgrade action needed if going down */ 7804 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7805 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7806 extra = " (ignoring downgrade)"; 7807 } 7808 dd_dev_info(dd, "8051: Link down%s\n", extra); 7809 queue_link_down = 1; 7810 host_msg &= ~(u64)LINK_GOING_DOWN; 7811 } 7812 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7813 queue_work(ppd->link_wq, &ppd->link_downgrade_work); 7814 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7815 } 7816 if (host_msg) { 7817 /* report remaining messages, but do not do anything */ 7818 dd_dev_info(dd, "8051 info host message: %s\n", 7819 dc8051_info_host_msg_string(buf, 7820 sizeof(buf), 7821 host_msg)); 7822 } 7823 7824 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK; 7825 } 7826 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) { 7827 /* 7828 * Lost the 8051 heartbeat. If this happens, we 7829 * receive constant interrupts about it. Disable 7830 * the interrupt after the first. 7831 */ 7832 dd_dev_err(dd, "Lost 8051 heartbeat\n"); 7833 write_csr(dd, DC_DC8051_ERR_EN, 7834 read_csr(dd, DC_DC8051_ERR_EN) & 7835 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK); 7836 7837 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK; 7838 } 7839 if (reg) { 7840 /* report the error, but do not do anything */ 7841 dd_dev_err(dd, "8051 error: %s\n", 7842 dc8051_err_string(buf, sizeof(buf), reg)); 7843 } 7844 7845 if (queue_link_down) { 7846 /* 7847 * if the link is already going down or disabled, do not 7848 * queue another. If there's a link down entry already 7849 * queued, don't queue another one. 7850 */ 7851 if ((ppd->host_link_state & 7852 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) || 7853 ppd->link_enabled == 0) { 7854 dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n", 7855 __func__, ppd->host_link_state, 7856 ppd->link_enabled); 7857 } else { 7858 if (xchg(&ppd->is_link_down_queued, 1) == 1) 7859 dd_dev_info(dd, 7860 "%s: link down request already queued\n", 7861 __func__); 7862 else 7863 queue_work(ppd->link_wq, &ppd->link_down_work); 7864 } 7865 } 7866 } 7867 7868 static const char * const fm_config_txt[] = { 7869 [0] = 7870 "BadHeadDist: Distance violation between two head flits", 7871 [1] = 7872 "BadTailDist: Distance violation between two tail flits", 7873 [2] = 7874 "BadCtrlDist: Distance violation between two credit control flits", 7875 [3] = 7876 "BadCrdAck: Credits return for unsupported VL", 7877 [4] = 7878 "UnsupportedVLMarker: Received VL Marker", 7879 [5] = 7880 "BadPreempt: Exceeded the preemption nesting level", 7881 [6] = 7882 "BadControlFlit: Received unsupported control flit", 7883 /* no 7 */ 7884 [8] = 7885 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL", 7886 }; 7887 7888 static const char * const port_rcv_txt[] = { 7889 [1] = 7890 "BadPktLen: Illegal PktLen", 7891 [2] = 7892 "PktLenTooLong: Packet longer than PktLen", 7893 [3] = 7894 "PktLenTooShort: Packet shorter than PktLen", 7895 [4] = 7896 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)", 7897 [5] = 7898 "BadDLID: Illegal DLID (0, doesn't match HFI)", 7899 [6] = 7900 "BadL2: Illegal L2 opcode", 7901 [7] = 7902 "BadSC: Unsupported SC", 7903 [9] = 7904 "BadRC: Illegal RC", 7905 [11] = 7906 "PreemptError: Preempting with same VL", 7907 [12] = 7908 "PreemptVL15: Preempting a VL15 packet", 7909 }; 7910 7911 #define OPA_LDR_FMCONFIG_OFFSET 16 7912 #define OPA_LDR_PORTRCV_OFFSET 0 7913 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 7914 { 7915 u64 info, hdr0, hdr1; 7916 const char *extra; 7917 char buf[96]; 7918 struct hfi1_pportdata *ppd = dd->pport; 7919 u8 lcl_reason = 0; 7920 int do_bounce = 0; 7921 7922 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) { 7923 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) { 7924 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); 7925 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK; 7926 /* set status bit */ 7927 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK; 7928 } 7929 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK; 7930 } 7931 7932 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) { 7933 struct hfi1_pportdata *ppd = dd->pport; 7934 /* this counter saturates at (2^32) - 1 */ 7935 if (ppd->link_downed < (u32)UINT_MAX) 7936 ppd->link_downed++; 7937 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK; 7938 } 7939 7940 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) { 7941 u8 reason_valid = 1; 7942 7943 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); 7944 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) { 7945 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK; 7946 /* set status bit */ 7947 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK; 7948 } 7949 switch (info) { 7950 case 0: 7951 case 1: 7952 case 2: 7953 case 3: 7954 case 4: 7955 case 5: 7956 case 6: 7957 extra = fm_config_txt[info]; 7958 break; 7959 case 8: 7960 extra = fm_config_txt[info]; 7961 if (ppd->port_error_action & 7962 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) { 7963 do_bounce = 1; 7964 /* 7965 * lcl_reason cannot be derived from info 7966 * for this error 7967 */ 7968 lcl_reason = 7969 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER; 7970 } 7971 break; 7972 default: 7973 reason_valid = 0; 7974 snprintf(buf, sizeof(buf), "reserved%lld", info); 7975 extra = buf; 7976 break; 7977 } 7978 7979 if (reason_valid && !do_bounce) { 7980 do_bounce = ppd->port_error_action & 7981 (1 << (OPA_LDR_FMCONFIG_OFFSET + info)); 7982 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST; 7983 } 7984 7985 /* just report this */ 7986 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n", 7987 extra); 7988 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK; 7989 } 7990 7991 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) { 7992 u8 reason_valid = 1; 7993 7994 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); 7995 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); 7996 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); 7997 if (!(dd->err_info_rcvport.status_and_code & 7998 OPA_EI_STATUS_SMASK)) { 7999 dd->err_info_rcvport.status_and_code = 8000 info & OPA_EI_CODE_SMASK; 8001 /* set status bit */ 8002 dd->err_info_rcvport.status_and_code |= 8003 OPA_EI_STATUS_SMASK; 8004 /* 8005 * save first 2 flits in the packet that caused 8006 * the error 8007 */ 8008 dd->err_info_rcvport.packet_flit1 = hdr0; 8009 dd->err_info_rcvport.packet_flit2 = hdr1; 8010 } 8011 switch (info) { 8012 case 1: 8013 case 2: 8014 case 3: 8015 case 4: 8016 case 5: 8017 case 6: 8018 case 7: 8019 case 9: 8020 case 11: 8021 case 12: 8022 extra = port_rcv_txt[info]; 8023 break; 8024 default: 8025 reason_valid = 0; 8026 snprintf(buf, sizeof(buf), "reserved%lld", info); 8027 extra = buf; 8028 break; 8029 } 8030 8031 if (reason_valid && !do_bounce) { 8032 do_bounce = ppd->port_error_action & 8033 (1 << (OPA_LDR_PORTRCV_OFFSET + info)); 8034 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0; 8035 } 8036 8037 /* just report this */ 8038 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n" 8039 " hdr0 0x%llx, hdr1 0x%llx\n", 8040 extra, hdr0, hdr1); 8041 8042 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK; 8043 } 8044 8045 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) { 8046 /* informative only */ 8047 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n"); 8048 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK; 8049 } 8050 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) { 8051 /* informative only */ 8052 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n"); 8053 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK; 8054 } 8055 8056 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev))) 8057 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK; 8058 8059 /* report any remaining errors */ 8060 if (reg) 8061 dd_dev_info_ratelimited(dd, "DCC Error: %s\n", 8062 dcc_err_string(buf, sizeof(buf), reg)); 8063 8064 if (lcl_reason == 0) 8065 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN; 8066 8067 if (do_bounce) { 8068 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n", 8069 __func__); 8070 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason); 8071 queue_work(ppd->link_wq, &ppd->link_bounce_work); 8072 } 8073 } 8074 8075 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 8076 { 8077 char buf[96]; 8078 8079 dd_dev_info(dd, "LCB Error: %s\n", 8080 lcb_err_string(buf, sizeof(buf), reg)); 8081 } 8082 8083 /* 8084 * CCE block DC interrupt. Source is < 8. 8085 */ 8086 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source) 8087 { 8088 const struct err_reg_info *eri = &dc_errs[source]; 8089 8090 if (eri->handler) { 8091 interrupt_clear_down(dd, 0, eri); 8092 } else if (source == 3 /* dc_lbm_int */) { 8093 /* 8094 * This indicates that a parity error has occurred on the 8095 * address/control lines presented to the LBM. The error 8096 * is a single pulse, there is no associated error flag, 8097 * and it is non-maskable. This is because if a parity 8098 * error occurs on the request the request is dropped. 8099 * This should never occur, but it is nice to know if it 8100 * ever does. 8101 */ 8102 dd_dev_err(dd, "Parity error in DC LBM block\n"); 8103 } else { 8104 dd_dev_err(dd, "Invalid DC interrupt %u\n", source); 8105 } 8106 } 8107 8108 /* 8109 * TX block send credit interrupt. Source is < 160. 8110 */ 8111 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source) 8112 { 8113 sc_group_release_update(dd, source); 8114 } 8115 8116 /* 8117 * TX block SDMA interrupt. Source is < 48. 8118 * 8119 * SDMA interrupts are grouped by type: 8120 * 8121 * 0 - N-1 = SDma 8122 * N - 2N-1 = SDmaProgress 8123 * 2N - 3N-1 = SDmaIdle 8124 */ 8125 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source) 8126 { 8127 /* what interrupt */ 8128 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 8129 /* which engine */ 8130 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 8131 8132 #ifdef CONFIG_SDMA_VERBOSITY 8133 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which, 8134 slashstrip(__FILE__), __LINE__, __func__); 8135 sdma_dumpstate(&dd->per_sdma[which]); 8136 #endif 8137 8138 if (likely(what < 3 && which < dd->num_sdma)) { 8139 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source); 8140 } else { 8141 /* should not happen */ 8142 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source); 8143 } 8144 } 8145 8146 /* 8147 * RX block receive available interrupt. Source is < 160. 8148 */ 8149 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source) 8150 { 8151 struct hfi1_ctxtdata *rcd; 8152 char *err_detail; 8153 8154 if (likely(source < dd->num_rcv_contexts)) { 8155 rcd = hfi1_rcd_get_by_index(dd, source); 8156 if (rcd) { 8157 /* Check for non-user contexts, including vnic */ 8158 if (source < dd->first_dyn_alloc_ctxt || rcd->is_vnic) 8159 rcd->do_interrupt(rcd, 0); 8160 else 8161 handle_user_interrupt(rcd); 8162 8163 hfi1_rcd_put(rcd); 8164 return; /* OK */ 8165 } 8166 /* received an interrupt, but no rcd */ 8167 err_detail = "dataless"; 8168 } else { 8169 /* received an interrupt, but are not using that context */ 8170 err_detail = "out of range"; 8171 } 8172 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n", 8173 err_detail, source); 8174 } 8175 8176 /* 8177 * RX block receive urgent interrupt. Source is < 160. 8178 */ 8179 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source) 8180 { 8181 struct hfi1_ctxtdata *rcd; 8182 char *err_detail; 8183 8184 if (likely(source < dd->num_rcv_contexts)) { 8185 rcd = hfi1_rcd_get_by_index(dd, source); 8186 if (rcd) { 8187 /* only pay attention to user urgent interrupts */ 8188 if (source >= dd->first_dyn_alloc_ctxt && 8189 !rcd->is_vnic) 8190 handle_user_interrupt(rcd); 8191 8192 hfi1_rcd_put(rcd); 8193 return; /* OK */ 8194 } 8195 /* received an interrupt, but no rcd */ 8196 err_detail = "dataless"; 8197 } else { 8198 /* received an interrupt, but are not using that context */ 8199 err_detail = "out of range"; 8200 } 8201 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n", 8202 err_detail, source); 8203 } 8204 8205 /* 8206 * Reserved range interrupt. Should not be called in normal operation. 8207 */ 8208 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source) 8209 { 8210 char name[64]; 8211 8212 dd_dev_err(dd, "unexpected %s interrupt\n", 8213 is_reserved_name(name, sizeof(name), source)); 8214 } 8215 8216 static const struct is_table is_table[] = { 8217 /* 8218 * start end 8219 * name func interrupt func 8220 */ 8221 { IS_GENERAL_ERR_START, IS_GENERAL_ERR_END, 8222 is_misc_err_name, is_misc_err_int }, 8223 { IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END, 8224 is_sdma_eng_err_name, is_sdma_eng_err_int }, 8225 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, 8226 is_sendctxt_err_name, is_sendctxt_err_int }, 8227 { IS_SDMA_START, IS_SDMA_END, 8228 is_sdma_eng_name, is_sdma_eng_int }, 8229 { IS_VARIOUS_START, IS_VARIOUS_END, 8230 is_various_name, is_various_int }, 8231 { IS_DC_START, IS_DC_END, 8232 is_dc_name, is_dc_int }, 8233 { IS_RCVAVAIL_START, IS_RCVAVAIL_END, 8234 is_rcv_avail_name, is_rcv_avail_int }, 8235 { IS_RCVURGENT_START, IS_RCVURGENT_END, 8236 is_rcv_urgent_name, is_rcv_urgent_int }, 8237 { IS_SENDCREDIT_START, IS_SENDCREDIT_END, 8238 is_send_credit_name, is_send_credit_int}, 8239 { IS_RESERVED_START, IS_RESERVED_END, 8240 is_reserved_name, is_reserved_int}, 8241 }; 8242 8243 /* 8244 * Interrupt source interrupt - called when the given source has an interrupt. 8245 * Source is a bit index into an array of 64-bit integers. 8246 */ 8247 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source) 8248 { 8249 const struct is_table *entry; 8250 8251 /* avoids a double compare by walking the table in-order */ 8252 for (entry = &is_table[0]; entry->is_name; entry++) { 8253 if (source < entry->end) { 8254 trace_hfi1_interrupt(dd, entry, source); 8255 entry->is_int(dd, source - entry->start); 8256 return; 8257 } 8258 } 8259 /* fell off the end */ 8260 dd_dev_err(dd, "invalid interrupt source %u\n", source); 8261 } 8262 8263 /* 8264 * General interrupt handler. This is able to correctly handle 8265 * all interrupts in case INTx is used. 8266 */ 8267 static irqreturn_t general_interrupt(int irq, void *data) 8268 { 8269 struct hfi1_devdata *dd = data; 8270 u64 regs[CCE_NUM_INT_CSRS]; 8271 u32 bit; 8272 int i; 8273 irqreturn_t handled = IRQ_NONE; 8274 8275 this_cpu_inc(*dd->int_counter); 8276 8277 /* phase 1: scan and clear all handled interrupts */ 8278 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 8279 if (dd->gi_mask[i] == 0) { 8280 regs[i] = 0; /* used later */ 8281 continue; 8282 } 8283 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & 8284 dd->gi_mask[i]; 8285 /* only clear if anything is set */ 8286 if (regs[i]) 8287 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); 8288 } 8289 8290 /* phase 2: call the appropriate handler */ 8291 for_each_set_bit(bit, (unsigned long *)®s[0], 8292 CCE_NUM_INT_CSRS * 64) { 8293 is_interrupt(dd, bit); 8294 handled = IRQ_HANDLED; 8295 } 8296 8297 return handled; 8298 } 8299 8300 static irqreturn_t sdma_interrupt(int irq, void *data) 8301 { 8302 struct sdma_engine *sde = data; 8303 struct hfi1_devdata *dd = sde->dd; 8304 u64 status; 8305 8306 #ifdef CONFIG_SDMA_VERBOSITY 8307 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 8308 slashstrip(__FILE__), __LINE__, __func__); 8309 sdma_dumpstate(sde); 8310 #endif 8311 8312 this_cpu_inc(*dd->int_counter); 8313 8314 /* This read_csr is really bad in the hot path */ 8315 status = read_csr(dd, 8316 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64))) 8317 & sde->imask; 8318 if (likely(status)) { 8319 /* clear the interrupt(s) */ 8320 write_csr(dd, 8321 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)), 8322 status); 8323 8324 /* handle the interrupt(s) */ 8325 sdma_engine_interrupt(sde, status); 8326 } else { 8327 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n", 8328 sde->this_idx); 8329 } 8330 return IRQ_HANDLED; 8331 } 8332 8333 /* 8334 * Clear the receive interrupt. Use a read of the interrupt clear CSR 8335 * to insure that the write completed. This does NOT guarantee that 8336 * queued DMA writes to memory from the chip are pushed. 8337 */ 8338 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd) 8339 { 8340 struct hfi1_devdata *dd = rcd->dd; 8341 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg); 8342 8343 mmiowb(); /* make sure everything before is written */ 8344 write_csr(dd, addr, rcd->imask); 8345 /* force the above write on the chip and get a value back */ 8346 (void)read_csr(dd, addr); 8347 } 8348 8349 /* force the receive interrupt */ 8350 void force_recv_intr(struct hfi1_ctxtdata *rcd) 8351 { 8352 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); 8353 } 8354 8355 /* 8356 * Return non-zero if a packet is present. 8357 * 8358 * This routine is called when rechecking for packets after the RcvAvail 8359 * interrupt has been cleared down. First, do a quick check of memory for 8360 * a packet present. If not found, use an expensive CSR read of the context 8361 * tail to determine the actual tail. The CSR read is necessary because there 8362 * is no method to push pending DMAs to memory other than an interrupt and we 8363 * are trying to determine if we need to force an interrupt. 8364 */ 8365 static inline int check_packet_present(struct hfi1_ctxtdata *rcd) 8366 { 8367 u32 tail; 8368 int present; 8369 8370 if (!rcd->rcvhdrtail_kvaddr) 8371 present = (rcd->seq_cnt == 8372 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd)))); 8373 else /* is RDMA rtail */ 8374 present = (rcd->head != get_rcvhdrtail(rcd)); 8375 8376 if (present) 8377 return 1; 8378 8379 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */ 8380 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 8381 return rcd->head != tail; 8382 } 8383 8384 /* 8385 * Receive packet IRQ handler. This routine expects to be on its own IRQ. 8386 * This routine will try to handle packets immediately (latency), but if 8387 * it finds too many, it will invoke the thread handler (bandwitdh). The 8388 * chip receive interrupt is *not* cleared down until this or the thread (if 8389 * invoked) is finished. The intent is to avoid extra interrupts while we 8390 * are processing packets anyway. 8391 */ 8392 static irqreturn_t receive_context_interrupt(int irq, void *data) 8393 { 8394 struct hfi1_ctxtdata *rcd = data; 8395 struct hfi1_devdata *dd = rcd->dd; 8396 int disposition; 8397 int present; 8398 8399 trace_hfi1_receive_interrupt(dd, rcd); 8400 this_cpu_inc(*dd->int_counter); 8401 aspm_ctx_disable(rcd); 8402 8403 /* receive interrupt remains blocked while processing packets */ 8404 disposition = rcd->do_interrupt(rcd, 0); 8405 8406 /* 8407 * Too many packets were seen while processing packets in this 8408 * IRQ handler. Invoke the handler thread. The receive interrupt 8409 * remains blocked. 8410 */ 8411 if (disposition == RCV_PKT_LIMIT) 8412 return IRQ_WAKE_THREAD; 8413 8414 /* 8415 * The packet processor detected no more packets. Clear the receive 8416 * interrupt and recheck for a packet packet that may have arrived 8417 * after the previous check and interrupt clear. If a packet arrived, 8418 * force another interrupt. 8419 */ 8420 clear_recv_intr(rcd); 8421 present = check_packet_present(rcd); 8422 if (present) 8423 force_recv_intr(rcd); 8424 8425 return IRQ_HANDLED; 8426 } 8427 8428 /* 8429 * Receive packet thread handler. This expects to be invoked with the 8430 * receive interrupt still blocked. 8431 */ 8432 static irqreturn_t receive_context_thread(int irq, void *data) 8433 { 8434 struct hfi1_ctxtdata *rcd = data; 8435 int present; 8436 8437 /* receive interrupt is still blocked from the IRQ handler */ 8438 (void)rcd->do_interrupt(rcd, 1); 8439 8440 /* 8441 * The packet processor will only return if it detected no more 8442 * packets. Hold IRQs here so we can safely clear the interrupt and 8443 * recheck for a packet that may have arrived after the previous 8444 * check and the interrupt clear. If a packet arrived, force another 8445 * interrupt. 8446 */ 8447 local_irq_disable(); 8448 clear_recv_intr(rcd); 8449 present = check_packet_present(rcd); 8450 if (present) 8451 force_recv_intr(rcd); 8452 local_irq_enable(); 8453 8454 return IRQ_HANDLED; 8455 } 8456 8457 /* ========================================================================= */ 8458 8459 u32 read_physical_state(struct hfi1_devdata *dd) 8460 { 8461 u64 reg; 8462 8463 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 8464 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT) 8465 & DC_DC8051_STS_CUR_STATE_PORT_MASK; 8466 } 8467 8468 u32 read_logical_state(struct hfi1_devdata *dd) 8469 { 8470 u64 reg; 8471 8472 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8473 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT) 8474 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK; 8475 } 8476 8477 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate) 8478 { 8479 u64 reg; 8480 8481 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8482 /* clear current state, set new state */ 8483 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK; 8484 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT; 8485 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); 8486 } 8487 8488 /* 8489 * Use the 8051 to read a LCB CSR. 8490 */ 8491 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data) 8492 { 8493 u32 regno; 8494 int ret; 8495 8496 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 8497 if (acquire_lcb_access(dd, 0) == 0) { 8498 *data = read_csr(dd, addr); 8499 release_lcb_access(dd, 0); 8500 return 0; 8501 } 8502 return -EBUSY; 8503 } 8504 8505 /* register is an index of LCB registers: (offset - base) / 8 */ 8506 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8507 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data); 8508 if (ret != HCMD_SUCCESS) 8509 return -EBUSY; 8510 return 0; 8511 } 8512 8513 /* 8514 * Provide a cache for some of the LCB registers in case the LCB is 8515 * unavailable. 8516 * (The LCB is unavailable in certain link states, for example.) 8517 */ 8518 struct lcb_datum { 8519 u32 off; 8520 u64 val; 8521 }; 8522 8523 static struct lcb_datum lcb_cache[] = { 8524 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0}, 8525 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 }, 8526 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 }, 8527 }; 8528 8529 static void update_lcb_cache(struct hfi1_devdata *dd) 8530 { 8531 int i; 8532 int ret; 8533 u64 val; 8534 8535 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8536 ret = read_lcb_csr(dd, lcb_cache[i].off, &val); 8537 8538 /* Update if we get good data */ 8539 if (likely(ret != -EBUSY)) 8540 lcb_cache[i].val = val; 8541 } 8542 } 8543 8544 static int read_lcb_cache(u32 off, u64 *val) 8545 { 8546 int i; 8547 8548 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8549 if (lcb_cache[i].off == off) { 8550 *val = lcb_cache[i].val; 8551 return 0; 8552 } 8553 } 8554 8555 pr_warn("%s bad offset 0x%x\n", __func__, off); 8556 return -1; 8557 } 8558 8559 /* 8560 * Read an LCB CSR. Access may not be in host control, so check. 8561 * Return 0 on success, -EBUSY on failure. 8562 */ 8563 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data) 8564 { 8565 struct hfi1_pportdata *ppd = dd->pport; 8566 8567 /* if up, go through the 8051 for the value */ 8568 if (ppd->host_link_state & HLS_UP) 8569 return read_lcb_via_8051(dd, addr, data); 8570 /* if going up or down, check the cache, otherwise, no access */ 8571 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) { 8572 if (read_lcb_cache(addr, data)) 8573 return -EBUSY; 8574 return 0; 8575 } 8576 8577 /* otherwise, host has access */ 8578 *data = read_csr(dd, addr); 8579 return 0; 8580 } 8581 8582 /* 8583 * Use the 8051 to write a LCB CSR. 8584 */ 8585 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data) 8586 { 8587 u32 regno; 8588 int ret; 8589 8590 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || 8591 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) { 8592 if (acquire_lcb_access(dd, 0) == 0) { 8593 write_csr(dd, addr, data); 8594 release_lcb_access(dd, 0); 8595 return 0; 8596 } 8597 return -EBUSY; 8598 } 8599 8600 /* register is an index of LCB registers: (offset - base) / 8 */ 8601 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8602 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data); 8603 if (ret != HCMD_SUCCESS) 8604 return -EBUSY; 8605 return 0; 8606 } 8607 8608 /* 8609 * Write an LCB CSR. Access may not be in host control, so check. 8610 * Return 0 on success, -EBUSY on failure. 8611 */ 8612 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data) 8613 { 8614 struct hfi1_pportdata *ppd = dd->pport; 8615 8616 /* if up, go through the 8051 for the value */ 8617 if (ppd->host_link_state & HLS_UP) 8618 return write_lcb_via_8051(dd, addr, data); 8619 /* if going up or down, no access */ 8620 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) 8621 return -EBUSY; 8622 /* otherwise, host has access */ 8623 write_csr(dd, addr, data); 8624 return 0; 8625 } 8626 8627 /* 8628 * Returns: 8629 * < 0 = Linux error, not able to get access 8630 * > 0 = 8051 command RETURN_CODE 8631 */ 8632 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 8633 u64 *out_data) 8634 { 8635 u64 reg, completed; 8636 int return_code; 8637 unsigned long timeout; 8638 8639 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data); 8640 8641 mutex_lock(&dd->dc8051_lock); 8642 8643 /* We can't send any commands to the 8051 if it's in reset */ 8644 if (dd->dc_shutdown) { 8645 return_code = -ENODEV; 8646 goto fail; 8647 } 8648 8649 /* 8650 * If an 8051 host command timed out previously, then the 8051 is 8651 * stuck. 8652 * 8653 * On first timeout, attempt to reset and restart the entire DC 8654 * block (including 8051). (Is this too big of a hammer?) 8655 * 8656 * If the 8051 times out a second time, the reset did not bring it 8657 * back to healthy life. In that case, fail any subsequent commands. 8658 */ 8659 if (dd->dc8051_timed_out) { 8660 if (dd->dc8051_timed_out > 1) { 8661 dd_dev_err(dd, 8662 "Previous 8051 host command timed out, skipping command %u\n", 8663 type); 8664 return_code = -ENXIO; 8665 goto fail; 8666 } 8667 _dc_shutdown(dd); 8668 _dc_start(dd); 8669 } 8670 8671 /* 8672 * If there is no timeout, then the 8051 command interface is 8673 * waiting for a command. 8674 */ 8675 8676 /* 8677 * When writing a LCB CSR, out_data contains the full value to 8678 * to be written, while in_data contains the relative LCB 8679 * address in 7:0. Do the work here, rather than the caller, 8680 * of distrubting the write data to where it needs to go: 8681 * 8682 * Write data 8683 * 39:00 -> in_data[47:8] 8684 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE 8685 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA 8686 */ 8687 if (type == HCMD_WRITE_LCB_CSR) { 8688 in_data |= ((*out_data) & 0xffffffffffull) << 8; 8689 /* must preserve COMPLETED - it is tied to hardware */ 8690 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); 8691 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK; 8692 reg |= ((((*out_data) >> 40) & 0xff) << 8693 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT) 8694 | ((((*out_data) >> 48) & 0xffff) << 8695 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 8696 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); 8697 } 8698 8699 /* 8700 * Do two writes: the first to stabilize the type and req_data, the 8701 * second to activate. 8702 */ 8703 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK) 8704 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8705 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK) 8706 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT; 8707 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8708 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK; 8709 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8710 8711 /* wait for completion, alternate: interrupt */ 8712 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT); 8713 while (1) { 8714 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); 8715 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK; 8716 if (completed) 8717 break; 8718 if (time_after(jiffies, timeout)) { 8719 dd->dc8051_timed_out++; 8720 dd_dev_err(dd, "8051 host command %u timeout\n", type); 8721 if (out_data) 8722 *out_data = 0; 8723 return_code = -ETIMEDOUT; 8724 goto fail; 8725 } 8726 udelay(2); 8727 } 8728 8729 if (out_data) { 8730 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT) 8731 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK; 8732 if (type == HCMD_READ_LCB_CSR) { 8733 /* top 16 bits are in a different register */ 8734 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) 8735 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK) 8736 << (48 8737 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT); 8738 } 8739 } 8740 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT) 8741 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK; 8742 dd->dc8051_timed_out = 0; 8743 /* 8744 * Clear command for next user. 8745 */ 8746 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); 8747 8748 fail: 8749 mutex_unlock(&dd->dc8051_lock); 8750 return return_code; 8751 } 8752 8753 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state) 8754 { 8755 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL); 8756 } 8757 8758 int load_8051_config(struct hfi1_devdata *dd, u8 field_id, 8759 u8 lane_id, u32 config_data) 8760 { 8761 u64 data; 8762 int ret; 8763 8764 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT 8765 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT 8766 | (u64)config_data << LOAD_DATA_DATA_SHIFT; 8767 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL); 8768 if (ret != HCMD_SUCCESS) { 8769 dd_dev_err(dd, 8770 "load 8051 config: field id %d, lane %d, err %d\n", 8771 (int)field_id, (int)lane_id, ret); 8772 } 8773 return ret; 8774 } 8775 8776 /* 8777 * Read the 8051 firmware "registers". Use the RAM directly. Always 8778 * set the result, even on error. 8779 * Return 0 on success, -errno on failure 8780 */ 8781 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id, 8782 u32 *result) 8783 { 8784 u64 big_data; 8785 u32 addr; 8786 int ret; 8787 8788 /* address start depends on the lane_id */ 8789 if (lane_id < 4) 8790 addr = (4 * NUM_GENERAL_FIELDS) 8791 + (lane_id * 4 * NUM_LANE_FIELDS); 8792 else 8793 addr = 0; 8794 addr += field_id * 4; 8795 8796 /* read is in 8-byte chunks, hardware will truncate the address down */ 8797 ret = read_8051_data(dd, addr, 8, &big_data); 8798 8799 if (ret == 0) { 8800 /* extract the 4 bytes we want */ 8801 if (addr & 0x4) 8802 *result = (u32)(big_data >> 32); 8803 else 8804 *result = (u32)big_data; 8805 } else { 8806 *result = 0; 8807 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n", 8808 __func__, lane_id, field_id); 8809 } 8810 8811 return ret; 8812 } 8813 8814 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management, 8815 u8 continuous) 8816 { 8817 u32 frame; 8818 8819 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 8820 | power_management << POWER_MANAGEMENT_SHIFT; 8821 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY, 8822 GENERAL_CONFIG, frame); 8823 } 8824 8825 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu, 8826 u16 vl15buf, u8 crc_sizes) 8827 { 8828 u32 frame; 8829 8830 frame = (u32)vau << VAU_SHIFT 8831 | (u32)z << Z_SHIFT 8832 | (u32)vcu << VCU_SHIFT 8833 | (u32)vl15buf << VL15BUF_SHIFT 8834 | (u32)crc_sizes << CRC_SIZES_SHIFT; 8835 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC, 8836 GENERAL_CONFIG, frame); 8837 } 8838 8839 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 8840 u8 *flag_bits, u16 *link_widths) 8841 { 8842 u32 frame; 8843 8844 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8845 &frame); 8846 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK; 8847 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK; 8848 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8849 } 8850 8851 static int write_vc_local_link_mode(struct hfi1_devdata *dd, 8852 u8 misc_bits, 8853 u8 flag_bits, 8854 u16 link_widths) 8855 { 8856 u32 frame; 8857 8858 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT 8859 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT 8860 | (u32)link_widths << LINK_WIDTH_SHIFT; 8861 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8862 frame); 8863 } 8864 8865 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id, 8866 u8 device_rev) 8867 { 8868 u32 frame; 8869 8870 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT) 8871 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT); 8872 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame); 8873 } 8874 8875 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 8876 u8 *device_rev) 8877 { 8878 u32 frame; 8879 8880 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame); 8881 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK; 8882 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT) 8883 & REMOTE_DEVICE_REV_MASK; 8884 } 8885 8886 int write_host_interface_version(struct hfi1_devdata *dd, u8 version) 8887 { 8888 u32 frame; 8889 u32 mask; 8890 8891 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); 8892 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame); 8893 /* Clear, then set field */ 8894 frame &= ~mask; 8895 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT); 8896 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, 8897 frame); 8898 } 8899 8900 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 8901 u8 *ver_patch) 8902 { 8903 u32 frame; 8904 8905 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame); 8906 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) & 8907 STS_FM_VERSION_MAJOR_MASK; 8908 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) & 8909 STS_FM_VERSION_MINOR_MASK; 8910 8911 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame); 8912 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) & 8913 STS_FM_VERSION_PATCH_MASK; 8914 } 8915 8916 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 8917 u8 *continuous) 8918 { 8919 u32 frame; 8920 8921 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame); 8922 *power_management = (frame >> POWER_MANAGEMENT_SHIFT) 8923 & POWER_MANAGEMENT_MASK; 8924 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT) 8925 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK; 8926 } 8927 8928 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 8929 u8 *vcu, u16 *vl15buf, u8 *crc_sizes) 8930 { 8931 u32 frame; 8932 8933 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame); 8934 *vau = (frame >> VAU_SHIFT) & VAU_MASK; 8935 *z = (frame >> Z_SHIFT) & Z_MASK; 8936 *vcu = (frame >> VCU_SHIFT) & VCU_MASK; 8937 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK; 8938 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK; 8939 } 8940 8941 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 8942 u8 *remote_tx_rate, 8943 u16 *link_widths) 8944 { 8945 u32 frame; 8946 8947 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG, 8948 &frame); 8949 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT) 8950 & REMOTE_TX_RATE_MASK; 8951 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8952 } 8953 8954 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx) 8955 { 8956 u32 frame; 8957 8958 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame); 8959 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK; 8960 } 8961 8962 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls) 8963 { 8964 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls); 8965 } 8966 8967 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs) 8968 { 8969 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs); 8970 } 8971 8972 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality) 8973 { 8974 u32 frame; 8975 int ret; 8976 8977 *link_quality = 0; 8978 if (dd->pport->host_link_state & HLS_UP) { 8979 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, 8980 &frame); 8981 if (ret == 0) 8982 *link_quality = (frame >> LINK_QUALITY_SHIFT) 8983 & LINK_QUALITY_MASK; 8984 } 8985 } 8986 8987 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc) 8988 { 8989 u32 frame; 8990 8991 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame); 8992 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK; 8993 } 8994 8995 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr) 8996 { 8997 u32 frame; 8998 8999 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame); 9000 *ldr = (frame & 0xff); 9001 } 9002 9003 static int read_tx_settings(struct hfi1_devdata *dd, 9004 u8 *enable_lane_tx, 9005 u8 *tx_polarity_inversion, 9006 u8 *rx_polarity_inversion, 9007 u8 *max_rate) 9008 { 9009 u32 frame; 9010 int ret; 9011 9012 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame); 9013 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT) 9014 & ENABLE_LANE_TX_MASK; 9015 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT) 9016 & TX_POLARITY_INVERSION_MASK; 9017 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT) 9018 & RX_POLARITY_INVERSION_MASK; 9019 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK; 9020 return ret; 9021 } 9022 9023 static int write_tx_settings(struct hfi1_devdata *dd, 9024 u8 enable_lane_tx, 9025 u8 tx_polarity_inversion, 9026 u8 rx_polarity_inversion, 9027 u8 max_rate) 9028 { 9029 u32 frame; 9030 9031 /* no need to mask, all variable sizes match field widths */ 9032 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT 9033 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT 9034 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT 9035 | max_rate << MAX_RATE_SHIFT; 9036 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame); 9037 } 9038 9039 /* 9040 * Read an idle LCB message. 9041 * 9042 * Returns 0 on success, -EINVAL on error 9043 */ 9044 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out) 9045 { 9046 int ret; 9047 9048 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out); 9049 if (ret != HCMD_SUCCESS) { 9050 dd_dev_err(dd, "read idle message: type %d, err %d\n", 9051 (u32)type, ret); 9052 return -EINVAL; 9053 } 9054 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out); 9055 /* return only the payload as we already know the type */ 9056 *data_out >>= IDLE_PAYLOAD_SHIFT; 9057 return 0; 9058 } 9059 9060 /* 9061 * Read an idle SMA message. To be done in response to a notification from 9062 * the 8051. 9063 * 9064 * Returns 0 on success, -EINVAL on error 9065 */ 9066 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data) 9067 { 9068 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT, 9069 data); 9070 } 9071 9072 /* 9073 * Send an idle LCB message. 9074 * 9075 * Returns 0 on success, -EINVAL on error 9076 */ 9077 static int send_idle_message(struct hfi1_devdata *dd, u64 data) 9078 { 9079 int ret; 9080 9081 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data); 9082 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL); 9083 if (ret != HCMD_SUCCESS) { 9084 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n", 9085 data, ret); 9086 return -EINVAL; 9087 } 9088 return 0; 9089 } 9090 9091 /* 9092 * Send an idle SMA message. 9093 * 9094 * Returns 0 on success, -EINVAL on error 9095 */ 9096 int send_idle_sma(struct hfi1_devdata *dd, u64 message) 9097 { 9098 u64 data; 9099 9100 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) | 9101 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT); 9102 return send_idle_message(dd, data); 9103 } 9104 9105 /* 9106 * Initialize the LCB then do a quick link up. This may or may not be 9107 * in loopback. 9108 * 9109 * return 0 on success, -errno on error 9110 */ 9111 static int do_quick_linkup(struct hfi1_devdata *dd) 9112 { 9113 int ret; 9114 9115 lcb_shutdown(dd, 0); 9116 9117 if (loopback) { 9118 /* LCB_CFG_LOOPBACK.VAL = 2 */ 9119 /* LCB_CFG_LANE_WIDTH.VAL = 0 */ 9120 write_csr(dd, DC_LCB_CFG_LOOPBACK, 9121 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT); 9122 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 9123 } 9124 9125 /* start the LCBs */ 9126 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */ 9127 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 9128 9129 /* simulator only loopback steps */ 9130 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 9131 /* LCB_CFG_RUN.EN = 1 */ 9132 write_csr(dd, DC_LCB_CFG_RUN, 9133 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 9134 9135 ret = wait_link_transfer_active(dd, 10); 9136 if (ret) 9137 return ret; 9138 9139 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 9140 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT); 9141 } 9142 9143 if (!loopback) { 9144 /* 9145 * When doing quick linkup and not in loopback, both 9146 * sides must be done with LCB set-up before either 9147 * starts the quick linkup. Put a delay here so that 9148 * both sides can be started and have a chance to be 9149 * done with LCB set up before resuming. 9150 */ 9151 dd_dev_err(dd, 9152 "Pausing for peer to be finished with LCB set up\n"); 9153 msleep(5000); 9154 dd_dev_err(dd, "Continuing with quick linkup\n"); 9155 } 9156 9157 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 9158 set_8051_lcb_access(dd); 9159 9160 /* 9161 * State "quick" LinkUp request sets the physical link state to 9162 * LinkUp without a verify capability sequence. 9163 * This state is in simulator v37 and later. 9164 */ 9165 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP); 9166 if (ret != HCMD_SUCCESS) { 9167 dd_dev_err(dd, 9168 "%s: set physical link state to quick LinkUp failed with return %d\n", 9169 __func__, ret); 9170 9171 set_host_lcb_access(dd); 9172 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 9173 9174 if (ret >= 0) 9175 ret = -EINVAL; 9176 return ret; 9177 } 9178 9179 return 0; /* success */ 9180 } 9181 9182 /* 9183 * Do all special steps to set up loopback. 9184 */ 9185 static int init_loopback(struct hfi1_devdata *dd) 9186 { 9187 dd_dev_info(dd, "Entering loopback mode\n"); 9188 9189 /* all loopbacks should disable self GUID check */ 9190 write_csr(dd, DC_DC8051_CFG_MODE, 9191 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); 9192 9193 /* 9194 * The simulator has only one loopback option - LCB. Switch 9195 * to that option, which includes quick link up. 9196 * 9197 * Accept all valid loopback values. 9198 */ 9199 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) && 9200 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB || 9201 loopback == LOOPBACK_CABLE)) { 9202 loopback = LOOPBACK_LCB; 9203 quick_linkup = 1; 9204 return 0; 9205 } 9206 9207 /* 9208 * SerDes loopback init sequence is handled in set_local_link_attributes 9209 */ 9210 if (loopback == LOOPBACK_SERDES) 9211 return 0; 9212 9213 /* LCB loopback - handled at poll time */ 9214 if (loopback == LOOPBACK_LCB) { 9215 quick_linkup = 1; /* LCB is always quick linkup */ 9216 9217 /* not supported in emulation due to emulation RTL changes */ 9218 if (dd->icode == ICODE_FPGA_EMULATION) { 9219 dd_dev_err(dd, 9220 "LCB loopback not supported in emulation\n"); 9221 return -EINVAL; 9222 } 9223 return 0; 9224 } 9225 9226 /* external cable loopback requires no extra steps */ 9227 if (loopback == LOOPBACK_CABLE) 9228 return 0; 9229 9230 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback); 9231 return -EINVAL; 9232 } 9233 9234 /* 9235 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits 9236 * used in the Verify Capability link width attribute. 9237 */ 9238 static u16 opa_to_vc_link_widths(u16 opa_widths) 9239 { 9240 int i; 9241 u16 result = 0; 9242 9243 static const struct link_bits { 9244 u16 from; 9245 u16 to; 9246 } opa_link_xlate[] = { 9247 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) }, 9248 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) }, 9249 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) }, 9250 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) }, 9251 }; 9252 9253 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) { 9254 if (opa_widths & opa_link_xlate[i].from) 9255 result |= opa_link_xlate[i].to; 9256 } 9257 return result; 9258 } 9259 9260 /* 9261 * Set link attributes before moving to polling. 9262 */ 9263 static int set_local_link_attributes(struct hfi1_pportdata *ppd) 9264 { 9265 struct hfi1_devdata *dd = ppd->dd; 9266 u8 enable_lane_tx; 9267 u8 tx_polarity_inversion; 9268 u8 rx_polarity_inversion; 9269 int ret; 9270 u32 misc_bits = 0; 9271 /* reset our fabric serdes to clear any lingering problems */ 9272 fabric_serdes_reset(dd); 9273 9274 /* set the local tx rate - need to read-modify-write */ 9275 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 9276 &rx_polarity_inversion, &ppd->local_tx_rate); 9277 if (ret) 9278 goto set_local_link_attributes_fail; 9279 9280 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 9281 /* set the tx rate to the fastest enabled */ 9282 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9283 ppd->local_tx_rate = 1; 9284 else 9285 ppd->local_tx_rate = 0; 9286 } else { 9287 /* set the tx rate to all enabled */ 9288 ppd->local_tx_rate = 0; 9289 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9290 ppd->local_tx_rate |= 2; 9291 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G) 9292 ppd->local_tx_rate |= 1; 9293 } 9294 9295 enable_lane_tx = 0xF; /* enable all four lanes */ 9296 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion, 9297 rx_polarity_inversion, ppd->local_tx_rate); 9298 if (ret != HCMD_SUCCESS) 9299 goto set_local_link_attributes_fail; 9300 9301 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION); 9302 if (ret != HCMD_SUCCESS) { 9303 dd_dev_err(dd, 9304 "Failed to set host interface version, return 0x%x\n", 9305 ret); 9306 goto set_local_link_attributes_fail; 9307 } 9308 9309 /* 9310 * DC supports continuous updates. 9311 */ 9312 ret = write_vc_local_phy(dd, 9313 0 /* no power management */, 9314 1 /* continuous updates */); 9315 if (ret != HCMD_SUCCESS) 9316 goto set_local_link_attributes_fail; 9317 9318 /* z=1 in the next call: AU of 0 is not supported by the hardware */ 9319 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init, 9320 ppd->port_crc_mode_enabled); 9321 if (ret != HCMD_SUCCESS) 9322 goto set_local_link_attributes_fail; 9323 9324 /* 9325 * SerDes loopback init sequence requires 9326 * setting bit 0 of MISC_CONFIG_BITS 9327 */ 9328 if (loopback == LOOPBACK_SERDES) 9329 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT; 9330 9331 /* 9332 * An external device configuration request is used to reset the LCB 9333 * to retry to obtain operational lanes when the first attempt is 9334 * unsuccesful. 9335 */ 9336 if (dd->dc8051_ver >= dc8051_ver(1, 25, 0)) 9337 misc_bits |= 1 << EXT_CFG_LCB_RESET_SUPPORTED_SHIFT; 9338 9339 ret = write_vc_local_link_mode(dd, misc_bits, 0, 9340 opa_to_vc_link_widths( 9341 ppd->link_width_enabled)); 9342 if (ret != HCMD_SUCCESS) 9343 goto set_local_link_attributes_fail; 9344 9345 /* let peer know who we are */ 9346 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev); 9347 if (ret == HCMD_SUCCESS) 9348 return 0; 9349 9350 set_local_link_attributes_fail: 9351 dd_dev_err(dd, 9352 "Failed to set local link attributes, return 0x%x\n", 9353 ret); 9354 return ret; 9355 } 9356 9357 /* 9358 * Call this to start the link. 9359 * Do not do anything if the link is disabled. 9360 * Returns 0 if link is disabled, moved to polling, or the driver is not ready. 9361 */ 9362 int start_link(struct hfi1_pportdata *ppd) 9363 { 9364 /* 9365 * Tune the SerDes to a ballpark setting for optimal signal and bit 9366 * error rate. Needs to be done before starting the link. 9367 */ 9368 tune_serdes(ppd); 9369 9370 if (!ppd->driver_link_ready) { 9371 dd_dev_info(ppd->dd, 9372 "%s: stopping link start because driver is not ready\n", 9373 __func__); 9374 return 0; 9375 } 9376 9377 /* 9378 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the 9379 * pkey table can be configured properly if the HFI unit is connected 9380 * to switch port with MgmtAllowed=NO 9381 */ 9382 clear_full_mgmt_pkey(ppd); 9383 9384 return set_link_state(ppd, HLS_DN_POLL); 9385 } 9386 9387 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd) 9388 { 9389 struct hfi1_devdata *dd = ppd->dd; 9390 u64 mask; 9391 unsigned long timeout; 9392 9393 /* 9394 * Some QSFP cables have a quirk that asserts the IntN line as a side 9395 * effect of power up on plug-in. We ignore this false positive 9396 * interrupt until the module has finished powering up by waiting for 9397 * a minimum timeout of the module inrush initialization time of 9398 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the 9399 * module have stabilized. 9400 */ 9401 msleep(500); 9402 9403 /* 9404 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1) 9405 */ 9406 timeout = jiffies + msecs_to_jiffies(2000); 9407 while (1) { 9408 mask = read_csr(dd, dd->hfi1_id ? 9409 ASIC_QSFP2_IN : ASIC_QSFP1_IN); 9410 if (!(mask & QSFP_HFI0_INT_N)) 9411 break; 9412 if (time_after(jiffies, timeout)) { 9413 dd_dev_info(dd, "%s: No IntN detected, reset complete\n", 9414 __func__); 9415 break; 9416 } 9417 udelay(2); 9418 } 9419 } 9420 9421 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable) 9422 { 9423 struct hfi1_devdata *dd = ppd->dd; 9424 u64 mask; 9425 9426 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); 9427 if (enable) { 9428 /* 9429 * Clear the status register to avoid an immediate interrupt 9430 * when we re-enable the IntN pin 9431 */ 9432 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9433 QSFP_HFI0_INT_N); 9434 mask |= (u64)QSFP_HFI0_INT_N; 9435 } else { 9436 mask &= ~(u64)QSFP_HFI0_INT_N; 9437 } 9438 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); 9439 } 9440 9441 int reset_qsfp(struct hfi1_pportdata *ppd) 9442 { 9443 struct hfi1_devdata *dd = ppd->dd; 9444 u64 mask, qsfp_mask; 9445 9446 /* Disable INT_N from triggering QSFP interrupts */ 9447 set_qsfp_int_n(ppd, 0); 9448 9449 /* Reset the QSFP */ 9450 mask = (u64)QSFP_HFI0_RESET_N; 9451 9452 qsfp_mask = read_csr(dd, 9453 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT); 9454 qsfp_mask &= ~mask; 9455 write_csr(dd, 9456 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9457 9458 udelay(10); 9459 9460 qsfp_mask |= mask; 9461 write_csr(dd, 9462 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9463 9464 wait_for_qsfp_init(ppd); 9465 9466 /* 9467 * Allow INT_N to trigger the QSFP interrupt to watch 9468 * for alarms and warnings 9469 */ 9470 set_qsfp_int_n(ppd, 1); 9471 9472 /* 9473 * After the reset, AOC transmitters are enabled by default. They need 9474 * to be turned off to complete the QSFP setup before they can be 9475 * enabled again. 9476 */ 9477 return set_qsfp_tx(ppd, 0); 9478 } 9479 9480 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd, 9481 u8 *qsfp_interrupt_status) 9482 { 9483 struct hfi1_devdata *dd = ppd->dd; 9484 9485 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) || 9486 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING)) 9487 dd_dev_err(dd, "%s: QSFP cable temperature too high\n", 9488 __func__); 9489 9490 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) || 9491 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING)) 9492 dd_dev_err(dd, "%s: QSFP cable temperature too low\n", 9493 __func__); 9494 9495 /* 9496 * The remaining alarms/warnings don't matter if the link is down. 9497 */ 9498 if (ppd->host_link_state & HLS_DOWN) 9499 return 0; 9500 9501 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) || 9502 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING)) 9503 dd_dev_err(dd, "%s: QSFP supply voltage too high\n", 9504 __func__); 9505 9506 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) || 9507 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING)) 9508 dd_dev_err(dd, "%s: QSFP supply voltage too low\n", 9509 __func__); 9510 9511 /* Byte 2 is vendor specific */ 9512 9513 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) || 9514 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING)) 9515 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n", 9516 __func__); 9517 9518 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) || 9519 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING)) 9520 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n", 9521 __func__); 9522 9523 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) || 9524 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING)) 9525 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n", 9526 __func__); 9527 9528 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) || 9529 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING)) 9530 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n", 9531 __func__); 9532 9533 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) || 9534 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING)) 9535 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n", 9536 __func__); 9537 9538 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) || 9539 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING)) 9540 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n", 9541 __func__); 9542 9543 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) || 9544 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING)) 9545 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n", 9546 __func__); 9547 9548 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) || 9549 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING)) 9550 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n", 9551 __func__); 9552 9553 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) || 9554 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING)) 9555 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n", 9556 __func__); 9557 9558 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) || 9559 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING)) 9560 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n", 9561 __func__); 9562 9563 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) || 9564 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING)) 9565 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n", 9566 __func__); 9567 9568 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) || 9569 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING)) 9570 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n", 9571 __func__); 9572 9573 /* Bytes 9-10 and 11-12 are reserved */ 9574 /* Bytes 13-15 are vendor specific */ 9575 9576 return 0; 9577 } 9578 9579 /* This routine will only be scheduled if the QSFP module present is asserted */ 9580 void qsfp_event(struct work_struct *work) 9581 { 9582 struct qsfp_data *qd; 9583 struct hfi1_pportdata *ppd; 9584 struct hfi1_devdata *dd; 9585 9586 qd = container_of(work, struct qsfp_data, qsfp_work); 9587 ppd = qd->ppd; 9588 dd = ppd->dd; 9589 9590 /* Sanity check */ 9591 if (!qsfp_mod_present(ppd)) 9592 return; 9593 9594 if (ppd->host_link_state == HLS_DN_DISABLE) { 9595 dd_dev_info(ppd->dd, 9596 "%s: stopping link start because link is disabled\n", 9597 __func__); 9598 return; 9599 } 9600 9601 /* 9602 * Turn DC back on after cable has been re-inserted. Up until 9603 * now, the DC has been in reset to save power. 9604 */ 9605 dc_start(dd); 9606 9607 if (qd->cache_refresh_required) { 9608 set_qsfp_int_n(ppd, 0); 9609 9610 wait_for_qsfp_init(ppd); 9611 9612 /* 9613 * Allow INT_N to trigger the QSFP interrupt to watch 9614 * for alarms and warnings 9615 */ 9616 set_qsfp_int_n(ppd, 1); 9617 9618 start_link(ppd); 9619 } 9620 9621 if (qd->check_interrupt_flags) { 9622 u8 qsfp_interrupt_status[16] = {0,}; 9623 9624 if (one_qsfp_read(ppd, dd->hfi1_id, 6, 9625 &qsfp_interrupt_status[0], 16) != 16) { 9626 dd_dev_info(dd, 9627 "%s: Failed to read status of QSFP module\n", 9628 __func__); 9629 } else { 9630 unsigned long flags; 9631 9632 handle_qsfp_error_conditions( 9633 ppd, qsfp_interrupt_status); 9634 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 9635 ppd->qsfp_info.check_interrupt_flags = 0; 9636 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 9637 flags); 9638 } 9639 } 9640 } 9641 9642 static void init_qsfp_int(struct hfi1_devdata *dd) 9643 { 9644 struct hfi1_pportdata *ppd = dd->pport; 9645 u64 qsfp_mask, cce_int_mask; 9646 const int qsfp1_int_smask = QSFP1_INT % 64; 9647 const int qsfp2_int_smask = QSFP2_INT % 64; 9648 9649 /* 9650 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0 9651 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR, 9652 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find 9653 * the index of the appropriate CSR in the CCEIntMask CSR array 9654 */ 9655 cce_int_mask = read_csr(dd, CCE_INT_MASK + 9656 (8 * (QSFP1_INT / 64))); 9657 if (dd->hfi1_id) { 9658 cce_int_mask &= ~((u64)1 << qsfp1_int_smask); 9659 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)), 9660 cce_int_mask); 9661 } else { 9662 cce_int_mask &= ~((u64)1 << qsfp2_int_smask); 9663 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)), 9664 cce_int_mask); 9665 } 9666 9667 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 9668 /* Clear current status to avoid spurious interrupts */ 9669 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9670 qsfp_mask); 9671 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, 9672 qsfp_mask); 9673 9674 set_qsfp_int_n(ppd, 0); 9675 9676 /* Handle active low nature of INT_N and MODPRST_N pins */ 9677 if (qsfp_mod_present(ppd)) 9678 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N; 9679 write_csr(dd, 9680 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT, 9681 qsfp_mask); 9682 } 9683 9684 /* 9685 * Do a one-time initialize of the LCB block. 9686 */ 9687 static void init_lcb(struct hfi1_devdata *dd) 9688 { 9689 /* simulator does not correctly handle LCB cclk loopback, skip */ 9690 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 9691 return; 9692 9693 /* the DC has been reset earlier in the driver load */ 9694 9695 /* set LCB for cclk loopback on the port */ 9696 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); 9697 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); 9698 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); 9699 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 9700 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); 9701 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); 9702 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); 9703 } 9704 9705 /* 9706 * Perform a test read on the QSFP. Return 0 on success, -ERRNO 9707 * on error. 9708 */ 9709 static int test_qsfp_read(struct hfi1_pportdata *ppd) 9710 { 9711 int ret; 9712 u8 status; 9713 9714 /* 9715 * Report success if not a QSFP or, if it is a QSFP, but the cable is 9716 * not present 9717 */ 9718 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd)) 9719 return 0; 9720 9721 /* read byte 2, the status byte */ 9722 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1); 9723 if (ret < 0) 9724 return ret; 9725 if (ret != 1) 9726 return -EIO; 9727 9728 return 0; /* success */ 9729 } 9730 9731 /* 9732 * Values for QSFP retry. 9733 * 9734 * Give up after 10s (20 x 500ms). The overall timeout was empirically 9735 * arrived at from experience on a large cluster. 9736 */ 9737 #define MAX_QSFP_RETRIES 20 9738 #define QSFP_RETRY_WAIT 500 /* msec */ 9739 9740 /* 9741 * Try a QSFP read. If it fails, schedule a retry for later. 9742 * Called on first link activation after driver load. 9743 */ 9744 static void try_start_link(struct hfi1_pportdata *ppd) 9745 { 9746 if (test_qsfp_read(ppd)) { 9747 /* read failed */ 9748 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) { 9749 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n"); 9750 return; 9751 } 9752 dd_dev_info(ppd->dd, 9753 "QSFP not responding, waiting and retrying %d\n", 9754 (int)ppd->qsfp_retry_count); 9755 ppd->qsfp_retry_count++; 9756 queue_delayed_work(ppd->link_wq, &ppd->start_link_work, 9757 msecs_to_jiffies(QSFP_RETRY_WAIT)); 9758 return; 9759 } 9760 ppd->qsfp_retry_count = 0; 9761 9762 start_link(ppd); 9763 } 9764 9765 /* 9766 * Workqueue function to start the link after a delay. 9767 */ 9768 void handle_start_link(struct work_struct *work) 9769 { 9770 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 9771 start_link_work.work); 9772 try_start_link(ppd); 9773 } 9774 9775 int bringup_serdes(struct hfi1_pportdata *ppd) 9776 { 9777 struct hfi1_devdata *dd = ppd->dd; 9778 u64 guid; 9779 int ret; 9780 9781 if (HFI1_CAP_IS_KSET(EXTENDED_PSN)) 9782 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK); 9783 9784 guid = ppd->guids[HFI1_PORT_GUID_INDEX]; 9785 if (!guid) { 9786 if (dd->base_guid) 9787 guid = dd->base_guid + ppd->port - 1; 9788 ppd->guids[HFI1_PORT_GUID_INDEX] = guid; 9789 } 9790 9791 /* Set linkinit_reason on power up per OPA spec */ 9792 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP; 9793 9794 /* one-time init of the LCB */ 9795 init_lcb(dd); 9796 9797 if (loopback) { 9798 ret = init_loopback(dd); 9799 if (ret < 0) 9800 return ret; 9801 } 9802 9803 get_port_type(ppd); 9804 if (ppd->port_type == PORT_TYPE_QSFP) { 9805 set_qsfp_int_n(ppd, 0); 9806 wait_for_qsfp_init(ppd); 9807 set_qsfp_int_n(ppd, 1); 9808 } 9809 9810 try_start_link(ppd); 9811 return 0; 9812 } 9813 9814 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd) 9815 { 9816 struct hfi1_devdata *dd = ppd->dd; 9817 9818 /* 9819 * Shut down the link and keep it down. First turn off that the 9820 * driver wants to allow the link to be up (driver_link_ready). 9821 * Then make sure the link is not automatically restarted 9822 * (link_enabled). Cancel any pending restart. And finally 9823 * go offline. 9824 */ 9825 ppd->driver_link_ready = 0; 9826 ppd->link_enabled = 0; 9827 9828 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */ 9829 flush_delayed_work(&ppd->start_link_work); 9830 cancel_delayed_work_sync(&ppd->start_link_work); 9831 9832 ppd->offline_disabled_reason = 9833 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT); 9834 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0, 9835 OPA_LINKDOWN_REASON_REBOOT); 9836 set_link_state(ppd, HLS_DN_OFFLINE); 9837 9838 /* disable the port */ 9839 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 9840 } 9841 9842 static inline int init_cpu_counters(struct hfi1_devdata *dd) 9843 { 9844 struct hfi1_pportdata *ppd; 9845 int i; 9846 9847 ppd = (struct hfi1_pportdata *)(dd + 1); 9848 for (i = 0; i < dd->num_pports; i++, ppd++) { 9849 ppd->ibport_data.rvp.rc_acks = NULL; 9850 ppd->ibport_data.rvp.rc_qacks = NULL; 9851 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64); 9852 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64); 9853 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64); 9854 if (!ppd->ibport_data.rvp.rc_acks || 9855 !ppd->ibport_data.rvp.rc_delayed_comp || 9856 !ppd->ibport_data.rvp.rc_qacks) 9857 return -ENOMEM; 9858 } 9859 9860 return 0; 9861 } 9862 9863 /* 9864 * index is the index into the receive array 9865 */ 9866 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, 9867 u32 type, unsigned long pa, u16 order) 9868 { 9869 u64 reg; 9870 9871 if (!(dd->flags & HFI1_PRESENT)) 9872 goto done; 9873 9874 if (type == PT_INVALID || type == PT_INVALID_FLUSH) { 9875 pa = 0; 9876 order = 0; 9877 } else if (type > PT_INVALID) { 9878 dd_dev_err(dd, 9879 "unexpected receive array type %u for index %u, not handled\n", 9880 type, index); 9881 goto done; 9882 } 9883 trace_hfi1_put_tid(dd, index, type, pa, order); 9884 9885 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */ 9886 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK 9887 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT 9888 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK) 9889 << RCV_ARRAY_RT_ADDR_SHIFT; 9890 trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg); 9891 writeq(reg, dd->rcvarray_wc + (index * 8)); 9892 9893 if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3) 9894 /* 9895 * Eager entries are written and flushed 9896 * 9897 * Expected entries are flushed every 4 writes 9898 */ 9899 flush_wc(); 9900 done: 9901 return; 9902 } 9903 9904 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd) 9905 { 9906 struct hfi1_devdata *dd = rcd->dd; 9907 u32 i; 9908 9909 /* this could be optimized */ 9910 for (i = rcd->eager_base; i < rcd->eager_base + 9911 rcd->egrbufs.alloced; i++) 9912 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 9913 9914 for (i = rcd->expected_base; 9915 i < rcd->expected_base + rcd->expected_count; i++) 9916 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 9917 } 9918 9919 static const char * const ib_cfg_name_strings[] = { 9920 "HFI1_IB_CFG_LIDLMC", 9921 "HFI1_IB_CFG_LWID_DG_ENB", 9922 "HFI1_IB_CFG_LWID_ENB", 9923 "HFI1_IB_CFG_LWID", 9924 "HFI1_IB_CFG_SPD_ENB", 9925 "HFI1_IB_CFG_SPD", 9926 "HFI1_IB_CFG_RXPOL_ENB", 9927 "HFI1_IB_CFG_LREV_ENB", 9928 "HFI1_IB_CFG_LINKLATENCY", 9929 "HFI1_IB_CFG_HRTBT", 9930 "HFI1_IB_CFG_OP_VLS", 9931 "HFI1_IB_CFG_VL_HIGH_CAP", 9932 "HFI1_IB_CFG_VL_LOW_CAP", 9933 "HFI1_IB_CFG_OVERRUN_THRESH", 9934 "HFI1_IB_CFG_PHYERR_THRESH", 9935 "HFI1_IB_CFG_LINKDEFAULT", 9936 "HFI1_IB_CFG_PKEYS", 9937 "HFI1_IB_CFG_MTU", 9938 "HFI1_IB_CFG_LSTATE", 9939 "HFI1_IB_CFG_VL_HIGH_LIMIT", 9940 "HFI1_IB_CFG_PMA_TICKS", 9941 "HFI1_IB_CFG_PORT" 9942 }; 9943 9944 static const char *ib_cfg_name(int which) 9945 { 9946 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings)) 9947 return "invalid"; 9948 return ib_cfg_name_strings[which]; 9949 } 9950 9951 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which) 9952 { 9953 struct hfi1_devdata *dd = ppd->dd; 9954 int val = 0; 9955 9956 switch (which) { 9957 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */ 9958 val = ppd->link_width_enabled; 9959 break; 9960 case HFI1_IB_CFG_LWID: /* currently active Link-width */ 9961 val = ppd->link_width_active; 9962 break; 9963 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 9964 val = ppd->link_speed_enabled; 9965 break; 9966 case HFI1_IB_CFG_SPD: /* current Link speed */ 9967 val = ppd->link_speed_active; 9968 break; 9969 9970 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */ 9971 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */ 9972 case HFI1_IB_CFG_LINKLATENCY: 9973 goto unimplemented; 9974 9975 case HFI1_IB_CFG_OP_VLS: 9976 val = ppd->actual_vls_operational; 9977 break; 9978 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */ 9979 val = VL_ARB_HIGH_PRIO_TABLE_SIZE; 9980 break; 9981 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */ 9982 val = VL_ARB_LOW_PRIO_TABLE_SIZE; 9983 break; 9984 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 9985 val = ppd->overrun_threshold; 9986 break; 9987 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 9988 val = ppd->phy_error_threshold; 9989 break; 9990 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 9991 val = HLS_DEFAULT; 9992 break; 9993 9994 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */ 9995 case HFI1_IB_CFG_PMA_TICKS: 9996 default: 9997 unimplemented: 9998 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 9999 dd_dev_info( 10000 dd, 10001 "%s: which %s: not implemented\n", 10002 __func__, 10003 ib_cfg_name(which)); 10004 break; 10005 } 10006 10007 return val; 10008 } 10009 10010 /* 10011 * The largest MAD packet size. 10012 */ 10013 #define MAX_MAD_PACKET 2048 10014 10015 /* 10016 * Return the maximum header bytes that can go on the _wire_ 10017 * for this device. This count includes the ICRC which is 10018 * not part of the packet held in memory but it is appended 10019 * by the HW. 10020 * This is dependent on the device's receive header entry size. 10021 * HFI allows this to be set per-receive context, but the 10022 * driver presently enforces a global value. 10023 */ 10024 u32 lrh_max_header_bytes(struct hfi1_devdata *dd) 10025 { 10026 /* 10027 * The maximum non-payload (MTU) bytes in LRH.PktLen are 10028 * the Receive Header Entry Size minus the PBC (or RHF) size 10029 * plus one DW for the ICRC appended by HW. 10030 * 10031 * dd->rcd[0].rcvhdrqentsize is in DW. 10032 * We use rcd[0] as all context will have the same value. Also, 10033 * the first kernel context would have been allocated by now so 10034 * we are guaranteed a valid value. 10035 */ 10036 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2; 10037 } 10038 10039 /* 10040 * Set Send Length 10041 * @ppd - per port data 10042 * 10043 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck* 10044 * registers compare against LRH.PktLen, so use the max bytes included 10045 * in the LRH. 10046 * 10047 * This routine changes all VL values except VL15, which it maintains at 10048 * the same value. 10049 */ 10050 static void set_send_length(struct hfi1_pportdata *ppd) 10051 { 10052 struct hfi1_devdata *dd = ppd->dd; 10053 u32 max_hb = lrh_max_header_bytes(dd), dcmtu; 10054 u32 maxvlmtu = dd->vld[15].mtu; 10055 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2) 10056 & SEND_LEN_CHECK1_LEN_VL15_MASK) << 10057 SEND_LEN_CHECK1_LEN_VL15_SHIFT; 10058 int i, j; 10059 u32 thres; 10060 10061 for (i = 0; i < ppd->vls_supported; i++) { 10062 if (dd->vld[i].mtu > maxvlmtu) 10063 maxvlmtu = dd->vld[i].mtu; 10064 if (i <= 3) 10065 len1 |= (((dd->vld[i].mtu + max_hb) >> 2) 10066 & SEND_LEN_CHECK0_LEN_VL0_MASK) << 10067 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT); 10068 else 10069 len2 |= (((dd->vld[i].mtu + max_hb) >> 2) 10070 & SEND_LEN_CHECK1_LEN_VL4_MASK) << 10071 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT); 10072 } 10073 write_csr(dd, SEND_LEN_CHECK0, len1); 10074 write_csr(dd, SEND_LEN_CHECK1, len2); 10075 /* adjust kernel credit return thresholds based on new MTUs */ 10076 /* all kernel receive contexts have the same hdrqentsize */ 10077 for (i = 0; i < ppd->vls_supported; i++) { 10078 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50), 10079 sc_mtu_to_threshold(dd->vld[i].sc, 10080 dd->vld[i].mtu, 10081 dd->rcd[0]->rcvhdrqentsize)); 10082 for (j = 0; j < INIT_SC_PER_VL; j++) 10083 sc_set_cr_threshold( 10084 pio_select_send_context_vl(dd, j, i), 10085 thres); 10086 } 10087 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50), 10088 sc_mtu_to_threshold(dd->vld[15].sc, 10089 dd->vld[15].mtu, 10090 dd->rcd[0]->rcvhdrqentsize)); 10091 sc_set_cr_threshold(dd->vld[15].sc, thres); 10092 10093 /* Adjust maximum MTU for the port in DC */ 10094 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 : 10095 (ilog2(maxvlmtu >> 8) + 1); 10096 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); 10097 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK; 10098 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) << 10099 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT; 10100 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); 10101 } 10102 10103 static void set_lidlmc(struct hfi1_pportdata *ppd) 10104 { 10105 int i; 10106 u64 sreg = 0; 10107 struct hfi1_devdata *dd = ppd->dd; 10108 u32 mask = ~((1U << ppd->lmc) - 1); 10109 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); 10110 u32 lid; 10111 10112 /* 10113 * Program 0 in CSR if port lid is extended. This prevents 10114 * 9B packets being sent out for large lids. 10115 */ 10116 lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid; 10117 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 10118 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK); 10119 c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK) 10120 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) | 10121 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK) 10122 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT); 10123 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); 10124 10125 /* 10126 * Iterate over all the send contexts and set their SLID check 10127 */ 10128 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) << 10129 SEND_CTXT_CHECK_SLID_MASK_SHIFT) | 10130 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) << 10131 SEND_CTXT_CHECK_SLID_VALUE_SHIFT); 10132 10133 for (i = 0; i < dd->chip_send_contexts; i++) { 10134 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x", 10135 i, (u32)sreg); 10136 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg); 10137 } 10138 10139 /* Now we have to do the same thing for the sdma engines */ 10140 sdma_update_lmc(dd, mask, lid); 10141 } 10142 10143 static const char *state_completed_string(u32 completed) 10144 { 10145 static const char * const state_completed[] = { 10146 "EstablishComm", 10147 "OptimizeEQ", 10148 "VerifyCap" 10149 }; 10150 10151 if (completed < ARRAY_SIZE(state_completed)) 10152 return state_completed[completed]; 10153 10154 return "unknown"; 10155 } 10156 10157 static const char all_lanes_dead_timeout_expired[] = 10158 "All lanes were inactive – was the interconnect media removed?"; 10159 static const char tx_out_of_policy[] = 10160 "Passing lanes on local port do not meet the local link width policy"; 10161 static const char no_state_complete[] = 10162 "State timeout occurred before link partner completed the state"; 10163 static const char * const state_complete_reasons[] = { 10164 [0x00] = "Reason unknown", 10165 [0x01] = "Link was halted by driver, refer to LinkDownReason", 10166 [0x02] = "Link partner reported failure", 10167 [0x10] = "Unable to achieve frame sync on any lane", 10168 [0x11] = 10169 "Unable to find a common bit rate with the link partner", 10170 [0x12] = 10171 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy", 10172 [0x13] = 10173 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy", 10174 [0x14] = no_state_complete, 10175 [0x15] = 10176 "State timeout occurred before link partner identified equalization presets", 10177 [0x16] = 10178 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy", 10179 [0x17] = tx_out_of_policy, 10180 [0x20] = all_lanes_dead_timeout_expired, 10181 [0x21] = 10182 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy", 10183 [0x22] = no_state_complete, 10184 [0x23] = 10185 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy", 10186 [0x24] = tx_out_of_policy, 10187 [0x30] = all_lanes_dead_timeout_expired, 10188 [0x31] = 10189 "State timeout occurred waiting for host to process received frames", 10190 [0x32] = no_state_complete, 10191 [0x33] = 10192 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy", 10193 [0x34] = tx_out_of_policy, 10194 [0x35] = "Negotiated link width is mutually exclusive", 10195 [0x36] = 10196 "Timed out before receiving verifycap frames in VerifyCap.Exchange", 10197 [0x37] = "Unable to resolve secure data exchange", 10198 }; 10199 10200 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd, 10201 u32 code) 10202 { 10203 const char *str = NULL; 10204 10205 if (code < ARRAY_SIZE(state_complete_reasons)) 10206 str = state_complete_reasons[code]; 10207 10208 if (str) 10209 return str; 10210 return "Reserved"; 10211 } 10212 10213 /* describe the given last state complete frame */ 10214 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame, 10215 const char *prefix) 10216 { 10217 struct hfi1_devdata *dd = ppd->dd; 10218 u32 success; 10219 u32 state; 10220 u32 reason; 10221 u32 lanes; 10222 10223 /* 10224 * Decode frame: 10225 * [ 0: 0] - success 10226 * [ 3: 1] - state 10227 * [ 7: 4] - next state timeout 10228 * [15: 8] - reason code 10229 * [31:16] - lanes 10230 */ 10231 success = frame & 0x1; 10232 state = (frame >> 1) & 0x7; 10233 reason = (frame >> 8) & 0xff; 10234 lanes = (frame >> 16) & 0xffff; 10235 10236 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n", 10237 prefix, frame); 10238 dd_dev_err(dd, " last reported state state: %s (0x%x)\n", 10239 state_completed_string(state), state); 10240 dd_dev_err(dd, " state successfully completed: %s\n", 10241 success ? "yes" : "no"); 10242 dd_dev_err(dd, " fail reason 0x%x: %s\n", 10243 reason, state_complete_reason_code_string(ppd, reason)); 10244 dd_dev_err(dd, " passing lane mask: 0x%x", lanes); 10245 } 10246 10247 /* 10248 * Read the last state complete frames and explain them. This routine 10249 * expects to be called if the link went down during link negotiation 10250 * and initialization (LNI). That is, anywhere between polling and link up. 10251 */ 10252 static void check_lni_states(struct hfi1_pportdata *ppd) 10253 { 10254 u32 last_local_state; 10255 u32 last_remote_state; 10256 10257 read_last_local_state(ppd->dd, &last_local_state); 10258 read_last_remote_state(ppd->dd, &last_remote_state); 10259 10260 /* 10261 * Don't report anything if there is nothing to report. A value of 10262 * 0 means the link was taken down while polling and there was no 10263 * training in-process. 10264 */ 10265 if (last_local_state == 0 && last_remote_state == 0) 10266 return; 10267 10268 decode_state_complete(ppd, last_local_state, "transmitted"); 10269 decode_state_complete(ppd, last_remote_state, "received"); 10270 } 10271 10272 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */ 10273 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms) 10274 { 10275 u64 reg; 10276 unsigned long timeout; 10277 10278 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */ 10279 timeout = jiffies + msecs_to_jiffies(wait_ms); 10280 while (1) { 10281 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); 10282 if (reg) 10283 break; 10284 if (time_after(jiffies, timeout)) { 10285 dd_dev_err(dd, 10286 "timeout waiting for LINK_TRANSFER_ACTIVE\n"); 10287 return -ETIMEDOUT; 10288 } 10289 udelay(2); 10290 } 10291 return 0; 10292 } 10293 10294 /* called when the logical link state is not down as it should be */ 10295 static void force_logical_link_state_down(struct hfi1_pportdata *ppd) 10296 { 10297 struct hfi1_devdata *dd = ppd->dd; 10298 10299 /* 10300 * Bring link up in LCB loopback 10301 */ 10302 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10303 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 10304 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 10305 10306 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 10307 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); 10308 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 10309 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); 10310 10311 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 10312 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); 10313 udelay(3); 10314 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); 10315 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 10316 10317 wait_link_transfer_active(dd, 100); 10318 10319 /* 10320 * Bring the link down again. 10321 */ 10322 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10323 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); 10324 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); 10325 10326 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n"); 10327 } 10328 10329 /* 10330 * Helper for set_link_state(). Do not call except from that routine. 10331 * Expects ppd->hls_mutex to be held. 10332 * 10333 * @rem_reason value to be sent to the neighbor 10334 * 10335 * LinkDownReasons only set if transition succeeds. 10336 */ 10337 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason) 10338 { 10339 struct hfi1_devdata *dd = ppd->dd; 10340 u32 previous_state; 10341 int offline_state_ret; 10342 int ret; 10343 10344 update_lcb_cache(dd); 10345 10346 previous_state = ppd->host_link_state; 10347 ppd->host_link_state = HLS_GOING_OFFLINE; 10348 10349 /* start offline transition */ 10350 ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE); 10351 10352 if (ret != HCMD_SUCCESS) { 10353 dd_dev_err(dd, 10354 "Failed to transition to Offline link state, return %d\n", 10355 ret); 10356 return -EINVAL; 10357 } 10358 if (ppd->offline_disabled_reason == 10359 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)) 10360 ppd->offline_disabled_reason = 10361 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 10362 10363 offline_state_ret = wait_phys_link_offline_substates(ppd, 10000); 10364 if (offline_state_ret < 0) 10365 return offline_state_ret; 10366 10367 /* Disabling AOC transmitters */ 10368 if (ppd->port_type == PORT_TYPE_QSFP && 10369 ppd->qsfp_info.limiting_active && 10370 qsfp_mod_present(ppd)) { 10371 int ret; 10372 10373 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT); 10374 if (ret == 0) { 10375 set_qsfp_tx(ppd, 0); 10376 release_chip_resource(dd, qsfp_resource(dd)); 10377 } else { 10378 /* not fatal, but should warn */ 10379 dd_dev_err(dd, 10380 "Unable to acquire lock to turn off QSFP TX\n"); 10381 } 10382 } 10383 10384 /* 10385 * Wait for the offline.Quiet transition if it hasn't happened yet. It 10386 * can take a while for the link to go down. 10387 */ 10388 if (offline_state_ret != PLS_OFFLINE_QUIET) { 10389 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000); 10390 if (ret < 0) 10391 return ret; 10392 } 10393 10394 /* 10395 * Now in charge of LCB - must be after the physical state is 10396 * offline.quiet and before host_link_state is changed. 10397 */ 10398 set_host_lcb_access(dd); 10399 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 10400 10401 /* make sure the logical state is also down */ 10402 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000); 10403 if (ret) 10404 force_logical_link_state_down(ppd); 10405 10406 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */ 10407 update_statusp(ppd, IB_PORT_DOWN); 10408 10409 /* 10410 * The LNI has a mandatory wait time after the physical state 10411 * moves to Offline.Quiet. The wait time may be different 10412 * depending on how the link went down. The 8051 firmware 10413 * will observe the needed wait time and only move to ready 10414 * when that is completed. The largest of the quiet timeouts 10415 * is 6s, so wait that long and then at least 0.5s more for 10416 * other transitions, and another 0.5s for a buffer. 10417 */ 10418 ret = wait_fm_ready(dd, 7000); 10419 if (ret) { 10420 dd_dev_err(dd, 10421 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n"); 10422 /* state is really offline, so make it so */ 10423 ppd->host_link_state = HLS_DN_OFFLINE; 10424 return ret; 10425 } 10426 10427 /* 10428 * The state is now offline and the 8051 is ready to accept host 10429 * requests. 10430 * - change our state 10431 * - notify others if we were previously in a linkup state 10432 */ 10433 ppd->host_link_state = HLS_DN_OFFLINE; 10434 if (previous_state & HLS_UP) { 10435 /* went down while link was up */ 10436 handle_linkup_change(dd, 0); 10437 } else if (previous_state 10438 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 10439 /* went down while attempting link up */ 10440 check_lni_states(ppd); 10441 10442 /* The QSFP doesn't need to be reset on LNI failure */ 10443 ppd->qsfp_info.reset_needed = 0; 10444 } 10445 10446 /* the active link width (downgrade) is 0 on link down */ 10447 ppd->link_width_active = 0; 10448 ppd->link_width_downgrade_tx_active = 0; 10449 ppd->link_width_downgrade_rx_active = 0; 10450 ppd->current_egress_rate = 0; 10451 return 0; 10452 } 10453 10454 /* return the link state name */ 10455 static const char *link_state_name(u32 state) 10456 { 10457 const char *name; 10458 int n = ilog2(state); 10459 static const char * const names[] = { 10460 [__HLS_UP_INIT_BP] = "INIT", 10461 [__HLS_UP_ARMED_BP] = "ARMED", 10462 [__HLS_UP_ACTIVE_BP] = "ACTIVE", 10463 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF", 10464 [__HLS_DN_POLL_BP] = "POLL", 10465 [__HLS_DN_DISABLE_BP] = "DISABLE", 10466 [__HLS_DN_OFFLINE_BP] = "OFFLINE", 10467 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP", 10468 [__HLS_GOING_UP_BP] = "GOING_UP", 10469 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE", 10470 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN" 10471 }; 10472 10473 name = n < ARRAY_SIZE(names) ? names[n] : NULL; 10474 return name ? name : "unknown"; 10475 } 10476 10477 /* return the link state reason name */ 10478 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state) 10479 { 10480 if (state == HLS_UP_INIT) { 10481 switch (ppd->linkinit_reason) { 10482 case OPA_LINKINIT_REASON_LINKUP: 10483 return "(LINKUP)"; 10484 case OPA_LINKINIT_REASON_FLAPPING: 10485 return "(FLAPPING)"; 10486 case OPA_LINKINIT_OUTSIDE_POLICY: 10487 return "(OUTSIDE_POLICY)"; 10488 case OPA_LINKINIT_QUARANTINED: 10489 return "(QUARANTINED)"; 10490 case OPA_LINKINIT_INSUFIC_CAPABILITY: 10491 return "(INSUFIC_CAPABILITY)"; 10492 default: 10493 break; 10494 } 10495 } 10496 return ""; 10497 } 10498 10499 /* 10500 * driver_pstate - convert the driver's notion of a port's 10501 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*). 10502 * Return -1 (converted to a u32) to indicate error. 10503 */ 10504 u32 driver_pstate(struct hfi1_pportdata *ppd) 10505 { 10506 switch (ppd->host_link_state) { 10507 case HLS_UP_INIT: 10508 case HLS_UP_ARMED: 10509 case HLS_UP_ACTIVE: 10510 return IB_PORTPHYSSTATE_LINKUP; 10511 case HLS_DN_POLL: 10512 return IB_PORTPHYSSTATE_POLLING; 10513 case HLS_DN_DISABLE: 10514 return IB_PORTPHYSSTATE_DISABLED; 10515 case HLS_DN_OFFLINE: 10516 return OPA_PORTPHYSSTATE_OFFLINE; 10517 case HLS_VERIFY_CAP: 10518 return IB_PORTPHYSSTATE_TRAINING; 10519 case HLS_GOING_UP: 10520 return IB_PORTPHYSSTATE_TRAINING; 10521 case HLS_GOING_OFFLINE: 10522 return OPA_PORTPHYSSTATE_OFFLINE; 10523 case HLS_LINK_COOLDOWN: 10524 return OPA_PORTPHYSSTATE_OFFLINE; 10525 case HLS_DN_DOWNDEF: 10526 default: 10527 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10528 ppd->host_link_state); 10529 return -1; 10530 } 10531 } 10532 10533 /* 10534 * driver_lstate - convert the driver's notion of a port's 10535 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1 10536 * (converted to a u32) to indicate error. 10537 */ 10538 u32 driver_lstate(struct hfi1_pportdata *ppd) 10539 { 10540 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN)) 10541 return IB_PORT_DOWN; 10542 10543 switch (ppd->host_link_state & HLS_UP) { 10544 case HLS_UP_INIT: 10545 return IB_PORT_INIT; 10546 case HLS_UP_ARMED: 10547 return IB_PORT_ARMED; 10548 case HLS_UP_ACTIVE: 10549 return IB_PORT_ACTIVE; 10550 default: 10551 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10552 ppd->host_link_state); 10553 return -1; 10554 } 10555 } 10556 10557 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 10558 u8 neigh_reason, u8 rem_reason) 10559 { 10560 if (ppd->local_link_down_reason.latest == 0 && 10561 ppd->neigh_link_down_reason.latest == 0) { 10562 ppd->local_link_down_reason.latest = lcl_reason; 10563 ppd->neigh_link_down_reason.latest = neigh_reason; 10564 ppd->remote_link_down_reason = rem_reason; 10565 } 10566 } 10567 10568 /* 10569 * Verify if BCT for data VLs is non-zero. 10570 */ 10571 static inline bool data_vls_operational(struct hfi1_pportdata *ppd) 10572 { 10573 return !!ppd->actual_vls_operational; 10574 } 10575 10576 /* 10577 * Change the physical and/or logical link state. 10578 * 10579 * Do not call this routine while inside an interrupt. It contains 10580 * calls to routines that can take multiple seconds to finish. 10581 * 10582 * Returns 0 on success, -errno on failure. 10583 */ 10584 int set_link_state(struct hfi1_pportdata *ppd, u32 state) 10585 { 10586 struct hfi1_devdata *dd = ppd->dd; 10587 struct ib_event event = {.device = NULL}; 10588 int ret1, ret = 0; 10589 int orig_new_state, poll_bounce; 10590 10591 mutex_lock(&ppd->hls_lock); 10592 10593 orig_new_state = state; 10594 if (state == HLS_DN_DOWNDEF) 10595 state = HLS_DEFAULT; 10596 10597 /* interpret poll -> poll as a link bounce */ 10598 poll_bounce = ppd->host_link_state == HLS_DN_POLL && 10599 state == HLS_DN_POLL; 10600 10601 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__, 10602 link_state_name(ppd->host_link_state), 10603 link_state_name(orig_new_state), 10604 poll_bounce ? "(bounce) " : "", 10605 link_state_reason_name(ppd, state)); 10606 10607 /* 10608 * If we're going to a (HLS_*) link state that implies the logical 10609 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then 10610 * reset is_sm_config_started to 0. 10611 */ 10612 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE))) 10613 ppd->is_sm_config_started = 0; 10614 10615 /* 10616 * Do nothing if the states match. Let a poll to poll link bounce 10617 * go through. 10618 */ 10619 if (ppd->host_link_state == state && !poll_bounce) 10620 goto done; 10621 10622 switch (state) { 10623 case HLS_UP_INIT: 10624 if (ppd->host_link_state == HLS_DN_POLL && 10625 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) { 10626 /* 10627 * Quick link up jumps from polling to here. 10628 * 10629 * Whether in normal or loopback mode, the 10630 * simulator jumps from polling to link up. 10631 * Accept that here. 10632 */ 10633 /* OK */ 10634 } else if (ppd->host_link_state != HLS_GOING_UP) { 10635 goto unexpected; 10636 } 10637 10638 /* 10639 * Wait for Link_Up physical state. 10640 * Physical and Logical states should already be 10641 * be transitioned to LinkUp and LinkInit respectively. 10642 */ 10643 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000); 10644 if (ret) { 10645 dd_dev_err(dd, 10646 "%s: physical state did not change to LINK-UP\n", 10647 __func__); 10648 break; 10649 } 10650 10651 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000); 10652 if (ret) { 10653 dd_dev_err(dd, 10654 "%s: logical state did not change to INIT\n", 10655 __func__); 10656 break; 10657 } 10658 10659 /* clear old transient LINKINIT_REASON code */ 10660 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR) 10661 ppd->linkinit_reason = 10662 OPA_LINKINIT_REASON_LINKUP; 10663 10664 /* enable the port */ 10665 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 10666 10667 handle_linkup_change(dd, 1); 10668 10669 /* 10670 * After link up, a new link width will have been set. 10671 * Update the xmit counters with regards to the new 10672 * link width. 10673 */ 10674 update_xmit_counters(ppd, ppd->link_width_active); 10675 10676 ppd->host_link_state = HLS_UP_INIT; 10677 update_statusp(ppd, IB_PORT_INIT); 10678 break; 10679 case HLS_UP_ARMED: 10680 if (ppd->host_link_state != HLS_UP_INIT) 10681 goto unexpected; 10682 10683 if (!data_vls_operational(ppd)) { 10684 dd_dev_err(dd, 10685 "%s: data VLs not operational\n", __func__); 10686 ret = -EINVAL; 10687 break; 10688 } 10689 10690 set_logical_state(dd, LSTATE_ARMED); 10691 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000); 10692 if (ret) { 10693 dd_dev_err(dd, 10694 "%s: logical state did not change to ARMED\n", 10695 __func__); 10696 break; 10697 } 10698 ppd->host_link_state = HLS_UP_ARMED; 10699 update_statusp(ppd, IB_PORT_ARMED); 10700 /* 10701 * The simulator does not currently implement SMA messages, 10702 * so neighbor_normal is not set. Set it here when we first 10703 * move to Armed. 10704 */ 10705 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 10706 ppd->neighbor_normal = 1; 10707 break; 10708 case HLS_UP_ACTIVE: 10709 if (ppd->host_link_state != HLS_UP_ARMED) 10710 goto unexpected; 10711 10712 set_logical_state(dd, LSTATE_ACTIVE); 10713 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000); 10714 if (ret) { 10715 dd_dev_err(dd, 10716 "%s: logical state did not change to ACTIVE\n", 10717 __func__); 10718 } else { 10719 /* tell all engines to go running */ 10720 sdma_all_running(dd); 10721 ppd->host_link_state = HLS_UP_ACTIVE; 10722 update_statusp(ppd, IB_PORT_ACTIVE); 10723 10724 /* Signal the IB layer that the port has went active */ 10725 event.device = &dd->verbs_dev.rdi.ibdev; 10726 event.element.port_num = ppd->port; 10727 event.event = IB_EVENT_PORT_ACTIVE; 10728 } 10729 break; 10730 case HLS_DN_POLL: 10731 if ((ppd->host_link_state == HLS_DN_DISABLE || 10732 ppd->host_link_state == HLS_DN_OFFLINE) && 10733 dd->dc_shutdown) 10734 dc_start(dd); 10735 /* Hand LED control to the DC */ 10736 write_csr(dd, DCC_CFG_LED_CNTRL, 0); 10737 10738 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10739 u8 tmp = ppd->link_enabled; 10740 10741 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10742 if (ret) { 10743 ppd->link_enabled = tmp; 10744 break; 10745 } 10746 ppd->remote_link_down_reason = 0; 10747 10748 if (ppd->driver_link_ready) 10749 ppd->link_enabled = 1; 10750 } 10751 10752 set_all_slowpath(ppd->dd); 10753 ret = set_local_link_attributes(ppd); 10754 if (ret) 10755 break; 10756 10757 ppd->port_error_action = 0; 10758 ppd->host_link_state = HLS_DN_POLL; 10759 10760 if (quick_linkup) { 10761 /* quick linkup does not go into polling */ 10762 ret = do_quick_linkup(dd); 10763 } else { 10764 ret1 = set_physical_link_state(dd, PLS_POLLING); 10765 if (ret1 != HCMD_SUCCESS) { 10766 dd_dev_err(dd, 10767 "Failed to transition to Polling link state, return 0x%x\n", 10768 ret1); 10769 ret = -EINVAL; 10770 } 10771 } 10772 ppd->offline_disabled_reason = 10773 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE); 10774 /* 10775 * If an error occurred above, go back to offline. The 10776 * caller may reschedule another attempt. 10777 */ 10778 if (ret) 10779 goto_offline(ppd, 0); 10780 else 10781 log_physical_state(ppd, PLS_POLLING); 10782 break; 10783 case HLS_DN_DISABLE: 10784 /* link is disabled */ 10785 ppd->link_enabled = 0; 10786 10787 /* allow any state to transition to disabled */ 10788 10789 /* must transition to offline first */ 10790 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10791 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10792 if (ret) 10793 break; 10794 ppd->remote_link_down_reason = 0; 10795 } 10796 10797 if (!dd->dc_shutdown) { 10798 ret1 = set_physical_link_state(dd, PLS_DISABLED); 10799 if (ret1 != HCMD_SUCCESS) { 10800 dd_dev_err(dd, 10801 "Failed to transition to Disabled link state, return 0x%x\n", 10802 ret1); 10803 ret = -EINVAL; 10804 break; 10805 } 10806 ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000); 10807 if (ret) { 10808 dd_dev_err(dd, 10809 "%s: physical state did not change to DISABLED\n", 10810 __func__); 10811 break; 10812 } 10813 dc_shutdown(dd); 10814 } 10815 ppd->host_link_state = HLS_DN_DISABLE; 10816 break; 10817 case HLS_DN_OFFLINE: 10818 if (ppd->host_link_state == HLS_DN_DISABLE) 10819 dc_start(dd); 10820 10821 /* allow any state to transition to offline */ 10822 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10823 if (!ret) 10824 ppd->remote_link_down_reason = 0; 10825 break; 10826 case HLS_VERIFY_CAP: 10827 if (ppd->host_link_state != HLS_DN_POLL) 10828 goto unexpected; 10829 ppd->host_link_state = HLS_VERIFY_CAP; 10830 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP); 10831 break; 10832 case HLS_GOING_UP: 10833 if (ppd->host_link_state != HLS_VERIFY_CAP) 10834 goto unexpected; 10835 10836 ret1 = set_physical_link_state(dd, PLS_LINKUP); 10837 if (ret1 != HCMD_SUCCESS) { 10838 dd_dev_err(dd, 10839 "Failed to transition to link up state, return 0x%x\n", 10840 ret1); 10841 ret = -EINVAL; 10842 break; 10843 } 10844 ppd->host_link_state = HLS_GOING_UP; 10845 break; 10846 10847 case HLS_GOING_OFFLINE: /* transient within goto_offline() */ 10848 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */ 10849 default: 10850 dd_dev_info(dd, "%s: state 0x%x: not supported\n", 10851 __func__, state); 10852 ret = -EINVAL; 10853 break; 10854 } 10855 10856 goto done; 10857 10858 unexpected: 10859 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n", 10860 __func__, link_state_name(ppd->host_link_state), 10861 link_state_name(state)); 10862 ret = -EINVAL; 10863 10864 done: 10865 mutex_unlock(&ppd->hls_lock); 10866 10867 if (event.device) 10868 ib_dispatch_event(&event); 10869 10870 return ret; 10871 } 10872 10873 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val) 10874 { 10875 u64 reg; 10876 int ret = 0; 10877 10878 switch (which) { 10879 case HFI1_IB_CFG_LIDLMC: 10880 set_lidlmc(ppd); 10881 break; 10882 case HFI1_IB_CFG_VL_HIGH_LIMIT: 10883 /* 10884 * The VL Arbitrator high limit is sent in units of 4k 10885 * bytes, while HFI stores it in units of 64 bytes. 10886 */ 10887 val *= 4096 / 64; 10888 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) 10889 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT; 10890 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); 10891 break; 10892 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 10893 /* HFI only supports POLL as the default link down state */ 10894 if (val != HLS_DN_POLL) 10895 ret = -EINVAL; 10896 break; 10897 case HFI1_IB_CFG_OP_VLS: 10898 if (ppd->vls_operational != val) { 10899 ppd->vls_operational = val; 10900 if (!ppd->port) 10901 ret = -EINVAL; 10902 } 10903 break; 10904 /* 10905 * For link width, link width downgrade, and speed enable, always AND 10906 * the setting with what is actually supported. This has two benefits. 10907 * First, enabled can't have unsupported values, no matter what the 10908 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean 10909 * "fill in with your supported value" have all the bits in the 10910 * field set, so simply ANDing with supported has the desired result. 10911 */ 10912 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */ 10913 ppd->link_width_enabled = val & ppd->link_width_supported; 10914 break; 10915 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */ 10916 ppd->link_width_downgrade_enabled = 10917 val & ppd->link_width_downgrade_supported; 10918 break; 10919 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 10920 ppd->link_speed_enabled = val & ppd->link_speed_supported; 10921 break; 10922 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 10923 /* 10924 * HFI does not follow IB specs, save this value 10925 * so we can report it, if asked. 10926 */ 10927 ppd->overrun_threshold = val; 10928 break; 10929 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 10930 /* 10931 * HFI does not follow IB specs, save this value 10932 * so we can report it, if asked. 10933 */ 10934 ppd->phy_error_threshold = val; 10935 break; 10936 10937 case HFI1_IB_CFG_MTU: 10938 set_send_length(ppd); 10939 break; 10940 10941 case HFI1_IB_CFG_PKEYS: 10942 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 10943 set_partition_keys(ppd); 10944 break; 10945 10946 default: 10947 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 10948 dd_dev_info(ppd->dd, 10949 "%s: which %s, val 0x%x: not implemented\n", 10950 __func__, ib_cfg_name(which), val); 10951 break; 10952 } 10953 return ret; 10954 } 10955 10956 /* begin functions related to vl arbitration table caching */ 10957 static void init_vl_arb_caches(struct hfi1_pportdata *ppd) 10958 { 10959 int i; 10960 10961 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 10962 VL_ARB_LOW_PRIO_TABLE_SIZE); 10963 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 10964 VL_ARB_HIGH_PRIO_TABLE_SIZE); 10965 10966 /* 10967 * Note that we always return values directly from the 10968 * 'vl_arb_cache' (and do no CSR reads) in response to a 10969 * 'Get(VLArbTable)'. This is obviously correct after a 10970 * 'Set(VLArbTable)', since the cache will then be up to 10971 * date. But it's also correct prior to any 'Set(VLArbTable)' 10972 * since then both the cache, and the relevant h/w registers 10973 * will be zeroed. 10974 */ 10975 10976 for (i = 0; i < MAX_PRIO_TABLE; i++) 10977 spin_lock_init(&ppd->vl_arb_cache[i].lock); 10978 } 10979 10980 /* 10981 * vl_arb_lock_cache 10982 * 10983 * All other vl_arb_* functions should be called only after locking 10984 * the cache. 10985 */ 10986 static inline struct vl_arb_cache * 10987 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx) 10988 { 10989 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE) 10990 return NULL; 10991 spin_lock(&ppd->vl_arb_cache[idx].lock); 10992 return &ppd->vl_arb_cache[idx]; 10993 } 10994 10995 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx) 10996 { 10997 spin_unlock(&ppd->vl_arb_cache[idx].lock); 10998 } 10999 11000 static void vl_arb_get_cache(struct vl_arb_cache *cache, 11001 struct ib_vl_weight_elem *vl) 11002 { 11003 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11004 } 11005 11006 static void vl_arb_set_cache(struct vl_arb_cache *cache, 11007 struct ib_vl_weight_elem *vl) 11008 { 11009 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11010 } 11011 11012 static int vl_arb_match_cache(struct vl_arb_cache *cache, 11013 struct ib_vl_weight_elem *vl) 11014 { 11015 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11016 } 11017 11018 /* end functions related to vl arbitration table caching */ 11019 11020 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target, 11021 u32 size, struct ib_vl_weight_elem *vl) 11022 { 11023 struct hfi1_devdata *dd = ppd->dd; 11024 u64 reg; 11025 unsigned int i, is_up = 0; 11026 int drain, ret = 0; 11027 11028 mutex_lock(&ppd->hls_lock); 11029 11030 if (ppd->host_link_state & HLS_UP) 11031 is_up = 1; 11032 11033 drain = !is_ax(dd) && is_up; 11034 11035 if (drain) 11036 /* 11037 * Before adjusting VL arbitration weights, empty per-VL 11038 * FIFOs, otherwise a packet whose VL weight is being 11039 * set to 0 could get stuck in a FIFO with no chance to 11040 * egress. 11041 */ 11042 ret = stop_drain_data_vls(dd); 11043 11044 if (ret) { 11045 dd_dev_err( 11046 dd, 11047 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n", 11048 __func__); 11049 goto err; 11050 } 11051 11052 for (i = 0; i < size; i++, vl++) { 11053 /* 11054 * NOTE: The low priority shift and mask are used here, but 11055 * they are the same for both the low and high registers. 11056 */ 11057 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK) 11058 << SEND_LOW_PRIORITY_LIST_VL_SHIFT) 11059 | (((u64)vl->weight 11060 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK) 11061 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT); 11062 write_csr(dd, target + (i * 8), reg); 11063 } 11064 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE); 11065 11066 if (drain) 11067 open_fill_data_vls(dd); /* reopen all VLs */ 11068 11069 err: 11070 mutex_unlock(&ppd->hls_lock); 11071 11072 return ret; 11073 } 11074 11075 /* 11076 * Read one credit merge VL register. 11077 */ 11078 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr, 11079 struct vl_limit *vll) 11080 { 11081 u64 reg = read_csr(dd, csr); 11082 11083 vll->dedicated = cpu_to_be16( 11084 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT) 11085 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK); 11086 vll->shared = cpu_to_be16( 11087 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT) 11088 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK); 11089 } 11090 11091 /* 11092 * Read the current credit merge limits. 11093 */ 11094 static int get_buffer_control(struct hfi1_devdata *dd, 11095 struct buffer_control *bc, u16 *overall_limit) 11096 { 11097 u64 reg; 11098 int i; 11099 11100 /* not all entries are filled in */ 11101 memset(bc, 0, sizeof(*bc)); 11102 11103 /* OPA and HFI have a 1-1 mapping */ 11104 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11105 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]); 11106 11107 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */ 11108 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]); 11109 11110 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11111 bc->overall_shared_limit = cpu_to_be16( 11112 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) 11113 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK); 11114 if (overall_limit) 11115 *overall_limit = (reg 11116 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) 11117 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK; 11118 return sizeof(struct buffer_control); 11119 } 11120 11121 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11122 { 11123 u64 reg; 11124 int i; 11125 11126 /* each register contains 16 SC->VLnt mappings, 4 bits each */ 11127 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); 11128 for (i = 0; i < sizeof(u64); i++) { 11129 u8 byte = *(((u8 *)®) + i); 11130 11131 dp->vlnt[2 * i] = byte & 0xf; 11132 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4; 11133 } 11134 11135 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); 11136 for (i = 0; i < sizeof(u64); i++) { 11137 u8 byte = *(((u8 *)®) + i); 11138 11139 dp->vlnt[16 + (2 * i)] = byte & 0xf; 11140 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4; 11141 } 11142 return sizeof(struct sc2vlnt); 11143 } 11144 11145 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems, 11146 struct ib_vl_weight_elem *vl) 11147 { 11148 unsigned int i; 11149 11150 for (i = 0; i < nelems; i++, vl++) { 11151 vl->vl = 0xf; 11152 vl->weight = 0; 11153 } 11154 } 11155 11156 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11157 { 11158 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, 11159 DC_SC_VL_VAL(15_0, 11160 0, dp->vlnt[0] & 0xf, 11161 1, dp->vlnt[1] & 0xf, 11162 2, dp->vlnt[2] & 0xf, 11163 3, dp->vlnt[3] & 0xf, 11164 4, dp->vlnt[4] & 0xf, 11165 5, dp->vlnt[5] & 0xf, 11166 6, dp->vlnt[6] & 0xf, 11167 7, dp->vlnt[7] & 0xf, 11168 8, dp->vlnt[8] & 0xf, 11169 9, dp->vlnt[9] & 0xf, 11170 10, dp->vlnt[10] & 0xf, 11171 11, dp->vlnt[11] & 0xf, 11172 12, dp->vlnt[12] & 0xf, 11173 13, dp->vlnt[13] & 0xf, 11174 14, dp->vlnt[14] & 0xf, 11175 15, dp->vlnt[15] & 0xf)); 11176 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, 11177 DC_SC_VL_VAL(31_16, 11178 16, dp->vlnt[16] & 0xf, 11179 17, dp->vlnt[17] & 0xf, 11180 18, dp->vlnt[18] & 0xf, 11181 19, dp->vlnt[19] & 0xf, 11182 20, dp->vlnt[20] & 0xf, 11183 21, dp->vlnt[21] & 0xf, 11184 22, dp->vlnt[22] & 0xf, 11185 23, dp->vlnt[23] & 0xf, 11186 24, dp->vlnt[24] & 0xf, 11187 25, dp->vlnt[25] & 0xf, 11188 26, dp->vlnt[26] & 0xf, 11189 27, dp->vlnt[27] & 0xf, 11190 28, dp->vlnt[28] & 0xf, 11191 29, dp->vlnt[29] & 0xf, 11192 30, dp->vlnt[30] & 0xf, 11193 31, dp->vlnt[31] & 0xf)); 11194 } 11195 11196 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what, 11197 u16 limit) 11198 { 11199 if (limit != 0) 11200 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n", 11201 what, (int)limit, idx); 11202 } 11203 11204 /* change only the shared limit portion of SendCmGLobalCredit */ 11205 static void set_global_shared(struct hfi1_devdata *dd, u16 limit) 11206 { 11207 u64 reg; 11208 11209 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11210 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK; 11211 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT; 11212 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11213 } 11214 11215 /* change only the total credit limit portion of SendCmGLobalCredit */ 11216 static void set_global_limit(struct hfi1_devdata *dd, u16 limit) 11217 { 11218 u64 reg; 11219 11220 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11221 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK; 11222 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 11223 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11224 } 11225 11226 /* set the given per-VL shared limit */ 11227 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit) 11228 { 11229 u64 reg; 11230 u32 addr; 11231 11232 if (vl < TXE_NUM_DATA_VL) 11233 addr = SEND_CM_CREDIT_VL + (8 * vl); 11234 else 11235 addr = SEND_CM_CREDIT_VL15; 11236 11237 reg = read_csr(dd, addr); 11238 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK; 11239 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT; 11240 write_csr(dd, addr, reg); 11241 } 11242 11243 /* set the given per-VL dedicated limit */ 11244 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit) 11245 { 11246 u64 reg; 11247 u32 addr; 11248 11249 if (vl < TXE_NUM_DATA_VL) 11250 addr = SEND_CM_CREDIT_VL + (8 * vl); 11251 else 11252 addr = SEND_CM_CREDIT_VL15; 11253 11254 reg = read_csr(dd, addr); 11255 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK; 11256 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT; 11257 write_csr(dd, addr, reg); 11258 } 11259 11260 /* spin until the given per-VL status mask bits clear */ 11261 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask, 11262 const char *which) 11263 { 11264 unsigned long timeout; 11265 u64 reg; 11266 11267 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT); 11268 while (1) { 11269 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; 11270 11271 if (reg == 0) 11272 return; /* success */ 11273 if (time_after(jiffies, timeout)) 11274 break; /* timed out */ 11275 udelay(1); 11276 } 11277 11278 dd_dev_err(dd, 11279 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n", 11280 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); 11281 /* 11282 * If this occurs, it is likely there was a credit loss on the link. 11283 * The only recovery from that is a link bounce. 11284 */ 11285 dd_dev_err(dd, 11286 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n"); 11287 } 11288 11289 /* 11290 * The number of credits on the VLs may be changed while everything 11291 * is "live", but the following algorithm must be followed due to 11292 * how the hardware is actually implemented. In particular, 11293 * Return_Credit_Status[] is the only correct status check. 11294 * 11295 * if (reducing Global_Shared_Credit_Limit or any shared limit changing) 11296 * set Global_Shared_Credit_Limit = 0 11297 * use_all_vl = 1 11298 * mask0 = all VLs that are changing either dedicated or shared limits 11299 * set Shared_Limit[mask0] = 0 11300 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0 11301 * if (changing any dedicated limit) 11302 * mask1 = all VLs that are lowering dedicated limits 11303 * lower Dedicated_Limit[mask1] 11304 * spin until Return_Credit_Status[mask1] == 0 11305 * raise Dedicated_Limits 11306 * raise Shared_Limits 11307 * raise Global_Shared_Credit_Limit 11308 * 11309 * lower = if the new limit is lower, set the limit to the new value 11310 * raise = if the new limit is higher than the current value (may be changed 11311 * earlier in the algorithm), set the new limit to the new value 11312 */ 11313 int set_buffer_control(struct hfi1_pportdata *ppd, 11314 struct buffer_control *new_bc) 11315 { 11316 struct hfi1_devdata *dd = ppd->dd; 11317 u64 changing_mask, ld_mask, stat_mask; 11318 int change_count; 11319 int i, use_all_mask; 11320 int this_shared_changing; 11321 int vl_count = 0, ret; 11322 /* 11323 * A0: add the variable any_shared_limit_changing below and in the 11324 * algorithm above. If removing A0 support, it can be removed. 11325 */ 11326 int any_shared_limit_changing; 11327 struct buffer_control cur_bc; 11328 u8 changing[OPA_MAX_VLS]; 11329 u8 lowering_dedicated[OPA_MAX_VLS]; 11330 u16 cur_total; 11331 u32 new_total = 0; 11332 const u64 all_mask = 11333 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK 11334 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK 11335 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK 11336 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK 11337 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK 11338 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK 11339 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK 11340 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK 11341 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK; 11342 11343 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15) 11344 #define NUM_USABLE_VLS 16 /* look at VL15 and less */ 11345 11346 /* find the new total credits, do sanity check on unused VLs */ 11347 for (i = 0; i < OPA_MAX_VLS; i++) { 11348 if (valid_vl(i)) { 11349 new_total += be16_to_cpu(new_bc->vl[i].dedicated); 11350 continue; 11351 } 11352 nonzero_msg(dd, i, "dedicated", 11353 be16_to_cpu(new_bc->vl[i].dedicated)); 11354 nonzero_msg(dd, i, "shared", 11355 be16_to_cpu(new_bc->vl[i].shared)); 11356 new_bc->vl[i].dedicated = 0; 11357 new_bc->vl[i].shared = 0; 11358 } 11359 new_total += be16_to_cpu(new_bc->overall_shared_limit); 11360 11361 /* fetch the current values */ 11362 get_buffer_control(dd, &cur_bc, &cur_total); 11363 11364 /* 11365 * Create the masks we will use. 11366 */ 11367 memset(changing, 0, sizeof(changing)); 11368 memset(lowering_dedicated, 0, sizeof(lowering_dedicated)); 11369 /* 11370 * NOTE: Assumes that the individual VL bits are adjacent and in 11371 * increasing order 11372 */ 11373 stat_mask = 11374 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK; 11375 changing_mask = 0; 11376 ld_mask = 0; 11377 change_count = 0; 11378 any_shared_limit_changing = 0; 11379 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) { 11380 if (!valid_vl(i)) 11381 continue; 11382 this_shared_changing = new_bc->vl[i].shared 11383 != cur_bc.vl[i].shared; 11384 if (this_shared_changing) 11385 any_shared_limit_changing = 1; 11386 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated || 11387 this_shared_changing) { 11388 changing[i] = 1; 11389 changing_mask |= stat_mask; 11390 change_count++; 11391 } 11392 if (be16_to_cpu(new_bc->vl[i].dedicated) < 11393 be16_to_cpu(cur_bc.vl[i].dedicated)) { 11394 lowering_dedicated[i] = 1; 11395 ld_mask |= stat_mask; 11396 } 11397 } 11398 11399 /* bracket the credit change with a total adjustment */ 11400 if (new_total > cur_total) 11401 set_global_limit(dd, new_total); 11402 11403 /* 11404 * Start the credit change algorithm. 11405 */ 11406 use_all_mask = 0; 11407 if ((be16_to_cpu(new_bc->overall_shared_limit) < 11408 be16_to_cpu(cur_bc.overall_shared_limit)) || 11409 (is_ax(dd) && any_shared_limit_changing)) { 11410 set_global_shared(dd, 0); 11411 cur_bc.overall_shared_limit = 0; 11412 use_all_mask = 1; 11413 } 11414 11415 for (i = 0; i < NUM_USABLE_VLS; i++) { 11416 if (!valid_vl(i)) 11417 continue; 11418 11419 if (changing[i]) { 11420 set_vl_shared(dd, i, 0); 11421 cur_bc.vl[i].shared = 0; 11422 } 11423 } 11424 11425 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask, 11426 "shared"); 11427 11428 if (change_count > 0) { 11429 for (i = 0; i < NUM_USABLE_VLS; i++) { 11430 if (!valid_vl(i)) 11431 continue; 11432 11433 if (lowering_dedicated[i]) { 11434 set_vl_dedicated(dd, i, 11435 be16_to_cpu(new_bc-> 11436 vl[i].dedicated)); 11437 cur_bc.vl[i].dedicated = 11438 new_bc->vl[i].dedicated; 11439 } 11440 } 11441 11442 wait_for_vl_status_clear(dd, ld_mask, "dedicated"); 11443 11444 /* now raise all dedicated that are going up */ 11445 for (i = 0; i < NUM_USABLE_VLS; i++) { 11446 if (!valid_vl(i)) 11447 continue; 11448 11449 if (be16_to_cpu(new_bc->vl[i].dedicated) > 11450 be16_to_cpu(cur_bc.vl[i].dedicated)) 11451 set_vl_dedicated(dd, i, 11452 be16_to_cpu(new_bc-> 11453 vl[i].dedicated)); 11454 } 11455 } 11456 11457 /* next raise all shared that are going up */ 11458 for (i = 0; i < NUM_USABLE_VLS; i++) { 11459 if (!valid_vl(i)) 11460 continue; 11461 11462 if (be16_to_cpu(new_bc->vl[i].shared) > 11463 be16_to_cpu(cur_bc.vl[i].shared)) 11464 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared)); 11465 } 11466 11467 /* finally raise the global shared */ 11468 if (be16_to_cpu(new_bc->overall_shared_limit) > 11469 be16_to_cpu(cur_bc.overall_shared_limit)) 11470 set_global_shared(dd, 11471 be16_to_cpu(new_bc->overall_shared_limit)); 11472 11473 /* bracket the credit change with a total adjustment */ 11474 if (new_total < cur_total) 11475 set_global_limit(dd, new_total); 11476 11477 /* 11478 * Determine the actual number of operational VLS using the number of 11479 * dedicated and shared credits for each VL. 11480 */ 11481 if (change_count > 0) { 11482 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11483 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 || 11484 be16_to_cpu(new_bc->vl[i].shared) > 0) 11485 vl_count++; 11486 ppd->actual_vls_operational = vl_count; 11487 ret = sdma_map_init(dd, ppd->port - 1, vl_count ? 11488 ppd->actual_vls_operational : 11489 ppd->vls_operational, 11490 NULL); 11491 if (ret == 0) 11492 ret = pio_map_init(dd, ppd->port - 1, vl_count ? 11493 ppd->actual_vls_operational : 11494 ppd->vls_operational, NULL); 11495 if (ret) 11496 return ret; 11497 } 11498 return 0; 11499 } 11500 11501 /* 11502 * Read the given fabric manager table. Return the size of the 11503 * table (in bytes) on success, and a negative error code on 11504 * failure. 11505 */ 11506 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t) 11507 11508 { 11509 int size; 11510 struct vl_arb_cache *vlc; 11511 11512 switch (which) { 11513 case FM_TBL_VL_HIGH_ARB: 11514 size = 256; 11515 /* 11516 * OPA specifies 128 elements (of 2 bytes each), though 11517 * HFI supports only 16 elements in h/w. 11518 */ 11519 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11520 vl_arb_get_cache(vlc, t); 11521 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11522 break; 11523 case FM_TBL_VL_LOW_ARB: 11524 size = 256; 11525 /* 11526 * OPA specifies 128 elements (of 2 bytes each), though 11527 * HFI supports only 16 elements in h/w. 11528 */ 11529 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11530 vl_arb_get_cache(vlc, t); 11531 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11532 break; 11533 case FM_TBL_BUFFER_CONTROL: 11534 size = get_buffer_control(ppd->dd, t, NULL); 11535 break; 11536 case FM_TBL_SC2VLNT: 11537 size = get_sc2vlnt(ppd->dd, t); 11538 break; 11539 case FM_TBL_VL_PREEMPT_ELEMS: 11540 size = 256; 11541 /* OPA specifies 128 elements, of 2 bytes each */ 11542 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t); 11543 break; 11544 case FM_TBL_VL_PREEMPT_MATRIX: 11545 size = 256; 11546 /* 11547 * OPA specifies that this is the same size as the VL 11548 * arbitration tables (i.e., 256 bytes). 11549 */ 11550 break; 11551 default: 11552 return -EINVAL; 11553 } 11554 return size; 11555 } 11556 11557 /* 11558 * Write the given fabric manager table. 11559 */ 11560 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t) 11561 { 11562 int ret = 0; 11563 struct vl_arb_cache *vlc; 11564 11565 switch (which) { 11566 case FM_TBL_VL_HIGH_ARB: 11567 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11568 if (vl_arb_match_cache(vlc, t)) { 11569 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11570 break; 11571 } 11572 vl_arb_set_cache(vlc, t); 11573 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11574 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST, 11575 VL_ARB_HIGH_PRIO_TABLE_SIZE, t); 11576 break; 11577 case FM_TBL_VL_LOW_ARB: 11578 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11579 if (vl_arb_match_cache(vlc, t)) { 11580 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11581 break; 11582 } 11583 vl_arb_set_cache(vlc, t); 11584 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11585 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST, 11586 VL_ARB_LOW_PRIO_TABLE_SIZE, t); 11587 break; 11588 case FM_TBL_BUFFER_CONTROL: 11589 ret = set_buffer_control(ppd, t); 11590 break; 11591 case FM_TBL_SC2VLNT: 11592 set_sc2vlnt(ppd->dd, t); 11593 break; 11594 default: 11595 ret = -EINVAL; 11596 } 11597 return ret; 11598 } 11599 11600 /* 11601 * Disable all data VLs. 11602 * 11603 * Return 0 if disabled, non-zero if the VLs cannot be disabled. 11604 */ 11605 static int disable_data_vls(struct hfi1_devdata *dd) 11606 { 11607 if (is_ax(dd)) 11608 return 1; 11609 11610 pio_send_control(dd, PSC_DATA_VL_DISABLE); 11611 11612 return 0; 11613 } 11614 11615 /* 11616 * open_fill_data_vls() - the counterpart to stop_drain_data_vls(). 11617 * Just re-enables all data VLs (the "fill" part happens 11618 * automatically - the name was chosen for symmetry with 11619 * stop_drain_data_vls()). 11620 * 11621 * Return 0 if successful, non-zero if the VLs cannot be enabled. 11622 */ 11623 int open_fill_data_vls(struct hfi1_devdata *dd) 11624 { 11625 if (is_ax(dd)) 11626 return 1; 11627 11628 pio_send_control(dd, PSC_DATA_VL_ENABLE); 11629 11630 return 0; 11631 } 11632 11633 /* 11634 * drain_data_vls() - assumes that disable_data_vls() has been called, 11635 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA 11636 * engines to drop to 0. 11637 */ 11638 static void drain_data_vls(struct hfi1_devdata *dd) 11639 { 11640 sc_wait(dd); 11641 sdma_wait(dd); 11642 pause_for_credit_return(dd); 11643 } 11644 11645 /* 11646 * stop_drain_data_vls() - disable, then drain all per-VL fifos. 11647 * 11648 * Use open_fill_data_vls() to resume using data VLs. This pair is 11649 * meant to be used like this: 11650 * 11651 * stop_drain_data_vls(dd); 11652 * // do things with per-VL resources 11653 * open_fill_data_vls(dd); 11654 */ 11655 int stop_drain_data_vls(struct hfi1_devdata *dd) 11656 { 11657 int ret; 11658 11659 ret = disable_data_vls(dd); 11660 if (ret == 0) 11661 drain_data_vls(dd); 11662 11663 return ret; 11664 } 11665 11666 /* 11667 * Convert a nanosecond time to a cclock count. No matter how slow 11668 * the cclock, a non-zero ns will always have a non-zero result. 11669 */ 11670 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns) 11671 { 11672 u32 cclocks; 11673 11674 if (dd->icode == ICODE_FPGA_EMULATION) 11675 cclocks = (ns * 1000) / FPGA_CCLOCK_PS; 11676 else /* simulation pretends to be ASIC */ 11677 cclocks = (ns * 1000) / ASIC_CCLOCK_PS; 11678 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */ 11679 cclocks = 1; 11680 return cclocks; 11681 } 11682 11683 /* 11684 * Convert a cclock count to nanoseconds. Not matter how slow 11685 * the cclock, a non-zero cclocks will always have a non-zero result. 11686 */ 11687 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks) 11688 { 11689 u32 ns; 11690 11691 if (dd->icode == ICODE_FPGA_EMULATION) 11692 ns = (cclocks * FPGA_CCLOCK_PS) / 1000; 11693 else /* simulation pretends to be ASIC */ 11694 ns = (cclocks * ASIC_CCLOCK_PS) / 1000; 11695 if (cclocks && !ns) 11696 ns = 1; 11697 return ns; 11698 } 11699 11700 /* 11701 * Dynamically adjust the receive interrupt timeout for a context based on 11702 * incoming packet rate. 11703 * 11704 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero. 11705 */ 11706 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts) 11707 { 11708 struct hfi1_devdata *dd = rcd->dd; 11709 u32 timeout = rcd->rcvavail_timeout; 11710 11711 /* 11712 * This algorithm doubles or halves the timeout depending on whether 11713 * the number of packets received in this interrupt were less than or 11714 * greater equal the interrupt count. 11715 * 11716 * The calculations below do not allow a steady state to be achieved. 11717 * Only at the endpoints it is possible to have an unchanging 11718 * timeout. 11719 */ 11720 if (npkts < rcv_intr_count) { 11721 /* 11722 * Not enough packets arrived before the timeout, adjust 11723 * timeout downward. 11724 */ 11725 if (timeout < 2) /* already at minimum? */ 11726 return; 11727 timeout >>= 1; 11728 } else { 11729 /* 11730 * More than enough packets arrived before the timeout, adjust 11731 * timeout upward. 11732 */ 11733 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */ 11734 return; 11735 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr); 11736 } 11737 11738 rcd->rcvavail_timeout = timeout; 11739 /* 11740 * timeout cannot be larger than rcv_intr_timeout_csr which has already 11741 * been verified to be in range 11742 */ 11743 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT, 11744 (u64)timeout << 11745 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11746 } 11747 11748 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, 11749 u32 intr_adjust, u32 npkts) 11750 { 11751 struct hfi1_devdata *dd = rcd->dd; 11752 u64 reg; 11753 u32 ctxt = rcd->ctxt; 11754 11755 /* 11756 * Need to write timeout register before updating RcvHdrHead to ensure 11757 * that a new value is used when the HW decides to restart counting. 11758 */ 11759 if (intr_adjust) 11760 adjust_rcv_timeout(rcd, npkts); 11761 if (updegr) { 11762 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK) 11763 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT; 11764 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg); 11765 } 11766 mmiowb(); 11767 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) | 11768 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK) 11769 << RCV_HDR_HEAD_HEAD_SHIFT); 11770 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11771 mmiowb(); 11772 } 11773 11774 u32 hdrqempty(struct hfi1_ctxtdata *rcd) 11775 { 11776 u32 head, tail; 11777 11778 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD) 11779 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT; 11780 11781 if (rcd->rcvhdrtail_kvaddr) 11782 tail = get_rcvhdrtail(rcd); 11783 else 11784 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 11785 11786 return head == tail; 11787 } 11788 11789 /* 11790 * Context Control and Receive Array encoding for buffer size: 11791 * 0x0 invalid 11792 * 0x1 4 KB 11793 * 0x2 8 KB 11794 * 0x3 16 KB 11795 * 0x4 32 KB 11796 * 0x5 64 KB 11797 * 0x6 128 KB 11798 * 0x7 256 KB 11799 * 0x8 512 KB (Receive Array only) 11800 * 0x9 1 MB (Receive Array only) 11801 * 0xa 2 MB (Receive Array only) 11802 * 11803 * 0xB-0xF - reserved (Receive Array only) 11804 * 11805 * 11806 * This routine assumes that the value has already been sanity checked. 11807 */ 11808 static u32 encoded_size(u32 size) 11809 { 11810 switch (size) { 11811 case 4 * 1024: return 0x1; 11812 case 8 * 1024: return 0x2; 11813 case 16 * 1024: return 0x3; 11814 case 32 * 1024: return 0x4; 11815 case 64 * 1024: return 0x5; 11816 case 128 * 1024: return 0x6; 11817 case 256 * 1024: return 0x7; 11818 case 512 * 1024: return 0x8; 11819 case 1 * 1024 * 1024: return 0x9; 11820 case 2 * 1024 * 1024: return 0xa; 11821 } 11822 return 0x1; /* if invalid, go with the minimum size */ 11823 } 11824 11825 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, 11826 struct hfi1_ctxtdata *rcd) 11827 { 11828 u64 rcvctrl, reg; 11829 int did_enable = 0; 11830 u16 ctxt; 11831 11832 if (!rcd) 11833 return; 11834 11835 ctxt = rcd->ctxt; 11836 11837 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op); 11838 11839 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL); 11840 /* if the context already enabled, don't do the extra steps */ 11841 if ((op & HFI1_RCVCTRL_CTXT_ENB) && 11842 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) { 11843 /* reset the tail and hdr addresses, and sequence count */ 11844 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR, 11845 rcd->rcvhdrq_dma); 11846 if (rcd->rcvhdrtail_kvaddr) 11847 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11848 rcd->rcvhdrqtailaddr_dma); 11849 rcd->seq_cnt = 1; 11850 11851 /* reset the cached receive header queue head value */ 11852 rcd->head = 0; 11853 11854 /* 11855 * Zero the receive header queue so we don't get false 11856 * positives when checking the sequence number. The 11857 * sequence numbers could land exactly on the same spot. 11858 * E.g. a rcd restart before the receive header wrapped. 11859 */ 11860 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size); 11861 11862 /* starting timeout */ 11863 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr; 11864 11865 /* enable the context */ 11866 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK; 11867 11868 /* clean the egr buffer size first */ 11869 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 11870 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size) 11871 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK) 11872 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT; 11873 11874 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */ 11875 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0); 11876 did_enable = 1; 11877 11878 /* zero RcvEgrIndexHead */ 11879 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0); 11880 11881 /* set eager count and base index */ 11882 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT) 11883 & RCV_EGR_CTRL_EGR_CNT_MASK) 11884 << RCV_EGR_CTRL_EGR_CNT_SHIFT) | 11885 (((rcd->eager_base >> RCV_SHIFT) 11886 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK) 11887 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT); 11888 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg); 11889 11890 /* 11891 * Set TID (expected) count and base index. 11892 * rcd->expected_count is set to individual RcvArray entries, 11893 * not pairs, and the CSR takes a pair-count in groups of 11894 * four, so divide by 8. 11895 */ 11896 reg = (((rcd->expected_count >> RCV_SHIFT) 11897 & RCV_TID_CTRL_TID_PAIR_CNT_MASK) 11898 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) | 11899 (((rcd->expected_base >> RCV_SHIFT) 11900 & RCV_TID_CTRL_TID_BASE_INDEX_MASK) 11901 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT); 11902 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg); 11903 if (ctxt == HFI1_CTRL_CTXT) 11904 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); 11905 } 11906 if (op & HFI1_RCVCTRL_CTXT_DIS) { 11907 write_csr(dd, RCV_VL15, 0); 11908 /* 11909 * When receive context is being disabled turn on tail 11910 * update with a dummy tail address and then disable 11911 * receive context. 11912 */ 11913 if (dd->rcvhdrtail_dummy_dma) { 11914 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11915 dd->rcvhdrtail_dummy_dma); 11916 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */ 11917 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11918 } 11919 11920 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK; 11921 } 11922 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB) 11923 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 11924 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS) 11925 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 11926 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && rcd->rcvhdrtail_kvaddr) 11927 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11928 if (op & HFI1_RCVCTRL_TAILUPD_DIS) { 11929 /* See comment on RcvCtxtCtrl.TailUpd above */ 11930 if (!(op & HFI1_RCVCTRL_CTXT_DIS)) 11931 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11932 } 11933 if (op & HFI1_RCVCTRL_TIDFLOW_ENB) 11934 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 11935 if (op & HFI1_RCVCTRL_TIDFLOW_DIS) 11936 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 11937 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) { 11938 /* 11939 * In one-packet-per-eager mode, the size comes from 11940 * the RcvArray entry. 11941 */ 11942 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 11943 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 11944 } 11945 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS) 11946 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 11947 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB) 11948 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 11949 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS) 11950 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 11951 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB) 11952 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 11953 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS) 11954 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 11955 rcd->rcvctrl = rcvctrl; 11956 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl); 11957 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl); 11958 11959 /* work around sticky RcvCtxtStatus.BlockedRHQFull */ 11960 if (did_enable && 11961 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) { 11962 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 11963 if (reg != 0) { 11964 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n", 11965 ctxt, reg); 11966 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 11967 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10); 11968 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00); 11969 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 11970 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 11971 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n", 11972 ctxt, reg, reg == 0 ? "not" : "still"); 11973 } 11974 } 11975 11976 if (did_enable) { 11977 /* 11978 * The interrupt timeout and count must be set after 11979 * the context is enabled to take effect. 11980 */ 11981 /* set interrupt timeout */ 11982 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT, 11983 (u64)rcd->rcvavail_timeout << 11984 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11985 11986 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */ 11987 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT; 11988 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11989 } 11990 11991 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS)) 11992 /* 11993 * If the context has been disabled and the Tail Update has 11994 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address 11995 * so it doesn't contain an address that is invalid. 11996 */ 11997 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11998 dd->rcvhdrtail_dummy_dma); 11999 } 12000 12001 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp) 12002 { 12003 int ret; 12004 u64 val = 0; 12005 12006 if (namep) { 12007 ret = dd->cntrnameslen; 12008 *namep = dd->cntrnames; 12009 } else { 12010 const struct cntr_entry *entry; 12011 int i, j; 12012 12013 ret = (dd->ndevcntrs) * sizeof(u64); 12014 12015 /* Get the start of the block of counters */ 12016 *cntrp = dd->cntrs; 12017 12018 /* 12019 * Now go and fill in each counter in the block. 12020 */ 12021 for (i = 0; i < DEV_CNTR_LAST; i++) { 12022 entry = &dev_cntrs[i]; 12023 hfi1_cdbg(CNTR, "reading %s", entry->name); 12024 if (entry->flags & CNTR_DISABLED) { 12025 /* Nothing */ 12026 hfi1_cdbg(CNTR, "\tDisabled\n"); 12027 } else { 12028 if (entry->flags & CNTR_VL) { 12029 hfi1_cdbg(CNTR, "\tPer VL\n"); 12030 for (j = 0; j < C_VL_COUNT; j++) { 12031 val = entry->rw_cntr(entry, 12032 dd, j, 12033 CNTR_MODE_R, 12034 0); 12035 hfi1_cdbg( 12036 CNTR, 12037 "\t\tRead 0x%llx for %d\n", 12038 val, j); 12039 dd->cntrs[entry->offset + j] = 12040 val; 12041 } 12042 } else if (entry->flags & CNTR_SDMA) { 12043 hfi1_cdbg(CNTR, 12044 "\t Per SDMA Engine\n"); 12045 for (j = 0; j < dd->chip_sdma_engines; 12046 j++) { 12047 val = 12048 entry->rw_cntr(entry, dd, j, 12049 CNTR_MODE_R, 0); 12050 hfi1_cdbg(CNTR, 12051 "\t\tRead 0x%llx for %d\n", 12052 val, j); 12053 dd->cntrs[entry->offset + j] = 12054 val; 12055 } 12056 } else { 12057 val = entry->rw_cntr(entry, dd, 12058 CNTR_INVALID_VL, 12059 CNTR_MODE_R, 0); 12060 dd->cntrs[entry->offset] = val; 12061 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12062 } 12063 } 12064 } 12065 } 12066 return ret; 12067 } 12068 12069 /* 12070 * Used by sysfs to create files for hfi stats to read 12071 */ 12072 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp) 12073 { 12074 int ret; 12075 u64 val = 0; 12076 12077 if (namep) { 12078 ret = ppd->dd->portcntrnameslen; 12079 *namep = ppd->dd->portcntrnames; 12080 } else { 12081 const struct cntr_entry *entry; 12082 int i, j; 12083 12084 ret = ppd->dd->nportcntrs * sizeof(u64); 12085 *cntrp = ppd->cntrs; 12086 12087 for (i = 0; i < PORT_CNTR_LAST; i++) { 12088 entry = &port_cntrs[i]; 12089 hfi1_cdbg(CNTR, "reading %s", entry->name); 12090 if (entry->flags & CNTR_DISABLED) { 12091 /* Nothing */ 12092 hfi1_cdbg(CNTR, "\tDisabled\n"); 12093 continue; 12094 } 12095 12096 if (entry->flags & CNTR_VL) { 12097 hfi1_cdbg(CNTR, "\tPer VL"); 12098 for (j = 0; j < C_VL_COUNT; j++) { 12099 val = entry->rw_cntr(entry, ppd, j, 12100 CNTR_MODE_R, 12101 0); 12102 hfi1_cdbg( 12103 CNTR, 12104 "\t\tRead 0x%llx for %d", 12105 val, j); 12106 ppd->cntrs[entry->offset + j] = val; 12107 } 12108 } else { 12109 val = entry->rw_cntr(entry, ppd, 12110 CNTR_INVALID_VL, 12111 CNTR_MODE_R, 12112 0); 12113 ppd->cntrs[entry->offset] = val; 12114 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12115 } 12116 } 12117 } 12118 return ret; 12119 } 12120 12121 static void free_cntrs(struct hfi1_devdata *dd) 12122 { 12123 struct hfi1_pportdata *ppd; 12124 int i; 12125 12126 if (dd->synth_stats_timer.function) 12127 del_timer_sync(&dd->synth_stats_timer); 12128 ppd = (struct hfi1_pportdata *)(dd + 1); 12129 for (i = 0; i < dd->num_pports; i++, ppd++) { 12130 kfree(ppd->cntrs); 12131 kfree(ppd->scntrs); 12132 free_percpu(ppd->ibport_data.rvp.rc_acks); 12133 free_percpu(ppd->ibport_data.rvp.rc_qacks); 12134 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp); 12135 ppd->cntrs = NULL; 12136 ppd->scntrs = NULL; 12137 ppd->ibport_data.rvp.rc_acks = NULL; 12138 ppd->ibport_data.rvp.rc_qacks = NULL; 12139 ppd->ibport_data.rvp.rc_delayed_comp = NULL; 12140 } 12141 kfree(dd->portcntrnames); 12142 dd->portcntrnames = NULL; 12143 kfree(dd->cntrs); 12144 dd->cntrs = NULL; 12145 kfree(dd->scntrs); 12146 dd->scntrs = NULL; 12147 kfree(dd->cntrnames); 12148 dd->cntrnames = NULL; 12149 if (dd->update_cntr_wq) { 12150 destroy_workqueue(dd->update_cntr_wq); 12151 dd->update_cntr_wq = NULL; 12152 } 12153 } 12154 12155 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry, 12156 u64 *psval, void *context, int vl) 12157 { 12158 u64 val; 12159 u64 sval = *psval; 12160 12161 if (entry->flags & CNTR_DISABLED) { 12162 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12163 return 0; 12164 } 12165 12166 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12167 12168 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0); 12169 12170 /* If its a synthetic counter there is more work we need to do */ 12171 if (entry->flags & CNTR_SYNTH) { 12172 if (sval == CNTR_MAX) { 12173 /* No need to read already saturated */ 12174 return CNTR_MAX; 12175 } 12176 12177 if (entry->flags & CNTR_32BIT) { 12178 /* 32bit counters can wrap multiple times */ 12179 u64 upper = sval >> 32; 12180 u64 lower = (sval << 32) >> 32; 12181 12182 if (lower > val) { /* hw wrapped */ 12183 if (upper == CNTR_32BIT_MAX) 12184 val = CNTR_MAX; 12185 else 12186 upper++; 12187 } 12188 12189 if (val != CNTR_MAX) 12190 val = (upper << 32) | val; 12191 12192 } else { 12193 /* If we rolled we are saturated */ 12194 if ((val < sval) || (val > CNTR_MAX)) 12195 val = CNTR_MAX; 12196 } 12197 } 12198 12199 *psval = val; 12200 12201 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12202 12203 return val; 12204 } 12205 12206 static u64 write_dev_port_cntr(struct hfi1_devdata *dd, 12207 struct cntr_entry *entry, 12208 u64 *psval, void *context, int vl, u64 data) 12209 { 12210 u64 val; 12211 12212 if (entry->flags & CNTR_DISABLED) { 12213 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12214 return 0; 12215 } 12216 12217 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12218 12219 if (entry->flags & CNTR_SYNTH) { 12220 *psval = data; 12221 if (entry->flags & CNTR_32BIT) { 12222 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12223 (data << 32) >> 32); 12224 val = data; /* return the full 64bit value */ 12225 } else { 12226 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12227 data); 12228 } 12229 } else { 12230 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data); 12231 } 12232 12233 *psval = val; 12234 12235 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12236 12237 return val; 12238 } 12239 12240 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl) 12241 { 12242 struct cntr_entry *entry; 12243 u64 *sval; 12244 12245 entry = &dev_cntrs[index]; 12246 sval = dd->scntrs + entry->offset; 12247 12248 if (vl != CNTR_INVALID_VL) 12249 sval += vl; 12250 12251 return read_dev_port_cntr(dd, entry, sval, dd, vl); 12252 } 12253 12254 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data) 12255 { 12256 struct cntr_entry *entry; 12257 u64 *sval; 12258 12259 entry = &dev_cntrs[index]; 12260 sval = dd->scntrs + entry->offset; 12261 12262 if (vl != CNTR_INVALID_VL) 12263 sval += vl; 12264 12265 return write_dev_port_cntr(dd, entry, sval, dd, vl, data); 12266 } 12267 12268 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl) 12269 { 12270 struct cntr_entry *entry; 12271 u64 *sval; 12272 12273 entry = &port_cntrs[index]; 12274 sval = ppd->scntrs + entry->offset; 12275 12276 if (vl != CNTR_INVALID_VL) 12277 sval += vl; 12278 12279 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12280 (index <= C_RCV_HDR_OVF_LAST)) { 12281 /* We do not want to bother for disabled contexts */ 12282 return 0; 12283 } 12284 12285 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl); 12286 } 12287 12288 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data) 12289 { 12290 struct cntr_entry *entry; 12291 u64 *sval; 12292 12293 entry = &port_cntrs[index]; 12294 sval = ppd->scntrs + entry->offset; 12295 12296 if (vl != CNTR_INVALID_VL) 12297 sval += vl; 12298 12299 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12300 (index <= C_RCV_HDR_OVF_LAST)) { 12301 /* We do not want to bother for disabled contexts */ 12302 return 0; 12303 } 12304 12305 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data); 12306 } 12307 12308 static void do_update_synth_timer(struct work_struct *work) 12309 { 12310 u64 cur_tx; 12311 u64 cur_rx; 12312 u64 total_flits; 12313 u8 update = 0; 12314 int i, j, vl; 12315 struct hfi1_pportdata *ppd; 12316 struct cntr_entry *entry; 12317 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata, 12318 update_cntr_work); 12319 12320 /* 12321 * Rather than keep beating on the CSRs pick a minimal set that we can 12322 * check to watch for potential roll over. We can do this by looking at 12323 * the number of flits sent/recv. If the total flits exceeds 32bits then 12324 * we have to iterate all the counters and update. 12325 */ 12326 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12327 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12328 12329 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12330 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12331 12332 hfi1_cdbg( 12333 CNTR, 12334 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n", 12335 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx); 12336 12337 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) { 12338 /* 12339 * May not be strictly necessary to update but it won't hurt and 12340 * simplifies the logic here. 12341 */ 12342 update = 1; 12343 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating", 12344 dd->unit); 12345 } else { 12346 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx); 12347 hfi1_cdbg(CNTR, 12348 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit, 12349 total_flits, (u64)CNTR_32BIT_MAX); 12350 if (total_flits >= CNTR_32BIT_MAX) { 12351 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating", 12352 dd->unit); 12353 update = 1; 12354 } 12355 } 12356 12357 if (update) { 12358 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit); 12359 for (i = 0; i < DEV_CNTR_LAST; i++) { 12360 entry = &dev_cntrs[i]; 12361 if (entry->flags & CNTR_VL) { 12362 for (vl = 0; vl < C_VL_COUNT; vl++) 12363 read_dev_cntr(dd, i, vl); 12364 } else { 12365 read_dev_cntr(dd, i, CNTR_INVALID_VL); 12366 } 12367 } 12368 ppd = (struct hfi1_pportdata *)(dd + 1); 12369 for (i = 0; i < dd->num_pports; i++, ppd++) { 12370 for (j = 0; j < PORT_CNTR_LAST; j++) { 12371 entry = &port_cntrs[j]; 12372 if (entry->flags & CNTR_VL) { 12373 for (vl = 0; vl < C_VL_COUNT; vl++) 12374 read_port_cntr(ppd, j, vl); 12375 } else { 12376 read_port_cntr(ppd, j, CNTR_INVALID_VL); 12377 } 12378 } 12379 } 12380 12381 /* 12382 * We want the value in the register. The goal is to keep track 12383 * of the number of "ticks" not the counter value. In other 12384 * words if the register rolls we want to notice it and go ahead 12385 * and force an update. 12386 */ 12387 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12388 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12389 CNTR_MODE_R, 0); 12390 12391 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12392 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12393 CNTR_MODE_R, 0); 12394 12395 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx", 12396 dd->unit, dd->last_tx, dd->last_rx); 12397 12398 } else { 12399 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit); 12400 } 12401 } 12402 12403 static void update_synth_timer(struct timer_list *t) 12404 { 12405 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer); 12406 12407 queue_work(dd->update_cntr_wq, &dd->update_cntr_work); 12408 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12409 } 12410 12411 #define C_MAX_NAME 16 /* 15 chars + one for /0 */ 12412 static int init_cntrs(struct hfi1_devdata *dd) 12413 { 12414 int i, rcv_ctxts, j; 12415 size_t sz; 12416 char *p; 12417 char name[C_MAX_NAME]; 12418 struct hfi1_pportdata *ppd; 12419 const char *bit_type_32 = ",32"; 12420 const int bit_type_32_sz = strlen(bit_type_32); 12421 12422 /* set up the stats timer; the add_timer is done at the end */ 12423 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0); 12424 12425 /***********************/ 12426 /* per device counters */ 12427 /***********************/ 12428 12429 /* size names and determine how many we have*/ 12430 dd->ndevcntrs = 0; 12431 sz = 0; 12432 12433 for (i = 0; i < DEV_CNTR_LAST; i++) { 12434 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12435 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name); 12436 continue; 12437 } 12438 12439 if (dev_cntrs[i].flags & CNTR_VL) { 12440 dev_cntrs[i].offset = dd->ndevcntrs; 12441 for (j = 0; j < C_VL_COUNT; j++) { 12442 snprintf(name, C_MAX_NAME, "%s%d", 12443 dev_cntrs[i].name, vl_from_idx(j)); 12444 sz += strlen(name); 12445 /* Add ",32" for 32-bit counters */ 12446 if (dev_cntrs[i].flags & CNTR_32BIT) 12447 sz += bit_type_32_sz; 12448 sz++; 12449 dd->ndevcntrs++; 12450 } 12451 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12452 dev_cntrs[i].offset = dd->ndevcntrs; 12453 for (j = 0; j < dd->chip_sdma_engines; j++) { 12454 snprintf(name, C_MAX_NAME, "%s%d", 12455 dev_cntrs[i].name, j); 12456 sz += strlen(name); 12457 /* Add ",32" for 32-bit counters */ 12458 if (dev_cntrs[i].flags & CNTR_32BIT) 12459 sz += bit_type_32_sz; 12460 sz++; 12461 dd->ndevcntrs++; 12462 } 12463 } else { 12464 /* +1 for newline. */ 12465 sz += strlen(dev_cntrs[i].name) + 1; 12466 /* Add ",32" for 32-bit counters */ 12467 if (dev_cntrs[i].flags & CNTR_32BIT) 12468 sz += bit_type_32_sz; 12469 dev_cntrs[i].offset = dd->ndevcntrs; 12470 dd->ndevcntrs++; 12471 } 12472 } 12473 12474 /* allocate space for the counter values */ 12475 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12476 if (!dd->cntrs) 12477 goto bail; 12478 12479 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12480 if (!dd->scntrs) 12481 goto bail; 12482 12483 /* allocate space for the counter names */ 12484 dd->cntrnameslen = sz; 12485 dd->cntrnames = kmalloc(sz, GFP_KERNEL); 12486 if (!dd->cntrnames) 12487 goto bail; 12488 12489 /* fill in the names */ 12490 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) { 12491 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12492 /* Nothing */ 12493 } else if (dev_cntrs[i].flags & CNTR_VL) { 12494 for (j = 0; j < C_VL_COUNT; j++) { 12495 snprintf(name, C_MAX_NAME, "%s%d", 12496 dev_cntrs[i].name, 12497 vl_from_idx(j)); 12498 memcpy(p, name, strlen(name)); 12499 p += strlen(name); 12500 12501 /* Counter is 32 bits */ 12502 if (dev_cntrs[i].flags & CNTR_32BIT) { 12503 memcpy(p, bit_type_32, bit_type_32_sz); 12504 p += bit_type_32_sz; 12505 } 12506 12507 *p++ = '\n'; 12508 } 12509 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12510 for (j = 0; j < dd->chip_sdma_engines; j++) { 12511 snprintf(name, C_MAX_NAME, "%s%d", 12512 dev_cntrs[i].name, j); 12513 memcpy(p, name, strlen(name)); 12514 p += strlen(name); 12515 12516 /* Counter is 32 bits */ 12517 if (dev_cntrs[i].flags & CNTR_32BIT) { 12518 memcpy(p, bit_type_32, bit_type_32_sz); 12519 p += bit_type_32_sz; 12520 } 12521 12522 *p++ = '\n'; 12523 } 12524 } else { 12525 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name)); 12526 p += strlen(dev_cntrs[i].name); 12527 12528 /* Counter is 32 bits */ 12529 if (dev_cntrs[i].flags & CNTR_32BIT) { 12530 memcpy(p, bit_type_32, bit_type_32_sz); 12531 p += bit_type_32_sz; 12532 } 12533 12534 *p++ = '\n'; 12535 } 12536 } 12537 12538 /*********************/ 12539 /* per port counters */ 12540 /*********************/ 12541 12542 /* 12543 * Go through the counters for the overflows and disable the ones we 12544 * don't need. This varies based on platform so we need to do it 12545 * dynamically here. 12546 */ 12547 rcv_ctxts = dd->num_rcv_contexts; 12548 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts; 12549 i <= C_RCV_HDR_OVF_LAST; i++) { 12550 port_cntrs[i].flags |= CNTR_DISABLED; 12551 } 12552 12553 /* size port counter names and determine how many we have*/ 12554 sz = 0; 12555 dd->nportcntrs = 0; 12556 for (i = 0; i < PORT_CNTR_LAST; i++) { 12557 if (port_cntrs[i].flags & CNTR_DISABLED) { 12558 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name); 12559 continue; 12560 } 12561 12562 if (port_cntrs[i].flags & CNTR_VL) { 12563 port_cntrs[i].offset = dd->nportcntrs; 12564 for (j = 0; j < C_VL_COUNT; j++) { 12565 snprintf(name, C_MAX_NAME, "%s%d", 12566 port_cntrs[i].name, vl_from_idx(j)); 12567 sz += strlen(name); 12568 /* Add ",32" for 32-bit counters */ 12569 if (port_cntrs[i].flags & CNTR_32BIT) 12570 sz += bit_type_32_sz; 12571 sz++; 12572 dd->nportcntrs++; 12573 } 12574 } else { 12575 /* +1 for newline */ 12576 sz += strlen(port_cntrs[i].name) + 1; 12577 /* Add ",32" for 32-bit counters */ 12578 if (port_cntrs[i].flags & CNTR_32BIT) 12579 sz += bit_type_32_sz; 12580 port_cntrs[i].offset = dd->nportcntrs; 12581 dd->nportcntrs++; 12582 } 12583 } 12584 12585 /* allocate space for the counter names */ 12586 dd->portcntrnameslen = sz; 12587 dd->portcntrnames = kmalloc(sz, GFP_KERNEL); 12588 if (!dd->portcntrnames) 12589 goto bail; 12590 12591 /* fill in port cntr names */ 12592 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) { 12593 if (port_cntrs[i].flags & CNTR_DISABLED) 12594 continue; 12595 12596 if (port_cntrs[i].flags & CNTR_VL) { 12597 for (j = 0; j < C_VL_COUNT; j++) { 12598 snprintf(name, C_MAX_NAME, "%s%d", 12599 port_cntrs[i].name, vl_from_idx(j)); 12600 memcpy(p, name, strlen(name)); 12601 p += strlen(name); 12602 12603 /* Counter is 32 bits */ 12604 if (port_cntrs[i].flags & CNTR_32BIT) { 12605 memcpy(p, bit_type_32, bit_type_32_sz); 12606 p += bit_type_32_sz; 12607 } 12608 12609 *p++ = '\n'; 12610 } 12611 } else { 12612 memcpy(p, port_cntrs[i].name, 12613 strlen(port_cntrs[i].name)); 12614 p += strlen(port_cntrs[i].name); 12615 12616 /* Counter is 32 bits */ 12617 if (port_cntrs[i].flags & CNTR_32BIT) { 12618 memcpy(p, bit_type_32, bit_type_32_sz); 12619 p += bit_type_32_sz; 12620 } 12621 12622 *p++ = '\n'; 12623 } 12624 } 12625 12626 /* allocate per port storage for counter values */ 12627 ppd = (struct hfi1_pportdata *)(dd + 1); 12628 for (i = 0; i < dd->num_pports; i++, ppd++) { 12629 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12630 if (!ppd->cntrs) 12631 goto bail; 12632 12633 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12634 if (!ppd->scntrs) 12635 goto bail; 12636 } 12637 12638 /* CPU counters need to be allocated and zeroed */ 12639 if (init_cpu_counters(dd)) 12640 goto bail; 12641 12642 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d", 12643 WQ_MEM_RECLAIM, dd->unit); 12644 if (!dd->update_cntr_wq) 12645 goto bail; 12646 12647 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer); 12648 12649 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12650 return 0; 12651 bail: 12652 free_cntrs(dd); 12653 return -ENOMEM; 12654 } 12655 12656 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate) 12657 { 12658 switch (chip_lstate) { 12659 default: 12660 dd_dev_err(dd, 12661 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n", 12662 chip_lstate); 12663 /* fall through */ 12664 case LSTATE_DOWN: 12665 return IB_PORT_DOWN; 12666 case LSTATE_INIT: 12667 return IB_PORT_INIT; 12668 case LSTATE_ARMED: 12669 return IB_PORT_ARMED; 12670 case LSTATE_ACTIVE: 12671 return IB_PORT_ACTIVE; 12672 } 12673 } 12674 12675 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate) 12676 { 12677 /* look at the HFI meta-states only */ 12678 switch (chip_pstate & 0xf0) { 12679 default: 12680 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n", 12681 chip_pstate); 12682 /* fall through */ 12683 case PLS_DISABLED: 12684 return IB_PORTPHYSSTATE_DISABLED; 12685 case PLS_OFFLINE: 12686 return OPA_PORTPHYSSTATE_OFFLINE; 12687 case PLS_POLLING: 12688 return IB_PORTPHYSSTATE_POLLING; 12689 case PLS_CONFIGPHY: 12690 return IB_PORTPHYSSTATE_TRAINING; 12691 case PLS_LINKUP: 12692 return IB_PORTPHYSSTATE_LINKUP; 12693 case PLS_PHYTEST: 12694 return IB_PORTPHYSSTATE_PHY_TEST; 12695 } 12696 } 12697 12698 /* return the OPA port logical state name */ 12699 const char *opa_lstate_name(u32 lstate) 12700 { 12701 static const char * const port_logical_names[] = { 12702 "PORT_NOP", 12703 "PORT_DOWN", 12704 "PORT_INIT", 12705 "PORT_ARMED", 12706 "PORT_ACTIVE", 12707 "PORT_ACTIVE_DEFER", 12708 }; 12709 if (lstate < ARRAY_SIZE(port_logical_names)) 12710 return port_logical_names[lstate]; 12711 return "unknown"; 12712 } 12713 12714 /* return the OPA port physical state name */ 12715 const char *opa_pstate_name(u32 pstate) 12716 { 12717 static const char * const port_physical_names[] = { 12718 "PHYS_NOP", 12719 "reserved1", 12720 "PHYS_POLL", 12721 "PHYS_DISABLED", 12722 "PHYS_TRAINING", 12723 "PHYS_LINKUP", 12724 "PHYS_LINK_ERR_RECOVER", 12725 "PHYS_PHY_TEST", 12726 "reserved8", 12727 "PHYS_OFFLINE", 12728 "PHYS_GANGED", 12729 "PHYS_TEST", 12730 }; 12731 if (pstate < ARRAY_SIZE(port_physical_names)) 12732 return port_physical_names[pstate]; 12733 return "unknown"; 12734 } 12735 12736 /** 12737 * update_statusp - Update userspace status flag 12738 * @ppd: Port data structure 12739 * @state: port state information 12740 * 12741 * Actual port status is determined by the host_link_state value 12742 * in the ppd. 12743 * 12744 * host_link_state MUST be updated before updating the user space 12745 * statusp. 12746 */ 12747 static void update_statusp(struct hfi1_pportdata *ppd, u32 state) 12748 { 12749 /* 12750 * Set port status flags in the page mapped into userspace 12751 * memory. Do it here to ensure a reliable state - this is 12752 * the only function called by all state handling code. 12753 * Always set the flags due to the fact that the cache value 12754 * might have been changed explicitly outside of this 12755 * function. 12756 */ 12757 if (ppd->statusp) { 12758 switch (state) { 12759 case IB_PORT_DOWN: 12760 case IB_PORT_INIT: 12761 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 12762 HFI1_STATUS_IB_READY); 12763 break; 12764 case IB_PORT_ARMED: 12765 *ppd->statusp |= HFI1_STATUS_IB_CONF; 12766 break; 12767 case IB_PORT_ACTIVE: 12768 *ppd->statusp |= HFI1_STATUS_IB_READY; 12769 break; 12770 } 12771 } 12772 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n", 12773 opa_lstate_name(state), state); 12774 } 12775 12776 /** 12777 * wait_logical_linkstate - wait for an IB link state change to occur 12778 * @ppd: port device 12779 * @state: the state to wait for 12780 * @msecs: the number of milliseconds to wait 12781 * 12782 * Wait up to msecs milliseconds for IB link state change to occur. 12783 * For now, take the easy polling route. 12784 * Returns 0 if state reached, otherwise -ETIMEDOUT. 12785 */ 12786 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 12787 int msecs) 12788 { 12789 unsigned long timeout; 12790 u32 new_state; 12791 12792 timeout = jiffies + msecs_to_jiffies(msecs); 12793 while (1) { 12794 new_state = chip_to_opa_lstate(ppd->dd, 12795 read_logical_state(ppd->dd)); 12796 if (new_state == state) 12797 break; 12798 if (time_after(jiffies, timeout)) { 12799 dd_dev_err(ppd->dd, 12800 "timeout waiting for link state 0x%x\n", 12801 state); 12802 return -ETIMEDOUT; 12803 } 12804 msleep(20); 12805 } 12806 12807 return 0; 12808 } 12809 12810 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state) 12811 { 12812 u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state); 12813 12814 dd_dev_info(ppd->dd, 12815 "physical state changed to %s (0x%x), phy 0x%x\n", 12816 opa_pstate_name(ib_pstate), ib_pstate, state); 12817 } 12818 12819 /* 12820 * Read the physical hardware link state and check if it matches host 12821 * drivers anticipated state. 12822 */ 12823 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state) 12824 { 12825 u32 read_state = read_physical_state(ppd->dd); 12826 12827 if (read_state == state) { 12828 log_state_transition(ppd, state); 12829 } else { 12830 dd_dev_err(ppd->dd, 12831 "anticipated phy link state 0x%x, read 0x%x\n", 12832 state, read_state); 12833 } 12834 } 12835 12836 /* 12837 * wait_physical_linkstate - wait for an physical link state change to occur 12838 * @ppd: port device 12839 * @state: the state to wait for 12840 * @msecs: the number of milliseconds to wait 12841 * 12842 * Wait up to msecs milliseconds for physical link state change to occur. 12843 * Returns 0 if state reached, otherwise -ETIMEDOUT. 12844 */ 12845 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 12846 int msecs) 12847 { 12848 u32 read_state; 12849 unsigned long timeout; 12850 12851 timeout = jiffies + msecs_to_jiffies(msecs); 12852 while (1) { 12853 read_state = read_physical_state(ppd->dd); 12854 if (read_state == state) 12855 break; 12856 if (time_after(jiffies, timeout)) { 12857 dd_dev_err(ppd->dd, 12858 "timeout waiting for phy link state 0x%x\n", 12859 state); 12860 return -ETIMEDOUT; 12861 } 12862 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12863 } 12864 12865 log_state_transition(ppd, state); 12866 return 0; 12867 } 12868 12869 /* 12870 * wait_phys_link_offline_quiet_substates - wait for any offline substate 12871 * @ppd: port device 12872 * @msecs: the number of milliseconds to wait 12873 * 12874 * Wait up to msecs milliseconds for any offline physical link 12875 * state change to occur. 12876 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 12877 */ 12878 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 12879 int msecs) 12880 { 12881 u32 read_state; 12882 unsigned long timeout; 12883 12884 timeout = jiffies + msecs_to_jiffies(msecs); 12885 while (1) { 12886 read_state = read_physical_state(ppd->dd); 12887 if ((read_state & 0xF0) == PLS_OFFLINE) 12888 break; 12889 if (time_after(jiffies, timeout)) { 12890 dd_dev_err(ppd->dd, 12891 "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n", 12892 read_state, msecs); 12893 return -ETIMEDOUT; 12894 } 12895 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12896 } 12897 12898 log_state_transition(ppd, read_state); 12899 return read_state; 12900 } 12901 12902 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ 12903 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 12904 12905 #define SET_STATIC_RATE_CONTROL_SMASK(r) \ 12906 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 12907 12908 void hfi1_init_ctxt(struct send_context *sc) 12909 { 12910 if (sc) { 12911 struct hfi1_devdata *dd = sc->dd; 12912 u64 reg; 12913 u8 set = (sc->type == SC_USER ? 12914 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) : 12915 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)); 12916 reg = read_kctxt_csr(dd, sc->hw_context, 12917 SEND_CTXT_CHECK_ENABLE); 12918 if (set) 12919 CLEAR_STATIC_RATE_CONTROL_SMASK(reg); 12920 else 12921 SET_STATIC_RATE_CONTROL_SMASK(reg); 12922 write_kctxt_csr(dd, sc->hw_context, 12923 SEND_CTXT_CHECK_ENABLE, reg); 12924 } 12925 } 12926 12927 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp) 12928 { 12929 int ret = 0; 12930 u64 reg; 12931 12932 if (dd->icode != ICODE_RTL_SILICON) { 12933 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 12934 dd_dev_info(dd, "%s: tempsense not supported by HW\n", 12935 __func__); 12936 return -EINVAL; 12937 } 12938 reg = read_csr(dd, ASIC_STS_THERM); 12939 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) & 12940 ASIC_STS_THERM_CURR_TEMP_MASK); 12941 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) & 12942 ASIC_STS_THERM_LO_TEMP_MASK); 12943 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) & 12944 ASIC_STS_THERM_HI_TEMP_MASK); 12945 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) & 12946 ASIC_STS_THERM_CRIT_TEMP_MASK); 12947 /* triggers is a 3-bit value - 1 bit per trigger. */ 12948 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7); 12949 12950 return ret; 12951 } 12952 12953 /** 12954 * get_int_mask - get 64 bit int mask 12955 * @dd - the devdata 12956 * @i - the csr (relative to CCE_INT_MASK) 12957 * 12958 * Returns the mask with the urgent interrupt mask 12959 * bit clear for kernel receive contexts. 12960 */ 12961 static u64 get_int_mask(struct hfi1_devdata *dd, u32 i) 12962 { 12963 u64 mask = U64_MAX; /* default to no change */ 12964 12965 if (i >= (IS_RCVURGENT_START / 64) && i < (IS_RCVURGENT_END / 64)) { 12966 int j = (i - (IS_RCVURGENT_START / 64)) * 64; 12967 int k = !j ? IS_RCVURGENT_START % 64 : 0; 12968 12969 if (j) 12970 j -= IS_RCVURGENT_START % 64; 12971 /* j = 0..dd->first_dyn_alloc_ctxt - 1,k = 0..63 */ 12972 for (; j < dd->first_dyn_alloc_ctxt && k < 64; j++, k++) 12973 /* convert to bit in mask and clear */ 12974 mask &= ~BIT_ULL(k); 12975 } 12976 return mask; 12977 } 12978 12979 /* ========================================================================= */ 12980 12981 /* 12982 * Enable/disable chip from delivering interrupts. 12983 */ 12984 void set_intr_state(struct hfi1_devdata *dd, u32 enable) 12985 { 12986 int i; 12987 12988 /* 12989 * In HFI, the mask needs to be 1 to allow interrupts. 12990 */ 12991 if (enable) { 12992 /* enable all interrupts but urgent on kernel contexts */ 12993 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 12994 u64 mask = get_int_mask(dd, i); 12995 12996 write_csr(dd, CCE_INT_MASK + (8 * i), mask); 12997 } 12998 12999 init_qsfp_int(dd); 13000 } else { 13001 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13002 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 13003 } 13004 } 13005 13006 /* 13007 * Clear all interrupt sources on the chip. 13008 */ 13009 static void clear_all_interrupts(struct hfi1_devdata *dd) 13010 { 13011 int i; 13012 13013 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13014 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); 13015 13016 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); 13017 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); 13018 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); 13019 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); 13020 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); 13021 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); 13022 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); 13023 for (i = 0; i < dd->chip_send_contexts; i++) 13024 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0); 13025 for (i = 0; i < dd->chip_sdma_engines; i++) 13026 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0); 13027 13028 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); 13029 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); 13030 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); 13031 } 13032 13033 /* Move to pcie.c? */ 13034 static void disable_intx(struct pci_dev *pdev) 13035 { 13036 pci_intx(pdev, 0); 13037 } 13038 13039 /** 13040 * hfi1_clean_up_interrupts() - Free all IRQ resources 13041 * @dd: valid device data data structure 13042 * 13043 * Free the MSI or INTx IRQs and assoicated PCI resources, 13044 * if they have been allocated. 13045 */ 13046 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd) 13047 { 13048 int i; 13049 13050 /* remove irqs - must happen before disabling/turning off */ 13051 if (dd->num_msix_entries) { 13052 /* MSI-X */ 13053 struct hfi1_msix_entry *me = dd->msix_entries; 13054 13055 for (i = 0; i < dd->num_msix_entries; i++, me++) { 13056 if (!me->arg) /* => no irq, no affinity */ 13057 continue; 13058 hfi1_put_irq_affinity(dd, me); 13059 pci_free_irq(dd->pcidev, i, me->arg); 13060 } 13061 13062 /* clean structures */ 13063 kfree(dd->msix_entries); 13064 dd->msix_entries = NULL; 13065 dd->num_msix_entries = 0; 13066 } else { 13067 /* INTx */ 13068 if (dd->requested_intx_irq) { 13069 pci_free_irq(dd->pcidev, 0, dd); 13070 dd->requested_intx_irq = 0; 13071 } 13072 disable_intx(dd->pcidev); 13073 } 13074 13075 pci_free_irq_vectors(dd->pcidev); 13076 } 13077 13078 /* 13079 * Remap the interrupt source from the general handler to the given MSI-X 13080 * interrupt. 13081 */ 13082 static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr) 13083 { 13084 u64 reg; 13085 int m, n; 13086 13087 /* clear from the handled mask of the general interrupt */ 13088 m = isrc / 64; 13089 n = isrc % 64; 13090 if (likely(m < CCE_NUM_INT_CSRS)) { 13091 dd->gi_mask[m] &= ~((u64)1 << n); 13092 } else { 13093 dd_dev_err(dd, "remap interrupt err\n"); 13094 return; 13095 } 13096 13097 /* direct the chip source to the given MSI-X interrupt */ 13098 m = isrc / 8; 13099 n = isrc % 8; 13100 reg = read_csr(dd, CCE_INT_MAP + (8 * m)); 13101 reg &= ~((u64)0xff << (8 * n)); 13102 reg |= ((u64)msix_intr & 0xff) << (8 * n); 13103 write_csr(dd, CCE_INT_MAP + (8 * m), reg); 13104 } 13105 13106 static void remap_sdma_interrupts(struct hfi1_devdata *dd, 13107 int engine, int msix_intr) 13108 { 13109 /* 13110 * SDMA engine interrupt sources grouped by type, rather than 13111 * engine. Per-engine interrupts are as follows: 13112 * SDMA 13113 * SDMAProgress 13114 * SDMAIdle 13115 */ 13116 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine, 13117 msix_intr); 13118 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine, 13119 msix_intr); 13120 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine, 13121 msix_intr); 13122 } 13123 13124 static int request_intx_irq(struct hfi1_devdata *dd) 13125 { 13126 int ret; 13127 13128 ret = pci_request_irq(dd->pcidev, 0, general_interrupt, NULL, dd, 13129 DRIVER_NAME "_%d", dd->unit); 13130 if (ret) 13131 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n", 13132 ret); 13133 else 13134 dd->requested_intx_irq = 1; 13135 return ret; 13136 } 13137 13138 static int request_msix_irqs(struct hfi1_devdata *dd) 13139 { 13140 int first_general, last_general; 13141 int first_sdma, last_sdma; 13142 int first_rx, last_rx; 13143 int i, ret = 0; 13144 13145 /* calculate the ranges we are going to use */ 13146 first_general = 0; 13147 last_general = first_general + 1; 13148 first_sdma = last_general; 13149 last_sdma = first_sdma + dd->num_sdma; 13150 first_rx = last_sdma; 13151 last_rx = first_rx + dd->n_krcv_queues + dd->num_vnic_contexts; 13152 13153 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */ 13154 dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues; 13155 13156 /* 13157 * Sanity check - the code expects all SDMA chip source 13158 * interrupts to be in the same CSR, starting at bit 0. Verify 13159 * that this is true by checking the bit location of the start. 13160 */ 13161 BUILD_BUG_ON(IS_SDMA_START % 64); 13162 13163 for (i = 0; i < dd->num_msix_entries; i++) { 13164 struct hfi1_msix_entry *me = &dd->msix_entries[i]; 13165 const char *err_info; 13166 irq_handler_t handler; 13167 irq_handler_t thread = NULL; 13168 void *arg = NULL; 13169 int idx; 13170 struct hfi1_ctxtdata *rcd = NULL; 13171 struct sdma_engine *sde = NULL; 13172 char name[MAX_NAME_SIZE]; 13173 13174 /* obtain the arguments to pci_request_irq */ 13175 if (first_general <= i && i < last_general) { 13176 idx = i - first_general; 13177 handler = general_interrupt; 13178 arg = dd; 13179 snprintf(name, sizeof(name), 13180 DRIVER_NAME "_%d", dd->unit); 13181 err_info = "general"; 13182 me->type = IRQ_GENERAL; 13183 } else if (first_sdma <= i && i < last_sdma) { 13184 idx = i - first_sdma; 13185 sde = &dd->per_sdma[idx]; 13186 handler = sdma_interrupt; 13187 arg = sde; 13188 snprintf(name, sizeof(name), 13189 DRIVER_NAME "_%d sdma%d", dd->unit, idx); 13190 err_info = "sdma"; 13191 remap_sdma_interrupts(dd, idx, i); 13192 me->type = IRQ_SDMA; 13193 } else if (first_rx <= i && i < last_rx) { 13194 idx = i - first_rx; 13195 rcd = hfi1_rcd_get_by_index_safe(dd, idx); 13196 if (rcd) { 13197 /* 13198 * Set the interrupt register and mask for this 13199 * context's interrupt. 13200 */ 13201 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64; 13202 rcd->imask = ((u64)1) << 13203 ((IS_RCVAVAIL_START + idx) % 64); 13204 handler = receive_context_interrupt; 13205 thread = receive_context_thread; 13206 arg = rcd; 13207 snprintf(name, sizeof(name), 13208 DRIVER_NAME "_%d kctxt%d", 13209 dd->unit, idx); 13210 err_info = "receive context"; 13211 remap_intr(dd, IS_RCVAVAIL_START + idx, i); 13212 me->type = IRQ_RCVCTXT; 13213 rcd->msix_intr = i; 13214 hfi1_rcd_put(rcd); 13215 } 13216 } else { 13217 /* not in our expected range - complain, then 13218 * ignore it 13219 */ 13220 dd_dev_err(dd, 13221 "Unexpected extra MSI-X interrupt %d\n", i); 13222 continue; 13223 } 13224 /* no argument, no interrupt */ 13225 if (!arg) 13226 continue; 13227 /* make sure the name is terminated */ 13228 name[sizeof(name) - 1] = 0; 13229 me->irq = pci_irq_vector(dd->pcidev, i); 13230 ret = pci_request_irq(dd->pcidev, i, handler, thread, arg, 13231 name); 13232 if (ret) { 13233 dd_dev_err(dd, 13234 "unable to allocate %s interrupt, irq %d, index %d, err %d\n", 13235 err_info, me->irq, idx, ret); 13236 return ret; 13237 } 13238 /* 13239 * assign arg after pci_request_irq call, so it will be 13240 * cleaned up 13241 */ 13242 me->arg = arg; 13243 13244 ret = hfi1_get_irq_affinity(dd, me); 13245 if (ret) 13246 dd_dev_err(dd, "unable to pin IRQ %d\n", ret); 13247 } 13248 13249 return ret; 13250 } 13251 13252 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd) 13253 { 13254 int i; 13255 13256 if (!dd->num_msix_entries) { 13257 synchronize_irq(pci_irq_vector(dd->pcidev, 0)); 13258 return; 13259 } 13260 13261 for (i = 0; i < dd->vnic.num_ctxt; i++) { 13262 struct hfi1_ctxtdata *rcd = dd->vnic.ctxt[i]; 13263 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr]; 13264 13265 synchronize_irq(me->irq); 13266 } 13267 } 13268 13269 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd) 13270 { 13271 struct hfi1_devdata *dd = rcd->dd; 13272 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr]; 13273 13274 if (!me->arg) /* => no irq, no affinity */ 13275 return; 13276 13277 hfi1_put_irq_affinity(dd, me); 13278 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg); 13279 13280 me->arg = NULL; 13281 } 13282 13283 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd) 13284 { 13285 struct hfi1_devdata *dd = rcd->dd; 13286 struct hfi1_msix_entry *me; 13287 int idx = rcd->ctxt; 13288 void *arg = rcd; 13289 int ret; 13290 13291 rcd->msix_intr = dd->vnic.msix_idx++; 13292 me = &dd->msix_entries[rcd->msix_intr]; 13293 13294 /* 13295 * Set the interrupt register and mask for this 13296 * context's interrupt. 13297 */ 13298 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64; 13299 rcd->imask = ((u64)1) << 13300 ((IS_RCVAVAIL_START + idx) % 64); 13301 me->type = IRQ_RCVCTXT; 13302 me->irq = pci_irq_vector(dd->pcidev, rcd->msix_intr); 13303 remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr); 13304 13305 ret = pci_request_irq(dd->pcidev, rcd->msix_intr, 13306 receive_context_interrupt, 13307 receive_context_thread, arg, 13308 DRIVER_NAME "_%d kctxt%d", dd->unit, idx); 13309 if (ret) { 13310 dd_dev_err(dd, "vnic irq request (irq %d, idx %d) fail %d\n", 13311 me->irq, idx, ret); 13312 return; 13313 } 13314 /* 13315 * assign arg after pci_request_irq call, so it will be 13316 * cleaned up 13317 */ 13318 me->arg = arg; 13319 13320 ret = hfi1_get_irq_affinity(dd, me); 13321 if (ret) { 13322 dd_dev_err(dd, 13323 "unable to pin IRQ %d\n", ret); 13324 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg); 13325 } 13326 } 13327 13328 /* 13329 * Set the general handler to accept all interrupts, remap all 13330 * chip interrupts back to MSI-X 0. 13331 */ 13332 static void reset_interrupts(struct hfi1_devdata *dd) 13333 { 13334 int i; 13335 13336 /* all interrupts handled by the general handler */ 13337 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13338 dd->gi_mask[i] = ~(u64)0; 13339 13340 /* all chip interrupts map to MSI-X 0 */ 13341 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13342 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13343 } 13344 13345 static int set_up_interrupts(struct hfi1_devdata *dd) 13346 { 13347 u32 total; 13348 int ret, request; 13349 int single_interrupt = 0; /* we expect to have all the interrupts */ 13350 13351 /* 13352 * Interrupt count: 13353 * 1 general, "slow path" interrupt (includes the SDMA engines 13354 * slow source, SDMACleanupDone) 13355 * N interrupts - one per used SDMA engine 13356 * M interrupt - one per kernel receive context 13357 * V interrupt - one for each VNIC context 13358 */ 13359 total = 1 + dd->num_sdma + dd->n_krcv_queues + dd->num_vnic_contexts; 13360 13361 /* ask for MSI-X interrupts */ 13362 request = request_msix(dd, total); 13363 if (request < 0) { 13364 ret = request; 13365 goto fail; 13366 } else if (request == 0) { 13367 /* using INTx */ 13368 /* dd->num_msix_entries already zero */ 13369 single_interrupt = 1; 13370 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n"); 13371 } else if (request < total) { 13372 /* using MSI-X, with reduced interrupts */ 13373 dd_dev_err(dd, "reduced interrupt found, wanted %u, got %u\n", 13374 total, request); 13375 ret = -EINVAL; 13376 goto fail; 13377 } else { 13378 dd->msix_entries = kcalloc(total, sizeof(*dd->msix_entries), 13379 GFP_KERNEL); 13380 if (!dd->msix_entries) { 13381 ret = -ENOMEM; 13382 goto fail; 13383 } 13384 /* using MSI-X */ 13385 dd->num_msix_entries = total; 13386 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total); 13387 } 13388 13389 /* mask all interrupts */ 13390 set_intr_state(dd, 0); 13391 /* clear all pending interrupts */ 13392 clear_all_interrupts(dd); 13393 13394 /* reset general handler mask, chip MSI-X mappings */ 13395 reset_interrupts(dd); 13396 13397 if (single_interrupt) 13398 ret = request_intx_irq(dd); 13399 else 13400 ret = request_msix_irqs(dd); 13401 if (ret) 13402 goto fail; 13403 13404 return 0; 13405 13406 fail: 13407 hfi1_clean_up_interrupts(dd); 13408 return ret; 13409 } 13410 13411 /* 13412 * Set up context values in dd. Sets: 13413 * 13414 * num_rcv_contexts - number of contexts being used 13415 * n_krcv_queues - number of kernel contexts 13416 * first_dyn_alloc_ctxt - first dynamically allocated context 13417 * in array of contexts 13418 * freectxts - number of free user contexts 13419 * num_send_contexts - number of PIO send contexts being used 13420 * num_vnic_contexts - number of contexts reserved for VNIC 13421 */ 13422 static int set_up_context_variables(struct hfi1_devdata *dd) 13423 { 13424 unsigned long num_kernel_contexts; 13425 u16 num_vnic_contexts = HFI1_NUM_VNIC_CTXT; 13426 int total_contexts; 13427 int ret; 13428 unsigned ngroups; 13429 int qos_rmt_count; 13430 int user_rmt_reduced; 13431 u32 n_usr_ctxts; 13432 13433 /* 13434 * Kernel receive contexts: 13435 * - Context 0 - control context (VL15/multicast/error) 13436 * - Context 1 - first kernel context 13437 * - Context 2 - second kernel context 13438 * ... 13439 */ 13440 if (n_krcvqs) 13441 /* 13442 * n_krcvqs is the sum of module parameter kernel receive 13443 * contexts, krcvqs[]. It does not include the control 13444 * context, so add that. 13445 */ 13446 num_kernel_contexts = n_krcvqs + 1; 13447 else 13448 num_kernel_contexts = DEFAULT_KRCVQS + 1; 13449 /* 13450 * Every kernel receive context needs an ACK send context. 13451 * one send context is allocated for each VL{0-7} and VL15 13452 */ 13453 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) { 13454 dd_dev_err(dd, 13455 "Reducing # kernel rcv contexts to: %d, from %lu\n", 13456 (int)(dd->chip_send_contexts - num_vls - 1), 13457 num_kernel_contexts); 13458 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1; 13459 } 13460 13461 /* Accommodate VNIC contexts if possible */ 13462 if ((num_kernel_contexts + num_vnic_contexts) > dd->chip_rcv_contexts) { 13463 dd_dev_err(dd, "No receive contexts available for VNIC\n"); 13464 num_vnic_contexts = 0; 13465 } 13466 total_contexts = num_kernel_contexts + num_vnic_contexts; 13467 13468 /* 13469 * User contexts: 13470 * - default to 1 user context per real (non-HT) CPU core if 13471 * num_user_contexts is negative 13472 */ 13473 if (num_user_contexts < 0) 13474 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask); 13475 else 13476 n_usr_ctxts = num_user_contexts; 13477 /* 13478 * Adjust the counts given a global max. 13479 */ 13480 if (total_contexts + n_usr_ctxts > dd->chip_rcv_contexts) { 13481 dd_dev_err(dd, 13482 "Reducing # user receive contexts to: %d, from %u\n", 13483 (int)(dd->chip_rcv_contexts - total_contexts), 13484 n_usr_ctxts); 13485 /* recalculate */ 13486 n_usr_ctxts = dd->chip_rcv_contexts - total_contexts; 13487 } 13488 13489 /* each user context requires an entry in the RMT */ 13490 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL); 13491 if (qos_rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) { 13492 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count; 13493 dd_dev_err(dd, 13494 "RMT size is reducing the number of user receive contexts from %u to %d\n", 13495 n_usr_ctxts, 13496 user_rmt_reduced); 13497 /* recalculate */ 13498 n_usr_ctxts = user_rmt_reduced; 13499 } 13500 13501 total_contexts += n_usr_ctxts; 13502 13503 /* the first N are kernel contexts, the rest are user/vnic contexts */ 13504 dd->num_rcv_contexts = total_contexts; 13505 dd->n_krcv_queues = num_kernel_contexts; 13506 dd->first_dyn_alloc_ctxt = num_kernel_contexts; 13507 dd->num_vnic_contexts = num_vnic_contexts; 13508 dd->num_user_contexts = n_usr_ctxts; 13509 dd->freectxts = n_usr_ctxts; 13510 dd_dev_info(dd, 13511 "rcv contexts: chip %d, used %d (kernel %d, vnic %u, user %u)\n", 13512 (int)dd->chip_rcv_contexts, 13513 (int)dd->num_rcv_contexts, 13514 (int)dd->n_krcv_queues, 13515 dd->num_vnic_contexts, 13516 dd->num_user_contexts); 13517 13518 /* 13519 * Receive array allocation: 13520 * All RcvArray entries are divided into groups of 8. This 13521 * is required by the hardware and will speed up writes to 13522 * consecutive entries by using write-combining of the entire 13523 * cacheline. 13524 * 13525 * The number of groups are evenly divided among all contexts. 13526 * any left over groups will be given to the first N user 13527 * contexts. 13528 */ 13529 dd->rcv_entries.group_size = RCV_INCREMENT; 13530 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size; 13531 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts; 13532 dd->rcv_entries.nctxt_extra = ngroups - 13533 (dd->num_rcv_contexts * dd->rcv_entries.ngroups); 13534 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n", 13535 dd->rcv_entries.ngroups, 13536 dd->rcv_entries.nctxt_extra); 13537 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size > 13538 MAX_EAGER_ENTRIES * 2) { 13539 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) / 13540 dd->rcv_entries.group_size; 13541 dd_dev_info(dd, 13542 "RcvArray group count too high, change to %u\n", 13543 dd->rcv_entries.ngroups); 13544 dd->rcv_entries.nctxt_extra = 0; 13545 } 13546 /* 13547 * PIO send contexts 13548 */ 13549 ret = init_sc_pools_and_sizes(dd); 13550 if (ret >= 0) { /* success */ 13551 dd->num_send_contexts = ret; 13552 dd_dev_info( 13553 dd, 13554 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n", 13555 dd->chip_send_contexts, 13556 dd->num_send_contexts, 13557 dd->sc_sizes[SC_KERNEL].count, 13558 dd->sc_sizes[SC_ACK].count, 13559 dd->sc_sizes[SC_USER].count, 13560 dd->sc_sizes[SC_VL15].count); 13561 ret = 0; /* success */ 13562 } 13563 13564 return ret; 13565 } 13566 13567 /* 13568 * Set the device/port partition key table. The MAD code 13569 * will ensure that, at least, the partial management 13570 * partition key is present in the table. 13571 */ 13572 static void set_partition_keys(struct hfi1_pportdata *ppd) 13573 { 13574 struct hfi1_devdata *dd = ppd->dd; 13575 u64 reg = 0; 13576 int i; 13577 13578 dd_dev_info(dd, "Setting partition keys\n"); 13579 for (i = 0; i < hfi1_get_npkeys(dd); i++) { 13580 reg |= (ppd->pkeys[i] & 13581 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) << 13582 ((i % 4) * 13583 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT); 13584 /* Each register holds 4 PKey values. */ 13585 if ((i % 4) == 3) { 13586 write_csr(dd, RCV_PARTITION_KEY + 13587 ((i - 3) * 2), reg); 13588 reg = 0; 13589 } 13590 } 13591 13592 /* Always enable HW pkeys check when pkeys table is set */ 13593 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK); 13594 } 13595 13596 /* 13597 * These CSRs and memories are uninitialized on reset and must be 13598 * written before reading to set the ECC/parity bits. 13599 * 13600 * NOTE: All user context CSRs that are not mmaped write-only 13601 * (e.g. the TID flows) must be initialized even if the driver never 13602 * reads them. 13603 */ 13604 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd) 13605 { 13606 int i, j; 13607 13608 /* CceIntMap */ 13609 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13610 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13611 13612 /* SendCtxtCreditReturnAddr */ 13613 for (i = 0; i < dd->chip_send_contexts; i++) 13614 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13615 13616 /* PIO Send buffers */ 13617 /* SDMA Send buffers */ 13618 /* 13619 * These are not normally read, and (presently) have no method 13620 * to be read, so are not pre-initialized 13621 */ 13622 13623 /* RcvHdrAddr */ 13624 /* RcvHdrTailAddr */ 13625 /* RcvTidFlowTable */ 13626 for (i = 0; i < dd->chip_rcv_contexts; i++) { 13627 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13628 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13629 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) 13630 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0); 13631 } 13632 13633 /* RcvArray */ 13634 for (i = 0; i < dd->chip_rcv_array_count; i++) 13635 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0); 13636 13637 /* RcvQPMapTable */ 13638 for (i = 0; i < 32; i++) 13639 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13640 } 13641 13642 /* 13643 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus. 13644 */ 13645 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits, 13646 u64 ctrl_bits) 13647 { 13648 unsigned long timeout; 13649 u64 reg; 13650 13651 /* is the condition present? */ 13652 reg = read_csr(dd, CCE_STATUS); 13653 if ((reg & status_bits) == 0) 13654 return; 13655 13656 /* clear the condition */ 13657 write_csr(dd, CCE_CTRL, ctrl_bits); 13658 13659 /* wait for the condition to clear */ 13660 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT); 13661 while (1) { 13662 reg = read_csr(dd, CCE_STATUS); 13663 if ((reg & status_bits) == 0) 13664 return; 13665 if (time_after(jiffies, timeout)) { 13666 dd_dev_err(dd, 13667 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n", 13668 status_bits, reg & status_bits); 13669 return; 13670 } 13671 udelay(1); 13672 } 13673 } 13674 13675 /* set CCE CSRs to chip reset defaults */ 13676 static void reset_cce_csrs(struct hfi1_devdata *dd) 13677 { 13678 int i; 13679 13680 /* CCE_REVISION read-only */ 13681 /* CCE_REVISION2 read-only */ 13682 /* CCE_CTRL - bits clear automatically */ 13683 /* CCE_STATUS read-only, use CceCtrl to clear */ 13684 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK); 13685 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK); 13686 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK); 13687 for (i = 0; i < CCE_NUM_SCRATCH; i++) 13688 write_csr(dd, CCE_SCRATCH + (8 * i), 0); 13689 /* CCE_ERR_STATUS read-only */ 13690 write_csr(dd, CCE_ERR_MASK, 0); 13691 write_csr(dd, CCE_ERR_CLEAR, ~0ull); 13692 /* CCE_ERR_FORCE leave alone */ 13693 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++) 13694 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); 13695 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); 13696 /* CCE_PCIE_CTRL leave alone */ 13697 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) { 13698 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); 13699 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), 13700 CCE_MSIX_TABLE_UPPER_RESETCSR); 13701 } 13702 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) { 13703 /* CCE_MSIX_PBA read-only */ 13704 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); 13705 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); 13706 } 13707 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13708 write_csr(dd, CCE_INT_MAP, 0); 13709 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 13710 /* CCE_INT_STATUS read-only */ 13711 write_csr(dd, CCE_INT_MASK + (8 * i), 0); 13712 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); 13713 /* CCE_INT_FORCE leave alone */ 13714 /* CCE_INT_BLOCKED read-only */ 13715 } 13716 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++) 13717 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); 13718 } 13719 13720 /* set MISC CSRs to chip reset defaults */ 13721 static void reset_misc_csrs(struct hfi1_devdata *dd) 13722 { 13723 int i; 13724 13725 for (i = 0; i < 32; i++) { 13726 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); 13727 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); 13728 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); 13729 } 13730 /* 13731 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can 13732 * only be written 128-byte chunks 13733 */ 13734 /* init RSA engine to clear lingering errors */ 13735 write_csr(dd, MISC_CFG_RSA_CMD, 1); 13736 write_csr(dd, MISC_CFG_RSA_MU, 0); 13737 write_csr(dd, MISC_CFG_FW_CTRL, 0); 13738 /* MISC_STS_8051_DIGEST read-only */ 13739 /* MISC_STS_SBM_DIGEST read-only */ 13740 /* MISC_STS_PCIE_DIGEST read-only */ 13741 /* MISC_STS_FAB_DIGEST read-only */ 13742 /* MISC_ERR_STATUS read-only */ 13743 write_csr(dd, MISC_ERR_MASK, 0); 13744 write_csr(dd, MISC_ERR_CLEAR, ~0ull); 13745 /* MISC_ERR_FORCE leave alone */ 13746 } 13747 13748 /* set TXE CSRs to chip reset defaults */ 13749 static void reset_txe_csrs(struct hfi1_devdata *dd) 13750 { 13751 int i; 13752 13753 /* 13754 * TXE Kernel CSRs 13755 */ 13756 write_csr(dd, SEND_CTRL, 0); 13757 __cm_reset(dd, 0); /* reset CM internal state */ 13758 /* SEND_CONTEXTS read-only */ 13759 /* SEND_DMA_ENGINES read-only */ 13760 /* SEND_PIO_MEM_SIZE read-only */ 13761 /* SEND_DMA_MEM_SIZE read-only */ 13762 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); 13763 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */ 13764 /* SEND_PIO_ERR_STATUS read-only */ 13765 write_csr(dd, SEND_PIO_ERR_MASK, 0); 13766 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); 13767 /* SEND_PIO_ERR_FORCE leave alone */ 13768 /* SEND_DMA_ERR_STATUS read-only */ 13769 write_csr(dd, SEND_DMA_ERR_MASK, 0); 13770 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); 13771 /* SEND_DMA_ERR_FORCE leave alone */ 13772 /* SEND_EGRESS_ERR_STATUS read-only */ 13773 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); 13774 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); 13775 /* SEND_EGRESS_ERR_FORCE leave alone */ 13776 write_csr(dd, SEND_BTH_QP, 0); 13777 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); 13778 write_csr(dd, SEND_SC2VLT0, 0); 13779 write_csr(dd, SEND_SC2VLT1, 0); 13780 write_csr(dd, SEND_SC2VLT2, 0); 13781 write_csr(dd, SEND_SC2VLT3, 0); 13782 write_csr(dd, SEND_LEN_CHECK0, 0); 13783 write_csr(dd, SEND_LEN_CHECK1, 0); 13784 /* SEND_ERR_STATUS read-only */ 13785 write_csr(dd, SEND_ERR_MASK, 0); 13786 write_csr(dd, SEND_ERR_CLEAR, ~0ull); 13787 /* SEND_ERR_FORCE read-only */ 13788 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++) 13789 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); 13790 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++) 13791 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); 13792 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++) 13793 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); 13794 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++) 13795 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); 13796 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++) 13797 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); 13798 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); 13799 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); 13800 /* SEND_CM_CREDIT_USED_STATUS read-only */ 13801 write_csr(dd, SEND_CM_TIMER_CTRL, 0); 13802 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); 13803 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); 13804 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); 13805 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); 13806 for (i = 0; i < TXE_NUM_DATA_VL; i++) 13807 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 13808 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 13809 /* SEND_CM_CREDIT_USED_VL read-only */ 13810 /* SEND_CM_CREDIT_USED_VL15 read-only */ 13811 /* SEND_EGRESS_CTXT_STATUS read-only */ 13812 /* SEND_EGRESS_SEND_DMA_STATUS read-only */ 13813 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); 13814 /* SEND_EGRESS_ERR_INFO read-only */ 13815 /* SEND_EGRESS_ERR_SOURCE read-only */ 13816 13817 /* 13818 * TXE Per-Context CSRs 13819 */ 13820 for (i = 0; i < dd->chip_send_contexts; i++) { 13821 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 13822 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0); 13823 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13824 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0); 13825 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0); 13826 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull); 13827 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0); 13828 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0); 13829 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0); 13830 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0); 13831 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0); 13832 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0); 13833 } 13834 13835 /* 13836 * TXE Per-SDMA CSRs 13837 */ 13838 for (i = 0; i < dd->chip_sdma_engines; i++) { 13839 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 13840 /* SEND_DMA_STATUS read-only */ 13841 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0); 13842 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0); 13843 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0); 13844 /* SEND_DMA_HEAD read-only */ 13845 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0); 13846 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0); 13847 /* SEND_DMA_IDLE_CNT read-only */ 13848 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0); 13849 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0); 13850 /* SEND_DMA_DESC_FETCHED_CNT read-only */ 13851 /* SEND_DMA_ENG_ERR_STATUS read-only */ 13852 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0); 13853 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull); 13854 /* SEND_DMA_ENG_ERR_FORCE leave alone */ 13855 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0); 13856 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0); 13857 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0); 13858 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0); 13859 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0); 13860 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0); 13861 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0); 13862 } 13863 } 13864 13865 /* 13866 * Expect on entry: 13867 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0 13868 */ 13869 static void init_rbufs(struct hfi1_devdata *dd) 13870 { 13871 u64 reg; 13872 int count; 13873 13874 /* 13875 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are 13876 * clear. 13877 */ 13878 count = 0; 13879 while (1) { 13880 reg = read_csr(dd, RCV_STATUS); 13881 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 13882 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0) 13883 break; 13884 /* 13885 * Give up after 1ms - maximum wait time. 13886 * 13887 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at 13888 * 250MB/s bandwidth. Lower rate to 66% for overhead to get: 13889 * 136 KB / (66% * 250MB/s) = 844us 13890 */ 13891 if (count++ > 500) { 13892 dd_dev_err(dd, 13893 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n", 13894 __func__, reg); 13895 break; 13896 } 13897 udelay(2); /* do not busy-wait the CSR */ 13898 } 13899 13900 /* start the init - expect RcvCtrl to be 0 */ 13901 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); 13902 13903 /* 13904 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief 13905 * period after the write before RcvStatus.RxRbufInitDone is valid. 13906 * The delay in the first run through the loop below is sufficient and 13907 * required before the first read of RcvStatus.RxRbufInintDone. 13908 */ 13909 read_csr(dd, RCV_CTRL); 13910 13911 /* wait for the init to finish */ 13912 count = 0; 13913 while (1) { 13914 /* delay is required first time through - see above */ 13915 udelay(2); /* do not busy-wait the CSR */ 13916 reg = read_csr(dd, RCV_STATUS); 13917 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK)) 13918 break; 13919 13920 /* give up after 100us - slowest possible at 33MHz is 73us */ 13921 if (count++ > 50) { 13922 dd_dev_err(dd, 13923 "%s: RcvStatus.RxRbufInit not set, continuing\n", 13924 __func__); 13925 break; 13926 } 13927 } 13928 } 13929 13930 /* set RXE CSRs to chip reset defaults */ 13931 static void reset_rxe_csrs(struct hfi1_devdata *dd) 13932 { 13933 int i, j; 13934 13935 /* 13936 * RXE Kernel CSRs 13937 */ 13938 write_csr(dd, RCV_CTRL, 0); 13939 init_rbufs(dd); 13940 /* RCV_STATUS read-only */ 13941 /* RCV_CONTEXTS read-only */ 13942 /* RCV_ARRAY_CNT read-only */ 13943 /* RCV_BUF_SIZE read-only */ 13944 write_csr(dd, RCV_BTH_QP, 0); 13945 write_csr(dd, RCV_MULTICAST, 0); 13946 write_csr(dd, RCV_BYPASS, 0); 13947 write_csr(dd, RCV_VL15, 0); 13948 /* this is a clear-down */ 13949 write_csr(dd, RCV_ERR_INFO, 13950 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK); 13951 /* RCV_ERR_STATUS read-only */ 13952 write_csr(dd, RCV_ERR_MASK, 0); 13953 write_csr(dd, RCV_ERR_CLEAR, ~0ull); 13954 /* RCV_ERR_FORCE leave alone */ 13955 for (i = 0; i < 32; i++) 13956 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13957 for (i = 0; i < 4; i++) 13958 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); 13959 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++) 13960 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); 13961 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++) 13962 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); 13963 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) 13964 clear_rsm_rule(dd, i); 13965 for (i = 0; i < 32; i++) 13966 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); 13967 13968 /* 13969 * RXE Kernel and User Per-Context CSRs 13970 */ 13971 for (i = 0; i < dd->chip_rcv_contexts; i++) { 13972 /* kernel */ 13973 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0); 13974 /* RCV_CTXT_STATUS read-only */ 13975 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0); 13976 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0); 13977 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0); 13978 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13979 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0); 13980 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0); 13981 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0); 13982 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13983 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0); 13984 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0); 13985 13986 /* user */ 13987 /* RCV_HDR_TAIL read-only */ 13988 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0); 13989 /* RCV_EGR_INDEX_TAIL read-only */ 13990 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0); 13991 /* RCV_EGR_OFFSET_TAIL read-only */ 13992 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) { 13993 write_uctxt_csr(dd, i, 13994 RCV_TID_FLOW_TABLE + (8 * j), 0); 13995 } 13996 } 13997 } 13998 13999 /* 14000 * Set sc2vl tables. 14001 * 14002 * They power on to zeros, so to avoid send context errors 14003 * they need to be set: 14004 * 14005 * SC 0-7 -> VL 0-7 (respectively) 14006 * SC 15 -> VL 15 14007 * otherwise 14008 * -> VL 0 14009 */ 14010 static void init_sc2vl_tables(struct hfi1_devdata *dd) 14011 { 14012 int i; 14013 /* init per architecture spec, constrained by hardware capability */ 14014 14015 /* HFI maps sent packets */ 14016 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( 14017 0, 14018 0, 0, 1, 1, 14019 2, 2, 3, 3, 14020 4, 4, 5, 5, 14021 6, 6, 7, 7)); 14022 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( 14023 1, 14024 8, 0, 9, 0, 14025 10, 0, 11, 0, 14026 12, 0, 13, 0, 14027 14, 0, 15, 15)); 14028 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( 14029 2, 14030 16, 0, 17, 0, 14031 18, 0, 19, 0, 14032 20, 0, 21, 0, 14033 22, 0, 23, 0)); 14034 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( 14035 3, 14036 24, 0, 25, 0, 14037 26, 0, 27, 0, 14038 28, 0, 29, 0, 14039 30, 0, 31, 0)); 14040 14041 /* DC maps received packets */ 14042 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( 14043 15_0, 14044 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 14045 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15)); 14046 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( 14047 31_16, 14048 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0, 14049 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0)); 14050 14051 /* initialize the cached sc2vl values consistently with h/w */ 14052 for (i = 0; i < 32; i++) { 14053 if (i < 8 || i == 15) 14054 *((u8 *)(dd->sc2vl) + i) = (u8)i; 14055 else 14056 *((u8 *)(dd->sc2vl) + i) = 0; 14057 } 14058 } 14059 14060 /* 14061 * Read chip sizes and then reset parts to sane, disabled, values. We cannot 14062 * depend on the chip going through a power-on reset - a driver may be loaded 14063 * and unloaded many times. 14064 * 14065 * Do not write any CSR values to the chip in this routine - there may be 14066 * a reset following the (possible) FLR in this routine. 14067 * 14068 */ 14069 static int init_chip(struct hfi1_devdata *dd) 14070 { 14071 int i; 14072 int ret = 0; 14073 14074 /* 14075 * Put the HFI CSRs in a known state. 14076 * Combine this with a DC reset. 14077 * 14078 * Stop the device from doing anything while we do a 14079 * reset. We know there are no other active users of 14080 * the device since we are now in charge. Turn off 14081 * off all outbound and inbound traffic and make sure 14082 * the device does not generate any interrupts. 14083 */ 14084 14085 /* disable send contexts and SDMA engines */ 14086 write_csr(dd, SEND_CTRL, 0); 14087 for (i = 0; i < dd->chip_send_contexts; i++) 14088 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 14089 for (i = 0; i < dd->chip_sdma_engines; i++) 14090 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 14091 /* disable port (turn off RXE inbound traffic) and contexts */ 14092 write_csr(dd, RCV_CTRL, 0); 14093 for (i = 0; i < dd->chip_rcv_contexts; i++) 14094 write_csr(dd, RCV_CTXT_CTRL, 0); 14095 /* mask all interrupt sources */ 14096 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 14097 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 14098 14099 /* 14100 * DC Reset: do a full DC reset before the register clear. 14101 * A recommended length of time to hold is one CSR read, 14102 * so reread the CceDcCtrl. Then, hold the DC in reset 14103 * across the clear. 14104 */ 14105 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 14106 (void)read_csr(dd, CCE_DC_CTRL); 14107 14108 if (use_flr) { 14109 /* 14110 * A FLR will reset the SPC core and part of the PCIe. 14111 * The parts that need to be restored have already been 14112 * saved. 14113 */ 14114 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14115 14116 /* do the FLR, the DC reset will remain */ 14117 pcie_flr(dd->pcidev); 14118 14119 /* restore command and BARs */ 14120 ret = restore_pci_variables(dd); 14121 if (ret) { 14122 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14123 __func__); 14124 return ret; 14125 } 14126 14127 if (is_ax(dd)) { 14128 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14129 pcie_flr(dd->pcidev); 14130 ret = restore_pci_variables(dd); 14131 if (ret) { 14132 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14133 __func__); 14134 return ret; 14135 } 14136 } 14137 } else { 14138 dd_dev_info(dd, "Resetting CSRs with writes\n"); 14139 reset_cce_csrs(dd); 14140 reset_txe_csrs(dd); 14141 reset_rxe_csrs(dd); 14142 reset_misc_csrs(dd); 14143 } 14144 /* clear the DC reset */ 14145 write_csr(dd, CCE_DC_CTRL, 0); 14146 14147 /* Set the LED off */ 14148 setextled(dd, 0); 14149 14150 /* 14151 * Clear the QSFP reset. 14152 * An FLR enforces a 0 on all out pins. The driver does not touch 14153 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and 14154 * anything plugged constantly in reset, if it pays attention 14155 * to RESET_N. 14156 * Prime examples of this are optical cables. Set all pins high. 14157 * I2CCLK and I2CDAT will change per direction, and INT_N and 14158 * MODPRS_N are input only and their value is ignored. 14159 */ 14160 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); 14161 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); 14162 init_chip_resources(dd); 14163 return ret; 14164 } 14165 14166 static void init_early_variables(struct hfi1_devdata *dd) 14167 { 14168 int i; 14169 14170 /* assign link credit variables */ 14171 dd->vau = CM_VAU; 14172 dd->link_credits = CM_GLOBAL_CREDITS; 14173 if (is_ax(dd)) 14174 dd->link_credits--; 14175 dd->vcu = cu_to_vcu(hfi1_cu); 14176 /* enough room for 8 MAD packets plus header - 17K */ 14177 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau); 14178 if (dd->vl15_init > dd->link_credits) 14179 dd->vl15_init = dd->link_credits; 14180 14181 write_uninitialized_csrs_and_memories(dd); 14182 14183 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 14184 for (i = 0; i < dd->num_pports; i++) { 14185 struct hfi1_pportdata *ppd = &dd->pport[i]; 14186 14187 set_partition_keys(ppd); 14188 } 14189 init_sc2vl_tables(dd); 14190 } 14191 14192 static void init_kdeth_qp(struct hfi1_devdata *dd) 14193 { 14194 /* user changed the KDETH_QP */ 14195 if (kdeth_qp != 0 && kdeth_qp >= 0xff) { 14196 /* out of range or illegal value */ 14197 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring"); 14198 kdeth_qp = 0; 14199 } 14200 if (kdeth_qp == 0) /* not set, or failed range check */ 14201 kdeth_qp = DEFAULT_KDETH_QP; 14202 14203 write_csr(dd, SEND_BTH_QP, 14204 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) << 14205 SEND_BTH_QP_KDETH_QP_SHIFT); 14206 14207 write_csr(dd, RCV_BTH_QP, 14208 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) << 14209 RCV_BTH_QP_KDETH_QP_SHIFT); 14210 } 14211 14212 /** 14213 * init_qpmap_table 14214 * @dd - device data 14215 * @first_ctxt - first context 14216 * @last_ctxt - first context 14217 * 14218 * This return sets the qpn mapping table that 14219 * is indexed by qpn[8:1]. 14220 * 14221 * The routine will round robin the 256 settings 14222 * from first_ctxt to last_ctxt. 14223 * 14224 * The first/last looks ahead to having specialized 14225 * receive contexts for mgmt and bypass. Normal 14226 * verbs traffic will assumed to be on a range 14227 * of receive contexts. 14228 */ 14229 static void init_qpmap_table(struct hfi1_devdata *dd, 14230 u32 first_ctxt, 14231 u32 last_ctxt) 14232 { 14233 u64 reg = 0; 14234 u64 regno = RCV_QP_MAP_TABLE; 14235 int i; 14236 u64 ctxt = first_ctxt; 14237 14238 for (i = 0; i < 256; i++) { 14239 reg |= ctxt << (8 * (i % 8)); 14240 ctxt++; 14241 if (ctxt > last_ctxt) 14242 ctxt = first_ctxt; 14243 if (i % 8 == 7) { 14244 write_csr(dd, regno, reg); 14245 reg = 0; 14246 regno += 8; 14247 } 14248 } 14249 14250 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 14251 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK); 14252 } 14253 14254 struct rsm_map_table { 14255 u64 map[NUM_MAP_REGS]; 14256 unsigned int used; 14257 }; 14258 14259 struct rsm_rule_data { 14260 u8 offset; 14261 u8 pkt_type; 14262 u32 field1_off; 14263 u32 field2_off; 14264 u32 index1_off; 14265 u32 index1_width; 14266 u32 index2_off; 14267 u32 index2_width; 14268 u32 mask1; 14269 u32 value1; 14270 u32 mask2; 14271 u32 value2; 14272 }; 14273 14274 /* 14275 * Return an initialized RMT map table for users to fill in. OK if it 14276 * returns NULL, indicating no table. 14277 */ 14278 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd) 14279 { 14280 struct rsm_map_table *rmt; 14281 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */ 14282 14283 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL); 14284 if (rmt) { 14285 memset(rmt->map, rxcontext, sizeof(rmt->map)); 14286 rmt->used = 0; 14287 } 14288 14289 return rmt; 14290 } 14291 14292 /* 14293 * Write the final RMT map table to the chip and free the table. OK if 14294 * table is NULL. 14295 */ 14296 static void complete_rsm_map_table(struct hfi1_devdata *dd, 14297 struct rsm_map_table *rmt) 14298 { 14299 int i; 14300 14301 if (rmt) { 14302 /* write table to chip */ 14303 for (i = 0; i < NUM_MAP_REGS; i++) 14304 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); 14305 14306 /* enable RSM */ 14307 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14308 } 14309 } 14310 14311 /* 14312 * Add a receive side mapping rule. 14313 */ 14314 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index, 14315 struct rsm_rule_data *rrd) 14316 { 14317 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 14318 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT | 14319 1ull << rule_index | /* enable bit */ 14320 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT); 14321 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 14322 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT | 14323 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT | 14324 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT | 14325 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT | 14326 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT | 14327 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT); 14328 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 14329 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT | 14330 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT | 14331 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT | 14332 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT); 14333 } 14334 14335 /* 14336 * Clear a receive side mapping rule. 14337 */ 14338 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14339 { 14340 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); 14341 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); 14342 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); 14343 } 14344 14345 /* return the number of RSM map table entries that will be used for QOS */ 14346 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 14347 unsigned int *np) 14348 { 14349 int i; 14350 unsigned int m, n; 14351 u8 max_by_vl = 0; 14352 14353 /* is QOS active at all? */ 14354 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS || 14355 num_vls == 1 || 14356 krcvqsset <= 1) 14357 goto no_qos; 14358 14359 /* determine bits for qpn */ 14360 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++) 14361 if (krcvqs[i] > max_by_vl) 14362 max_by_vl = krcvqs[i]; 14363 if (max_by_vl > 32) 14364 goto no_qos; 14365 m = ilog2(__roundup_pow_of_two(max_by_vl)); 14366 14367 /* determine bits for vl */ 14368 n = ilog2(__roundup_pow_of_two(num_vls)); 14369 14370 /* reject if too much is used */ 14371 if ((m + n) > 7) 14372 goto no_qos; 14373 14374 if (mp) 14375 *mp = m; 14376 if (np) 14377 *np = n; 14378 14379 return 1 << (m + n); 14380 14381 no_qos: 14382 if (mp) 14383 *mp = 0; 14384 if (np) 14385 *np = 0; 14386 return 0; 14387 } 14388 14389 /** 14390 * init_qos - init RX qos 14391 * @dd - device data 14392 * @rmt - RSM map table 14393 * 14394 * This routine initializes Rule 0 and the RSM map table to implement 14395 * quality of service (qos). 14396 * 14397 * If all of the limit tests succeed, qos is applied based on the array 14398 * interpretation of krcvqs where entry 0 is VL0. 14399 * 14400 * The number of vl bits (n) and the number of qpn bits (m) are computed to 14401 * feed both the RSM map table and the single rule. 14402 */ 14403 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt) 14404 { 14405 struct rsm_rule_data rrd; 14406 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m; 14407 unsigned int rmt_entries; 14408 u64 reg; 14409 14410 if (!rmt) 14411 goto bail; 14412 rmt_entries = qos_rmt_entries(dd, &m, &n); 14413 if (rmt_entries == 0) 14414 goto bail; 14415 qpns_per_vl = 1 << m; 14416 14417 /* enough room in the map table? */ 14418 rmt_entries = 1 << (m + n); 14419 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES) 14420 goto bail; 14421 14422 /* add qos entries to the the RSM map table */ 14423 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) { 14424 unsigned tctxt; 14425 14426 for (qpn = 0, tctxt = ctxt; 14427 krcvqs[i] && qpn < qpns_per_vl; qpn++) { 14428 unsigned idx, regoff, regidx; 14429 14430 /* generate the index the hardware will produce */ 14431 idx = rmt->used + ((qpn << n) ^ i); 14432 regoff = (idx % 8) * 8; 14433 regidx = idx / 8; 14434 /* replace default with context number */ 14435 reg = rmt->map[regidx]; 14436 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 14437 << regoff); 14438 reg |= (u64)(tctxt++) << regoff; 14439 rmt->map[regidx] = reg; 14440 if (tctxt == ctxt + krcvqs[i]) 14441 tctxt = ctxt; 14442 } 14443 ctxt += krcvqs[i]; 14444 } 14445 14446 rrd.offset = rmt->used; 14447 rrd.pkt_type = 2; 14448 rrd.field1_off = LRH_BTH_MATCH_OFFSET; 14449 rrd.field2_off = LRH_SC_MATCH_OFFSET; 14450 rrd.index1_off = LRH_SC_SELECT_OFFSET; 14451 rrd.index1_width = n; 14452 rrd.index2_off = QPN_SELECT_OFFSET; 14453 rrd.index2_width = m + n; 14454 rrd.mask1 = LRH_BTH_MASK; 14455 rrd.value1 = LRH_BTH_VALUE; 14456 rrd.mask2 = LRH_SC_MASK; 14457 rrd.value2 = LRH_SC_VALUE; 14458 14459 /* add rule 0 */ 14460 add_rsm_rule(dd, RSM_INS_VERBS, &rrd); 14461 14462 /* mark RSM map entries as used */ 14463 rmt->used += rmt_entries; 14464 /* map everything else to the mcast/err/vl15 context */ 14465 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT); 14466 dd->qos_shift = n + 1; 14467 return; 14468 bail: 14469 dd->qos_shift = 1; 14470 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1); 14471 } 14472 14473 static void init_user_fecn_handling(struct hfi1_devdata *dd, 14474 struct rsm_map_table *rmt) 14475 { 14476 struct rsm_rule_data rrd; 14477 u64 reg; 14478 int i, idx, regoff, regidx; 14479 u8 offset; 14480 14481 /* there needs to be enough room in the map table */ 14482 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) { 14483 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n"); 14484 return; 14485 } 14486 14487 /* 14488 * RSM will extract the destination context as an index into the 14489 * map table. The destination contexts are a sequential block 14490 * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive). 14491 * Map entries are accessed as offset + extracted value. Adjust 14492 * the added offset so this sequence can be placed anywhere in 14493 * the table - as long as the entries themselves do not wrap. 14494 * There are only enough bits in offset for the table size, so 14495 * start with that to allow for a "negative" offset. 14496 */ 14497 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used - 14498 (int)dd->first_dyn_alloc_ctxt); 14499 14500 for (i = dd->first_dyn_alloc_ctxt, idx = rmt->used; 14501 i < dd->num_rcv_contexts; i++, idx++) { 14502 /* replace with identity mapping */ 14503 regoff = (idx % 8) * 8; 14504 regidx = idx / 8; 14505 reg = rmt->map[regidx]; 14506 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff); 14507 reg |= (u64)i << regoff; 14508 rmt->map[regidx] = reg; 14509 } 14510 14511 /* 14512 * For RSM intercept of Expected FECN packets: 14513 * o packet type 0 - expected 14514 * o match on F (bit 95), using select/match 1, and 14515 * o match on SH (bit 133), using select/match 2. 14516 * 14517 * Use index 1 to extract the 8-bit receive context from DestQP 14518 * (start at bit 64). Use that as the RSM map table index. 14519 */ 14520 rrd.offset = offset; 14521 rrd.pkt_type = 0; 14522 rrd.field1_off = 95; 14523 rrd.field2_off = 133; 14524 rrd.index1_off = 64; 14525 rrd.index1_width = 8; 14526 rrd.index2_off = 0; 14527 rrd.index2_width = 0; 14528 rrd.mask1 = 1; 14529 rrd.value1 = 1; 14530 rrd.mask2 = 1; 14531 rrd.value2 = 1; 14532 14533 /* add rule 1 */ 14534 add_rsm_rule(dd, RSM_INS_FECN, &rrd); 14535 14536 rmt->used += dd->num_user_contexts; 14537 } 14538 14539 /* Initialize RSM for VNIC */ 14540 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd) 14541 { 14542 u8 i, j; 14543 u8 ctx_id = 0; 14544 u64 reg; 14545 u32 regoff; 14546 struct rsm_rule_data rrd; 14547 14548 if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) { 14549 dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n", 14550 dd->vnic.rmt_start); 14551 return; 14552 } 14553 14554 dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n", 14555 dd->vnic.rmt_start, 14556 dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES); 14557 14558 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */ 14559 regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8; 14560 reg = read_csr(dd, regoff); 14561 for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) { 14562 /* Update map register with vnic context */ 14563 j = (dd->vnic.rmt_start + i) % 8; 14564 reg &= ~(0xffllu << (j * 8)); 14565 reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8); 14566 /* Wrap up vnic ctx index */ 14567 ctx_id %= dd->vnic.num_ctxt; 14568 /* Write back map register */ 14569 if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) { 14570 dev_dbg(&(dd)->pcidev->dev, 14571 "Vnic rsm map reg[%d] =0x%llx\n", 14572 regoff - RCV_RSM_MAP_TABLE, reg); 14573 14574 write_csr(dd, regoff, reg); 14575 regoff += 8; 14576 if (i < (NUM_VNIC_MAP_ENTRIES - 1)) 14577 reg = read_csr(dd, regoff); 14578 } 14579 } 14580 14581 /* Add rule for vnic */ 14582 rrd.offset = dd->vnic.rmt_start; 14583 rrd.pkt_type = 4; 14584 /* Match 16B packets */ 14585 rrd.field1_off = L2_TYPE_MATCH_OFFSET; 14586 rrd.mask1 = L2_TYPE_MASK; 14587 rrd.value1 = L2_16B_VALUE; 14588 /* Match ETH L4 packets */ 14589 rrd.field2_off = L4_TYPE_MATCH_OFFSET; 14590 rrd.mask2 = L4_16B_TYPE_MASK; 14591 rrd.value2 = L4_16B_ETH_VALUE; 14592 /* Calc context from veswid and entropy */ 14593 rrd.index1_off = L4_16B_HDR_VESWID_OFFSET; 14594 rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES); 14595 rrd.index2_off = L2_16B_ENTROPY_OFFSET; 14596 rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES); 14597 add_rsm_rule(dd, RSM_INS_VNIC, &rrd); 14598 14599 /* Enable RSM if not already enabled */ 14600 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14601 } 14602 14603 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd) 14604 { 14605 clear_rsm_rule(dd, RSM_INS_VNIC); 14606 14607 /* Disable RSM if used only by vnic */ 14608 if (dd->vnic.rmt_start == 0) 14609 clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14610 } 14611 14612 static void init_rxe(struct hfi1_devdata *dd) 14613 { 14614 struct rsm_map_table *rmt; 14615 u64 val; 14616 14617 /* enable all receive errors */ 14618 write_csr(dd, RCV_ERR_MASK, ~0ull); 14619 14620 rmt = alloc_rsm_map_table(dd); 14621 /* set up QOS, including the QPN map table */ 14622 init_qos(dd, rmt); 14623 init_user_fecn_handling(dd, rmt); 14624 complete_rsm_map_table(dd, rmt); 14625 /* record number of used rsm map entries for vnic */ 14626 dd->vnic.rmt_start = rmt->used; 14627 kfree(rmt); 14628 14629 /* 14630 * make sure RcvCtrl.RcvWcb <= PCIe Device Control 14631 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config 14632 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one 14633 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and 14634 * Max_PayLoad_Size set to its minimum of 128. 14635 * 14636 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0 14637 * (64 bytes). Max_Payload_Size is possibly modified upward in 14638 * tune_pcie_caps() which is called after this routine. 14639 */ 14640 14641 /* Have 16 bytes (4DW) of bypass header available in header queue */ 14642 val = read_csr(dd, RCV_BYPASS); 14643 val &= ~RCV_BYPASS_HDR_SIZE_SMASK; 14644 val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) << 14645 RCV_BYPASS_HDR_SIZE_SHIFT); 14646 write_csr(dd, RCV_BYPASS, val); 14647 } 14648 14649 static void init_other(struct hfi1_devdata *dd) 14650 { 14651 /* enable all CCE errors */ 14652 write_csr(dd, CCE_ERR_MASK, ~0ull); 14653 /* enable *some* Misc errors */ 14654 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); 14655 /* enable all DC errors, except LCB */ 14656 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); 14657 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); 14658 } 14659 14660 /* 14661 * Fill out the given AU table using the given CU. A CU is defined in terms 14662 * AUs. The table is a an encoding: given the index, how many AUs does that 14663 * represent? 14664 * 14665 * NOTE: Assumes that the register layout is the same for the 14666 * local and remote tables. 14667 */ 14668 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu, 14669 u32 csr0to3, u32 csr4to7) 14670 { 14671 write_csr(dd, csr0to3, 14672 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT | 14673 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT | 14674 2ull * cu << 14675 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT | 14676 4ull * cu << 14677 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT); 14678 write_csr(dd, csr4to7, 14679 8ull * cu << 14680 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT | 14681 16ull * cu << 14682 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT | 14683 32ull * cu << 14684 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT | 14685 64ull * cu << 14686 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT); 14687 } 14688 14689 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14690 { 14691 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3, 14692 SEND_CM_LOCAL_AU_TABLE4_TO7); 14693 } 14694 14695 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14696 { 14697 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3, 14698 SEND_CM_REMOTE_AU_TABLE4_TO7); 14699 } 14700 14701 static void init_txe(struct hfi1_devdata *dd) 14702 { 14703 int i; 14704 14705 /* enable all PIO, SDMA, general, and Egress errors */ 14706 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); 14707 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); 14708 write_csr(dd, SEND_ERR_MASK, ~0ull); 14709 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); 14710 14711 /* enable all per-context and per-SDMA engine errors */ 14712 for (i = 0; i < dd->chip_send_contexts; i++) 14713 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull); 14714 for (i = 0; i < dd->chip_sdma_engines; i++) 14715 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull); 14716 14717 /* set the local CU to AU mapping */ 14718 assign_local_cm_au_table(dd, dd->vcu); 14719 14720 /* 14721 * Set reasonable default for Credit Return Timer 14722 * Don't set on Simulator - causes it to choke. 14723 */ 14724 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 14725 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); 14726 } 14727 14728 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14729 u16 jkey) 14730 { 14731 u8 hw_ctxt; 14732 u64 reg; 14733 14734 if (!rcd || !rcd->sc) 14735 return -EINVAL; 14736 14737 hw_ctxt = rcd->sc->hw_context; 14738 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */ 14739 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) << 14740 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT); 14741 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */ 14742 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY)) 14743 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK; 14744 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg); 14745 /* 14746 * Enable send-side J_KEY integrity check, unless this is A0 h/w 14747 */ 14748 if (!is_ax(dd)) { 14749 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14750 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14751 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14752 } 14753 14754 /* Enable J_KEY check on receive context. */ 14755 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK | 14756 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) << 14757 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT); 14758 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg); 14759 14760 return 0; 14761 } 14762 14763 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 14764 { 14765 u8 hw_ctxt; 14766 u64 reg; 14767 14768 if (!rcd || !rcd->sc) 14769 return -EINVAL; 14770 14771 hw_ctxt = rcd->sc->hw_context; 14772 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0); 14773 /* 14774 * Disable send-side J_KEY integrity check, unless this is A0 h/w. 14775 * This check would not have been enabled for A0 h/w, see 14776 * set_ctxt_jkey(). 14777 */ 14778 if (!is_ax(dd)) { 14779 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14780 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14781 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14782 } 14783 /* Turn off the J_KEY on the receive side */ 14784 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0); 14785 14786 return 0; 14787 } 14788 14789 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14790 u16 pkey) 14791 { 14792 u8 hw_ctxt; 14793 u64 reg; 14794 14795 if (!rcd || !rcd->sc) 14796 return -EINVAL; 14797 14798 hw_ctxt = rcd->sc->hw_context; 14799 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) << 14800 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT; 14801 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg); 14802 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14803 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14804 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK; 14805 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14806 14807 return 0; 14808 } 14809 14810 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt) 14811 { 14812 u8 hw_ctxt; 14813 u64 reg; 14814 14815 if (!ctxt || !ctxt->sc) 14816 return -EINVAL; 14817 14818 hw_ctxt = ctxt->sc->hw_context; 14819 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14820 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14821 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14822 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0); 14823 14824 return 0; 14825 } 14826 14827 /* 14828 * Start doing the clean up the the chip. Our clean up happens in multiple 14829 * stages and this is just the first. 14830 */ 14831 void hfi1_start_cleanup(struct hfi1_devdata *dd) 14832 { 14833 aspm_exit(dd); 14834 free_cntrs(dd); 14835 free_rcverr(dd); 14836 finish_chip_resources(dd); 14837 } 14838 14839 #define HFI_BASE_GUID(dev) \ 14840 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT)) 14841 14842 /* 14843 * Information can be shared between the two HFIs on the same ASIC 14844 * in the same OS. This function finds the peer device and sets 14845 * up a shared structure. 14846 */ 14847 static int init_asic_data(struct hfi1_devdata *dd) 14848 { 14849 unsigned long flags; 14850 struct hfi1_devdata *tmp, *peer = NULL; 14851 struct hfi1_asic_data *asic_data; 14852 int ret = 0; 14853 14854 /* pre-allocate the asic structure in case we are the first device */ 14855 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL); 14856 if (!asic_data) 14857 return -ENOMEM; 14858 14859 spin_lock_irqsave(&hfi1_devs_lock, flags); 14860 /* Find our peer device */ 14861 list_for_each_entry(tmp, &hfi1_dev_list, list) { 14862 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) && 14863 dd->unit != tmp->unit) { 14864 peer = tmp; 14865 break; 14866 } 14867 } 14868 14869 if (peer) { 14870 /* use already allocated structure */ 14871 dd->asic_data = peer->asic_data; 14872 kfree(asic_data); 14873 } else { 14874 dd->asic_data = asic_data; 14875 mutex_init(&dd->asic_data->asic_resource_mutex); 14876 } 14877 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */ 14878 spin_unlock_irqrestore(&hfi1_devs_lock, flags); 14879 14880 /* first one through - set up i2c devices */ 14881 if (!peer) 14882 ret = set_up_i2c(dd, dd->asic_data); 14883 14884 return ret; 14885 } 14886 14887 /* 14888 * Set dd->boardname. Use a generic name if a name is not returned from 14889 * EFI variable space. 14890 * 14891 * Return 0 on success, -ENOMEM if space could not be allocated. 14892 */ 14893 static int obtain_boardname(struct hfi1_devdata *dd) 14894 { 14895 /* generic board description */ 14896 const char generic[] = 14897 "Intel Omni-Path Host Fabric Interface Adapter 100 Series"; 14898 unsigned long size; 14899 int ret; 14900 14901 ret = read_hfi1_efi_var(dd, "description", &size, 14902 (void **)&dd->boardname); 14903 if (ret) { 14904 dd_dev_info(dd, "Board description not found\n"); 14905 /* use generic description */ 14906 dd->boardname = kstrdup(generic, GFP_KERNEL); 14907 if (!dd->boardname) 14908 return -ENOMEM; 14909 } 14910 return 0; 14911 } 14912 14913 /* 14914 * Check the interrupt registers to make sure that they are mapped correctly. 14915 * It is intended to help user identify any mismapping by VMM when the driver 14916 * is running in a VM. This function should only be called before interrupt 14917 * is set up properly. 14918 * 14919 * Return 0 on success, -EINVAL on failure. 14920 */ 14921 static int check_int_registers(struct hfi1_devdata *dd) 14922 { 14923 u64 reg; 14924 u64 all_bits = ~(u64)0; 14925 u64 mask; 14926 14927 /* Clear CceIntMask[0] to avoid raising any interrupts */ 14928 mask = read_csr(dd, CCE_INT_MASK); 14929 write_csr(dd, CCE_INT_MASK, 0ull); 14930 reg = read_csr(dd, CCE_INT_MASK); 14931 if (reg) 14932 goto err_exit; 14933 14934 /* Clear all interrupt status bits */ 14935 write_csr(dd, CCE_INT_CLEAR, all_bits); 14936 reg = read_csr(dd, CCE_INT_STATUS); 14937 if (reg) 14938 goto err_exit; 14939 14940 /* Set all interrupt status bits */ 14941 write_csr(dd, CCE_INT_FORCE, all_bits); 14942 reg = read_csr(dd, CCE_INT_STATUS); 14943 if (reg != all_bits) 14944 goto err_exit; 14945 14946 /* Restore the interrupt mask */ 14947 write_csr(dd, CCE_INT_CLEAR, all_bits); 14948 write_csr(dd, CCE_INT_MASK, mask); 14949 14950 return 0; 14951 err_exit: 14952 write_csr(dd, CCE_INT_MASK, mask); 14953 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n"); 14954 return -EINVAL; 14955 } 14956 14957 /** 14958 * Allocate and initialize the device structure for the hfi. 14959 * @dev: the pci_dev for hfi1_ib device 14960 * @ent: pci_device_id struct for this dev 14961 * 14962 * Also allocates, initializes, and returns the devdata struct for this 14963 * device instance 14964 * 14965 * This is global, and is called directly at init to set up the 14966 * chip-specific function pointers for later use. 14967 */ 14968 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, 14969 const struct pci_device_id *ent) 14970 { 14971 struct hfi1_devdata *dd; 14972 struct hfi1_pportdata *ppd; 14973 u64 reg; 14974 int i, ret; 14975 static const char * const inames[] = { /* implementation names */ 14976 "RTL silicon", 14977 "RTL VCS simulation", 14978 "RTL FPGA emulation", 14979 "Functional simulator" 14980 }; 14981 struct pci_dev *parent = pdev->bus->self; 14982 14983 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS * 14984 sizeof(struct hfi1_pportdata)); 14985 if (IS_ERR(dd)) 14986 goto bail; 14987 ppd = dd->pport; 14988 for (i = 0; i < dd->num_pports; i++, ppd++) { 14989 int vl; 14990 /* init common fields */ 14991 hfi1_init_pportdata(pdev, ppd, dd, 0, 1); 14992 /* DC supports 4 link widths */ 14993 ppd->link_width_supported = 14994 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X | 14995 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X; 14996 ppd->link_width_downgrade_supported = 14997 ppd->link_width_supported; 14998 /* start out enabling only 4X */ 14999 ppd->link_width_enabled = OPA_LINK_WIDTH_4X; 15000 ppd->link_width_downgrade_enabled = 15001 ppd->link_width_downgrade_supported; 15002 /* link width active is 0 when link is down */ 15003 /* link width downgrade active is 0 when link is down */ 15004 15005 if (num_vls < HFI1_MIN_VLS_SUPPORTED || 15006 num_vls > HFI1_MAX_VLS_SUPPORTED) { 15007 dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n", 15008 num_vls, HFI1_MAX_VLS_SUPPORTED); 15009 num_vls = HFI1_MAX_VLS_SUPPORTED; 15010 } 15011 ppd->vls_supported = num_vls; 15012 ppd->vls_operational = ppd->vls_supported; 15013 /* Set the default MTU. */ 15014 for (vl = 0; vl < num_vls; vl++) 15015 dd->vld[vl].mtu = hfi1_max_mtu; 15016 dd->vld[15].mtu = MAX_MAD_PACKET; 15017 /* 15018 * Set the initial values to reasonable default, will be set 15019 * for real when link is up. 15020 */ 15021 ppd->overrun_threshold = 0x4; 15022 ppd->phy_error_threshold = 0xf; 15023 ppd->port_crc_mode_enabled = link_crc_mask; 15024 /* initialize supported LTP CRC mode */ 15025 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 15026 /* initialize enabled LTP CRC mode */ 15027 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4; 15028 /* start in offline */ 15029 ppd->host_link_state = HLS_DN_OFFLINE; 15030 init_vl_arb_caches(ppd); 15031 } 15032 15033 /* 15034 * Do remaining PCIe setup and save PCIe values in dd. 15035 * Any error printing is already done by the init code. 15036 * On return, we have the chip mapped. 15037 */ 15038 ret = hfi1_pcie_ddinit(dd, pdev); 15039 if (ret < 0) 15040 goto bail_free; 15041 15042 /* Save PCI space registers to rewrite after device reset */ 15043 ret = save_pci_variables(dd); 15044 if (ret < 0) 15045 goto bail_cleanup; 15046 15047 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT) 15048 & CCE_REVISION_CHIP_REV_MAJOR_MASK; 15049 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT) 15050 & CCE_REVISION_CHIP_REV_MINOR_MASK; 15051 15052 /* 15053 * Check interrupt registers mapping if the driver has no access to 15054 * the upstream component. In this case, it is likely that the driver 15055 * is running in a VM. 15056 */ 15057 if (!parent) { 15058 ret = check_int_registers(dd); 15059 if (ret) 15060 goto bail_cleanup; 15061 } 15062 15063 /* 15064 * obtain the hardware ID - NOT related to unit, which is a 15065 * software enumeration 15066 */ 15067 reg = read_csr(dd, CCE_REVISION2); 15068 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT) 15069 & CCE_REVISION2_HFI_ID_MASK; 15070 /* the variable size will remove unwanted bits */ 15071 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT; 15072 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT; 15073 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n", 15074 dd->icode < ARRAY_SIZE(inames) ? 15075 inames[dd->icode] : "unknown", (int)dd->irev); 15076 15077 /* speeds the hardware can support */ 15078 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G; 15079 /* speeds allowed to run at */ 15080 dd->pport->link_speed_enabled = dd->pport->link_speed_supported; 15081 /* give a reasonable active value, will be set on link up */ 15082 dd->pport->link_speed_active = OPA_LINK_SPEED_25G; 15083 15084 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS); 15085 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS); 15086 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES); 15087 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE); 15088 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE); 15089 /* fix up link widths for emulation _p */ 15090 ppd = dd->pport; 15091 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) { 15092 ppd->link_width_supported = 15093 ppd->link_width_enabled = 15094 ppd->link_width_downgrade_supported = 15095 ppd->link_width_downgrade_enabled = 15096 OPA_LINK_WIDTH_1X; 15097 } 15098 /* insure num_vls isn't larger than number of sdma engines */ 15099 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) { 15100 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n", 15101 num_vls, dd->chip_sdma_engines); 15102 num_vls = dd->chip_sdma_engines; 15103 ppd->vls_supported = dd->chip_sdma_engines; 15104 ppd->vls_operational = ppd->vls_supported; 15105 } 15106 15107 /* 15108 * Convert the ns parameter to the 64 * cclocks used in the CSR. 15109 * Limit the max if larger than the field holds. If timeout is 15110 * non-zero, then the calculated field will be at least 1. 15111 * 15112 * Must be after icode is set up - the cclock rate depends 15113 * on knowing the hardware being used. 15114 */ 15115 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64; 15116 if (dd->rcv_intr_timeout_csr > 15117 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK) 15118 dd->rcv_intr_timeout_csr = 15119 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK; 15120 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout) 15121 dd->rcv_intr_timeout_csr = 1; 15122 15123 /* needs to be done before we look for the peer device */ 15124 read_guid(dd); 15125 15126 /* set up shared ASIC data with peer device */ 15127 ret = init_asic_data(dd); 15128 if (ret) 15129 goto bail_cleanup; 15130 15131 /* obtain chip sizes, reset chip CSRs */ 15132 ret = init_chip(dd); 15133 if (ret) 15134 goto bail_cleanup; 15135 15136 /* read in the PCIe link speed information */ 15137 ret = pcie_speeds(dd); 15138 if (ret) 15139 goto bail_cleanup; 15140 15141 /* call before get_platform_config(), after init_chip_resources() */ 15142 ret = eprom_init(dd); 15143 if (ret) 15144 goto bail_free_rcverr; 15145 15146 /* Needs to be called before hfi1_firmware_init */ 15147 get_platform_config(dd); 15148 15149 /* read in firmware */ 15150 ret = hfi1_firmware_init(dd); 15151 if (ret) 15152 goto bail_cleanup; 15153 15154 /* 15155 * In general, the PCIe Gen3 transition must occur after the 15156 * chip has been idled (so it won't initiate any PCIe transactions 15157 * e.g. an interrupt) and before the driver changes any registers 15158 * (the transition will reset the registers). 15159 * 15160 * In particular, place this call after: 15161 * - init_chip() - the chip will not initiate any PCIe transactions 15162 * - pcie_speeds() - reads the current link speed 15163 * - hfi1_firmware_init() - the needed firmware is ready to be 15164 * downloaded 15165 */ 15166 ret = do_pcie_gen3_transition(dd); 15167 if (ret) 15168 goto bail_cleanup; 15169 15170 /* start setting dd values and adjusting CSRs */ 15171 init_early_variables(dd); 15172 15173 parse_platform_config(dd); 15174 15175 ret = obtain_boardname(dd); 15176 if (ret) 15177 goto bail_cleanup; 15178 15179 snprintf(dd->boardversion, BOARD_VERS_MAX, 15180 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n", 15181 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN, 15182 (u32)dd->majrev, 15183 (u32)dd->minrev, 15184 (dd->revision >> CCE_REVISION_SW_SHIFT) 15185 & CCE_REVISION_SW_MASK); 15186 15187 ret = set_up_context_variables(dd); 15188 if (ret) 15189 goto bail_cleanup; 15190 15191 /* set initial RXE CSRs */ 15192 init_rxe(dd); 15193 /* set initial TXE CSRs */ 15194 init_txe(dd); 15195 /* set initial non-RXE, non-TXE CSRs */ 15196 init_other(dd); 15197 /* set up KDETH QP prefix in both RX and TX CSRs */ 15198 init_kdeth_qp(dd); 15199 15200 ret = hfi1_dev_affinity_init(dd); 15201 if (ret) 15202 goto bail_cleanup; 15203 15204 /* send contexts must be set up before receive contexts */ 15205 ret = init_send_contexts(dd); 15206 if (ret) 15207 goto bail_cleanup; 15208 15209 ret = hfi1_create_kctxts(dd); 15210 if (ret) 15211 goto bail_cleanup; 15212 15213 /* 15214 * Initialize aspm, to be done after gen3 transition and setting up 15215 * contexts and before enabling interrupts 15216 */ 15217 aspm_init(dd); 15218 15219 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE; 15220 /* 15221 * rcd[0] is guaranteed to be valid by this point. Also, all 15222 * context are using the same value, as per the module parameter. 15223 */ 15224 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32); 15225 15226 ret = init_pervl_scs(dd); 15227 if (ret) 15228 goto bail_cleanup; 15229 15230 /* sdma init */ 15231 for (i = 0; i < dd->num_pports; ++i) { 15232 ret = sdma_init(dd, i); 15233 if (ret) 15234 goto bail_cleanup; 15235 } 15236 15237 /* use contexts created by hfi1_create_kctxts */ 15238 ret = set_up_interrupts(dd); 15239 if (ret) 15240 goto bail_cleanup; 15241 15242 ret = hfi1_comp_vectors_set_up(dd); 15243 if (ret) 15244 goto bail_clear_intr; 15245 15246 /* set up LCB access - must be after set_up_interrupts() */ 15247 init_lcb_access(dd); 15248 15249 /* 15250 * Serial number is created from the base guid: 15251 * [27:24] = base guid [38:35] 15252 * [23: 0] = base guid [23: 0] 15253 */ 15254 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n", 15255 (dd->base_guid & 0xFFFFFF) | 15256 ((dd->base_guid >> 11) & 0xF000000)); 15257 15258 dd->oui1 = dd->base_guid >> 56 & 0xFF; 15259 dd->oui2 = dd->base_guid >> 48 & 0xFF; 15260 dd->oui3 = dd->base_guid >> 40 & 0xFF; 15261 15262 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */ 15263 if (ret) 15264 goto bail_clear_intr; 15265 15266 thermal_init(dd); 15267 15268 ret = init_cntrs(dd); 15269 if (ret) 15270 goto bail_clear_intr; 15271 15272 ret = init_rcverr(dd); 15273 if (ret) 15274 goto bail_free_cntrs; 15275 15276 init_completion(&dd->user_comp); 15277 15278 /* The user refcount starts with one to inidicate an active device */ 15279 atomic_set(&dd->user_refcount, 1); 15280 15281 goto bail; 15282 15283 bail_free_rcverr: 15284 free_rcverr(dd); 15285 bail_free_cntrs: 15286 free_cntrs(dd); 15287 bail_clear_intr: 15288 hfi1_comp_vectors_clean_up(dd); 15289 hfi1_clean_up_interrupts(dd); 15290 bail_cleanup: 15291 hfi1_pcie_ddcleanup(dd); 15292 bail_free: 15293 hfi1_free_devdata(dd); 15294 dd = ERR_PTR(ret); 15295 bail: 15296 return dd; 15297 } 15298 15299 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate, 15300 u32 dw_len) 15301 { 15302 u32 delta_cycles; 15303 u32 current_egress_rate = ppd->current_egress_rate; 15304 /* rates here are in units of 10^6 bits/sec */ 15305 15306 if (desired_egress_rate == -1) 15307 return 0; /* shouldn't happen */ 15308 15309 if (desired_egress_rate >= current_egress_rate) 15310 return 0; /* we can't help go faster, only slower */ 15311 15312 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) - 15313 egress_cycles(dw_len * 4, current_egress_rate); 15314 15315 return (u16)delta_cycles; 15316 } 15317 15318 /** 15319 * create_pbc - build a pbc for transmission 15320 * @flags: special case flags or-ed in built pbc 15321 * @srate: static rate 15322 * @vl: vl 15323 * @dwlen: dword length (header words + data words + pbc words) 15324 * 15325 * Create a PBC with the given flags, rate, VL, and length. 15326 * 15327 * NOTE: The PBC created will not insert any HCRC - all callers but one are 15328 * for verbs, which does not use this PSM feature. The lone other caller 15329 * is for the diagnostic interface which calls this if the user does not 15330 * supply their own PBC. 15331 */ 15332 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, 15333 u32 dw_len) 15334 { 15335 u64 pbc, delay = 0; 15336 15337 if (unlikely(srate_mbs)) 15338 delay = delay_cycles(ppd, srate_mbs, dw_len); 15339 15340 pbc = flags 15341 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT) 15342 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT) 15343 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT 15344 | (dw_len & PBC_LENGTH_DWS_MASK) 15345 << PBC_LENGTH_DWS_SHIFT; 15346 15347 return pbc; 15348 } 15349 15350 #define SBUS_THERMAL 0x4f 15351 #define SBUS_THERM_MONITOR_MODE 0x1 15352 15353 #define THERM_FAILURE(dev, ret, reason) \ 15354 dd_dev_err((dd), \ 15355 "Thermal sensor initialization failed: %s (%d)\n", \ 15356 (reason), (ret)) 15357 15358 /* 15359 * Initialize the thermal sensor. 15360 * 15361 * After initialization, enable polling of thermal sensor through 15362 * SBus interface. In order for this to work, the SBus Master 15363 * firmware has to be loaded due to the fact that the HW polling 15364 * logic uses SBus interrupts, which are not supported with 15365 * default firmware. Otherwise, no data will be returned through 15366 * the ASIC_STS_THERM CSR. 15367 */ 15368 static int thermal_init(struct hfi1_devdata *dd) 15369 { 15370 int ret = 0; 15371 15372 if (dd->icode != ICODE_RTL_SILICON || 15373 check_chip_resource(dd, CR_THERM_INIT, NULL)) 15374 return ret; 15375 15376 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 15377 if (ret) { 15378 THERM_FAILURE(dd, ret, "Acquire SBus"); 15379 return ret; 15380 } 15381 15382 dd_dev_info(dd, "Initializing thermal sensor\n"); 15383 /* Disable polling of thermal readings */ 15384 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 15385 msleep(100); 15386 /* Thermal Sensor Initialization */ 15387 /* Step 1: Reset the Thermal SBus Receiver */ 15388 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15389 RESET_SBUS_RECEIVER, 0); 15390 if (ret) { 15391 THERM_FAILURE(dd, ret, "Bus Reset"); 15392 goto done; 15393 } 15394 /* Step 2: Set Reset bit in Thermal block */ 15395 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15396 WRITE_SBUS_RECEIVER, 0x1); 15397 if (ret) { 15398 THERM_FAILURE(dd, ret, "Therm Block Reset"); 15399 goto done; 15400 } 15401 /* Step 3: Write clock divider value (100MHz -> 2MHz) */ 15402 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1, 15403 WRITE_SBUS_RECEIVER, 0x32); 15404 if (ret) { 15405 THERM_FAILURE(dd, ret, "Write Clock Div"); 15406 goto done; 15407 } 15408 /* Step 4: Select temperature mode */ 15409 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3, 15410 WRITE_SBUS_RECEIVER, 15411 SBUS_THERM_MONITOR_MODE); 15412 if (ret) { 15413 THERM_FAILURE(dd, ret, "Write Mode Sel"); 15414 goto done; 15415 } 15416 /* Step 5: De-assert block reset and start conversion */ 15417 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15418 WRITE_SBUS_RECEIVER, 0x2); 15419 if (ret) { 15420 THERM_FAILURE(dd, ret, "Write Reset Deassert"); 15421 goto done; 15422 } 15423 /* Step 5.1: Wait for first conversion (21.5ms per spec) */ 15424 msleep(22); 15425 15426 /* Enable polling of thermal readings */ 15427 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 15428 15429 /* Set initialized flag */ 15430 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0); 15431 if (ret) 15432 THERM_FAILURE(dd, ret, "Unable to set thermal init flag"); 15433 15434 done: 15435 release_chip_resource(dd, CR_SBUS); 15436 return ret; 15437 } 15438 15439 static void handle_temp_err(struct hfi1_devdata *dd) 15440 { 15441 struct hfi1_pportdata *ppd = &dd->pport[0]; 15442 /* 15443 * Thermal Critical Interrupt 15444 * Put the device into forced freeze mode, take link down to 15445 * offline, and put DC into reset. 15446 */ 15447 dd_dev_emerg(dd, 15448 "Critical temperature reached! Forcing device into freeze mode!\n"); 15449 dd->flags |= HFI1_FORCED_FREEZE; 15450 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT); 15451 /* 15452 * Shut DC down as much and as quickly as possible. 15453 * 15454 * Step 1: Take the link down to OFFLINE. This will cause the 15455 * 8051 to put the Serdes in reset. However, we don't want to 15456 * go through the entire link state machine since we want to 15457 * shutdown ASAP. Furthermore, this is not a graceful shutdown 15458 * but rather an attempt to save the chip. 15459 * Code below is almost the same as quiet_serdes() but avoids 15460 * all the extra work and the sleeps. 15461 */ 15462 ppd->driver_link_ready = 0; 15463 ppd->link_enabled = 0; 15464 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) | 15465 PLS_OFFLINE); 15466 /* 15467 * Step 2: Shutdown LCB and 8051 15468 * After shutdown, do not restore DC_CFG_RESET value. 15469 */ 15470 dc_shutdown(dd); 15471 } 15472