1 /* 2 * Copyright(c) 2015 - 2017 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 /* 49 * This file contains all of the code that is specific to the HFI chip 50 */ 51 52 #include <linux/pci.h> 53 #include <linux/delay.h> 54 #include <linux/interrupt.h> 55 #include <linux/module.h> 56 57 #include "hfi.h" 58 #include "trace.h" 59 #include "mad.h" 60 #include "pio.h" 61 #include "sdma.h" 62 #include "eprom.h" 63 #include "efivar.h" 64 #include "platform.h" 65 #include "aspm.h" 66 #include "affinity.h" 67 #include "debugfs.h" 68 69 #define NUM_IB_PORTS 1 70 71 uint kdeth_qp; 72 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO); 73 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix"); 74 75 uint num_vls = HFI1_MAX_VLS_SUPPORTED; 76 module_param(num_vls, uint, S_IRUGO); 77 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 78 79 /* 80 * Default time to aggregate two 10K packets from the idle state 81 * (timer not running). The timer starts at the end of the first packet, 82 * so only the time for one 10K packet and header plus a bit extra is needed. 83 * 10 * 1024 + 64 header byte = 10304 byte 84 * 10304 byte / 12.5 GB/s = 824.32ns 85 */ 86 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */ 87 module_param(rcv_intr_timeout, uint, S_IRUGO); 88 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns"); 89 90 uint rcv_intr_count = 16; /* same as qib */ 91 module_param(rcv_intr_count, uint, S_IRUGO); 92 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count"); 93 94 ushort link_crc_mask = SUPPORTED_CRCS; 95 module_param(link_crc_mask, ushort, S_IRUGO); 96 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link"); 97 98 uint loopback; 99 module_param_named(loopback, loopback, uint, S_IRUGO); 100 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable"); 101 102 /* Other driver tunables */ 103 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/ 104 static ushort crc_14b_sideband = 1; 105 static uint use_flr = 1; 106 uint quick_linkup; /* skip LNI */ 107 108 struct flag_table { 109 u64 flag; /* the flag */ 110 char *str; /* description string */ 111 u16 extra; /* extra information */ 112 u16 unused0; 113 u32 unused1; 114 }; 115 116 /* str must be a string constant */ 117 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra} 118 #define FLAG_ENTRY0(str, flag) {flag, str, 0} 119 120 /* Send Error Consequences */ 121 #define SEC_WRITE_DROPPED 0x1 122 #define SEC_PACKET_DROPPED 0x2 123 #define SEC_SC_HALTED 0x4 /* per-context only */ 124 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */ 125 126 #define DEFAULT_KRCVQS 2 127 #define MIN_KERNEL_KCTXTS 2 128 #define FIRST_KERNEL_KCTXT 1 129 130 /* 131 * RSM instance allocation 132 * 0 - Verbs 133 * 1 - User Fecn Handling 134 * 2 - Vnic 135 */ 136 #define RSM_INS_VERBS 0 137 #define RSM_INS_FECN 1 138 #define RSM_INS_VNIC 2 139 140 /* Bit offset into the GUID which carries HFI id information */ 141 #define GUID_HFI_INDEX_SHIFT 39 142 143 /* extract the emulation revision */ 144 #define emulator_rev(dd) ((dd)->irev >> 8) 145 /* parallel and serial emulation versions are 3 and 4 respectively */ 146 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3) 147 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4) 148 149 /* RSM fields for Verbs */ 150 /* packet type */ 151 #define IB_PACKET_TYPE 2ull 152 #define QW_SHIFT 6ull 153 /* QPN[7..1] */ 154 #define QPN_WIDTH 7ull 155 156 /* LRH.BTH: QW 0, OFFSET 48 - for match */ 157 #define LRH_BTH_QW 0ull 158 #define LRH_BTH_BIT_OFFSET 48ull 159 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off)) 160 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET) 161 #define LRH_BTH_SELECT 162 #define LRH_BTH_MASK 3ull 163 #define LRH_BTH_VALUE 2ull 164 165 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */ 166 #define LRH_SC_QW 0ull 167 #define LRH_SC_BIT_OFFSET 56ull 168 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off)) 169 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET) 170 #define LRH_SC_MASK 128ull 171 #define LRH_SC_VALUE 0ull 172 173 /* SC[n..0] QW 0, OFFSET 60 - for select */ 174 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull)) 175 176 /* QPN[m+n:1] QW 1, OFFSET 1 */ 177 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull)) 178 179 /* RSM fields for Vnic */ 180 /* L2_TYPE: QW 0, OFFSET 61 - for match */ 181 #define L2_TYPE_QW 0ull 182 #define L2_TYPE_BIT_OFFSET 61ull 183 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off)) 184 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET) 185 #define L2_TYPE_MASK 3ull 186 #define L2_16B_VALUE 2ull 187 188 /* L4_TYPE QW 1, OFFSET 0 - for match */ 189 #define L4_TYPE_QW 1ull 190 #define L4_TYPE_BIT_OFFSET 0ull 191 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off)) 192 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET) 193 #define L4_16B_TYPE_MASK 0xFFull 194 #define L4_16B_ETH_VALUE 0x78ull 195 196 /* 16B VESWID - for select */ 197 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull)) 198 /* 16B ENTROPY - for select */ 199 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull)) 200 201 /* defines to build power on SC2VL table */ 202 #define SC2VL_VAL( \ 203 num, \ 204 sc0, sc0val, \ 205 sc1, sc1val, \ 206 sc2, sc2val, \ 207 sc3, sc3val, \ 208 sc4, sc4val, \ 209 sc5, sc5val, \ 210 sc6, sc6val, \ 211 sc7, sc7val) \ 212 ( \ 213 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \ 214 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \ 215 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \ 216 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \ 217 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \ 218 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \ 219 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \ 220 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \ 221 ) 222 223 #define DC_SC_VL_VAL( \ 224 range, \ 225 e0, e0val, \ 226 e1, e1val, \ 227 e2, e2val, \ 228 e3, e3val, \ 229 e4, e4val, \ 230 e5, e5val, \ 231 e6, e6val, \ 232 e7, e7val, \ 233 e8, e8val, \ 234 e9, e9val, \ 235 e10, e10val, \ 236 e11, e11val, \ 237 e12, e12val, \ 238 e13, e13val, \ 239 e14, e14val, \ 240 e15, e15val) \ 241 ( \ 242 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \ 243 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \ 244 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \ 245 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \ 246 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \ 247 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \ 248 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \ 249 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \ 250 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \ 251 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \ 252 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \ 253 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \ 254 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \ 255 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \ 256 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \ 257 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \ 258 ) 259 260 /* all CceStatus sub-block freeze bits */ 261 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \ 262 | CCE_STATUS_RXE_FROZE_SMASK \ 263 | CCE_STATUS_TXE_FROZE_SMASK \ 264 | CCE_STATUS_TXE_PIO_FROZE_SMASK) 265 /* all CceStatus sub-block TXE pause bits */ 266 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \ 267 | CCE_STATUS_TXE_PAUSED_SMASK \ 268 | CCE_STATUS_SDMA_PAUSED_SMASK) 269 /* all CceStatus sub-block RXE pause bits */ 270 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK 271 272 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL 273 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF 274 275 /* 276 * CCE Error flags. 277 */ 278 static struct flag_table cce_err_status_flags[] = { 279 /* 0*/ FLAG_ENTRY0("CceCsrParityErr", 280 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK), 281 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr", 282 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK), 283 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr", 284 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK), 285 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr", 286 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK), 287 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr", 288 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK), 289 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr", 290 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK), 291 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr", 292 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK), 293 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr", 294 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK), 295 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr", 296 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK), 297 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 298 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK), 299 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 300 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK), 301 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError", 302 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK), 303 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError", 304 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK), 305 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr", 306 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK), 307 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr", 308 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK), 309 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr", 310 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK), 311 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr", 312 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK), 313 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr", 314 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK), 315 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr", 316 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK), 317 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr", 318 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK), 319 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr", 320 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK), 321 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr", 322 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK), 323 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr", 324 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK), 325 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr", 326 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK), 327 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr", 328 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK), 329 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr", 330 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK), 331 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr", 332 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK), 333 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr", 334 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK), 335 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr", 336 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK), 337 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr", 338 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK), 339 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr", 340 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK), 341 /*31*/ FLAG_ENTRY0("LATriggered", 342 CCE_ERR_STATUS_LA_TRIGGERED_SMASK), 343 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr", 344 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK), 345 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr", 346 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK), 347 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr", 348 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK), 349 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr", 350 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK), 351 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr", 352 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK), 353 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr", 354 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK), 355 /*38*/ FLAG_ENTRY0("CceIntMapCorErr", 356 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK), 357 /*39*/ FLAG_ENTRY0("CceIntMapUncErr", 358 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK), 359 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr", 360 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK), 361 /*41-63 reserved*/ 362 }; 363 364 /* 365 * Misc Error flags 366 */ 367 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK 368 static struct flag_table misc_err_status_flags[] = { 369 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)), 370 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)), 371 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)), 372 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)), 373 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)), 374 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)), 375 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)), 376 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)), 377 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)), 378 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)), 379 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)), 380 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)), 381 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL)) 382 }; 383 384 /* 385 * TXE PIO Error flags and consequences 386 */ 387 static struct flag_table pio_err_status_flags[] = { 388 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt", 389 SEC_WRITE_DROPPED, 390 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK), 391 /* 1*/ FLAG_ENTRY("PioWriteAddrParity", 392 SEC_SPC_FREEZE, 393 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK), 394 /* 2*/ FLAG_ENTRY("PioCsrParity", 395 SEC_SPC_FREEZE, 396 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK), 397 /* 3*/ FLAG_ENTRY("PioSbMemFifo0", 398 SEC_SPC_FREEZE, 399 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK), 400 /* 4*/ FLAG_ENTRY("PioSbMemFifo1", 401 SEC_SPC_FREEZE, 402 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK), 403 /* 5*/ FLAG_ENTRY("PioPccFifoParity", 404 SEC_SPC_FREEZE, 405 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK), 406 /* 6*/ FLAG_ENTRY("PioPecFifoParity", 407 SEC_SPC_FREEZE, 408 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK), 409 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity", 410 SEC_SPC_FREEZE, 411 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK), 412 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity", 413 SEC_SPC_FREEZE, 414 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK), 415 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr", 416 SEC_SPC_FREEZE, 417 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK), 418 /*10*/ FLAG_ENTRY("PioSmPktResetParity", 419 SEC_SPC_FREEZE, 420 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK), 421 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc", 422 SEC_SPC_FREEZE, 423 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK), 424 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc", 425 SEC_SPC_FREEZE, 426 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK), 427 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor", 428 0, 429 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK), 430 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor", 431 0, 432 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK), 433 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity", 434 SEC_SPC_FREEZE, 435 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK), 436 /*16*/ FLAG_ENTRY("PioPpmcPblFifo", 437 SEC_SPC_FREEZE, 438 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK), 439 /*17*/ FLAG_ENTRY("PioInitSmIn", 440 0, 441 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK), 442 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm", 443 SEC_SPC_FREEZE, 444 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK), 445 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc", 446 SEC_SPC_FREEZE, 447 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK), 448 /*20*/ FLAG_ENTRY("PioHostAddrMemCor", 449 0, 450 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK), 451 /*21*/ FLAG_ENTRY("PioWriteDataParity", 452 SEC_SPC_FREEZE, 453 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK), 454 /*22*/ FLAG_ENTRY("PioStateMachine", 455 SEC_SPC_FREEZE, 456 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK), 457 /*23*/ FLAG_ENTRY("PioWriteQwValidParity", 458 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 459 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK), 460 /*24*/ FLAG_ENTRY("PioBlockQwCountParity", 461 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 462 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK), 463 /*25*/ FLAG_ENTRY("PioVlfVlLenParity", 464 SEC_SPC_FREEZE, 465 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK), 466 /*26*/ FLAG_ENTRY("PioVlfSopParity", 467 SEC_SPC_FREEZE, 468 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK), 469 /*27*/ FLAG_ENTRY("PioVlFifoParity", 470 SEC_SPC_FREEZE, 471 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK), 472 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity", 473 SEC_SPC_FREEZE, 474 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK), 475 /*29*/ FLAG_ENTRY("PioPpmcSopLen", 476 SEC_SPC_FREEZE, 477 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK), 478 /*30-31 reserved*/ 479 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity", 480 SEC_SPC_FREEZE, 481 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK), 482 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity", 483 SEC_SPC_FREEZE, 484 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK), 485 /*34*/ FLAG_ENTRY("PioPccSopHeadParity", 486 SEC_SPC_FREEZE, 487 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK), 488 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr", 489 SEC_SPC_FREEZE, 490 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK), 491 /*36-63 reserved*/ 492 }; 493 494 /* TXE PIO errors that cause an SPC freeze */ 495 #define ALL_PIO_FREEZE_ERR \ 496 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \ 497 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \ 498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \ 499 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \ 500 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \ 501 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \ 502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \ 503 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 504 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \ 505 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \ 506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \ 507 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \ 508 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \ 509 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \ 510 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \ 511 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \ 512 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \ 513 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \ 514 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \ 515 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 516 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \ 517 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \ 518 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \ 519 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \ 520 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \ 521 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 522 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 523 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 524 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK) 525 526 /* 527 * TXE SDMA Error flags 528 */ 529 static struct flag_table sdma_err_status_flags[] = { 530 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr", 531 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK), 532 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr", 533 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK), 534 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr", 535 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK), 536 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr", 537 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK), 538 /*04-63 reserved*/ 539 }; 540 541 /* TXE SDMA errors that cause an SPC freeze */ 542 #define ALL_SDMA_FREEZE_ERR \ 543 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \ 544 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \ 545 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK) 546 547 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */ 548 #define PORT_DISCARD_EGRESS_ERRS \ 549 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \ 550 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \ 551 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK) 552 553 /* 554 * TXE Egress Error flags 555 */ 556 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK 557 static struct flag_table egress_err_status_flags[] = { 558 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)), 559 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)), 560 /* 2 reserved */ 561 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr", 562 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)), 563 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)), 564 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)), 565 /* 6 reserved */ 566 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr", 567 SEES(TX_PIO_LAUNCH_INTF_PARITY)), 568 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr", 569 SEES(TX_SDMA_LAUNCH_INTF_PARITY)), 570 /* 9-10 reserved */ 571 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr", 572 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)), 573 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)), 574 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)), 575 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)), 576 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)), 577 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr", 578 SEES(TX_SDMA0_DISALLOWED_PACKET)), 579 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr", 580 SEES(TX_SDMA1_DISALLOWED_PACKET)), 581 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr", 582 SEES(TX_SDMA2_DISALLOWED_PACKET)), 583 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr", 584 SEES(TX_SDMA3_DISALLOWED_PACKET)), 585 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr", 586 SEES(TX_SDMA4_DISALLOWED_PACKET)), 587 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr", 588 SEES(TX_SDMA5_DISALLOWED_PACKET)), 589 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr", 590 SEES(TX_SDMA6_DISALLOWED_PACKET)), 591 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr", 592 SEES(TX_SDMA7_DISALLOWED_PACKET)), 593 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr", 594 SEES(TX_SDMA8_DISALLOWED_PACKET)), 595 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr", 596 SEES(TX_SDMA9_DISALLOWED_PACKET)), 597 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr", 598 SEES(TX_SDMA10_DISALLOWED_PACKET)), 599 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr", 600 SEES(TX_SDMA11_DISALLOWED_PACKET)), 601 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr", 602 SEES(TX_SDMA12_DISALLOWED_PACKET)), 603 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr", 604 SEES(TX_SDMA13_DISALLOWED_PACKET)), 605 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr", 606 SEES(TX_SDMA14_DISALLOWED_PACKET)), 607 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr", 608 SEES(TX_SDMA15_DISALLOWED_PACKET)), 609 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr", 610 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)), 611 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr", 612 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)), 613 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr", 614 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)), 615 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr", 616 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)), 617 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr", 618 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)), 619 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr", 620 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)), 621 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr", 622 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)), 623 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr", 624 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)), 625 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr", 626 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)), 627 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)), 628 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)), 629 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)), 630 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)), 631 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)), 632 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)), 633 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)), 634 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)), 635 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)), 636 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)), 637 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)), 638 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)), 639 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)), 640 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)), 641 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)), 642 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)), 643 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)), 644 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)), 645 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)), 646 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)), 647 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)), 648 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr", 649 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)), 650 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr", 651 SEES(TX_READ_PIO_MEMORY_CSR_UNC)), 652 }; 653 654 /* 655 * TXE Egress Error Info flags 656 */ 657 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK 658 static struct flag_table egress_err_info_flags[] = { 659 /* 0*/ FLAG_ENTRY0("Reserved", 0ull), 660 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)), 661 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 662 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 663 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)), 664 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)), 665 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)), 666 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)), 667 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)), 668 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)), 669 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)), 670 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)), 671 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)), 672 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)), 673 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)), 674 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)), 675 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)), 676 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)), 677 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)), 678 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)), 679 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)), 680 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)), 681 }; 682 683 /* TXE Egress errors that cause an SPC freeze */ 684 #define ALL_TXE_EGRESS_FREEZE_ERR \ 685 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \ 686 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \ 687 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \ 688 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \ 689 | SEES(TX_LAUNCH_CSR_PARITY) \ 690 | SEES(TX_SBRD_CTL_CSR_PARITY) \ 691 | SEES(TX_CONFIG_PARITY) \ 692 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \ 693 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \ 694 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \ 695 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \ 696 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \ 697 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \ 698 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \ 699 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \ 700 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \ 701 | SEES(TX_CREDIT_RETURN_PARITY)) 702 703 /* 704 * TXE Send error flags 705 */ 706 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK 707 static struct flag_table send_err_status_flags[] = { 708 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)), 709 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)), 710 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR)) 711 }; 712 713 /* 714 * TXE Send Context Error flags and consequences 715 */ 716 static struct flag_table sc_err_status_flags[] = { 717 /* 0*/ FLAG_ENTRY("InconsistentSop", 718 SEC_PACKET_DROPPED | SEC_SC_HALTED, 719 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK), 720 /* 1*/ FLAG_ENTRY("DisallowedPacket", 721 SEC_PACKET_DROPPED | SEC_SC_HALTED, 722 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK), 723 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary", 724 SEC_WRITE_DROPPED | SEC_SC_HALTED, 725 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK), 726 /* 3*/ FLAG_ENTRY("WriteOverflow", 727 SEC_WRITE_DROPPED | SEC_SC_HALTED, 728 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK), 729 /* 4*/ FLAG_ENTRY("WriteOutOfBounds", 730 SEC_WRITE_DROPPED | SEC_SC_HALTED, 731 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK), 732 /* 5-63 reserved*/ 733 }; 734 735 /* 736 * RXE Receive Error flags 737 */ 738 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK 739 static struct flag_table rxe_err_status_flags[] = { 740 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)), 741 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)), 742 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)), 743 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)), 744 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)), 745 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)), 746 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)), 747 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)), 748 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)), 749 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)), 750 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)), 751 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)), 752 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)), 753 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)), 754 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)), 755 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)), 756 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr", 757 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)), 758 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)), 759 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)), 760 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr", 761 RXES(RBUF_BLOCK_LIST_READ_UNC)), 762 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr", 763 RXES(RBUF_BLOCK_LIST_READ_COR)), 764 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr", 765 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)), 766 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr", 767 RXES(RBUF_CSR_QENT_CNT_PARITY)), 768 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr", 769 RXES(RBUF_CSR_QNEXT_BUF_PARITY)), 770 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr", 771 RXES(RBUF_CSR_QVLD_BIT_PARITY)), 772 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)), 773 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)), 774 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr", 775 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)), 776 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)), 777 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)), 778 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)), 779 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)), 780 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)), 781 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)), 782 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)), 783 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr", 784 RXES(RBUF_FL_INITDONE_PARITY)), 785 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr", 786 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)), 787 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)), 788 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)), 789 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)), 790 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr", 791 RXES(LOOKUP_DES_PART1_UNC_COR)), 792 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr", 793 RXES(LOOKUP_DES_PART2_PARITY)), 794 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)), 795 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)), 796 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)), 797 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)), 798 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)), 799 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)), 800 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)), 801 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)), 802 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)), 803 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)), 804 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)), 805 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)), 806 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)), 807 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)), 808 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)), 809 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)), 810 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)), 811 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)), 812 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)), 813 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)), 814 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)), 815 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY)) 816 }; 817 818 /* RXE errors that will trigger an SPC freeze */ 819 #define ALL_RXE_FREEZE_ERR \ 820 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \ 821 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \ 822 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \ 823 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \ 824 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \ 825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \ 826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \ 827 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \ 828 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \ 829 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 830 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \ 831 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \ 832 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \ 833 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \ 834 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \ 835 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 836 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \ 837 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \ 838 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \ 839 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \ 840 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \ 841 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \ 842 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \ 843 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \ 844 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 845 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \ 846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \ 847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 848 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 849 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \ 850 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \ 851 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \ 852 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \ 853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \ 854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \ 855 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \ 856 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \ 857 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 858 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \ 859 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \ 860 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 861 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 862 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \ 863 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK) 864 865 #define RXE_FREEZE_ABORT_MASK \ 866 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \ 867 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \ 868 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK) 869 870 /* 871 * DCC Error Flags 872 */ 873 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK 874 static struct flag_table dcc_err_flags[] = { 875 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)), 876 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)), 877 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)), 878 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)), 879 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)), 880 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)), 881 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)), 882 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)), 883 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)), 884 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)), 885 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)), 886 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)), 887 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)), 888 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)), 889 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)), 890 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)), 891 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)), 892 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)), 893 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)), 894 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)), 895 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)), 896 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)), 897 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)), 898 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)), 899 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)), 900 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)), 901 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)), 902 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)), 903 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)), 904 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)), 905 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)), 906 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)), 907 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)), 908 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)), 909 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)), 910 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)), 911 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)), 912 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)), 913 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)), 914 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)), 915 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)), 916 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)), 917 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)), 918 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)), 919 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)), 920 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)), 921 }; 922 923 /* 924 * LCB error flags 925 */ 926 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK 927 static struct flag_table lcb_err_flags[] = { 928 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)), 929 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)), 930 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)), 931 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST", 932 LCBE(ALL_LNS_FAILED_REINIT_TEST)), 933 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)), 934 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)), 935 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)), 936 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)), 937 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)), 938 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)), 939 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)), 940 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)), 941 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)), 942 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER", 943 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)), 944 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)), 945 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)), 946 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)), 947 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)), 948 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)), 949 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE", 950 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)), 951 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)), 952 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)), 953 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)), 954 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)), 955 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)), 956 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)), 957 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP", 958 LCBE(RST_FOR_INCOMPLT_RND_TRIP)), 959 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)), 960 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE", 961 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)), 962 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR", 963 LCBE(REDUNDANT_FLIT_PARITY_ERR)) 964 }; 965 966 /* 967 * DC8051 Error Flags 968 */ 969 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK 970 static struct flag_table dc8051_err_flags[] = { 971 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)), 972 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)), 973 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)), 974 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)), 975 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)), 976 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)), 977 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)), 978 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)), 979 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES", 980 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)), 981 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)), 982 }; 983 984 /* 985 * DC8051 Information Error flags 986 * 987 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field. 988 */ 989 static struct flag_table dc8051_info_err_flags[] = { 990 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED), 991 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME), 992 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET), 993 FLAG_ENTRY0("Serdes internal loopback failure", 994 FAILED_SERDES_INTERNAL_LOOPBACK), 995 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT), 996 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING), 997 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE), 998 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM), 999 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ), 1000 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1), 1001 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2), 1002 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT), 1003 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT), 1004 FLAG_ENTRY0("External Device Request Timeout", 1005 EXTERNAL_DEVICE_REQ_TIMEOUT), 1006 }; 1007 1008 /* 1009 * DC8051 Information Host Information flags 1010 * 1011 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field. 1012 */ 1013 static struct flag_table dc8051_info_host_msg_flags[] = { 1014 FLAG_ENTRY0("Host request done", 0x0001), 1015 FLAG_ENTRY0("BC PWR_MGM message", 0x0002), 1016 FLAG_ENTRY0("BC SMA message", 0x0004), 1017 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008), 1018 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010), 1019 FLAG_ENTRY0("External device config request", 0x0020), 1020 FLAG_ENTRY0("VerifyCap all frames received", 0x0040), 1021 FLAG_ENTRY0("LinkUp achieved", 0x0080), 1022 FLAG_ENTRY0("Link going down", 0x0100), 1023 FLAG_ENTRY0("Link width downgraded", 0x0200), 1024 }; 1025 1026 static u32 encoded_size(u32 size); 1027 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate); 1028 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state); 1029 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 1030 u8 *continuous); 1031 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 1032 u8 *vcu, u16 *vl15buf, u8 *crc_sizes); 1033 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 1034 u8 *remote_tx_rate, u16 *link_widths); 1035 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits, 1036 u8 *flag_bits, u16 *link_widths); 1037 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 1038 u8 *device_rev); 1039 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx); 1040 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx, 1041 u8 *tx_polarity_inversion, 1042 u8 *rx_polarity_inversion, u8 *max_rate); 1043 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 1044 unsigned int context, u64 err_status); 1045 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg); 1046 static void handle_dcc_err(struct hfi1_devdata *dd, 1047 unsigned int context, u64 err_status); 1048 static void handle_lcb_err(struct hfi1_devdata *dd, 1049 unsigned int context, u64 err_status); 1050 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg); 1051 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1052 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1053 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1054 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1055 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1056 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1057 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1058 static void set_partition_keys(struct hfi1_pportdata *ppd); 1059 static const char *link_state_name(u32 state); 1060 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, 1061 u32 state); 1062 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 1063 u64 *out_data); 1064 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data); 1065 static int thermal_init(struct hfi1_devdata *dd); 1066 1067 static void update_statusp(struct hfi1_pportdata *ppd, u32 state); 1068 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 1069 int msecs); 1070 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1071 int msecs); 1072 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state); 1073 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state); 1074 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1075 int msecs); 1076 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc); 1077 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr); 1078 static void handle_temp_err(struct hfi1_devdata *dd); 1079 static void dc_shutdown(struct hfi1_devdata *dd); 1080 static void dc_start(struct hfi1_devdata *dd); 1081 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 1082 unsigned int *np); 1083 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd); 1084 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms); 1085 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index); 1086 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width); 1087 1088 /* 1089 * Error interrupt table entry. This is used as input to the interrupt 1090 * "clear down" routine used for all second tier error interrupt register. 1091 * Second tier interrupt registers have a single bit representing them 1092 * in the top-level CceIntStatus. 1093 */ 1094 struct err_reg_info { 1095 u32 status; /* status CSR offset */ 1096 u32 clear; /* clear CSR offset */ 1097 u32 mask; /* mask CSR offset */ 1098 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg); 1099 const char *desc; 1100 }; 1101 1102 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START) 1103 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START) 1104 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START) 1105 1106 /* 1107 * Helpers for building HFI and DC error interrupt table entries. Different 1108 * helpers are needed because of inconsistent register names. 1109 */ 1110 #define EE(reg, handler, desc) \ 1111 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ 1112 handler, desc } 1113 #define DC_EE1(reg, handler, desc) \ 1114 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc } 1115 #define DC_EE2(reg, handler, desc) \ 1116 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc } 1117 1118 /* 1119 * Table of the "misc" grouping of error interrupts. Each entry refers to 1120 * another register containing more information. 1121 */ 1122 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = { 1123 /* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"), 1124 /* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"), 1125 /* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"), 1126 /* 3*/ { 0, 0, 0, NULL }, /* reserved */ 1127 /* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"), 1128 /* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"), 1129 /* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"), 1130 /* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr") 1131 /* the rest are reserved */ 1132 }; 1133 1134 /* 1135 * Index into the Various section of the interrupt sources 1136 * corresponding to the Critical Temperature interrupt. 1137 */ 1138 #define TCRIT_INT_SOURCE 4 1139 1140 /* 1141 * SDMA error interrupt entry - refers to another register containing more 1142 * information. 1143 */ 1144 static const struct err_reg_info sdma_eng_err = 1145 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr"); 1146 1147 static const struct err_reg_info various_err[NUM_VARIOUS] = { 1148 /* 0*/ { 0, 0, 0, NULL }, /* PbcInt */ 1149 /* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */ 1150 /* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"), 1151 /* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"), 1152 /* 4*/ { 0, 0, 0, NULL }, /* TCritInt */ 1153 /* rest are reserved */ 1154 }; 1155 1156 /* 1157 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG 1158 * register can not be derived from the MTU value because 10K is not 1159 * a power of 2. Therefore, we need a constant. Everything else can 1160 * be calculated. 1161 */ 1162 #define DCC_CFG_PORT_MTU_CAP_10240 7 1163 1164 /* 1165 * Table of the DC grouping of error interrupts. Each entry refers to 1166 * another register containing more information. 1167 */ 1168 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = { 1169 /* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"), 1170 /* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"), 1171 /* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"), 1172 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */ 1173 /* the rest are reserved */ 1174 }; 1175 1176 struct cntr_entry { 1177 /* 1178 * counter name 1179 */ 1180 char *name; 1181 1182 /* 1183 * csr to read for name (if applicable) 1184 */ 1185 u64 csr; 1186 1187 /* 1188 * offset into dd or ppd to store the counter's value 1189 */ 1190 int offset; 1191 1192 /* 1193 * flags 1194 */ 1195 u8 flags; 1196 1197 /* 1198 * accessor for stat element, context either dd or ppd 1199 */ 1200 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl, 1201 int mode, u64 data); 1202 }; 1203 1204 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0 1205 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159 1206 1207 #define CNTR_ELEM(name, csr, offset, flags, accessor) \ 1208 { \ 1209 name, \ 1210 csr, \ 1211 offset, \ 1212 flags, \ 1213 accessor \ 1214 } 1215 1216 /* 32bit RXE */ 1217 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1218 CNTR_ELEM(#name, \ 1219 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1220 0, flags | CNTR_32BIT, \ 1221 port_access_u32_csr) 1222 1223 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \ 1224 CNTR_ELEM(#name, \ 1225 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1226 0, flags | CNTR_32BIT, \ 1227 dev_access_u32_csr) 1228 1229 /* 64bit RXE */ 1230 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1231 CNTR_ELEM(#name, \ 1232 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1233 0, flags, \ 1234 port_access_u64_csr) 1235 1236 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \ 1237 CNTR_ELEM(#name, \ 1238 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1239 0, flags, \ 1240 dev_access_u64_csr) 1241 1242 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx 1243 #define OVR_ELM(ctx) \ 1244 CNTR_ELEM("RcvHdrOvr" #ctx, \ 1245 (RCV_HDR_OVFL_CNT + ctx * 0x100), \ 1246 0, CNTR_NORMAL, port_access_u64_csr) 1247 1248 /* 32bit TXE */ 1249 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1250 CNTR_ELEM(#name, \ 1251 (counter * 8 + SEND_COUNTER_ARRAY32), \ 1252 0, flags | CNTR_32BIT, \ 1253 port_access_u32_csr) 1254 1255 /* 64bit TXE */ 1256 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1257 CNTR_ELEM(#name, \ 1258 (counter * 8 + SEND_COUNTER_ARRAY64), \ 1259 0, flags, \ 1260 port_access_u64_csr) 1261 1262 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \ 1263 CNTR_ELEM(#name,\ 1264 counter * 8 + SEND_COUNTER_ARRAY64, \ 1265 0, \ 1266 flags, \ 1267 dev_access_u64_csr) 1268 1269 /* CCE */ 1270 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \ 1271 CNTR_ELEM(#name, \ 1272 (counter * 8 + CCE_COUNTER_ARRAY32), \ 1273 0, flags | CNTR_32BIT, \ 1274 dev_access_u32_csr) 1275 1276 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \ 1277 CNTR_ELEM(#name, \ 1278 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \ 1279 0, flags | CNTR_32BIT, \ 1280 dev_access_u32_csr) 1281 1282 /* DC */ 1283 #define DC_PERF_CNTR(name, counter, flags) \ 1284 CNTR_ELEM(#name, \ 1285 counter, \ 1286 0, \ 1287 flags, \ 1288 dev_access_u64_csr) 1289 1290 #define DC_PERF_CNTR_LCB(name, counter, flags) \ 1291 CNTR_ELEM(#name, \ 1292 counter, \ 1293 0, \ 1294 flags, \ 1295 dc_access_lcb_cntr) 1296 1297 /* ibp counters */ 1298 #define SW_IBP_CNTR(name, cntr) \ 1299 CNTR_ELEM(#name, \ 1300 0, \ 1301 0, \ 1302 CNTR_SYNTH, \ 1303 access_ibp_##cntr) 1304 1305 /** 1306 * hfi_addr_from_offset - return addr for readq/writeq 1307 * @dd - the dd device 1308 * @offset - the offset of the CSR within bar0 1309 * 1310 * This routine selects the appropriate base address 1311 * based on the indicated offset. 1312 */ 1313 static inline void __iomem *hfi1_addr_from_offset( 1314 const struct hfi1_devdata *dd, 1315 u32 offset) 1316 { 1317 if (offset >= dd->base2_start) 1318 return dd->kregbase2 + (offset - dd->base2_start); 1319 return dd->kregbase1 + offset; 1320 } 1321 1322 /** 1323 * read_csr - read CSR at the indicated offset 1324 * @dd - the dd device 1325 * @offset - the offset of the CSR within bar0 1326 * 1327 * Return: the value read or all FF's if there 1328 * is no mapping 1329 */ 1330 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) 1331 { 1332 if (dd->flags & HFI1_PRESENT) 1333 return readq(hfi1_addr_from_offset(dd, offset)); 1334 return -1; 1335 } 1336 1337 /** 1338 * write_csr - write CSR at the indicated offset 1339 * @dd - the dd device 1340 * @offset - the offset of the CSR within bar0 1341 * @value - value to write 1342 */ 1343 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) 1344 { 1345 if (dd->flags & HFI1_PRESENT) { 1346 void __iomem *base = hfi1_addr_from_offset(dd, offset); 1347 1348 /* avoid write to RcvArray */ 1349 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start)) 1350 return; 1351 writeq(value, base); 1352 } 1353 } 1354 1355 /** 1356 * get_csr_addr - return te iomem address for offset 1357 * @dd - the dd device 1358 * @offset - the offset of the CSR within bar0 1359 * 1360 * Return: The iomem address to use in subsequent 1361 * writeq/readq operations. 1362 */ 1363 void __iomem *get_csr_addr( 1364 const struct hfi1_devdata *dd, 1365 u32 offset) 1366 { 1367 if (dd->flags & HFI1_PRESENT) 1368 return hfi1_addr_from_offset(dd, offset); 1369 return NULL; 1370 } 1371 1372 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr, 1373 int mode, u64 value) 1374 { 1375 u64 ret; 1376 1377 if (mode == CNTR_MODE_R) { 1378 ret = read_csr(dd, csr); 1379 } else if (mode == CNTR_MODE_W) { 1380 write_csr(dd, csr, value); 1381 ret = value; 1382 } else { 1383 dd_dev_err(dd, "Invalid cntr register access mode"); 1384 return 0; 1385 } 1386 1387 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode); 1388 return ret; 1389 } 1390 1391 /* Dev Access */ 1392 static u64 dev_access_u32_csr(const struct cntr_entry *entry, 1393 void *context, int vl, int mode, u64 data) 1394 { 1395 struct hfi1_devdata *dd = context; 1396 u64 csr = entry->csr; 1397 1398 if (entry->flags & CNTR_SDMA) { 1399 if (vl == CNTR_INVALID_VL) 1400 return 0; 1401 csr += 0x100 * vl; 1402 } else { 1403 if (vl != CNTR_INVALID_VL) 1404 return 0; 1405 } 1406 return read_write_csr(dd, csr, mode, data); 1407 } 1408 1409 static u64 access_sde_err_cnt(const struct cntr_entry *entry, 1410 void *context, int idx, int mode, u64 data) 1411 { 1412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1413 1414 if (dd->per_sdma && idx < dd->num_sdma) 1415 return dd->per_sdma[idx].err_cnt; 1416 return 0; 1417 } 1418 1419 static u64 access_sde_int_cnt(const struct cntr_entry *entry, 1420 void *context, int idx, int mode, u64 data) 1421 { 1422 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1423 1424 if (dd->per_sdma && idx < dd->num_sdma) 1425 return dd->per_sdma[idx].sdma_int_cnt; 1426 return 0; 1427 } 1428 1429 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry, 1430 void *context, int idx, int mode, u64 data) 1431 { 1432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1433 1434 if (dd->per_sdma && idx < dd->num_sdma) 1435 return dd->per_sdma[idx].idle_int_cnt; 1436 return 0; 1437 } 1438 1439 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry, 1440 void *context, int idx, int mode, 1441 u64 data) 1442 { 1443 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1444 1445 if (dd->per_sdma && idx < dd->num_sdma) 1446 return dd->per_sdma[idx].progress_int_cnt; 1447 return 0; 1448 } 1449 1450 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context, 1451 int vl, int mode, u64 data) 1452 { 1453 struct hfi1_devdata *dd = context; 1454 1455 u64 val = 0; 1456 u64 csr = entry->csr; 1457 1458 if (entry->flags & CNTR_VL) { 1459 if (vl == CNTR_INVALID_VL) 1460 return 0; 1461 csr += 8 * vl; 1462 } else { 1463 if (vl != CNTR_INVALID_VL) 1464 return 0; 1465 } 1466 1467 val = read_write_csr(dd, csr, mode, data); 1468 return val; 1469 } 1470 1471 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context, 1472 int vl, int mode, u64 data) 1473 { 1474 struct hfi1_devdata *dd = context; 1475 u32 csr = entry->csr; 1476 int ret = 0; 1477 1478 if (vl != CNTR_INVALID_VL) 1479 return 0; 1480 if (mode == CNTR_MODE_R) 1481 ret = read_lcb_csr(dd, csr, &data); 1482 else if (mode == CNTR_MODE_W) 1483 ret = write_lcb_csr(dd, csr, data); 1484 1485 if (ret) { 1486 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr); 1487 return 0; 1488 } 1489 1490 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode); 1491 return data; 1492 } 1493 1494 /* Port Access */ 1495 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context, 1496 int vl, int mode, u64 data) 1497 { 1498 struct hfi1_pportdata *ppd = context; 1499 1500 if (vl != CNTR_INVALID_VL) 1501 return 0; 1502 return read_write_csr(ppd->dd, entry->csr, mode, data); 1503 } 1504 1505 static u64 port_access_u64_csr(const struct cntr_entry *entry, 1506 void *context, int vl, int mode, u64 data) 1507 { 1508 struct hfi1_pportdata *ppd = context; 1509 u64 val; 1510 u64 csr = entry->csr; 1511 1512 if (entry->flags & CNTR_VL) { 1513 if (vl == CNTR_INVALID_VL) 1514 return 0; 1515 csr += 8 * vl; 1516 } else { 1517 if (vl != CNTR_INVALID_VL) 1518 return 0; 1519 } 1520 val = read_write_csr(ppd->dd, csr, mode, data); 1521 return val; 1522 } 1523 1524 /* Software defined */ 1525 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode, 1526 u64 data) 1527 { 1528 u64 ret; 1529 1530 if (mode == CNTR_MODE_R) { 1531 ret = *cntr; 1532 } else if (mode == CNTR_MODE_W) { 1533 *cntr = data; 1534 ret = data; 1535 } else { 1536 dd_dev_err(dd, "Invalid cntr sw access mode"); 1537 return 0; 1538 } 1539 1540 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode); 1541 1542 return ret; 1543 } 1544 1545 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context, 1546 int vl, int mode, u64 data) 1547 { 1548 struct hfi1_pportdata *ppd = context; 1549 1550 if (vl != CNTR_INVALID_VL) 1551 return 0; 1552 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data); 1553 } 1554 1555 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context, 1556 int vl, int mode, u64 data) 1557 { 1558 struct hfi1_pportdata *ppd = context; 1559 1560 if (vl != CNTR_INVALID_VL) 1561 return 0; 1562 return read_write_sw(ppd->dd, &ppd->link_up, mode, data); 1563 } 1564 1565 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry, 1566 void *context, int vl, int mode, 1567 u64 data) 1568 { 1569 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1570 1571 if (vl != CNTR_INVALID_VL) 1572 return 0; 1573 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data); 1574 } 1575 1576 static u64 access_sw_xmit_discards(const struct cntr_entry *entry, 1577 void *context, int vl, int mode, u64 data) 1578 { 1579 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1580 u64 zero = 0; 1581 u64 *counter; 1582 1583 if (vl == CNTR_INVALID_VL) 1584 counter = &ppd->port_xmit_discards; 1585 else if (vl >= 0 && vl < C_VL_COUNT) 1586 counter = &ppd->port_xmit_discards_vl[vl]; 1587 else 1588 counter = &zero; 1589 1590 return read_write_sw(ppd->dd, counter, mode, data); 1591 } 1592 1593 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry, 1594 void *context, int vl, int mode, 1595 u64 data) 1596 { 1597 struct hfi1_pportdata *ppd = context; 1598 1599 if (vl != CNTR_INVALID_VL) 1600 return 0; 1601 1602 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors, 1603 mode, data); 1604 } 1605 1606 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry, 1607 void *context, int vl, int mode, u64 data) 1608 { 1609 struct hfi1_pportdata *ppd = context; 1610 1611 if (vl != CNTR_INVALID_VL) 1612 return 0; 1613 1614 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors, 1615 mode, data); 1616 } 1617 1618 u64 get_all_cpu_total(u64 __percpu *cntr) 1619 { 1620 int cpu; 1621 u64 counter = 0; 1622 1623 for_each_possible_cpu(cpu) 1624 counter += *per_cpu_ptr(cntr, cpu); 1625 return counter; 1626 } 1627 1628 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val, 1629 u64 __percpu *cntr, 1630 int vl, int mode, u64 data) 1631 { 1632 u64 ret = 0; 1633 1634 if (vl != CNTR_INVALID_VL) 1635 return 0; 1636 1637 if (mode == CNTR_MODE_R) { 1638 ret = get_all_cpu_total(cntr) - *z_val; 1639 } else if (mode == CNTR_MODE_W) { 1640 /* A write can only zero the counter */ 1641 if (data == 0) 1642 *z_val = get_all_cpu_total(cntr); 1643 else 1644 dd_dev_err(dd, "Per CPU cntrs can only be zeroed"); 1645 } else { 1646 dd_dev_err(dd, "Invalid cntr sw cpu access mode"); 1647 return 0; 1648 } 1649 1650 return ret; 1651 } 1652 1653 static u64 access_sw_cpu_intr(const struct cntr_entry *entry, 1654 void *context, int vl, int mode, u64 data) 1655 { 1656 struct hfi1_devdata *dd = context; 1657 1658 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl, 1659 mode, data); 1660 } 1661 1662 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry, 1663 void *context, int vl, int mode, u64 data) 1664 { 1665 struct hfi1_devdata *dd = context; 1666 1667 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl, 1668 mode, data); 1669 } 1670 1671 static u64 access_sw_pio_wait(const struct cntr_entry *entry, 1672 void *context, int vl, int mode, u64 data) 1673 { 1674 struct hfi1_devdata *dd = context; 1675 1676 return dd->verbs_dev.n_piowait; 1677 } 1678 1679 static u64 access_sw_pio_drain(const struct cntr_entry *entry, 1680 void *context, int vl, int mode, u64 data) 1681 { 1682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1683 1684 return dd->verbs_dev.n_piodrain; 1685 } 1686 1687 static u64 access_sw_vtx_wait(const struct cntr_entry *entry, 1688 void *context, int vl, int mode, u64 data) 1689 { 1690 struct hfi1_devdata *dd = context; 1691 1692 return dd->verbs_dev.n_txwait; 1693 } 1694 1695 static u64 access_sw_kmem_wait(const struct cntr_entry *entry, 1696 void *context, int vl, int mode, u64 data) 1697 { 1698 struct hfi1_devdata *dd = context; 1699 1700 return dd->verbs_dev.n_kmem_wait; 1701 } 1702 1703 static u64 access_sw_send_schedule(const struct cntr_entry *entry, 1704 void *context, int vl, int mode, u64 data) 1705 { 1706 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1707 1708 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl, 1709 mode, data); 1710 } 1711 1712 /* Software counters for the error status bits within MISC_ERR_STATUS */ 1713 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry, 1714 void *context, int vl, int mode, 1715 u64 data) 1716 { 1717 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1718 1719 return dd->misc_err_status_cnt[12]; 1720 } 1721 1722 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry, 1723 void *context, int vl, int mode, 1724 u64 data) 1725 { 1726 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1727 1728 return dd->misc_err_status_cnt[11]; 1729 } 1730 1731 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry, 1732 void *context, int vl, int mode, 1733 u64 data) 1734 { 1735 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1736 1737 return dd->misc_err_status_cnt[10]; 1738 } 1739 1740 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry, 1741 void *context, int vl, 1742 int mode, u64 data) 1743 { 1744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1745 1746 return dd->misc_err_status_cnt[9]; 1747 } 1748 1749 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry, 1750 void *context, int vl, int mode, 1751 u64 data) 1752 { 1753 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1754 1755 return dd->misc_err_status_cnt[8]; 1756 } 1757 1758 static u64 access_misc_efuse_read_bad_addr_err_cnt( 1759 const struct cntr_entry *entry, 1760 void *context, int vl, int mode, u64 data) 1761 { 1762 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1763 1764 return dd->misc_err_status_cnt[7]; 1765 } 1766 1767 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry, 1768 void *context, int vl, 1769 int mode, u64 data) 1770 { 1771 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1772 1773 return dd->misc_err_status_cnt[6]; 1774 } 1775 1776 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry, 1777 void *context, int vl, int mode, 1778 u64 data) 1779 { 1780 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1781 1782 return dd->misc_err_status_cnt[5]; 1783 } 1784 1785 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry, 1786 void *context, int vl, int mode, 1787 u64 data) 1788 { 1789 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1790 1791 return dd->misc_err_status_cnt[4]; 1792 } 1793 1794 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry, 1795 void *context, int vl, 1796 int mode, u64 data) 1797 { 1798 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1799 1800 return dd->misc_err_status_cnt[3]; 1801 } 1802 1803 static u64 access_misc_csr_write_bad_addr_err_cnt( 1804 const struct cntr_entry *entry, 1805 void *context, int vl, int mode, u64 data) 1806 { 1807 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1808 1809 return dd->misc_err_status_cnt[2]; 1810 } 1811 1812 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1813 void *context, int vl, 1814 int mode, u64 data) 1815 { 1816 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1817 1818 return dd->misc_err_status_cnt[1]; 1819 } 1820 1821 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry, 1822 void *context, int vl, int mode, 1823 u64 data) 1824 { 1825 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1826 1827 return dd->misc_err_status_cnt[0]; 1828 } 1829 1830 /* 1831 * Software counter for the aggregate of 1832 * individual CceErrStatus counters 1833 */ 1834 static u64 access_sw_cce_err_status_aggregated_cnt( 1835 const struct cntr_entry *entry, 1836 void *context, int vl, int mode, u64 data) 1837 { 1838 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1839 1840 return dd->sw_cce_err_status_aggregate; 1841 } 1842 1843 /* 1844 * Software counters corresponding to each of the 1845 * error status bits within CceErrStatus 1846 */ 1847 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry, 1848 void *context, int vl, int mode, 1849 u64 data) 1850 { 1851 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1852 1853 return dd->cce_err_status_cnt[40]; 1854 } 1855 1856 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry, 1857 void *context, int vl, int mode, 1858 u64 data) 1859 { 1860 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1861 1862 return dd->cce_err_status_cnt[39]; 1863 } 1864 1865 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry, 1866 void *context, int vl, int mode, 1867 u64 data) 1868 { 1869 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1870 1871 return dd->cce_err_status_cnt[38]; 1872 } 1873 1874 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry, 1875 void *context, int vl, int mode, 1876 u64 data) 1877 { 1878 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1879 1880 return dd->cce_err_status_cnt[37]; 1881 } 1882 1883 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry, 1884 void *context, int vl, int mode, 1885 u64 data) 1886 { 1887 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1888 1889 return dd->cce_err_status_cnt[36]; 1890 } 1891 1892 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt( 1893 const struct cntr_entry *entry, 1894 void *context, int vl, int mode, u64 data) 1895 { 1896 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1897 1898 return dd->cce_err_status_cnt[35]; 1899 } 1900 1901 static u64 access_cce_rcpl_async_fifo_parity_err_cnt( 1902 const struct cntr_entry *entry, 1903 void *context, int vl, int mode, u64 data) 1904 { 1905 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1906 1907 return dd->cce_err_status_cnt[34]; 1908 } 1909 1910 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry, 1911 void *context, int vl, 1912 int mode, u64 data) 1913 { 1914 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1915 1916 return dd->cce_err_status_cnt[33]; 1917 } 1918 1919 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1920 void *context, int vl, int mode, 1921 u64 data) 1922 { 1923 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1924 1925 return dd->cce_err_status_cnt[32]; 1926 } 1927 1928 static u64 access_la_triggered_cnt(const struct cntr_entry *entry, 1929 void *context, int vl, int mode, u64 data) 1930 { 1931 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1932 1933 return dd->cce_err_status_cnt[31]; 1934 } 1935 1936 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry, 1937 void *context, int vl, int mode, 1938 u64 data) 1939 { 1940 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1941 1942 return dd->cce_err_status_cnt[30]; 1943 } 1944 1945 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry, 1946 void *context, int vl, int mode, 1947 u64 data) 1948 { 1949 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1950 1951 return dd->cce_err_status_cnt[29]; 1952 } 1953 1954 static u64 access_pcic_transmit_back_parity_err_cnt( 1955 const struct cntr_entry *entry, 1956 void *context, int vl, int mode, u64 data) 1957 { 1958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1959 1960 return dd->cce_err_status_cnt[28]; 1961 } 1962 1963 static u64 access_pcic_transmit_front_parity_err_cnt( 1964 const struct cntr_entry *entry, 1965 void *context, int vl, int mode, u64 data) 1966 { 1967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1968 1969 return dd->cce_err_status_cnt[27]; 1970 } 1971 1972 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry, 1973 void *context, int vl, int mode, 1974 u64 data) 1975 { 1976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1977 1978 return dd->cce_err_status_cnt[26]; 1979 } 1980 1981 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry, 1982 void *context, int vl, int mode, 1983 u64 data) 1984 { 1985 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1986 1987 return dd->cce_err_status_cnt[25]; 1988 } 1989 1990 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry, 1991 void *context, int vl, int mode, 1992 u64 data) 1993 { 1994 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1995 1996 return dd->cce_err_status_cnt[24]; 1997 } 1998 1999 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2000 void *context, int vl, int mode, 2001 u64 data) 2002 { 2003 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2004 2005 return dd->cce_err_status_cnt[23]; 2006 } 2007 2008 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry, 2009 void *context, int vl, 2010 int mode, u64 data) 2011 { 2012 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2013 2014 return dd->cce_err_status_cnt[22]; 2015 } 2016 2017 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry, 2018 void *context, int vl, int mode, 2019 u64 data) 2020 { 2021 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2022 2023 return dd->cce_err_status_cnt[21]; 2024 } 2025 2026 static u64 access_pcic_n_post_dat_q_parity_err_cnt( 2027 const struct cntr_entry *entry, 2028 void *context, int vl, int mode, u64 data) 2029 { 2030 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2031 2032 return dd->cce_err_status_cnt[20]; 2033 } 2034 2035 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry, 2036 void *context, int vl, 2037 int mode, u64 data) 2038 { 2039 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2040 2041 return dd->cce_err_status_cnt[19]; 2042 } 2043 2044 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2045 void *context, int vl, int mode, 2046 u64 data) 2047 { 2048 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2049 2050 return dd->cce_err_status_cnt[18]; 2051 } 2052 2053 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2054 void *context, int vl, int mode, 2055 u64 data) 2056 { 2057 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2058 2059 return dd->cce_err_status_cnt[17]; 2060 } 2061 2062 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2063 void *context, int vl, int mode, 2064 u64 data) 2065 { 2066 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2067 2068 return dd->cce_err_status_cnt[16]; 2069 } 2070 2071 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2072 void *context, int vl, int mode, 2073 u64 data) 2074 { 2075 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2076 2077 return dd->cce_err_status_cnt[15]; 2078 } 2079 2080 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry, 2081 void *context, int vl, 2082 int mode, u64 data) 2083 { 2084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2085 2086 return dd->cce_err_status_cnt[14]; 2087 } 2088 2089 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry, 2090 void *context, int vl, int mode, 2091 u64 data) 2092 { 2093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2094 2095 return dd->cce_err_status_cnt[13]; 2096 } 2097 2098 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt( 2099 const struct cntr_entry *entry, 2100 void *context, int vl, int mode, u64 data) 2101 { 2102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2103 2104 return dd->cce_err_status_cnt[12]; 2105 } 2106 2107 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt( 2108 const struct cntr_entry *entry, 2109 void *context, int vl, int mode, u64 data) 2110 { 2111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2112 2113 return dd->cce_err_status_cnt[11]; 2114 } 2115 2116 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt( 2117 const struct cntr_entry *entry, 2118 void *context, int vl, int mode, u64 data) 2119 { 2120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2121 2122 return dd->cce_err_status_cnt[10]; 2123 } 2124 2125 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt( 2126 const struct cntr_entry *entry, 2127 void *context, int vl, int mode, u64 data) 2128 { 2129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2130 2131 return dd->cce_err_status_cnt[9]; 2132 } 2133 2134 static u64 access_cce_cli2_async_fifo_parity_err_cnt( 2135 const struct cntr_entry *entry, 2136 void *context, int vl, int mode, u64 data) 2137 { 2138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2139 2140 return dd->cce_err_status_cnt[8]; 2141 } 2142 2143 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry, 2144 void *context, int vl, 2145 int mode, u64 data) 2146 { 2147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2148 2149 return dd->cce_err_status_cnt[7]; 2150 } 2151 2152 static u64 access_cce_cli0_async_fifo_parity_err_cnt( 2153 const struct cntr_entry *entry, 2154 void *context, int vl, int mode, u64 data) 2155 { 2156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2157 2158 return dd->cce_err_status_cnt[6]; 2159 } 2160 2161 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry, 2162 void *context, int vl, int mode, 2163 u64 data) 2164 { 2165 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2166 2167 return dd->cce_err_status_cnt[5]; 2168 } 2169 2170 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry, 2171 void *context, int vl, int mode, 2172 u64 data) 2173 { 2174 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2175 2176 return dd->cce_err_status_cnt[4]; 2177 } 2178 2179 static u64 access_cce_trgt_async_fifo_parity_err_cnt( 2180 const struct cntr_entry *entry, 2181 void *context, int vl, int mode, u64 data) 2182 { 2183 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2184 2185 return dd->cce_err_status_cnt[3]; 2186 } 2187 2188 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2189 void *context, int vl, 2190 int mode, u64 data) 2191 { 2192 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2193 2194 return dd->cce_err_status_cnt[2]; 2195 } 2196 2197 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2198 void *context, int vl, 2199 int mode, u64 data) 2200 { 2201 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2202 2203 return dd->cce_err_status_cnt[1]; 2204 } 2205 2206 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry, 2207 void *context, int vl, int mode, 2208 u64 data) 2209 { 2210 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2211 2212 return dd->cce_err_status_cnt[0]; 2213 } 2214 2215 /* 2216 * Software counters corresponding to each of the 2217 * error status bits within RcvErrStatus 2218 */ 2219 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry, 2220 void *context, int vl, int mode, 2221 u64 data) 2222 { 2223 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2224 2225 return dd->rcv_err_status_cnt[63]; 2226 } 2227 2228 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2229 void *context, int vl, 2230 int mode, u64 data) 2231 { 2232 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2233 2234 return dd->rcv_err_status_cnt[62]; 2235 } 2236 2237 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2238 void *context, int vl, int mode, 2239 u64 data) 2240 { 2241 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2242 2243 return dd->rcv_err_status_cnt[61]; 2244 } 2245 2246 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry, 2247 void *context, int vl, int mode, 2248 u64 data) 2249 { 2250 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2251 2252 return dd->rcv_err_status_cnt[60]; 2253 } 2254 2255 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2256 void *context, int vl, 2257 int mode, u64 data) 2258 { 2259 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2260 2261 return dd->rcv_err_status_cnt[59]; 2262 } 2263 2264 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2265 void *context, int vl, 2266 int mode, u64 data) 2267 { 2268 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2269 2270 return dd->rcv_err_status_cnt[58]; 2271 } 2272 2273 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry, 2274 void *context, int vl, int mode, 2275 u64 data) 2276 { 2277 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2278 2279 return dd->rcv_err_status_cnt[57]; 2280 } 2281 2282 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry, 2283 void *context, int vl, int mode, 2284 u64 data) 2285 { 2286 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2287 2288 return dd->rcv_err_status_cnt[56]; 2289 } 2290 2291 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry, 2292 void *context, int vl, int mode, 2293 u64 data) 2294 { 2295 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2296 2297 return dd->rcv_err_status_cnt[55]; 2298 } 2299 2300 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt( 2301 const struct cntr_entry *entry, 2302 void *context, int vl, int mode, u64 data) 2303 { 2304 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2305 2306 return dd->rcv_err_status_cnt[54]; 2307 } 2308 2309 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt( 2310 const struct cntr_entry *entry, 2311 void *context, int vl, int mode, u64 data) 2312 { 2313 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2314 2315 return dd->rcv_err_status_cnt[53]; 2316 } 2317 2318 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry, 2319 void *context, int vl, 2320 int mode, u64 data) 2321 { 2322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2323 2324 return dd->rcv_err_status_cnt[52]; 2325 } 2326 2327 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry, 2328 void *context, int vl, 2329 int mode, u64 data) 2330 { 2331 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2332 2333 return dd->rcv_err_status_cnt[51]; 2334 } 2335 2336 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry, 2337 void *context, int vl, 2338 int mode, u64 data) 2339 { 2340 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2341 2342 return dd->rcv_err_status_cnt[50]; 2343 } 2344 2345 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry, 2346 void *context, int vl, 2347 int mode, u64 data) 2348 { 2349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2350 2351 return dd->rcv_err_status_cnt[49]; 2352 } 2353 2354 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry, 2355 void *context, int vl, 2356 int mode, u64 data) 2357 { 2358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2359 2360 return dd->rcv_err_status_cnt[48]; 2361 } 2362 2363 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry, 2364 void *context, int vl, 2365 int mode, u64 data) 2366 { 2367 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2368 2369 return dd->rcv_err_status_cnt[47]; 2370 } 2371 2372 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry, 2373 void *context, int vl, int mode, 2374 u64 data) 2375 { 2376 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2377 2378 return dd->rcv_err_status_cnt[46]; 2379 } 2380 2381 static u64 access_rx_hq_intr_csr_parity_err_cnt( 2382 const struct cntr_entry *entry, 2383 void *context, int vl, int mode, u64 data) 2384 { 2385 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2386 2387 return dd->rcv_err_status_cnt[45]; 2388 } 2389 2390 static u64 access_rx_lookup_csr_parity_err_cnt( 2391 const struct cntr_entry *entry, 2392 void *context, int vl, int mode, u64 data) 2393 { 2394 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2395 2396 return dd->rcv_err_status_cnt[44]; 2397 } 2398 2399 static u64 access_rx_lookup_rcv_array_cor_err_cnt( 2400 const struct cntr_entry *entry, 2401 void *context, int vl, int mode, u64 data) 2402 { 2403 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2404 2405 return dd->rcv_err_status_cnt[43]; 2406 } 2407 2408 static u64 access_rx_lookup_rcv_array_unc_err_cnt( 2409 const struct cntr_entry *entry, 2410 void *context, int vl, int mode, u64 data) 2411 { 2412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2413 2414 return dd->rcv_err_status_cnt[42]; 2415 } 2416 2417 static u64 access_rx_lookup_des_part2_parity_err_cnt( 2418 const struct cntr_entry *entry, 2419 void *context, int vl, int mode, u64 data) 2420 { 2421 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2422 2423 return dd->rcv_err_status_cnt[41]; 2424 } 2425 2426 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt( 2427 const struct cntr_entry *entry, 2428 void *context, int vl, int mode, u64 data) 2429 { 2430 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2431 2432 return dd->rcv_err_status_cnt[40]; 2433 } 2434 2435 static u64 access_rx_lookup_des_part1_unc_err_cnt( 2436 const struct cntr_entry *entry, 2437 void *context, int vl, int mode, u64 data) 2438 { 2439 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2440 2441 return dd->rcv_err_status_cnt[39]; 2442 } 2443 2444 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt( 2445 const struct cntr_entry *entry, 2446 void *context, int vl, int mode, u64 data) 2447 { 2448 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2449 2450 return dd->rcv_err_status_cnt[38]; 2451 } 2452 2453 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt( 2454 const struct cntr_entry *entry, 2455 void *context, int vl, int mode, u64 data) 2456 { 2457 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2458 2459 return dd->rcv_err_status_cnt[37]; 2460 } 2461 2462 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt( 2463 const struct cntr_entry *entry, 2464 void *context, int vl, int mode, u64 data) 2465 { 2466 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2467 2468 return dd->rcv_err_status_cnt[36]; 2469 } 2470 2471 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt( 2472 const struct cntr_entry *entry, 2473 void *context, int vl, int mode, u64 data) 2474 { 2475 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2476 2477 return dd->rcv_err_status_cnt[35]; 2478 } 2479 2480 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt( 2481 const struct cntr_entry *entry, 2482 void *context, int vl, int mode, u64 data) 2483 { 2484 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2485 2486 return dd->rcv_err_status_cnt[34]; 2487 } 2488 2489 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt( 2490 const struct cntr_entry *entry, 2491 void *context, int vl, int mode, u64 data) 2492 { 2493 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2494 2495 return dd->rcv_err_status_cnt[33]; 2496 } 2497 2498 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry, 2499 void *context, int vl, int mode, 2500 u64 data) 2501 { 2502 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2503 2504 return dd->rcv_err_status_cnt[32]; 2505 } 2506 2507 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry, 2508 void *context, int vl, int mode, 2509 u64 data) 2510 { 2511 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2512 2513 return dd->rcv_err_status_cnt[31]; 2514 } 2515 2516 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry, 2517 void *context, int vl, int mode, 2518 u64 data) 2519 { 2520 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2521 2522 return dd->rcv_err_status_cnt[30]; 2523 } 2524 2525 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry, 2526 void *context, int vl, int mode, 2527 u64 data) 2528 { 2529 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2530 2531 return dd->rcv_err_status_cnt[29]; 2532 } 2533 2534 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry, 2535 void *context, int vl, 2536 int mode, u64 data) 2537 { 2538 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2539 2540 return dd->rcv_err_status_cnt[28]; 2541 } 2542 2543 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt( 2544 const struct cntr_entry *entry, 2545 void *context, int vl, int mode, u64 data) 2546 { 2547 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2548 2549 return dd->rcv_err_status_cnt[27]; 2550 } 2551 2552 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt( 2553 const struct cntr_entry *entry, 2554 void *context, int vl, int mode, u64 data) 2555 { 2556 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2557 2558 return dd->rcv_err_status_cnt[26]; 2559 } 2560 2561 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt( 2562 const struct cntr_entry *entry, 2563 void *context, int vl, int mode, u64 data) 2564 { 2565 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2566 2567 return dd->rcv_err_status_cnt[25]; 2568 } 2569 2570 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt( 2571 const struct cntr_entry *entry, 2572 void *context, int vl, int mode, u64 data) 2573 { 2574 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2575 2576 return dd->rcv_err_status_cnt[24]; 2577 } 2578 2579 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt( 2580 const struct cntr_entry *entry, 2581 void *context, int vl, int mode, u64 data) 2582 { 2583 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2584 2585 return dd->rcv_err_status_cnt[23]; 2586 } 2587 2588 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt( 2589 const struct cntr_entry *entry, 2590 void *context, int vl, int mode, u64 data) 2591 { 2592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2593 2594 return dd->rcv_err_status_cnt[22]; 2595 } 2596 2597 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt( 2598 const struct cntr_entry *entry, 2599 void *context, int vl, int mode, u64 data) 2600 { 2601 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2602 2603 return dd->rcv_err_status_cnt[21]; 2604 } 2605 2606 static u64 access_rx_rbuf_block_list_read_cor_err_cnt( 2607 const struct cntr_entry *entry, 2608 void *context, int vl, int mode, u64 data) 2609 { 2610 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2611 2612 return dd->rcv_err_status_cnt[20]; 2613 } 2614 2615 static u64 access_rx_rbuf_block_list_read_unc_err_cnt( 2616 const struct cntr_entry *entry, 2617 void *context, int vl, int mode, u64 data) 2618 { 2619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2620 2621 return dd->rcv_err_status_cnt[19]; 2622 } 2623 2624 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry, 2625 void *context, int vl, 2626 int mode, u64 data) 2627 { 2628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2629 2630 return dd->rcv_err_status_cnt[18]; 2631 } 2632 2633 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry, 2634 void *context, int vl, 2635 int mode, u64 data) 2636 { 2637 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2638 2639 return dd->rcv_err_status_cnt[17]; 2640 } 2641 2642 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt( 2643 const struct cntr_entry *entry, 2644 void *context, int vl, int mode, u64 data) 2645 { 2646 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2647 2648 return dd->rcv_err_status_cnt[16]; 2649 } 2650 2651 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt( 2652 const struct cntr_entry *entry, 2653 void *context, int vl, int mode, u64 data) 2654 { 2655 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2656 2657 return dd->rcv_err_status_cnt[15]; 2658 } 2659 2660 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry, 2661 void *context, int vl, 2662 int mode, u64 data) 2663 { 2664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2665 2666 return dd->rcv_err_status_cnt[14]; 2667 } 2668 2669 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry, 2670 void *context, int vl, 2671 int mode, u64 data) 2672 { 2673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2674 2675 return dd->rcv_err_status_cnt[13]; 2676 } 2677 2678 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2679 void *context, int vl, int mode, 2680 u64 data) 2681 { 2682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2683 2684 return dd->rcv_err_status_cnt[12]; 2685 } 2686 2687 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry, 2688 void *context, int vl, int mode, 2689 u64 data) 2690 { 2691 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2692 2693 return dd->rcv_err_status_cnt[11]; 2694 } 2695 2696 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry, 2697 void *context, int vl, int mode, 2698 u64 data) 2699 { 2700 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2701 2702 return dd->rcv_err_status_cnt[10]; 2703 } 2704 2705 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry, 2706 void *context, int vl, int mode, 2707 u64 data) 2708 { 2709 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2710 2711 return dd->rcv_err_status_cnt[9]; 2712 } 2713 2714 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry, 2715 void *context, int vl, int mode, 2716 u64 data) 2717 { 2718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2719 2720 return dd->rcv_err_status_cnt[8]; 2721 } 2722 2723 static u64 access_rx_rcv_qp_map_table_cor_err_cnt( 2724 const struct cntr_entry *entry, 2725 void *context, int vl, int mode, u64 data) 2726 { 2727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2728 2729 return dd->rcv_err_status_cnt[7]; 2730 } 2731 2732 static u64 access_rx_rcv_qp_map_table_unc_err_cnt( 2733 const struct cntr_entry *entry, 2734 void *context, int vl, int mode, u64 data) 2735 { 2736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2737 2738 return dd->rcv_err_status_cnt[6]; 2739 } 2740 2741 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry, 2742 void *context, int vl, int mode, 2743 u64 data) 2744 { 2745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2746 2747 return dd->rcv_err_status_cnt[5]; 2748 } 2749 2750 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry, 2751 void *context, int vl, int mode, 2752 u64 data) 2753 { 2754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2755 2756 return dd->rcv_err_status_cnt[4]; 2757 } 2758 2759 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry, 2760 void *context, int vl, int mode, 2761 u64 data) 2762 { 2763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2764 2765 return dd->rcv_err_status_cnt[3]; 2766 } 2767 2768 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry, 2769 void *context, int vl, int mode, 2770 u64 data) 2771 { 2772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2773 2774 return dd->rcv_err_status_cnt[2]; 2775 } 2776 2777 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry, 2778 void *context, int vl, int mode, 2779 u64 data) 2780 { 2781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2782 2783 return dd->rcv_err_status_cnt[1]; 2784 } 2785 2786 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry, 2787 void *context, int vl, int mode, 2788 u64 data) 2789 { 2790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2791 2792 return dd->rcv_err_status_cnt[0]; 2793 } 2794 2795 /* 2796 * Software counters corresponding to each of the 2797 * error status bits within SendPioErrStatus 2798 */ 2799 static u64 access_pio_pec_sop_head_parity_err_cnt( 2800 const struct cntr_entry *entry, 2801 void *context, int vl, int mode, u64 data) 2802 { 2803 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2804 2805 return dd->send_pio_err_status_cnt[35]; 2806 } 2807 2808 static u64 access_pio_pcc_sop_head_parity_err_cnt( 2809 const struct cntr_entry *entry, 2810 void *context, int vl, int mode, u64 data) 2811 { 2812 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2813 2814 return dd->send_pio_err_status_cnt[34]; 2815 } 2816 2817 static u64 access_pio_last_returned_cnt_parity_err_cnt( 2818 const struct cntr_entry *entry, 2819 void *context, int vl, int mode, u64 data) 2820 { 2821 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2822 2823 return dd->send_pio_err_status_cnt[33]; 2824 } 2825 2826 static u64 access_pio_current_free_cnt_parity_err_cnt( 2827 const struct cntr_entry *entry, 2828 void *context, int vl, int mode, u64 data) 2829 { 2830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2831 2832 return dd->send_pio_err_status_cnt[32]; 2833 } 2834 2835 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry, 2836 void *context, int vl, int mode, 2837 u64 data) 2838 { 2839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2840 2841 return dd->send_pio_err_status_cnt[31]; 2842 } 2843 2844 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry, 2845 void *context, int vl, int mode, 2846 u64 data) 2847 { 2848 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2849 2850 return dd->send_pio_err_status_cnt[30]; 2851 } 2852 2853 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry, 2854 void *context, int vl, int mode, 2855 u64 data) 2856 { 2857 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2858 2859 return dd->send_pio_err_status_cnt[29]; 2860 } 2861 2862 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt( 2863 const struct cntr_entry *entry, 2864 void *context, int vl, int mode, u64 data) 2865 { 2866 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2867 2868 return dd->send_pio_err_status_cnt[28]; 2869 } 2870 2871 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry, 2872 void *context, int vl, int mode, 2873 u64 data) 2874 { 2875 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2876 2877 return dd->send_pio_err_status_cnt[27]; 2878 } 2879 2880 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry, 2881 void *context, int vl, int mode, 2882 u64 data) 2883 { 2884 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2885 2886 return dd->send_pio_err_status_cnt[26]; 2887 } 2888 2889 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry, 2890 void *context, int vl, 2891 int mode, u64 data) 2892 { 2893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2894 2895 return dd->send_pio_err_status_cnt[25]; 2896 } 2897 2898 static u64 access_pio_block_qw_count_parity_err_cnt( 2899 const struct cntr_entry *entry, 2900 void *context, int vl, int mode, u64 data) 2901 { 2902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2903 2904 return dd->send_pio_err_status_cnt[24]; 2905 } 2906 2907 static u64 access_pio_write_qw_valid_parity_err_cnt( 2908 const struct cntr_entry *entry, 2909 void *context, int vl, int mode, u64 data) 2910 { 2911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2912 2913 return dd->send_pio_err_status_cnt[23]; 2914 } 2915 2916 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry, 2917 void *context, int vl, int mode, 2918 u64 data) 2919 { 2920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2921 2922 return dd->send_pio_err_status_cnt[22]; 2923 } 2924 2925 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry, 2926 void *context, int vl, 2927 int mode, u64 data) 2928 { 2929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2930 2931 return dd->send_pio_err_status_cnt[21]; 2932 } 2933 2934 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry, 2935 void *context, int vl, 2936 int mode, u64 data) 2937 { 2938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2939 2940 return dd->send_pio_err_status_cnt[20]; 2941 } 2942 2943 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry, 2944 void *context, int vl, 2945 int mode, u64 data) 2946 { 2947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2948 2949 return dd->send_pio_err_status_cnt[19]; 2950 } 2951 2952 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt( 2953 const struct cntr_entry *entry, 2954 void *context, int vl, int mode, u64 data) 2955 { 2956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2957 2958 return dd->send_pio_err_status_cnt[18]; 2959 } 2960 2961 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry, 2962 void *context, int vl, int mode, 2963 u64 data) 2964 { 2965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2966 2967 return dd->send_pio_err_status_cnt[17]; 2968 } 2969 2970 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry, 2971 void *context, int vl, int mode, 2972 u64 data) 2973 { 2974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2975 2976 return dd->send_pio_err_status_cnt[16]; 2977 } 2978 2979 static u64 access_pio_credit_ret_fifo_parity_err_cnt( 2980 const struct cntr_entry *entry, 2981 void *context, int vl, int mode, u64 data) 2982 { 2983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2984 2985 return dd->send_pio_err_status_cnt[15]; 2986 } 2987 2988 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt( 2989 const struct cntr_entry *entry, 2990 void *context, int vl, int mode, u64 data) 2991 { 2992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2993 2994 return dd->send_pio_err_status_cnt[14]; 2995 } 2996 2997 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt( 2998 const struct cntr_entry *entry, 2999 void *context, int vl, int mode, u64 data) 3000 { 3001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3002 3003 return dd->send_pio_err_status_cnt[13]; 3004 } 3005 3006 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt( 3007 const struct cntr_entry *entry, 3008 void *context, int vl, int mode, u64 data) 3009 { 3010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3011 3012 return dd->send_pio_err_status_cnt[12]; 3013 } 3014 3015 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt( 3016 const struct cntr_entry *entry, 3017 void *context, int vl, int mode, u64 data) 3018 { 3019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3020 3021 return dd->send_pio_err_status_cnt[11]; 3022 } 3023 3024 static u64 access_pio_sm_pkt_reset_parity_err_cnt( 3025 const struct cntr_entry *entry, 3026 void *context, int vl, int mode, u64 data) 3027 { 3028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3029 3030 return dd->send_pio_err_status_cnt[10]; 3031 } 3032 3033 static u64 access_pio_pkt_evict_fifo_parity_err_cnt( 3034 const struct cntr_entry *entry, 3035 void *context, int vl, int mode, u64 data) 3036 { 3037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3038 3039 return dd->send_pio_err_status_cnt[9]; 3040 } 3041 3042 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt( 3043 const struct cntr_entry *entry, 3044 void *context, int vl, int mode, u64 data) 3045 { 3046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3047 3048 return dd->send_pio_err_status_cnt[8]; 3049 } 3050 3051 static u64 access_pio_sbrdctl_crrel_parity_err_cnt( 3052 const struct cntr_entry *entry, 3053 void *context, int vl, int mode, u64 data) 3054 { 3055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3056 3057 return dd->send_pio_err_status_cnt[7]; 3058 } 3059 3060 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry, 3061 void *context, int vl, int mode, 3062 u64 data) 3063 { 3064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3065 3066 return dd->send_pio_err_status_cnt[6]; 3067 } 3068 3069 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry, 3070 void *context, int vl, int mode, 3071 u64 data) 3072 { 3073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3074 3075 return dd->send_pio_err_status_cnt[5]; 3076 } 3077 3078 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry, 3079 void *context, int vl, int mode, 3080 u64 data) 3081 { 3082 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3083 3084 return dd->send_pio_err_status_cnt[4]; 3085 } 3086 3087 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry, 3088 void *context, int vl, int mode, 3089 u64 data) 3090 { 3091 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3092 3093 return dd->send_pio_err_status_cnt[3]; 3094 } 3095 3096 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry, 3097 void *context, int vl, int mode, 3098 u64 data) 3099 { 3100 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3101 3102 return dd->send_pio_err_status_cnt[2]; 3103 } 3104 3105 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry, 3106 void *context, int vl, 3107 int mode, u64 data) 3108 { 3109 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3110 3111 return dd->send_pio_err_status_cnt[1]; 3112 } 3113 3114 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry, 3115 void *context, int vl, int mode, 3116 u64 data) 3117 { 3118 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3119 3120 return dd->send_pio_err_status_cnt[0]; 3121 } 3122 3123 /* 3124 * Software counters corresponding to each of the 3125 * error status bits within SendDmaErrStatus 3126 */ 3127 static u64 access_sdma_pcie_req_tracking_cor_err_cnt( 3128 const struct cntr_entry *entry, 3129 void *context, int vl, int mode, u64 data) 3130 { 3131 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3132 3133 return dd->send_dma_err_status_cnt[3]; 3134 } 3135 3136 static u64 access_sdma_pcie_req_tracking_unc_err_cnt( 3137 const struct cntr_entry *entry, 3138 void *context, int vl, int mode, u64 data) 3139 { 3140 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3141 3142 return dd->send_dma_err_status_cnt[2]; 3143 } 3144 3145 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry, 3146 void *context, int vl, int mode, 3147 u64 data) 3148 { 3149 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3150 3151 return dd->send_dma_err_status_cnt[1]; 3152 } 3153 3154 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry, 3155 void *context, int vl, int mode, 3156 u64 data) 3157 { 3158 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3159 3160 return dd->send_dma_err_status_cnt[0]; 3161 } 3162 3163 /* 3164 * Software counters corresponding to each of the 3165 * error status bits within SendEgressErrStatus 3166 */ 3167 static u64 access_tx_read_pio_memory_csr_unc_err_cnt( 3168 const struct cntr_entry *entry, 3169 void *context, int vl, int mode, u64 data) 3170 { 3171 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3172 3173 return dd->send_egress_err_status_cnt[63]; 3174 } 3175 3176 static u64 access_tx_read_sdma_memory_csr_err_cnt( 3177 const struct cntr_entry *entry, 3178 void *context, int vl, int mode, u64 data) 3179 { 3180 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3181 3182 return dd->send_egress_err_status_cnt[62]; 3183 } 3184 3185 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry, 3186 void *context, int vl, int mode, 3187 u64 data) 3188 { 3189 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3190 3191 return dd->send_egress_err_status_cnt[61]; 3192 } 3193 3194 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry, 3195 void *context, int vl, 3196 int mode, u64 data) 3197 { 3198 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3199 3200 return dd->send_egress_err_status_cnt[60]; 3201 } 3202 3203 static u64 access_tx_read_sdma_memory_cor_err_cnt( 3204 const struct cntr_entry *entry, 3205 void *context, int vl, int mode, u64 data) 3206 { 3207 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3208 3209 return dd->send_egress_err_status_cnt[59]; 3210 } 3211 3212 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry, 3213 void *context, int vl, int mode, 3214 u64 data) 3215 { 3216 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3217 3218 return dd->send_egress_err_status_cnt[58]; 3219 } 3220 3221 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry, 3222 void *context, int vl, int mode, 3223 u64 data) 3224 { 3225 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3226 3227 return dd->send_egress_err_status_cnt[57]; 3228 } 3229 3230 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry, 3231 void *context, int vl, int mode, 3232 u64 data) 3233 { 3234 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3235 3236 return dd->send_egress_err_status_cnt[56]; 3237 } 3238 3239 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry, 3240 void *context, int vl, int mode, 3241 u64 data) 3242 { 3243 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3244 3245 return dd->send_egress_err_status_cnt[55]; 3246 } 3247 3248 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry, 3249 void *context, int vl, int mode, 3250 u64 data) 3251 { 3252 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3253 3254 return dd->send_egress_err_status_cnt[54]; 3255 } 3256 3257 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry, 3258 void *context, int vl, int mode, 3259 u64 data) 3260 { 3261 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3262 3263 return dd->send_egress_err_status_cnt[53]; 3264 } 3265 3266 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry, 3267 void *context, int vl, int mode, 3268 u64 data) 3269 { 3270 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3271 3272 return dd->send_egress_err_status_cnt[52]; 3273 } 3274 3275 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry, 3276 void *context, int vl, int mode, 3277 u64 data) 3278 { 3279 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3280 3281 return dd->send_egress_err_status_cnt[51]; 3282 } 3283 3284 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry, 3285 void *context, int vl, int mode, 3286 u64 data) 3287 { 3288 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3289 3290 return dd->send_egress_err_status_cnt[50]; 3291 } 3292 3293 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry, 3294 void *context, int vl, int mode, 3295 u64 data) 3296 { 3297 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3298 3299 return dd->send_egress_err_status_cnt[49]; 3300 } 3301 3302 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry, 3303 void *context, int vl, int mode, 3304 u64 data) 3305 { 3306 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3307 3308 return dd->send_egress_err_status_cnt[48]; 3309 } 3310 3311 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry, 3312 void *context, int vl, int mode, 3313 u64 data) 3314 { 3315 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3316 3317 return dd->send_egress_err_status_cnt[47]; 3318 } 3319 3320 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry, 3321 void *context, int vl, int mode, 3322 u64 data) 3323 { 3324 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3325 3326 return dd->send_egress_err_status_cnt[46]; 3327 } 3328 3329 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry, 3330 void *context, int vl, int mode, 3331 u64 data) 3332 { 3333 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3334 3335 return dd->send_egress_err_status_cnt[45]; 3336 } 3337 3338 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry, 3339 void *context, int vl, 3340 int mode, u64 data) 3341 { 3342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3343 3344 return dd->send_egress_err_status_cnt[44]; 3345 } 3346 3347 static u64 access_tx_read_sdma_memory_unc_err_cnt( 3348 const struct cntr_entry *entry, 3349 void *context, int vl, int mode, u64 data) 3350 { 3351 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3352 3353 return dd->send_egress_err_status_cnt[43]; 3354 } 3355 3356 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry, 3357 void *context, int vl, int mode, 3358 u64 data) 3359 { 3360 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3361 3362 return dd->send_egress_err_status_cnt[42]; 3363 } 3364 3365 static u64 access_tx_credit_return_partiy_err_cnt( 3366 const struct cntr_entry *entry, 3367 void *context, int vl, int mode, u64 data) 3368 { 3369 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3370 3371 return dd->send_egress_err_status_cnt[41]; 3372 } 3373 3374 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt( 3375 const struct cntr_entry *entry, 3376 void *context, int vl, int mode, u64 data) 3377 { 3378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3379 3380 return dd->send_egress_err_status_cnt[40]; 3381 } 3382 3383 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt( 3384 const struct cntr_entry *entry, 3385 void *context, int vl, int mode, u64 data) 3386 { 3387 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3388 3389 return dd->send_egress_err_status_cnt[39]; 3390 } 3391 3392 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt( 3393 const struct cntr_entry *entry, 3394 void *context, int vl, int mode, u64 data) 3395 { 3396 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3397 3398 return dd->send_egress_err_status_cnt[38]; 3399 } 3400 3401 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt( 3402 const struct cntr_entry *entry, 3403 void *context, int vl, int mode, u64 data) 3404 { 3405 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3406 3407 return dd->send_egress_err_status_cnt[37]; 3408 } 3409 3410 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt( 3411 const struct cntr_entry *entry, 3412 void *context, int vl, int mode, u64 data) 3413 { 3414 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3415 3416 return dd->send_egress_err_status_cnt[36]; 3417 } 3418 3419 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt( 3420 const struct cntr_entry *entry, 3421 void *context, int vl, int mode, u64 data) 3422 { 3423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3424 3425 return dd->send_egress_err_status_cnt[35]; 3426 } 3427 3428 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt( 3429 const struct cntr_entry *entry, 3430 void *context, int vl, int mode, u64 data) 3431 { 3432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3433 3434 return dd->send_egress_err_status_cnt[34]; 3435 } 3436 3437 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt( 3438 const struct cntr_entry *entry, 3439 void *context, int vl, int mode, u64 data) 3440 { 3441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3442 3443 return dd->send_egress_err_status_cnt[33]; 3444 } 3445 3446 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt( 3447 const struct cntr_entry *entry, 3448 void *context, int vl, int mode, u64 data) 3449 { 3450 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3451 3452 return dd->send_egress_err_status_cnt[32]; 3453 } 3454 3455 static u64 access_tx_sdma15_disallowed_packet_err_cnt( 3456 const struct cntr_entry *entry, 3457 void *context, int vl, int mode, u64 data) 3458 { 3459 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3460 3461 return dd->send_egress_err_status_cnt[31]; 3462 } 3463 3464 static u64 access_tx_sdma14_disallowed_packet_err_cnt( 3465 const struct cntr_entry *entry, 3466 void *context, int vl, int mode, u64 data) 3467 { 3468 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3469 3470 return dd->send_egress_err_status_cnt[30]; 3471 } 3472 3473 static u64 access_tx_sdma13_disallowed_packet_err_cnt( 3474 const struct cntr_entry *entry, 3475 void *context, int vl, int mode, u64 data) 3476 { 3477 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3478 3479 return dd->send_egress_err_status_cnt[29]; 3480 } 3481 3482 static u64 access_tx_sdma12_disallowed_packet_err_cnt( 3483 const struct cntr_entry *entry, 3484 void *context, int vl, int mode, u64 data) 3485 { 3486 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3487 3488 return dd->send_egress_err_status_cnt[28]; 3489 } 3490 3491 static u64 access_tx_sdma11_disallowed_packet_err_cnt( 3492 const struct cntr_entry *entry, 3493 void *context, int vl, int mode, u64 data) 3494 { 3495 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3496 3497 return dd->send_egress_err_status_cnt[27]; 3498 } 3499 3500 static u64 access_tx_sdma10_disallowed_packet_err_cnt( 3501 const struct cntr_entry *entry, 3502 void *context, int vl, int mode, u64 data) 3503 { 3504 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3505 3506 return dd->send_egress_err_status_cnt[26]; 3507 } 3508 3509 static u64 access_tx_sdma9_disallowed_packet_err_cnt( 3510 const struct cntr_entry *entry, 3511 void *context, int vl, int mode, u64 data) 3512 { 3513 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3514 3515 return dd->send_egress_err_status_cnt[25]; 3516 } 3517 3518 static u64 access_tx_sdma8_disallowed_packet_err_cnt( 3519 const struct cntr_entry *entry, 3520 void *context, int vl, int mode, u64 data) 3521 { 3522 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3523 3524 return dd->send_egress_err_status_cnt[24]; 3525 } 3526 3527 static u64 access_tx_sdma7_disallowed_packet_err_cnt( 3528 const struct cntr_entry *entry, 3529 void *context, int vl, int mode, u64 data) 3530 { 3531 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3532 3533 return dd->send_egress_err_status_cnt[23]; 3534 } 3535 3536 static u64 access_tx_sdma6_disallowed_packet_err_cnt( 3537 const struct cntr_entry *entry, 3538 void *context, int vl, int mode, u64 data) 3539 { 3540 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3541 3542 return dd->send_egress_err_status_cnt[22]; 3543 } 3544 3545 static u64 access_tx_sdma5_disallowed_packet_err_cnt( 3546 const struct cntr_entry *entry, 3547 void *context, int vl, int mode, u64 data) 3548 { 3549 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3550 3551 return dd->send_egress_err_status_cnt[21]; 3552 } 3553 3554 static u64 access_tx_sdma4_disallowed_packet_err_cnt( 3555 const struct cntr_entry *entry, 3556 void *context, int vl, int mode, u64 data) 3557 { 3558 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3559 3560 return dd->send_egress_err_status_cnt[20]; 3561 } 3562 3563 static u64 access_tx_sdma3_disallowed_packet_err_cnt( 3564 const struct cntr_entry *entry, 3565 void *context, int vl, int mode, u64 data) 3566 { 3567 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3568 3569 return dd->send_egress_err_status_cnt[19]; 3570 } 3571 3572 static u64 access_tx_sdma2_disallowed_packet_err_cnt( 3573 const struct cntr_entry *entry, 3574 void *context, int vl, int mode, u64 data) 3575 { 3576 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3577 3578 return dd->send_egress_err_status_cnt[18]; 3579 } 3580 3581 static u64 access_tx_sdma1_disallowed_packet_err_cnt( 3582 const struct cntr_entry *entry, 3583 void *context, int vl, int mode, u64 data) 3584 { 3585 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3586 3587 return dd->send_egress_err_status_cnt[17]; 3588 } 3589 3590 static u64 access_tx_sdma0_disallowed_packet_err_cnt( 3591 const struct cntr_entry *entry, 3592 void *context, int vl, int mode, u64 data) 3593 { 3594 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3595 3596 return dd->send_egress_err_status_cnt[16]; 3597 } 3598 3599 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry, 3600 void *context, int vl, int mode, 3601 u64 data) 3602 { 3603 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3604 3605 return dd->send_egress_err_status_cnt[15]; 3606 } 3607 3608 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry, 3609 void *context, int vl, 3610 int mode, u64 data) 3611 { 3612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3613 3614 return dd->send_egress_err_status_cnt[14]; 3615 } 3616 3617 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry, 3618 void *context, int vl, int mode, 3619 u64 data) 3620 { 3621 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3622 3623 return dd->send_egress_err_status_cnt[13]; 3624 } 3625 3626 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry, 3627 void *context, int vl, int mode, 3628 u64 data) 3629 { 3630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3631 3632 return dd->send_egress_err_status_cnt[12]; 3633 } 3634 3635 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt( 3636 const struct cntr_entry *entry, 3637 void *context, int vl, int mode, u64 data) 3638 { 3639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3640 3641 return dd->send_egress_err_status_cnt[11]; 3642 } 3643 3644 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry, 3645 void *context, int vl, int mode, 3646 u64 data) 3647 { 3648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3649 3650 return dd->send_egress_err_status_cnt[10]; 3651 } 3652 3653 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry, 3654 void *context, int vl, int mode, 3655 u64 data) 3656 { 3657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3658 3659 return dd->send_egress_err_status_cnt[9]; 3660 } 3661 3662 static u64 access_tx_sdma_launch_intf_parity_err_cnt( 3663 const struct cntr_entry *entry, 3664 void *context, int vl, int mode, u64 data) 3665 { 3666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3667 3668 return dd->send_egress_err_status_cnt[8]; 3669 } 3670 3671 static u64 access_tx_pio_launch_intf_parity_err_cnt( 3672 const struct cntr_entry *entry, 3673 void *context, int vl, int mode, u64 data) 3674 { 3675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3676 3677 return dd->send_egress_err_status_cnt[7]; 3678 } 3679 3680 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry, 3681 void *context, int vl, int mode, 3682 u64 data) 3683 { 3684 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3685 3686 return dd->send_egress_err_status_cnt[6]; 3687 } 3688 3689 static u64 access_tx_incorrect_link_state_err_cnt( 3690 const struct cntr_entry *entry, 3691 void *context, int vl, int mode, u64 data) 3692 { 3693 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3694 3695 return dd->send_egress_err_status_cnt[5]; 3696 } 3697 3698 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry, 3699 void *context, int vl, int mode, 3700 u64 data) 3701 { 3702 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3703 3704 return dd->send_egress_err_status_cnt[4]; 3705 } 3706 3707 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt( 3708 const struct cntr_entry *entry, 3709 void *context, int vl, int mode, u64 data) 3710 { 3711 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3712 3713 return dd->send_egress_err_status_cnt[3]; 3714 } 3715 3716 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry, 3717 void *context, int vl, int mode, 3718 u64 data) 3719 { 3720 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3721 3722 return dd->send_egress_err_status_cnt[2]; 3723 } 3724 3725 static u64 access_tx_pkt_integrity_mem_unc_err_cnt( 3726 const struct cntr_entry *entry, 3727 void *context, int vl, int mode, u64 data) 3728 { 3729 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3730 3731 return dd->send_egress_err_status_cnt[1]; 3732 } 3733 3734 static u64 access_tx_pkt_integrity_mem_cor_err_cnt( 3735 const struct cntr_entry *entry, 3736 void *context, int vl, int mode, u64 data) 3737 { 3738 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3739 3740 return dd->send_egress_err_status_cnt[0]; 3741 } 3742 3743 /* 3744 * Software counters corresponding to each of the 3745 * error status bits within SendErrStatus 3746 */ 3747 static u64 access_send_csr_write_bad_addr_err_cnt( 3748 const struct cntr_entry *entry, 3749 void *context, int vl, int mode, u64 data) 3750 { 3751 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3752 3753 return dd->send_err_status_cnt[2]; 3754 } 3755 3756 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 3757 void *context, int vl, 3758 int mode, u64 data) 3759 { 3760 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3761 3762 return dd->send_err_status_cnt[1]; 3763 } 3764 3765 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry, 3766 void *context, int vl, int mode, 3767 u64 data) 3768 { 3769 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3770 3771 return dd->send_err_status_cnt[0]; 3772 } 3773 3774 /* 3775 * Software counters corresponding to each of the 3776 * error status bits within SendCtxtErrStatus 3777 */ 3778 static u64 access_pio_write_out_of_bounds_err_cnt( 3779 const struct cntr_entry *entry, 3780 void *context, int vl, int mode, u64 data) 3781 { 3782 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3783 3784 return dd->sw_ctxt_err_status_cnt[4]; 3785 } 3786 3787 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry, 3788 void *context, int vl, int mode, 3789 u64 data) 3790 { 3791 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3792 3793 return dd->sw_ctxt_err_status_cnt[3]; 3794 } 3795 3796 static u64 access_pio_write_crosses_boundary_err_cnt( 3797 const struct cntr_entry *entry, 3798 void *context, int vl, int mode, u64 data) 3799 { 3800 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3801 3802 return dd->sw_ctxt_err_status_cnt[2]; 3803 } 3804 3805 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry, 3806 void *context, int vl, 3807 int mode, u64 data) 3808 { 3809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3810 3811 return dd->sw_ctxt_err_status_cnt[1]; 3812 } 3813 3814 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry, 3815 void *context, int vl, int mode, 3816 u64 data) 3817 { 3818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3819 3820 return dd->sw_ctxt_err_status_cnt[0]; 3821 } 3822 3823 /* 3824 * Software counters corresponding to each of the 3825 * error status bits within SendDmaEngErrStatus 3826 */ 3827 static u64 access_sdma_header_request_fifo_cor_err_cnt( 3828 const struct cntr_entry *entry, 3829 void *context, int vl, int mode, u64 data) 3830 { 3831 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3832 3833 return dd->sw_send_dma_eng_err_status_cnt[23]; 3834 } 3835 3836 static u64 access_sdma_header_storage_cor_err_cnt( 3837 const struct cntr_entry *entry, 3838 void *context, int vl, int mode, u64 data) 3839 { 3840 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3841 3842 return dd->sw_send_dma_eng_err_status_cnt[22]; 3843 } 3844 3845 static u64 access_sdma_packet_tracking_cor_err_cnt( 3846 const struct cntr_entry *entry, 3847 void *context, int vl, int mode, u64 data) 3848 { 3849 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3850 3851 return dd->sw_send_dma_eng_err_status_cnt[21]; 3852 } 3853 3854 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry, 3855 void *context, int vl, int mode, 3856 u64 data) 3857 { 3858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3859 3860 return dd->sw_send_dma_eng_err_status_cnt[20]; 3861 } 3862 3863 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry, 3864 void *context, int vl, int mode, 3865 u64 data) 3866 { 3867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3868 3869 return dd->sw_send_dma_eng_err_status_cnt[19]; 3870 } 3871 3872 static u64 access_sdma_header_request_fifo_unc_err_cnt( 3873 const struct cntr_entry *entry, 3874 void *context, int vl, int mode, u64 data) 3875 { 3876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3877 3878 return dd->sw_send_dma_eng_err_status_cnt[18]; 3879 } 3880 3881 static u64 access_sdma_header_storage_unc_err_cnt( 3882 const struct cntr_entry *entry, 3883 void *context, int vl, int mode, u64 data) 3884 { 3885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3886 3887 return dd->sw_send_dma_eng_err_status_cnt[17]; 3888 } 3889 3890 static u64 access_sdma_packet_tracking_unc_err_cnt( 3891 const struct cntr_entry *entry, 3892 void *context, int vl, int mode, u64 data) 3893 { 3894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3895 3896 return dd->sw_send_dma_eng_err_status_cnt[16]; 3897 } 3898 3899 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry, 3900 void *context, int vl, int mode, 3901 u64 data) 3902 { 3903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3904 3905 return dd->sw_send_dma_eng_err_status_cnt[15]; 3906 } 3907 3908 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry, 3909 void *context, int vl, int mode, 3910 u64 data) 3911 { 3912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3913 3914 return dd->sw_send_dma_eng_err_status_cnt[14]; 3915 } 3916 3917 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry, 3918 void *context, int vl, int mode, 3919 u64 data) 3920 { 3921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3922 3923 return dd->sw_send_dma_eng_err_status_cnt[13]; 3924 } 3925 3926 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry, 3927 void *context, int vl, int mode, 3928 u64 data) 3929 { 3930 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3931 3932 return dd->sw_send_dma_eng_err_status_cnt[12]; 3933 } 3934 3935 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry, 3936 void *context, int vl, int mode, 3937 u64 data) 3938 { 3939 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3940 3941 return dd->sw_send_dma_eng_err_status_cnt[11]; 3942 } 3943 3944 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry, 3945 void *context, int vl, int mode, 3946 u64 data) 3947 { 3948 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3949 3950 return dd->sw_send_dma_eng_err_status_cnt[10]; 3951 } 3952 3953 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry, 3954 void *context, int vl, int mode, 3955 u64 data) 3956 { 3957 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3958 3959 return dd->sw_send_dma_eng_err_status_cnt[9]; 3960 } 3961 3962 static u64 access_sdma_packet_desc_overflow_err_cnt( 3963 const struct cntr_entry *entry, 3964 void *context, int vl, int mode, u64 data) 3965 { 3966 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3967 3968 return dd->sw_send_dma_eng_err_status_cnt[8]; 3969 } 3970 3971 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry, 3972 void *context, int vl, 3973 int mode, u64 data) 3974 { 3975 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3976 3977 return dd->sw_send_dma_eng_err_status_cnt[7]; 3978 } 3979 3980 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry, 3981 void *context, int vl, int mode, u64 data) 3982 { 3983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3984 3985 return dd->sw_send_dma_eng_err_status_cnt[6]; 3986 } 3987 3988 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry, 3989 void *context, int vl, int mode, 3990 u64 data) 3991 { 3992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3993 3994 return dd->sw_send_dma_eng_err_status_cnt[5]; 3995 } 3996 3997 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry, 3998 void *context, int vl, int mode, 3999 u64 data) 4000 { 4001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4002 4003 return dd->sw_send_dma_eng_err_status_cnt[4]; 4004 } 4005 4006 static u64 access_sdma_tail_out_of_bounds_err_cnt( 4007 const struct cntr_entry *entry, 4008 void *context, int vl, int mode, u64 data) 4009 { 4010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4011 4012 return dd->sw_send_dma_eng_err_status_cnt[3]; 4013 } 4014 4015 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry, 4016 void *context, int vl, int mode, 4017 u64 data) 4018 { 4019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4020 4021 return dd->sw_send_dma_eng_err_status_cnt[2]; 4022 } 4023 4024 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry, 4025 void *context, int vl, int mode, 4026 u64 data) 4027 { 4028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4029 4030 return dd->sw_send_dma_eng_err_status_cnt[1]; 4031 } 4032 4033 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry, 4034 void *context, int vl, int mode, 4035 u64 data) 4036 { 4037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4038 4039 return dd->sw_send_dma_eng_err_status_cnt[0]; 4040 } 4041 4042 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry, 4043 void *context, int vl, int mode, 4044 u64 data) 4045 { 4046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4047 4048 u64 val = 0; 4049 u64 csr = entry->csr; 4050 4051 val = read_write_csr(dd, csr, mode, data); 4052 if (mode == CNTR_MODE_R) { 4053 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ? 4054 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors; 4055 } else if (mode == CNTR_MODE_W) { 4056 dd->sw_rcv_bypass_packet_errors = 0; 4057 } else { 4058 dd_dev_err(dd, "Invalid cntr register access mode"); 4059 return 0; 4060 } 4061 return val; 4062 } 4063 4064 #define def_access_sw_cpu(cntr) \ 4065 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \ 4066 void *context, int vl, int mode, u64 data) \ 4067 { \ 4068 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4069 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \ 4070 ppd->ibport_data.rvp.cntr, vl, \ 4071 mode, data); \ 4072 } 4073 4074 def_access_sw_cpu(rc_acks); 4075 def_access_sw_cpu(rc_qacks); 4076 def_access_sw_cpu(rc_delayed_comp); 4077 4078 #define def_access_ibp_counter(cntr) \ 4079 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \ 4080 void *context, int vl, int mode, u64 data) \ 4081 { \ 4082 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4083 \ 4084 if (vl != CNTR_INVALID_VL) \ 4085 return 0; \ 4086 \ 4087 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \ 4088 mode, data); \ 4089 } 4090 4091 def_access_ibp_counter(loop_pkts); 4092 def_access_ibp_counter(rc_resends); 4093 def_access_ibp_counter(rnr_naks); 4094 def_access_ibp_counter(other_naks); 4095 def_access_ibp_counter(rc_timeouts); 4096 def_access_ibp_counter(pkt_drops); 4097 def_access_ibp_counter(dmawait); 4098 def_access_ibp_counter(rc_seqnak); 4099 def_access_ibp_counter(rc_dupreq); 4100 def_access_ibp_counter(rdma_seq); 4101 def_access_ibp_counter(unaligned); 4102 def_access_ibp_counter(seq_naks); 4103 4104 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = { 4105 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH), 4106 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT, 4107 CNTR_NORMAL), 4108 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT, 4109 CNTR_NORMAL), 4110 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs, 4111 RCV_TID_FLOW_GEN_MISMATCH_CNT, 4112 CNTR_NORMAL), 4113 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL, 4114 CNTR_NORMAL), 4115 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs, 4116 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL), 4117 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt, 4118 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL), 4119 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT, 4120 CNTR_NORMAL), 4121 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT, 4122 CNTR_NORMAL), 4123 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT, 4124 CNTR_NORMAL), 4125 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT, 4126 CNTR_NORMAL), 4127 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT, 4128 CNTR_NORMAL), 4129 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT, 4130 CNTR_NORMAL), 4131 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt, 4132 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL), 4133 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt, 4134 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL), 4135 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT, 4136 CNTR_SYNTH), 4137 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH, 4138 access_dc_rcv_err_cnt), 4139 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT, 4140 CNTR_SYNTH), 4141 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT, 4142 CNTR_SYNTH), 4143 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT, 4144 CNTR_SYNTH), 4145 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts, 4146 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH), 4147 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts, 4148 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT, 4149 CNTR_SYNTH), 4150 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr, 4151 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH), 4152 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT, 4153 CNTR_SYNTH), 4154 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT, 4155 CNTR_SYNTH), 4156 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT, 4157 CNTR_SYNTH), 4158 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT, 4159 CNTR_SYNTH), 4160 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT, 4161 CNTR_SYNTH), 4162 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT, 4163 CNTR_SYNTH), 4164 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT, 4165 CNTR_SYNTH), 4166 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT, 4167 CNTR_SYNTH | CNTR_VL), 4168 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT, 4169 CNTR_SYNTH | CNTR_VL), 4170 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH), 4171 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT, 4172 CNTR_SYNTH | CNTR_VL), 4173 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH), 4174 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT, 4175 CNTR_SYNTH | CNTR_VL), 4176 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT, 4177 CNTR_SYNTH), 4178 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT, 4179 CNTR_SYNTH | CNTR_VL), 4180 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT, 4181 CNTR_SYNTH), 4182 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT, 4183 CNTR_SYNTH | CNTR_VL), 4184 [C_DC_TOTAL_CRC] = 4185 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR, 4186 CNTR_SYNTH), 4187 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0, 4188 CNTR_SYNTH), 4189 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1, 4190 CNTR_SYNTH), 4191 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2, 4192 CNTR_SYNTH), 4193 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3, 4194 CNTR_SYNTH), 4195 [C_DC_CRC_MULT_LN] = 4196 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN, 4197 CNTR_SYNTH), 4198 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT, 4199 CNTR_SYNTH), 4200 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT, 4201 CNTR_SYNTH), 4202 [C_DC_SEQ_CRC_CNT] = 4203 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT, 4204 CNTR_SYNTH), 4205 [C_DC_ESC0_ONLY_CNT] = 4206 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT, 4207 CNTR_SYNTH), 4208 [C_DC_ESC0_PLUS1_CNT] = 4209 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT, 4210 CNTR_SYNTH), 4211 [C_DC_ESC0_PLUS2_CNT] = 4212 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT, 4213 CNTR_SYNTH), 4214 [C_DC_REINIT_FROM_PEER_CNT] = 4215 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 4216 CNTR_SYNTH), 4217 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT, 4218 CNTR_SYNTH), 4219 [C_DC_MISC_FLG_CNT] = 4220 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT, 4221 CNTR_SYNTH), 4222 [C_DC_PRF_GOOD_LTP_CNT] = 4223 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH), 4224 [C_DC_PRF_ACCEPTED_LTP_CNT] = 4225 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT, 4226 CNTR_SYNTH), 4227 [C_DC_PRF_RX_FLIT_CNT] = 4228 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH), 4229 [C_DC_PRF_TX_FLIT_CNT] = 4230 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH), 4231 [C_DC_PRF_CLK_CNTR] = 4232 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH), 4233 [C_DC_PG_DBG_FLIT_CRDTS_CNT] = 4234 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH), 4235 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] = 4236 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT, 4237 CNTR_SYNTH), 4238 [C_DC_PG_STS_TX_SBE_CNT] = 4239 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH), 4240 [C_DC_PG_STS_TX_MBE_CNT] = 4241 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT, 4242 CNTR_SYNTH), 4243 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL, 4244 access_sw_cpu_intr), 4245 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL, 4246 access_sw_cpu_rcv_limit), 4247 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL, 4248 access_sw_vtx_wait), 4249 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL, 4250 access_sw_pio_wait), 4251 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL, 4252 access_sw_pio_drain), 4253 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL, 4254 access_sw_kmem_wait), 4255 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL, 4256 access_sw_send_schedule), 4257 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn", 4258 SEND_DMA_DESC_FETCHED_CNT, 0, 4259 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4260 dev_access_u32_csr), 4261 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0, 4262 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4263 access_sde_int_cnt), 4264 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0, 4265 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4266 access_sde_err_cnt), 4267 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0, 4268 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4269 access_sde_idle_int_cnt), 4270 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0, 4271 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4272 access_sde_progress_int_cnt), 4273 /* MISC_ERR_STATUS */ 4274 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0, 4275 CNTR_NORMAL, 4276 access_misc_pll_lock_fail_err_cnt), 4277 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0, 4278 CNTR_NORMAL, 4279 access_misc_mbist_fail_err_cnt), 4280 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0, 4281 CNTR_NORMAL, 4282 access_misc_invalid_eep_cmd_err_cnt), 4283 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0, 4284 CNTR_NORMAL, 4285 access_misc_efuse_done_parity_err_cnt), 4286 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0, 4287 CNTR_NORMAL, 4288 access_misc_efuse_write_err_cnt), 4289 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0, 4290 0, CNTR_NORMAL, 4291 access_misc_efuse_read_bad_addr_err_cnt), 4292 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0, 4293 CNTR_NORMAL, 4294 access_misc_efuse_csr_parity_err_cnt), 4295 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0, 4296 CNTR_NORMAL, 4297 access_misc_fw_auth_failed_err_cnt), 4298 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0, 4299 CNTR_NORMAL, 4300 access_misc_key_mismatch_err_cnt), 4301 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0, 4302 CNTR_NORMAL, 4303 access_misc_sbus_write_failed_err_cnt), 4304 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0, 4305 CNTR_NORMAL, 4306 access_misc_csr_write_bad_addr_err_cnt), 4307 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0, 4308 CNTR_NORMAL, 4309 access_misc_csr_read_bad_addr_err_cnt), 4310 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0, 4311 CNTR_NORMAL, 4312 access_misc_csr_parity_err_cnt), 4313 /* CceErrStatus */ 4314 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0, 4315 CNTR_NORMAL, 4316 access_sw_cce_err_status_aggregated_cnt), 4317 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0, 4318 CNTR_NORMAL, 4319 access_cce_msix_csr_parity_err_cnt), 4320 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0, 4321 CNTR_NORMAL, 4322 access_cce_int_map_unc_err_cnt), 4323 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0, 4324 CNTR_NORMAL, 4325 access_cce_int_map_cor_err_cnt), 4326 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0, 4327 CNTR_NORMAL, 4328 access_cce_msix_table_unc_err_cnt), 4329 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0, 4330 CNTR_NORMAL, 4331 access_cce_msix_table_cor_err_cnt), 4332 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0, 4333 0, CNTR_NORMAL, 4334 access_cce_rxdma_conv_fifo_parity_err_cnt), 4335 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0, 4336 0, CNTR_NORMAL, 4337 access_cce_rcpl_async_fifo_parity_err_cnt), 4338 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0, 4339 CNTR_NORMAL, 4340 access_cce_seg_write_bad_addr_err_cnt), 4341 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0, 4342 CNTR_NORMAL, 4343 access_cce_seg_read_bad_addr_err_cnt), 4344 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0, 4345 CNTR_NORMAL, 4346 access_la_triggered_cnt), 4347 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0, 4348 CNTR_NORMAL, 4349 access_cce_trgt_cpl_timeout_err_cnt), 4350 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0, 4351 CNTR_NORMAL, 4352 access_pcic_receive_parity_err_cnt), 4353 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0, 4354 CNTR_NORMAL, 4355 access_pcic_transmit_back_parity_err_cnt), 4356 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0, 4357 0, CNTR_NORMAL, 4358 access_pcic_transmit_front_parity_err_cnt), 4359 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0, 4360 CNTR_NORMAL, 4361 access_pcic_cpl_dat_q_unc_err_cnt), 4362 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0, 4363 CNTR_NORMAL, 4364 access_pcic_cpl_hd_q_unc_err_cnt), 4365 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0, 4366 CNTR_NORMAL, 4367 access_pcic_post_dat_q_unc_err_cnt), 4368 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0, 4369 CNTR_NORMAL, 4370 access_pcic_post_hd_q_unc_err_cnt), 4371 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0, 4372 CNTR_NORMAL, 4373 access_pcic_retry_sot_mem_unc_err_cnt), 4374 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0, 4375 CNTR_NORMAL, 4376 access_pcic_retry_mem_unc_err), 4377 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0, 4378 CNTR_NORMAL, 4379 access_pcic_n_post_dat_q_parity_err_cnt), 4380 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0, 4381 CNTR_NORMAL, 4382 access_pcic_n_post_h_q_parity_err_cnt), 4383 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0, 4384 CNTR_NORMAL, 4385 access_pcic_cpl_dat_q_cor_err_cnt), 4386 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0, 4387 CNTR_NORMAL, 4388 access_pcic_cpl_hd_q_cor_err_cnt), 4389 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0, 4390 CNTR_NORMAL, 4391 access_pcic_post_dat_q_cor_err_cnt), 4392 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0, 4393 CNTR_NORMAL, 4394 access_pcic_post_hd_q_cor_err_cnt), 4395 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0, 4396 CNTR_NORMAL, 4397 access_pcic_retry_sot_mem_cor_err_cnt), 4398 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0, 4399 CNTR_NORMAL, 4400 access_pcic_retry_mem_cor_err_cnt), 4401 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM( 4402 "CceCli1AsyncFifoDbgParityError", 0, 0, 4403 CNTR_NORMAL, 4404 access_cce_cli1_async_fifo_dbg_parity_err_cnt), 4405 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM( 4406 "CceCli1AsyncFifoRxdmaParityError", 0, 0, 4407 CNTR_NORMAL, 4408 access_cce_cli1_async_fifo_rxdma_parity_err_cnt 4409 ), 4410 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM( 4411 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0, 4412 CNTR_NORMAL, 4413 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt), 4414 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM( 4415 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0, 4416 CNTR_NORMAL, 4417 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt), 4418 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0, 4419 0, CNTR_NORMAL, 4420 access_cce_cli2_async_fifo_parity_err_cnt), 4421 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0, 4422 CNTR_NORMAL, 4423 access_cce_csr_cfg_bus_parity_err_cnt), 4424 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0, 4425 0, CNTR_NORMAL, 4426 access_cce_cli0_async_fifo_parity_err_cnt), 4427 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0, 4428 CNTR_NORMAL, 4429 access_cce_rspd_data_parity_err_cnt), 4430 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0, 4431 CNTR_NORMAL, 4432 access_cce_trgt_access_err_cnt), 4433 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0, 4434 0, CNTR_NORMAL, 4435 access_cce_trgt_async_fifo_parity_err_cnt), 4436 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0, 4437 CNTR_NORMAL, 4438 access_cce_csr_write_bad_addr_err_cnt), 4439 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0, 4440 CNTR_NORMAL, 4441 access_cce_csr_read_bad_addr_err_cnt), 4442 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0, 4443 CNTR_NORMAL, 4444 access_ccs_csr_parity_err_cnt), 4445 4446 /* RcvErrStatus */ 4447 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0, 4448 CNTR_NORMAL, 4449 access_rx_csr_parity_err_cnt), 4450 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0, 4451 CNTR_NORMAL, 4452 access_rx_csr_write_bad_addr_err_cnt), 4453 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0, 4454 CNTR_NORMAL, 4455 access_rx_csr_read_bad_addr_err_cnt), 4456 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0, 4457 CNTR_NORMAL, 4458 access_rx_dma_csr_unc_err_cnt), 4459 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0, 4460 CNTR_NORMAL, 4461 access_rx_dma_dq_fsm_encoding_err_cnt), 4462 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0, 4463 CNTR_NORMAL, 4464 access_rx_dma_eq_fsm_encoding_err_cnt), 4465 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0, 4466 CNTR_NORMAL, 4467 access_rx_dma_csr_parity_err_cnt), 4468 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0, 4469 CNTR_NORMAL, 4470 access_rx_rbuf_data_cor_err_cnt), 4471 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0, 4472 CNTR_NORMAL, 4473 access_rx_rbuf_data_unc_err_cnt), 4474 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0, 4475 CNTR_NORMAL, 4476 access_rx_dma_data_fifo_rd_cor_err_cnt), 4477 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0, 4478 CNTR_NORMAL, 4479 access_rx_dma_data_fifo_rd_unc_err_cnt), 4480 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0, 4481 CNTR_NORMAL, 4482 access_rx_dma_hdr_fifo_rd_cor_err_cnt), 4483 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0, 4484 CNTR_NORMAL, 4485 access_rx_dma_hdr_fifo_rd_unc_err_cnt), 4486 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0, 4487 CNTR_NORMAL, 4488 access_rx_rbuf_desc_part2_cor_err_cnt), 4489 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0, 4490 CNTR_NORMAL, 4491 access_rx_rbuf_desc_part2_unc_err_cnt), 4492 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0, 4493 CNTR_NORMAL, 4494 access_rx_rbuf_desc_part1_cor_err_cnt), 4495 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0, 4496 CNTR_NORMAL, 4497 access_rx_rbuf_desc_part1_unc_err_cnt), 4498 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0, 4499 CNTR_NORMAL, 4500 access_rx_hq_intr_fsm_err_cnt), 4501 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0, 4502 CNTR_NORMAL, 4503 access_rx_hq_intr_csr_parity_err_cnt), 4504 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0, 4505 CNTR_NORMAL, 4506 access_rx_lookup_csr_parity_err_cnt), 4507 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0, 4508 CNTR_NORMAL, 4509 access_rx_lookup_rcv_array_cor_err_cnt), 4510 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0, 4511 CNTR_NORMAL, 4512 access_rx_lookup_rcv_array_unc_err_cnt), 4513 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0, 4514 0, CNTR_NORMAL, 4515 access_rx_lookup_des_part2_parity_err_cnt), 4516 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0, 4517 0, CNTR_NORMAL, 4518 access_rx_lookup_des_part1_unc_cor_err_cnt), 4519 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0, 4520 CNTR_NORMAL, 4521 access_rx_lookup_des_part1_unc_err_cnt), 4522 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0, 4523 CNTR_NORMAL, 4524 access_rx_rbuf_next_free_buf_cor_err_cnt), 4525 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0, 4526 CNTR_NORMAL, 4527 access_rx_rbuf_next_free_buf_unc_err_cnt), 4528 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM( 4529 "RxRbufFlInitWrAddrParityErr", 0, 0, 4530 CNTR_NORMAL, 4531 access_rbuf_fl_init_wr_addr_parity_err_cnt), 4532 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0, 4533 0, CNTR_NORMAL, 4534 access_rx_rbuf_fl_initdone_parity_err_cnt), 4535 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0, 4536 0, CNTR_NORMAL, 4537 access_rx_rbuf_fl_write_addr_parity_err_cnt), 4538 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0, 4539 CNTR_NORMAL, 4540 access_rx_rbuf_fl_rd_addr_parity_err_cnt), 4541 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0, 4542 CNTR_NORMAL, 4543 access_rx_rbuf_empty_err_cnt), 4544 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0, 4545 CNTR_NORMAL, 4546 access_rx_rbuf_full_err_cnt), 4547 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0, 4548 CNTR_NORMAL, 4549 access_rbuf_bad_lookup_err_cnt), 4550 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0, 4551 CNTR_NORMAL, 4552 access_rbuf_ctx_id_parity_err_cnt), 4553 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0, 4554 CNTR_NORMAL, 4555 access_rbuf_csr_qeopdw_parity_err_cnt), 4556 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM( 4557 "RxRbufCsrQNumOfPktParityErr", 0, 0, 4558 CNTR_NORMAL, 4559 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt), 4560 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM( 4561 "RxRbufCsrQTlPtrParityErr", 0, 0, 4562 CNTR_NORMAL, 4563 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt), 4564 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0, 4565 0, CNTR_NORMAL, 4566 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt), 4567 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0, 4568 0, CNTR_NORMAL, 4569 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt), 4570 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr", 4571 0, 0, CNTR_NORMAL, 4572 access_rx_rbuf_csr_q_next_buf_parity_err_cnt), 4573 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0, 4574 0, CNTR_NORMAL, 4575 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt), 4576 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM( 4577 "RxRbufCsrQHeadBufNumParityErr", 0, 0, 4578 CNTR_NORMAL, 4579 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt), 4580 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0, 4581 0, CNTR_NORMAL, 4582 access_rx_rbuf_block_list_read_cor_err_cnt), 4583 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0, 4584 0, CNTR_NORMAL, 4585 access_rx_rbuf_block_list_read_unc_err_cnt), 4586 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0, 4587 CNTR_NORMAL, 4588 access_rx_rbuf_lookup_des_cor_err_cnt), 4589 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0, 4590 CNTR_NORMAL, 4591 access_rx_rbuf_lookup_des_unc_err_cnt), 4592 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM( 4593 "RxRbufLookupDesRegUncCorErr", 0, 0, 4594 CNTR_NORMAL, 4595 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt), 4596 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0, 4597 CNTR_NORMAL, 4598 access_rx_rbuf_lookup_des_reg_unc_err_cnt), 4599 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0, 4600 CNTR_NORMAL, 4601 access_rx_rbuf_free_list_cor_err_cnt), 4602 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0, 4603 CNTR_NORMAL, 4604 access_rx_rbuf_free_list_unc_err_cnt), 4605 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0, 4606 CNTR_NORMAL, 4607 access_rx_rcv_fsm_encoding_err_cnt), 4608 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0, 4609 CNTR_NORMAL, 4610 access_rx_dma_flag_cor_err_cnt), 4611 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0, 4612 CNTR_NORMAL, 4613 access_rx_dma_flag_unc_err_cnt), 4614 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0, 4615 CNTR_NORMAL, 4616 access_rx_dc_sop_eop_parity_err_cnt), 4617 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0, 4618 CNTR_NORMAL, 4619 access_rx_rcv_csr_parity_err_cnt), 4620 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0, 4621 CNTR_NORMAL, 4622 access_rx_rcv_qp_map_table_cor_err_cnt), 4623 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0, 4624 CNTR_NORMAL, 4625 access_rx_rcv_qp_map_table_unc_err_cnt), 4626 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0, 4627 CNTR_NORMAL, 4628 access_rx_rcv_data_cor_err_cnt), 4629 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0, 4630 CNTR_NORMAL, 4631 access_rx_rcv_data_unc_err_cnt), 4632 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0, 4633 CNTR_NORMAL, 4634 access_rx_rcv_hdr_cor_err_cnt), 4635 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0, 4636 CNTR_NORMAL, 4637 access_rx_rcv_hdr_unc_err_cnt), 4638 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0, 4639 CNTR_NORMAL, 4640 access_rx_dc_intf_parity_err_cnt), 4641 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0, 4642 CNTR_NORMAL, 4643 access_rx_dma_csr_cor_err_cnt), 4644 /* SendPioErrStatus */ 4645 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0, 4646 CNTR_NORMAL, 4647 access_pio_pec_sop_head_parity_err_cnt), 4648 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0, 4649 CNTR_NORMAL, 4650 access_pio_pcc_sop_head_parity_err_cnt), 4651 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr", 4652 0, 0, CNTR_NORMAL, 4653 access_pio_last_returned_cnt_parity_err_cnt), 4654 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0, 4655 0, CNTR_NORMAL, 4656 access_pio_current_free_cnt_parity_err_cnt), 4657 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0, 4658 CNTR_NORMAL, 4659 access_pio_reserved_31_err_cnt), 4660 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0, 4661 CNTR_NORMAL, 4662 access_pio_reserved_30_err_cnt), 4663 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0, 4664 CNTR_NORMAL, 4665 access_pio_ppmc_sop_len_err_cnt), 4666 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0, 4667 CNTR_NORMAL, 4668 access_pio_ppmc_bqc_mem_parity_err_cnt), 4669 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0, 4670 CNTR_NORMAL, 4671 access_pio_vl_fifo_parity_err_cnt), 4672 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0, 4673 CNTR_NORMAL, 4674 access_pio_vlf_sop_parity_err_cnt), 4675 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0, 4676 CNTR_NORMAL, 4677 access_pio_vlf_v1_len_parity_err_cnt), 4678 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0, 4679 CNTR_NORMAL, 4680 access_pio_block_qw_count_parity_err_cnt), 4681 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0, 4682 CNTR_NORMAL, 4683 access_pio_write_qw_valid_parity_err_cnt), 4684 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0, 4685 CNTR_NORMAL, 4686 access_pio_state_machine_err_cnt), 4687 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0, 4688 CNTR_NORMAL, 4689 access_pio_write_data_parity_err_cnt), 4690 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0, 4691 CNTR_NORMAL, 4692 access_pio_host_addr_mem_cor_err_cnt), 4693 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0, 4694 CNTR_NORMAL, 4695 access_pio_host_addr_mem_unc_err_cnt), 4696 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0, 4697 CNTR_NORMAL, 4698 access_pio_pkt_evict_sm_or_arb_sm_err_cnt), 4699 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0, 4700 CNTR_NORMAL, 4701 access_pio_init_sm_in_err_cnt), 4702 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0, 4703 CNTR_NORMAL, 4704 access_pio_ppmc_pbl_fifo_err_cnt), 4705 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0, 4706 0, CNTR_NORMAL, 4707 access_pio_credit_ret_fifo_parity_err_cnt), 4708 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0, 4709 CNTR_NORMAL, 4710 access_pio_v1_len_mem_bank1_cor_err_cnt), 4711 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0, 4712 CNTR_NORMAL, 4713 access_pio_v1_len_mem_bank0_cor_err_cnt), 4714 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0, 4715 CNTR_NORMAL, 4716 access_pio_v1_len_mem_bank1_unc_err_cnt), 4717 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0, 4718 CNTR_NORMAL, 4719 access_pio_v1_len_mem_bank0_unc_err_cnt), 4720 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0, 4721 CNTR_NORMAL, 4722 access_pio_sm_pkt_reset_parity_err_cnt), 4723 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0, 4724 CNTR_NORMAL, 4725 access_pio_pkt_evict_fifo_parity_err_cnt), 4726 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM( 4727 "PioSbrdctrlCrrelFifoParityErr", 0, 0, 4728 CNTR_NORMAL, 4729 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt), 4730 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0, 4731 CNTR_NORMAL, 4732 access_pio_sbrdctl_crrel_parity_err_cnt), 4733 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0, 4734 CNTR_NORMAL, 4735 access_pio_pec_fifo_parity_err_cnt), 4736 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0, 4737 CNTR_NORMAL, 4738 access_pio_pcc_fifo_parity_err_cnt), 4739 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0, 4740 CNTR_NORMAL, 4741 access_pio_sb_mem_fifo1_err_cnt), 4742 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0, 4743 CNTR_NORMAL, 4744 access_pio_sb_mem_fifo0_err_cnt), 4745 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0, 4746 CNTR_NORMAL, 4747 access_pio_csr_parity_err_cnt), 4748 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0, 4749 CNTR_NORMAL, 4750 access_pio_write_addr_parity_err_cnt), 4751 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0, 4752 CNTR_NORMAL, 4753 access_pio_write_bad_ctxt_err_cnt), 4754 /* SendDmaErrStatus */ 4755 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0, 4756 0, CNTR_NORMAL, 4757 access_sdma_pcie_req_tracking_cor_err_cnt), 4758 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0, 4759 0, CNTR_NORMAL, 4760 access_sdma_pcie_req_tracking_unc_err_cnt), 4761 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0, 4762 CNTR_NORMAL, 4763 access_sdma_csr_parity_err_cnt), 4764 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0, 4765 CNTR_NORMAL, 4766 access_sdma_rpy_tag_err_cnt), 4767 /* SendEgressErrStatus */ 4768 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0, 4769 CNTR_NORMAL, 4770 access_tx_read_pio_memory_csr_unc_err_cnt), 4771 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0, 4772 0, CNTR_NORMAL, 4773 access_tx_read_sdma_memory_csr_err_cnt), 4774 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0, 4775 CNTR_NORMAL, 4776 access_tx_egress_fifo_cor_err_cnt), 4777 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0, 4778 CNTR_NORMAL, 4779 access_tx_read_pio_memory_cor_err_cnt), 4780 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0, 4781 CNTR_NORMAL, 4782 access_tx_read_sdma_memory_cor_err_cnt), 4783 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0, 4784 CNTR_NORMAL, 4785 access_tx_sb_hdr_cor_err_cnt), 4786 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0, 4787 CNTR_NORMAL, 4788 access_tx_credit_overrun_err_cnt), 4789 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0, 4790 CNTR_NORMAL, 4791 access_tx_launch_fifo8_cor_err_cnt), 4792 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0, 4793 CNTR_NORMAL, 4794 access_tx_launch_fifo7_cor_err_cnt), 4795 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0, 4796 CNTR_NORMAL, 4797 access_tx_launch_fifo6_cor_err_cnt), 4798 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0, 4799 CNTR_NORMAL, 4800 access_tx_launch_fifo5_cor_err_cnt), 4801 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0, 4802 CNTR_NORMAL, 4803 access_tx_launch_fifo4_cor_err_cnt), 4804 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0, 4805 CNTR_NORMAL, 4806 access_tx_launch_fifo3_cor_err_cnt), 4807 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0, 4808 CNTR_NORMAL, 4809 access_tx_launch_fifo2_cor_err_cnt), 4810 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0, 4811 CNTR_NORMAL, 4812 access_tx_launch_fifo1_cor_err_cnt), 4813 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0, 4814 CNTR_NORMAL, 4815 access_tx_launch_fifo0_cor_err_cnt), 4816 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0, 4817 CNTR_NORMAL, 4818 access_tx_credit_return_vl_err_cnt), 4819 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0, 4820 CNTR_NORMAL, 4821 access_tx_hcrc_insertion_err_cnt), 4822 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0, 4823 CNTR_NORMAL, 4824 access_tx_egress_fifo_unc_err_cnt), 4825 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0, 4826 CNTR_NORMAL, 4827 access_tx_read_pio_memory_unc_err_cnt), 4828 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0, 4829 CNTR_NORMAL, 4830 access_tx_read_sdma_memory_unc_err_cnt), 4831 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0, 4832 CNTR_NORMAL, 4833 access_tx_sb_hdr_unc_err_cnt), 4834 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0, 4835 CNTR_NORMAL, 4836 access_tx_credit_return_partiy_err_cnt), 4837 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr", 4838 0, 0, CNTR_NORMAL, 4839 access_tx_launch_fifo8_unc_or_parity_err_cnt), 4840 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr", 4841 0, 0, CNTR_NORMAL, 4842 access_tx_launch_fifo7_unc_or_parity_err_cnt), 4843 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr", 4844 0, 0, CNTR_NORMAL, 4845 access_tx_launch_fifo6_unc_or_parity_err_cnt), 4846 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr", 4847 0, 0, CNTR_NORMAL, 4848 access_tx_launch_fifo5_unc_or_parity_err_cnt), 4849 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr", 4850 0, 0, CNTR_NORMAL, 4851 access_tx_launch_fifo4_unc_or_parity_err_cnt), 4852 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr", 4853 0, 0, CNTR_NORMAL, 4854 access_tx_launch_fifo3_unc_or_parity_err_cnt), 4855 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr", 4856 0, 0, CNTR_NORMAL, 4857 access_tx_launch_fifo2_unc_or_parity_err_cnt), 4858 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr", 4859 0, 0, CNTR_NORMAL, 4860 access_tx_launch_fifo1_unc_or_parity_err_cnt), 4861 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr", 4862 0, 0, CNTR_NORMAL, 4863 access_tx_launch_fifo0_unc_or_parity_err_cnt), 4864 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr", 4865 0, 0, CNTR_NORMAL, 4866 access_tx_sdma15_disallowed_packet_err_cnt), 4867 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr", 4868 0, 0, CNTR_NORMAL, 4869 access_tx_sdma14_disallowed_packet_err_cnt), 4870 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr", 4871 0, 0, CNTR_NORMAL, 4872 access_tx_sdma13_disallowed_packet_err_cnt), 4873 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr", 4874 0, 0, CNTR_NORMAL, 4875 access_tx_sdma12_disallowed_packet_err_cnt), 4876 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr", 4877 0, 0, CNTR_NORMAL, 4878 access_tx_sdma11_disallowed_packet_err_cnt), 4879 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr", 4880 0, 0, CNTR_NORMAL, 4881 access_tx_sdma10_disallowed_packet_err_cnt), 4882 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr", 4883 0, 0, CNTR_NORMAL, 4884 access_tx_sdma9_disallowed_packet_err_cnt), 4885 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr", 4886 0, 0, CNTR_NORMAL, 4887 access_tx_sdma8_disallowed_packet_err_cnt), 4888 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr", 4889 0, 0, CNTR_NORMAL, 4890 access_tx_sdma7_disallowed_packet_err_cnt), 4891 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr", 4892 0, 0, CNTR_NORMAL, 4893 access_tx_sdma6_disallowed_packet_err_cnt), 4894 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr", 4895 0, 0, CNTR_NORMAL, 4896 access_tx_sdma5_disallowed_packet_err_cnt), 4897 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr", 4898 0, 0, CNTR_NORMAL, 4899 access_tx_sdma4_disallowed_packet_err_cnt), 4900 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr", 4901 0, 0, CNTR_NORMAL, 4902 access_tx_sdma3_disallowed_packet_err_cnt), 4903 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr", 4904 0, 0, CNTR_NORMAL, 4905 access_tx_sdma2_disallowed_packet_err_cnt), 4906 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr", 4907 0, 0, CNTR_NORMAL, 4908 access_tx_sdma1_disallowed_packet_err_cnt), 4909 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr", 4910 0, 0, CNTR_NORMAL, 4911 access_tx_sdma0_disallowed_packet_err_cnt), 4912 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0, 4913 CNTR_NORMAL, 4914 access_tx_config_parity_err_cnt), 4915 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0, 4916 CNTR_NORMAL, 4917 access_tx_sbrd_ctl_csr_parity_err_cnt), 4918 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0, 4919 CNTR_NORMAL, 4920 access_tx_launch_csr_parity_err_cnt), 4921 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0, 4922 CNTR_NORMAL, 4923 access_tx_illegal_vl_err_cnt), 4924 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM( 4925 "TxSbrdCtlStateMachineParityErr", 0, 0, 4926 CNTR_NORMAL, 4927 access_tx_sbrd_ctl_state_machine_parity_err_cnt), 4928 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0, 4929 CNTR_NORMAL, 4930 access_egress_reserved_10_err_cnt), 4931 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0, 4932 CNTR_NORMAL, 4933 access_egress_reserved_9_err_cnt), 4934 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr", 4935 0, 0, CNTR_NORMAL, 4936 access_tx_sdma_launch_intf_parity_err_cnt), 4937 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0, 4938 CNTR_NORMAL, 4939 access_tx_pio_launch_intf_parity_err_cnt), 4940 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0, 4941 CNTR_NORMAL, 4942 access_egress_reserved_6_err_cnt), 4943 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0, 4944 CNTR_NORMAL, 4945 access_tx_incorrect_link_state_err_cnt), 4946 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0, 4947 CNTR_NORMAL, 4948 access_tx_linkdown_err_cnt), 4949 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM( 4950 "EgressFifoUnderrunOrParityErr", 0, 0, 4951 CNTR_NORMAL, 4952 access_tx_egress_fifi_underrun_or_parity_err_cnt), 4953 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0, 4954 CNTR_NORMAL, 4955 access_egress_reserved_2_err_cnt), 4956 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0, 4957 CNTR_NORMAL, 4958 access_tx_pkt_integrity_mem_unc_err_cnt), 4959 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0, 4960 CNTR_NORMAL, 4961 access_tx_pkt_integrity_mem_cor_err_cnt), 4962 /* SendErrStatus */ 4963 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0, 4964 CNTR_NORMAL, 4965 access_send_csr_write_bad_addr_err_cnt), 4966 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0, 4967 CNTR_NORMAL, 4968 access_send_csr_read_bad_addr_err_cnt), 4969 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0, 4970 CNTR_NORMAL, 4971 access_send_csr_parity_cnt), 4972 /* SendCtxtErrStatus */ 4973 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0, 4974 CNTR_NORMAL, 4975 access_pio_write_out_of_bounds_err_cnt), 4976 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0, 4977 CNTR_NORMAL, 4978 access_pio_write_overflow_err_cnt), 4979 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr", 4980 0, 0, CNTR_NORMAL, 4981 access_pio_write_crosses_boundary_err_cnt), 4982 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0, 4983 CNTR_NORMAL, 4984 access_pio_disallowed_packet_err_cnt), 4985 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0, 4986 CNTR_NORMAL, 4987 access_pio_inconsistent_sop_err_cnt), 4988 /* SendDmaEngErrStatus */ 4989 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr", 4990 0, 0, CNTR_NORMAL, 4991 access_sdma_header_request_fifo_cor_err_cnt), 4992 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0, 4993 CNTR_NORMAL, 4994 access_sdma_header_storage_cor_err_cnt), 4995 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0, 4996 CNTR_NORMAL, 4997 access_sdma_packet_tracking_cor_err_cnt), 4998 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0, 4999 CNTR_NORMAL, 5000 access_sdma_assembly_cor_err_cnt), 5001 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0, 5002 CNTR_NORMAL, 5003 access_sdma_desc_table_cor_err_cnt), 5004 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr", 5005 0, 0, CNTR_NORMAL, 5006 access_sdma_header_request_fifo_unc_err_cnt), 5007 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0, 5008 CNTR_NORMAL, 5009 access_sdma_header_storage_unc_err_cnt), 5010 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0, 5011 CNTR_NORMAL, 5012 access_sdma_packet_tracking_unc_err_cnt), 5013 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0, 5014 CNTR_NORMAL, 5015 access_sdma_assembly_unc_err_cnt), 5016 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0, 5017 CNTR_NORMAL, 5018 access_sdma_desc_table_unc_err_cnt), 5019 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0, 5020 CNTR_NORMAL, 5021 access_sdma_timeout_err_cnt), 5022 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0, 5023 CNTR_NORMAL, 5024 access_sdma_header_length_err_cnt), 5025 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0, 5026 CNTR_NORMAL, 5027 access_sdma_header_address_err_cnt), 5028 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0, 5029 CNTR_NORMAL, 5030 access_sdma_header_select_err_cnt), 5031 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0, 5032 CNTR_NORMAL, 5033 access_sdma_reserved_9_err_cnt), 5034 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0, 5035 CNTR_NORMAL, 5036 access_sdma_packet_desc_overflow_err_cnt), 5037 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0, 5038 CNTR_NORMAL, 5039 access_sdma_length_mismatch_err_cnt), 5040 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0, 5041 CNTR_NORMAL, 5042 access_sdma_halt_err_cnt), 5043 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0, 5044 CNTR_NORMAL, 5045 access_sdma_mem_read_err_cnt), 5046 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0, 5047 CNTR_NORMAL, 5048 access_sdma_first_desc_err_cnt), 5049 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0, 5050 CNTR_NORMAL, 5051 access_sdma_tail_out_of_bounds_err_cnt), 5052 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0, 5053 CNTR_NORMAL, 5054 access_sdma_too_long_err_cnt), 5055 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0, 5056 CNTR_NORMAL, 5057 access_sdma_gen_mismatch_err_cnt), 5058 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0, 5059 CNTR_NORMAL, 5060 access_sdma_wrong_dw_err_cnt), 5061 }; 5062 5063 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = { 5064 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT, 5065 CNTR_NORMAL), 5066 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT, 5067 CNTR_NORMAL), 5068 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT, 5069 CNTR_NORMAL), 5070 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT, 5071 CNTR_NORMAL), 5072 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT, 5073 CNTR_NORMAL), 5074 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT, 5075 CNTR_NORMAL), 5076 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT, 5077 CNTR_NORMAL), 5078 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL), 5079 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL), 5080 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH), 5081 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT, 5082 CNTR_SYNTH | CNTR_VL), 5083 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT, 5084 CNTR_SYNTH | CNTR_VL), 5085 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT, 5086 CNTR_SYNTH | CNTR_VL), 5087 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL), 5088 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL), 5089 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5090 access_sw_link_dn_cnt), 5091 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5092 access_sw_link_up_cnt), 5093 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL, 5094 access_sw_unknown_frame_cnt), 5095 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5096 access_sw_xmit_discards), 5097 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0, 5098 CNTR_SYNTH | CNTR_32BIT | CNTR_VL, 5099 access_sw_xmit_discards), 5100 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH, 5101 access_xmit_constraint_errs), 5102 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH, 5103 access_rcv_constraint_errs), 5104 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts), 5105 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends), 5106 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks), 5107 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks), 5108 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts), 5109 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops), 5110 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait), 5111 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak), 5112 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq), 5113 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq), 5114 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned), 5115 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks), 5116 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL, 5117 access_sw_cpu_rc_acks), 5118 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL, 5119 access_sw_cpu_rc_qacks), 5120 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL, 5121 access_sw_cpu_rc_delayed_comp), 5122 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1), 5123 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3), 5124 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5), 5125 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7), 5126 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9), 5127 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11), 5128 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13), 5129 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15), 5130 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17), 5131 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19), 5132 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21), 5133 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23), 5134 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25), 5135 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27), 5136 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29), 5137 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31), 5138 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33), 5139 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35), 5140 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37), 5141 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39), 5142 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41), 5143 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43), 5144 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45), 5145 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47), 5146 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49), 5147 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51), 5148 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53), 5149 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55), 5150 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57), 5151 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59), 5152 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61), 5153 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63), 5154 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65), 5155 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67), 5156 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69), 5157 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71), 5158 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73), 5159 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75), 5160 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77), 5161 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79), 5162 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81), 5163 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83), 5164 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85), 5165 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87), 5166 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89), 5167 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91), 5168 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93), 5169 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95), 5170 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97), 5171 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99), 5172 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101), 5173 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103), 5174 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105), 5175 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107), 5176 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109), 5177 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111), 5178 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113), 5179 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115), 5180 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117), 5181 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119), 5182 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121), 5183 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123), 5184 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125), 5185 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127), 5186 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129), 5187 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131), 5188 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133), 5189 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135), 5190 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137), 5191 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139), 5192 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141), 5193 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143), 5194 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145), 5195 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147), 5196 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149), 5197 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151), 5198 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153), 5199 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155), 5200 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157), 5201 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159), 5202 }; 5203 5204 /* ======================================================================== */ 5205 5206 /* return true if this is chip revision revision a */ 5207 int is_ax(struct hfi1_devdata *dd) 5208 { 5209 u8 chip_rev_minor = 5210 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5211 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5212 return (chip_rev_minor & 0xf0) == 0; 5213 } 5214 5215 /* return true if this is chip revision revision b */ 5216 int is_bx(struct hfi1_devdata *dd) 5217 { 5218 u8 chip_rev_minor = 5219 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5220 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5221 return (chip_rev_minor & 0xF0) == 0x10; 5222 } 5223 5224 /* 5225 * Append string s to buffer buf. Arguments curp and len are the current 5226 * position and remaining length, respectively. 5227 * 5228 * return 0 on success, 1 on out of room 5229 */ 5230 static int append_str(char *buf, char **curp, int *lenp, const char *s) 5231 { 5232 char *p = *curp; 5233 int len = *lenp; 5234 int result = 0; /* success */ 5235 char c; 5236 5237 /* add a comma, if first in the buffer */ 5238 if (p != buf) { 5239 if (len == 0) { 5240 result = 1; /* out of room */ 5241 goto done; 5242 } 5243 *p++ = ','; 5244 len--; 5245 } 5246 5247 /* copy the string */ 5248 while ((c = *s++) != 0) { 5249 if (len == 0) { 5250 result = 1; /* out of room */ 5251 goto done; 5252 } 5253 *p++ = c; 5254 len--; 5255 } 5256 5257 done: 5258 /* write return values */ 5259 *curp = p; 5260 *lenp = len; 5261 5262 return result; 5263 } 5264 5265 /* 5266 * Using the given flag table, print a comma separated string into 5267 * the buffer. End in '*' if the buffer is too short. 5268 */ 5269 static char *flag_string(char *buf, int buf_len, u64 flags, 5270 struct flag_table *table, int table_size) 5271 { 5272 char extra[32]; 5273 char *p = buf; 5274 int len = buf_len; 5275 int no_room = 0; 5276 int i; 5277 5278 /* make sure there is at least 2 so we can form "*" */ 5279 if (len < 2) 5280 return ""; 5281 5282 len--; /* leave room for a nul */ 5283 for (i = 0; i < table_size; i++) { 5284 if (flags & table[i].flag) { 5285 no_room = append_str(buf, &p, &len, table[i].str); 5286 if (no_room) 5287 break; 5288 flags &= ~table[i].flag; 5289 } 5290 } 5291 5292 /* any undocumented bits left? */ 5293 if (!no_room && flags) { 5294 snprintf(extra, sizeof(extra), "bits 0x%llx", flags); 5295 no_room = append_str(buf, &p, &len, extra); 5296 } 5297 5298 /* add * if ran out of room */ 5299 if (no_room) { 5300 /* may need to back up to add space for a '*' */ 5301 if (len == 0) 5302 --p; 5303 *p++ = '*'; 5304 } 5305 5306 /* add final nul - space already allocated above */ 5307 *p = 0; 5308 return buf; 5309 } 5310 5311 /* first 8 CCE error interrupt source names */ 5312 static const char * const cce_misc_names[] = { 5313 "CceErrInt", /* 0 */ 5314 "RxeErrInt", /* 1 */ 5315 "MiscErrInt", /* 2 */ 5316 "Reserved3", /* 3 */ 5317 "PioErrInt", /* 4 */ 5318 "SDmaErrInt", /* 5 */ 5319 "EgressErrInt", /* 6 */ 5320 "TxeErrInt" /* 7 */ 5321 }; 5322 5323 /* 5324 * Return the miscellaneous error interrupt name. 5325 */ 5326 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source) 5327 { 5328 if (source < ARRAY_SIZE(cce_misc_names)) 5329 strncpy(buf, cce_misc_names[source], bsize); 5330 else 5331 snprintf(buf, bsize, "Reserved%u", 5332 source + IS_GENERAL_ERR_START); 5333 5334 return buf; 5335 } 5336 5337 /* 5338 * Return the SDMA engine error interrupt name. 5339 */ 5340 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source) 5341 { 5342 snprintf(buf, bsize, "SDmaEngErrInt%u", source); 5343 return buf; 5344 } 5345 5346 /* 5347 * Return the send context error interrupt name. 5348 */ 5349 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source) 5350 { 5351 snprintf(buf, bsize, "SendCtxtErrInt%u", source); 5352 return buf; 5353 } 5354 5355 static const char * const various_names[] = { 5356 "PbcInt", 5357 "GpioAssertInt", 5358 "Qsfp1Int", 5359 "Qsfp2Int", 5360 "TCritInt" 5361 }; 5362 5363 /* 5364 * Return the various interrupt name. 5365 */ 5366 static char *is_various_name(char *buf, size_t bsize, unsigned int source) 5367 { 5368 if (source < ARRAY_SIZE(various_names)) 5369 strncpy(buf, various_names[source], bsize); 5370 else 5371 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START); 5372 return buf; 5373 } 5374 5375 /* 5376 * Return the DC interrupt name. 5377 */ 5378 static char *is_dc_name(char *buf, size_t bsize, unsigned int source) 5379 { 5380 static const char * const dc_int_names[] = { 5381 "common", 5382 "lcb", 5383 "8051", 5384 "lbm" /* local block merge */ 5385 }; 5386 5387 if (source < ARRAY_SIZE(dc_int_names)) 5388 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]); 5389 else 5390 snprintf(buf, bsize, "DCInt%u", source); 5391 return buf; 5392 } 5393 5394 static const char * const sdma_int_names[] = { 5395 "SDmaInt", 5396 "SdmaIdleInt", 5397 "SdmaProgressInt", 5398 }; 5399 5400 /* 5401 * Return the SDMA engine interrupt name. 5402 */ 5403 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source) 5404 { 5405 /* what interrupt */ 5406 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 5407 /* which engine */ 5408 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 5409 5410 if (likely(what < 3)) 5411 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which); 5412 else 5413 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source); 5414 return buf; 5415 } 5416 5417 /* 5418 * Return the receive available interrupt name. 5419 */ 5420 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source) 5421 { 5422 snprintf(buf, bsize, "RcvAvailInt%u", source); 5423 return buf; 5424 } 5425 5426 /* 5427 * Return the receive urgent interrupt name. 5428 */ 5429 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source) 5430 { 5431 snprintf(buf, bsize, "RcvUrgentInt%u", source); 5432 return buf; 5433 } 5434 5435 /* 5436 * Return the send credit interrupt name. 5437 */ 5438 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source) 5439 { 5440 snprintf(buf, bsize, "SendCreditInt%u", source); 5441 return buf; 5442 } 5443 5444 /* 5445 * Return the reserved interrupt name. 5446 */ 5447 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source) 5448 { 5449 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START); 5450 return buf; 5451 } 5452 5453 static char *cce_err_status_string(char *buf, int buf_len, u64 flags) 5454 { 5455 return flag_string(buf, buf_len, flags, 5456 cce_err_status_flags, 5457 ARRAY_SIZE(cce_err_status_flags)); 5458 } 5459 5460 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags) 5461 { 5462 return flag_string(buf, buf_len, flags, 5463 rxe_err_status_flags, 5464 ARRAY_SIZE(rxe_err_status_flags)); 5465 } 5466 5467 static char *misc_err_status_string(char *buf, int buf_len, u64 flags) 5468 { 5469 return flag_string(buf, buf_len, flags, misc_err_status_flags, 5470 ARRAY_SIZE(misc_err_status_flags)); 5471 } 5472 5473 static char *pio_err_status_string(char *buf, int buf_len, u64 flags) 5474 { 5475 return flag_string(buf, buf_len, flags, 5476 pio_err_status_flags, 5477 ARRAY_SIZE(pio_err_status_flags)); 5478 } 5479 5480 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags) 5481 { 5482 return flag_string(buf, buf_len, flags, 5483 sdma_err_status_flags, 5484 ARRAY_SIZE(sdma_err_status_flags)); 5485 } 5486 5487 static char *egress_err_status_string(char *buf, int buf_len, u64 flags) 5488 { 5489 return flag_string(buf, buf_len, flags, 5490 egress_err_status_flags, 5491 ARRAY_SIZE(egress_err_status_flags)); 5492 } 5493 5494 static char *egress_err_info_string(char *buf, int buf_len, u64 flags) 5495 { 5496 return flag_string(buf, buf_len, flags, 5497 egress_err_info_flags, 5498 ARRAY_SIZE(egress_err_info_flags)); 5499 } 5500 5501 static char *send_err_status_string(char *buf, int buf_len, u64 flags) 5502 { 5503 return flag_string(buf, buf_len, flags, 5504 send_err_status_flags, 5505 ARRAY_SIZE(send_err_status_flags)); 5506 } 5507 5508 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5509 { 5510 char buf[96]; 5511 int i = 0; 5512 5513 /* 5514 * For most these errors, there is nothing that can be done except 5515 * report or record it. 5516 */ 5517 dd_dev_info(dd, "CCE Error: %s\n", 5518 cce_err_status_string(buf, sizeof(buf), reg)); 5519 5520 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) && 5521 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) { 5522 /* this error requires a manual drop into SPC freeze mode */ 5523 /* then a fix up */ 5524 start_freeze_handling(dd->pport, FREEZE_SELF); 5525 } 5526 5527 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) { 5528 if (reg & (1ull << i)) { 5529 incr_cntr64(&dd->cce_err_status_cnt[i]); 5530 /* maintain a counter over all cce_err_status errors */ 5531 incr_cntr64(&dd->sw_cce_err_status_aggregate); 5532 } 5533 } 5534 } 5535 5536 /* 5537 * Check counters for receive errors that do not have an interrupt 5538 * associated with them. 5539 */ 5540 #define RCVERR_CHECK_TIME 10 5541 static void update_rcverr_timer(struct timer_list *t) 5542 { 5543 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer); 5544 struct hfi1_pportdata *ppd = dd->pport; 5545 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL); 5546 5547 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt && 5548 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) { 5549 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__); 5550 set_link_down_reason( 5551 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0, 5552 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN); 5553 queue_work(ppd->link_wq, &ppd->link_bounce_work); 5554 } 5555 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt; 5556 5557 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5558 } 5559 5560 static int init_rcverr(struct hfi1_devdata *dd) 5561 { 5562 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0); 5563 /* Assume the hardware counter has been reset */ 5564 dd->rcv_ovfl_cnt = 0; 5565 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5566 } 5567 5568 static void free_rcverr(struct hfi1_devdata *dd) 5569 { 5570 if (dd->rcverr_timer.function) 5571 del_timer_sync(&dd->rcverr_timer); 5572 } 5573 5574 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5575 { 5576 char buf[96]; 5577 int i = 0; 5578 5579 dd_dev_info(dd, "Receive Error: %s\n", 5580 rxe_err_status_string(buf, sizeof(buf), reg)); 5581 5582 if (reg & ALL_RXE_FREEZE_ERR) { 5583 int flags = 0; 5584 5585 /* 5586 * Freeze mode recovery is disabled for the errors 5587 * in RXE_FREEZE_ABORT_MASK 5588 */ 5589 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK)) 5590 flags = FREEZE_ABORT; 5591 5592 start_freeze_handling(dd->pport, flags); 5593 } 5594 5595 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) { 5596 if (reg & (1ull << i)) 5597 incr_cntr64(&dd->rcv_err_status_cnt[i]); 5598 } 5599 } 5600 5601 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5602 { 5603 char buf[96]; 5604 int i = 0; 5605 5606 dd_dev_info(dd, "Misc Error: %s", 5607 misc_err_status_string(buf, sizeof(buf), reg)); 5608 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) { 5609 if (reg & (1ull << i)) 5610 incr_cntr64(&dd->misc_err_status_cnt[i]); 5611 } 5612 } 5613 5614 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5615 { 5616 char buf[96]; 5617 int i = 0; 5618 5619 dd_dev_info(dd, "PIO Error: %s\n", 5620 pio_err_status_string(buf, sizeof(buf), reg)); 5621 5622 if (reg & ALL_PIO_FREEZE_ERR) 5623 start_freeze_handling(dd->pport, 0); 5624 5625 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) { 5626 if (reg & (1ull << i)) 5627 incr_cntr64(&dd->send_pio_err_status_cnt[i]); 5628 } 5629 } 5630 5631 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5632 { 5633 char buf[96]; 5634 int i = 0; 5635 5636 dd_dev_info(dd, "SDMA Error: %s\n", 5637 sdma_err_status_string(buf, sizeof(buf), reg)); 5638 5639 if (reg & ALL_SDMA_FREEZE_ERR) 5640 start_freeze_handling(dd->pport, 0); 5641 5642 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) { 5643 if (reg & (1ull << i)) 5644 incr_cntr64(&dd->send_dma_err_status_cnt[i]); 5645 } 5646 } 5647 5648 static inline void __count_port_discards(struct hfi1_pportdata *ppd) 5649 { 5650 incr_cntr64(&ppd->port_xmit_discards); 5651 } 5652 5653 static void count_port_inactive(struct hfi1_devdata *dd) 5654 { 5655 __count_port_discards(dd->pport); 5656 } 5657 5658 /* 5659 * We have had a "disallowed packet" error during egress. Determine the 5660 * integrity check which failed, and update relevant error counter, etc. 5661 * 5662 * Note that the SEND_EGRESS_ERR_INFO register has only a single 5663 * bit of state per integrity check, and so we can miss the reason for an 5664 * egress error if more than one packet fails the same integrity check 5665 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO. 5666 */ 5667 static void handle_send_egress_err_info(struct hfi1_devdata *dd, 5668 int vl) 5669 { 5670 struct hfi1_pportdata *ppd = dd->pport; 5671 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ 5672 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); 5673 char buf[96]; 5674 5675 /* clear down all observed info as quickly as possible after read */ 5676 write_csr(dd, SEND_EGRESS_ERR_INFO, info); 5677 5678 dd_dev_info(dd, 5679 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n", 5680 info, egress_err_info_string(buf, sizeof(buf), info), src); 5681 5682 /* Eventually add other counters for each bit */ 5683 if (info & PORT_DISCARD_EGRESS_ERRS) { 5684 int weight, i; 5685 5686 /* 5687 * Count all applicable bits as individual errors and 5688 * attribute them to the packet that triggered this handler. 5689 * This may not be completely accurate due to limitations 5690 * on the available hardware error information. There is 5691 * a single information register and any number of error 5692 * packets may have occurred and contributed to it before 5693 * this routine is called. This means that: 5694 * a) If multiple packets with the same error occur before 5695 * this routine is called, earlier packets are missed. 5696 * There is only a single bit for each error type. 5697 * b) Errors may not be attributed to the correct VL. 5698 * The driver is attributing all bits in the info register 5699 * to the packet that triggered this call, but bits 5700 * could be an accumulation of different packets with 5701 * different VLs. 5702 * c) A single error packet may have multiple counts attached 5703 * to it. There is no way for the driver to know if 5704 * multiple bits set in the info register are due to a 5705 * single packet or multiple packets. The driver assumes 5706 * multiple packets. 5707 */ 5708 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS); 5709 for (i = 0; i < weight; i++) { 5710 __count_port_discards(ppd); 5711 if (vl >= 0 && vl < TXE_NUM_DATA_VL) 5712 incr_cntr64(&ppd->port_xmit_discards_vl[vl]); 5713 else if (vl == 15) 5714 incr_cntr64(&ppd->port_xmit_discards_vl 5715 [C_VL_15]); 5716 } 5717 } 5718 } 5719 5720 /* 5721 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5722 * register. Does it represent a 'port inactive' error? 5723 */ 5724 static inline int port_inactive_err(u64 posn) 5725 { 5726 return (posn >= SEES(TX_LINKDOWN) && 5727 posn <= SEES(TX_INCORRECT_LINK_STATE)); 5728 } 5729 5730 /* 5731 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5732 * register. Does it represent a 'disallowed packet' error? 5733 */ 5734 static inline int disallowed_pkt_err(int posn) 5735 { 5736 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) && 5737 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET)); 5738 } 5739 5740 /* 5741 * Input value is a bit position of one of the SDMA engine disallowed 5742 * packet errors. Return which engine. Use of this must be guarded by 5743 * disallowed_pkt_err(). 5744 */ 5745 static inline int disallowed_pkt_engine(int posn) 5746 { 5747 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET); 5748 } 5749 5750 /* 5751 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot 5752 * be done. 5753 */ 5754 static int engine_to_vl(struct hfi1_devdata *dd, int engine) 5755 { 5756 struct sdma_vl_map *m; 5757 int vl; 5758 5759 /* range check */ 5760 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES) 5761 return -1; 5762 5763 rcu_read_lock(); 5764 m = rcu_dereference(dd->sdma_map); 5765 vl = m->engine_to_vl[engine]; 5766 rcu_read_unlock(); 5767 5768 return vl; 5769 } 5770 5771 /* 5772 * Translate the send context (sofware index) into a VL. Return -1 if the 5773 * translation cannot be done. 5774 */ 5775 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index) 5776 { 5777 struct send_context_info *sci; 5778 struct send_context *sc; 5779 int i; 5780 5781 sci = &dd->send_contexts[sw_index]; 5782 5783 /* there is no information for user (PSM) and ack contexts */ 5784 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15)) 5785 return -1; 5786 5787 sc = sci->sc; 5788 if (!sc) 5789 return -1; 5790 if (dd->vld[15].sc == sc) 5791 return 15; 5792 for (i = 0; i < num_vls; i++) 5793 if (dd->vld[i].sc == sc) 5794 return i; 5795 5796 return -1; 5797 } 5798 5799 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5800 { 5801 u64 reg_copy = reg, handled = 0; 5802 char buf[96]; 5803 int i = 0; 5804 5805 if (reg & ALL_TXE_EGRESS_FREEZE_ERR) 5806 start_freeze_handling(dd->pport, 0); 5807 else if (is_ax(dd) && 5808 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) && 5809 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) 5810 start_freeze_handling(dd->pport, 0); 5811 5812 while (reg_copy) { 5813 int posn = fls64(reg_copy); 5814 /* fls64() returns a 1-based offset, we want it zero based */ 5815 int shift = posn - 1; 5816 u64 mask = 1ULL << shift; 5817 5818 if (port_inactive_err(shift)) { 5819 count_port_inactive(dd); 5820 handled |= mask; 5821 } else if (disallowed_pkt_err(shift)) { 5822 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift)); 5823 5824 handle_send_egress_err_info(dd, vl); 5825 handled |= mask; 5826 } 5827 reg_copy &= ~mask; 5828 } 5829 5830 reg &= ~handled; 5831 5832 if (reg) 5833 dd_dev_info(dd, "Egress Error: %s\n", 5834 egress_err_status_string(buf, sizeof(buf), reg)); 5835 5836 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) { 5837 if (reg & (1ull << i)) 5838 incr_cntr64(&dd->send_egress_err_status_cnt[i]); 5839 } 5840 } 5841 5842 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5843 { 5844 char buf[96]; 5845 int i = 0; 5846 5847 dd_dev_info(dd, "Send Error: %s\n", 5848 send_err_status_string(buf, sizeof(buf), reg)); 5849 5850 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) { 5851 if (reg & (1ull << i)) 5852 incr_cntr64(&dd->send_err_status_cnt[i]); 5853 } 5854 } 5855 5856 /* 5857 * The maximum number of times the error clear down will loop before 5858 * blocking a repeating error. This value is arbitrary. 5859 */ 5860 #define MAX_CLEAR_COUNT 20 5861 5862 /* 5863 * Clear and handle an error register. All error interrupts are funneled 5864 * through here to have a central location to correctly handle single- 5865 * or multi-shot errors. 5866 * 5867 * For non per-context registers, call this routine with a context value 5868 * of 0 so the per-context offset is zero. 5869 * 5870 * If the handler loops too many times, assume that something is wrong 5871 * and can't be fixed, so mask the error bits. 5872 */ 5873 static void interrupt_clear_down(struct hfi1_devdata *dd, 5874 u32 context, 5875 const struct err_reg_info *eri) 5876 { 5877 u64 reg; 5878 u32 count; 5879 5880 /* read in a loop until no more errors are seen */ 5881 count = 0; 5882 while (1) { 5883 reg = read_kctxt_csr(dd, context, eri->status); 5884 if (reg == 0) 5885 break; 5886 write_kctxt_csr(dd, context, eri->clear, reg); 5887 if (likely(eri->handler)) 5888 eri->handler(dd, context, reg); 5889 count++; 5890 if (count > MAX_CLEAR_COUNT) { 5891 u64 mask; 5892 5893 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n", 5894 eri->desc, reg); 5895 /* 5896 * Read-modify-write so any other masked bits 5897 * remain masked. 5898 */ 5899 mask = read_kctxt_csr(dd, context, eri->mask); 5900 mask &= ~reg; 5901 write_kctxt_csr(dd, context, eri->mask, mask); 5902 break; 5903 } 5904 } 5905 } 5906 5907 /* 5908 * CCE block "misc" interrupt. Source is < 16. 5909 */ 5910 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source) 5911 { 5912 const struct err_reg_info *eri = &misc_errs[source]; 5913 5914 if (eri->handler) { 5915 interrupt_clear_down(dd, 0, eri); 5916 } else { 5917 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n", 5918 source); 5919 } 5920 } 5921 5922 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags) 5923 { 5924 return flag_string(buf, buf_len, flags, 5925 sc_err_status_flags, 5926 ARRAY_SIZE(sc_err_status_flags)); 5927 } 5928 5929 /* 5930 * Send context error interrupt. Source (hw_context) is < 160. 5931 * 5932 * All send context errors cause the send context to halt. The normal 5933 * clear-down mechanism cannot be used because we cannot clear the 5934 * error bits until several other long-running items are done first. 5935 * This is OK because with the context halted, nothing else is going 5936 * to happen on it anyway. 5937 */ 5938 static void is_sendctxt_err_int(struct hfi1_devdata *dd, 5939 unsigned int hw_context) 5940 { 5941 struct send_context_info *sci; 5942 struct send_context *sc; 5943 char flags[96]; 5944 u64 status; 5945 u32 sw_index; 5946 int i = 0; 5947 unsigned long irq_flags; 5948 5949 sw_index = dd->hw_to_sw[hw_context]; 5950 if (sw_index >= dd->num_send_contexts) { 5951 dd_dev_err(dd, 5952 "out of range sw index %u for send context %u\n", 5953 sw_index, hw_context); 5954 return; 5955 } 5956 sci = &dd->send_contexts[sw_index]; 5957 spin_lock_irqsave(&dd->sc_lock, irq_flags); 5958 sc = sci->sc; 5959 if (!sc) { 5960 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__, 5961 sw_index, hw_context); 5962 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 5963 return; 5964 } 5965 5966 /* tell the software that a halt has begun */ 5967 sc_stop(sc, SCF_HALTED); 5968 5969 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS); 5970 5971 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context, 5972 send_context_err_status_string(flags, sizeof(flags), 5973 status)); 5974 5975 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK) 5976 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index)); 5977 5978 /* 5979 * Automatically restart halted kernel contexts out of interrupt 5980 * context. User contexts must ask the driver to restart the context. 5981 */ 5982 if (sc->type != SC_USER) 5983 queue_work(dd->pport->hfi1_wq, &sc->halt_work); 5984 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 5985 5986 /* 5987 * Update the counters for the corresponding status bits. 5988 * Note that these particular counters are aggregated over all 5989 * 160 contexts. 5990 */ 5991 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) { 5992 if (status & (1ull << i)) 5993 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]); 5994 } 5995 } 5996 5997 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 5998 unsigned int source, u64 status) 5999 { 6000 struct sdma_engine *sde; 6001 int i = 0; 6002 6003 sde = &dd->per_sdma[source]; 6004 #ifdef CONFIG_SDMA_VERBOSITY 6005 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6006 slashstrip(__FILE__), __LINE__, __func__); 6007 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n", 6008 sde->this_idx, source, (unsigned long long)status); 6009 #endif 6010 sde->err_cnt++; 6011 sdma_engine_error(sde, status); 6012 6013 /* 6014 * Update the counters for the corresponding status bits. 6015 * Note that these particular counters are aggregated over 6016 * all 16 DMA engines. 6017 */ 6018 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) { 6019 if (status & (1ull << i)) 6020 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]); 6021 } 6022 } 6023 6024 /* 6025 * CCE block SDMA error interrupt. Source is < 16. 6026 */ 6027 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source) 6028 { 6029 #ifdef CONFIG_SDMA_VERBOSITY 6030 struct sdma_engine *sde = &dd->per_sdma[source]; 6031 6032 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6033 slashstrip(__FILE__), __LINE__, __func__); 6034 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx, 6035 source); 6036 sdma_dumpstate(sde); 6037 #endif 6038 interrupt_clear_down(dd, source, &sdma_eng_err); 6039 } 6040 6041 /* 6042 * CCE block "various" interrupt. Source is < 8. 6043 */ 6044 static void is_various_int(struct hfi1_devdata *dd, unsigned int source) 6045 { 6046 const struct err_reg_info *eri = &various_err[source]; 6047 6048 /* 6049 * TCritInt cannot go through interrupt_clear_down() 6050 * because it is not a second tier interrupt. The handler 6051 * should be called directly. 6052 */ 6053 if (source == TCRIT_INT_SOURCE) 6054 handle_temp_err(dd); 6055 else if (eri->handler) 6056 interrupt_clear_down(dd, 0, eri); 6057 else 6058 dd_dev_info(dd, 6059 "%s: Unimplemented/reserved interrupt %d\n", 6060 __func__, source); 6061 } 6062 6063 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg) 6064 { 6065 /* src_ctx is always zero */ 6066 struct hfi1_pportdata *ppd = dd->pport; 6067 unsigned long flags; 6068 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 6069 6070 if (reg & QSFP_HFI0_MODPRST_N) { 6071 if (!qsfp_mod_present(ppd)) { 6072 dd_dev_info(dd, "%s: QSFP module removed\n", 6073 __func__); 6074 6075 ppd->driver_link_ready = 0; 6076 /* 6077 * Cable removed, reset all our information about the 6078 * cache and cable capabilities 6079 */ 6080 6081 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6082 /* 6083 * We don't set cache_refresh_required here as we expect 6084 * an interrupt when a cable is inserted 6085 */ 6086 ppd->qsfp_info.cache_valid = 0; 6087 ppd->qsfp_info.reset_needed = 0; 6088 ppd->qsfp_info.limiting_active = 0; 6089 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6090 flags); 6091 /* Invert the ModPresent pin now to detect plug-in */ 6092 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6093 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6094 6095 if ((ppd->offline_disabled_reason > 6096 HFI1_ODR_MASK( 6097 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) || 6098 (ppd->offline_disabled_reason == 6099 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))) 6100 ppd->offline_disabled_reason = 6101 HFI1_ODR_MASK( 6102 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED); 6103 6104 if (ppd->host_link_state == HLS_DN_POLL) { 6105 /* 6106 * The link is still in POLL. This means 6107 * that the normal link down processing 6108 * will not happen. We have to do it here 6109 * before turning the DC off. 6110 */ 6111 queue_work(ppd->link_wq, &ppd->link_down_work); 6112 } 6113 } else { 6114 dd_dev_info(dd, "%s: QSFP module inserted\n", 6115 __func__); 6116 6117 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6118 ppd->qsfp_info.cache_valid = 0; 6119 ppd->qsfp_info.cache_refresh_required = 1; 6120 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6121 flags); 6122 6123 /* 6124 * Stop inversion of ModPresent pin to detect 6125 * removal of the cable 6126 */ 6127 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N; 6128 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6129 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6130 6131 ppd->offline_disabled_reason = 6132 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 6133 } 6134 } 6135 6136 if (reg & QSFP_HFI0_INT_N) { 6137 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n", 6138 __func__); 6139 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6140 ppd->qsfp_info.check_interrupt_flags = 1; 6141 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags); 6142 } 6143 6144 /* Schedule the QSFP work only if there is a cable attached. */ 6145 if (qsfp_mod_present(ppd)) 6146 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work); 6147 } 6148 6149 static int request_host_lcb_access(struct hfi1_devdata *dd) 6150 { 6151 int ret; 6152 6153 ret = do_8051_command(dd, HCMD_MISC, 6154 (u64)HCMD_MISC_REQUEST_LCB_ACCESS << 6155 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6156 if (ret != HCMD_SUCCESS) { 6157 dd_dev_err(dd, "%s: command failed with error %d\n", 6158 __func__, ret); 6159 } 6160 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6161 } 6162 6163 static int request_8051_lcb_access(struct hfi1_devdata *dd) 6164 { 6165 int ret; 6166 6167 ret = do_8051_command(dd, HCMD_MISC, 6168 (u64)HCMD_MISC_GRANT_LCB_ACCESS << 6169 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6170 if (ret != HCMD_SUCCESS) { 6171 dd_dev_err(dd, "%s: command failed with error %d\n", 6172 __func__, ret); 6173 } 6174 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6175 } 6176 6177 /* 6178 * Set the LCB selector - allow host access. The DCC selector always 6179 * points to the host. 6180 */ 6181 static inline void set_host_lcb_access(struct hfi1_devdata *dd) 6182 { 6183 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6184 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK | 6185 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK); 6186 } 6187 6188 /* 6189 * Clear the LCB selector - allow 8051 access. The DCC selector always 6190 * points to the host. 6191 */ 6192 static inline void set_8051_lcb_access(struct hfi1_devdata *dd) 6193 { 6194 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6195 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK); 6196 } 6197 6198 /* 6199 * Acquire LCB access from the 8051. If the host already has access, 6200 * just increment a counter. Otherwise, inform the 8051 that the 6201 * host is taking access. 6202 * 6203 * Returns: 6204 * 0 on success 6205 * -EBUSY if the 8051 has control and cannot be disturbed 6206 * -errno if unable to acquire access from the 8051 6207 */ 6208 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6209 { 6210 struct hfi1_pportdata *ppd = dd->pport; 6211 int ret = 0; 6212 6213 /* 6214 * Use the host link state lock so the operation of this routine 6215 * { link state check, selector change, count increment } can occur 6216 * as a unit against a link state change. Otherwise there is a 6217 * race between the state change and the count increment. 6218 */ 6219 if (sleep_ok) { 6220 mutex_lock(&ppd->hls_lock); 6221 } else { 6222 while (!mutex_trylock(&ppd->hls_lock)) 6223 udelay(1); 6224 } 6225 6226 /* this access is valid only when the link is up */ 6227 if (ppd->host_link_state & HLS_DOWN) { 6228 dd_dev_info(dd, "%s: link state %s not up\n", 6229 __func__, link_state_name(ppd->host_link_state)); 6230 ret = -EBUSY; 6231 goto done; 6232 } 6233 6234 if (dd->lcb_access_count == 0) { 6235 ret = request_host_lcb_access(dd); 6236 if (ret) { 6237 dd_dev_err(dd, 6238 "%s: unable to acquire LCB access, err %d\n", 6239 __func__, ret); 6240 goto done; 6241 } 6242 set_host_lcb_access(dd); 6243 } 6244 dd->lcb_access_count++; 6245 done: 6246 mutex_unlock(&ppd->hls_lock); 6247 return ret; 6248 } 6249 6250 /* 6251 * Release LCB access by decrementing the use count. If the count is moving 6252 * from 1 to 0, inform 8051 that it has control back. 6253 * 6254 * Returns: 6255 * 0 on success 6256 * -errno if unable to release access to the 8051 6257 */ 6258 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6259 { 6260 int ret = 0; 6261 6262 /* 6263 * Use the host link state lock because the acquire needed it. 6264 * Here, we only need to keep { selector change, count decrement } 6265 * as a unit. 6266 */ 6267 if (sleep_ok) { 6268 mutex_lock(&dd->pport->hls_lock); 6269 } else { 6270 while (!mutex_trylock(&dd->pport->hls_lock)) 6271 udelay(1); 6272 } 6273 6274 if (dd->lcb_access_count == 0) { 6275 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n", 6276 __func__); 6277 goto done; 6278 } 6279 6280 if (dd->lcb_access_count == 1) { 6281 set_8051_lcb_access(dd); 6282 ret = request_8051_lcb_access(dd); 6283 if (ret) { 6284 dd_dev_err(dd, 6285 "%s: unable to release LCB access, err %d\n", 6286 __func__, ret); 6287 /* restore host access if the grant didn't work */ 6288 set_host_lcb_access(dd); 6289 goto done; 6290 } 6291 } 6292 dd->lcb_access_count--; 6293 done: 6294 mutex_unlock(&dd->pport->hls_lock); 6295 return ret; 6296 } 6297 6298 /* 6299 * Initialize LCB access variables and state. Called during driver load, 6300 * after most of the initialization is finished. 6301 * 6302 * The DC default is LCB access on for the host. The driver defaults to 6303 * leaving access to the 8051. Assign access now - this constrains the call 6304 * to this routine to be after all LCB set-up is done. In particular, after 6305 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts() 6306 */ 6307 static void init_lcb_access(struct hfi1_devdata *dd) 6308 { 6309 dd->lcb_access_count = 0; 6310 } 6311 6312 /* 6313 * Write a response back to a 8051 request. 6314 */ 6315 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data) 6316 { 6317 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 6318 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK | 6319 (u64)return_code << 6320 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT | 6321 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 6322 } 6323 6324 /* 6325 * Handle host requests from the 8051. 6326 */ 6327 static void handle_8051_request(struct hfi1_pportdata *ppd) 6328 { 6329 struct hfi1_devdata *dd = ppd->dd; 6330 u64 reg; 6331 u16 data = 0; 6332 u8 type; 6333 6334 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); 6335 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0) 6336 return; /* no request */ 6337 6338 /* zero out COMPLETED so the response is seen */ 6339 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); 6340 6341 /* extract request details */ 6342 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT) 6343 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK; 6344 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT) 6345 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK; 6346 6347 switch (type) { 6348 case HREQ_LOAD_CONFIG: 6349 case HREQ_SAVE_CONFIG: 6350 case HREQ_READ_CONFIG: 6351 case HREQ_SET_TX_EQ_ABS: 6352 case HREQ_SET_TX_EQ_REL: 6353 case HREQ_ENABLE: 6354 dd_dev_info(dd, "8051 request: request 0x%x not supported\n", 6355 type); 6356 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6357 break; 6358 case HREQ_CONFIG_DONE: 6359 hreq_response(dd, HREQ_SUCCESS, 0); 6360 break; 6361 6362 case HREQ_INTERFACE_TEST: 6363 hreq_response(dd, HREQ_SUCCESS, data); 6364 break; 6365 default: 6366 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type); 6367 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6368 break; 6369 } 6370 } 6371 6372 /* 6373 * Set up allocation unit vaulue. 6374 */ 6375 void set_up_vau(struct hfi1_devdata *dd, u8 vau) 6376 { 6377 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6378 6379 /* do not modify other values in the register */ 6380 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK; 6381 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT; 6382 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6383 } 6384 6385 /* 6386 * Set up initial VL15 credits of the remote. Assumes the rest of 6387 * the CM credit registers are zero from a previous global or credit reset. 6388 * Shared limit for VL15 will always be 0. 6389 */ 6390 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf) 6391 { 6392 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6393 6394 /* set initial values for total and shared credit limit */ 6395 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK | 6396 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK); 6397 6398 /* 6399 * Set total limit to be equal to VL15 credits. 6400 * Leave shared limit at 0. 6401 */ 6402 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 6403 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6404 6405 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf 6406 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); 6407 } 6408 6409 /* 6410 * Zero all credit details from the previous connection and 6411 * reset the CM manager's internal counters. 6412 */ 6413 void reset_link_credits(struct hfi1_devdata *dd) 6414 { 6415 int i; 6416 6417 /* remove all previous VL credit limits */ 6418 for (i = 0; i < TXE_NUM_DATA_VL; i++) 6419 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 6420 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 6421 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); 6422 /* reset the CM block */ 6423 pio_send_control(dd, PSC_CM_RESET); 6424 /* reset cached value */ 6425 dd->vl15buf_cached = 0; 6426 } 6427 6428 /* convert a vCU to a CU */ 6429 static u32 vcu_to_cu(u8 vcu) 6430 { 6431 return 1 << vcu; 6432 } 6433 6434 /* convert a CU to a vCU */ 6435 static u8 cu_to_vcu(u32 cu) 6436 { 6437 return ilog2(cu); 6438 } 6439 6440 /* convert a vAU to an AU */ 6441 static u32 vau_to_au(u8 vau) 6442 { 6443 return 8 * (1 << vau); 6444 } 6445 6446 static void set_linkup_defaults(struct hfi1_pportdata *ppd) 6447 { 6448 ppd->sm_trap_qp = 0x0; 6449 ppd->sa_qp = 0x1; 6450 } 6451 6452 /* 6453 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset. 6454 */ 6455 static void lcb_shutdown(struct hfi1_devdata *dd, int abort) 6456 { 6457 u64 reg; 6458 6459 /* clear lcb run: LCB_CFG_RUN.EN = 0 */ 6460 write_csr(dd, DC_LCB_CFG_RUN, 0); 6461 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */ 6462 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 6463 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT); 6464 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */ 6465 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); 6466 reg = read_csr(dd, DCC_CFG_RESET); 6467 write_csr(dd, DCC_CFG_RESET, reg | 6468 (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) | 6469 (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT)); 6470 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ 6471 if (!abort) { 6472 udelay(1); /* must hold for the longer of 16cclks or 20ns */ 6473 write_csr(dd, DCC_CFG_RESET, reg); 6474 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6475 } 6476 } 6477 6478 /* 6479 * This routine should be called after the link has been transitioned to 6480 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into 6481 * reset). 6482 * 6483 * The expectation is that the caller of this routine would have taken 6484 * care of properly transitioning the link into the correct state. 6485 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6486 * before calling this function. 6487 */ 6488 static void _dc_shutdown(struct hfi1_devdata *dd) 6489 { 6490 lockdep_assert_held(&dd->dc8051_lock); 6491 6492 if (dd->dc_shutdown) 6493 return; 6494 6495 dd->dc_shutdown = 1; 6496 /* Shutdown the LCB */ 6497 lcb_shutdown(dd, 1); 6498 /* 6499 * Going to OFFLINE would have causes the 8051 to put the 6500 * SerDes into reset already. Just need to shut down the 8051, 6501 * itself. 6502 */ 6503 write_csr(dd, DC_DC8051_CFG_RST, 0x1); 6504 } 6505 6506 static void dc_shutdown(struct hfi1_devdata *dd) 6507 { 6508 mutex_lock(&dd->dc8051_lock); 6509 _dc_shutdown(dd); 6510 mutex_unlock(&dd->dc8051_lock); 6511 } 6512 6513 /* 6514 * Calling this after the DC has been brought out of reset should not 6515 * do any damage. 6516 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6517 * before calling this function. 6518 */ 6519 static void _dc_start(struct hfi1_devdata *dd) 6520 { 6521 lockdep_assert_held(&dd->dc8051_lock); 6522 6523 if (!dd->dc_shutdown) 6524 return; 6525 6526 /* Take the 8051 out of reset */ 6527 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 6528 /* Wait until 8051 is ready */ 6529 if (wait_fm_ready(dd, TIMEOUT_8051_START)) 6530 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n", 6531 __func__); 6532 6533 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */ 6534 write_csr(dd, DCC_CFG_RESET, 0x10); 6535 /* lcb_shutdown() with abort=1 does not restore these */ 6536 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6537 dd->dc_shutdown = 0; 6538 } 6539 6540 static void dc_start(struct hfi1_devdata *dd) 6541 { 6542 mutex_lock(&dd->dc8051_lock); 6543 _dc_start(dd); 6544 mutex_unlock(&dd->dc8051_lock); 6545 } 6546 6547 /* 6548 * These LCB adjustments are for the Aurora SerDes core in the FPGA. 6549 */ 6550 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd) 6551 { 6552 u64 rx_radr, tx_radr; 6553 u32 version; 6554 6555 if (dd->icode != ICODE_FPGA_EMULATION) 6556 return; 6557 6558 /* 6559 * These LCB defaults on emulator _s are good, nothing to do here: 6560 * LCB_CFG_TX_FIFOS_RADR 6561 * LCB_CFG_RX_FIFOS_RADR 6562 * LCB_CFG_LN_DCLK 6563 * LCB_CFG_IGNORE_LOST_RCLK 6564 */ 6565 if (is_emulator_s(dd)) 6566 return; 6567 /* else this is _p */ 6568 6569 version = emulator_rev(dd); 6570 if (!is_ax(dd)) 6571 version = 0x2d; /* all B0 use 0x2d or higher settings */ 6572 6573 if (version <= 0x12) { 6574 /* release 0x12 and below */ 6575 6576 /* 6577 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9 6578 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9 6579 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa 6580 */ 6581 rx_radr = 6582 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6583 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6584 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6585 /* 6586 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default) 6587 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6 6588 */ 6589 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6590 } else if (version <= 0x18) { 6591 /* release 0x13 up to 0x18 */ 6592 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6593 rx_radr = 6594 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6595 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6596 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6597 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6598 } else if (version == 0x19) { 6599 /* release 0x19 */ 6600 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */ 6601 rx_radr = 6602 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6603 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6604 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6605 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6606 } else if (version == 0x1a) { 6607 /* release 0x1a */ 6608 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6609 rx_radr = 6610 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6611 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6612 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6613 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6614 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); 6615 } else { 6616 /* release 0x1b and higher */ 6617 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */ 6618 rx_radr = 6619 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6620 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6621 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6622 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6623 } 6624 6625 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); 6626 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */ 6627 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 6628 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 6629 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); 6630 } 6631 6632 /* 6633 * Handle a SMA idle message 6634 * 6635 * This is a work-queue function outside of the interrupt. 6636 */ 6637 void handle_sma_message(struct work_struct *work) 6638 { 6639 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6640 sma_message_work); 6641 struct hfi1_devdata *dd = ppd->dd; 6642 u64 msg; 6643 int ret; 6644 6645 /* 6646 * msg is bytes 1-4 of the 40-bit idle message - the command code 6647 * is stripped off 6648 */ 6649 ret = read_idle_sma(dd, &msg); 6650 if (ret) 6651 return; 6652 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg); 6653 /* 6654 * React to the SMA message. Byte[1] (0 for us) is the command. 6655 */ 6656 switch (msg & 0xff) { 6657 case SMA_IDLE_ARM: 6658 /* 6659 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6660 * State Transitions 6661 * 6662 * Only expected in INIT or ARMED, discard otherwise. 6663 */ 6664 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED)) 6665 ppd->neighbor_normal = 1; 6666 break; 6667 case SMA_IDLE_ACTIVE: 6668 /* 6669 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6670 * State Transitions 6671 * 6672 * Can activate the node. Discard otherwise. 6673 */ 6674 if (ppd->host_link_state == HLS_UP_ARMED && 6675 ppd->is_active_optimize_enabled) { 6676 ppd->neighbor_normal = 1; 6677 ret = set_link_state(ppd, HLS_UP_ACTIVE); 6678 if (ret) 6679 dd_dev_err( 6680 dd, 6681 "%s: received Active SMA idle message, couldn't set link to Active\n", 6682 __func__); 6683 } 6684 break; 6685 default: 6686 dd_dev_err(dd, 6687 "%s: received unexpected SMA idle message 0x%llx\n", 6688 __func__, msg); 6689 break; 6690 } 6691 } 6692 6693 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear) 6694 { 6695 u64 rcvctrl; 6696 unsigned long flags; 6697 6698 spin_lock_irqsave(&dd->rcvctrl_lock, flags); 6699 rcvctrl = read_csr(dd, RCV_CTRL); 6700 rcvctrl |= add; 6701 rcvctrl &= ~clear; 6702 write_csr(dd, RCV_CTRL, rcvctrl); 6703 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags); 6704 } 6705 6706 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add) 6707 { 6708 adjust_rcvctrl(dd, add, 0); 6709 } 6710 6711 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear) 6712 { 6713 adjust_rcvctrl(dd, 0, clear); 6714 } 6715 6716 /* 6717 * Called from all interrupt handlers to start handling an SPC freeze. 6718 */ 6719 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags) 6720 { 6721 struct hfi1_devdata *dd = ppd->dd; 6722 struct send_context *sc; 6723 int i; 6724 6725 if (flags & FREEZE_SELF) 6726 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6727 6728 /* enter frozen mode */ 6729 dd->flags |= HFI1_FROZEN; 6730 6731 /* notify all SDMA engines that they are going into a freeze */ 6732 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN)); 6733 6734 /* do halt pre-handling on all enabled send contexts */ 6735 for (i = 0; i < dd->num_send_contexts; i++) { 6736 sc = dd->send_contexts[i].sc; 6737 if (sc && (sc->flags & SCF_ENABLED)) 6738 sc_stop(sc, SCF_FROZEN | SCF_HALTED); 6739 } 6740 6741 /* Send context are frozen. Notify user space */ 6742 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT); 6743 6744 if (flags & FREEZE_ABORT) { 6745 dd_dev_err(dd, 6746 "Aborted freeze recovery. Please REBOOT system\n"); 6747 return; 6748 } 6749 /* queue non-interrupt handler */ 6750 queue_work(ppd->hfi1_wq, &ppd->freeze_work); 6751 } 6752 6753 /* 6754 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen, 6755 * depending on the "freeze" parameter. 6756 * 6757 * No need to return an error if it times out, our only option 6758 * is to proceed anyway. 6759 */ 6760 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze) 6761 { 6762 unsigned long timeout; 6763 u64 reg; 6764 6765 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT); 6766 while (1) { 6767 reg = read_csr(dd, CCE_STATUS); 6768 if (freeze) { 6769 /* waiting until all indicators are set */ 6770 if ((reg & ALL_FROZE) == ALL_FROZE) 6771 return; /* all done */ 6772 } else { 6773 /* waiting until all indicators are clear */ 6774 if ((reg & ALL_FROZE) == 0) 6775 return; /* all done */ 6776 } 6777 6778 if (time_after(jiffies, timeout)) { 6779 dd_dev_err(dd, 6780 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing", 6781 freeze ? "" : "un", reg & ALL_FROZE, 6782 freeze ? ALL_FROZE : 0ull); 6783 return; 6784 } 6785 usleep_range(80, 120); 6786 } 6787 } 6788 6789 /* 6790 * Do all freeze handling for the RXE block. 6791 */ 6792 static void rxe_freeze(struct hfi1_devdata *dd) 6793 { 6794 int i; 6795 struct hfi1_ctxtdata *rcd; 6796 6797 /* disable port */ 6798 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6799 6800 /* disable all receive contexts */ 6801 for (i = 0; i < dd->num_rcv_contexts; i++) { 6802 rcd = hfi1_rcd_get_by_index(dd, i); 6803 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd); 6804 hfi1_rcd_put(rcd); 6805 } 6806 } 6807 6808 /* 6809 * Unfreeze handling for the RXE block - kernel contexts only. 6810 * This will also enable the port. User contexts will do unfreeze 6811 * handling on a per-context basis as they call into the driver. 6812 * 6813 */ 6814 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd) 6815 { 6816 u32 rcvmask; 6817 u16 i; 6818 struct hfi1_ctxtdata *rcd; 6819 6820 /* enable all kernel contexts */ 6821 for (i = 0; i < dd->num_rcv_contexts; i++) { 6822 rcd = hfi1_rcd_get_by_index(dd, i); 6823 6824 /* Ensure all non-user contexts(including vnic) are enabled */ 6825 if (!rcd || 6826 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) { 6827 hfi1_rcd_put(rcd); 6828 continue; 6829 } 6830 rcvmask = HFI1_RCVCTRL_CTXT_ENB; 6831 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */ 6832 rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ? 6833 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 6834 hfi1_rcvctrl(dd, rcvmask, rcd); 6835 hfi1_rcd_put(rcd); 6836 } 6837 6838 /* enable port */ 6839 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6840 } 6841 6842 /* 6843 * Non-interrupt SPC freeze handling. 6844 * 6845 * This is a work-queue function outside of the triggering interrupt. 6846 */ 6847 void handle_freeze(struct work_struct *work) 6848 { 6849 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6850 freeze_work); 6851 struct hfi1_devdata *dd = ppd->dd; 6852 6853 /* wait for freeze indicators on all affected blocks */ 6854 wait_for_freeze_status(dd, 1); 6855 6856 /* SPC is now frozen */ 6857 6858 /* do send PIO freeze steps */ 6859 pio_freeze(dd); 6860 6861 /* do send DMA freeze steps */ 6862 sdma_freeze(dd); 6863 6864 /* do send egress freeze steps - nothing to do */ 6865 6866 /* do receive freeze steps */ 6867 rxe_freeze(dd); 6868 6869 /* 6870 * Unfreeze the hardware - clear the freeze, wait for each 6871 * block's frozen bit to clear, then clear the frozen flag. 6872 */ 6873 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6874 wait_for_freeze_status(dd, 0); 6875 6876 if (is_ax(dd)) { 6877 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6878 wait_for_freeze_status(dd, 1); 6879 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6880 wait_for_freeze_status(dd, 0); 6881 } 6882 6883 /* do send PIO unfreeze steps for kernel contexts */ 6884 pio_kernel_unfreeze(dd); 6885 6886 /* do send DMA unfreeze steps */ 6887 sdma_unfreeze(dd); 6888 6889 /* do send egress unfreeze steps - nothing to do */ 6890 6891 /* do receive unfreeze steps for kernel contexts */ 6892 rxe_kernel_unfreeze(dd); 6893 6894 /* 6895 * The unfreeze procedure touches global device registers when 6896 * it disables and re-enables RXE. Mark the device unfrozen 6897 * after all that is done so other parts of the driver waiting 6898 * for the device to unfreeze don't do things out of order. 6899 * 6900 * The above implies that the meaning of HFI1_FROZEN flag is 6901 * "Device has gone into freeze mode and freeze mode handling 6902 * is still in progress." 6903 * 6904 * The flag will be removed when freeze mode processing has 6905 * completed. 6906 */ 6907 dd->flags &= ~HFI1_FROZEN; 6908 wake_up(&dd->event_queue); 6909 6910 /* no longer frozen */ 6911 } 6912 6913 /** 6914 * update_xmit_counters - update PortXmitWait/PortVlXmitWait 6915 * counters. 6916 * @ppd: info of physical Hfi port 6917 * @link_width: new link width after link up or downgrade 6918 * 6919 * Update the PortXmitWait and PortVlXmitWait counters after 6920 * a link up or downgrade event to reflect a link width change. 6921 */ 6922 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width) 6923 { 6924 int i; 6925 u16 tx_width; 6926 u16 link_speed; 6927 6928 tx_width = tx_link_width(link_width); 6929 link_speed = get_link_speed(ppd->link_speed_active); 6930 6931 /* 6932 * There are C_VL_COUNT number of PortVLXmitWait counters. 6933 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter. 6934 */ 6935 for (i = 0; i < C_VL_COUNT + 1; i++) 6936 get_xmit_wait_counters(ppd, tx_width, link_speed, i); 6937 } 6938 6939 /* 6940 * Handle a link up interrupt from the 8051. 6941 * 6942 * This is a work-queue function outside of the interrupt. 6943 */ 6944 void handle_link_up(struct work_struct *work) 6945 { 6946 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6947 link_up_work); 6948 struct hfi1_devdata *dd = ppd->dd; 6949 6950 set_link_state(ppd, HLS_UP_INIT); 6951 6952 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */ 6953 read_ltp_rtt(dd); 6954 /* 6955 * OPA specifies that certain counters are cleared on a transition 6956 * to link up, so do that. 6957 */ 6958 clear_linkup_counters(dd); 6959 /* 6960 * And (re)set link up default values. 6961 */ 6962 set_linkup_defaults(ppd); 6963 6964 /* 6965 * Set VL15 credits. Use cached value from verify cap interrupt. 6966 * In case of quick linkup or simulator, vl15 value will be set by 6967 * handle_linkup_change. VerifyCap interrupt handler will not be 6968 * called in those scenarios. 6969 */ 6970 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) 6971 set_up_vl15(dd, dd->vl15buf_cached); 6972 6973 /* enforce link speed enabled */ 6974 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) { 6975 /* oops - current speed is not enabled, bounce */ 6976 dd_dev_err(dd, 6977 "Link speed active 0x%x is outside enabled 0x%x, downing link\n", 6978 ppd->link_speed_active, ppd->link_speed_enabled); 6979 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0, 6980 OPA_LINKDOWN_REASON_SPEED_POLICY); 6981 set_link_state(ppd, HLS_DN_OFFLINE); 6982 start_link(ppd); 6983 } 6984 } 6985 6986 /* 6987 * Several pieces of LNI information were cached for SMA in ppd. 6988 * Reset these on link down 6989 */ 6990 static void reset_neighbor_info(struct hfi1_pportdata *ppd) 6991 { 6992 ppd->neighbor_guid = 0; 6993 ppd->neighbor_port_number = 0; 6994 ppd->neighbor_type = 0; 6995 ppd->neighbor_fm_security = 0; 6996 } 6997 6998 static const char * const link_down_reason_strs[] = { 6999 [OPA_LINKDOWN_REASON_NONE] = "None", 7000 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0", 7001 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length", 7002 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long", 7003 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short", 7004 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID", 7005 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID", 7006 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2", 7007 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC", 7008 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8", 7009 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail", 7010 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10", 7011 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error", 7012 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15", 7013 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker", 7014 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14", 7015 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15", 7016 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance", 7017 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance", 7018 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance", 7019 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack", 7020 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker", 7021 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt", 7022 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit", 7023 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit", 7024 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24", 7025 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25", 7026 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26", 7027 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27", 7028 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28", 7029 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29", 7030 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30", 7031 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] = 7032 "Excessive buffer overrun", 7033 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown", 7034 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot", 7035 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown", 7036 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce", 7037 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy", 7038 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy", 7039 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected", 7040 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] = 7041 "Local media not installed", 7042 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed", 7043 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config", 7044 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] = 7045 "End to end not installed", 7046 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy", 7047 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy", 7048 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy", 7049 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management", 7050 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled", 7051 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient" 7052 }; 7053 7054 /* return the neighbor link down reason string */ 7055 static const char *link_down_reason_str(u8 reason) 7056 { 7057 const char *str = NULL; 7058 7059 if (reason < ARRAY_SIZE(link_down_reason_strs)) 7060 str = link_down_reason_strs[reason]; 7061 if (!str) 7062 str = "(invalid)"; 7063 7064 return str; 7065 } 7066 7067 /* 7068 * Handle a link down interrupt from the 8051. 7069 * 7070 * This is a work-queue function outside of the interrupt. 7071 */ 7072 void handle_link_down(struct work_struct *work) 7073 { 7074 u8 lcl_reason, neigh_reason = 0; 7075 u8 link_down_reason; 7076 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7077 link_down_work); 7078 int was_up; 7079 static const char ldr_str[] = "Link down reason: "; 7080 7081 if ((ppd->host_link_state & 7082 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) && 7083 ppd->port_type == PORT_TYPE_FIXED) 7084 ppd->offline_disabled_reason = 7085 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED); 7086 7087 /* Go offline first, then deal with reading/writing through 8051 */ 7088 was_up = !!(ppd->host_link_state & HLS_UP); 7089 set_link_state(ppd, HLS_DN_OFFLINE); 7090 xchg(&ppd->is_link_down_queued, 0); 7091 7092 if (was_up) { 7093 lcl_reason = 0; 7094 /* link down reason is only valid if the link was up */ 7095 read_link_down_reason(ppd->dd, &link_down_reason); 7096 switch (link_down_reason) { 7097 case LDR_LINK_TRANSFER_ACTIVE_LOW: 7098 /* the link went down, no idle message reason */ 7099 dd_dev_info(ppd->dd, "%sUnexpected link down\n", 7100 ldr_str); 7101 break; 7102 case LDR_RECEIVED_LINKDOWN_IDLE_MSG: 7103 /* 7104 * The neighbor reason is only valid if an idle message 7105 * was received for it. 7106 */ 7107 read_planned_down_reason_code(ppd->dd, &neigh_reason); 7108 dd_dev_info(ppd->dd, 7109 "%sNeighbor link down message %d, %s\n", 7110 ldr_str, neigh_reason, 7111 link_down_reason_str(neigh_reason)); 7112 break; 7113 case LDR_RECEIVED_HOST_OFFLINE_REQ: 7114 dd_dev_info(ppd->dd, 7115 "%sHost requested link to go offline\n", 7116 ldr_str); 7117 break; 7118 default: 7119 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n", 7120 ldr_str, link_down_reason); 7121 break; 7122 } 7123 7124 /* 7125 * If no reason, assume peer-initiated but missed 7126 * LinkGoingDown idle flits. 7127 */ 7128 if (neigh_reason == 0) 7129 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN; 7130 } else { 7131 /* went down while polling or going up */ 7132 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT; 7133 } 7134 7135 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0); 7136 7137 /* inform the SMA when the link transitions from up to down */ 7138 if (was_up && ppd->local_link_down_reason.sma == 0 && 7139 ppd->neigh_link_down_reason.sma == 0) { 7140 ppd->local_link_down_reason.sma = 7141 ppd->local_link_down_reason.latest; 7142 ppd->neigh_link_down_reason.sma = 7143 ppd->neigh_link_down_reason.latest; 7144 } 7145 7146 reset_neighbor_info(ppd); 7147 7148 /* disable the port */ 7149 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 7150 7151 /* 7152 * If there is no cable attached, turn the DC off. Otherwise, 7153 * start the link bring up. 7154 */ 7155 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) 7156 dc_shutdown(ppd->dd); 7157 else 7158 start_link(ppd); 7159 } 7160 7161 void handle_link_bounce(struct work_struct *work) 7162 { 7163 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7164 link_bounce_work); 7165 7166 /* 7167 * Only do something if the link is currently up. 7168 */ 7169 if (ppd->host_link_state & HLS_UP) { 7170 set_link_state(ppd, HLS_DN_OFFLINE); 7171 start_link(ppd); 7172 } else { 7173 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n", 7174 __func__, link_state_name(ppd->host_link_state)); 7175 } 7176 } 7177 7178 /* 7179 * Mask conversion: Capability exchange to Port LTP. The capability 7180 * exchange has an implicit 16b CRC that is mandatory. 7181 */ 7182 static int cap_to_port_ltp(int cap) 7183 { 7184 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */ 7185 7186 if (cap & CAP_CRC_14B) 7187 port_ltp |= PORT_LTP_CRC_MODE_14; 7188 if (cap & CAP_CRC_48B) 7189 port_ltp |= PORT_LTP_CRC_MODE_48; 7190 if (cap & CAP_CRC_12B_16B_PER_LANE) 7191 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE; 7192 7193 return port_ltp; 7194 } 7195 7196 /* 7197 * Convert an OPA Port LTP mask to capability mask 7198 */ 7199 int port_ltp_to_cap(int port_ltp) 7200 { 7201 int cap_mask = 0; 7202 7203 if (port_ltp & PORT_LTP_CRC_MODE_14) 7204 cap_mask |= CAP_CRC_14B; 7205 if (port_ltp & PORT_LTP_CRC_MODE_48) 7206 cap_mask |= CAP_CRC_48B; 7207 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE) 7208 cap_mask |= CAP_CRC_12B_16B_PER_LANE; 7209 7210 return cap_mask; 7211 } 7212 7213 /* 7214 * Convert a single DC LCB CRC mode to an OPA Port LTP mask. 7215 */ 7216 static int lcb_to_port_ltp(int lcb_crc) 7217 { 7218 int port_ltp = 0; 7219 7220 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE) 7221 port_ltp = PORT_LTP_CRC_MODE_PER_LANE; 7222 else if (lcb_crc == LCB_CRC_48B) 7223 port_ltp = PORT_LTP_CRC_MODE_48; 7224 else if (lcb_crc == LCB_CRC_14B) 7225 port_ltp = PORT_LTP_CRC_MODE_14; 7226 else 7227 port_ltp = PORT_LTP_CRC_MODE_16; 7228 7229 return port_ltp; 7230 } 7231 7232 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd) 7233 { 7234 if (ppd->pkeys[2] != 0) { 7235 ppd->pkeys[2] = 0; 7236 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0); 7237 hfi1_event_pkey_change(ppd->dd, ppd->port); 7238 } 7239 } 7240 7241 /* 7242 * Convert the given link width to the OPA link width bitmask. 7243 */ 7244 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width) 7245 { 7246 switch (width) { 7247 case 0: 7248 /* 7249 * Simulator and quick linkup do not set the width. 7250 * Just set it to 4x without complaint. 7251 */ 7252 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup) 7253 return OPA_LINK_WIDTH_4X; 7254 return 0; /* no lanes up */ 7255 case 1: return OPA_LINK_WIDTH_1X; 7256 case 2: return OPA_LINK_WIDTH_2X; 7257 case 3: return OPA_LINK_WIDTH_3X; 7258 default: 7259 dd_dev_info(dd, "%s: invalid width %d, using 4\n", 7260 __func__, width); 7261 /* fall through */ 7262 case 4: return OPA_LINK_WIDTH_4X; 7263 } 7264 } 7265 7266 /* 7267 * Do a population count on the bottom nibble. 7268 */ 7269 static const u8 bit_counts[16] = { 7270 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 7271 }; 7272 7273 static inline u8 nibble_to_count(u8 nibble) 7274 { 7275 return bit_counts[nibble & 0xf]; 7276 } 7277 7278 /* 7279 * Read the active lane information from the 8051 registers and return 7280 * their widths. 7281 * 7282 * Active lane information is found in these 8051 registers: 7283 * enable_lane_tx 7284 * enable_lane_rx 7285 */ 7286 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width, 7287 u16 *rx_width) 7288 { 7289 u16 tx, rx; 7290 u8 enable_lane_rx; 7291 u8 enable_lane_tx; 7292 u8 tx_polarity_inversion; 7293 u8 rx_polarity_inversion; 7294 u8 max_rate; 7295 7296 /* read the active lanes */ 7297 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 7298 &rx_polarity_inversion, &max_rate); 7299 read_local_lni(dd, &enable_lane_rx); 7300 7301 /* convert to counts */ 7302 tx = nibble_to_count(enable_lane_tx); 7303 rx = nibble_to_count(enable_lane_rx); 7304 7305 /* 7306 * Set link_speed_active here, overriding what was set in 7307 * handle_verify_cap(). The ASIC 8051 firmware does not correctly 7308 * set the max_rate field in handle_verify_cap until v0.19. 7309 */ 7310 if ((dd->icode == ICODE_RTL_SILICON) && 7311 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) { 7312 /* max_rate: 0 = 12.5G, 1 = 25G */ 7313 switch (max_rate) { 7314 case 0: 7315 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G; 7316 break; 7317 default: 7318 dd_dev_err(dd, 7319 "%s: unexpected max rate %d, using 25Gb\n", 7320 __func__, (int)max_rate); 7321 /* fall through */ 7322 case 1: 7323 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G; 7324 break; 7325 } 7326 } 7327 7328 dd_dev_info(dd, 7329 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n", 7330 enable_lane_tx, tx, enable_lane_rx, rx); 7331 *tx_width = link_width_to_bits(dd, tx); 7332 *rx_width = link_width_to_bits(dd, rx); 7333 } 7334 7335 /* 7336 * Read verify_cap_local_fm_link_width[1] to obtain the link widths. 7337 * Valid after the end of VerifyCap and during LinkUp. Does not change 7338 * after link up. I.e. look elsewhere for downgrade information. 7339 * 7340 * Bits are: 7341 * + bits [7:4] contain the number of active transmitters 7342 * + bits [3:0] contain the number of active receivers 7343 * These are numbers 1 through 4 and can be different values if the 7344 * link is asymmetric. 7345 * 7346 * verify_cap_local_fm_link_width[0] retains its original value. 7347 */ 7348 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width, 7349 u16 *rx_width) 7350 { 7351 u16 widths, tx, rx; 7352 u8 misc_bits, local_flags; 7353 u16 active_tx, active_rx; 7354 7355 read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths); 7356 tx = widths >> 12; 7357 rx = (widths >> 8) & 0xf; 7358 7359 *tx_width = link_width_to_bits(dd, tx); 7360 *rx_width = link_width_to_bits(dd, rx); 7361 7362 /* print the active widths */ 7363 get_link_widths(dd, &active_tx, &active_rx); 7364 } 7365 7366 /* 7367 * Set ppd->link_width_active and ppd->link_width_downgrade_active using 7368 * hardware information when the link first comes up. 7369 * 7370 * The link width is not available until after VerifyCap.AllFramesReceived 7371 * (the trigger for handle_verify_cap), so this is outside that routine 7372 * and should be called when the 8051 signals linkup. 7373 */ 7374 void get_linkup_link_widths(struct hfi1_pportdata *ppd) 7375 { 7376 u16 tx_width, rx_width; 7377 7378 /* get end-of-LNI link widths */ 7379 get_linkup_widths(ppd->dd, &tx_width, &rx_width); 7380 7381 /* use tx_width as the link is supposed to be symmetric on link up */ 7382 ppd->link_width_active = tx_width; 7383 /* link width downgrade active (LWD.A) starts out matching LW.A */ 7384 ppd->link_width_downgrade_tx_active = ppd->link_width_active; 7385 ppd->link_width_downgrade_rx_active = ppd->link_width_active; 7386 /* per OPA spec, on link up LWD.E resets to LWD.S */ 7387 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported; 7388 /* cache the active egress rate (units {10^6 bits/sec]) */ 7389 ppd->current_egress_rate = active_egress_rate(ppd); 7390 } 7391 7392 /* 7393 * Handle a verify capabilities interrupt from the 8051. 7394 * 7395 * This is a work-queue function outside of the interrupt. 7396 */ 7397 void handle_verify_cap(struct work_struct *work) 7398 { 7399 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7400 link_vc_work); 7401 struct hfi1_devdata *dd = ppd->dd; 7402 u64 reg; 7403 u8 power_management; 7404 u8 continuous; 7405 u8 vcu; 7406 u8 vau; 7407 u8 z; 7408 u16 vl15buf; 7409 u16 link_widths; 7410 u16 crc_mask; 7411 u16 crc_val; 7412 u16 device_id; 7413 u16 active_tx, active_rx; 7414 u8 partner_supported_crc; 7415 u8 remote_tx_rate; 7416 u8 device_rev; 7417 7418 set_link_state(ppd, HLS_VERIFY_CAP); 7419 7420 lcb_shutdown(dd, 0); 7421 adjust_lcb_for_fpga_serdes(dd); 7422 7423 read_vc_remote_phy(dd, &power_management, &continuous); 7424 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf, 7425 &partner_supported_crc); 7426 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths); 7427 read_remote_device_id(dd, &device_id, &device_rev); 7428 7429 /* print the active widths */ 7430 get_link_widths(dd, &active_tx, &active_rx); 7431 dd_dev_info(dd, 7432 "Peer PHY: power management 0x%x, continuous updates 0x%x\n", 7433 (int)power_management, (int)continuous); 7434 dd_dev_info(dd, 7435 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n", 7436 (int)vau, (int)z, (int)vcu, (int)vl15buf, 7437 (int)partner_supported_crc); 7438 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n", 7439 (u32)remote_tx_rate, (u32)link_widths); 7440 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n", 7441 (u32)device_id, (u32)device_rev); 7442 /* 7443 * The peer vAU value just read is the peer receiver value. HFI does 7444 * not support a transmit vAU of 0 (AU == 8). We advertised that 7445 * with Z=1 in the fabric capabilities sent to the peer. The peer 7446 * will see our Z=1, and, if it advertised a vAU of 0, will move its 7447 * receive to vAU of 1 (AU == 16). Do the same here. We do not care 7448 * about the peer Z value - our sent vAU is 3 (hardwired) and is not 7449 * subject to the Z value exception. 7450 */ 7451 if (vau == 0) 7452 vau = 1; 7453 set_up_vau(dd, vau); 7454 7455 /* 7456 * Set VL15 credits to 0 in global credit register. Cache remote VL15 7457 * credits value and wait for link-up interrupt ot set it. 7458 */ 7459 set_up_vl15(dd, 0); 7460 dd->vl15buf_cached = vl15buf; 7461 7462 /* set up the LCB CRC mode */ 7463 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc; 7464 7465 /* order is important: use the lowest bit in common */ 7466 if (crc_mask & CAP_CRC_14B) 7467 crc_val = LCB_CRC_14B; 7468 else if (crc_mask & CAP_CRC_48B) 7469 crc_val = LCB_CRC_48B; 7470 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE) 7471 crc_val = LCB_CRC_12B_16B_PER_LANE; 7472 else 7473 crc_val = LCB_CRC_16B; 7474 7475 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val); 7476 write_csr(dd, DC_LCB_CFG_CRC_MODE, 7477 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT); 7478 7479 /* set (14b only) or clear sideband credit */ 7480 reg = read_csr(dd, SEND_CM_CTRL); 7481 if (crc_val == LCB_CRC_14B && crc_14b_sideband) { 7482 write_csr(dd, SEND_CM_CTRL, 7483 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7484 } else { 7485 write_csr(dd, SEND_CM_CTRL, 7486 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7487 } 7488 7489 ppd->link_speed_active = 0; /* invalid value */ 7490 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 7491 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */ 7492 switch (remote_tx_rate) { 7493 case 0: 7494 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7495 break; 7496 case 1: 7497 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7498 break; 7499 } 7500 } else { 7501 /* actual rate is highest bit of the ANDed rates */ 7502 u8 rate = remote_tx_rate & ppd->local_tx_rate; 7503 7504 if (rate & 2) 7505 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7506 else if (rate & 1) 7507 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7508 } 7509 if (ppd->link_speed_active == 0) { 7510 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n", 7511 __func__, (int)remote_tx_rate); 7512 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7513 } 7514 7515 /* 7516 * Cache the values of the supported, enabled, and active 7517 * LTP CRC modes to return in 'portinfo' queries. But the bit 7518 * flags that are returned in the portinfo query differ from 7519 * what's in the link_crc_mask, crc_sizes, and crc_val 7520 * variables. Convert these here. 7521 */ 7522 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 7523 /* supported crc modes */ 7524 ppd->port_ltp_crc_mode |= 7525 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4; 7526 /* enabled crc modes */ 7527 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val); 7528 /* active crc mode */ 7529 7530 /* set up the remote credit return table */ 7531 assign_remote_cm_au_table(dd, vcu); 7532 7533 /* 7534 * The LCB is reset on entry to handle_verify_cap(), so this must 7535 * be applied on every link up. 7536 * 7537 * Adjust LCB error kill enable to kill the link if 7538 * these RBUF errors are seen: 7539 * REPLAY_BUF_MBE_SMASK 7540 * FLIT_INPUT_BUF_MBE_SMASK 7541 */ 7542 if (is_ax(dd)) { /* fixed in B0 */ 7543 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); 7544 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 7545 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK; 7546 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); 7547 } 7548 7549 /* pull LCB fifos out of reset - all fifo clocks must be stable */ 7550 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 7551 7552 /* give 8051 access to the LCB CSRs */ 7553 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 7554 set_8051_lcb_access(dd); 7555 7556 /* tell the 8051 to go to LinkUp */ 7557 set_link_state(ppd, HLS_GOING_UP); 7558 } 7559 7560 /** 7561 * apply_link_downgrade_policy - Apply the link width downgrade enabled 7562 * policy against the current active link widths. 7563 * @ppd: info of physical Hfi port 7564 * @refresh_widths: True indicates link downgrade event 7565 * @return: True indicates a successful link downgrade. False indicates 7566 * link downgrade event failed and the link will bounce back to 7567 * default link width. 7568 * 7569 * Called when the enabled policy changes or the active link widths 7570 * change. 7571 * Refresh_widths indicates that a link downgrade occurred. The 7572 * link_downgraded variable is set by refresh_widths and 7573 * determines the success/failure of the policy application. 7574 */ 7575 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, 7576 bool refresh_widths) 7577 { 7578 int do_bounce = 0; 7579 int tries; 7580 u16 lwde; 7581 u16 tx, rx; 7582 bool link_downgraded = refresh_widths; 7583 7584 /* use the hls lock to avoid a race with actual link up */ 7585 tries = 0; 7586 retry: 7587 mutex_lock(&ppd->hls_lock); 7588 /* only apply if the link is up */ 7589 if (ppd->host_link_state & HLS_DOWN) { 7590 /* still going up..wait and retry */ 7591 if (ppd->host_link_state & HLS_GOING_UP) { 7592 if (++tries < 1000) { 7593 mutex_unlock(&ppd->hls_lock); 7594 usleep_range(100, 120); /* arbitrary */ 7595 goto retry; 7596 } 7597 dd_dev_err(ppd->dd, 7598 "%s: giving up waiting for link state change\n", 7599 __func__); 7600 } 7601 goto done; 7602 } 7603 7604 lwde = ppd->link_width_downgrade_enabled; 7605 7606 if (refresh_widths) { 7607 get_link_widths(ppd->dd, &tx, &rx); 7608 ppd->link_width_downgrade_tx_active = tx; 7609 ppd->link_width_downgrade_rx_active = rx; 7610 } 7611 7612 if (ppd->link_width_downgrade_tx_active == 0 || 7613 ppd->link_width_downgrade_rx_active == 0) { 7614 /* the 8051 reported a dead link as a downgrade */ 7615 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n"); 7616 link_downgraded = false; 7617 } else if (lwde == 0) { 7618 /* downgrade is disabled */ 7619 7620 /* bounce if not at starting active width */ 7621 if ((ppd->link_width_active != 7622 ppd->link_width_downgrade_tx_active) || 7623 (ppd->link_width_active != 7624 ppd->link_width_downgrade_rx_active)) { 7625 dd_dev_err(ppd->dd, 7626 "Link downgrade is disabled and link has downgraded, downing link\n"); 7627 dd_dev_err(ppd->dd, 7628 " original 0x%x, tx active 0x%x, rx active 0x%x\n", 7629 ppd->link_width_active, 7630 ppd->link_width_downgrade_tx_active, 7631 ppd->link_width_downgrade_rx_active); 7632 do_bounce = 1; 7633 link_downgraded = false; 7634 } 7635 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 || 7636 (lwde & ppd->link_width_downgrade_rx_active) == 0) { 7637 /* Tx or Rx is outside the enabled policy */ 7638 dd_dev_err(ppd->dd, 7639 "Link is outside of downgrade allowed, downing link\n"); 7640 dd_dev_err(ppd->dd, 7641 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n", 7642 lwde, ppd->link_width_downgrade_tx_active, 7643 ppd->link_width_downgrade_rx_active); 7644 do_bounce = 1; 7645 link_downgraded = false; 7646 } 7647 7648 done: 7649 mutex_unlock(&ppd->hls_lock); 7650 7651 if (do_bounce) { 7652 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0, 7653 OPA_LINKDOWN_REASON_WIDTH_POLICY); 7654 set_link_state(ppd, HLS_DN_OFFLINE); 7655 start_link(ppd); 7656 } 7657 7658 return link_downgraded; 7659 } 7660 7661 /* 7662 * Handle a link downgrade interrupt from the 8051. 7663 * 7664 * This is a work-queue function outside of the interrupt. 7665 */ 7666 void handle_link_downgrade(struct work_struct *work) 7667 { 7668 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7669 link_downgrade_work); 7670 7671 dd_dev_info(ppd->dd, "8051: Link width downgrade\n"); 7672 if (apply_link_downgrade_policy(ppd, true)) 7673 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active); 7674 } 7675 7676 static char *dcc_err_string(char *buf, int buf_len, u64 flags) 7677 { 7678 return flag_string(buf, buf_len, flags, dcc_err_flags, 7679 ARRAY_SIZE(dcc_err_flags)); 7680 } 7681 7682 static char *lcb_err_string(char *buf, int buf_len, u64 flags) 7683 { 7684 return flag_string(buf, buf_len, flags, lcb_err_flags, 7685 ARRAY_SIZE(lcb_err_flags)); 7686 } 7687 7688 static char *dc8051_err_string(char *buf, int buf_len, u64 flags) 7689 { 7690 return flag_string(buf, buf_len, flags, dc8051_err_flags, 7691 ARRAY_SIZE(dc8051_err_flags)); 7692 } 7693 7694 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags) 7695 { 7696 return flag_string(buf, buf_len, flags, dc8051_info_err_flags, 7697 ARRAY_SIZE(dc8051_info_err_flags)); 7698 } 7699 7700 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags) 7701 { 7702 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags, 7703 ARRAY_SIZE(dc8051_info_host_msg_flags)); 7704 } 7705 7706 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg) 7707 { 7708 struct hfi1_pportdata *ppd = dd->pport; 7709 u64 info, err, host_msg; 7710 int queue_link_down = 0; 7711 char buf[96]; 7712 7713 /* look at the flags */ 7714 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) { 7715 /* 8051 information set by firmware */ 7716 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */ 7717 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); 7718 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT) 7719 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK; 7720 host_msg = (info >> 7721 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT) 7722 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK; 7723 7724 /* 7725 * Handle error flags. 7726 */ 7727 if (err & FAILED_LNI) { 7728 /* 7729 * LNI error indications are cleared by the 8051 7730 * only when starting polling. Only pay attention 7731 * to them when in the states that occur during 7732 * LNI. 7733 */ 7734 if (ppd->host_link_state 7735 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 7736 queue_link_down = 1; 7737 dd_dev_info(dd, "Link error: %s\n", 7738 dc8051_info_err_string(buf, 7739 sizeof(buf), 7740 err & 7741 FAILED_LNI)); 7742 } 7743 err &= ~(u64)FAILED_LNI; 7744 } 7745 /* unknown frames can happen durning LNI, just count */ 7746 if (err & UNKNOWN_FRAME) { 7747 ppd->unknown_frame_count++; 7748 err &= ~(u64)UNKNOWN_FRAME; 7749 } 7750 if (err) { 7751 /* report remaining errors, but do not do anything */ 7752 dd_dev_err(dd, "8051 info error: %s\n", 7753 dc8051_info_err_string(buf, sizeof(buf), 7754 err)); 7755 } 7756 7757 /* 7758 * Handle host message flags. 7759 */ 7760 if (host_msg & HOST_REQ_DONE) { 7761 /* 7762 * Presently, the driver does a busy wait for 7763 * host requests to complete. This is only an 7764 * informational message. 7765 * NOTE: The 8051 clears the host message 7766 * information *on the next 8051 command*. 7767 * Therefore, when linkup is achieved, 7768 * this flag will still be set. 7769 */ 7770 host_msg &= ~(u64)HOST_REQ_DONE; 7771 } 7772 if (host_msg & BC_SMA_MSG) { 7773 queue_work(ppd->link_wq, &ppd->sma_message_work); 7774 host_msg &= ~(u64)BC_SMA_MSG; 7775 } 7776 if (host_msg & LINKUP_ACHIEVED) { 7777 dd_dev_info(dd, "8051: Link up\n"); 7778 queue_work(ppd->link_wq, &ppd->link_up_work); 7779 host_msg &= ~(u64)LINKUP_ACHIEVED; 7780 } 7781 if (host_msg & EXT_DEVICE_CFG_REQ) { 7782 handle_8051_request(ppd); 7783 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ; 7784 } 7785 if (host_msg & VERIFY_CAP_FRAME) { 7786 queue_work(ppd->link_wq, &ppd->link_vc_work); 7787 host_msg &= ~(u64)VERIFY_CAP_FRAME; 7788 } 7789 if (host_msg & LINK_GOING_DOWN) { 7790 const char *extra = ""; 7791 /* no downgrade action needed if going down */ 7792 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7793 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7794 extra = " (ignoring downgrade)"; 7795 } 7796 dd_dev_info(dd, "8051: Link down%s\n", extra); 7797 queue_link_down = 1; 7798 host_msg &= ~(u64)LINK_GOING_DOWN; 7799 } 7800 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7801 queue_work(ppd->link_wq, &ppd->link_downgrade_work); 7802 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7803 } 7804 if (host_msg) { 7805 /* report remaining messages, but do not do anything */ 7806 dd_dev_info(dd, "8051 info host message: %s\n", 7807 dc8051_info_host_msg_string(buf, 7808 sizeof(buf), 7809 host_msg)); 7810 } 7811 7812 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK; 7813 } 7814 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) { 7815 /* 7816 * Lost the 8051 heartbeat. If this happens, we 7817 * receive constant interrupts about it. Disable 7818 * the interrupt after the first. 7819 */ 7820 dd_dev_err(dd, "Lost 8051 heartbeat\n"); 7821 write_csr(dd, DC_DC8051_ERR_EN, 7822 read_csr(dd, DC_DC8051_ERR_EN) & 7823 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK); 7824 7825 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK; 7826 } 7827 if (reg) { 7828 /* report the error, but do not do anything */ 7829 dd_dev_err(dd, "8051 error: %s\n", 7830 dc8051_err_string(buf, sizeof(buf), reg)); 7831 } 7832 7833 if (queue_link_down) { 7834 /* 7835 * if the link is already going down or disabled, do not 7836 * queue another. If there's a link down entry already 7837 * queued, don't queue another one. 7838 */ 7839 if ((ppd->host_link_state & 7840 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) || 7841 ppd->link_enabled == 0) { 7842 dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n", 7843 __func__, ppd->host_link_state, 7844 ppd->link_enabled); 7845 } else { 7846 if (xchg(&ppd->is_link_down_queued, 1) == 1) 7847 dd_dev_info(dd, 7848 "%s: link down request already queued\n", 7849 __func__); 7850 else 7851 queue_work(ppd->link_wq, &ppd->link_down_work); 7852 } 7853 } 7854 } 7855 7856 static const char * const fm_config_txt[] = { 7857 [0] = 7858 "BadHeadDist: Distance violation between two head flits", 7859 [1] = 7860 "BadTailDist: Distance violation between two tail flits", 7861 [2] = 7862 "BadCtrlDist: Distance violation between two credit control flits", 7863 [3] = 7864 "BadCrdAck: Credits return for unsupported VL", 7865 [4] = 7866 "UnsupportedVLMarker: Received VL Marker", 7867 [5] = 7868 "BadPreempt: Exceeded the preemption nesting level", 7869 [6] = 7870 "BadControlFlit: Received unsupported control flit", 7871 /* no 7 */ 7872 [8] = 7873 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL", 7874 }; 7875 7876 static const char * const port_rcv_txt[] = { 7877 [1] = 7878 "BadPktLen: Illegal PktLen", 7879 [2] = 7880 "PktLenTooLong: Packet longer than PktLen", 7881 [3] = 7882 "PktLenTooShort: Packet shorter than PktLen", 7883 [4] = 7884 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)", 7885 [5] = 7886 "BadDLID: Illegal DLID (0, doesn't match HFI)", 7887 [6] = 7888 "BadL2: Illegal L2 opcode", 7889 [7] = 7890 "BadSC: Unsupported SC", 7891 [9] = 7892 "BadRC: Illegal RC", 7893 [11] = 7894 "PreemptError: Preempting with same VL", 7895 [12] = 7896 "PreemptVL15: Preempting a VL15 packet", 7897 }; 7898 7899 #define OPA_LDR_FMCONFIG_OFFSET 16 7900 #define OPA_LDR_PORTRCV_OFFSET 0 7901 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 7902 { 7903 u64 info, hdr0, hdr1; 7904 const char *extra; 7905 char buf[96]; 7906 struct hfi1_pportdata *ppd = dd->pport; 7907 u8 lcl_reason = 0; 7908 int do_bounce = 0; 7909 7910 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) { 7911 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) { 7912 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); 7913 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK; 7914 /* set status bit */ 7915 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK; 7916 } 7917 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK; 7918 } 7919 7920 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) { 7921 struct hfi1_pportdata *ppd = dd->pport; 7922 /* this counter saturates at (2^32) - 1 */ 7923 if (ppd->link_downed < (u32)UINT_MAX) 7924 ppd->link_downed++; 7925 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK; 7926 } 7927 7928 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) { 7929 u8 reason_valid = 1; 7930 7931 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); 7932 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) { 7933 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK; 7934 /* set status bit */ 7935 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK; 7936 } 7937 switch (info) { 7938 case 0: 7939 case 1: 7940 case 2: 7941 case 3: 7942 case 4: 7943 case 5: 7944 case 6: 7945 extra = fm_config_txt[info]; 7946 break; 7947 case 8: 7948 extra = fm_config_txt[info]; 7949 if (ppd->port_error_action & 7950 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) { 7951 do_bounce = 1; 7952 /* 7953 * lcl_reason cannot be derived from info 7954 * for this error 7955 */ 7956 lcl_reason = 7957 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER; 7958 } 7959 break; 7960 default: 7961 reason_valid = 0; 7962 snprintf(buf, sizeof(buf), "reserved%lld", info); 7963 extra = buf; 7964 break; 7965 } 7966 7967 if (reason_valid && !do_bounce) { 7968 do_bounce = ppd->port_error_action & 7969 (1 << (OPA_LDR_FMCONFIG_OFFSET + info)); 7970 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST; 7971 } 7972 7973 /* just report this */ 7974 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n", 7975 extra); 7976 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK; 7977 } 7978 7979 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) { 7980 u8 reason_valid = 1; 7981 7982 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); 7983 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); 7984 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); 7985 if (!(dd->err_info_rcvport.status_and_code & 7986 OPA_EI_STATUS_SMASK)) { 7987 dd->err_info_rcvport.status_and_code = 7988 info & OPA_EI_CODE_SMASK; 7989 /* set status bit */ 7990 dd->err_info_rcvport.status_and_code |= 7991 OPA_EI_STATUS_SMASK; 7992 /* 7993 * save first 2 flits in the packet that caused 7994 * the error 7995 */ 7996 dd->err_info_rcvport.packet_flit1 = hdr0; 7997 dd->err_info_rcvport.packet_flit2 = hdr1; 7998 } 7999 switch (info) { 8000 case 1: 8001 case 2: 8002 case 3: 8003 case 4: 8004 case 5: 8005 case 6: 8006 case 7: 8007 case 9: 8008 case 11: 8009 case 12: 8010 extra = port_rcv_txt[info]; 8011 break; 8012 default: 8013 reason_valid = 0; 8014 snprintf(buf, sizeof(buf), "reserved%lld", info); 8015 extra = buf; 8016 break; 8017 } 8018 8019 if (reason_valid && !do_bounce) { 8020 do_bounce = ppd->port_error_action & 8021 (1 << (OPA_LDR_PORTRCV_OFFSET + info)); 8022 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0; 8023 } 8024 8025 /* just report this */ 8026 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n" 8027 " hdr0 0x%llx, hdr1 0x%llx\n", 8028 extra, hdr0, hdr1); 8029 8030 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK; 8031 } 8032 8033 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) { 8034 /* informative only */ 8035 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n"); 8036 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK; 8037 } 8038 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) { 8039 /* informative only */ 8040 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n"); 8041 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK; 8042 } 8043 8044 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev))) 8045 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK; 8046 8047 /* report any remaining errors */ 8048 if (reg) 8049 dd_dev_info_ratelimited(dd, "DCC Error: %s\n", 8050 dcc_err_string(buf, sizeof(buf), reg)); 8051 8052 if (lcl_reason == 0) 8053 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN; 8054 8055 if (do_bounce) { 8056 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n", 8057 __func__); 8058 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason); 8059 queue_work(ppd->link_wq, &ppd->link_bounce_work); 8060 } 8061 } 8062 8063 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 8064 { 8065 char buf[96]; 8066 8067 dd_dev_info(dd, "LCB Error: %s\n", 8068 lcb_err_string(buf, sizeof(buf), reg)); 8069 } 8070 8071 /* 8072 * CCE block DC interrupt. Source is < 8. 8073 */ 8074 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source) 8075 { 8076 const struct err_reg_info *eri = &dc_errs[source]; 8077 8078 if (eri->handler) { 8079 interrupt_clear_down(dd, 0, eri); 8080 } else if (source == 3 /* dc_lbm_int */) { 8081 /* 8082 * This indicates that a parity error has occurred on the 8083 * address/control lines presented to the LBM. The error 8084 * is a single pulse, there is no associated error flag, 8085 * and it is non-maskable. This is because if a parity 8086 * error occurs on the request the request is dropped. 8087 * This should never occur, but it is nice to know if it 8088 * ever does. 8089 */ 8090 dd_dev_err(dd, "Parity error in DC LBM block\n"); 8091 } else { 8092 dd_dev_err(dd, "Invalid DC interrupt %u\n", source); 8093 } 8094 } 8095 8096 /* 8097 * TX block send credit interrupt. Source is < 160. 8098 */ 8099 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source) 8100 { 8101 sc_group_release_update(dd, source); 8102 } 8103 8104 /* 8105 * TX block SDMA interrupt. Source is < 48. 8106 * 8107 * SDMA interrupts are grouped by type: 8108 * 8109 * 0 - N-1 = SDma 8110 * N - 2N-1 = SDmaProgress 8111 * 2N - 3N-1 = SDmaIdle 8112 */ 8113 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source) 8114 { 8115 /* what interrupt */ 8116 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 8117 /* which engine */ 8118 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 8119 8120 #ifdef CONFIG_SDMA_VERBOSITY 8121 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which, 8122 slashstrip(__FILE__), __LINE__, __func__); 8123 sdma_dumpstate(&dd->per_sdma[which]); 8124 #endif 8125 8126 if (likely(what < 3 && which < dd->num_sdma)) { 8127 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source); 8128 } else { 8129 /* should not happen */ 8130 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source); 8131 } 8132 } 8133 8134 /* 8135 * RX block receive available interrupt. Source is < 160. 8136 */ 8137 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source) 8138 { 8139 struct hfi1_ctxtdata *rcd; 8140 char *err_detail; 8141 8142 if (likely(source < dd->num_rcv_contexts)) { 8143 rcd = hfi1_rcd_get_by_index(dd, source); 8144 if (rcd) { 8145 /* Check for non-user contexts, including vnic */ 8146 if (source < dd->first_dyn_alloc_ctxt || rcd->is_vnic) 8147 rcd->do_interrupt(rcd, 0); 8148 else 8149 handle_user_interrupt(rcd); 8150 8151 hfi1_rcd_put(rcd); 8152 return; /* OK */ 8153 } 8154 /* received an interrupt, but no rcd */ 8155 err_detail = "dataless"; 8156 } else { 8157 /* received an interrupt, but are not using that context */ 8158 err_detail = "out of range"; 8159 } 8160 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n", 8161 err_detail, source); 8162 } 8163 8164 /* 8165 * RX block receive urgent interrupt. Source is < 160. 8166 */ 8167 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source) 8168 { 8169 struct hfi1_ctxtdata *rcd; 8170 char *err_detail; 8171 8172 if (likely(source < dd->num_rcv_contexts)) { 8173 rcd = hfi1_rcd_get_by_index(dd, source); 8174 if (rcd) { 8175 /* only pay attention to user urgent interrupts */ 8176 if (source >= dd->first_dyn_alloc_ctxt && 8177 !rcd->is_vnic) 8178 handle_user_interrupt(rcd); 8179 8180 hfi1_rcd_put(rcd); 8181 return; /* OK */ 8182 } 8183 /* received an interrupt, but no rcd */ 8184 err_detail = "dataless"; 8185 } else { 8186 /* received an interrupt, but are not using that context */ 8187 err_detail = "out of range"; 8188 } 8189 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n", 8190 err_detail, source); 8191 } 8192 8193 /* 8194 * Reserved range interrupt. Should not be called in normal operation. 8195 */ 8196 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source) 8197 { 8198 char name[64]; 8199 8200 dd_dev_err(dd, "unexpected %s interrupt\n", 8201 is_reserved_name(name, sizeof(name), source)); 8202 } 8203 8204 static const struct is_table is_table[] = { 8205 /* 8206 * start end 8207 * name func interrupt func 8208 */ 8209 { IS_GENERAL_ERR_START, IS_GENERAL_ERR_END, 8210 is_misc_err_name, is_misc_err_int }, 8211 { IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END, 8212 is_sdma_eng_err_name, is_sdma_eng_err_int }, 8213 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, 8214 is_sendctxt_err_name, is_sendctxt_err_int }, 8215 { IS_SDMA_START, IS_SDMA_END, 8216 is_sdma_eng_name, is_sdma_eng_int }, 8217 { IS_VARIOUS_START, IS_VARIOUS_END, 8218 is_various_name, is_various_int }, 8219 { IS_DC_START, IS_DC_END, 8220 is_dc_name, is_dc_int }, 8221 { IS_RCVAVAIL_START, IS_RCVAVAIL_END, 8222 is_rcv_avail_name, is_rcv_avail_int }, 8223 { IS_RCVURGENT_START, IS_RCVURGENT_END, 8224 is_rcv_urgent_name, is_rcv_urgent_int }, 8225 { IS_SENDCREDIT_START, IS_SENDCREDIT_END, 8226 is_send_credit_name, is_send_credit_int}, 8227 { IS_RESERVED_START, IS_RESERVED_END, 8228 is_reserved_name, is_reserved_int}, 8229 }; 8230 8231 /* 8232 * Interrupt source interrupt - called when the given source has an interrupt. 8233 * Source is a bit index into an array of 64-bit integers. 8234 */ 8235 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source) 8236 { 8237 const struct is_table *entry; 8238 8239 /* avoids a double compare by walking the table in-order */ 8240 for (entry = &is_table[0]; entry->is_name; entry++) { 8241 if (source < entry->end) { 8242 trace_hfi1_interrupt(dd, entry, source); 8243 entry->is_int(dd, source - entry->start); 8244 return; 8245 } 8246 } 8247 /* fell off the end */ 8248 dd_dev_err(dd, "invalid interrupt source %u\n", source); 8249 } 8250 8251 /* 8252 * General interrupt handler. This is able to correctly handle 8253 * all interrupts in case INTx is used. 8254 */ 8255 static irqreturn_t general_interrupt(int irq, void *data) 8256 { 8257 struct hfi1_devdata *dd = data; 8258 u64 regs[CCE_NUM_INT_CSRS]; 8259 u32 bit; 8260 int i; 8261 irqreturn_t handled = IRQ_NONE; 8262 8263 this_cpu_inc(*dd->int_counter); 8264 8265 /* phase 1: scan and clear all handled interrupts */ 8266 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 8267 if (dd->gi_mask[i] == 0) { 8268 regs[i] = 0; /* used later */ 8269 continue; 8270 } 8271 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & 8272 dd->gi_mask[i]; 8273 /* only clear if anything is set */ 8274 if (regs[i]) 8275 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); 8276 } 8277 8278 /* phase 2: call the appropriate handler */ 8279 for_each_set_bit(bit, (unsigned long *)®s[0], 8280 CCE_NUM_INT_CSRS * 64) { 8281 is_interrupt(dd, bit); 8282 handled = IRQ_HANDLED; 8283 } 8284 8285 return handled; 8286 } 8287 8288 static irqreturn_t sdma_interrupt(int irq, void *data) 8289 { 8290 struct sdma_engine *sde = data; 8291 struct hfi1_devdata *dd = sde->dd; 8292 u64 status; 8293 8294 #ifdef CONFIG_SDMA_VERBOSITY 8295 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 8296 slashstrip(__FILE__), __LINE__, __func__); 8297 sdma_dumpstate(sde); 8298 #endif 8299 8300 this_cpu_inc(*dd->int_counter); 8301 8302 /* This read_csr is really bad in the hot path */ 8303 status = read_csr(dd, 8304 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64))) 8305 & sde->imask; 8306 if (likely(status)) { 8307 /* clear the interrupt(s) */ 8308 write_csr(dd, 8309 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)), 8310 status); 8311 8312 /* handle the interrupt(s) */ 8313 sdma_engine_interrupt(sde, status); 8314 } else { 8315 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n", 8316 sde->this_idx); 8317 } 8318 return IRQ_HANDLED; 8319 } 8320 8321 /* 8322 * Clear the receive interrupt. Use a read of the interrupt clear CSR 8323 * to insure that the write completed. This does NOT guarantee that 8324 * queued DMA writes to memory from the chip are pushed. 8325 */ 8326 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd) 8327 { 8328 struct hfi1_devdata *dd = rcd->dd; 8329 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg); 8330 8331 mmiowb(); /* make sure everything before is written */ 8332 write_csr(dd, addr, rcd->imask); 8333 /* force the above write on the chip and get a value back */ 8334 (void)read_csr(dd, addr); 8335 } 8336 8337 /* force the receive interrupt */ 8338 void force_recv_intr(struct hfi1_ctxtdata *rcd) 8339 { 8340 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); 8341 } 8342 8343 /* 8344 * Return non-zero if a packet is present. 8345 * 8346 * This routine is called when rechecking for packets after the RcvAvail 8347 * interrupt has been cleared down. First, do a quick check of memory for 8348 * a packet present. If not found, use an expensive CSR read of the context 8349 * tail to determine the actual tail. The CSR read is necessary because there 8350 * is no method to push pending DMAs to memory other than an interrupt and we 8351 * are trying to determine if we need to force an interrupt. 8352 */ 8353 static inline int check_packet_present(struct hfi1_ctxtdata *rcd) 8354 { 8355 u32 tail; 8356 int present; 8357 8358 if (!HFI1_CAP_IS_KSET(DMA_RTAIL)) 8359 present = (rcd->seq_cnt == 8360 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd)))); 8361 else /* is RDMA rtail */ 8362 present = (rcd->head != get_rcvhdrtail(rcd)); 8363 8364 if (present) 8365 return 1; 8366 8367 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */ 8368 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 8369 return rcd->head != tail; 8370 } 8371 8372 /* 8373 * Receive packet IRQ handler. This routine expects to be on its own IRQ. 8374 * This routine will try to handle packets immediately (latency), but if 8375 * it finds too many, it will invoke the thread handler (bandwitdh). The 8376 * chip receive interrupt is *not* cleared down until this or the thread (if 8377 * invoked) is finished. The intent is to avoid extra interrupts while we 8378 * are processing packets anyway. 8379 */ 8380 static irqreturn_t receive_context_interrupt(int irq, void *data) 8381 { 8382 struct hfi1_ctxtdata *rcd = data; 8383 struct hfi1_devdata *dd = rcd->dd; 8384 int disposition; 8385 int present; 8386 8387 trace_hfi1_receive_interrupt(dd, rcd); 8388 this_cpu_inc(*dd->int_counter); 8389 aspm_ctx_disable(rcd); 8390 8391 /* receive interrupt remains blocked while processing packets */ 8392 disposition = rcd->do_interrupt(rcd, 0); 8393 8394 /* 8395 * Too many packets were seen while processing packets in this 8396 * IRQ handler. Invoke the handler thread. The receive interrupt 8397 * remains blocked. 8398 */ 8399 if (disposition == RCV_PKT_LIMIT) 8400 return IRQ_WAKE_THREAD; 8401 8402 /* 8403 * The packet processor detected no more packets. Clear the receive 8404 * interrupt and recheck for a packet packet that may have arrived 8405 * after the previous check and interrupt clear. If a packet arrived, 8406 * force another interrupt. 8407 */ 8408 clear_recv_intr(rcd); 8409 present = check_packet_present(rcd); 8410 if (present) 8411 force_recv_intr(rcd); 8412 8413 return IRQ_HANDLED; 8414 } 8415 8416 /* 8417 * Receive packet thread handler. This expects to be invoked with the 8418 * receive interrupt still blocked. 8419 */ 8420 static irqreturn_t receive_context_thread(int irq, void *data) 8421 { 8422 struct hfi1_ctxtdata *rcd = data; 8423 int present; 8424 8425 /* receive interrupt is still blocked from the IRQ handler */ 8426 (void)rcd->do_interrupt(rcd, 1); 8427 8428 /* 8429 * The packet processor will only return if it detected no more 8430 * packets. Hold IRQs here so we can safely clear the interrupt and 8431 * recheck for a packet that may have arrived after the previous 8432 * check and the interrupt clear. If a packet arrived, force another 8433 * interrupt. 8434 */ 8435 local_irq_disable(); 8436 clear_recv_intr(rcd); 8437 present = check_packet_present(rcd); 8438 if (present) 8439 force_recv_intr(rcd); 8440 local_irq_enable(); 8441 8442 return IRQ_HANDLED; 8443 } 8444 8445 /* ========================================================================= */ 8446 8447 u32 read_physical_state(struct hfi1_devdata *dd) 8448 { 8449 u64 reg; 8450 8451 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 8452 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT) 8453 & DC_DC8051_STS_CUR_STATE_PORT_MASK; 8454 } 8455 8456 u32 read_logical_state(struct hfi1_devdata *dd) 8457 { 8458 u64 reg; 8459 8460 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8461 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT) 8462 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK; 8463 } 8464 8465 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate) 8466 { 8467 u64 reg; 8468 8469 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8470 /* clear current state, set new state */ 8471 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK; 8472 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT; 8473 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); 8474 } 8475 8476 /* 8477 * Use the 8051 to read a LCB CSR. 8478 */ 8479 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data) 8480 { 8481 u32 regno; 8482 int ret; 8483 8484 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 8485 if (acquire_lcb_access(dd, 0) == 0) { 8486 *data = read_csr(dd, addr); 8487 release_lcb_access(dd, 0); 8488 return 0; 8489 } 8490 return -EBUSY; 8491 } 8492 8493 /* register is an index of LCB registers: (offset - base) / 8 */ 8494 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8495 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data); 8496 if (ret != HCMD_SUCCESS) 8497 return -EBUSY; 8498 return 0; 8499 } 8500 8501 /* 8502 * Provide a cache for some of the LCB registers in case the LCB is 8503 * unavailable. 8504 * (The LCB is unavailable in certain link states, for example.) 8505 */ 8506 struct lcb_datum { 8507 u32 off; 8508 u64 val; 8509 }; 8510 8511 static struct lcb_datum lcb_cache[] = { 8512 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0}, 8513 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 }, 8514 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 }, 8515 }; 8516 8517 static void update_lcb_cache(struct hfi1_devdata *dd) 8518 { 8519 int i; 8520 int ret; 8521 u64 val; 8522 8523 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8524 ret = read_lcb_csr(dd, lcb_cache[i].off, &val); 8525 8526 /* Update if we get good data */ 8527 if (likely(ret != -EBUSY)) 8528 lcb_cache[i].val = val; 8529 } 8530 } 8531 8532 static int read_lcb_cache(u32 off, u64 *val) 8533 { 8534 int i; 8535 8536 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8537 if (lcb_cache[i].off == off) { 8538 *val = lcb_cache[i].val; 8539 return 0; 8540 } 8541 } 8542 8543 pr_warn("%s bad offset 0x%x\n", __func__, off); 8544 return -1; 8545 } 8546 8547 /* 8548 * Read an LCB CSR. Access may not be in host control, so check. 8549 * Return 0 on success, -EBUSY on failure. 8550 */ 8551 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data) 8552 { 8553 struct hfi1_pportdata *ppd = dd->pport; 8554 8555 /* if up, go through the 8051 for the value */ 8556 if (ppd->host_link_state & HLS_UP) 8557 return read_lcb_via_8051(dd, addr, data); 8558 /* if going up or down, check the cache, otherwise, no access */ 8559 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) { 8560 if (read_lcb_cache(addr, data)) 8561 return -EBUSY; 8562 return 0; 8563 } 8564 8565 /* otherwise, host has access */ 8566 *data = read_csr(dd, addr); 8567 return 0; 8568 } 8569 8570 /* 8571 * Use the 8051 to write a LCB CSR. 8572 */ 8573 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data) 8574 { 8575 u32 regno; 8576 int ret; 8577 8578 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || 8579 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) { 8580 if (acquire_lcb_access(dd, 0) == 0) { 8581 write_csr(dd, addr, data); 8582 release_lcb_access(dd, 0); 8583 return 0; 8584 } 8585 return -EBUSY; 8586 } 8587 8588 /* register is an index of LCB registers: (offset - base) / 8 */ 8589 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8590 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data); 8591 if (ret != HCMD_SUCCESS) 8592 return -EBUSY; 8593 return 0; 8594 } 8595 8596 /* 8597 * Write an LCB CSR. Access may not be in host control, so check. 8598 * Return 0 on success, -EBUSY on failure. 8599 */ 8600 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data) 8601 { 8602 struct hfi1_pportdata *ppd = dd->pport; 8603 8604 /* if up, go through the 8051 for the value */ 8605 if (ppd->host_link_state & HLS_UP) 8606 return write_lcb_via_8051(dd, addr, data); 8607 /* if going up or down, no access */ 8608 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) 8609 return -EBUSY; 8610 /* otherwise, host has access */ 8611 write_csr(dd, addr, data); 8612 return 0; 8613 } 8614 8615 /* 8616 * Returns: 8617 * < 0 = Linux error, not able to get access 8618 * > 0 = 8051 command RETURN_CODE 8619 */ 8620 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 8621 u64 *out_data) 8622 { 8623 u64 reg, completed; 8624 int return_code; 8625 unsigned long timeout; 8626 8627 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data); 8628 8629 mutex_lock(&dd->dc8051_lock); 8630 8631 /* We can't send any commands to the 8051 if it's in reset */ 8632 if (dd->dc_shutdown) { 8633 return_code = -ENODEV; 8634 goto fail; 8635 } 8636 8637 /* 8638 * If an 8051 host command timed out previously, then the 8051 is 8639 * stuck. 8640 * 8641 * On first timeout, attempt to reset and restart the entire DC 8642 * block (including 8051). (Is this too big of a hammer?) 8643 * 8644 * If the 8051 times out a second time, the reset did not bring it 8645 * back to healthy life. In that case, fail any subsequent commands. 8646 */ 8647 if (dd->dc8051_timed_out) { 8648 if (dd->dc8051_timed_out > 1) { 8649 dd_dev_err(dd, 8650 "Previous 8051 host command timed out, skipping command %u\n", 8651 type); 8652 return_code = -ENXIO; 8653 goto fail; 8654 } 8655 _dc_shutdown(dd); 8656 _dc_start(dd); 8657 } 8658 8659 /* 8660 * If there is no timeout, then the 8051 command interface is 8661 * waiting for a command. 8662 */ 8663 8664 /* 8665 * When writing a LCB CSR, out_data contains the full value to 8666 * to be written, while in_data contains the relative LCB 8667 * address in 7:0. Do the work here, rather than the caller, 8668 * of distrubting the write data to where it needs to go: 8669 * 8670 * Write data 8671 * 39:00 -> in_data[47:8] 8672 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE 8673 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA 8674 */ 8675 if (type == HCMD_WRITE_LCB_CSR) { 8676 in_data |= ((*out_data) & 0xffffffffffull) << 8; 8677 /* must preserve COMPLETED - it is tied to hardware */ 8678 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); 8679 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK; 8680 reg |= ((((*out_data) >> 40) & 0xff) << 8681 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT) 8682 | ((((*out_data) >> 48) & 0xffff) << 8683 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 8684 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); 8685 } 8686 8687 /* 8688 * Do two writes: the first to stabilize the type and req_data, the 8689 * second to activate. 8690 */ 8691 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK) 8692 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8693 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK) 8694 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT; 8695 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8696 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK; 8697 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8698 8699 /* wait for completion, alternate: interrupt */ 8700 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT); 8701 while (1) { 8702 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); 8703 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK; 8704 if (completed) 8705 break; 8706 if (time_after(jiffies, timeout)) { 8707 dd->dc8051_timed_out++; 8708 dd_dev_err(dd, "8051 host command %u timeout\n", type); 8709 if (out_data) 8710 *out_data = 0; 8711 return_code = -ETIMEDOUT; 8712 goto fail; 8713 } 8714 udelay(2); 8715 } 8716 8717 if (out_data) { 8718 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT) 8719 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK; 8720 if (type == HCMD_READ_LCB_CSR) { 8721 /* top 16 bits are in a different register */ 8722 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) 8723 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK) 8724 << (48 8725 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT); 8726 } 8727 } 8728 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT) 8729 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK; 8730 dd->dc8051_timed_out = 0; 8731 /* 8732 * Clear command for next user. 8733 */ 8734 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); 8735 8736 fail: 8737 mutex_unlock(&dd->dc8051_lock); 8738 return return_code; 8739 } 8740 8741 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state) 8742 { 8743 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL); 8744 } 8745 8746 int load_8051_config(struct hfi1_devdata *dd, u8 field_id, 8747 u8 lane_id, u32 config_data) 8748 { 8749 u64 data; 8750 int ret; 8751 8752 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT 8753 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT 8754 | (u64)config_data << LOAD_DATA_DATA_SHIFT; 8755 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL); 8756 if (ret != HCMD_SUCCESS) { 8757 dd_dev_err(dd, 8758 "load 8051 config: field id %d, lane %d, err %d\n", 8759 (int)field_id, (int)lane_id, ret); 8760 } 8761 return ret; 8762 } 8763 8764 /* 8765 * Read the 8051 firmware "registers". Use the RAM directly. Always 8766 * set the result, even on error. 8767 * Return 0 on success, -errno on failure 8768 */ 8769 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id, 8770 u32 *result) 8771 { 8772 u64 big_data; 8773 u32 addr; 8774 int ret; 8775 8776 /* address start depends on the lane_id */ 8777 if (lane_id < 4) 8778 addr = (4 * NUM_GENERAL_FIELDS) 8779 + (lane_id * 4 * NUM_LANE_FIELDS); 8780 else 8781 addr = 0; 8782 addr += field_id * 4; 8783 8784 /* read is in 8-byte chunks, hardware will truncate the address down */ 8785 ret = read_8051_data(dd, addr, 8, &big_data); 8786 8787 if (ret == 0) { 8788 /* extract the 4 bytes we want */ 8789 if (addr & 0x4) 8790 *result = (u32)(big_data >> 32); 8791 else 8792 *result = (u32)big_data; 8793 } else { 8794 *result = 0; 8795 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n", 8796 __func__, lane_id, field_id); 8797 } 8798 8799 return ret; 8800 } 8801 8802 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management, 8803 u8 continuous) 8804 { 8805 u32 frame; 8806 8807 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 8808 | power_management << POWER_MANAGEMENT_SHIFT; 8809 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY, 8810 GENERAL_CONFIG, frame); 8811 } 8812 8813 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu, 8814 u16 vl15buf, u8 crc_sizes) 8815 { 8816 u32 frame; 8817 8818 frame = (u32)vau << VAU_SHIFT 8819 | (u32)z << Z_SHIFT 8820 | (u32)vcu << VCU_SHIFT 8821 | (u32)vl15buf << VL15BUF_SHIFT 8822 | (u32)crc_sizes << CRC_SIZES_SHIFT; 8823 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC, 8824 GENERAL_CONFIG, frame); 8825 } 8826 8827 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits, 8828 u8 *flag_bits, u16 *link_widths) 8829 { 8830 u32 frame; 8831 8832 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG, 8833 &frame); 8834 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK; 8835 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK; 8836 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8837 } 8838 8839 static int write_vc_local_link_width(struct hfi1_devdata *dd, 8840 u8 misc_bits, 8841 u8 flag_bits, 8842 u16 link_widths) 8843 { 8844 u32 frame; 8845 8846 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT 8847 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT 8848 | (u32)link_widths << LINK_WIDTH_SHIFT; 8849 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG, 8850 frame); 8851 } 8852 8853 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id, 8854 u8 device_rev) 8855 { 8856 u32 frame; 8857 8858 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT) 8859 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT); 8860 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame); 8861 } 8862 8863 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 8864 u8 *device_rev) 8865 { 8866 u32 frame; 8867 8868 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame); 8869 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK; 8870 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT) 8871 & REMOTE_DEVICE_REV_MASK; 8872 } 8873 8874 int write_host_interface_version(struct hfi1_devdata *dd, u8 version) 8875 { 8876 u32 frame; 8877 u32 mask; 8878 8879 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); 8880 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame); 8881 /* Clear, then set field */ 8882 frame &= ~mask; 8883 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT); 8884 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, 8885 frame); 8886 } 8887 8888 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 8889 u8 *ver_patch) 8890 { 8891 u32 frame; 8892 8893 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame); 8894 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) & 8895 STS_FM_VERSION_MAJOR_MASK; 8896 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) & 8897 STS_FM_VERSION_MINOR_MASK; 8898 8899 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame); 8900 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) & 8901 STS_FM_VERSION_PATCH_MASK; 8902 } 8903 8904 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 8905 u8 *continuous) 8906 { 8907 u32 frame; 8908 8909 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame); 8910 *power_management = (frame >> POWER_MANAGEMENT_SHIFT) 8911 & POWER_MANAGEMENT_MASK; 8912 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT) 8913 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK; 8914 } 8915 8916 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 8917 u8 *vcu, u16 *vl15buf, u8 *crc_sizes) 8918 { 8919 u32 frame; 8920 8921 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame); 8922 *vau = (frame >> VAU_SHIFT) & VAU_MASK; 8923 *z = (frame >> Z_SHIFT) & Z_MASK; 8924 *vcu = (frame >> VCU_SHIFT) & VCU_MASK; 8925 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK; 8926 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK; 8927 } 8928 8929 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 8930 u8 *remote_tx_rate, 8931 u16 *link_widths) 8932 { 8933 u32 frame; 8934 8935 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG, 8936 &frame); 8937 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT) 8938 & REMOTE_TX_RATE_MASK; 8939 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8940 } 8941 8942 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx) 8943 { 8944 u32 frame; 8945 8946 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame); 8947 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK; 8948 } 8949 8950 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls) 8951 { 8952 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls); 8953 } 8954 8955 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs) 8956 { 8957 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs); 8958 } 8959 8960 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality) 8961 { 8962 u32 frame; 8963 int ret; 8964 8965 *link_quality = 0; 8966 if (dd->pport->host_link_state & HLS_UP) { 8967 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, 8968 &frame); 8969 if (ret == 0) 8970 *link_quality = (frame >> LINK_QUALITY_SHIFT) 8971 & LINK_QUALITY_MASK; 8972 } 8973 } 8974 8975 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc) 8976 { 8977 u32 frame; 8978 8979 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame); 8980 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK; 8981 } 8982 8983 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr) 8984 { 8985 u32 frame; 8986 8987 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame); 8988 *ldr = (frame & 0xff); 8989 } 8990 8991 static int read_tx_settings(struct hfi1_devdata *dd, 8992 u8 *enable_lane_tx, 8993 u8 *tx_polarity_inversion, 8994 u8 *rx_polarity_inversion, 8995 u8 *max_rate) 8996 { 8997 u32 frame; 8998 int ret; 8999 9000 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame); 9001 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT) 9002 & ENABLE_LANE_TX_MASK; 9003 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT) 9004 & TX_POLARITY_INVERSION_MASK; 9005 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT) 9006 & RX_POLARITY_INVERSION_MASK; 9007 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK; 9008 return ret; 9009 } 9010 9011 static int write_tx_settings(struct hfi1_devdata *dd, 9012 u8 enable_lane_tx, 9013 u8 tx_polarity_inversion, 9014 u8 rx_polarity_inversion, 9015 u8 max_rate) 9016 { 9017 u32 frame; 9018 9019 /* no need to mask, all variable sizes match field widths */ 9020 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT 9021 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT 9022 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT 9023 | max_rate << MAX_RATE_SHIFT; 9024 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame); 9025 } 9026 9027 /* 9028 * Read an idle LCB message. 9029 * 9030 * Returns 0 on success, -EINVAL on error 9031 */ 9032 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out) 9033 { 9034 int ret; 9035 9036 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out); 9037 if (ret != HCMD_SUCCESS) { 9038 dd_dev_err(dd, "read idle message: type %d, err %d\n", 9039 (u32)type, ret); 9040 return -EINVAL; 9041 } 9042 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out); 9043 /* return only the payload as we already know the type */ 9044 *data_out >>= IDLE_PAYLOAD_SHIFT; 9045 return 0; 9046 } 9047 9048 /* 9049 * Read an idle SMA message. To be done in response to a notification from 9050 * the 8051. 9051 * 9052 * Returns 0 on success, -EINVAL on error 9053 */ 9054 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data) 9055 { 9056 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT, 9057 data); 9058 } 9059 9060 /* 9061 * Send an idle LCB message. 9062 * 9063 * Returns 0 on success, -EINVAL on error 9064 */ 9065 static int send_idle_message(struct hfi1_devdata *dd, u64 data) 9066 { 9067 int ret; 9068 9069 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data); 9070 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL); 9071 if (ret != HCMD_SUCCESS) { 9072 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n", 9073 data, ret); 9074 return -EINVAL; 9075 } 9076 return 0; 9077 } 9078 9079 /* 9080 * Send an idle SMA message. 9081 * 9082 * Returns 0 on success, -EINVAL on error 9083 */ 9084 int send_idle_sma(struct hfi1_devdata *dd, u64 message) 9085 { 9086 u64 data; 9087 9088 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) | 9089 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT); 9090 return send_idle_message(dd, data); 9091 } 9092 9093 /* 9094 * Initialize the LCB then do a quick link up. This may or may not be 9095 * in loopback. 9096 * 9097 * return 0 on success, -errno on error 9098 */ 9099 static int do_quick_linkup(struct hfi1_devdata *dd) 9100 { 9101 int ret; 9102 9103 lcb_shutdown(dd, 0); 9104 9105 if (loopback) { 9106 /* LCB_CFG_LOOPBACK.VAL = 2 */ 9107 /* LCB_CFG_LANE_WIDTH.VAL = 0 */ 9108 write_csr(dd, DC_LCB_CFG_LOOPBACK, 9109 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT); 9110 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 9111 } 9112 9113 /* start the LCBs */ 9114 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */ 9115 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 9116 9117 /* simulator only loopback steps */ 9118 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 9119 /* LCB_CFG_RUN.EN = 1 */ 9120 write_csr(dd, DC_LCB_CFG_RUN, 9121 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 9122 9123 ret = wait_link_transfer_active(dd, 10); 9124 if (ret) 9125 return ret; 9126 9127 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 9128 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT); 9129 } 9130 9131 if (!loopback) { 9132 /* 9133 * When doing quick linkup and not in loopback, both 9134 * sides must be done with LCB set-up before either 9135 * starts the quick linkup. Put a delay here so that 9136 * both sides can be started and have a chance to be 9137 * done with LCB set up before resuming. 9138 */ 9139 dd_dev_err(dd, 9140 "Pausing for peer to be finished with LCB set up\n"); 9141 msleep(5000); 9142 dd_dev_err(dd, "Continuing with quick linkup\n"); 9143 } 9144 9145 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 9146 set_8051_lcb_access(dd); 9147 9148 /* 9149 * State "quick" LinkUp request sets the physical link state to 9150 * LinkUp without a verify capability sequence. 9151 * This state is in simulator v37 and later. 9152 */ 9153 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP); 9154 if (ret != HCMD_SUCCESS) { 9155 dd_dev_err(dd, 9156 "%s: set physical link state to quick LinkUp failed with return %d\n", 9157 __func__, ret); 9158 9159 set_host_lcb_access(dd); 9160 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 9161 9162 if (ret >= 0) 9163 ret = -EINVAL; 9164 return ret; 9165 } 9166 9167 return 0; /* success */ 9168 } 9169 9170 /* 9171 * Do all special steps to set up loopback. 9172 */ 9173 static int init_loopback(struct hfi1_devdata *dd) 9174 { 9175 dd_dev_info(dd, "Entering loopback mode\n"); 9176 9177 /* all loopbacks should disable self GUID check */ 9178 write_csr(dd, DC_DC8051_CFG_MODE, 9179 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); 9180 9181 /* 9182 * The simulator has only one loopback option - LCB. Switch 9183 * to that option, which includes quick link up. 9184 * 9185 * Accept all valid loopback values. 9186 */ 9187 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) && 9188 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB || 9189 loopback == LOOPBACK_CABLE)) { 9190 loopback = LOOPBACK_LCB; 9191 quick_linkup = 1; 9192 return 0; 9193 } 9194 9195 /* 9196 * SerDes loopback init sequence is handled in set_local_link_attributes 9197 */ 9198 if (loopback == LOOPBACK_SERDES) 9199 return 0; 9200 9201 /* LCB loopback - handled at poll time */ 9202 if (loopback == LOOPBACK_LCB) { 9203 quick_linkup = 1; /* LCB is always quick linkup */ 9204 9205 /* not supported in emulation due to emulation RTL changes */ 9206 if (dd->icode == ICODE_FPGA_EMULATION) { 9207 dd_dev_err(dd, 9208 "LCB loopback not supported in emulation\n"); 9209 return -EINVAL; 9210 } 9211 return 0; 9212 } 9213 9214 /* external cable loopback requires no extra steps */ 9215 if (loopback == LOOPBACK_CABLE) 9216 return 0; 9217 9218 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback); 9219 return -EINVAL; 9220 } 9221 9222 /* 9223 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits 9224 * used in the Verify Capability link width attribute. 9225 */ 9226 static u16 opa_to_vc_link_widths(u16 opa_widths) 9227 { 9228 int i; 9229 u16 result = 0; 9230 9231 static const struct link_bits { 9232 u16 from; 9233 u16 to; 9234 } opa_link_xlate[] = { 9235 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) }, 9236 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) }, 9237 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) }, 9238 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) }, 9239 }; 9240 9241 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) { 9242 if (opa_widths & opa_link_xlate[i].from) 9243 result |= opa_link_xlate[i].to; 9244 } 9245 return result; 9246 } 9247 9248 /* 9249 * Set link attributes before moving to polling. 9250 */ 9251 static int set_local_link_attributes(struct hfi1_pportdata *ppd) 9252 { 9253 struct hfi1_devdata *dd = ppd->dd; 9254 u8 enable_lane_tx; 9255 u8 tx_polarity_inversion; 9256 u8 rx_polarity_inversion; 9257 int ret; 9258 u32 misc_bits = 0; 9259 /* reset our fabric serdes to clear any lingering problems */ 9260 fabric_serdes_reset(dd); 9261 9262 /* set the local tx rate - need to read-modify-write */ 9263 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 9264 &rx_polarity_inversion, &ppd->local_tx_rate); 9265 if (ret) 9266 goto set_local_link_attributes_fail; 9267 9268 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 9269 /* set the tx rate to the fastest enabled */ 9270 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9271 ppd->local_tx_rate = 1; 9272 else 9273 ppd->local_tx_rate = 0; 9274 } else { 9275 /* set the tx rate to all enabled */ 9276 ppd->local_tx_rate = 0; 9277 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9278 ppd->local_tx_rate |= 2; 9279 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G) 9280 ppd->local_tx_rate |= 1; 9281 } 9282 9283 enable_lane_tx = 0xF; /* enable all four lanes */ 9284 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion, 9285 rx_polarity_inversion, ppd->local_tx_rate); 9286 if (ret != HCMD_SUCCESS) 9287 goto set_local_link_attributes_fail; 9288 9289 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION); 9290 if (ret != HCMD_SUCCESS) { 9291 dd_dev_err(dd, 9292 "Failed to set host interface version, return 0x%x\n", 9293 ret); 9294 goto set_local_link_attributes_fail; 9295 } 9296 9297 /* 9298 * DC supports continuous updates. 9299 */ 9300 ret = write_vc_local_phy(dd, 9301 0 /* no power management */, 9302 1 /* continuous updates */); 9303 if (ret != HCMD_SUCCESS) 9304 goto set_local_link_attributes_fail; 9305 9306 /* z=1 in the next call: AU of 0 is not supported by the hardware */ 9307 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init, 9308 ppd->port_crc_mode_enabled); 9309 if (ret != HCMD_SUCCESS) 9310 goto set_local_link_attributes_fail; 9311 9312 /* 9313 * SerDes loopback init sequence requires 9314 * setting bit 0 of MISC_CONFIG_BITS 9315 */ 9316 if (loopback == LOOPBACK_SERDES) 9317 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT; 9318 9319 ret = write_vc_local_link_width(dd, misc_bits, 0, 9320 opa_to_vc_link_widths( 9321 ppd->link_width_enabled)); 9322 if (ret != HCMD_SUCCESS) 9323 goto set_local_link_attributes_fail; 9324 9325 /* let peer know who we are */ 9326 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev); 9327 if (ret == HCMD_SUCCESS) 9328 return 0; 9329 9330 set_local_link_attributes_fail: 9331 dd_dev_err(dd, 9332 "Failed to set local link attributes, return 0x%x\n", 9333 ret); 9334 return ret; 9335 } 9336 9337 /* 9338 * Call this to start the link. 9339 * Do not do anything if the link is disabled. 9340 * Returns 0 if link is disabled, moved to polling, or the driver is not ready. 9341 */ 9342 int start_link(struct hfi1_pportdata *ppd) 9343 { 9344 /* 9345 * Tune the SerDes to a ballpark setting for optimal signal and bit 9346 * error rate. Needs to be done before starting the link. 9347 */ 9348 tune_serdes(ppd); 9349 9350 if (!ppd->driver_link_ready) { 9351 dd_dev_info(ppd->dd, 9352 "%s: stopping link start because driver is not ready\n", 9353 __func__); 9354 return 0; 9355 } 9356 9357 /* 9358 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the 9359 * pkey table can be configured properly if the HFI unit is connected 9360 * to switch port with MgmtAllowed=NO 9361 */ 9362 clear_full_mgmt_pkey(ppd); 9363 9364 return set_link_state(ppd, HLS_DN_POLL); 9365 } 9366 9367 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd) 9368 { 9369 struct hfi1_devdata *dd = ppd->dd; 9370 u64 mask; 9371 unsigned long timeout; 9372 9373 /* 9374 * Some QSFP cables have a quirk that asserts the IntN line as a side 9375 * effect of power up on plug-in. We ignore this false positive 9376 * interrupt until the module has finished powering up by waiting for 9377 * a minimum timeout of the module inrush initialization time of 9378 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the 9379 * module have stabilized. 9380 */ 9381 msleep(500); 9382 9383 /* 9384 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1) 9385 */ 9386 timeout = jiffies + msecs_to_jiffies(2000); 9387 while (1) { 9388 mask = read_csr(dd, dd->hfi1_id ? 9389 ASIC_QSFP2_IN : ASIC_QSFP1_IN); 9390 if (!(mask & QSFP_HFI0_INT_N)) 9391 break; 9392 if (time_after(jiffies, timeout)) { 9393 dd_dev_info(dd, "%s: No IntN detected, reset complete\n", 9394 __func__); 9395 break; 9396 } 9397 udelay(2); 9398 } 9399 } 9400 9401 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable) 9402 { 9403 struct hfi1_devdata *dd = ppd->dd; 9404 u64 mask; 9405 9406 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); 9407 if (enable) { 9408 /* 9409 * Clear the status register to avoid an immediate interrupt 9410 * when we re-enable the IntN pin 9411 */ 9412 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9413 QSFP_HFI0_INT_N); 9414 mask |= (u64)QSFP_HFI0_INT_N; 9415 } else { 9416 mask &= ~(u64)QSFP_HFI0_INT_N; 9417 } 9418 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); 9419 } 9420 9421 int reset_qsfp(struct hfi1_pportdata *ppd) 9422 { 9423 struct hfi1_devdata *dd = ppd->dd; 9424 u64 mask, qsfp_mask; 9425 9426 /* Disable INT_N from triggering QSFP interrupts */ 9427 set_qsfp_int_n(ppd, 0); 9428 9429 /* Reset the QSFP */ 9430 mask = (u64)QSFP_HFI0_RESET_N; 9431 9432 qsfp_mask = read_csr(dd, 9433 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT); 9434 qsfp_mask &= ~mask; 9435 write_csr(dd, 9436 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9437 9438 udelay(10); 9439 9440 qsfp_mask |= mask; 9441 write_csr(dd, 9442 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9443 9444 wait_for_qsfp_init(ppd); 9445 9446 /* 9447 * Allow INT_N to trigger the QSFP interrupt to watch 9448 * for alarms and warnings 9449 */ 9450 set_qsfp_int_n(ppd, 1); 9451 9452 /* 9453 * After the reset, AOC transmitters are enabled by default. They need 9454 * to be turned off to complete the QSFP setup before they can be 9455 * enabled again. 9456 */ 9457 return set_qsfp_tx(ppd, 0); 9458 } 9459 9460 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd, 9461 u8 *qsfp_interrupt_status) 9462 { 9463 struct hfi1_devdata *dd = ppd->dd; 9464 9465 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) || 9466 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING)) 9467 dd_dev_err(dd, "%s: QSFP cable temperature too high\n", 9468 __func__); 9469 9470 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) || 9471 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING)) 9472 dd_dev_err(dd, "%s: QSFP cable temperature too low\n", 9473 __func__); 9474 9475 /* 9476 * The remaining alarms/warnings don't matter if the link is down. 9477 */ 9478 if (ppd->host_link_state & HLS_DOWN) 9479 return 0; 9480 9481 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) || 9482 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING)) 9483 dd_dev_err(dd, "%s: QSFP supply voltage too high\n", 9484 __func__); 9485 9486 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) || 9487 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING)) 9488 dd_dev_err(dd, "%s: QSFP supply voltage too low\n", 9489 __func__); 9490 9491 /* Byte 2 is vendor specific */ 9492 9493 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) || 9494 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING)) 9495 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n", 9496 __func__); 9497 9498 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) || 9499 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING)) 9500 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n", 9501 __func__); 9502 9503 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) || 9504 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING)) 9505 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n", 9506 __func__); 9507 9508 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) || 9509 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING)) 9510 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n", 9511 __func__); 9512 9513 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) || 9514 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING)) 9515 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n", 9516 __func__); 9517 9518 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) || 9519 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING)) 9520 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n", 9521 __func__); 9522 9523 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) || 9524 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING)) 9525 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n", 9526 __func__); 9527 9528 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) || 9529 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING)) 9530 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n", 9531 __func__); 9532 9533 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) || 9534 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING)) 9535 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n", 9536 __func__); 9537 9538 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) || 9539 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING)) 9540 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n", 9541 __func__); 9542 9543 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) || 9544 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING)) 9545 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n", 9546 __func__); 9547 9548 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) || 9549 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING)) 9550 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n", 9551 __func__); 9552 9553 /* Bytes 9-10 and 11-12 are reserved */ 9554 /* Bytes 13-15 are vendor specific */ 9555 9556 return 0; 9557 } 9558 9559 /* This routine will only be scheduled if the QSFP module present is asserted */ 9560 void qsfp_event(struct work_struct *work) 9561 { 9562 struct qsfp_data *qd; 9563 struct hfi1_pportdata *ppd; 9564 struct hfi1_devdata *dd; 9565 9566 qd = container_of(work, struct qsfp_data, qsfp_work); 9567 ppd = qd->ppd; 9568 dd = ppd->dd; 9569 9570 /* Sanity check */ 9571 if (!qsfp_mod_present(ppd)) 9572 return; 9573 9574 if (ppd->host_link_state == HLS_DN_DISABLE) { 9575 dd_dev_info(ppd->dd, 9576 "%s: stopping link start because link is disabled\n", 9577 __func__); 9578 return; 9579 } 9580 9581 /* 9582 * Turn DC back on after cable has been re-inserted. Up until 9583 * now, the DC has been in reset to save power. 9584 */ 9585 dc_start(dd); 9586 9587 if (qd->cache_refresh_required) { 9588 set_qsfp_int_n(ppd, 0); 9589 9590 wait_for_qsfp_init(ppd); 9591 9592 /* 9593 * Allow INT_N to trigger the QSFP interrupt to watch 9594 * for alarms and warnings 9595 */ 9596 set_qsfp_int_n(ppd, 1); 9597 9598 start_link(ppd); 9599 } 9600 9601 if (qd->check_interrupt_flags) { 9602 u8 qsfp_interrupt_status[16] = {0,}; 9603 9604 if (one_qsfp_read(ppd, dd->hfi1_id, 6, 9605 &qsfp_interrupt_status[0], 16) != 16) { 9606 dd_dev_info(dd, 9607 "%s: Failed to read status of QSFP module\n", 9608 __func__); 9609 } else { 9610 unsigned long flags; 9611 9612 handle_qsfp_error_conditions( 9613 ppd, qsfp_interrupt_status); 9614 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 9615 ppd->qsfp_info.check_interrupt_flags = 0; 9616 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 9617 flags); 9618 } 9619 } 9620 } 9621 9622 static void init_qsfp_int(struct hfi1_devdata *dd) 9623 { 9624 struct hfi1_pportdata *ppd = dd->pport; 9625 u64 qsfp_mask, cce_int_mask; 9626 const int qsfp1_int_smask = QSFP1_INT % 64; 9627 const int qsfp2_int_smask = QSFP2_INT % 64; 9628 9629 /* 9630 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0 9631 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR, 9632 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find 9633 * the index of the appropriate CSR in the CCEIntMask CSR array 9634 */ 9635 cce_int_mask = read_csr(dd, CCE_INT_MASK + 9636 (8 * (QSFP1_INT / 64))); 9637 if (dd->hfi1_id) { 9638 cce_int_mask &= ~((u64)1 << qsfp1_int_smask); 9639 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)), 9640 cce_int_mask); 9641 } else { 9642 cce_int_mask &= ~((u64)1 << qsfp2_int_smask); 9643 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)), 9644 cce_int_mask); 9645 } 9646 9647 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 9648 /* Clear current status to avoid spurious interrupts */ 9649 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9650 qsfp_mask); 9651 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, 9652 qsfp_mask); 9653 9654 set_qsfp_int_n(ppd, 0); 9655 9656 /* Handle active low nature of INT_N and MODPRST_N pins */ 9657 if (qsfp_mod_present(ppd)) 9658 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N; 9659 write_csr(dd, 9660 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT, 9661 qsfp_mask); 9662 } 9663 9664 /* 9665 * Do a one-time initialize of the LCB block. 9666 */ 9667 static void init_lcb(struct hfi1_devdata *dd) 9668 { 9669 /* simulator does not correctly handle LCB cclk loopback, skip */ 9670 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 9671 return; 9672 9673 /* the DC has been reset earlier in the driver load */ 9674 9675 /* set LCB for cclk loopback on the port */ 9676 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); 9677 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); 9678 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); 9679 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 9680 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); 9681 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); 9682 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); 9683 } 9684 9685 /* 9686 * Perform a test read on the QSFP. Return 0 on success, -ERRNO 9687 * on error. 9688 */ 9689 static int test_qsfp_read(struct hfi1_pportdata *ppd) 9690 { 9691 int ret; 9692 u8 status; 9693 9694 /* 9695 * Report success if not a QSFP or, if it is a QSFP, but the cable is 9696 * not present 9697 */ 9698 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd)) 9699 return 0; 9700 9701 /* read byte 2, the status byte */ 9702 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1); 9703 if (ret < 0) 9704 return ret; 9705 if (ret != 1) 9706 return -EIO; 9707 9708 return 0; /* success */ 9709 } 9710 9711 /* 9712 * Values for QSFP retry. 9713 * 9714 * Give up after 10s (20 x 500ms). The overall timeout was empirically 9715 * arrived at from experience on a large cluster. 9716 */ 9717 #define MAX_QSFP_RETRIES 20 9718 #define QSFP_RETRY_WAIT 500 /* msec */ 9719 9720 /* 9721 * Try a QSFP read. If it fails, schedule a retry for later. 9722 * Called on first link activation after driver load. 9723 */ 9724 static void try_start_link(struct hfi1_pportdata *ppd) 9725 { 9726 if (test_qsfp_read(ppd)) { 9727 /* read failed */ 9728 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) { 9729 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n"); 9730 return; 9731 } 9732 dd_dev_info(ppd->dd, 9733 "QSFP not responding, waiting and retrying %d\n", 9734 (int)ppd->qsfp_retry_count); 9735 ppd->qsfp_retry_count++; 9736 queue_delayed_work(ppd->link_wq, &ppd->start_link_work, 9737 msecs_to_jiffies(QSFP_RETRY_WAIT)); 9738 return; 9739 } 9740 ppd->qsfp_retry_count = 0; 9741 9742 start_link(ppd); 9743 } 9744 9745 /* 9746 * Workqueue function to start the link after a delay. 9747 */ 9748 void handle_start_link(struct work_struct *work) 9749 { 9750 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 9751 start_link_work.work); 9752 try_start_link(ppd); 9753 } 9754 9755 int bringup_serdes(struct hfi1_pportdata *ppd) 9756 { 9757 struct hfi1_devdata *dd = ppd->dd; 9758 u64 guid; 9759 int ret; 9760 9761 if (HFI1_CAP_IS_KSET(EXTENDED_PSN)) 9762 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK); 9763 9764 guid = ppd->guids[HFI1_PORT_GUID_INDEX]; 9765 if (!guid) { 9766 if (dd->base_guid) 9767 guid = dd->base_guid + ppd->port - 1; 9768 ppd->guids[HFI1_PORT_GUID_INDEX] = guid; 9769 } 9770 9771 /* Set linkinit_reason on power up per OPA spec */ 9772 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP; 9773 9774 /* one-time init of the LCB */ 9775 init_lcb(dd); 9776 9777 if (loopback) { 9778 ret = init_loopback(dd); 9779 if (ret < 0) 9780 return ret; 9781 } 9782 9783 get_port_type(ppd); 9784 if (ppd->port_type == PORT_TYPE_QSFP) { 9785 set_qsfp_int_n(ppd, 0); 9786 wait_for_qsfp_init(ppd); 9787 set_qsfp_int_n(ppd, 1); 9788 } 9789 9790 try_start_link(ppd); 9791 return 0; 9792 } 9793 9794 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd) 9795 { 9796 struct hfi1_devdata *dd = ppd->dd; 9797 9798 /* 9799 * Shut down the link and keep it down. First turn off that the 9800 * driver wants to allow the link to be up (driver_link_ready). 9801 * Then make sure the link is not automatically restarted 9802 * (link_enabled). Cancel any pending restart. And finally 9803 * go offline. 9804 */ 9805 ppd->driver_link_ready = 0; 9806 ppd->link_enabled = 0; 9807 9808 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */ 9809 flush_delayed_work(&ppd->start_link_work); 9810 cancel_delayed_work_sync(&ppd->start_link_work); 9811 9812 ppd->offline_disabled_reason = 9813 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT); 9814 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0, 9815 OPA_LINKDOWN_REASON_REBOOT); 9816 set_link_state(ppd, HLS_DN_OFFLINE); 9817 9818 /* disable the port */ 9819 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 9820 } 9821 9822 static inline int init_cpu_counters(struct hfi1_devdata *dd) 9823 { 9824 struct hfi1_pportdata *ppd; 9825 int i; 9826 9827 ppd = (struct hfi1_pportdata *)(dd + 1); 9828 for (i = 0; i < dd->num_pports; i++, ppd++) { 9829 ppd->ibport_data.rvp.rc_acks = NULL; 9830 ppd->ibport_data.rvp.rc_qacks = NULL; 9831 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64); 9832 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64); 9833 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64); 9834 if (!ppd->ibport_data.rvp.rc_acks || 9835 !ppd->ibport_data.rvp.rc_delayed_comp || 9836 !ppd->ibport_data.rvp.rc_qacks) 9837 return -ENOMEM; 9838 } 9839 9840 return 0; 9841 } 9842 9843 /* 9844 * index is the index into the receive array 9845 */ 9846 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, 9847 u32 type, unsigned long pa, u16 order) 9848 { 9849 u64 reg; 9850 9851 if (!(dd->flags & HFI1_PRESENT)) 9852 goto done; 9853 9854 if (type == PT_INVALID || type == PT_INVALID_FLUSH) { 9855 pa = 0; 9856 order = 0; 9857 } else if (type > PT_INVALID) { 9858 dd_dev_err(dd, 9859 "unexpected receive array type %u for index %u, not handled\n", 9860 type, index); 9861 goto done; 9862 } 9863 trace_hfi1_put_tid(dd, index, type, pa, order); 9864 9865 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */ 9866 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK 9867 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT 9868 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK) 9869 << RCV_ARRAY_RT_ADDR_SHIFT; 9870 trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg); 9871 writeq(reg, dd->rcvarray_wc + (index * 8)); 9872 9873 if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3) 9874 /* 9875 * Eager entries are written and flushed 9876 * 9877 * Expected entries are flushed every 4 writes 9878 */ 9879 flush_wc(); 9880 done: 9881 return; 9882 } 9883 9884 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd) 9885 { 9886 struct hfi1_devdata *dd = rcd->dd; 9887 u32 i; 9888 9889 /* this could be optimized */ 9890 for (i = rcd->eager_base; i < rcd->eager_base + 9891 rcd->egrbufs.alloced; i++) 9892 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 9893 9894 for (i = rcd->expected_base; 9895 i < rcd->expected_base + rcd->expected_count; i++) 9896 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 9897 } 9898 9899 static const char * const ib_cfg_name_strings[] = { 9900 "HFI1_IB_CFG_LIDLMC", 9901 "HFI1_IB_CFG_LWID_DG_ENB", 9902 "HFI1_IB_CFG_LWID_ENB", 9903 "HFI1_IB_CFG_LWID", 9904 "HFI1_IB_CFG_SPD_ENB", 9905 "HFI1_IB_CFG_SPD", 9906 "HFI1_IB_CFG_RXPOL_ENB", 9907 "HFI1_IB_CFG_LREV_ENB", 9908 "HFI1_IB_CFG_LINKLATENCY", 9909 "HFI1_IB_CFG_HRTBT", 9910 "HFI1_IB_CFG_OP_VLS", 9911 "HFI1_IB_CFG_VL_HIGH_CAP", 9912 "HFI1_IB_CFG_VL_LOW_CAP", 9913 "HFI1_IB_CFG_OVERRUN_THRESH", 9914 "HFI1_IB_CFG_PHYERR_THRESH", 9915 "HFI1_IB_CFG_LINKDEFAULT", 9916 "HFI1_IB_CFG_PKEYS", 9917 "HFI1_IB_CFG_MTU", 9918 "HFI1_IB_CFG_LSTATE", 9919 "HFI1_IB_CFG_VL_HIGH_LIMIT", 9920 "HFI1_IB_CFG_PMA_TICKS", 9921 "HFI1_IB_CFG_PORT" 9922 }; 9923 9924 static const char *ib_cfg_name(int which) 9925 { 9926 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings)) 9927 return "invalid"; 9928 return ib_cfg_name_strings[which]; 9929 } 9930 9931 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which) 9932 { 9933 struct hfi1_devdata *dd = ppd->dd; 9934 int val = 0; 9935 9936 switch (which) { 9937 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */ 9938 val = ppd->link_width_enabled; 9939 break; 9940 case HFI1_IB_CFG_LWID: /* currently active Link-width */ 9941 val = ppd->link_width_active; 9942 break; 9943 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 9944 val = ppd->link_speed_enabled; 9945 break; 9946 case HFI1_IB_CFG_SPD: /* current Link speed */ 9947 val = ppd->link_speed_active; 9948 break; 9949 9950 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */ 9951 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */ 9952 case HFI1_IB_CFG_LINKLATENCY: 9953 goto unimplemented; 9954 9955 case HFI1_IB_CFG_OP_VLS: 9956 val = ppd->actual_vls_operational; 9957 break; 9958 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */ 9959 val = VL_ARB_HIGH_PRIO_TABLE_SIZE; 9960 break; 9961 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */ 9962 val = VL_ARB_LOW_PRIO_TABLE_SIZE; 9963 break; 9964 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 9965 val = ppd->overrun_threshold; 9966 break; 9967 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 9968 val = ppd->phy_error_threshold; 9969 break; 9970 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 9971 val = HLS_DEFAULT; 9972 break; 9973 9974 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */ 9975 case HFI1_IB_CFG_PMA_TICKS: 9976 default: 9977 unimplemented: 9978 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 9979 dd_dev_info( 9980 dd, 9981 "%s: which %s: not implemented\n", 9982 __func__, 9983 ib_cfg_name(which)); 9984 break; 9985 } 9986 9987 return val; 9988 } 9989 9990 /* 9991 * The largest MAD packet size. 9992 */ 9993 #define MAX_MAD_PACKET 2048 9994 9995 /* 9996 * Return the maximum header bytes that can go on the _wire_ 9997 * for this device. This count includes the ICRC which is 9998 * not part of the packet held in memory but it is appended 9999 * by the HW. 10000 * This is dependent on the device's receive header entry size. 10001 * HFI allows this to be set per-receive context, but the 10002 * driver presently enforces a global value. 10003 */ 10004 u32 lrh_max_header_bytes(struct hfi1_devdata *dd) 10005 { 10006 /* 10007 * The maximum non-payload (MTU) bytes in LRH.PktLen are 10008 * the Receive Header Entry Size minus the PBC (or RHF) size 10009 * plus one DW for the ICRC appended by HW. 10010 * 10011 * dd->rcd[0].rcvhdrqentsize is in DW. 10012 * We use rcd[0] as all context will have the same value. Also, 10013 * the first kernel context would have been allocated by now so 10014 * we are guaranteed a valid value. 10015 */ 10016 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2; 10017 } 10018 10019 /* 10020 * Set Send Length 10021 * @ppd - per port data 10022 * 10023 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck* 10024 * registers compare against LRH.PktLen, so use the max bytes included 10025 * in the LRH. 10026 * 10027 * This routine changes all VL values except VL15, which it maintains at 10028 * the same value. 10029 */ 10030 static void set_send_length(struct hfi1_pportdata *ppd) 10031 { 10032 struct hfi1_devdata *dd = ppd->dd; 10033 u32 max_hb = lrh_max_header_bytes(dd), dcmtu; 10034 u32 maxvlmtu = dd->vld[15].mtu; 10035 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2) 10036 & SEND_LEN_CHECK1_LEN_VL15_MASK) << 10037 SEND_LEN_CHECK1_LEN_VL15_SHIFT; 10038 int i, j; 10039 u32 thres; 10040 10041 for (i = 0; i < ppd->vls_supported; i++) { 10042 if (dd->vld[i].mtu > maxvlmtu) 10043 maxvlmtu = dd->vld[i].mtu; 10044 if (i <= 3) 10045 len1 |= (((dd->vld[i].mtu + max_hb) >> 2) 10046 & SEND_LEN_CHECK0_LEN_VL0_MASK) << 10047 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT); 10048 else 10049 len2 |= (((dd->vld[i].mtu + max_hb) >> 2) 10050 & SEND_LEN_CHECK1_LEN_VL4_MASK) << 10051 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT); 10052 } 10053 write_csr(dd, SEND_LEN_CHECK0, len1); 10054 write_csr(dd, SEND_LEN_CHECK1, len2); 10055 /* adjust kernel credit return thresholds based on new MTUs */ 10056 /* all kernel receive contexts have the same hdrqentsize */ 10057 for (i = 0; i < ppd->vls_supported; i++) { 10058 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50), 10059 sc_mtu_to_threshold(dd->vld[i].sc, 10060 dd->vld[i].mtu, 10061 dd->rcd[0]->rcvhdrqentsize)); 10062 for (j = 0; j < INIT_SC_PER_VL; j++) 10063 sc_set_cr_threshold( 10064 pio_select_send_context_vl(dd, j, i), 10065 thres); 10066 } 10067 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50), 10068 sc_mtu_to_threshold(dd->vld[15].sc, 10069 dd->vld[15].mtu, 10070 dd->rcd[0]->rcvhdrqentsize)); 10071 sc_set_cr_threshold(dd->vld[15].sc, thres); 10072 10073 /* Adjust maximum MTU for the port in DC */ 10074 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 : 10075 (ilog2(maxvlmtu >> 8) + 1); 10076 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); 10077 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK; 10078 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) << 10079 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT; 10080 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); 10081 } 10082 10083 static void set_lidlmc(struct hfi1_pportdata *ppd) 10084 { 10085 int i; 10086 u64 sreg = 0; 10087 struct hfi1_devdata *dd = ppd->dd; 10088 u32 mask = ~((1U << ppd->lmc) - 1); 10089 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); 10090 u32 lid; 10091 10092 /* 10093 * Program 0 in CSR if port lid is extended. This prevents 10094 * 9B packets being sent out for large lids. 10095 */ 10096 lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid; 10097 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 10098 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK); 10099 c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK) 10100 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) | 10101 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK) 10102 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT); 10103 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); 10104 10105 /* 10106 * Iterate over all the send contexts and set their SLID check 10107 */ 10108 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) << 10109 SEND_CTXT_CHECK_SLID_MASK_SHIFT) | 10110 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) << 10111 SEND_CTXT_CHECK_SLID_VALUE_SHIFT); 10112 10113 for (i = 0; i < dd->chip_send_contexts; i++) { 10114 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x", 10115 i, (u32)sreg); 10116 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg); 10117 } 10118 10119 /* Now we have to do the same thing for the sdma engines */ 10120 sdma_update_lmc(dd, mask, lid); 10121 } 10122 10123 static const char *state_completed_string(u32 completed) 10124 { 10125 static const char * const state_completed[] = { 10126 "EstablishComm", 10127 "OptimizeEQ", 10128 "VerifyCap" 10129 }; 10130 10131 if (completed < ARRAY_SIZE(state_completed)) 10132 return state_completed[completed]; 10133 10134 return "unknown"; 10135 } 10136 10137 static const char all_lanes_dead_timeout_expired[] = 10138 "All lanes were inactive – was the interconnect media removed?"; 10139 static const char tx_out_of_policy[] = 10140 "Passing lanes on local port do not meet the local link width policy"; 10141 static const char no_state_complete[] = 10142 "State timeout occurred before link partner completed the state"; 10143 static const char * const state_complete_reasons[] = { 10144 [0x00] = "Reason unknown", 10145 [0x01] = "Link was halted by driver, refer to LinkDownReason", 10146 [0x02] = "Link partner reported failure", 10147 [0x10] = "Unable to achieve frame sync on any lane", 10148 [0x11] = 10149 "Unable to find a common bit rate with the link partner", 10150 [0x12] = 10151 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy", 10152 [0x13] = 10153 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy", 10154 [0x14] = no_state_complete, 10155 [0x15] = 10156 "State timeout occurred before link partner identified equalization presets", 10157 [0x16] = 10158 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy", 10159 [0x17] = tx_out_of_policy, 10160 [0x20] = all_lanes_dead_timeout_expired, 10161 [0x21] = 10162 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy", 10163 [0x22] = no_state_complete, 10164 [0x23] = 10165 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy", 10166 [0x24] = tx_out_of_policy, 10167 [0x30] = all_lanes_dead_timeout_expired, 10168 [0x31] = 10169 "State timeout occurred waiting for host to process received frames", 10170 [0x32] = no_state_complete, 10171 [0x33] = 10172 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy", 10173 [0x34] = tx_out_of_policy, 10174 [0x35] = "Negotiated link width is mutually exclusive", 10175 [0x36] = 10176 "Timed out before receiving verifycap frames in VerifyCap.Exchange", 10177 [0x37] = "Unable to resolve secure data exchange", 10178 }; 10179 10180 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd, 10181 u32 code) 10182 { 10183 const char *str = NULL; 10184 10185 if (code < ARRAY_SIZE(state_complete_reasons)) 10186 str = state_complete_reasons[code]; 10187 10188 if (str) 10189 return str; 10190 return "Reserved"; 10191 } 10192 10193 /* describe the given last state complete frame */ 10194 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame, 10195 const char *prefix) 10196 { 10197 struct hfi1_devdata *dd = ppd->dd; 10198 u32 success; 10199 u32 state; 10200 u32 reason; 10201 u32 lanes; 10202 10203 /* 10204 * Decode frame: 10205 * [ 0: 0] - success 10206 * [ 3: 1] - state 10207 * [ 7: 4] - next state timeout 10208 * [15: 8] - reason code 10209 * [31:16] - lanes 10210 */ 10211 success = frame & 0x1; 10212 state = (frame >> 1) & 0x7; 10213 reason = (frame >> 8) & 0xff; 10214 lanes = (frame >> 16) & 0xffff; 10215 10216 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n", 10217 prefix, frame); 10218 dd_dev_err(dd, " last reported state state: %s (0x%x)\n", 10219 state_completed_string(state), state); 10220 dd_dev_err(dd, " state successfully completed: %s\n", 10221 success ? "yes" : "no"); 10222 dd_dev_err(dd, " fail reason 0x%x: %s\n", 10223 reason, state_complete_reason_code_string(ppd, reason)); 10224 dd_dev_err(dd, " passing lane mask: 0x%x", lanes); 10225 } 10226 10227 /* 10228 * Read the last state complete frames and explain them. This routine 10229 * expects to be called if the link went down during link negotiation 10230 * and initialization (LNI). That is, anywhere between polling and link up. 10231 */ 10232 static void check_lni_states(struct hfi1_pportdata *ppd) 10233 { 10234 u32 last_local_state; 10235 u32 last_remote_state; 10236 10237 read_last_local_state(ppd->dd, &last_local_state); 10238 read_last_remote_state(ppd->dd, &last_remote_state); 10239 10240 /* 10241 * Don't report anything if there is nothing to report. A value of 10242 * 0 means the link was taken down while polling and there was no 10243 * training in-process. 10244 */ 10245 if (last_local_state == 0 && last_remote_state == 0) 10246 return; 10247 10248 decode_state_complete(ppd, last_local_state, "transmitted"); 10249 decode_state_complete(ppd, last_remote_state, "received"); 10250 } 10251 10252 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */ 10253 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms) 10254 { 10255 u64 reg; 10256 unsigned long timeout; 10257 10258 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */ 10259 timeout = jiffies + msecs_to_jiffies(wait_ms); 10260 while (1) { 10261 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); 10262 if (reg) 10263 break; 10264 if (time_after(jiffies, timeout)) { 10265 dd_dev_err(dd, 10266 "timeout waiting for LINK_TRANSFER_ACTIVE\n"); 10267 return -ETIMEDOUT; 10268 } 10269 udelay(2); 10270 } 10271 return 0; 10272 } 10273 10274 /* called when the logical link state is not down as it should be */ 10275 static void force_logical_link_state_down(struct hfi1_pportdata *ppd) 10276 { 10277 struct hfi1_devdata *dd = ppd->dd; 10278 10279 /* 10280 * Bring link up in LCB loopback 10281 */ 10282 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10283 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 10284 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 10285 10286 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 10287 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); 10288 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 10289 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); 10290 10291 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 10292 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); 10293 udelay(3); 10294 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); 10295 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 10296 10297 wait_link_transfer_active(dd, 100); 10298 10299 /* 10300 * Bring the link down again. 10301 */ 10302 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10303 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); 10304 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); 10305 10306 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n"); 10307 } 10308 10309 /* 10310 * Helper for set_link_state(). Do not call except from that routine. 10311 * Expects ppd->hls_mutex to be held. 10312 * 10313 * @rem_reason value to be sent to the neighbor 10314 * 10315 * LinkDownReasons only set if transition succeeds. 10316 */ 10317 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason) 10318 { 10319 struct hfi1_devdata *dd = ppd->dd; 10320 u32 previous_state; 10321 int offline_state_ret; 10322 int ret; 10323 10324 update_lcb_cache(dd); 10325 10326 previous_state = ppd->host_link_state; 10327 ppd->host_link_state = HLS_GOING_OFFLINE; 10328 10329 /* start offline transition */ 10330 ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE); 10331 10332 if (ret != HCMD_SUCCESS) { 10333 dd_dev_err(dd, 10334 "Failed to transition to Offline link state, return %d\n", 10335 ret); 10336 return -EINVAL; 10337 } 10338 if (ppd->offline_disabled_reason == 10339 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)) 10340 ppd->offline_disabled_reason = 10341 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 10342 10343 offline_state_ret = wait_phys_link_offline_substates(ppd, 10000); 10344 if (offline_state_ret < 0) 10345 return offline_state_ret; 10346 10347 /* Disabling AOC transmitters */ 10348 if (ppd->port_type == PORT_TYPE_QSFP && 10349 ppd->qsfp_info.limiting_active && 10350 qsfp_mod_present(ppd)) { 10351 int ret; 10352 10353 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT); 10354 if (ret == 0) { 10355 set_qsfp_tx(ppd, 0); 10356 release_chip_resource(dd, qsfp_resource(dd)); 10357 } else { 10358 /* not fatal, but should warn */ 10359 dd_dev_err(dd, 10360 "Unable to acquire lock to turn off QSFP TX\n"); 10361 } 10362 } 10363 10364 /* 10365 * Wait for the offline.Quiet transition if it hasn't happened yet. It 10366 * can take a while for the link to go down. 10367 */ 10368 if (offline_state_ret != PLS_OFFLINE_QUIET) { 10369 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000); 10370 if (ret < 0) 10371 return ret; 10372 } 10373 10374 /* 10375 * Now in charge of LCB - must be after the physical state is 10376 * offline.quiet and before host_link_state is changed. 10377 */ 10378 set_host_lcb_access(dd); 10379 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 10380 10381 /* make sure the logical state is also down */ 10382 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000); 10383 if (ret) 10384 force_logical_link_state_down(ppd); 10385 10386 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */ 10387 update_statusp(ppd, IB_PORT_DOWN); 10388 10389 /* 10390 * The LNI has a mandatory wait time after the physical state 10391 * moves to Offline.Quiet. The wait time may be different 10392 * depending on how the link went down. The 8051 firmware 10393 * will observe the needed wait time and only move to ready 10394 * when that is completed. The largest of the quiet timeouts 10395 * is 6s, so wait that long and then at least 0.5s more for 10396 * other transitions, and another 0.5s for a buffer. 10397 */ 10398 ret = wait_fm_ready(dd, 7000); 10399 if (ret) { 10400 dd_dev_err(dd, 10401 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n"); 10402 /* state is really offline, so make it so */ 10403 ppd->host_link_state = HLS_DN_OFFLINE; 10404 return ret; 10405 } 10406 10407 /* 10408 * The state is now offline and the 8051 is ready to accept host 10409 * requests. 10410 * - change our state 10411 * - notify others if we were previously in a linkup state 10412 */ 10413 ppd->host_link_state = HLS_DN_OFFLINE; 10414 if (previous_state & HLS_UP) { 10415 /* went down while link was up */ 10416 handle_linkup_change(dd, 0); 10417 } else if (previous_state 10418 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 10419 /* went down while attempting link up */ 10420 check_lni_states(ppd); 10421 10422 /* The QSFP doesn't need to be reset on LNI failure */ 10423 ppd->qsfp_info.reset_needed = 0; 10424 } 10425 10426 /* the active link width (downgrade) is 0 on link down */ 10427 ppd->link_width_active = 0; 10428 ppd->link_width_downgrade_tx_active = 0; 10429 ppd->link_width_downgrade_rx_active = 0; 10430 ppd->current_egress_rate = 0; 10431 return 0; 10432 } 10433 10434 /* return the link state name */ 10435 static const char *link_state_name(u32 state) 10436 { 10437 const char *name; 10438 int n = ilog2(state); 10439 static const char * const names[] = { 10440 [__HLS_UP_INIT_BP] = "INIT", 10441 [__HLS_UP_ARMED_BP] = "ARMED", 10442 [__HLS_UP_ACTIVE_BP] = "ACTIVE", 10443 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF", 10444 [__HLS_DN_POLL_BP] = "POLL", 10445 [__HLS_DN_DISABLE_BP] = "DISABLE", 10446 [__HLS_DN_OFFLINE_BP] = "OFFLINE", 10447 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP", 10448 [__HLS_GOING_UP_BP] = "GOING_UP", 10449 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE", 10450 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN" 10451 }; 10452 10453 name = n < ARRAY_SIZE(names) ? names[n] : NULL; 10454 return name ? name : "unknown"; 10455 } 10456 10457 /* return the link state reason name */ 10458 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state) 10459 { 10460 if (state == HLS_UP_INIT) { 10461 switch (ppd->linkinit_reason) { 10462 case OPA_LINKINIT_REASON_LINKUP: 10463 return "(LINKUP)"; 10464 case OPA_LINKINIT_REASON_FLAPPING: 10465 return "(FLAPPING)"; 10466 case OPA_LINKINIT_OUTSIDE_POLICY: 10467 return "(OUTSIDE_POLICY)"; 10468 case OPA_LINKINIT_QUARANTINED: 10469 return "(QUARANTINED)"; 10470 case OPA_LINKINIT_INSUFIC_CAPABILITY: 10471 return "(INSUFIC_CAPABILITY)"; 10472 default: 10473 break; 10474 } 10475 } 10476 return ""; 10477 } 10478 10479 /* 10480 * driver_pstate - convert the driver's notion of a port's 10481 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*). 10482 * Return -1 (converted to a u32) to indicate error. 10483 */ 10484 u32 driver_pstate(struct hfi1_pportdata *ppd) 10485 { 10486 switch (ppd->host_link_state) { 10487 case HLS_UP_INIT: 10488 case HLS_UP_ARMED: 10489 case HLS_UP_ACTIVE: 10490 return IB_PORTPHYSSTATE_LINKUP; 10491 case HLS_DN_POLL: 10492 return IB_PORTPHYSSTATE_POLLING; 10493 case HLS_DN_DISABLE: 10494 return IB_PORTPHYSSTATE_DISABLED; 10495 case HLS_DN_OFFLINE: 10496 return OPA_PORTPHYSSTATE_OFFLINE; 10497 case HLS_VERIFY_CAP: 10498 return IB_PORTPHYSSTATE_POLLING; 10499 case HLS_GOING_UP: 10500 return IB_PORTPHYSSTATE_POLLING; 10501 case HLS_GOING_OFFLINE: 10502 return OPA_PORTPHYSSTATE_OFFLINE; 10503 case HLS_LINK_COOLDOWN: 10504 return OPA_PORTPHYSSTATE_OFFLINE; 10505 case HLS_DN_DOWNDEF: 10506 default: 10507 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10508 ppd->host_link_state); 10509 return -1; 10510 } 10511 } 10512 10513 /* 10514 * driver_lstate - convert the driver's notion of a port's 10515 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1 10516 * (converted to a u32) to indicate error. 10517 */ 10518 u32 driver_lstate(struct hfi1_pportdata *ppd) 10519 { 10520 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN)) 10521 return IB_PORT_DOWN; 10522 10523 switch (ppd->host_link_state & HLS_UP) { 10524 case HLS_UP_INIT: 10525 return IB_PORT_INIT; 10526 case HLS_UP_ARMED: 10527 return IB_PORT_ARMED; 10528 case HLS_UP_ACTIVE: 10529 return IB_PORT_ACTIVE; 10530 default: 10531 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10532 ppd->host_link_state); 10533 return -1; 10534 } 10535 } 10536 10537 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 10538 u8 neigh_reason, u8 rem_reason) 10539 { 10540 if (ppd->local_link_down_reason.latest == 0 && 10541 ppd->neigh_link_down_reason.latest == 0) { 10542 ppd->local_link_down_reason.latest = lcl_reason; 10543 ppd->neigh_link_down_reason.latest = neigh_reason; 10544 ppd->remote_link_down_reason = rem_reason; 10545 } 10546 } 10547 10548 /* 10549 * Verify if BCT for data VLs is non-zero. 10550 */ 10551 static inline bool data_vls_operational(struct hfi1_pportdata *ppd) 10552 { 10553 return !!ppd->actual_vls_operational; 10554 } 10555 10556 /* 10557 * Change the physical and/or logical link state. 10558 * 10559 * Do not call this routine while inside an interrupt. It contains 10560 * calls to routines that can take multiple seconds to finish. 10561 * 10562 * Returns 0 on success, -errno on failure. 10563 */ 10564 int set_link_state(struct hfi1_pportdata *ppd, u32 state) 10565 { 10566 struct hfi1_devdata *dd = ppd->dd; 10567 struct ib_event event = {.device = NULL}; 10568 int ret1, ret = 0; 10569 int orig_new_state, poll_bounce; 10570 10571 mutex_lock(&ppd->hls_lock); 10572 10573 orig_new_state = state; 10574 if (state == HLS_DN_DOWNDEF) 10575 state = HLS_DEFAULT; 10576 10577 /* interpret poll -> poll as a link bounce */ 10578 poll_bounce = ppd->host_link_state == HLS_DN_POLL && 10579 state == HLS_DN_POLL; 10580 10581 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__, 10582 link_state_name(ppd->host_link_state), 10583 link_state_name(orig_new_state), 10584 poll_bounce ? "(bounce) " : "", 10585 link_state_reason_name(ppd, state)); 10586 10587 /* 10588 * If we're going to a (HLS_*) link state that implies the logical 10589 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then 10590 * reset is_sm_config_started to 0. 10591 */ 10592 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE))) 10593 ppd->is_sm_config_started = 0; 10594 10595 /* 10596 * Do nothing if the states match. Let a poll to poll link bounce 10597 * go through. 10598 */ 10599 if (ppd->host_link_state == state && !poll_bounce) 10600 goto done; 10601 10602 switch (state) { 10603 case HLS_UP_INIT: 10604 if (ppd->host_link_state == HLS_DN_POLL && 10605 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) { 10606 /* 10607 * Quick link up jumps from polling to here. 10608 * 10609 * Whether in normal or loopback mode, the 10610 * simulator jumps from polling to link up. 10611 * Accept that here. 10612 */ 10613 /* OK */ 10614 } else if (ppd->host_link_state != HLS_GOING_UP) { 10615 goto unexpected; 10616 } 10617 10618 /* 10619 * Wait for Link_Up physical state. 10620 * Physical and Logical states should already be 10621 * be transitioned to LinkUp and LinkInit respectively. 10622 */ 10623 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000); 10624 if (ret) { 10625 dd_dev_err(dd, 10626 "%s: physical state did not change to LINK-UP\n", 10627 __func__); 10628 break; 10629 } 10630 10631 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000); 10632 if (ret) { 10633 dd_dev_err(dd, 10634 "%s: logical state did not change to INIT\n", 10635 __func__); 10636 break; 10637 } 10638 10639 /* clear old transient LINKINIT_REASON code */ 10640 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR) 10641 ppd->linkinit_reason = 10642 OPA_LINKINIT_REASON_LINKUP; 10643 10644 /* enable the port */ 10645 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 10646 10647 handle_linkup_change(dd, 1); 10648 10649 /* 10650 * After link up, a new link width will have been set. 10651 * Update the xmit counters with regards to the new 10652 * link width. 10653 */ 10654 update_xmit_counters(ppd, ppd->link_width_active); 10655 10656 ppd->host_link_state = HLS_UP_INIT; 10657 update_statusp(ppd, IB_PORT_INIT); 10658 break; 10659 case HLS_UP_ARMED: 10660 if (ppd->host_link_state != HLS_UP_INIT) 10661 goto unexpected; 10662 10663 if (!data_vls_operational(ppd)) { 10664 dd_dev_err(dd, 10665 "%s: data VLs not operational\n", __func__); 10666 ret = -EINVAL; 10667 break; 10668 } 10669 10670 set_logical_state(dd, LSTATE_ARMED); 10671 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000); 10672 if (ret) { 10673 dd_dev_err(dd, 10674 "%s: logical state did not change to ARMED\n", 10675 __func__); 10676 break; 10677 } 10678 ppd->host_link_state = HLS_UP_ARMED; 10679 update_statusp(ppd, IB_PORT_ARMED); 10680 /* 10681 * The simulator does not currently implement SMA messages, 10682 * so neighbor_normal is not set. Set it here when we first 10683 * move to Armed. 10684 */ 10685 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 10686 ppd->neighbor_normal = 1; 10687 break; 10688 case HLS_UP_ACTIVE: 10689 if (ppd->host_link_state != HLS_UP_ARMED) 10690 goto unexpected; 10691 10692 set_logical_state(dd, LSTATE_ACTIVE); 10693 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000); 10694 if (ret) { 10695 dd_dev_err(dd, 10696 "%s: logical state did not change to ACTIVE\n", 10697 __func__); 10698 } else { 10699 /* tell all engines to go running */ 10700 sdma_all_running(dd); 10701 ppd->host_link_state = HLS_UP_ACTIVE; 10702 update_statusp(ppd, IB_PORT_ACTIVE); 10703 10704 /* Signal the IB layer that the port has went active */ 10705 event.device = &dd->verbs_dev.rdi.ibdev; 10706 event.element.port_num = ppd->port; 10707 event.event = IB_EVENT_PORT_ACTIVE; 10708 } 10709 break; 10710 case HLS_DN_POLL: 10711 if ((ppd->host_link_state == HLS_DN_DISABLE || 10712 ppd->host_link_state == HLS_DN_OFFLINE) && 10713 dd->dc_shutdown) 10714 dc_start(dd); 10715 /* Hand LED control to the DC */ 10716 write_csr(dd, DCC_CFG_LED_CNTRL, 0); 10717 10718 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10719 u8 tmp = ppd->link_enabled; 10720 10721 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10722 if (ret) { 10723 ppd->link_enabled = tmp; 10724 break; 10725 } 10726 ppd->remote_link_down_reason = 0; 10727 10728 if (ppd->driver_link_ready) 10729 ppd->link_enabled = 1; 10730 } 10731 10732 set_all_slowpath(ppd->dd); 10733 ret = set_local_link_attributes(ppd); 10734 if (ret) 10735 break; 10736 10737 ppd->port_error_action = 0; 10738 ppd->host_link_state = HLS_DN_POLL; 10739 10740 if (quick_linkup) { 10741 /* quick linkup does not go into polling */ 10742 ret = do_quick_linkup(dd); 10743 } else { 10744 ret1 = set_physical_link_state(dd, PLS_POLLING); 10745 if (ret1 != HCMD_SUCCESS) { 10746 dd_dev_err(dd, 10747 "Failed to transition to Polling link state, return 0x%x\n", 10748 ret1); 10749 ret = -EINVAL; 10750 } 10751 } 10752 ppd->offline_disabled_reason = 10753 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE); 10754 /* 10755 * If an error occurred above, go back to offline. The 10756 * caller may reschedule another attempt. 10757 */ 10758 if (ret) 10759 goto_offline(ppd, 0); 10760 else 10761 log_physical_state(ppd, PLS_POLLING); 10762 break; 10763 case HLS_DN_DISABLE: 10764 /* link is disabled */ 10765 ppd->link_enabled = 0; 10766 10767 /* allow any state to transition to disabled */ 10768 10769 /* must transition to offline first */ 10770 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10771 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10772 if (ret) 10773 break; 10774 ppd->remote_link_down_reason = 0; 10775 } 10776 10777 if (!dd->dc_shutdown) { 10778 ret1 = set_physical_link_state(dd, PLS_DISABLED); 10779 if (ret1 != HCMD_SUCCESS) { 10780 dd_dev_err(dd, 10781 "Failed to transition to Disabled link state, return 0x%x\n", 10782 ret1); 10783 ret = -EINVAL; 10784 break; 10785 } 10786 ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000); 10787 if (ret) { 10788 dd_dev_err(dd, 10789 "%s: physical state did not change to DISABLED\n", 10790 __func__); 10791 break; 10792 } 10793 dc_shutdown(dd); 10794 } 10795 ppd->host_link_state = HLS_DN_DISABLE; 10796 break; 10797 case HLS_DN_OFFLINE: 10798 if (ppd->host_link_state == HLS_DN_DISABLE) 10799 dc_start(dd); 10800 10801 /* allow any state to transition to offline */ 10802 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10803 if (!ret) 10804 ppd->remote_link_down_reason = 0; 10805 break; 10806 case HLS_VERIFY_CAP: 10807 if (ppd->host_link_state != HLS_DN_POLL) 10808 goto unexpected; 10809 ppd->host_link_state = HLS_VERIFY_CAP; 10810 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP); 10811 break; 10812 case HLS_GOING_UP: 10813 if (ppd->host_link_state != HLS_VERIFY_CAP) 10814 goto unexpected; 10815 10816 ret1 = set_physical_link_state(dd, PLS_LINKUP); 10817 if (ret1 != HCMD_SUCCESS) { 10818 dd_dev_err(dd, 10819 "Failed to transition to link up state, return 0x%x\n", 10820 ret1); 10821 ret = -EINVAL; 10822 break; 10823 } 10824 ppd->host_link_state = HLS_GOING_UP; 10825 break; 10826 10827 case HLS_GOING_OFFLINE: /* transient within goto_offline() */ 10828 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */ 10829 default: 10830 dd_dev_info(dd, "%s: state 0x%x: not supported\n", 10831 __func__, state); 10832 ret = -EINVAL; 10833 break; 10834 } 10835 10836 goto done; 10837 10838 unexpected: 10839 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n", 10840 __func__, link_state_name(ppd->host_link_state), 10841 link_state_name(state)); 10842 ret = -EINVAL; 10843 10844 done: 10845 mutex_unlock(&ppd->hls_lock); 10846 10847 if (event.device) 10848 ib_dispatch_event(&event); 10849 10850 return ret; 10851 } 10852 10853 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val) 10854 { 10855 u64 reg; 10856 int ret = 0; 10857 10858 switch (which) { 10859 case HFI1_IB_CFG_LIDLMC: 10860 set_lidlmc(ppd); 10861 break; 10862 case HFI1_IB_CFG_VL_HIGH_LIMIT: 10863 /* 10864 * The VL Arbitrator high limit is sent in units of 4k 10865 * bytes, while HFI stores it in units of 64 bytes. 10866 */ 10867 val *= 4096 / 64; 10868 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) 10869 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT; 10870 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); 10871 break; 10872 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 10873 /* HFI only supports POLL as the default link down state */ 10874 if (val != HLS_DN_POLL) 10875 ret = -EINVAL; 10876 break; 10877 case HFI1_IB_CFG_OP_VLS: 10878 if (ppd->vls_operational != val) { 10879 ppd->vls_operational = val; 10880 if (!ppd->port) 10881 ret = -EINVAL; 10882 } 10883 break; 10884 /* 10885 * For link width, link width downgrade, and speed enable, always AND 10886 * the setting with what is actually supported. This has two benefits. 10887 * First, enabled can't have unsupported values, no matter what the 10888 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean 10889 * "fill in with your supported value" have all the bits in the 10890 * field set, so simply ANDing with supported has the desired result. 10891 */ 10892 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */ 10893 ppd->link_width_enabled = val & ppd->link_width_supported; 10894 break; 10895 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */ 10896 ppd->link_width_downgrade_enabled = 10897 val & ppd->link_width_downgrade_supported; 10898 break; 10899 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 10900 ppd->link_speed_enabled = val & ppd->link_speed_supported; 10901 break; 10902 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 10903 /* 10904 * HFI does not follow IB specs, save this value 10905 * so we can report it, if asked. 10906 */ 10907 ppd->overrun_threshold = val; 10908 break; 10909 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 10910 /* 10911 * HFI does not follow IB specs, save this value 10912 * so we can report it, if asked. 10913 */ 10914 ppd->phy_error_threshold = val; 10915 break; 10916 10917 case HFI1_IB_CFG_MTU: 10918 set_send_length(ppd); 10919 break; 10920 10921 case HFI1_IB_CFG_PKEYS: 10922 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 10923 set_partition_keys(ppd); 10924 break; 10925 10926 default: 10927 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 10928 dd_dev_info(ppd->dd, 10929 "%s: which %s, val 0x%x: not implemented\n", 10930 __func__, ib_cfg_name(which), val); 10931 break; 10932 } 10933 return ret; 10934 } 10935 10936 /* begin functions related to vl arbitration table caching */ 10937 static void init_vl_arb_caches(struct hfi1_pportdata *ppd) 10938 { 10939 int i; 10940 10941 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 10942 VL_ARB_LOW_PRIO_TABLE_SIZE); 10943 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 10944 VL_ARB_HIGH_PRIO_TABLE_SIZE); 10945 10946 /* 10947 * Note that we always return values directly from the 10948 * 'vl_arb_cache' (and do no CSR reads) in response to a 10949 * 'Get(VLArbTable)'. This is obviously correct after a 10950 * 'Set(VLArbTable)', since the cache will then be up to 10951 * date. But it's also correct prior to any 'Set(VLArbTable)' 10952 * since then both the cache, and the relevant h/w registers 10953 * will be zeroed. 10954 */ 10955 10956 for (i = 0; i < MAX_PRIO_TABLE; i++) 10957 spin_lock_init(&ppd->vl_arb_cache[i].lock); 10958 } 10959 10960 /* 10961 * vl_arb_lock_cache 10962 * 10963 * All other vl_arb_* functions should be called only after locking 10964 * the cache. 10965 */ 10966 static inline struct vl_arb_cache * 10967 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx) 10968 { 10969 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE) 10970 return NULL; 10971 spin_lock(&ppd->vl_arb_cache[idx].lock); 10972 return &ppd->vl_arb_cache[idx]; 10973 } 10974 10975 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx) 10976 { 10977 spin_unlock(&ppd->vl_arb_cache[idx].lock); 10978 } 10979 10980 static void vl_arb_get_cache(struct vl_arb_cache *cache, 10981 struct ib_vl_weight_elem *vl) 10982 { 10983 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl)); 10984 } 10985 10986 static void vl_arb_set_cache(struct vl_arb_cache *cache, 10987 struct ib_vl_weight_elem *vl) 10988 { 10989 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 10990 } 10991 10992 static int vl_arb_match_cache(struct vl_arb_cache *cache, 10993 struct ib_vl_weight_elem *vl) 10994 { 10995 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 10996 } 10997 10998 /* end functions related to vl arbitration table caching */ 10999 11000 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target, 11001 u32 size, struct ib_vl_weight_elem *vl) 11002 { 11003 struct hfi1_devdata *dd = ppd->dd; 11004 u64 reg; 11005 unsigned int i, is_up = 0; 11006 int drain, ret = 0; 11007 11008 mutex_lock(&ppd->hls_lock); 11009 11010 if (ppd->host_link_state & HLS_UP) 11011 is_up = 1; 11012 11013 drain = !is_ax(dd) && is_up; 11014 11015 if (drain) 11016 /* 11017 * Before adjusting VL arbitration weights, empty per-VL 11018 * FIFOs, otherwise a packet whose VL weight is being 11019 * set to 0 could get stuck in a FIFO with no chance to 11020 * egress. 11021 */ 11022 ret = stop_drain_data_vls(dd); 11023 11024 if (ret) { 11025 dd_dev_err( 11026 dd, 11027 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n", 11028 __func__); 11029 goto err; 11030 } 11031 11032 for (i = 0; i < size; i++, vl++) { 11033 /* 11034 * NOTE: The low priority shift and mask are used here, but 11035 * they are the same for both the low and high registers. 11036 */ 11037 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK) 11038 << SEND_LOW_PRIORITY_LIST_VL_SHIFT) 11039 | (((u64)vl->weight 11040 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK) 11041 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT); 11042 write_csr(dd, target + (i * 8), reg); 11043 } 11044 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE); 11045 11046 if (drain) 11047 open_fill_data_vls(dd); /* reopen all VLs */ 11048 11049 err: 11050 mutex_unlock(&ppd->hls_lock); 11051 11052 return ret; 11053 } 11054 11055 /* 11056 * Read one credit merge VL register. 11057 */ 11058 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr, 11059 struct vl_limit *vll) 11060 { 11061 u64 reg = read_csr(dd, csr); 11062 11063 vll->dedicated = cpu_to_be16( 11064 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT) 11065 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK); 11066 vll->shared = cpu_to_be16( 11067 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT) 11068 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK); 11069 } 11070 11071 /* 11072 * Read the current credit merge limits. 11073 */ 11074 static int get_buffer_control(struct hfi1_devdata *dd, 11075 struct buffer_control *bc, u16 *overall_limit) 11076 { 11077 u64 reg; 11078 int i; 11079 11080 /* not all entries are filled in */ 11081 memset(bc, 0, sizeof(*bc)); 11082 11083 /* OPA and HFI have a 1-1 mapping */ 11084 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11085 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]); 11086 11087 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */ 11088 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]); 11089 11090 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11091 bc->overall_shared_limit = cpu_to_be16( 11092 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) 11093 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK); 11094 if (overall_limit) 11095 *overall_limit = (reg 11096 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) 11097 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK; 11098 return sizeof(struct buffer_control); 11099 } 11100 11101 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11102 { 11103 u64 reg; 11104 int i; 11105 11106 /* each register contains 16 SC->VLnt mappings, 4 bits each */ 11107 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); 11108 for (i = 0; i < sizeof(u64); i++) { 11109 u8 byte = *(((u8 *)®) + i); 11110 11111 dp->vlnt[2 * i] = byte & 0xf; 11112 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4; 11113 } 11114 11115 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); 11116 for (i = 0; i < sizeof(u64); i++) { 11117 u8 byte = *(((u8 *)®) + i); 11118 11119 dp->vlnt[16 + (2 * i)] = byte & 0xf; 11120 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4; 11121 } 11122 return sizeof(struct sc2vlnt); 11123 } 11124 11125 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems, 11126 struct ib_vl_weight_elem *vl) 11127 { 11128 unsigned int i; 11129 11130 for (i = 0; i < nelems; i++, vl++) { 11131 vl->vl = 0xf; 11132 vl->weight = 0; 11133 } 11134 } 11135 11136 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11137 { 11138 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, 11139 DC_SC_VL_VAL(15_0, 11140 0, dp->vlnt[0] & 0xf, 11141 1, dp->vlnt[1] & 0xf, 11142 2, dp->vlnt[2] & 0xf, 11143 3, dp->vlnt[3] & 0xf, 11144 4, dp->vlnt[4] & 0xf, 11145 5, dp->vlnt[5] & 0xf, 11146 6, dp->vlnt[6] & 0xf, 11147 7, dp->vlnt[7] & 0xf, 11148 8, dp->vlnt[8] & 0xf, 11149 9, dp->vlnt[9] & 0xf, 11150 10, dp->vlnt[10] & 0xf, 11151 11, dp->vlnt[11] & 0xf, 11152 12, dp->vlnt[12] & 0xf, 11153 13, dp->vlnt[13] & 0xf, 11154 14, dp->vlnt[14] & 0xf, 11155 15, dp->vlnt[15] & 0xf)); 11156 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, 11157 DC_SC_VL_VAL(31_16, 11158 16, dp->vlnt[16] & 0xf, 11159 17, dp->vlnt[17] & 0xf, 11160 18, dp->vlnt[18] & 0xf, 11161 19, dp->vlnt[19] & 0xf, 11162 20, dp->vlnt[20] & 0xf, 11163 21, dp->vlnt[21] & 0xf, 11164 22, dp->vlnt[22] & 0xf, 11165 23, dp->vlnt[23] & 0xf, 11166 24, dp->vlnt[24] & 0xf, 11167 25, dp->vlnt[25] & 0xf, 11168 26, dp->vlnt[26] & 0xf, 11169 27, dp->vlnt[27] & 0xf, 11170 28, dp->vlnt[28] & 0xf, 11171 29, dp->vlnt[29] & 0xf, 11172 30, dp->vlnt[30] & 0xf, 11173 31, dp->vlnt[31] & 0xf)); 11174 } 11175 11176 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what, 11177 u16 limit) 11178 { 11179 if (limit != 0) 11180 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n", 11181 what, (int)limit, idx); 11182 } 11183 11184 /* change only the shared limit portion of SendCmGLobalCredit */ 11185 static void set_global_shared(struct hfi1_devdata *dd, u16 limit) 11186 { 11187 u64 reg; 11188 11189 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11190 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK; 11191 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT; 11192 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11193 } 11194 11195 /* change only the total credit limit portion of SendCmGLobalCredit */ 11196 static void set_global_limit(struct hfi1_devdata *dd, u16 limit) 11197 { 11198 u64 reg; 11199 11200 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11201 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK; 11202 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 11203 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11204 } 11205 11206 /* set the given per-VL shared limit */ 11207 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit) 11208 { 11209 u64 reg; 11210 u32 addr; 11211 11212 if (vl < TXE_NUM_DATA_VL) 11213 addr = SEND_CM_CREDIT_VL + (8 * vl); 11214 else 11215 addr = SEND_CM_CREDIT_VL15; 11216 11217 reg = read_csr(dd, addr); 11218 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK; 11219 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT; 11220 write_csr(dd, addr, reg); 11221 } 11222 11223 /* set the given per-VL dedicated limit */ 11224 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit) 11225 { 11226 u64 reg; 11227 u32 addr; 11228 11229 if (vl < TXE_NUM_DATA_VL) 11230 addr = SEND_CM_CREDIT_VL + (8 * vl); 11231 else 11232 addr = SEND_CM_CREDIT_VL15; 11233 11234 reg = read_csr(dd, addr); 11235 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK; 11236 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT; 11237 write_csr(dd, addr, reg); 11238 } 11239 11240 /* spin until the given per-VL status mask bits clear */ 11241 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask, 11242 const char *which) 11243 { 11244 unsigned long timeout; 11245 u64 reg; 11246 11247 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT); 11248 while (1) { 11249 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; 11250 11251 if (reg == 0) 11252 return; /* success */ 11253 if (time_after(jiffies, timeout)) 11254 break; /* timed out */ 11255 udelay(1); 11256 } 11257 11258 dd_dev_err(dd, 11259 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n", 11260 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); 11261 /* 11262 * If this occurs, it is likely there was a credit loss on the link. 11263 * The only recovery from that is a link bounce. 11264 */ 11265 dd_dev_err(dd, 11266 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n"); 11267 } 11268 11269 /* 11270 * The number of credits on the VLs may be changed while everything 11271 * is "live", but the following algorithm must be followed due to 11272 * how the hardware is actually implemented. In particular, 11273 * Return_Credit_Status[] is the only correct status check. 11274 * 11275 * if (reducing Global_Shared_Credit_Limit or any shared limit changing) 11276 * set Global_Shared_Credit_Limit = 0 11277 * use_all_vl = 1 11278 * mask0 = all VLs that are changing either dedicated or shared limits 11279 * set Shared_Limit[mask0] = 0 11280 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0 11281 * if (changing any dedicated limit) 11282 * mask1 = all VLs that are lowering dedicated limits 11283 * lower Dedicated_Limit[mask1] 11284 * spin until Return_Credit_Status[mask1] == 0 11285 * raise Dedicated_Limits 11286 * raise Shared_Limits 11287 * raise Global_Shared_Credit_Limit 11288 * 11289 * lower = if the new limit is lower, set the limit to the new value 11290 * raise = if the new limit is higher than the current value (may be changed 11291 * earlier in the algorithm), set the new limit to the new value 11292 */ 11293 int set_buffer_control(struct hfi1_pportdata *ppd, 11294 struct buffer_control *new_bc) 11295 { 11296 struct hfi1_devdata *dd = ppd->dd; 11297 u64 changing_mask, ld_mask, stat_mask; 11298 int change_count; 11299 int i, use_all_mask; 11300 int this_shared_changing; 11301 int vl_count = 0, ret; 11302 /* 11303 * A0: add the variable any_shared_limit_changing below and in the 11304 * algorithm above. If removing A0 support, it can be removed. 11305 */ 11306 int any_shared_limit_changing; 11307 struct buffer_control cur_bc; 11308 u8 changing[OPA_MAX_VLS]; 11309 u8 lowering_dedicated[OPA_MAX_VLS]; 11310 u16 cur_total; 11311 u32 new_total = 0; 11312 const u64 all_mask = 11313 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK 11314 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK 11315 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK 11316 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK 11317 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK 11318 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK 11319 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK 11320 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK 11321 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK; 11322 11323 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15) 11324 #define NUM_USABLE_VLS 16 /* look at VL15 and less */ 11325 11326 /* find the new total credits, do sanity check on unused VLs */ 11327 for (i = 0; i < OPA_MAX_VLS; i++) { 11328 if (valid_vl(i)) { 11329 new_total += be16_to_cpu(new_bc->vl[i].dedicated); 11330 continue; 11331 } 11332 nonzero_msg(dd, i, "dedicated", 11333 be16_to_cpu(new_bc->vl[i].dedicated)); 11334 nonzero_msg(dd, i, "shared", 11335 be16_to_cpu(new_bc->vl[i].shared)); 11336 new_bc->vl[i].dedicated = 0; 11337 new_bc->vl[i].shared = 0; 11338 } 11339 new_total += be16_to_cpu(new_bc->overall_shared_limit); 11340 11341 /* fetch the current values */ 11342 get_buffer_control(dd, &cur_bc, &cur_total); 11343 11344 /* 11345 * Create the masks we will use. 11346 */ 11347 memset(changing, 0, sizeof(changing)); 11348 memset(lowering_dedicated, 0, sizeof(lowering_dedicated)); 11349 /* 11350 * NOTE: Assumes that the individual VL bits are adjacent and in 11351 * increasing order 11352 */ 11353 stat_mask = 11354 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK; 11355 changing_mask = 0; 11356 ld_mask = 0; 11357 change_count = 0; 11358 any_shared_limit_changing = 0; 11359 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) { 11360 if (!valid_vl(i)) 11361 continue; 11362 this_shared_changing = new_bc->vl[i].shared 11363 != cur_bc.vl[i].shared; 11364 if (this_shared_changing) 11365 any_shared_limit_changing = 1; 11366 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated || 11367 this_shared_changing) { 11368 changing[i] = 1; 11369 changing_mask |= stat_mask; 11370 change_count++; 11371 } 11372 if (be16_to_cpu(new_bc->vl[i].dedicated) < 11373 be16_to_cpu(cur_bc.vl[i].dedicated)) { 11374 lowering_dedicated[i] = 1; 11375 ld_mask |= stat_mask; 11376 } 11377 } 11378 11379 /* bracket the credit change with a total adjustment */ 11380 if (new_total > cur_total) 11381 set_global_limit(dd, new_total); 11382 11383 /* 11384 * Start the credit change algorithm. 11385 */ 11386 use_all_mask = 0; 11387 if ((be16_to_cpu(new_bc->overall_shared_limit) < 11388 be16_to_cpu(cur_bc.overall_shared_limit)) || 11389 (is_ax(dd) && any_shared_limit_changing)) { 11390 set_global_shared(dd, 0); 11391 cur_bc.overall_shared_limit = 0; 11392 use_all_mask = 1; 11393 } 11394 11395 for (i = 0; i < NUM_USABLE_VLS; i++) { 11396 if (!valid_vl(i)) 11397 continue; 11398 11399 if (changing[i]) { 11400 set_vl_shared(dd, i, 0); 11401 cur_bc.vl[i].shared = 0; 11402 } 11403 } 11404 11405 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask, 11406 "shared"); 11407 11408 if (change_count > 0) { 11409 for (i = 0; i < NUM_USABLE_VLS; i++) { 11410 if (!valid_vl(i)) 11411 continue; 11412 11413 if (lowering_dedicated[i]) { 11414 set_vl_dedicated(dd, i, 11415 be16_to_cpu(new_bc-> 11416 vl[i].dedicated)); 11417 cur_bc.vl[i].dedicated = 11418 new_bc->vl[i].dedicated; 11419 } 11420 } 11421 11422 wait_for_vl_status_clear(dd, ld_mask, "dedicated"); 11423 11424 /* now raise all dedicated that are going up */ 11425 for (i = 0; i < NUM_USABLE_VLS; i++) { 11426 if (!valid_vl(i)) 11427 continue; 11428 11429 if (be16_to_cpu(new_bc->vl[i].dedicated) > 11430 be16_to_cpu(cur_bc.vl[i].dedicated)) 11431 set_vl_dedicated(dd, i, 11432 be16_to_cpu(new_bc-> 11433 vl[i].dedicated)); 11434 } 11435 } 11436 11437 /* next raise all shared that are going up */ 11438 for (i = 0; i < NUM_USABLE_VLS; i++) { 11439 if (!valid_vl(i)) 11440 continue; 11441 11442 if (be16_to_cpu(new_bc->vl[i].shared) > 11443 be16_to_cpu(cur_bc.vl[i].shared)) 11444 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared)); 11445 } 11446 11447 /* finally raise the global shared */ 11448 if (be16_to_cpu(new_bc->overall_shared_limit) > 11449 be16_to_cpu(cur_bc.overall_shared_limit)) 11450 set_global_shared(dd, 11451 be16_to_cpu(new_bc->overall_shared_limit)); 11452 11453 /* bracket the credit change with a total adjustment */ 11454 if (new_total < cur_total) 11455 set_global_limit(dd, new_total); 11456 11457 /* 11458 * Determine the actual number of operational VLS using the number of 11459 * dedicated and shared credits for each VL. 11460 */ 11461 if (change_count > 0) { 11462 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11463 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 || 11464 be16_to_cpu(new_bc->vl[i].shared) > 0) 11465 vl_count++; 11466 ppd->actual_vls_operational = vl_count; 11467 ret = sdma_map_init(dd, ppd->port - 1, vl_count ? 11468 ppd->actual_vls_operational : 11469 ppd->vls_operational, 11470 NULL); 11471 if (ret == 0) 11472 ret = pio_map_init(dd, ppd->port - 1, vl_count ? 11473 ppd->actual_vls_operational : 11474 ppd->vls_operational, NULL); 11475 if (ret) 11476 return ret; 11477 } 11478 return 0; 11479 } 11480 11481 /* 11482 * Read the given fabric manager table. Return the size of the 11483 * table (in bytes) on success, and a negative error code on 11484 * failure. 11485 */ 11486 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t) 11487 11488 { 11489 int size; 11490 struct vl_arb_cache *vlc; 11491 11492 switch (which) { 11493 case FM_TBL_VL_HIGH_ARB: 11494 size = 256; 11495 /* 11496 * OPA specifies 128 elements (of 2 bytes each), though 11497 * HFI supports only 16 elements in h/w. 11498 */ 11499 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11500 vl_arb_get_cache(vlc, t); 11501 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11502 break; 11503 case FM_TBL_VL_LOW_ARB: 11504 size = 256; 11505 /* 11506 * OPA specifies 128 elements (of 2 bytes each), though 11507 * HFI supports only 16 elements in h/w. 11508 */ 11509 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11510 vl_arb_get_cache(vlc, t); 11511 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11512 break; 11513 case FM_TBL_BUFFER_CONTROL: 11514 size = get_buffer_control(ppd->dd, t, NULL); 11515 break; 11516 case FM_TBL_SC2VLNT: 11517 size = get_sc2vlnt(ppd->dd, t); 11518 break; 11519 case FM_TBL_VL_PREEMPT_ELEMS: 11520 size = 256; 11521 /* OPA specifies 128 elements, of 2 bytes each */ 11522 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t); 11523 break; 11524 case FM_TBL_VL_PREEMPT_MATRIX: 11525 size = 256; 11526 /* 11527 * OPA specifies that this is the same size as the VL 11528 * arbitration tables (i.e., 256 bytes). 11529 */ 11530 break; 11531 default: 11532 return -EINVAL; 11533 } 11534 return size; 11535 } 11536 11537 /* 11538 * Write the given fabric manager table. 11539 */ 11540 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t) 11541 { 11542 int ret = 0; 11543 struct vl_arb_cache *vlc; 11544 11545 switch (which) { 11546 case FM_TBL_VL_HIGH_ARB: 11547 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11548 if (vl_arb_match_cache(vlc, t)) { 11549 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11550 break; 11551 } 11552 vl_arb_set_cache(vlc, t); 11553 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11554 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST, 11555 VL_ARB_HIGH_PRIO_TABLE_SIZE, t); 11556 break; 11557 case FM_TBL_VL_LOW_ARB: 11558 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11559 if (vl_arb_match_cache(vlc, t)) { 11560 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11561 break; 11562 } 11563 vl_arb_set_cache(vlc, t); 11564 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11565 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST, 11566 VL_ARB_LOW_PRIO_TABLE_SIZE, t); 11567 break; 11568 case FM_TBL_BUFFER_CONTROL: 11569 ret = set_buffer_control(ppd, t); 11570 break; 11571 case FM_TBL_SC2VLNT: 11572 set_sc2vlnt(ppd->dd, t); 11573 break; 11574 default: 11575 ret = -EINVAL; 11576 } 11577 return ret; 11578 } 11579 11580 /* 11581 * Disable all data VLs. 11582 * 11583 * Return 0 if disabled, non-zero if the VLs cannot be disabled. 11584 */ 11585 static int disable_data_vls(struct hfi1_devdata *dd) 11586 { 11587 if (is_ax(dd)) 11588 return 1; 11589 11590 pio_send_control(dd, PSC_DATA_VL_DISABLE); 11591 11592 return 0; 11593 } 11594 11595 /* 11596 * open_fill_data_vls() - the counterpart to stop_drain_data_vls(). 11597 * Just re-enables all data VLs (the "fill" part happens 11598 * automatically - the name was chosen for symmetry with 11599 * stop_drain_data_vls()). 11600 * 11601 * Return 0 if successful, non-zero if the VLs cannot be enabled. 11602 */ 11603 int open_fill_data_vls(struct hfi1_devdata *dd) 11604 { 11605 if (is_ax(dd)) 11606 return 1; 11607 11608 pio_send_control(dd, PSC_DATA_VL_ENABLE); 11609 11610 return 0; 11611 } 11612 11613 /* 11614 * drain_data_vls() - assumes that disable_data_vls() has been called, 11615 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA 11616 * engines to drop to 0. 11617 */ 11618 static void drain_data_vls(struct hfi1_devdata *dd) 11619 { 11620 sc_wait(dd); 11621 sdma_wait(dd); 11622 pause_for_credit_return(dd); 11623 } 11624 11625 /* 11626 * stop_drain_data_vls() - disable, then drain all per-VL fifos. 11627 * 11628 * Use open_fill_data_vls() to resume using data VLs. This pair is 11629 * meant to be used like this: 11630 * 11631 * stop_drain_data_vls(dd); 11632 * // do things with per-VL resources 11633 * open_fill_data_vls(dd); 11634 */ 11635 int stop_drain_data_vls(struct hfi1_devdata *dd) 11636 { 11637 int ret; 11638 11639 ret = disable_data_vls(dd); 11640 if (ret == 0) 11641 drain_data_vls(dd); 11642 11643 return ret; 11644 } 11645 11646 /* 11647 * Convert a nanosecond time to a cclock count. No matter how slow 11648 * the cclock, a non-zero ns will always have a non-zero result. 11649 */ 11650 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns) 11651 { 11652 u32 cclocks; 11653 11654 if (dd->icode == ICODE_FPGA_EMULATION) 11655 cclocks = (ns * 1000) / FPGA_CCLOCK_PS; 11656 else /* simulation pretends to be ASIC */ 11657 cclocks = (ns * 1000) / ASIC_CCLOCK_PS; 11658 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */ 11659 cclocks = 1; 11660 return cclocks; 11661 } 11662 11663 /* 11664 * Convert a cclock count to nanoseconds. Not matter how slow 11665 * the cclock, a non-zero cclocks will always have a non-zero result. 11666 */ 11667 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks) 11668 { 11669 u32 ns; 11670 11671 if (dd->icode == ICODE_FPGA_EMULATION) 11672 ns = (cclocks * FPGA_CCLOCK_PS) / 1000; 11673 else /* simulation pretends to be ASIC */ 11674 ns = (cclocks * ASIC_CCLOCK_PS) / 1000; 11675 if (cclocks && !ns) 11676 ns = 1; 11677 return ns; 11678 } 11679 11680 /* 11681 * Dynamically adjust the receive interrupt timeout for a context based on 11682 * incoming packet rate. 11683 * 11684 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero. 11685 */ 11686 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts) 11687 { 11688 struct hfi1_devdata *dd = rcd->dd; 11689 u32 timeout = rcd->rcvavail_timeout; 11690 11691 /* 11692 * This algorithm doubles or halves the timeout depending on whether 11693 * the number of packets received in this interrupt were less than or 11694 * greater equal the interrupt count. 11695 * 11696 * The calculations below do not allow a steady state to be achieved. 11697 * Only at the endpoints it is possible to have an unchanging 11698 * timeout. 11699 */ 11700 if (npkts < rcv_intr_count) { 11701 /* 11702 * Not enough packets arrived before the timeout, adjust 11703 * timeout downward. 11704 */ 11705 if (timeout < 2) /* already at minimum? */ 11706 return; 11707 timeout >>= 1; 11708 } else { 11709 /* 11710 * More than enough packets arrived before the timeout, adjust 11711 * timeout upward. 11712 */ 11713 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */ 11714 return; 11715 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr); 11716 } 11717 11718 rcd->rcvavail_timeout = timeout; 11719 /* 11720 * timeout cannot be larger than rcv_intr_timeout_csr which has already 11721 * been verified to be in range 11722 */ 11723 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT, 11724 (u64)timeout << 11725 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11726 } 11727 11728 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, 11729 u32 intr_adjust, u32 npkts) 11730 { 11731 struct hfi1_devdata *dd = rcd->dd; 11732 u64 reg; 11733 u32 ctxt = rcd->ctxt; 11734 11735 /* 11736 * Need to write timeout register before updating RcvHdrHead to ensure 11737 * that a new value is used when the HW decides to restart counting. 11738 */ 11739 if (intr_adjust) 11740 adjust_rcv_timeout(rcd, npkts); 11741 if (updegr) { 11742 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK) 11743 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT; 11744 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg); 11745 } 11746 mmiowb(); 11747 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) | 11748 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK) 11749 << RCV_HDR_HEAD_HEAD_SHIFT); 11750 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11751 mmiowb(); 11752 } 11753 11754 u32 hdrqempty(struct hfi1_ctxtdata *rcd) 11755 { 11756 u32 head, tail; 11757 11758 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD) 11759 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT; 11760 11761 if (rcd->rcvhdrtail_kvaddr) 11762 tail = get_rcvhdrtail(rcd); 11763 else 11764 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 11765 11766 return head == tail; 11767 } 11768 11769 /* 11770 * Context Control and Receive Array encoding for buffer size: 11771 * 0x0 invalid 11772 * 0x1 4 KB 11773 * 0x2 8 KB 11774 * 0x3 16 KB 11775 * 0x4 32 KB 11776 * 0x5 64 KB 11777 * 0x6 128 KB 11778 * 0x7 256 KB 11779 * 0x8 512 KB (Receive Array only) 11780 * 0x9 1 MB (Receive Array only) 11781 * 0xa 2 MB (Receive Array only) 11782 * 11783 * 0xB-0xF - reserved (Receive Array only) 11784 * 11785 * 11786 * This routine assumes that the value has already been sanity checked. 11787 */ 11788 static u32 encoded_size(u32 size) 11789 { 11790 switch (size) { 11791 case 4 * 1024: return 0x1; 11792 case 8 * 1024: return 0x2; 11793 case 16 * 1024: return 0x3; 11794 case 32 * 1024: return 0x4; 11795 case 64 * 1024: return 0x5; 11796 case 128 * 1024: return 0x6; 11797 case 256 * 1024: return 0x7; 11798 case 512 * 1024: return 0x8; 11799 case 1 * 1024 * 1024: return 0x9; 11800 case 2 * 1024 * 1024: return 0xa; 11801 } 11802 return 0x1; /* if invalid, go with the minimum size */ 11803 } 11804 11805 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, 11806 struct hfi1_ctxtdata *rcd) 11807 { 11808 u64 rcvctrl, reg; 11809 int did_enable = 0; 11810 u16 ctxt; 11811 11812 if (!rcd) 11813 return; 11814 11815 ctxt = rcd->ctxt; 11816 11817 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op); 11818 11819 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL); 11820 /* if the context already enabled, don't do the extra steps */ 11821 if ((op & HFI1_RCVCTRL_CTXT_ENB) && 11822 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) { 11823 /* reset the tail and hdr addresses, and sequence count */ 11824 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR, 11825 rcd->rcvhdrq_dma); 11826 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) 11827 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11828 rcd->rcvhdrqtailaddr_dma); 11829 rcd->seq_cnt = 1; 11830 11831 /* reset the cached receive header queue head value */ 11832 rcd->head = 0; 11833 11834 /* 11835 * Zero the receive header queue so we don't get false 11836 * positives when checking the sequence number. The 11837 * sequence numbers could land exactly on the same spot. 11838 * E.g. a rcd restart before the receive header wrapped. 11839 */ 11840 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size); 11841 11842 /* starting timeout */ 11843 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr; 11844 11845 /* enable the context */ 11846 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK; 11847 11848 /* clean the egr buffer size first */ 11849 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 11850 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size) 11851 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK) 11852 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT; 11853 11854 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */ 11855 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0); 11856 did_enable = 1; 11857 11858 /* zero RcvEgrIndexHead */ 11859 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0); 11860 11861 /* set eager count and base index */ 11862 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT) 11863 & RCV_EGR_CTRL_EGR_CNT_MASK) 11864 << RCV_EGR_CTRL_EGR_CNT_SHIFT) | 11865 (((rcd->eager_base >> RCV_SHIFT) 11866 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK) 11867 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT); 11868 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg); 11869 11870 /* 11871 * Set TID (expected) count and base index. 11872 * rcd->expected_count is set to individual RcvArray entries, 11873 * not pairs, and the CSR takes a pair-count in groups of 11874 * four, so divide by 8. 11875 */ 11876 reg = (((rcd->expected_count >> RCV_SHIFT) 11877 & RCV_TID_CTRL_TID_PAIR_CNT_MASK) 11878 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) | 11879 (((rcd->expected_base >> RCV_SHIFT) 11880 & RCV_TID_CTRL_TID_BASE_INDEX_MASK) 11881 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT); 11882 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg); 11883 if (ctxt == HFI1_CTRL_CTXT) 11884 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); 11885 } 11886 if (op & HFI1_RCVCTRL_CTXT_DIS) { 11887 write_csr(dd, RCV_VL15, 0); 11888 /* 11889 * When receive context is being disabled turn on tail 11890 * update with a dummy tail address and then disable 11891 * receive context. 11892 */ 11893 if (dd->rcvhdrtail_dummy_dma) { 11894 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11895 dd->rcvhdrtail_dummy_dma); 11896 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */ 11897 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11898 } 11899 11900 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK; 11901 } 11902 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB) 11903 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 11904 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS) 11905 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 11906 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma) 11907 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11908 if (op & HFI1_RCVCTRL_TAILUPD_DIS) { 11909 /* See comment on RcvCtxtCtrl.TailUpd above */ 11910 if (!(op & HFI1_RCVCTRL_CTXT_DIS)) 11911 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11912 } 11913 if (op & HFI1_RCVCTRL_TIDFLOW_ENB) 11914 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 11915 if (op & HFI1_RCVCTRL_TIDFLOW_DIS) 11916 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 11917 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) { 11918 /* 11919 * In one-packet-per-eager mode, the size comes from 11920 * the RcvArray entry. 11921 */ 11922 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 11923 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 11924 } 11925 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS) 11926 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 11927 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB) 11928 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 11929 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS) 11930 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 11931 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB) 11932 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 11933 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS) 11934 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 11935 rcd->rcvctrl = rcvctrl; 11936 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl); 11937 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl); 11938 11939 /* work around sticky RcvCtxtStatus.BlockedRHQFull */ 11940 if (did_enable && 11941 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) { 11942 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 11943 if (reg != 0) { 11944 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n", 11945 ctxt, reg); 11946 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 11947 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10); 11948 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00); 11949 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 11950 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 11951 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n", 11952 ctxt, reg, reg == 0 ? "not" : "still"); 11953 } 11954 } 11955 11956 if (did_enable) { 11957 /* 11958 * The interrupt timeout and count must be set after 11959 * the context is enabled to take effect. 11960 */ 11961 /* set interrupt timeout */ 11962 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT, 11963 (u64)rcd->rcvavail_timeout << 11964 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11965 11966 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */ 11967 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT; 11968 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11969 } 11970 11971 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS)) 11972 /* 11973 * If the context has been disabled and the Tail Update has 11974 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address 11975 * so it doesn't contain an address that is invalid. 11976 */ 11977 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11978 dd->rcvhdrtail_dummy_dma); 11979 } 11980 11981 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp) 11982 { 11983 int ret; 11984 u64 val = 0; 11985 11986 if (namep) { 11987 ret = dd->cntrnameslen; 11988 *namep = dd->cntrnames; 11989 } else { 11990 const struct cntr_entry *entry; 11991 int i, j; 11992 11993 ret = (dd->ndevcntrs) * sizeof(u64); 11994 11995 /* Get the start of the block of counters */ 11996 *cntrp = dd->cntrs; 11997 11998 /* 11999 * Now go and fill in each counter in the block. 12000 */ 12001 for (i = 0; i < DEV_CNTR_LAST; i++) { 12002 entry = &dev_cntrs[i]; 12003 hfi1_cdbg(CNTR, "reading %s", entry->name); 12004 if (entry->flags & CNTR_DISABLED) { 12005 /* Nothing */ 12006 hfi1_cdbg(CNTR, "\tDisabled\n"); 12007 } else { 12008 if (entry->flags & CNTR_VL) { 12009 hfi1_cdbg(CNTR, "\tPer VL\n"); 12010 for (j = 0; j < C_VL_COUNT; j++) { 12011 val = entry->rw_cntr(entry, 12012 dd, j, 12013 CNTR_MODE_R, 12014 0); 12015 hfi1_cdbg( 12016 CNTR, 12017 "\t\tRead 0x%llx for %d\n", 12018 val, j); 12019 dd->cntrs[entry->offset + j] = 12020 val; 12021 } 12022 } else if (entry->flags & CNTR_SDMA) { 12023 hfi1_cdbg(CNTR, 12024 "\t Per SDMA Engine\n"); 12025 for (j = 0; j < dd->chip_sdma_engines; 12026 j++) { 12027 val = 12028 entry->rw_cntr(entry, dd, j, 12029 CNTR_MODE_R, 0); 12030 hfi1_cdbg(CNTR, 12031 "\t\tRead 0x%llx for %d\n", 12032 val, j); 12033 dd->cntrs[entry->offset + j] = 12034 val; 12035 } 12036 } else { 12037 val = entry->rw_cntr(entry, dd, 12038 CNTR_INVALID_VL, 12039 CNTR_MODE_R, 0); 12040 dd->cntrs[entry->offset] = val; 12041 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12042 } 12043 } 12044 } 12045 } 12046 return ret; 12047 } 12048 12049 /* 12050 * Used by sysfs to create files for hfi stats to read 12051 */ 12052 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp) 12053 { 12054 int ret; 12055 u64 val = 0; 12056 12057 if (namep) { 12058 ret = ppd->dd->portcntrnameslen; 12059 *namep = ppd->dd->portcntrnames; 12060 } else { 12061 const struct cntr_entry *entry; 12062 int i, j; 12063 12064 ret = ppd->dd->nportcntrs * sizeof(u64); 12065 *cntrp = ppd->cntrs; 12066 12067 for (i = 0; i < PORT_CNTR_LAST; i++) { 12068 entry = &port_cntrs[i]; 12069 hfi1_cdbg(CNTR, "reading %s", entry->name); 12070 if (entry->flags & CNTR_DISABLED) { 12071 /* Nothing */ 12072 hfi1_cdbg(CNTR, "\tDisabled\n"); 12073 continue; 12074 } 12075 12076 if (entry->flags & CNTR_VL) { 12077 hfi1_cdbg(CNTR, "\tPer VL"); 12078 for (j = 0; j < C_VL_COUNT; j++) { 12079 val = entry->rw_cntr(entry, ppd, j, 12080 CNTR_MODE_R, 12081 0); 12082 hfi1_cdbg( 12083 CNTR, 12084 "\t\tRead 0x%llx for %d", 12085 val, j); 12086 ppd->cntrs[entry->offset + j] = val; 12087 } 12088 } else { 12089 val = entry->rw_cntr(entry, ppd, 12090 CNTR_INVALID_VL, 12091 CNTR_MODE_R, 12092 0); 12093 ppd->cntrs[entry->offset] = val; 12094 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12095 } 12096 } 12097 } 12098 return ret; 12099 } 12100 12101 static void free_cntrs(struct hfi1_devdata *dd) 12102 { 12103 struct hfi1_pportdata *ppd; 12104 int i; 12105 12106 if (dd->synth_stats_timer.function) 12107 del_timer_sync(&dd->synth_stats_timer); 12108 ppd = (struct hfi1_pportdata *)(dd + 1); 12109 for (i = 0; i < dd->num_pports; i++, ppd++) { 12110 kfree(ppd->cntrs); 12111 kfree(ppd->scntrs); 12112 free_percpu(ppd->ibport_data.rvp.rc_acks); 12113 free_percpu(ppd->ibport_data.rvp.rc_qacks); 12114 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp); 12115 ppd->cntrs = NULL; 12116 ppd->scntrs = NULL; 12117 ppd->ibport_data.rvp.rc_acks = NULL; 12118 ppd->ibport_data.rvp.rc_qacks = NULL; 12119 ppd->ibport_data.rvp.rc_delayed_comp = NULL; 12120 } 12121 kfree(dd->portcntrnames); 12122 dd->portcntrnames = NULL; 12123 kfree(dd->cntrs); 12124 dd->cntrs = NULL; 12125 kfree(dd->scntrs); 12126 dd->scntrs = NULL; 12127 kfree(dd->cntrnames); 12128 dd->cntrnames = NULL; 12129 if (dd->update_cntr_wq) { 12130 destroy_workqueue(dd->update_cntr_wq); 12131 dd->update_cntr_wq = NULL; 12132 } 12133 } 12134 12135 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry, 12136 u64 *psval, void *context, int vl) 12137 { 12138 u64 val; 12139 u64 sval = *psval; 12140 12141 if (entry->flags & CNTR_DISABLED) { 12142 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12143 return 0; 12144 } 12145 12146 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12147 12148 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0); 12149 12150 /* If its a synthetic counter there is more work we need to do */ 12151 if (entry->flags & CNTR_SYNTH) { 12152 if (sval == CNTR_MAX) { 12153 /* No need to read already saturated */ 12154 return CNTR_MAX; 12155 } 12156 12157 if (entry->flags & CNTR_32BIT) { 12158 /* 32bit counters can wrap multiple times */ 12159 u64 upper = sval >> 32; 12160 u64 lower = (sval << 32) >> 32; 12161 12162 if (lower > val) { /* hw wrapped */ 12163 if (upper == CNTR_32BIT_MAX) 12164 val = CNTR_MAX; 12165 else 12166 upper++; 12167 } 12168 12169 if (val != CNTR_MAX) 12170 val = (upper << 32) | val; 12171 12172 } else { 12173 /* If we rolled we are saturated */ 12174 if ((val < sval) || (val > CNTR_MAX)) 12175 val = CNTR_MAX; 12176 } 12177 } 12178 12179 *psval = val; 12180 12181 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12182 12183 return val; 12184 } 12185 12186 static u64 write_dev_port_cntr(struct hfi1_devdata *dd, 12187 struct cntr_entry *entry, 12188 u64 *psval, void *context, int vl, u64 data) 12189 { 12190 u64 val; 12191 12192 if (entry->flags & CNTR_DISABLED) { 12193 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12194 return 0; 12195 } 12196 12197 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12198 12199 if (entry->flags & CNTR_SYNTH) { 12200 *psval = data; 12201 if (entry->flags & CNTR_32BIT) { 12202 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12203 (data << 32) >> 32); 12204 val = data; /* return the full 64bit value */ 12205 } else { 12206 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12207 data); 12208 } 12209 } else { 12210 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data); 12211 } 12212 12213 *psval = val; 12214 12215 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12216 12217 return val; 12218 } 12219 12220 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl) 12221 { 12222 struct cntr_entry *entry; 12223 u64 *sval; 12224 12225 entry = &dev_cntrs[index]; 12226 sval = dd->scntrs + entry->offset; 12227 12228 if (vl != CNTR_INVALID_VL) 12229 sval += vl; 12230 12231 return read_dev_port_cntr(dd, entry, sval, dd, vl); 12232 } 12233 12234 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data) 12235 { 12236 struct cntr_entry *entry; 12237 u64 *sval; 12238 12239 entry = &dev_cntrs[index]; 12240 sval = dd->scntrs + entry->offset; 12241 12242 if (vl != CNTR_INVALID_VL) 12243 sval += vl; 12244 12245 return write_dev_port_cntr(dd, entry, sval, dd, vl, data); 12246 } 12247 12248 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl) 12249 { 12250 struct cntr_entry *entry; 12251 u64 *sval; 12252 12253 entry = &port_cntrs[index]; 12254 sval = ppd->scntrs + entry->offset; 12255 12256 if (vl != CNTR_INVALID_VL) 12257 sval += vl; 12258 12259 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12260 (index <= C_RCV_HDR_OVF_LAST)) { 12261 /* We do not want to bother for disabled contexts */ 12262 return 0; 12263 } 12264 12265 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl); 12266 } 12267 12268 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data) 12269 { 12270 struct cntr_entry *entry; 12271 u64 *sval; 12272 12273 entry = &port_cntrs[index]; 12274 sval = ppd->scntrs + entry->offset; 12275 12276 if (vl != CNTR_INVALID_VL) 12277 sval += vl; 12278 12279 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12280 (index <= C_RCV_HDR_OVF_LAST)) { 12281 /* We do not want to bother for disabled contexts */ 12282 return 0; 12283 } 12284 12285 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data); 12286 } 12287 12288 static void do_update_synth_timer(struct work_struct *work) 12289 { 12290 u64 cur_tx; 12291 u64 cur_rx; 12292 u64 total_flits; 12293 u8 update = 0; 12294 int i, j, vl; 12295 struct hfi1_pportdata *ppd; 12296 struct cntr_entry *entry; 12297 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata, 12298 update_cntr_work); 12299 12300 /* 12301 * Rather than keep beating on the CSRs pick a minimal set that we can 12302 * check to watch for potential roll over. We can do this by looking at 12303 * the number of flits sent/recv. If the total flits exceeds 32bits then 12304 * we have to iterate all the counters and update. 12305 */ 12306 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12307 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12308 12309 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12310 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12311 12312 hfi1_cdbg( 12313 CNTR, 12314 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n", 12315 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx); 12316 12317 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) { 12318 /* 12319 * May not be strictly necessary to update but it won't hurt and 12320 * simplifies the logic here. 12321 */ 12322 update = 1; 12323 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating", 12324 dd->unit); 12325 } else { 12326 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx); 12327 hfi1_cdbg(CNTR, 12328 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit, 12329 total_flits, (u64)CNTR_32BIT_MAX); 12330 if (total_flits >= CNTR_32BIT_MAX) { 12331 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating", 12332 dd->unit); 12333 update = 1; 12334 } 12335 } 12336 12337 if (update) { 12338 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit); 12339 for (i = 0; i < DEV_CNTR_LAST; i++) { 12340 entry = &dev_cntrs[i]; 12341 if (entry->flags & CNTR_VL) { 12342 for (vl = 0; vl < C_VL_COUNT; vl++) 12343 read_dev_cntr(dd, i, vl); 12344 } else { 12345 read_dev_cntr(dd, i, CNTR_INVALID_VL); 12346 } 12347 } 12348 ppd = (struct hfi1_pportdata *)(dd + 1); 12349 for (i = 0; i < dd->num_pports; i++, ppd++) { 12350 for (j = 0; j < PORT_CNTR_LAST; j++) { 12351 entry = &port_cntrs[j]; 12352 if (entry->flags & CNTR_VL) { 12353 for (vl = 0; vl < C_VL_COUNT; vl++) 12354 read_port_cntr(ppd, j, vl); 12355 } else { 12356 read_port_cntr(ppd, j, CNTR_INVALID_VL); 12357 } 12358 } 12359 } 12360 12361 /* 12362 * We want the value in the register. The goal is to keep track 12363 * of the number of "ticks" not the counter value. In other 12364 * words if the register rolls we want to notice it and go ahead 12365 * and force an update. 12366 */ 12367 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12368 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12369 CNTR_MODE_R, 0); 12370 12371 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12372 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12373 CNTR_MODE_R, 0); 12374 12375 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx", 12376 dd->unit, dd->last_tx, dd->last_rx); 12377 12378 } else { 12379 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit); 12380 } 12381 } 12382 12383 static void update_synth_timer(struct timer_list *t) 12384 { 12385 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer); 12386 12387 queue_work(dd->update_cntr_wq, &dd->update_cntr_work); 12388 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12389 } 12390 12391 #define C_MAX_NAME 16 /* 15 chars + one for /0 */ 12392 static int init_cntrs(struct hfi1_devdata *dd) 12393 { 12394 int i, rcv_ctxts, j; 12395 size_t sz; 12396 char *p; 12397 char name[C_MAX_NAME]; 12398 struct hfi1_pportdata *ppd; 12399 const char *bit_type_32 = ",32"; 12400 const int bit_type_32_sz = strlen(bit_type_32); 12401 12402 /* set up the stats timer; the add_timer is done at the end */ 12403 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0); 12404 12405 /***********************/ 12406 /* per device counters */ 12407 /***********************/ 12408 12409 /* size names and determine how many we have*/ 12410 dd->ndevcntrs = 0; 12411 sz = 0; 12412 12413 for (i = 0; i < DEV_CNTR_LAST; i++) { 12414 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12415 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name); 12416 continue; 12417 } 12418 12419 if (dev_cntrs[i].flags & CNTR_VL) { 12420 dev_cntrs[i].offset = dd->ndevcntrs; 12421 for (j = 0; j < C_VL_COUNT; j++) { 12422 snprintf(name, C_MAX_NAME, "%s%d", 12423 dev_cntrs[i].name, vl_from_idx(j)); 12424 sz += strlen(name); 12425 /* Add ",32" for 32-bit counters */ 12426 if (dev_cntrs[i].flags & CNTR_32BIT) 12427 sz += bit_type_32_sz; 12428 sz++; 12429 dd->ndevcntrs++; 12430 } 12431 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12432 dev_cntrs[i].offset = dd->ndevcntrs; 12433 for (j = 0; j < dd->chip_sdma_engines; j++) { 12434 snprintf(name, C_MAX_NAME, "%s%d", 12435 dev_cntrs[i].name, j); 12436 sz += strlen(name); 12437 /* Add ",32" for 32-bit counters */ 12438 if (dev_cntrs[i].flags & CNTR_32BIT) 12439 sz += bit_type_32_sz; 12440 sz++; 12441 dd->ndevcntrs++; 12442 } 12443 } else { 12444 /* +1 for newline. */ 12445 sz += strlen(dev_cntrs[i].name) + 1; 12446 /* Add ",32" for 32-bit counters */ 12447 if (dev_cntrs[i].flags & CNTR_32BIT) 12448 sz += bit_type_32_sz; 12449 dev_cntrs[i].offset = dd->ndevcntrs; 12450 dd->ndevcntrs++; 12451 } 12452 } 12453 12454 /* allocate space for the counter values */ 12455 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12456 if (!dd->cntrs) 12457 goto bail; 12458 12459 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12460 if (!dd->scntrs) 12461 goto bail; 12462 12463 /* allocate space for the counter names */ 12464 dd->cntrnameslen = sz; 12465 dd->cntrnames = kmalloc(sz, GFP_KERNEL); 12466 if (!dd->cntrnames) 12467 goto bail; 12468 12469 /* fill in the names */ 12470 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) { 12471 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12472 /* Nothing */ 12473 } else if (dev_cntrs[i].flags & CNTR_VL) { 12474 for (j = 0; j < C_VL_COUNT; j++) { 12475 snprintf(name, C_MAX_NAME, "%s%d", 12476 dev_cntrs[i].name, 12477 vl_from_idx(j)); 12478 memcpy(p, name, strlen(name)); 12479 p += strlen(name); 12480 12481 /* Counter is 32 bits */ 12482 if (dev_cntrs[i].flags & CNTR_32BIT) { 12483 memcpy(p, bit_type_32, bit_type_32_sz); 12484 p += bit_type_32_sz; 12485 } 12486 12487 *p++ = '\n'; 12488 } 12489 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12490 for (j = 0; j < dd->chip_sdma_engines; j++) { 12491 snprintf(name, C_MAX_NAME, "%s%d", 12492 dev_cntrs[i].name, j); 12493 memcpy(p, name, strlen(name)); 12494 p += strlen(name); 12495 12496 /* Counter is 32 bits */ 12497 if (dev_cntrs[i].flags & CNTR_32BIT) { 12498 memcpy(p, bit_type_32, bit_type_32_sz); 12499 p += bit_type_32_sz; 12500 } 12501 12502 *p++ = '\n'; 12503 } 12504 } else { 12505 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name)); 12506 p += strlen(dev_cntrs[i].name); 12507 12508 /* Counter is 32 bits */ 12509 if (dev_cntrs[i].flags & CNTR_32BIT) { 12510 memcpy(p, bit_type_32, bit_type_32_sz); 12511 p += bit_type_32_sz; 12512 } 12513 12514 *p++ = '\n'; 12515 } 12516 } 12517 12518 /*********************/ 12519 /* per port counters */ 12520 /*********************/ 12521 12522 /* 12523 * Go through the counters for the overflows and disable the ones we 12524 * don't need. This varies based on platform so we need to do it 12525 * dynamically here. 12526 */ 12527 rcv_ctxts = dd->num_rcv_contexts; 12528 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts; 12529 i <= C_RCV_HDR_OVF_LAST; i++) { 12530 port_cntrs[i].flags |= CNTR_DISABLED; 12531 } 12532 12533 /* size port counter names and determine how many we have*/ 12534 sz = 0; 12535 dd->nportcntrs = 0; 12536 for (i = 0; i < PORT_CNTR_LAST; i++) { 12537 if (port_cntrs[i].flags & CNTR_DISABLED) { 12538 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name); 12539 continue; 12540 } 12541 12542 if (port_cntrs[i].flags & CNTR_VL) { 12543 port_cntrs[i].offset = dd->nportcntrs; 12544 for (j = 0; j < C_VL_COUNT; j++) { 12545 snprintf(name, C_MAX_NAME, "%s%d", 12546 port_cntrs[i].name, vl_from_idx(j)); 12547 sz += strlen(name); 12548 /* Add ",32" for 32-bit counters */ 12549 if (port_cntrs[i].flags & CNTR_32BIT) 12550 sz += bit_type_32_sz; 12551 sz++; 12552 dd->nportcntrs++; 12553 } 12554 } else { 12555 /* +1 for newline */ 12556 sz += strlen(port_cntrs[i].name) + 1; 12557 /* Add ",32" for 32-bit counters */ 12558 if (port_cntrs[i].flags & CNTR_32BIT) 12559 sz += bit_type_32_sz; 12560 port_cntrs[i].offset = dd->nportcntrs; 12561 dd->nportcntrs++; 12562 } 12563 } 12564 12565 /* allocate space for the counter names */ 12566 dd->portcntrnameslen = sz; 12567 dd->portcntrnames = kmalloc(sz, GFP_KERNEL); 12568 if (!dd->portcntrnames) 12569 goto bail; 12570 12571 /* fill in port cntr names */ 12572 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) { 12573 if (port_cntrs[i].flags & CNTR_DISABLED) 12574 continue; 12575 12576 if (port_cntrs[i].flags & CNTR_VL) { 12577 for (j = 0; j < C_VL_COUNT; j++) { 12578 snprintf(name, C_MAX_NAME, "%s%d", 12579 port_cntrs[i].name, vl_from_idx(j)); 12580 memcpy(p, name, strlen(name)); 12581 p += strlen(name); 12582 12583 /* Counter is 32 bits */ 12584 if (port_cntrs[i].flags & CNTR_32BIT) { 12585 memcpy(p, bit_type_32, bit_type_32_sz); 12586 p += bit_type_32_sz; 12587 } 12588 12589 *p++ = '\n'; 12590 } 12591 } else { 12592 memcpy(p, port_cntrs[i].name, 12593 strlen(port_cntrs[i].name)); 12594 p += strlen(port_cntrs[i].name); 12595 12596 /* Counter is 32 bits */ 12597 if (port_cntrs[i].flags & CNTR_32BIT) { 12598 memcpy(p, bit_type_32, bit_type_32_sz); 12599 p += bit_type_32_sz; 12600 } 12601 12602 *p++ = '\n'; 12603 } 12604 } 12605 12606 /* allocate per port storage for counter values */ 12607 ppd = (struct hfi1_pportdata *)(dd + 1); 12608 for (i = 0; i < dd->num_pports; i++, ppd++) { 12609 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12610 if (!ppd->cntrs) 12611 goto bail; 12612 12613 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12614 if (!ppd->scntrs) 12615 goto bail; 12616 } 12617 12618 /* CPU counters need to be allocated and zeroed */ 12619 if (init_cpu_counters(dd)) 12620 goto bail; 12621 12622 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d", 12623 WQ_MEM_RECLAIM, dd->unit); 12624 if (!dd->update_cntr_wq) 12625 goto bail; 12626 12627 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer); 12628 12629 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12630 return 0; 12631 bail: 12632 free_cntrs(dd); 12633 return -ENOMEM; 12634 } 12635 12636 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate) 12637 { 12638 switch (chip_lstate) { 12639 default: 12640 dd_dev_err(dd, 12641 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n", 12642 chip_lstate); 12643 /* fall through */ 12644 case LSTATE_DOWN: 12645 return IB_PORT_DOWN; 12646 case LSTATE_INIT: 12647 return IB_PORT_INIT; 12648 case LSTATE_ARMED: 12649 return IB_PORT_ARMED; 12650 case LSTATE_ACTIVE: 12651 return IB_PORT_ACTIVE; 12652 } 12653 } 12654 12655 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate) 12656 { 12657 /* look at the HFI meta-states only */ 12658 switch (chip_pstate & 0xf0) { 12659 default: 12660 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n", 12661 chip_pstate); 12662 /* fall through */ 12663 case PLS_DISABLED: 12664 return IB_PORTPHYSSTATE_DISABLED; 12665 case PLS_OFFLINE: 12666 return OPA_PORTPHYSSTATE_OFFLINE; 12667 case PLS_POLLING: 12668 return IB_PORTPHYSSTATE_POLLING; 12669 case PLS_CONFIGPHY: 12670 return IB_PORTPHYSSTATE_TRAINING; 12671 case PLS_LINKUP: 12672 return IB_PORTPHYSSTATE_LINKUP; 12673 case PLS_PHYTEST: 12674 return IB_PORTPHYSSTATE_PHY_TEST; 12675 } 12676 } 12677 12678 /* return the OPA port logical state name */ 12679 const char *opa_lstate_name(u32 lstate) 12680 { 12681 static const char * const port_logical_names[] = { 12682 "PORT_NOP", 12683 "PORT_DOWN", 12684 "PORT_INIT", 12685 "PORT_ARMED", 12686 "PORT_ACTIVE", 12687 "PORT_ACTIVE_DEFER", 12688 }; 12689 if (lstate < ARRAY_SIZE(port_logical_names)) 12690 return port_logical_names[lstate]; 12691 return "unknown"; 12692 } 12693 12694 /* return the OPA port physical state name */ 12695 const char *opa_pstate_name(u32 pstate) 12696 { 12697 static const char * const port_physical_names[] = { 12698 "PHYS_NOP", 12699 "reserved1", 12700 "PHYS_POLL", 12701 "PHYS_DISABLED", 12702 "PHYS_TRAINING", 12703 "PHYS_LINKUP", 12704 "PHYS_LINK_ERR_RECOVER", 12705 "PHYS_PHY_TEST", 12706 "reserved8", 12707 "PHYS_OFFLINE", 12708 "PHYS_GANGED", 12709 "PHYS_TEST", 12710 }; 12711 if (pstate < ARRAY_SIZE(port_physical_names)) 12712 return port_physical_names[pstate]; 12713 return "unknown"; 12714 } 12715 12716 /** 12717 * update_statusp - Update userspace status flag 12718 * @ppd: Port data structure 12719 * @state: port state information 12720 * 12721 * Actual port status is determined by the host_link_state value 12722 * in the ppd. 12723 * 12724 * host_link_state MUST be updated before updating the user space 12725 * statusp. 12726 */ 12727 static void update_statusp(struct hfi1_pportdata *ppd, u32 state) 12728 { 12729 /* 12730 * Set port status flags in the page mapped into userspace 12731 * memory. Do it here to ensure a reliable state - this is 12732 * the only function called by all state handling code. 12733 * Always set the flags due to the fact that the cache value 12734 * might have been changed explicitly outside of this 12735 * function. 12736 */ 12737 if (ppd->statusp) { 12738 switch (state) { 12739 case IB_PORT_DOWN: 12740 case IB_PORT_INIT: 12741 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 12742 HFI1_STATUS_IB_READY); 12743 break; 12744 case IB_PORT_ARMED: 12745 *ppd->statusp |= HFI1_STATUS_IB_CONF; 12746 break; 12747 case IB_PORT_ACTIVE: 12748 *ppd->statusp |= HFI1_STATUS_IB_READY; 12749 break; 12750 } 12751 } 12752 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n", 12753 opa_lstate_name(state), state); 12754 } 12755 12756 /** 12757 * wait_logical_linkstate - wait for an IB link state change to occur 12758 * @ppd: port device 12759 * @state: the state to wait for 12760 * @msecs: the number of milliseconds to wait 12761 * 12762 * Wait up to msecs milliseconds for IB link state change to occur. 12763 * For now, take the easy polling route. 12764 * Returns 0 if state reached, otherwise -ETIMEDOUT. 12765 */ 12766 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 12767 int msecs) 12768 { 12769 unsigned long timeout; 12770 u32 new_state; 12771 12772 timeout = jiffies + msecs_to_jiffies(msecs); 12773 while (1) { 12774 new_state = chip_to_opa_lstate(ppd->dd, 12775 read_logical_state(ppd->dd)); 12776 if (new_state == state) 12777 break; 12778 if (time_after(jiffies, timeout)) { 12779 dd_dev_err(ppd->dd, 12780 "timeout waiting for link state 0x%x\n", 12781 state); 12782 return -ETIMEDOUT; 12783 } 12784 msleep(20); 12785 } 12786 12787 return 0; 12788 } 12789 12790 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state) 12791 { 12792 u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state); 12793 12794 dd_dev_info(ppd->dd, 12795 "physical state changed to %s (0x%x), phy 0x%x\n", 12796 opa_pstate_name(ib_pstate), ib_pstate, state); 12797 } 12798 12799 /* 12800 * Read the physical hardware link state and check if it matches host 12801 * drivers anticipated state. 12802 */ 12803 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state) 12804 { 12805 u32 read_state = read_physical_state(ppd->dd); 12806 12807 if (read_state == state) { 12808 log_state_transition(ppd, state); 12809 } else { 12810 dd_dev_err(ppd->dd, 12811 "anticipated phy link state 0x%x, read 0x%x\n", 12812 state, read_state); 12813 } 12814 } 12815 12816 /* 12817 * wait_physical_linkstate - wait for an physical link state change to occur 12818 * @ppd: port device 12819 * @state: the state to wait for 12820 * @msecs: the number of milliseconds to wait 12821 * 12822 * Wait up to msecs milliseconds for physical link state change to occur. 12823 * Returns 0 if state reached, otherwise -ETIMEDOUT. 12824 */ 12825 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 12826 int msecs) 12827 { 12828 u32 read_state; 12829 unsigned long timeout; 12830 12831 timeout = jiffies + msecs_to_jiffies(msecs); 12832 while (1) { 12833 read_state = read_physical_state(ppd->dd); 12834 if (read_state == state) 12835 break; 12836 if (time_after(jiffies, timeout)) { 12837 dd_dev_err(ppd->dd, 12838 "timeout waiting for phy link state 0x%x\n", 12839 state); 12840 return -ETIMEDOUT; 12841 } 12842 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12843 } 12844 12845 log_state_transition(ppd, state); 12846 return 0; 12847 } 12848 12849 /* 12850 * wait_phys_link_offline_quiet_substates - wait for any offline substate 12851 * @ppd: port device 12852 * @msecs: the number of milliseconds to wait 12853 * 12854 * Wait up to msecs milliseconds for any offline physical link 12855 * state change to occur. 12856 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 12857 */ 12858 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 12859 int msecs) 12860 { 12861 u32 read_state; 12862 unsigned long timeout; 12863 12864 timeout = jiffies + msecs_to_jiffies(msecs); 12865 while (1) { 12866 read_state = read_physical_state(ppd->dd); 12867 if ((read_state & 0xF0) == PLS_OFFLINE) 12868 break; 12869 if (time_after(jiffies, timeout)) { 12870 dd_dev_err(ppd->dd, 12871 "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n", 12872 read_state, msecs); 12873 return -ETIMEDOUT; 12874 } 12875 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12876 } 12877 12878 log_state_transition(ppd, read_state); 12879 return read_state; 12880 } 12881 12882 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ 12883 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 12884 12885 #define SET_STATIC_RATE_CONTROL_SMASK(r) \ 12886 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 12887 12888 void hfi1_init_ctxt(struct send_context *sc) 12889 { 12890 if (sc) { 12891 struct hfi1_devdata *dd = sc->dd; 12892 u64 reg; 12893 u8 set = (sc->type == SC_USER ? 12894 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) : 12895 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)); 12896 reg = read_kctxt_csr(dd, sc->hw_context, 12897 SEND_CTXT_CHECK_ENABLE); 12898 if (set) 12899 CLEAR_STATIC_RATE_CONTROL_SMASK(reg); 12900 else 12901 SET_STATIC_RATE_CONTROL_SMASK(reg); 12902 write_kctxt_csr(dd, sc->hw_context, 12903 SEND_CTXT_CHECK_ENABLE, reg); 12904 } 12905 } 12906 12907 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp) 12908 { 12909 int ret = 0; 12910 u64 reg; 12911 12912 if (dd->icode != ICODE_RTL_SILICON) { 12913 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 12914 dd_dev_info(dd, "%s: tempsense not supported by HW\n", 12915 __func__); 12916 return -EINVAL; 12917 } 12918 reg = read_csr(dd, ASIC_STS_THERM); 12919 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) & 12920 ASIC_STS_THERM_CURR_TEMP_MASK); 12921 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) & 12922 ASIC_STS_THERM_LO_TEMP_MASK); 12923 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) & 12924 ASIC_STS_THERM_HI_TEMP_MASK); 12925 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) & 12926 ASIC_STS_THERM_CRIT_TEMP_MASK); 12927 /* triggers is a 3-bit value - 1 bit per trigger. */ 12928 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7); 12929 12930 return ret; 12931 } 12932 12933 /** 12934 * get_int_mask - get 64 bit int mask 12935 * @dd - the devdata 12936 * @i - the csr (relative to CCE_INT_MASK) 12937 * 12938 * Returns the mask with the urgent interrupt mask 12939 * bit clear for kernel receive contexts. 12940 */ 12941 static u64 get_int_mask(struct hfi1_devdata *dd, u32 i) 12942 { 12943 u64 mask = U64_MAX; /* default to no change */ 12944 12945 if (i >= (IS_RCVURGENT_START / 64) && i < (IS_RCVURGENT_END / 64)) { 12946 int j = (i - (IS_RCVURGENT_START / 64)) * 64; 12947 int k = !j ? IS_RCVURGENT_START % 64 : 0; 12948 12949 if (j) 12950 j -= IS_RCVURGENT_START % 64; 12951 /* j = 0..dd->first_dyn_alloc_ctxt - 1,k = 0..63 */ 12952 for (; j < dd->first_dyn_alloc_ctxt && k < 64; j++, k++) 12953 /* convert to bit in mask and clear */ 12954 mask &= ~BIT_ULL(k); 12955 } 12956 return mask; 12957 } 12958 12959 /* ========================================================================= */ 12960 12961 /* 12962 * Enable/disable chip from delivering interrupts. 12963 */ 12964 void set_intr_state(struct hfi1_devdata *dd, u32 enable) 12965 { 12966 int i; 12967 12968 /* 12969 * In HFI, the mask needs to be 1 to allow interrupts. 12970 */ 12971 if (enable) { 12972 /* enable all interrupts but urgent on kernel contexts */ 12973 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 12974 u64 mask = get_int_mask(dd, i); 12975 12976 write_csr(dd, CCE_INT_MASK + (8 * i), mask); 12977 } 12978 12979 init_qsfp_int(dd); 12980 } else { 12981 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 12982 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 12983 } 12984 } 12985 12986 /* 12987 * Clear all interrupt sources on the chip. 12988 */ 12989 static void clear_all_interrupts(struct hfi1_devdata *dd) 12990 { 12991 int i; 12992 12993 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 12994 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); 12995 12996 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); 12997 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); 12998 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); 12999 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); 13000 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); 13001 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); 13002 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); 13003 for (i = 0; i < dd->chip_send_contexts; i++) 13004 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0); 13005 for (i = 0; i < dd->chip_sdma_engines; i++) 13006 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0); 13007 13008 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); 13009 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); 13010 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); 13011 } 13012 13013 /* Move to pcie.c? */ 13014 static void disable_intx(struct pci_dev *pdev) 13015 { 13016 pci_intx(pdev, 0); 13017 } 13018 13019 /** 13020 * hfi1_clean_up_interrupts() - Free all IRQ resources 13021 * @dd: valid device data data structure 13022 * 13023 * Free the MSI or INTx IRQs and assoicated PCI resources, 13024 * if they have been allocated. 13025 */ 13026 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd) 13027 { 13028 int i; 13029 13030 /* remove irqs - must happen before disabling/turning off */ 13031 if (dd->num_msix_entries) { 13032 /* MSI-X */ 13033 struct hfi1_msix_entry *me = dd->msix_entries; 13034 13035 for (i = 0; i < dd->num_msix_entries; i++, me++) { 13036 if (!me->arg) /* => no irq, no affinity */ 13037 continue; 13038 hfi1_put_irq_affinity(dd, me); 13039 pci_free_irq(dd->pcidev, i, me->arg); 13040 } 13041 13042 /* clean structures */ 13043 kfree(dd->msix_entries); 13044 dd->msix_entries = NULL; 13045 dd->num_msix_entries = 0; 13046 } else { 13047 /* INTx */ 13048 if (dd->requested_intx_irq) { 13049 pci_free_irq(dd->pcidev, 0, dd); 13050 dd->requested_intx_irq = 0; 13051 } 13052 disable_intx(dd->pcidev); 13053 } 13054 13055 pci_free_irq_vectors(dd->pcidev); 13056 } 13057 13058 /* 13059 * Remap the interrupt source from the general handler to the given MSI-X 13060 * interrupt. 13061 */ 13062 static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr) 13063 { 13064 u64 reg; 13065 int m, n; 13066 13067 /* clear from the handled mask of the general interrupt */ 13068 m = isrc / 64; 13069 n = isrc % 64; 13070 if (likely(m < CCE_NUM_INT_CSRS)) { 13071 dd->gi_mask[m] &= ~((u64)1 << n); 13072 } else { 13073 dd_dev_err(dd, "remap interrupt err\n"); 13074 return; 13075 } 13076 13077 /* direct the chip source to the given MSI-X interrupt */ 13078 m = isrc / 8; 13079 n = isrc % 8; 13080 reg = read_csr(dd, CCE_INT_MAP + (8 * m)); 13081 reg &= ~((u64)0xff << (8 * n)); 13082 reg |= ((u64)msix_intr & 0xff) << (8 * n); 13083 write_csr(dd, CCE_INT_MAP + (8 * m), reg); 13084 } 13085 13086 static void remap_sdma_interrupts(struct hfi1_devdata *dd, 13087 int engine, int msix_intr) 13088 { 13089 /* 13090 * SDMA engine interrupt sources grouped by type, rather than 13091 * engine. Per-engine interrupts are as follows: 13092 * SDMA 13093 * SDMAProgress 13094 * SDMAIdle 13095 */ 13096 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine, 13097 msix_intr); 13098 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine, 13099 msix_intr); 13100 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine, 13101 msix_intr); 13102 } 13103 13104 static int request_intx_irq(struct hfi1_devdata *dd) 13105 { 13106 int ret; 13107 13108 ret = pci_request_irq(dd->pcidev, 0, general_interrupt, NULL, dd, 13109 DRIVER_NAME "_%d", dd->unit); 13110 if (ret) 13111 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n", 13112 ret); 13113 else 13114 dd->requested_intx_irq = 1; 13115 return ret; 13116 } 13117 13118 static int request_msix_irqs(struct hfi1_devdata *dd) 13119 { 13120 int first_general, last_general; 13121 int first_sdma, last_sdma; 13122 int first_rx, last_rx; 13123 int i, ret = 0; 13124 13125 /* calculate the ranges we are going to use */ 13126 first_general = 0; 13127 last_general = first_general + 1; 13128 first_sdma = last_general; 13129 last_sdma = first_sdma + dd->num_sdma; 13130 first_rx = last_sdma; 13131 last_rx = first_rx + dd->n_krcv_queues + dd->num_vnic_contexts; 13132 13133 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */ 13134 dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues; 13135 13136 /* 13137 * Sanity check - the code expects all SDMA chip source 13138 * interrupts to be in the same CSR, starting at bit 0. Verify 13139 * that this is true by checking the bit location of the start. 13140 */ 13141 BUILD_BUG_ON(IS_SDMA_START % 64); 13142 13143 for (i = 0; i < dd->num_msix_entries; i++) { 13144 struct hfi1_msix_entry *me = &dd->msix_entries[i]; 13145 const char *err_info; 13146 irq_handler_t handler; 13147 irq_handler_t thread = NULL; 13148 void *arg = NULL; 13149 int idx; 13150 struct hfi1_ctxtdata *rcd = NULL; 13151 struct sdma_engine *sde = NULL; 13152 char name[MAX_NAME_SIZE]; 13153 13154 /* obtain the arguments to pci_request_irq */ 13155 if (first_general <= i && i < last_general) { 13156 idx = i - first_general; 13157 handler = general_interrupt; 13158 arg = dd; 13159 snprintf(name, sizeof(name), 13160 DRIVER_NAME "_%d", dd->unit); 13161 err_info = "general"; 13162 me->type = IRQ_GENERAL; 13163 } else if (first_sdma <= i && i < last_sdma) { 13164 idx = i - first_sdma; 13165 sde = &dd->per_sdma[idx]; 13166 handler = sdma_interrupt; 13167 arg = sde; 13168 snprintf(name, sizeof(name), 13169 DRIVER_NAME "_%d sdma%d", dd->unit, idx); 13170 err_info = "sdma"; 13171 remap_sdma_interrupts(dd, idx, i); 13172 me->type = IRQ_SDMA; 13173 } else if (first_rx <= i && i < last_rx) { 13174 idx = i - first_rx; 13175 rcd = hfi1_rcd_get_by_index_safe(dd, idx); 13176 if (rcd) { 13177 /* 13178 * Set the interrupt register and mask for this 13179 * context's interrupt. 13180 */ 13181 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64; 13182 rcd->imask = ((u64)1) << 13183 ((IS_RCVAVAIL_START + idx) % 64); 13184 handler = receive_context_interrupt; 13185 thread = receive_context_thread; 13186 arg = rcd; 13187 snprintf(name, sizeof(name), 13188 DRIVER_NAME "_%d kctxt%d", 13189 dd->unit, idx); 13190 err_info = "receive context"; 13191 remap_intr(dd, IS_RCVAVAIL_START + idx, i); 13192 me->type = IRQ_RCVCTXT; 13193 rcd->msix_intr = i; 13194 hfi1_rcd_put(rcd); 13195 } 13196 } else { 13197 /* not in our expected range - complain, then 13198 * ignore it 13199 */ 13200 dd_dev_err(dd, 13201 "Unexpected extra MSI-X interrupt %d\n", i); 13202 continue; 13203 } 13204 /* no argument, no interrupt */ 13205 if (!arg) 13206 continue; 13207 /* make sure the name is terminated */ 13208 name[sizeof(name) - 1] = 0; 13209 me->irq = pci_irq_vector(dd->pcidev, i); 13210 ret = pci_request_irq(dd->pcidev, i, handler, thread, arg, 13211 name); 13212 if (ret) { 13213 dd_dev_err(dd, 13214 "unable to allocate %s interrupt, irq %d, index %d, err %d\n", 13215 err_info, me->irq, idx, ret); 13216 return ret; 13217 } 13218 /* 13219 * assign arg after pci_request_irq call, so it will be 13220 * cleaned up 13221 */ 13222 me->arg = arg; 13223 13224 ret = hfi1_get_irq_affinity(dd, me); 13225 if (ret) 13226 dd_dev_err(dd, "unable to pin IRQ %d\n", ret); 13227 } 13228 13229 return ret; 13230 } 13231 13232 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd) 13233 { 13234 int i; 13235 13236 if (!dd->num_msix_entries) { 13237 synchronize_irq(pci_irq_vector(dd->pcidev, 0)); 13238 return; 13239 } 13240 13241 for (i = 0; i < dd->vnic.num_ctxt; i++) { 13242 struct hfi1_ctxtdata *rcd = dd->vnic.ctxt[i]; 13243 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr]; 13244 13245 synchronize_irq(me->irq); 13246 } 13247 } 13248 13249 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd) 13250 { 13251 struct hfi1_devdata *dd = rcd->dd; 13252 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr]; 13253 13254 if (!me->arg) /* => no irq, no affinity */ 13255 return; 13256 13257 hfi1_put_irq_affinity(dd, me); 13258 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg); 13259 13260 me->arg = NULL; 13261 } 13262 13263 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd) 13264 { 13265 struct hfi1_devdata *dd = rcd->dd; 13266 struct hfi1_msix_entry *me; 13267 int idx = rcd->ctxt; 13268 void *arg = rcd; 13269 int ret; 13270 13271 rcd->msix_intr = dd->vnic.msix_idx++; 13272 me = &dd->msix_entries[rcd->msix_intr]; 13273 13274 /* 13275 * Set the interrupt register and mask for this 13276 * context's interrupt. 13277 */ 13278 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64; 13279 rcd->imask = ((u64)1) << 13280 ((IS_RCVAVAIL_START + idx) % 64); 13281 me->type = IRQ_RCVCTXT; 13282 me->irq = pci_irq_vector(dd->pcidev, rcd->msix_intr); 13283 remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr); 13284 13285 ret = pci_request_irq(dd->pcidev, rcd->msix_intr, 13286 receive_context_interrupt, 13287 receive_context_thread, arg, 13288 DRIVER_NAME "_%d kctxt%d", dd->unit, idx); 13289 if (ret) { 13290 dd_dev_err(dd, "vnic irq request (irq %d, idx %d) fail %d\n", 13291 me->irq, idx, ret); 13292 return; 13293 } 13294 /* 13295 * assign arg after pci_request_irq call, so it will be 13296 * cleaned up 13297 */ 13298 me->arg = arg; 13299 13300 ret = hfi1_get_irq_affinity(dd, me); 13301 if (ret) { 13302 dd_dev_err(dd, 13303 "unable to pin IRQ %d\n", ret); 13304 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg); 13305 } 13306 } 13307 13308 /* 13309 * Set the general handler to accept all interrupts, remap all 13310 * chip interrupts back to MSI-X 0. 13311 */ 13312 static void reset_interrupts(struct hfi1_devdata *dd) 13313 { 13314 int i; 13315 13316 /* all interrupts handled by the general handler */ 13317 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13318 dd->gi_mask[i] = ~(u64)0; 13319 13320 /* all chip interrupts map to MSI-X 0 */ 13321 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13322 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13323 } 13324 13325 static int set_up_interrupts(struct hfi1_devdata *dd) 13326 { 13327 u32 total; 13328 int ret, request; 13329 int single_interrupt = 0; /* we expect to have all the interrupts */ 13330 13331 /* 13332 * Interrupt count: 13333 * 1 general, "slow path" interrupt (includes the SDMA engines 13334 * slow source, SDMACleanupDone) 13335 * N interrupts - one per used SDMA engine 13336 * M interrupt - one per kernel receive context 13337 * V interrupt - one for each VNIC context 13338 */ 13339 total = 1 + dd->num_sdma + dd->n_krcv_queues + dd->num_vnic_contexts; 13340 13341 /* ask for MSI-X interrupts */ 13342 request = request_msix(dd, total); 13343 if (request < 0) { 13344 ret = request; 13345 goto fail; 13346 } else if (request == 0) { 13347 /* using INTx */ 13348 /* dd->num_msix_entries already zero */ 13349 single_interrupt = 1; 13350 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n"); 13351 } else if (request < total) { 13352 /* using MSI-X, with reduced interrupts */ 13353 dd_dev_err(dd, "reduced interrupt found, wanted %u, got %u\n", 13354 total, request); 13355 ret = -EINVAL; 13356 goto fail; 13357 } else { 13358 dd->msix_entries = kcalloc(total, sizeof(*dd->msix_entries), 13359 GFP_KERNEL); 13360 if (!dd->msix_entries) { 13361 ret = -ENOMEM; 13362 goto fail; 13363 } 13364 /* using MSI-X */ 13365 dd->num_msix_entries = total; 13366 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total); 13367 } 13368 13369 /* mask all interrupts */ 13370 set_intr_state(dd, 0); 13371 /* clear all pending interrupts */ 13372 clear_all_interrupts(dd); 13373 13374 /* reset general handler mask, chip MSI-X mappings */ 13375 reset_interrupts(dd); 13376 13377 if (single_interrupt) 13378 ret = request_intx_irq(dd); 13379 else 13380 ret = request_msix_irqs(dd); 13381 if (ret) 13382 goto fail; 13383 13384 return 0; 13385 13386 fail: 13387 hfi1_clean_up_interrupts(dd); 13388 return ret; 13389 } 13390 13391 /* 13392 * Set up context values in dd. Sets: 13393 * 13394 * num_rcv_contexts - number of contexts being used 13395 * n_krcv_queues - number of kernel contexts 13396 * first_dyn_alloc_ctxt - first dynamically allocated context 13397 * in array of contexts 13398 * freectxts - number of free user contexts 13399 * num_send_contexts - number of PIO send contexts being used 13400 * num_vnic_contexts - number of contexts reserved for VNIC 13401 */ 13402 static int set_up_context_variables(struct hfi1_devdata *dd) 13403 { 13404 unsigned long num_kernel_contexts; 13405 u16 num_vnic_contexts = HFI1_NUM_VNIC_CTXT; 13406 int total_contexts; 13407 int ret; 13408 unsigned ngroups; 13409 int qos_rmt_count; 13410 int user_rmt_reduced; 13411 u32 n_usr_ctxts; 13412 13413 /* 13414 * Kernel receive contexts: 13415 * - Context 0 - control context (VL15/multicast/error) 13416 * - Context 1 - first kernel context 13417 * - Context 2 - second kernel context 13418 * ... 13419 */ 13420 if (n_krcvqs) 13421 /* 13422 * n_krcvqs is the sum of module parameter kernel receive 13423 * contexts, krcvqs[]. It does not include the control 13424 * context, so add that. 13425 */ 13426 num_kernel_contexts = n_krcvqs + 1; 13427 else 13428 num_kernel_contexts = DEFAULT_KRCVQS + 1; 13429 /* 13430 * Every kernel receive context needs an ACK send context. 13431 * one send context is allocated for each VL{0-7} and VL15 13432 */ 13433 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) { 13434 dd_dev_err(dd, 13435 "Reducing # kernel rcv contexts to: %d, from %lu\n", 13436 (int)(dd->chip_send_contexts - num_vls - 1), 13437 num_kernel_contexts); 13438 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1; 13439 } 13440 13441 /* Accommodate VNIC contexts if possible */ 13442 if ((num_kernel_contexts + num_vnic_contexts) > dd->chip_rcv_contexts) { 13443 dd_dev_err(dd, "No receive contexts available for VNIC\n"); 13444 num_vnic_contexts = 0; 13445 } 13446 total_contexts = num_kernel_contexts + num_vnic_contexts; 13447 13448 /* 13449 * User contexts: 13450 * - default to 1 user context per real (non-HT) CPU core if 13451 * num_user_contexts is negative 13452 */ 13453 if (num_user_contexts < 0) 13454 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask); 13455 else 13456 n_usr_ctxts = num_user_contexts; 13457 /* 13458 * Adjust the counts given a global max. 13459 */ 13460 if (total_contexts + n_usr_ctxts > dd->chip_rcv_contexts) { 13461 dd_dev_err(dd, 13462 "Reducing # user receive contexts to: %d, from %u\n", 13463 (int)(dd->chip_rcv_contexts - total_contexts), 13464 n_usr_ctxts); 13465 /* recalculate */ 13466 n_usr_ctxts = dd->chip_rcv_contexts - total_contexts; 13467 } 13468 13469 /* each user context requires an entry in the RMT */ 13470 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL); 13471 if (qos_rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) { 13472 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count; 13473 dd_dev_err(dd, 13474 "RMT size is reducing the number of user receive contexts from %u to %d\n", 13475 n_usr_ctxts, 13476 user_rmt_reduced); 13477 /* recalculate */ 13478 n_usr_ctxts = user_rmt_reduced; 13479 } 13480 13481 total_contexts += n_usr_ctxts; 13482 13483 /* the first N are kernel contexts, the rest are user/vnic contexts */ 13484 dd->num_rcv_contexts = total_contexts; 13485 dd->n_krcv_queues = num_kernel_contexts; 13486 dd->first_dyn_alloc_ctxt = num_kernel_contexts; 13487 dd->num_vnic_contexts = num_vnic_contexts; 13488 dd->num_user_contexts = n_usr_ctxts; 13489 dd->freectxts = n_usr_ctxts; 13490 dd_dev_info(dd, 13491 "rcv contexts: chip %d, used %d (kernel %d, vnic %u, user %u)\n", 13492 (int)dd->chip_rcv_contexts, 13493 (int)dd->num_rcv_contexts, 13494 (int)dd->n_krcv_queues, 13495 dd->num_vnic_contexts, 13496 dd->num_user_contexts); 13497 13498 /* 13499 * Receive array allocation: 13500 * All RcvArray entries are divided into groups of 8. This 13501 * is required by the hardware and will speed up writes to 13502 * consecutive entries by using write-combining of the entire 13503 * cacheline. 13504 * 13505 * The number of groups are evenly divided among all contexts. 13506 * any left over groups will be given to the first N user 13507 * contexts. 13508 */ 13509 dd->rcv_entries.group_size = RCV_INCREMENT; 13510 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size; 13511 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts; 13512 dd->rcv_entries.nctxt_extra = ngroups - 13513 (dd->num_rcv_contexts * dd->rcv_entries.ngroups); 13514 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n", 13515 dd->rcv_entries.ngroups, 13516 dd->rcv_entries.nctxt_extra); 13517 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size > 13518 MAX_EAGER_ENTRIES * 2) { 13519 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) / 13520 dd->rcv_entries.group_size; 13521 dd_dev_info(dd, 13522 "RcvArray group count too high, change to %u\n", 13523 dd->rcv_entries.ngroups); 13524 dd->rcv_entries.nctxt_extra = 0; 13525 } 13526 /* 13527 * PIO send contexts 13528 */ 13529 ret = init_sc_pools_and_sizes(dd); 13530 if (ret >= 0) { /* success */ 13531 dd->num_send_contexts = ret; 13532 dd_dev_info( 13533 dd, 13534 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n", 13535 dd->chip_send_contexts, 13536 dd->num_send_contexts, 13537 dd->sc_sizes[SC_KERNEL].count, 13538 dd->sc_sizes[SC_ACK].count, 13539 dd->sc_sizes[SC_USER].count, 13540 dd->sc_sizes[SC_VL15].count); 13541 ret = 0; /* success */ 13542 } 13543 13544 return ret; 13545 } 13546 13547 /* 13548 * Set the device/port partition key table. The MAD code 13549 * will ensure that, at least, the partial management 13550 * partition key is present in the table. 13551 */ 13552 static void set_partition_keys(struct hfi1_pportdata *ppd) 13553 { 13554 struct hfi1_devdata *dd = ppd->dd; 13555 u64 reg = 0; 13556 int i; 13557 13558 dd_dev_info(dd, "Setting partition keys\n"); 13559 for (i = 0; i < hfi1_get_npkeys(dd); i++) { 13560 reg |= (ppd->pkeys[i] & 13561 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) << 13562 ((i % 4) * 13563 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT); 13564 /* Each register holds 4 PKey values. */ 13565 if ((i % 4) == 3) { 13566 write_csr(dd, RCV_PARTITION_KEY + 13567 ((i - 3) * 2), reg); 13568 reg = 0; 13569 } 13570 } 13571 13572 /* Always enable HW pkeys check when pkeys table is set */ 13573 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK); 13574 } 13575 13576 /* 13577 * These CSRs and memories are uninitialized on reset and must be 13578 * written before reading to set the ECC/parity bits. 13579 * 13580 * NOTE: All user context CSRs that are not mmaped write-only 13581 * (e.g. the TID flows) must be initialized even if the driver never 13582 * reads them. 13583 */ 13584 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd) 13585 { 13586 int i, j; 13587 13588 /* CceIntMap */ 13589 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13590 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13591 13592 /* SendCtxtCreditReturnAddr */ 13593 for (i = 0; i < dd->chip_send_contexts; i++) 13594 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13595 13596 /* PIO Send buffers */ 13597 /* SDMA Send buffers */ 13598 /* 13599 * These are not normally read, and (presently) have no method 13600 * to be read, so are not pre-initialized 13601 */ 13602 13603 /* RcvHdrAddr */ 13604 /* RcvHdrTailAddr */ 13605 /* RcvTidFlowTable */ 13606 for (i = 0; i < dd->chip_rcv_contexts; i++) { 13607 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13608 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13609 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) 13610 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0); 13611 } 13612 13613 /* RcvArray */ 13614 for (i = 0; i < dd->chip_rcv_array_count; i++) 13615 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0); 13616 13617 /* RcvQPMapTable */ 13618 for (i = 0; i < 32; i++) 13619 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13620 } 13621 13622 /* 13623 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus. 13624 */ 13625 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits, 13626 u64 ctrl_bits) 13627 { 13628 unsigned long timeout; 13629 u64 reg; 13630 13631 /* is the condition present? */ 13632 reg = read_csr(dd, CCE_STATUS); 13633 if ((reg & status_bits) == 0) 13634 return; 13635 13636 /* clear the condition */ 13637 write_csr(dd, CCE_CTRL, ctrl_bits); 13638 13639 /* wait for the condition to clear */ 13640 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT); 13641 while (1) { 13642 reg = read_csr(dd, CCE_STATUS); 13643 if ((reg & status_bits) == 0) 13644 return; 13645 if (time_after(jiffies, timeout)) { 13646 dd_dev_err(dd, 13647 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n", 13648 status_bits, reg & status_bits); 13649 return; 13650 } 13651 udelay(1); 13652 } 13653 } 13654 13655 /* set CCE CSRs to chip reset defaults */ 13656 static void reset_cce_csrs(struct hfi1_devdata *dd) 13657 { 13658 int i; 13659 13660 /* CCE_REVISION read-only */ 13661 /* CCE_REVISION2 read-only */ 13662 /* CCE_CTRL - bits clear automatically */ 13663 /* CCE_STATUS read-only, use CceCtrl to clear */ 13664 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK); 13665 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK); 13666 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK); 13667 for (i = 0; i < CCE_NUM_SCRATCH; i++) 13668 write_csr(dd, CCE_SCRATCH + (8 * i), 0); 13669 /* CCE_ERR_STATUS read-only */ 13670 write_csr(dd, CCE_ERR_MASK, 0); 13671 write_csr(dd, CCE_ERR_CLEAR, ~0ull); 13672 /* CCE_ERR_FORCE leave alone */ 13673 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++) 13674 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); 13675 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); 13676 /* CCE_PCIE_CTRL leave alone */ 13677 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) { 13678 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); 13679 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), 13680 CCE_MSIX_TABLE_UPPER_RESETCSR); 13681 } 13682 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) { 13683 /* CCE_MSIX_PBA read-only */ 13684 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); 13685 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); 13686 } 13687 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13688 write_csr(dd, CCE_INT_MAP, 0); 13689 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 13690 /* CCE_INT_STATUS read-only */ 13691 write_csr(dd, CCE_INT_MASK + (8 * i), 0); 13692 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); 13693 /* CCE_INT_FORCE leave alone */ 13694 /* CCE_INT_BLOCKED read-only */ 13695 } 13696 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++) 13697 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); 13698 } 13699 13700 /* set MISC CSRs to chip reset defaults */ 13701 static void reset_misc_csrs(struct hfi1_devdata *dd) 13702 { 13703 int i; 13704 13705 for (i = 0; i < 32; i++) { 13706 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); 13707 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); 13708 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); 13709 } 13710 /* 13711 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can 13712 * only be written 128-byte chunks 13713 */ 13714 /* init RSA engine to clear lingering errors */ 13715 write_csr(dd, MISC_CFG_RSA_CMD, 1); 13716 write_csr(dd, MISC_CFG_RSA_MU, 0); 13717 write_csr(dd, MISC_CFG_FW_CTRL, 0); 13718 /* MISC_STS_8051_DIGEST read-only */ 13719 /* MISC_STS_SBM_DIGEST read-only */ 13720 /* MISC_STS_PCIE_DIGEST read-only */ 13721 /* MISC_STS_FAB_DIGEST read-only */ 13722 /* MISC_ERR_STATUS read-only */ 13723 write_csr(dd, MISC_ERR_MASK, 0); 13724 write_csr(dd, MISC_ERR_CLEAR, ~0ull); 13725 /* MISC_ERR_FORCE leave alone */ 13726 } 13727 13728 /* set TXE CSRs to chip reset defaults */ 13729 static void reset_txe_csrs(struct hfi1_devdata *dd) 13730 { 13731 int i; 13732 13733 /* 13734 * TXE Kernel CSRs 13735 */ 13736 write_csr(dd, SEND_CTRL, 0); 13737 __cm_reset(dd, 0); /* reset CM internal state */ 13738 /* SEND_CONTEXTS read-only */ 13739 /* SEND_DMA_ENGINES read-only */ 13740 /* SEND_PIO_MEM_SIZE read-only */ 13741 /* SEND_DMA_MEM_SIZE read-only */ 13742 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); 13743 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */ 13744 /* SEND_PIO_ERR_STATUS read-only */ 13745 write_csr(dd, SEND_PIO_ERR_MASK, 0); 13746 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); 13747 /* SEND_PIO_ERR_FORCE leave alone */ 13748 /* SEND_DMA_ERR_STATUS read-only */ 13749 write_csr(dd, SEND_DMA_ERR_MASK, 0); 13750 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); 13751 /* SEND_DMA_ERR_FORCE leave alone */ 13752 /* SEND_EGRESS_ERR_STATUS read-only */ 13753 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); 13754 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); 13755 /* SEND_EGRESS_ERR_FORCE leave alone */ 13756 write_csr(dd, SEND_BTH_QP, 0); 13757 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); 13758 write_csr(dd, SEND_SC2VLT0, 0); 13759 write_csr(dd, SEND_SC2VLT1, 0); 13760 write_csr(dd, SEND_SC2VLT2, 0); 13761 write_csr(dd, SEND_SC2VLT3, 0); 13762 write_csr(dd, SEND_LEN_CHECK0, 0); 13763 write_csr(dd, SEND_LEN_CHECK1, 0); 13764 /* SEND_ERR_STATUS read-only */ 13765 write_csr(dd, SEND_ERR_MASK, 0); 13766 write_csr(dd, SEND_ERR_CLEAR, ~0ull); 13767 /* SEND_ERR_FORCE read-only */ 13768 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++) 13769 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); 13770 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++) 13771 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); 13772 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++) 13773 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); 13774 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++) 13775 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); 13776 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++) 13777 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); 13778 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); 13779 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); 13780 /* SEND_CM_CREDIT_USED_STATUS read-only */ 13781 write_csr(dd, SEND_CM_TIMER_CTRL, 0); 13782 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); 13783 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); 13784 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); 13785 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); 13786 for (i = 0; i < TXE_NUM_DATA_VL; i++) 13787 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 13788 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 13789 /* SEND_CM_CREDIT_USED_VL read-only */ 13790 /* SEND_CM_CREDIT_USED_VL15 read-only */ 13791 /* SEND_EGRESS_CTXT_STATUS read-only */ 13792 /* SEND_EGRESS_SEND_DMA_STATUS read-only */ 13793 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); 13794 /* SEND_EGRESS_ERR_INFO read-only */ 13795 /* SEND_EGRESS_ERR_SOURCE read-only */ 13796 13797 /* 13798 * TXE Per-Context CSRs 13799 */ 13800 for (i = 0; i < dd->chip_send_contexts; i++) { 13801 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 13802 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0); 13803 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13804 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0); 13805 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0); 13806 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull); 13807 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0); 13808 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0); 13809 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0); 13810 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0); 13811 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0); 13812 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0); 13813 } 13814 13815 /* 13816 * TXE Per-SDMA CSRs 13817 */ 13818 for (i = 0; i < dd->chip_sdma_engines; i++) { 13819 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 13820 /* SEND_DMA_STATUS read-only */ 13821 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0); 13822 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0); 13823 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0); 13824 /* SEND_DMA_HEAD read-only */ 13825 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0); 13826 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0); 13827 /* SEND_DMA_IDLE_CNT read-only */ 13828 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0); 13829 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0); 13830 /* SEND_DMA_DESC_FETCHED_CNT read-only */ 13831 /* SEND_DMA_ENG_ERR_STATUS read-only */ 13832 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0); 13833 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull); 13834 /* SEND_DMA_ENG_ERR_FORCE leave alone */ 13835 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0); 13836 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0); 13837 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0); 13838 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0); 13839 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0); 13840 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0); 13841 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0); 13842 } 13843 } 13844 13845 /* 13846 * Expect on entry: 13847 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0 13848 */ 13849 static void init_rbufs(struct hfi1_devdata *dd) 13850 { 13851 u64 reg; 13852 int count; 13853 13854 /* 13855 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are 13856 * clear. 13857 */ 13858 count = 0; 13859 while (1) { 13860 reg = read_csr(dd, RCV_STATUS); 13861 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 13862 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0) 13863 break; 13864 /* 13865 * Give up after 1ms - maximum wait time. 13866 * 13867 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at 13868 * 250MB/s bandwidth. Lower rate to 66% for overhead to get: 13869 * 136 KB / (66% * 250MB/s) = 844us 13870 */ 13871 if (count++ > 500) { 13872 dd_dev_err(dd, 13873 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n", 13874 __func__, reg); 13875 break; 13876 } 13877 udelay(2); /* do not busy-wait the CSR */ 13878 } 13879 13880 /* start the init - expect RcvCtrl to be 0 */ 13881 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); 13882 13883 /* 13884 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief 13885 * period after the write before RcvStatus.RxRbufInitDone is valid. 13886 * The delay in the first run through the loop below is sufficient and 13887 * required before the first read of RcvStatus.RxRbufInintDone. 13888 */ 13889 read_csr(dd, RCV_CTRL); 13890 13891 /* wait for the init to finish */ 13892 count = 0; 13893 while (1) { 13894 /* delay is required first time through - see above */ 13895 udelay(2); /* do not busy-wait the CSR */ 13896 reg = read_csr(dd, RCV_STATUS); 13897 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK)) 13898 break; 13899 13900 /* give up after 100us - slowest possible at 33MHz is 73us */ 13901 if (count++ > 50) { 13902 dd_dev_err(dd, 13903 "%s: RcvStatus.RxRbufInit not set, continuing\n", 13904 __func__); 13905 break; 13906 } 13907 } 13908 } 13909 13910 /* set RXE CSRs to chip reset defaults */ 13911 static void reset_rxe_csrs(struct hfi1_devdata *dd) 13912 { 13913 int i, j; 13914 13915 /* 13916 * RXE Kernel CSRs 13917 */ 13918 write_csr(dd, RCV_CTRL, 0); 13919 init_rbufs(dd); 13920 /* RCV_STATUS read-only */ 13921 /* RCV_CONTEXTS read-only */ 13922 /* RCV_ARRAY_CNT read-only */ 13923 /* RCV_BUF_SIZE read-only */ 13924 write_csr(dd, RCV_BTH_QP, 0); 13925 write_csr(dd, RCV_MULTICAST, 0); 13926 write_csr(dd, RCV_BYPASS, 0); 13927 write_csr(dd, RCV_VL15, 0); 13928 /* this is a clear-down */ 13929 write_csr(dd, RCV_ERR_INFO, 13930 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK); 13931 /* RCV_ERR_STATUS read-only */ 13932 write_csr(dd, RCV_ERR_MASK, 0); 13933 write_csr(dd, RCV_ERR_CLEAR, ~0ull); 13934 /* RCV_ERR_FORCE leave alone */ 13935 for (i = 0; i < 32; i++) 13936 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13937 for (i = 0; i < 4; i++) 13938 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); 13939 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++) 13940 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); 13941 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++) 13942 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); 13943 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) 13944 clear_rsm_rule(dd, i); 13945 for (i = 0; i < 32; i++) 13946 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); 13947 13948 /* 13949 * RXE Kernel and User Per-Context CSRs 13950 */ 13951 for (i = 0; i < dd->chip_rcv_contexts; i++) { 13952 /* kernel */ 13953 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0); 13954 /* RCV_CTXT_STATUS read-only */ 13955 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0); 13956 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0); 13957 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0); 13958 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13959 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0); 13960 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0); 13961 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0); 13962 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13963 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0); 13964 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0); 13965 13966 /* user */ 13967 /* RCV_HDR_TAIL read-only */ 13968 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0); 13969 /* RCV_EGR_INDEX_TAIL read-only */ 13970 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0); 13971 /* RCV_EGR_OFFSET_TAIL read-only */ 13972 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) { 13973 write_uctxt_csr(dd, i, 13974 RCV_TID_FLOW_TABLE + (8 * j), 0); 13975 } 13976 } 13977 } 13978 13979 /* 13980 * Set sc2vl tables. 13981 * 13982 * They power on to zeros, so to avoid send context errors 13983 * they need to be set: 13984 * 13985 * SC 0-7 -> VL 0-7 (respectively) 13986 * SC 15 -> VL 15 13987 * otherwise 13988 * -> VL 0 13989 */ 13990 static void init_sc2vl_tables(struct hfi1_devdata *dd) 13991 { 13992 int i; 13993 /* init per architecture spec, constrained by hardware capability */ 13994 13995 /* HFI maps sent packets */ 13996 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( 13997 0, 13998 0, 0, 1, 1, 13999 2, 2, 3, 3, 14000 4, 4, 5, 5, 14001 6, 6, 7, 7)); 14002 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( 14003 1, 14004 8, 0, 9, 0, 14005 10, 0, 11, 0, 14006 12, 0, 13, 0, 14007 14, 0, 15, 15)); 14008 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( 14009 2, 14010 16, 0, 17, 0, 14011 18, 0, 19, 0, 14012 20, 0, 21, 0, 14013 22, 0, 23, 0)); 14014 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( 14015 3, 14016 24, 0, 25, 0, 14017 26, 0, 27, 0, 14018 28, 0, 29, 0, 14019 30, 0, 31, 0)); 14020 14021 /* DC maps received packets */ 14022 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( 14023 15_0, 14024 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 14025 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15)); 14026 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( 14027 31_16, 14028 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0, 14029 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0)); 14030 14031 /* initialize the cached sc2vl values consistently with h/w */ 14032 for (i = 0; i < 32; i++) { 14033 if (i < 8 || i == 15) 14034 *((u8 *)(dd->sc2vl) + i) = (u8)i; 14035 else 14036 *((u8 *)(dd->sc2vl) + i) = 0; 14037 } 14038 } 14039 14040 /* 14041 * Read chip sizes and then reset parts to sane, disabled, values. We cannot 14042 * depend on the chip going through a power-on reset - a driver may be loaded 14043 * and unloaded many times. 14044 * 14045 * Do not write any CSR values to the chip in this routine - there may be 14046 * a reset following the (possible) FLR in this routine. 14047 * 14048 */ 14049 static int init_chip(struct hfi1_devdata *dd) 14050 { 14051 int i; 14052 int ret = 0; 14053 14054 /* 14055 * Put the HFI CSRs in a known state. 14056 * Combine this with a DC reset. 14057 * 14058 * Stop the device from doing anything while we do a 14059 * reset. We know there are no other active users of 14060 * the device since we are now in charge. Turn off 14061 * off all outbound and inbound traffic and make sure 14062 * the device does not generate any interrupts. 14063 */ 14064 14065 /* disable send contexts and SDMA engines */ 14066 write_csr(dd, SEND_CTRL, 0); 14067 for (i = 0; i < dd->chip_send_contexts; i++) 14068 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 14069 for (i = 0; i < dd->chip_sdma_engines; i++) 14070 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 14071 /* disable port (turn off RXE inbound traffic) and contexts */ 14072 write_csr(dd, RCV_CTRL, 0); 14073 for (i = 0; i < dd->chip_rcv_contexts; i++) 14074 write_csr(dd, RCV_CTXT_CTRL, 0); 14075 /* mask all interrupt sources */ 14076 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 14077 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 14078 14079 /* 14080 * DC Reset: do a full DC reset before the register clear. 14081 * A recommended length of time to hold is one CSR read, 14082 * so reread the CceDcCtrl. Then, hold the DC in reset 14083 * across the clear. 14084 */ 14085 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 14086 (void)read_csr(dd, CCE_DC_CTRL); 14087 14088 if (use_flr) { 14089 /* 14090 * A FLR will reset the SPC core and part of the PCIe. 14091 * The parts that need to be restored have already been 14092 * saved. 14093 */ 14094 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14095 14096 /* do the FLR, the DC reset will remain */ 14097 pcie_flr(dd->pcidev); 14098 14099 /* restore command and BARs */ 14100 ret = restore_pci_variables(dd); 14101 if (ret) { 14102 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14103 __func__); 14104 return ret; 14105 } 14106 14107 if (is_ax(dd)) { 14108 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14109 pcie_flr(dd->pcidev); 14110 ret = restore_pci_variables(dd); 14111 if (ret) { 14112 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14113 __func__); 14114 return ret; 14115 } 14116 } 14117 } else { 14118 dd_dev_info(dd, "Resetting CSRs with writes\n"); 14119 reset_cce_csrs(dd); 14120 reset_txe_csrs(dd); 14121 reset_rxe_csrs(dd); 14122 reset_misc_csrs(dd); 14123 } 14124 /* clear the DC reset */ 14125 write_csr(dd, CCE_DC_CTRL, 0); 14126 14127 /* Set the LED off */ 14128 setextled(dd, 0); 14129 14130 /* 14131 * Clear the QSFP reset. 14132 * An FLR enforces a 0 on all out pins. The driver does not touch 14133 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and 14134 * anything plugged constantly in reset, if it pays attention 14135 * to RESET_N. 14136 * Prime examples of this are optical cables. Set all pins high. 14137 * I2CCLK and I2CDAT will change per direction, and INT_N and 14138 * MODPRS_N are input only and their value is ignored. 14139 */ 14140 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); 14141 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); 14142 init_chip_resources(dd); 14143 return ret; 14144 } 14145 14146 static void init_early_variables(struct hfi1_devdata *dd) 14147 { 14148 int i; 14149 14150 /* assign link credit variables */ 14151 dd->vau = CM_VAU; 14152 dd->link_credits = CM_GLOBAL_CREDITS; 14153 if (is_ax(dd)) 14154 dd->link_credits--; 14155 dd->vcu = cu_to_vcu(hfi1_cu); 14156 /* enough room for 8 MAD packets plus header - 17K */ 14157 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau); 14158 if (dd->vl15_init > dd->link_credits) 14159 dd->vl15_init = dd->link_credits; 14160 14161 write_uninitialized_csrs_and_memories(dd); 14162 14163 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 14164 for (i = 0; i < dd->num_pports; i++) { 14165 struct hfi1_pportdata *ppd = &dd->pport[i]; 14166 14167 set_partition_keys(ppd); 14168 } 14169 init_sc2vl_tables(dd); 14170 } 14171 14172 static void init_kdeth_qp(struct hfi1_devdata *dd) 14173 { 14174 /* user changed the KDETH_QP */ 14175 if (kdeth_qp != 0 && kdeth_qp >= 0xff) { 14176 /* out of range or illegal value */ 14177 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring"); 14178 kdeth_qp = 0; 14179 } 14180 if (kdeth_qp == 0) /* not set, or failed range check */ 14181 kdeth_qp = DEFAULT_KDETH_QP; 14182 14183 write_csr(dd, SEND_BTH_QP, 14184 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) << 14185 SEND_BTH_QP_KDETH_QP_SHIFT); 14186 14187 write_csr(dd, RCV_BTH_QP, 14188 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) << 14189 RCV_BTH_QP_KDETH_QP_SHIFT); 14190 } 14191 14192 /** 14193 * init_qpmap_table 14194 * @dd - device data 14195 * @first_ctxt - first context 14196 * @last_ctxt - first context 14197 * 14198 * This return sets the qpn mapping table that 14199 * is indexed by qpn[8:1]. 14200 * 14201 * The routine will round robin the 256 settings 14202 * from first_ctxt to last_ctxt. 14203 * 14204 * The first/last looks ahead to having specialized 14205 * receive contexts for mgmt and bypass. Normal 14206 * verbs traffic will assumed to be on a range 14207 * of receive contexts. 14208 */ 14209 static void init_qpmap_table(struct hfi1_devdata *dd, 14210 u32 first_ctxt, 14211 u32 last_ctxt) 14212 { 14213 u64 reg = 0; 14214 u64 regno = RCV_QP_MAP_TABLE; 14215 int i; 14216 u64 ctxt = first_ctxt; 14217 14218 for (i = 0; i < 256; i++) { 14219 reg |= ctxt << (8 * (i % 8)); 14220 ctxt++; 14221 if (ctxt > last_ctxt) 14222 ctxt = first_ctxt; 14223 if (i % 8 == 7) { 14224 write_csr(dd, regno, reg); 14225 reg = 0; 14226 regno += 8; 14227 } 14228 } 14229 14230 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 14231 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK); 14232 } 14233 14234 struct rsm_map_table { 14235 u64 map[NUM_MAP_REGS]; 14236 unsigned int used; 14237 }; 14238 14239 struct rsm_rule_data { 14240 u8 offset; 14241 u8 pkt_type; 14242 u32 field1_off; 14243 u32 field2_off; 14244 u32 index1_off; 14245 u32 index1_width; 14246 u32 index2_off; 14247 u32 index2_width; 14248 u32 mask1; 14249 u32 value1; 14250 u32 mask2; 14251 u32 value2; 14252 }; 14253 14254 /* 14255 * Return an initialized RMT map table for users to fill in. OK if it 14256 * returns NULL, indicating no table. 14257 */ 14258 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd) 14259 { 14260 struct rsm_map_table *rmt; 14261 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */ 14262 14263 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL); 14264 if (rmt) { 14265 memset(rmt->map, rxcontext, sizeof(rmt->map)); 14266 rmt->used = 0; 14267 } 14268 14269 return rmt; 14270 } 14271 14272 /* 14273 * Write the final RMT map table to the chip and free the table. OK if 14274 * table is NULL. 14275 */ 14276 static void complete_rsm_map_table(struct hfi1_devdata *dd, 14277 struct rsm_map_table *rmt) 14278 { 14279 int i; 14280 14281 if (rmt) { 14282 /* write table to chip */ 14283 for (i = 0; i < NUM_MAP_REGS; i++) 14284 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); 14285 14286 /* enable RSM */ 14287 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14288 } 14289 } 14290 14291 /* 14292 * Add a receive side mapping rule. 14293 */ 14294 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index, 14295 struct rsm_rule_data *rrd) 14296 { 14297 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 14298 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT | 14299 1ull << rule_index | /* enable bit */ 14300 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT); 14301 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 14302 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT | 14303 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT | 14304 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT | 14305 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT | 14306 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT | 14307 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT); 14308 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 14309 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT | 14310 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT | 14311 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT | 14312 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT); 14313 } 14314 14315 /* 14316 * Clear a receive side mapping rule. 14317 */ 14318 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14319 { 14320 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); 14321 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); 14322 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); 14323 } 14324 14325 /* return the number of RSM map table entries that will be used for QOS */ 14326 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 14327 unsigned int *np) 14328 { 14329 int i; 14330 unsigned int m, n; 14331 u8 max_by_vl = 0; 14332 14333 /* is QOS active at all? */ 14334 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS || 14335 num_vls == 1 || 14336 krcvqsset <= 1) 14337 goto no_qos; 14338 14339 /* determine bits for qpn */ 14340 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++) 14341 if (krcvqs[i] > max_by_vl) 14342 max_by_vl = krcvqs[i]; 14343 if (max_by_vl > 32) 14344 goto no_qos; 14345 m = ilog2(__roundup_pow_of_two(max_by_vl)); 14346 14347 /* determine bits for vl */ 14348 n = ilog2(__roundup_pow_of_two(num_vls)); 14349 14350 /* reject if too much is used */ 14351 if ((m + n) > 7) 14352 goto no_qos; 14353 14354 if (mp) 14355 *mp = m; 14356 if (np) 14357 *np = n; 14358 14359 return 1 << (m + n); 14360 14361 no_qos: 14362 if (mp) 14363 *mp = 0; 14364 if (np) 14365 *np = 0; 14366 return 0; 14367 } 14368 14369 /** 14370 * init_qos - init RX qos 14371 * @dd - device data 14372 * @rmt - RSM map table 14373 * 14374 * This routine initializes Rule 0 and the RSM map table to implement 14375 * quality of service (qos). 14376 * 14377 * If all of the limit tests succeed, qos is applied based on the array 14378 * interpretation of krcvqs where entry 0 is VL0. 14379 * 14380 * The number of vl bits (n) and the number of qpn bits (m) are computed to 14381 * feed both the RSM map table and the single rule. 14382 */ 14383 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt) 14384 { 14385 struct rsm_rule_data rrd; 14386 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m; 14387 unsigned int rmt_entries; 14388 u64 reg; 14389 14390 if (!rmt) 14391 goto bail; 14392 rmt_entries = qos_rmt_entries(dd, &m, &n); 14393 if (rmt_entries == 0) 14394 goto bail; 14395 qpns_per_vl = 1 << m; 14396 14397 /* enough room in the map table? */ 14398 rmt_entries = 1 << (m + n); 14399 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES) 14400 goto bail; 14401 14402 /* add qos entries to the the RSM map table */ 14403 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) { 14404 unsigned tctxt; 14405 14406 for (qpn = 0, tctxt = ctxt; 14407 krcvqs[i] && qpn < qpns_per_vl; qpn++) { 14408 unsigned idx, regoff, regidx; 14409 14410 /* generate the index the hardware will produce */ 14411 idx = rmt->used + ((qpn << n) ^ i); 14412 regoff = (idx % 8) * 8; 14413 regidx = idx / 8; 14414 /* replace default with context number */ 14415 reg = rmt->map[regidx]; 14416 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 14417 << regoff); 14418 reg |= (u64)(tctxt++) << regoff; 14419 rmt->map[regidx] = reg; 14420 if (tctxt == ctxt + krcvqs[i]) 14421 tctxt = ctxt; 14422 } 14423 ctxt += krcvqs[i]; 14424 } 14425 14426 rrd.offset = rmt->used; 14427 rrd.pkt_type = 2; 14428 rrd.field1_off = LRH_BTH_MATCH_OFFSET; 14429 rrd.field2_off = LRH_SC_MATCH_OFFSET; 14430 rrd.index1_off = LRH_SC_SELECT_OFFSET; 14431 rrd.index1_width = n; 14432 rrd.index2_off = QPN_SELECT_OFFSET; 14433 rrd.index2_width = m + n; 14434 rrd.mask1 = LRH_BTH_MASK; 14435 rrd.value1 = LRH_BTH_VALUE; 14436 rrd.mask2 = LRH_SC_MASK; 14437 rrd.value2 = LRH_SC_VALUE; 14438 14439 /* add rule 0 */ 14440 add_rsm_rule(dd, RSM_INS_VERBS, &rrd); 14441 14442 /* mark RSM map entries as used */ 14443 rmt->used += rmt_entries; 14444 /* map everything else to the mcast/err/vl15 context */ 14445 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT); 14446 dd->qos_shift = n + 1; 14447 return; 14448 bail: 14449 dd->qos_shift = 1; 14450 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1); 14451 } 14452 14453 static void init_user_fecn_handling(struct hfi1_devdata *dd, 14454 struct rsm_map_table *rmt) 14455 { 14456 struct rsm_rule_data rrd; 14457 u64 reg; 14458 int i, idx, regoff, regidx; 14459 u8 offset; 14460 14461 /* there needs to be enough room in the map table */ 14462 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) { 14463 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n"); 14464 return; 14465 } 14466 14467 /* 14468 * RSM will extract the destination context as an index into the 14469 * map table. The destination contexts are a sequential block 14470 * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive). 14471 * Map entries are accessed as offset + extracted value. Adjust 14472 * the added offset so this sequence can be placed anywhere in 14473 * the table - as long as the entries themselves do not wrap. 14474 * There are only enough bits in offset for the table size, so 14475 * start with that to allow for a "negative" offset. 14476 */ 14477 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used - 14478 (int)dd->first_dyn_alloc_ctxt); 14479 14480 for (i = dd->first_dyn_alloc_ctxt, idx = rmt->used; 14481 i < dd->num_rcv_contexts; i++, idx++) { 14482 /* replace with identity mapping */ 14483 regoff = (idx % 8) * 8; 14484 regidx = idx / 8; 14485 reg = rmt->map[regidx]; 14486 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff); 14487 reg |= (u64)i << regoff; 14488 rmt->map[regidx] = reg; 14489 } 14490 14491 /* 14492 * For RSM intercept of Expected FECN packets: 14493 * o packet type 0 - expected 14494 * o match on F (bit 95), using select/match 1, and 14495 * o match on SH (bit 133), using select/match 2. 14496 * 14497 * Use index 1 to extract the 8-bit receive context from DestQP 14498 * (start at bit 64). Use that as the RSM map table index. 14499 */ 14500 rrd.offset = offset; 14501 rrd.pkt_type = 0; 14502 rrd.field1_off = 95; 14503 rrd.field2_off = 133; 14504 rrd.index1_off = 64; 14505 rrd.index1_width = 8; 14506 rrd.index2_off = 0; 14507 rrd.index2_width = 0; 14508 rrd.mask1 = 1; 14509 rrd.value1 = 1; 14510 rrd.mask2 = 1; 14511 rrd.value2 = 1; 14512 14513 /* add rule 1 */ 14514 add_rsm_rule(dd, RSM_INS_FECN, &rrd); 14515 14516 rmt->used += dd->num_user_contexts; 14517 } 14518 14519 /* Initialize RSM for VNIC */ 14520 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd) 14521 { 14522 u8 i, j; 14523 u8 ctx_id = 0; 14524 u64 reg; 14525 u32 regoff; 14526 struct rsm_rule_data rrd; 14527 14528 if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) { 14529 dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n", 14530 dd->vnic.rmt_start); 14531 return; 14532 } 14533 14534 dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n", 14535 dd->vnic.rmt_start, 14536 dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES); 14537 14538 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */ 14539 regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8; 14540 reg = read_csr(dd, regoff); 14541 for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) { 14542 /* Update map register with vnic context */ 14543 j = (dd->vnic.rmt_start + i) % 8; 14544 reg &= ~(0xffllu << (j * 8)); 14545 reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8); 14546 /* Wrap up vnic ctx index */ 14547 ctx_id %= dd->vnic.num_ctxt; 14548 /* Write back map register */ 14549 if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) { 14550 dev_dbg(&(dd)->pcidev->dev, 14551 "Vnic rsm map reg[%d] =0x%llx\n", 14552 regoff - RCV_RSM_MAP_TABLE, reg); 14553 14554 write_csr(dd, regoff, reg); 14555 regoff += 8; 14556 if (i < (NUM_VNIC_MAP_ENTRIES - 1)) 14557 reg = read_csr(dd, regoff); 14558 } 14559 } 14560 14561 /* Add rule for vnic */ 14562 rrd.offset = dd->vnic.rmt_start; 14563 rrd.pkt_type = 4; 14564 /* Match 16B packets */ 14565 rrd.field1_off = L2_TYPE_MATCH_OFFSET; 14566 rrd.mask1 = L2_TYPE_MASK; 14567 rrd.value1 = L2_16B_VALUE; 14568 /* Match ETH L4 packets */ 14569 rrd.field2_off = L4_TYPE_MATCH_OFFSET; 14570 rrd.mask2 = L4_16B_TYPE_MASK; 14571 rrd.value2 = L4_16B_ETH_VALUE; 14572 /* Calc context from veswid and entropy */ 14573 rrd.index1_off = L4_16B_HDR_VESWID_OFFSET; 14574 rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES); 14575 rrd.index2_off = L2_16B_ENTROPY_OFFSET; 14576 rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES); 14577 add_rsm_rule(dd, RSM_INS_VNIC, &rrd); 14578 14579 /* Enable RSM if not already enabled */ 14580 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14581 } 14582 14583 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd) 14584 { 14585 clear_rsm_rule(dd, RSM_INS_VNIC); 14586 14587 /* Disable RSM if used only by vnic */ 14588 if (dd->vnic.rmt_start == 0) 14589 clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14590 } 14591 14592 static void init_rxe(struct hfi1_devdata *dd) 14593 { 14594 struct rsm_map_table *rmt; 14595 u64 val; 14596 14597 /* enable all receive errors */ 14598 write_csr(dd, RCV_ERR_MASK, ~0ull); 14599 14600 rmt = alloc_rsm_map_table(dd); 14601 /* set up QOS, including the QPN map table */ 14602 init_qos(dd, rmt); 14603 init_user_fecn_handling(dd, rmt); 14604 complete_rsm_map_table(dd, rmt); 14605 /* record number of used rsm map entries for vnic */ 14606 dd->vnic.rmt_start = rmt->used; 14607 kfree(rmt); 14608 14609 /* 14610 * make sure RcvCtrl.RcvWcb <= PCIe Device Control 14611 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config 14612 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one 14613 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and 14614 * Max_PayLoad_Size set to its minimum of 128. 14615 * 14616 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0 14617 * (64 bytes). Max_Payload_Size is possibly modified upward in 14618 * tune_pcie_caps() which is called after this routine. 14619 */ 14620 14621 /* Have 16 bytes (4DW) of bypass header available in header queue */ 14622 val = read_csr(dd, RCV_BYPASS); 14623 val |= (4ull << 16); 14624 write_csr(dd, RCV_BYPASS, val); 14625 } 14626 14627 static void init_other(struct hfi1_devdata *dd) 14628 { 14629 /* enable all CCE errors */ 14630 write_csr(dd, CCE_ERR_MASK, ~0ull); 14631 /* enable *some* Misc errors */ 14632 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); 14633 /* enable all DC errors, except LCB */ 14634 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); 14635 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); 14636 } 14637 14638 /* 14639 * Fill out the given AU table using the given CU. A CU is defined in terms 14640 * AUs. The table is a an encoding: given the index, how many AUs does that 14641 * represent? 14642 * 14643 * NOTE: Assumes that the register layout is the same for the 14644 * local and remote tables. 14645 */ 14646 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu, 14647 u32 csr0to3, u32 csr4to7) 14648 { 14649 write_csr(dd, csr0to3, 14650 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT | 14651 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT | 14652 2ull * cu << 14653 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT | 14654 4ull * cu << 14655 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT); 14656 write_csr(dd, csr4to7, 14657 8ull * cu << 14658 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT | 14659 16ull * cu << 14660 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT | 14661 32ull * cu << 14662 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT | 14663 64ull * cu << 14664 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT); 14665 } 14666 14667 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14668 { 14669 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3, 14670 SEND_CM_LOCAL_AU_TABLE4_TO7); 14671 } 14672 14673 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14674 { 14675 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3, 14676 SEND_CM_REMOTE_AU_TABLE4_TO7); 14677 } 14678 14679 static void init_txe(struct hfi1_devdata *dd) 14680 { 14681 int i; 14682 14683 /* enable all PIO, SDMA, general, and Egress errors */ 14684 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); 14685 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); 14686 write_csr(dd, SEND_ERR_MASK, ~0ull); 14687 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); 14688 14689 /* enable all per-context and per-SDMA engine errors */ 14690 for (i = 0; i < dd->chip_send_contexts; i++) 14691 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull); 14692 for (i = 0; i < dd->chip_sdma_engines; i++) 14693 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull); 14694 14695 /* set the local CU to AU mapping */ 14696 assign_local_cm_au_table(dd, dd->vcu); 14697 14698 /* 14699 * Set reasonable default for Credit Return Timer 14700 * Don't set on Simulator - causes it to choke. 14701 */ 14702 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 14703 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); 14704 } 14705 14706 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14707 u16 jkey) 14708 { 14709 u8 hw_ctxt; 14710 u64 reg; 14711 14712 if (!rcd || !rcd->sc) 14713 return -EINVAL; 14714 14715 hw_ctxt = rcd->sc->hw_context; 14716 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */ 14717 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) << 14718 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT); 14719 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */ 14720 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY)) 14721 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK; 14722 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg); 14723 /* 14724 * Enable send-side J_KEY integrity check, unless this is A0 h/w 14725 */ 14726 if (!is_ax(dd)) { 14727 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14728 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14729 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14730 } 14731 14732 /* Enable J_KEY check on receive context. */ 14733 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK | 14734 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) << 14735 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT); 14736 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg); 14737 14738 return 0; 14739 } 14740 14741 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 14742 { 14743 u8 hw_ctxt; 14744 u64 reg; 14745 14746 if (!rcd || !rcd->sc) 14747 return -EINVAL; 14748 14749 hw_ctxt = rcd->sc->hw_context; 14750 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0); 14751 /* 14752 * Disable send-side J_KEY integrity check, unless this is A0 h/w. 14753 * This check would not have been enabled for A0 h/w, see 14754 * set_ctxt_jkey(). 14755 */ 14756 if (!is_ax(dd)) { 14757 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14758 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14759 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14760 } 14761 /* Turn off the J_KEY on the receive side */ 14762 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0); 14763 14764 return 0; 14765 } 14766 14767 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14768 u16 pkey) 14769 { 14770 u8 hw_ctxt; 14771 u64 reg; 14772 14773 if (!rcd || !rcd->sc) 14774 return -EINVAL; 14775 14776 hw_ctxt = rcd->sc->hw_context; 14777 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) << 14778 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT; 14779 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg); 14780 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14781 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14782 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK; 14783 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14784 14785 return 0; 14786 } 14787 14788 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt) 14789 { 14790 u8 hw_ctxt; 14791 u64 reg; 14792 14793 if (!ctxt || !ctxt->sc) 14794 return -EINVAL; 14795 14796 hw_ctxt = ctxt->sc->hw_context; 14797 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14798 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14799 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14800 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0); 14801 14802 return 0; 14803 } 14804 14805 /* 14806 * Start doing the clean up the the chip. Our clean up happens in multiple 14807 * stages and this is just the first. 14808 */ 14809 void hfi1_start_cleanup(struct hfi1_devdata *dd) 14810 { 14811 aspm_exit(dd); 14812 free_cntrs(dd); 14813 free_rcverr(dd); 14814 finish_chip_resources(dd); 14815 } 14816 14817 #define HFI_BASE_GUID(dev) \ 14818 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT)) 14819 14820 /* 14821 * Information can be shared between the two HFIs on the same ASIC 14822 * in the same OS. This function finds the peer device and sets 14823 * up a shared structure. 14824 */ 14825 static int init_asic_data(struct hfi1_devdata *dd) 14826 { 14827 unsigned long flags; 14828 struct hfi1_devdata *tmp, *peer = NULL; 14829 struct hfi1_asic_data *asic_data; 14830 int ret = 0; 14831 14832 /* pre-allocate the asic structure in case we are the first device */ 14833 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL); 14834 if (!asic_data) 14835 return -ENOMEM; 14836 14837 spin_lock_irqsave(&hfi1_devs_lock, flags); 14838 /* Find our peer device */ 14839 list_for_each_entry(tmp, &hfi1_dev_list, list) { 14840 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) && 14841 dd->unit != tmp->unit) { 14842 peer = tmp; 14843 break; 14844 } 14845 } 14846 14847 if (peer) { 14848 /* use already allocated structure */ 14849 dd->asic_data = peer->asic_data; 14850 kfree(asic_data); 14851 } else { 14852 dd->asic_data = asic_data; 14853 mutex_init(&dd->asic_data->asic_resource_mutex); 14854 } 14855 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */ 14856 spin_unlock_irqrestore(&hfi1_devs_lock, flags); 14857 14858 /* first one through - set up i2c devices */ 14859 if (!peer) 14860 ret = set_up_i2c(dd, dd->asic_data); 14861 14862 return ret; 14863 } 14864 14865 /* 14866 * Set dd->boardname. Use a generic name if a name is not returned from 14867 * EFI variable space. 14868 * 14869 * Return 0 on success, -ENOMEM if space could not be allocated. 14870 */ 14871 static int obtain_boardname(struct hfi1_devdata *dd) 14872 { 14873 /* generic board description */ 14874 const char generic[] = 14875 "Intel Omni-Path Host Fabric Interface Adapter 100 Series"; 14876 unsigned long size; 14877 int ret; 14878 14879 ret = read_hfi1_efi_var(dd, "description", &size, 14880 (void **)&dd->boardname); 14881 if (ret) { 14882 dd_dev_info(dd, "Board description not found\n"); 14883 /* use generic description */ 14884 dd->boardname = kstrdup(generic, GFP_KERNEL); 14885 if (!dd->boardname) 14886 return -ENOMEM; 14887 } 14888 return 0; 14889 } 14890 14891 /* 14892 * Check the interrupt registers to make sure that they are mapped correctly. 14893 * It is intended to help user identify any mismapping by VMM when the driver 14894 * is running in a VM. This function should only be called before interrupt 14895 * is set up properly. 14896 * 14897 * Return 0 on success, -EINVAL on failure. 14898 */ 14899 static int check_int_registers(struct hfi1_devdata *dd) 14900 { 14901 u64 reg; 14902 u64 all_bits = ~(u64)0; 14903 u64 mask; 14904 14905 /* Clear CceIntMask[0] to avoid raising any interrupts */ 14906 mask = read_csr(dd, CCE_INT_MASK); 14907 write_csr(dd, CCE_INT_MASK, 0ull); 14908 reg = read_csr(dd, CCE_INT_MASK); 14909 if (reg) 14910 goto err_exit; 14911 14912 /* Clear all interrupt status bits */ 14913 write_csr(dd, CCE_INT_CLEAR, all_bits); 14914 reg = read_csr(dd, CCE_INT_STATUS); 14915 if (reg) 14916 goto err_exit; 14917 14918 /* Set all interrupt status bits */ 14919 write_csr(dd, CCE_INT_FORCE, all_bits); 14920 reg = read_csr(dd, CCE_INT_STATUS); 14921 if (reg != all_bits) 14922 goto err_exit; 14923 14924 /* Restore the interrupt mask */ 14925 write_csr(dd, CCE_INT_CLEAR, all_bits); 14926 write_csr(dd, CCE_INT_MASK, mask); 14927 14928 return 0; 14929 err_exit: 14930 write_csr(dd, CCE_INT_MASK, mask); 14931 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n"); 14932 return -EINVAL; 14933 } 14934 14935 /** 14936 * Allocate and initialize the device structure for the hfi. 14937 * @dev: the pci_dev for hfi1_ib device 14938 * @ent: pci_device_id struct for this dev 14939 * 14940 * Also allocates, initializes, and returns the devdata struct for this 14941 * device instance 14942 * 14943 * This is global, and is called directly at init to set up the 14944 * chip-specific function pointers for later use. 14945 */ 14946 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, 14947 const struct pci_device_id *ent) 14948 { 14949 struct hfi1_devdata *dd; 14950 struct hfi1_pportdata *ppd; 14951 u64 reg; 14952 int i, ret; 14953 static const char * const inames[] = { /* implementation names */ 14954 "RTL silicon", 14955 "RTL VCS simulation", 14956 "RTL FPGA emulation", 14957 "Functional simulator" 14958 }; 14959 struct pci_dev *parent = pdev->bus->self; 14960 14961 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS * 14962 sizeof(struct hfi1_pportdata)); 14963 if (IS_ERR(dd)) 14964 goto bail; 14965 ppd = dd->pport; 14966 for (i = 0; i < dd->num_pports; i++, ppd++) { 14967 int vl; 14968 /* init common fields */ 14969 hfi1_init_pportdata(pdev, ppd, dd, 0, 1); 14970 /* DC supports 4 link widths */ 14971 ppd->link_width_supported = 14972 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X | 14973 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X; 14974 ppd->link_width_downgrade_supported = 14975 ppd->link_width_supported; 14976 /* start out enabling only 4X */ 14977 ppd->link_width_enabled = OPA_LINK_WIDTH_4X; 14978 ppd->link_width_downgrade_enabled = 14979 ppd->link_width_downgrade_supported; 14980 /* link width active is 0 when link is down */ 14981 /* link width downgrade active is 0 when link is down */ 14982 14983 if (num_vls < HFI1_MIN_VLS_SUPPORTED || 14984 num_vls > HFI1_MAX_VLS_SUPPORTED) { 14985 dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n", 14986 num_vls, HFI1_MAX_VLS_SUPPORTED); 14987 num_vls = HFI1_MAX_VLS_SUPPORTED; 14988 } 14989 ppd->vls_supported = num_vls; 14990 ppd->vls_operational = ppd->vls_supported; 14991 /* Set the default MTU. */ 14992 for (vl = 0; vl < num_vls; vl++) 14993 dd->vld[vl].mtu = hfi1_max_mtu; 14994 dd->vld[15].mtu = MAX_MAD_PACKET; 14995 /* 14996 * Set the initial values to reasonable default, will be set 14997 * for real when link is up. 14998 */ 14999 ppd->overrun_threshold = 0x4; 15000 ppd->phy_error_threshold = 0xf; 15001 ppd->port_crc_mode_enabled = link_crc_mask; 15002 /* initialize supported LTP CRC mode */ 15003 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 15004 /* initialize enabled LTP CRC mode */ 15005 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4; 15006 /* start in offline */ 15007 ppd->host_link_state = HLS_DN_OFFLINE; 15008 init_vl_arb_caches(ppd); 15009 } 15010 15011 /* 15012 * Do remaining PCIe setup and save PCIe values in dd. 15013 * Any error printing is already done by the init code. 15014 * On return, we have the chip mapped. 15015 */ 15016 ret = hfi1_pcie_ddinit(dd, pdev); 15017 if (ret < 0) 15018 goto bail_free; 15019 15020 /* Save PCI space registers to rewrite after device reset */ 15021 ret = save_pci_variables(dd); 15022 if (ret < 0) 15023 goto bail_cleanup; 15024 15025 /* verify that reads actually work, save revision for reset check */ 15026 dd->revision = read_csr(dd, CCE_REVISION); 15027 if (dd->revision == ~(u64)0) { 15028 dd_dev_err(dd, "cannot read chip CSRs\n"); 15029 ret = -EINVAL; 15030 goto bail_cleanup; 15031 } 15032 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT) 15033 & CCE_REVISION_CHIP_REV_MAJOR_MASK; 15034 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT) 15035 & CCE_REVISION_CHIP_REV_MINOR_MASK; 15036 15037 /* 15038 * Check interrupt registers mapping if the driver has no access to 15039 * the upstream component. In this case, it is likely that the driver 15040 * is running in a VM. 15041 */ 15042 if (!parent) { 15043 ret = check_int_registers(dd); 15044 if (ret) 15045 goto bail_cleanup; 15046 } 15047 15048 /* 15049 * obtain the hardware ID - NOT related to unit, which is a 15050 * software enumeration 15051 */ 15052 reg = read_csr(dd, CCE_REVISION2); 15053 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT) 15054 & CCE_REVISION2_HFI_ID_MASK; 15055 /* the variable size will remove unwanted bits */ 15056 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT; 15057 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT; 15058 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n", 15059 dd->icode < ARRAY_SIZE(inames) ? 15060 inames[dd->icode] : "unknown", (int)dd->irev); 15061 15062 /* speeds the hardware can support */ 15063 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G; 15064 /* speeds allowed to run at */ 15065 dd->pport->link_speed_enabled = dd->pport->link_speed_supported; 15066 /* give a reasonable active value, will be set on link up */ 15067 dd->pport->link_speed_active = OPA_LINK_SPEED_25G; 15068 15069 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS); 15070 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS); 15071 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES); 15072 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE); 15073 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE); 15074 /* fix up link widths for emulation _p */ 15075 ppd = dd->pport; 15076 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) { 15077 ppd->link_width_supported = 15078 ppd->link_width_enabled = 15079 ppd->link_width_downgrade_supported = 15080 ppd->link_width_downgrade_enabled = 15081 OPA_LINK_WIDTH_1X; 15082 } 15083 /* insure num_vls isn't larger than number of sdma engines */ 15084 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) { 15085 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n", 15086 num_vls, dd->chip_sdma_engines); 15087 num_vls = dd->chip_sdma_engines; 15088 ppd->vls_supported = dd->chip_sdma_engines; 15089 ppd->vls_operational = ppd->vls_supported; 15090 } 15091 15092 /* 15093 * Convert the ns parameter to the 64 * cclocks used in the CSR. 15094 * Limit the max if larger than the field holds. If timeout is 15095 * non-zero, then the calculated field will be at least 1. 15096 * 15097 * Must be after icode is set up - the cclock rate depends 15098 * on knowing the hardware being used. 15099 */ 15100 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64; 15101 if (dd->rcv_intr_timeout_csr > 15102 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK) 15103 dd->rcv_intr_timeout_csr = 15104 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK; 15105 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout) 15106 dd->rcv_intr_timeout_csr = 1; 15107 15108 /* needs to be done before we look for the peer device */ 15109 read_guid(dd); 15110 15111 /* set up shared ASIC data with peer device */ 15112 ret = init_asic_data(dd); 15113 if (ret) 15114 goto bail_cleanup; 15115 15116 /* obtain chip sizes, reset chip CSRs */ 15117 ret = init_chip(dd); 15118 if (ret) 15119 goto bail_cleanup; 15120 15121 /* read in the PCIe link speed information */ 15122 ret = pcie_speeds(dd); 15123 if (ret) 15124 goto bail_cleanup; 15125 15126 /* call before get_platform_config(), after init_chip_resources() */ 15127 ret = eprom_init(dd); 15128 if (ret) 15129 goto bail_free_rcverr; 15130 15131 /* Needs to be called before hfi1_firmware_init */ 15132 get_platform_config(dd); 15133 15134 /* read in firmware */ 15135 ret = hfi1_firmware_init(dd); 15136 if (ret) 15137 goto bail_cleanup; 15138 15139 /* 15140 * In general, the PCIe Gen3 transition must occur after the 15141 * chip has been idled (so it won't initiate any PCIe transactions 15142 * e.g. an interrupt) and before the driver changes any registers 15143 * (the transition will reset the registers). 15144 * 15145 * In particular, place this call after: 15146 * - init_chip() - the chip will not initiate any PCIe transactions 15147 * - pcie_speeds() - reads the current link speed 15148 * - hfi1_firmware_init() - the needed firmware is ready to be 15149 * downloaded 15150 */ 15151 ret = do_pcie_gen3_transition(dd); 15152 if (ret) 15153 goto bail_cleanup; 15154 15155 /* start setting dd values and adjusting CSRs */ 15156 init_early_variables(dd); 15157 15158 parse_platform_config(dd); 15159 15160 ret = obtain_boardname(dd); 15161 if (ret) 15162 goto bail_cleanup; 15163 15164 snprintf(dd->boardversion, BOARD_VERS_MAX, 15165 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n", 15166 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN, 15167 (u32)dd->majrev, 15168 (u32)dd->minrev, 15169 (dd->revision >> CCE_REVISION_SW_SHIFT) 15170 & CCE_REVISION_SW_MASK); 15171 15172 ret = set_up_context_variables(dd); 15173 if (ret) 15174 goto bail_cleanup; 15175 15176 /* set initial RXE CSRs */ 15177 init_rxe(dd); 15178 /* set initial TXE CSRs */ 15179 init_txe(dd); 15180 /* set initial non-RXE, non-TXE CSRs */ 15181 init_other(dd); 15182 /* set up KDETH QP prefix in both RX and TX CSRs */ 15183 init_kdeth_qp(dd); 15184 15185 ret = hfi1_dev_affinity_init(dd); 15186 if (ret) 15187 goto bail_cleanup; 15188 15189 /* send contexts must be set up before receive contexts */ 15190 ret = init_send_contexts(dd); 15191 if (ret) 15192 goto bail_cleanup; 15193 15194 ret = hfi1_create_kctxts(dd); 15195 if (ret) 15196 goto bail_cleanup; 15197 15198 /* 15199 * Initialize aspm, to be done after gen3 transition and setting up 15200 * contexts and before enabling interrupts 15201 */ 15202 aspm_init(dd); 15203 15204 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE; 15205 /* 15206 * rcd[0] is guaranteed to be valid by this point. Also, all 15207 * context are using the same value, as per the module parameter. 15208 */ 15209 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32); 15210 15211 ret = init_pervl_scs(dd); 15212 if (ret) 15213 goto bail_cleanup; 15214 15215 /* sdma init */ 15216 for (i = 0; i < dd->num_pports; ++i) { 15217 ret = sdma_init(dd, i); 15218 if (ret) 15219 goto bail_cleanup; 15220 } 15221 15222 /* use contexts created by hfi1_create_kctxts */ 15223 ret = set_up_interrupts(dd); 15224 if (ret) 15225 goto bail_cleanup; 15226 15227 /* set up LCB access - must be after set_up_interrupts() */ 15228 init_lcb_access(dd); 15229 15230 /* 15231 * Serial number is created from the base guid: 15232 * [27:24] = base guid [38:35] 15233 * [23: 0] = base guid [23: 0] 15234 */ 15235 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n", 15236 (dd->base_guid & 0xFFFFFF) | 15237 ((dd->base_guid >> 11) & 0xF000000)); 15238 15239 dd->oui1 = dd->base_guid >> 56 & 0xFF; 15240 dd->oui2 = dd->base_guid >> 48 & 0xFF; 15241 dd->oui3 = dd->base_guid >> 40 & 0xFF; 15242 15243 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */ 15244 if (ret) 15245 goto bail_clear_intr; 15246 15247 thermal_init(dd); 15248 15249 ret = init_cntrs(dd); 15250 if (ret) 15251 goto bail_clear_intr; 15252 15253 ret = init_rcverr(dd); 15254 if (ret) 15255 goto bail_free_cntrs; 15256 15257 init_completion(&dd->user_comp); 15258 15259 /* The user refcount starts with one to inidicate an active device */ 15260 atomic_set(&dd->user_refcount, 1); 15261 15262 goto bail; 15263 15264 bail_free_rcverr: 15265 free_rcverr(dd); 15266 bail_free_cntrs: 15267 free_cntrs(dd); 15268 bail_clear_intr: 15269 hfi1_clean_up_interrupts(dd); 15270 bail_cleanup: 15271 hfi1_pcie_ddcleanup(dd); 15272 bail_free: 15273 hfi1_free_devdata(dd); 15274 dd = ERR_PTR(ret); 15275 bail: 15276 return dd; 15277 } 15278 15279 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate, 15280 u32 dw_len) 15281 { 15282 u32 delta_cycles; 15283 u32 current_egress_rate = ppd->current_egress_rate; 15284 /* rates here are in units of 10^6 bits/sec */ 15285 15286 if (desired_egress_rate == -1) 15287 return 0; /* shouldn't happen */ 15288 15289 if (desired_egress_rate >= current_egress_rate) 15290 return 0; /* we can't help go faster, only slower */ 15291 15292 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) - 15293 egress_cycles(dw_len * 4, current_egress_rate); 15294 15295 return (u16)delta_cycles; 15296 } 15297 15298 /** 15299 * create_pbc - build a pbc for transmission 15300 * @flags: special case flags or-ed in built pbc 15301 * @srate: static rate 15302 * @vl: vl 15303 * @dwlen: dword length (header words + data words + pbc words) 15304 * 15305 * Create a PBC with the given flags, rate, VL, and length. 15306 * 15307 * NOTE: The PBC created will not insert any HCRC - all callers but one are 15308 * for verbs, which does not use this PSM feature. The lone other caller 15309 * is for the diagnostic interface which calls this if the user does not 15310 * supply their own PBC. 15311 */ 15312 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, 15313 u32 dw_len) 15314 { 15315 u64 pbc, delay = 0; 15316 15317 if (unlikely(srate_mbs)) 15318 delay = delay_cycles(ppd, srate_mbs, dw_len); 15319 15320 pbc = flags 15321 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT) 15322 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT) 15323 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT 15324 | (dw_len & PBC_LENGTH_DWS_MASK) 15325 << PBC_LENGTH_DWS_SHIFT; 15326 15327 return pbc; 15328 } 15329 15330 #define SBUS_THERMAL 0x4f 15331 #define SBUS_THERM_MONITOR_MODE 0x1 15332 15333 #define THERM_FAILURE(dev, ret, reason) \ 15334 dd_dev_err((dd), \ 15335 "Thermal sensor initialization failed: %s (%d)\n", \ 15336 (reason), (ret)) 15337 15338 /* 15339 * Initialize the thermal sensor. 15340 * 15341 * After initialization, enable polling of thermal sensor through 15342 * SBus interface. In order for this to work, the SBus Master 15343 * firmware has to be loaded due to the fact that the HW polling 15344 * logic uses SBus interrupts, which are not supported with 15345 * default firmware. Otherwise, no data will be returned through 15346 * the ASIC_STS_THERM CSR. 15347 */ 15348 static int thermal_init(struct hfi1_devdata *dd) 15349 { 15350 int ret = 0; 15351 15352 if (dd->icode != ICODE_RTL_SILICON || 15353 check_chip_resource(dd, CR_THERM_INIT, NULL)) 15354 return ret; 15355 15356 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 15357 if (ret) { 15358 THERM_FAILURE(dd, ret, "Acquire SBus"); 15359 return ret; 15360 } 15361 15362 dd_dev_info(dd, "Initializing thermal sensor\n"); 15363 /* Disable polling of thermal readings */ 15364 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 15365 msleep(100); 15366 /* Thermal Sensor Initialization */ 15367 /* Step 1: Reset the Thermal SBus Receiver */ 15368 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15369 RESET_SBUS_RECEIVER, 0); 15370 if (ret) { 15371 THERM_FAILURE(dd, ret, "Bus Reset"); 15372 goto done; 15373 } 15374 /* Step 2: Set Reset bit in Thermal block */ 15375 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15376 WRITE_SBUS_RECEIVER, 0x1); 15377 if (ret) { 15378 THERM_FAILURE(dd, ret, "Therm Block Reset"); 15379 goto done; 15380 } 15381 /* Step 3: Write clock divider value (100MHz -> 2MHz) */ 15382 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1, 15383 WRITE_SBUS_RECEIVER, 0x32); 15384 if (ret) { 15385 THERM_FAILURE(dd, ret, "Write Clock Div"); 15386 goto done; 15387 } 15388 /* Step 4: Select temperature mode */ 15389 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3, 15390 WRITE_SBUS_RECEIVER, 15391 SBUS_THERM_MONITOR_MODE); 15392 if (ret) { 15393 THERM_FAILURE(dd, ret, "Write Mode Sel"); 15394 goto done; 15395 } 15396 /* Step 5: De-assert block reset and start conversion */ 15397 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15398 WRITE_SBUS_RECEIVER, 0x2); 15399 if (ret) { 15400 THERM_FAILURE(dd, ret, "Write Reset Deassert"); 15401 goto done; 15402 } 15403 /* Step 5.1: Wait for first conversion (21.5ms per spec) */ 15404 msleep(22); 15405 15406 /* Enable polling of thermal readings */ 15407 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 15408 15409 /* Set initialized flag */ 15410 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0); 15411 if (ret) 15412 THERM_FAILURE(dd, ret, "Unable to set thermal init flag"); 15413 15414 done: 15415 release_chip_resource(dd, CR_SBUS); 15416 return ret; 15417 } 15418 15419 static void handle_temp_err(struct hfi1_devdata *dd) 15420 { 15421 struct hfi1_pportdata *ppd = &dd->pport[0]; 15422 /* 15423 * Thermal Critical Interrupt 15424 * Put the device into forced freeze mode, take link down to 15425 * offline, and put DC into reset. 15426 */ 15427 dd_dev_emerg(dd, 15428 "Critical temperature reached! Forcing device into freeze mode!\n"); 15429 dd->flags |= HFI1_FORCED_FREEZE; 15430 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT); 15431 /* 15432 * Shut DC down as much and as quickly as possible. 15433 * 15434 * Step 1: Take the link down to OFFLINE. This will cause the 15435 * 8051 to put the Serdes in reset. However, we don't want to 15436 * go through the entire link state machine since we want to 15437 * shutdown ASAP. Furthermore, this is not a graceful shutdown 15438 * but rather an attempt to save the chip. 15439 * Code below is almost the same as quiet_serdes() but avoids 15440 * all the extra work and the sleeps. 15441 */ 15442 ppd->driver_link_ready = 0; 15443 ppd->link_enabled = 0; 15444 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) | 15445 PLS_OFFLINE); 15446 /* 15447 * Step 2: Shutdown LCB and 8051 15448 * After shutdown, do not restore DC_CFG_RESET value. 15449 */ 15450 dc_shutdown(dd); 15451 } 15452