1 /* 2 * Copyright(c) 2015 - 2020 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 /* 49 * This file contains all of the code that is specific to the HFI chip 50 */ 51 52 #include <linux/pci.h> 53 #include <linux/delay.h> 54 #include <linux/interrupt.h> 55 #include <linux/module.h> 56 57 #include "hfi.h" 58 #include "trace.h" 59 #include "mad.h" 60 #include "pio.h" 61 #include "sdma.h" 62 #include "eprom.h" 63 #include "efivar.h" 64 #include "platform.h" 65 #include "aspm.h" 66 #include "affinity.h" 67 #include "debugfs.h" 68 #include "fault.h" 69 #include "netdev.h" 70 71 uint num_vls = HFI1_MAX_VLS_SUPPORTED; 72 module_param(num_vls, uint, S_IRUGO); 73 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 74 75 /* 76 * Default time to aggregate two 10K packets from the idle state 77 * (timer not running). The timer starts at the end of the first packet, 78 * so only the time for one 10K packet and header plus a bit extra is needed. 79 * 10 * 1024 + 64 header byte = 10304 byte 80 * 10304 byte / 12.5 GB/s = 824.32ns 81 */ 82 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */ 83 module_param(rcv_intr_timeout, uint, S_IRUGO); 84 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns"); 85 86 uint rcv_intr_count = 16; /* same as qib */ 87 module_param(rcv_intr_count, uint, S_IRUGO); 88 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count"); 89 90 ushort link_crc_mask = SUPPORTED_CRCS; 91 module_param(link_crc_mask, ushort, S_IRUGO); 92 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link"); 93 94 uint loopback; 95 module_param_named(loopback, loopback, uint, S_IRUGO); 96 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable"); 97 98 /* Other driver tunables */ 99 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/ 100 static ushort crc_14b_sideband = 1; 101 static uint use_flr = 1; 102 uint quick_linkup; /* skip LNI */ 103 104 struct flag_table { 105 u64 flag; /* the flag */ 106 char *str; /* description string */ 107 u16 extra; /* extra information */ 108 u16 unused0; 109 u32 unused1; 110 }; 111 112 /* str must be a string constant */ 113 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra} 114 #define FLAG_ENTRY0(str, flag) {flag, str, 0} 115 116 /* Send Error Consequences */ 117 #define SEC_WRITE_DROPPED 0x1 118 #define SEC_PACKET_DROPPED 0x2 119 #define SEC_SC_HALTED 0x4 /* per-context only */ 120 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */ 121 122 #define DEFAULT_KRCVQS 2 123 #define MIN_KERNEL_KCTXTS 2 124 #define FIRST_KERNEL_KCTXT 1 125 126 /* 127 * RSM instance allocation 128 * 0 - User Fecn Handling 129 * 1 - Vnic 130 * 2 - AIP 131 * 3 - Verbs 132 */ 133 #define RSM_INS_FECN 0 134 #define RSM_INS_VNIC 1 135 #define RSM_INS_AIP 2 136 #define RSM_INS_VERBS 3 137 138 /* Bit offset into the GUID which carries HFI id information */ 139 #define GUID_HFI_INDEX_SHIFT 39 140 141 /* extract the emulation revision */ 142 #define emulator_rev(dd) ((dd)->irev >> 8) 143 /* parallel and serial emulation versions are 3 and 4 respectively */ 144 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3) 145 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4) 146 147 /* RSM fields for Verbs */ 148 /* packet type */ 149 #define IB_PACKET_TYPE 2ull 150 #define QW_SHIFT 6ull 151 /* QPN[7..1] */ 152 #define QPN_WIDTH 7ull 153 154 /* LRH.BTH: QW 0, OFFSET 48 - for match */ 155 #define LRH_BTH_QW 0ull 156 #define LRH_BTH_BIT_OFFSET 48ull 157 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off)) 158 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET) 159 #define LRH_BTH_SELECT 160 #define LRH_BTH_MASK 3ull 161 #define LRH_BTH_VALUE 2ull 162 163 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */ 164 #define LRH_SC_QW 0ull 165 #define LRH_SC_BIT_OFFSET 56ull 166 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off)) 167 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET) 168 #define LRH_SC_MASK 128ull 169 #define LRH_SC_VALUE 0ull 170 171 /* SC[n..0] QW 0, OFFSET 60 - for select */ 172 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull)) 173 174 /* QPN[m+n:1] QW 1, OFFSET 1 */ 175 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull)) 176 177 /* RSM fields for AIP */ 178 /* LRH.BTH above is reused for this rule */ 179 180 /* BTH.DESTQP: QW 1, OFFSET 16 for match */ 181 #define BTH_DESTQP_QW 1ull 182 #define BTH_DESTQP_BIT_OFFSET 16ull 183 #define BTH_DESTQP_OFFSET(off) ((BTH_DESTQP_QW << QW_SHIFT) | (off)) 184 #define BTH_DESTQP_MATCH_OFFSET BTH_DESTQP_OFFSET(BTH_DESTQP_BIT_OFFSET) 185 #define BTH_DESTQP_MASK 0xFFull 186 #define BTH_DESTQP_VALUE 0x81ull 187 188 /* DETH.SQPN: QW 1 Offset 56 for select */ 189 /* We use 8 most significant Soure QPN bits as entropy fpr AIP */ 190 #define DETH_AIP_SQPN_QW 3ull 191 #define DETH_AIP_SQPN_BIT_OFFSET 56ull 192 #define DETH_AIP_SQPN_OFFSET(off) ((DETH_AIP_SQPN_QW << QW_SHIFT) | (off)) 193 #define DETH_AIP_SQPN_SELECT_OFFSET \ 194 DETH_AIP_SQPN_OFFSET(DETH_AIP_SQPN_BIT_OFFSET) 195 196 /* RSM fields for Vnic */ 197 /* L2_TYPE: QW 0, OFFSET 61 - for match */ 198 #define L2_TYPE_QW 0ull 199 #define L2_TYPE_BIT_OFFSET 61ull 200 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off)) 201 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET) 202 #define L2_TYPE_MASK 3ull 203 #define L2_16B_VALUE 2ull 204 205 /* L4_TYPE QW 1, OFFSET 0 - for match */ 206 #define L4_TYPE_QW 1ull 207 #define L4_TYPE_BIT_OFFSET 0ull 208 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off)) 209 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET) 210 #define L4_16B_TYPE_MASK 0xFFull 211 #define L4_16B_ETH_VALUE 0x78ull 212 213 /* 16B VESWID - for select */ 214 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull)) 215 /* 16B ENTROPY - for select */ 216 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull)) 217 218 /* defines to build power on SC2VL table */ 219 #define SC2VL_VAL( \ 220 num, \ 221 sc0, sc0val, \ 222 sc1, sc1val, \ 223 sc2, sc2val, \ 224 sc3, sc3val, \ 225 sc4, sc4val, \ 226 sc5, sc5val, \ 227 sc6, sc6val, \ 228 sc7, sc7val) \ 229 ( \ 230 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \ 231 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \ 232 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \ 233 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \ 234 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \ 235 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \ 236 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \ 237 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \ 238 ) 239 240 #define DC_SC_VL_VAL( \ 241 range, \ 242 e0, e0val, \ 243 e1, e1val, \ 244 e2, e2val, \ 245 e3, e3val, \ 246 e4, e4val, \ 247 e5, e5val, \ 248 e6, e6val, \ 249 e7, e7val, \ 250 e8, e8val, \ 251 e9, e9val, \ 252 e10, e10val, \ 253 e11, e11val, \ 254 e12, e12val, \ 255 e13, e13val, \ 256 e14, e14val, \ 257 e15, e15val) \ 258 ( \ 259 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \ 260 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \ 261 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \ 262 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \ 263 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \ 264 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \ 265 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \ 266 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \ 267 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \ 268 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \ 269 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \ 270 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \ 271 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \ 272 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \ 273 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \ 274 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \ 275 ) 276 277 /* all CceStatus sub-block freeze bits */ 278 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \ 279 | CCE_STATUS_RXE_FROZE_SMASK \ 280 | CCE_STATUS_TXE_FROZE_SMASK \ 281 | CCE_STATUS_TXE_PIO_FROZE_SMASK) 282 /* all CceStatus sub-block TXE pause bits */ 283 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \ 284 | CCE_STATUS_TXE_PAUSED_SMASK \ 285 | CCE_STATUS_SDMA_PAUSED_SMASK) 286 /* all CceStatus sub-block RXE pause bits */ 287 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK 288 289 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL 290 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF 291 292 /* 293 * CCE Error flags. 294 */ 295 static struct flag_table cce_err_status_flags[] = { 296 /* 0*/ FLAG_ENTRY0("CceCsrParityErr", 297 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK), 298 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr", 299 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK), 300 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr", 301 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK), 302 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr", 303 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK), 304 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr", 305 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK), 306 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr", 307 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK), 308 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr", 309 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK), 310 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr", 311 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK), 312 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr", 313 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK), 314 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 315 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK), 316 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 317 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK), 318 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError", 319 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK), 320 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError", 321 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK), 322 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr", 323 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK), 324 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr", 325 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK), 326 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr", 327 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK), 328 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr", 329 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK), 330 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr", 331 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK), 332 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr", 333 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK), 334 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr", 335 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK), 336 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr", 337 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK), 338 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr", 339 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK), 340 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr", 341 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK), 342 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr", 343 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK), 344 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr", 345 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK), 346 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr", 347 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK), 348 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr", 349 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK), 350 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr", 351 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK), 352 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr", 353 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK), 354 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr", 355 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK), 356 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr", 357 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK), 358 /*31*/ FLAG_ENTRY0("LATriggered", 359 CCE_ERR_STATUS_LA_TRIGGERED_SMASK), 360 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr", 361 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK), 362 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr", 363 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK), 364 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr", 365 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK), 366 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr", 367 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK), 368 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr", 369 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK), 370 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr", 371 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK), 372 /*38*/ FLAG_ENTRY0("CceIntMapCorErr", 373 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK), 374 /*39*/ FLAG_ENTRY0("CceIntMapUncErr", 375 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK), 376 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr", 377 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK), 378 /*41-63 reserved*/ 379 }; 380 381 /* 382 * Misc Error flags 383 */ 384 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK 385 static struct flag_table misc_err_status_flags[] = { 386 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)), 387 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)), 388 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)), 389 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)), 390 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)), 391 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)), 392 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)), 393 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)), 394 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)), 395 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)), 396 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)), 397 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)), 398 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL)) 399 }; 400 401 /* 402 * TXE PIO Error flags and consequences 403 */ 404 static struct flag_table pio_err_status_flags[] = { 405 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt", 406 SEC_WRITE_DROPPED, 407 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK), 408 /* 1*/ FLAG_ENTRY("PioWriteAddrParity", 409 SEC_SPC_FREEZE, 410 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK), 411 /* 2*/ FLAG_ENTRY("PioCsrParity", 412 SEC_SPC_FREEZE, 413 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK), 414 /* 3*/ FLAG_ENTRY("PioSbMemFifo0", 415 SEC_SPC_FREEZE, 416 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK), 417 /* 4*/ FLAG_ENTRY("PioSbMemFifo1", 418 SEC_SPC_FREEZE, 419 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK), 420 /* 5*/ FLAG_ENTRY("PioPccFifoParity", 421 SEC_SPC_FREEZE, 422 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK), 423 /* 6*/ FLAG_ENTRY("PioPecFifoParity", 424 SEC_SPC_FREEZE, 425 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK), 426 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity", 427 SEC_SPC_FREEZE, 428 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK), 429 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity", 430 SEC_SPC_FREEZE, 431 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK), 432 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr", 433 SEC_SPC_FREEZE, 434 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK), 435 /*10*/ FLAG_ENTRY("PioSmPktResetParity", 436 SEC_SPC_FREEZE, 437 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK), 438 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc", 439 SEC_SPC_FREEZE, 440 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK), 441 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc", 442 SEC_SPC_FREEZE, 443 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK), 444 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor", 445 0, 446 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK), 447 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor", 448 0, 449 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK), 450 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity", 451 SEC_SPC_FREEZE, 452 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK), 453 /*16*/ FLAG_ENTRY("PioPpmcPblFifo", 454 SEC_SPC_FREEZE, 455 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK), 456 /*17*/ FLAG_ENTRY("PioInitSmIn", 457 0, 458 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK), 459 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm", 460 SEC_SPC_FREEZE, 461 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK), 462 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc", 463 SEC_SPC_FREEZE, 464 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK), 465 /*20*/ FLAG_ENTRY("PioHostAddrMemCor", 466 0, 467 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK), 468 /*21*/ FLAG_ENTRY("PioWriteDataParity", 469 SEC_SPC_FREEZE, 470 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK), 471 /*22*/ FLAG_ENTRY("PioStateMachine", 472 SEC_SPC_FREEZE, 473 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK), 474 /*23*/ FLAG_ENTRY("PioWriteQwValidParity", 475 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 476 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK), 477 /*24*/ FLAG_ENTRY("PioBlockQwCountParity", 478 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 479 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK), 480 /*25*/ FLAG_ENTRY("PioVlfVlLenParity", 481 SEC_SPC_FREEZE, 482 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK), 483 /*26*/ FLAG_ENTRY("PioVlfSopParity", 484 SEC_SPC_FREEZE, 485 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK), 486 /*27*/ FLAG_ENTRY("PioVlFifoParity", 487 SEC_SPC_FREEZE, 488 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK), 489 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity", 490 SEC_SPC_FREEZE, 491 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK), 492 /*29*/ FLAG_ENTRY("PioPpmcSopLen", 493 SEC_SPC_FREEZE, 494 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK), 495 /*30-31 reserved*/ 496 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity", 497 SEC_SPC_FREEZE, 498 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK), 499 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity", 500 SEC_SPC_FREEZE, 501 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK), 502 /*34*/ FLAG_ENTRY("PioPccSopHeadParity", 503 SEC_SPC_FREEZE, 504 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK), 505 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr", 506 SEC_SPC_FREEZE, 507 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK), 508 /*36-63 reserved*/ 509 }; 510 511 /* TXE PIO errors that cause an SPC freeze */ 512 #define ALL_PIO_FREEZE_ERR \ 513 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \ 514 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \ 515 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \ 516 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \ 517 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \ 518 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \ 519 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \ 520 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 521 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \ 522 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \ 523 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \ 524 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \ 525 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \ 526 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \ 527 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \ 528 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \ 529 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \ 530 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \ 531 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \ 532 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 533 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \ 534 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \ 535 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \ 536 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \ 537 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \ 538 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 539 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 540 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 541 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK) 542 543 /* 544 * TXE SDMA Error flags 545 */ 546 static struct flag_table sdma_err_status_flags[] = { 547 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr", 548 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK), 549 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr", 550 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK), 551 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr", 552 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK), 553 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr", 554 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK), 555 /*04-63 reserved*/ 556 }; 557 558 /* TXE SDMA errors that cause an SPC freeze */ 559 #define ALL_SDMA_FREEZE_ERR \ 560 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \ 561 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \ 562 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK) 563 564 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */ 565 #define PORT_DISCARD_EGRESS_ERRS \ 566 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \ 567 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \ 568 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK) 569 570 /* 571 * TXE Egress Error flags 572 */ 573 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK 574 static struct flag_table egress_err_status_flags[] = { 575 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)), 576 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)), 577 /* 2 reserved */ 578 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr", 579 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)), 580 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)), 581 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)), 582 /* 6 reserved */ 583 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr", 584 SEES(TX_PIO_LAUNCH_INTF_PARITY)), 585 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr", 586 SEES(TX_SDMA_LAUNCH_INTF_PARITY)), 587 /* 9-10 reserved */ 588 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr", 589 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)), 590 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)), 591 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)), 592 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)), 593 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)), 594 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr", 595 SEES(TX_SDMA0_DISALLOWED_PACKET)), 596 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr", 597 SEES(TX_SDMA1_DISALLOWED_PACKET)), 598 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr", 599 SEES(TX_SDMA2_DISALLOWED_PACKET)), 600 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr", 601 SEES(TX_SDMA3_DISALLOWED_PACKET)), 602 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr", 603 SEES(TX_SDMA4_DISALLOWED_PACKET)), 604 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr", 605 SEES(TX_SDMA5_DISALLOWED_PACKET)), 606 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr", 607 SEES(TX_SDMA6_DISALLOWED_PACKET)), 608 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr", 609 SEES(TX_SDMA7_DISALLOWED_PACKET)), 610 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr", 611 SEES(TX_SDMA8_DISALLOWED_PACKET)), 612 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr", 613 SEES(TX_SDMA9_DISALLOWED_PACKET)), 614 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr", 615 SEES(TX_SDMA10_DISALLOWED_PACKET)), 616 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr", 617 SEES(TX_SDMA11_DISALLOWED_PACKET)), 618 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr", 619 SEES(TX_SDMA12_DISALLOWED_PACKET)), 620 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr", 621 SEES(TX_SDMA13_DISALLOWED_PACKET)), 622 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr", 623 SEES(TX_SDMA14_DISALLOWED_PACKET)), 624 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr", 625 SEES(TX_SDMA15_DISALLOWED_PACKET)), 626 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr", 627 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)), 628 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr", 629 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)), 630 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr", 631 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)), 632 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr", 633 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)), 634 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr", 635 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)), 636 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr", 637 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)), 638 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr", 639 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)), 640 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr", 641 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)), 642 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr", 643 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)), 644 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)), 645 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)), 646 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)), 647 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)), 648 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)), 649 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)), 650 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)), 651 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)), 652 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)), 653 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)), 654 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)), 655 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)), 656 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)), 657 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)), 658 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)), 659 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)), 660 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)), 661 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)), 662 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)), 663 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)), 664 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)), 665 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr", 666 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)), 667 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr", 668 SEES(TX_READ_PIO_MEMORY_CSR_UNC)), 669 }; 670 671 /* 672 * TXE Egress Error Info flags 673 */ 674 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK 675 static struct flag_table egress_err_info_flags[] = { 676 /* 0*/ FLAG_ENTRY0("Reserved", 0ull), 677 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)), 678 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 679 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 680 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)), 681 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)), 682 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)), 683 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)), 684 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)), 685 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)), 686 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)), 687 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)), 688 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)), 689 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)), 690 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)), 691 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)), 692 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)), 693 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)), 694 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)), 695 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)), 696 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)), 697 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)), 698 }; 699 700 /* TXE Egress errors that cause an SPC freeze */ 701 #define ALL_TXE_EGRESS_FREEZE_ERR \ 702 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \ 703 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \ 704 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \ 705 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \ 706 | SEES(TX_LAUNCH_CSR_PARITY) \ 707 | SEES(TX_SBRD_CTL_CSR_PARITY) \ 708 | SEES(TX_CONFIG_PARITY) \ 709 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \ 710 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \ 711 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \ 712 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \ 713 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \ 714 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \ 715 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \ 716 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \ 717 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \ 718 | SEES(TX_CREDIT_RETURN_PARITY)) 719 720 /* 721 * TXE Send error flags 722 */ 723 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK 724 static struct flag_table send_err_status_flags[] = { 725 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)), 726 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)), 727 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR)) 728 }; 729 730 /* 731 * TXE Send Context Error flags and consequences 732 */ 733 static struct flag_table sc_err_status_flags[] = { 734 /* 0*/ FLAG_ENTRY("InconsistentSop", 735 SEC_PACKET_DROPPED | SEC_SC_HALTED, 736 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK), 737 /* 1*/ FLAG_ENTRY("DisallowedPacket", 738 SEC_PACKET_DROPPED | SEC_SC_HALTED, 739 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK), 740 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary", 741 SEC_WRITE_DROPPED | SEC_SC_HALTED, 742 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK), 743 /* 3*/ FLAG_ENTRY("WriteOverflow", 744 SEC_WRITE_DROPPED | SEC_SC_HALTED, 745 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK), 746 /* 4*/ FLAG_ENTRY("WriteOutOfBounds", 747 SEC_WRITE_DROPPED | SEC_SC_HALTED, 748 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK), 749 /* 5-63 reserved*/ 750 }; 751 752 /* 753 * RXE Receive Error flags 754 */ 755 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK 756 static struct flag_table rxe_err_status_flags[] = { 757 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)), 758 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)), 759 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)), 760 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)), 761 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)), 762 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)), 763 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)), 764 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)), 765 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)), 766 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)), 767 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)), 768 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)), 769 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)), 770 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)), 771 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)), 772 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)), 773 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr", 774 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)), 775 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)), 776 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)), 777 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr", 778 RXES(RBUF_BLOCK_LIST_READ_UNC)), 779 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr", 780 RXES(RBUF_BLOCK_LIST_READ_COR)), 781 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr", 782 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)), 783 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr", 784 RXES(RBUF_CSR_QENT_CNT_PARITY)), 785 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr", 786 RXES(RBUF_CSR_QNEXT_BUF_PARITY)), 787 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr", 788 RXES(RBUF_CSR_QVLD_BIT_PARITY)), 789 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)), 790 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)), 791 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr", 792 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)), 793 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)), 794 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)), 795 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)), 796 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)), 797 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)), 798 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)), 799 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)), 800 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr", 801 RXES(RBUF_FL_INITDONE_PARITY)), 802 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr", 803 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)), 804 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)), 805 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)), 806 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)), 807 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr", 808 RXES(LOOKUP_DES_PART1_UNC_COR)), 809 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr", 810 RXES(LOOKUP_DES_PART2_PARITY)), 811 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)), 812 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)), 813 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)), 814 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)), 815 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)), 816 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)), 817 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)), 818 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)), 819 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)), 820 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)), 821 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)), 822 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)), 823 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)), 824 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)), 825 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)), 826 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)), 827 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)), 828 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)), 829 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)), 830 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)), 831 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)), 832 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY)) 833 }; 834 835 /* RXE errors that will trigger an SPC freeze */ 836 #define ALL_RXE_FREEZE_ERR \ 837 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \ 838 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \ 839 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \ 840 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \ 841 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \ 842 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \ 843 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \ 844 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \ 845 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \ 846 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 847 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \ 848 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \ 849 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \ 850 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \ 851 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \ 852 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 853 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \ 854 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \ 855 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \ 856 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \ 857 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \ 858 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \ 859 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \ 860 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \ 861 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 862 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \ 863 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \ 864 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 865 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 866 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \ 867 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \ 868 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \ 869 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \ 870 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \ 871 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \ 872 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \ 873 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \ 874 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 875 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \ 876 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \ 877 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 878 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 879 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \ 880 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK) 881 882 #define RXE_FREEZE_ABORT_MASK \ 883 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \ 884 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \ 885 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK) 886 887 /* 888 * DCC Error Flags 889 */ 890 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK 891 static struct flag_table dcc_err_flags[] = { 892 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)), 893 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)), 894 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)), 895 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)), 896 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)), 897 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)), 898 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)), 899 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)), 900 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)), 901 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)), 902 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)), 903 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)), 904 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)), 905 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)), 906 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)), 907 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)), 908 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)), 909 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)), 910 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)), 911 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)), 912 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)), 913 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)), 914 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)), 915 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)), 916 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)), 917 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)), 918 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)), 919 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)), 920 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)), 921 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)), 922 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)), 923 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)), 924 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)), 925 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)), 926 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)), 927 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)), 928 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)), 929 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)), 930 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)), 931 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)), 932 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)), 933 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)), 934 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)), 935 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)), 936 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)), 937 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)), 938 }; 939 940 /* 941 * LCB error flags 942 */ 943 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK 944 static struct flag_table lcb_err_flags[] = { 945 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)), 946 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)), 947 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)), 948 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST", 949 LCBE(ALL_LNS_FAILED_REINIT_TEST)), 950 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)), 951 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)), 952 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)), 953 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)), 954 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)), 955 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)), 956 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)), 957 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)), 958 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)), 959 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER", 960 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)), 961 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)), 962 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)), 963 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)), 964 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)), 965 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)), 966 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE", 967 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)), 968 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)), 969 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)), 970 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)), 971 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)), 972 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)), 973 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)), 974 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP", 975 LCBE(RST_FOR_INCOMPLT_RND_TRIP)), 976 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)), 977 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE", 978 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)), 979 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR", 980 LCBE(REDUNDANT_FLIT_PARITY_ERR)) 981 }; 982 983 /* 984 * DC8051 Error Flags 985 */ 986 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK 987 static struct flag_table dc8051_err_flags[] = { 988 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)), 989 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)), 990 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)), 991 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)), 992 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)), 993 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)), 994 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)), 995 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)), 996 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES", 997 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)), 998 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)), 999 }; 1000 1001 /* 1002 * DC8051 Information Error flags 1003 * 1004 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field. 1005 */ 1006 static struct flag_table dc8051_info_err_flags[] = { 1007 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED), 1008 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME), 1009 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET), 1010 FLAG_ENTRY0("Serdes internal loopback failure", 1011 FAILED_SERDES_INTERNAL_LOOPBACK), 1012 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT), 1013 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING), 1014 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE), 1015 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM), 1016 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ), 1017 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1), 1018 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2), 1019 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT), 1020 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT), 1021 FLAG_ENTRY0("External Device Request Timeout", 1022 EXTERNAL_DEVICE_REQ_TIMEOUT), 1023 }; 1024 1025 /* 1026 * DC8051 Information Host Information flags 1027 * 1028 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field. 1029 */ 1030 static struct flag_table dc8051_info_host_msg_flags[] = { 1031 FLAG_ENTRY0("Host request done", 0x0001), 1032 FLAG_ENTRY0("BC PWR_MGM message", 0x0002), 1033 FLAG_ENTRY0("BC SMA message", 0x0004), 1034 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008), 1035 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010), 1036 FLAG_ENTRY0("External device config request", 0x0020), 1037 FLAG_ENTRY0("VerifyCap all frames received", 0x0040), 1038 FLAG_ENTRY0("LinkUp achieved", 0x0080), 1039 FLAG_ENTRY0("Link going down", 0x0100), 1040 FLAG_ENTRY0("Link width downgraded", 0x0200), 1041 }; 1042 1043 static u32 encoded_size(u32 size); 1044 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate); 1045 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state); 1046 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 1047 u8 *continuous); 1048 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 1049 u8 *vcu, u16 *vl15buf, u8 *crc_sizes); 1050 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 1051 u8 *remote_tx_rate, u16 *link_widths); 1052 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 1053 u8 *flag_bits, u16 *link_widths); 1054 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 1055 u8 *device_rev); 1056 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx); 1057 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx, 1058 u8 *tx_polarity_inversion, 1059 u8 *rx_polarity_inversion, u8 *max_rate); 1060 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 1061 unsigned int context, u64 err_status); 1062 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg); 1063 static void handle_dcc_err(struct hfi1_devdata *dd, 1064 unsigned int context, u64 err_status); 1065 static void handle_lcb_err(struct hfi1_devdata *dd, 1066 unsigned int context, u64 err_status); 1067 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg); 1068 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1069 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1070 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1071 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1072 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1073 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1074 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1075 static void set_partition_keys(struct hfi1_pportdata *ppd); 1076 static const char *link_state_name(u32 state); 1077 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, 1078 u32 state); 1079 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 1080 u64 *out_data); 1081 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data); 1082 static int thermal_init(struct hfi1_devdata *dd); 1083 1084 static void update_statusp(struct hfi1_pportdata *ppd, u32 state); 1085 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 1086 int msecs); 1087 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1088 int msecs); 1089 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state); 1090 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state); 1091 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1092 int msecs); 1093 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd, 1094 int msecs); 1095 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc); 1096 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr); 1097 static void handle_temp_err(struct hfi1_devdata *dd); 1098 static void dc_shutdown(struct hfi1_devdata *dd); 1099 static void dc_start(struct hfi1_devdata *dd); 1100 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 1101 unsigned int *np); 1102 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd); 1103 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms); 1104 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index); 1105 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width); 1106 1107 /* 1108 * Error interrupt table entry. This is used as input to the interrupt 1109 * "clear down" routine used for all second tier error interrupt register. 1110 * Second tier interrupt registers have a single bit representing them 1111 * in the top-level CceIntStatus. 1112 */ 1113 struct err_reg_info { 1114 u32 status; /* status CSR offset */ 1115 u32 clear; /* clear CSR offset */ 1116 u32 mask; /* mask CSR offset */ 1117 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg); 1118 const char *desc; 1119 }; 1120 1121 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START) 1122 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START) 1123 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START) 1124 1125 /* 1126 * Helpers for building HFI and DC error interrupt table entries. Different 1127 * helpers are needed because of inconsistent register names. 1128 */ 1129 #define EE(reg, handler, desc) \ 1130 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ 1131 handler, desc } 1132 #define DC_EE1(reg, handler, desc) \ 1133 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc } 1134 #define DC_EE2(reg, handler, desc) \ 1135 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc } 1136 1137 /* 1138 * Table of the "misc" grouping of error interrupts. Each entry refers to 1139 * another register containing more information. 1140 */ 1141 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = { 1142 /* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"), 1143 /* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"), 1144 /* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"), 1145 /* 3*/ { 0, 0, 0, NULL }, /* reserved */ 1146 /* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"), 1147 /* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"), 1148 /* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"), 1149 /* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr") 1150 /* the rest are reserved */ 1151 }; 1152 1153 /* 1154 * Index into the Various section of the interrupt sources 1155 * corresponding to the Critical Temperature interrupt. 1156 */ 1157 #define TCRIT_INT_SOURCE 4 1158 1159 /* 1160 * SDMA error interrupt entry - refers to another register containing more 1161 * information. 1162 */ 1163 static const struct err_reg_info sdma_eng_err = 1164 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr"); 1165 1166 static const struct err_reg_info various_err[NUM_VARIOUS] = { 1167 /* 0*/ { 0, 0, 0, NULL }, /* PbcInt */ 1168 /* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */ 1169 /* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"), 1170 /* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"), 1171 /* 4*/ { 0, 0, 0, NULL }, /* TCritInt */ 1172 /* rest are reserved */ 1173 }; 1174 1175 /* 1176 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG 1177 * register can not be derived from the MTU value because 10K is not 1178 * a power of 2. Therefore, we need a constant. Everything else can 1179 * be calculated. 1180 */ 1181 #define DCC_CFG_PORT_MTU_CAP_10240 7 1182 1183 /* 1184 * Table of the DC grouping of error interrupts. Each entry refers to 1185 * another register containing more information. 1186 */ 1187 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = { 1188 /* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"), 1189 /* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"), 1190 /* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"), 1191 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */ 1192 /* the rest are reserved */ 1193 }; 1194 1195 struct cntr_entry { 1196 /* 1197 * counter name 1198 */ 1199 char *name; 1200 1201 /* 1202 * csr to read for name (if applicable) 1203 */ 1204 u64 csr; 1205 1206 /* 1207 * offset into dd or ppd to store the counter's value 1208 */ 1209 int offset; 1210 1211 /* 1212 * flags 1213 */ 1214 u8 flags; 1215 1216 /* 1217 * accessor for stat element, context either dd or ppd 1218 */ 1219 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl, 1220 int mode, u64 data); 1221 }; 1222 1223 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0 1224 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159 1225 1226 #define CNTR_ELEM(name, csr, offset, flags, accessor) \ 1227 { \ 1228 name, \ 1229 csr, \ 1230 offset, \ 1231 flags, \ 1232 accessor \ 1233 } 1234 1235 /* 32bit RXE */ 1236 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1237 CNTR_ELEM(#name, \ 1238 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1239 0, flags | CNTR_32BIT, \ 1240 port_access_u32_csr) 1241 1242 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \ 1243 CNTR_ELEM(#name, \ 1244 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1245 0, flags | CNTR_32BIT, \ 1246 dev_access_u32_csr) 1247 1248 /* 64bit RXE */ 1249 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1250 CNTR_ELEM(#name, \ 1251 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1252 0, flags, \ 1253 port_access_u64_csr) 1254 1255 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \ 1256 CNTR_ELEM(#name, \ 1257 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1258 0, flags, \ 1259 dev_access_u64_csr) 1260 1261 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx 1262 #define OVR_ELM(ctx) \ 1263 CNTR_ELEM("RcvHdrOvr" #ctx, \ 1264 (RCV_HDR_OVFL_CNT + ctx * 0x100), \ 1265 0, CNTR_NORMAL, port_access_u64_csr) 1266 1267 /* 32bit TXE */ 1268 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1269 CNTR_ELEM(#name, \ 1270 (counter * 8 + SEND_COUNTER_ARRAY32), \ 1271 0, flags | CNTR_32BIT, \ 1272 port_access_u32_csr) 1273 1274 /* 64bit TXE */ 1275 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1276 CNTR_ELEM(#name, \ 1277 (counter * 8 + SEND_COUNTER_ARRAY64), \ 1278 0, flags, \ 1279 port_access_u64_csr) 1280 1281 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \ 1282 CNTR_ELEM(#name,\ 1283 counter * 8 + SEND_COUNTER_ARRAY64, \ 1284 0, \ 1285 flags, \ 1286 dev_access_u64_csr) 1287 1288 /* CCE */ 1289 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \ 1290 CNTR_ELEM(#name, \ 1291 (counter * 8 + CCE_COUNTER_ARRAY32), \ 1292 0, flags | CNTR_32BIT, \ 1293 dev_access_u32_csr) 1294 1295 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \ 1296 CNTR_ELEM(#name, \ 1297 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \ 1298 0, flags | CNTR_32BIT, \ 1299 dev_access_u32_csr) 1300 1301 /* DC */ 1302 #define DC_PERF_CNTR(name, counter, flags) \ 1303 CNTR_ELEM(#name, \ 1304 counter, \ 1305 0, \ 1306 flags, \ 1307 dev_access_u64_csr) 1308 1309 #define DC_PERF_CNTR_LCB(name, counter, flags) \ 1310 CNTR_ELEM(#name, \ 1311 counter, \ 1312 0, \ 1313 flags, \ 1314 dc_access_lcb_cntr) 1315 1316 /* ibp counters */ 1317 #define SW_IBP_CNTR(name, cntr) \ 1318 CNTR_ELEM(#name, \ 1319 0, \ 1320 0, \ 1321 CNTR_SYNTH, \ 1322 access_ibp_##cntr) 1323 1324 /** 1325 * hfi_addr_from_offset - return addr for readq/writeq 1326 * @dd - the dd device 1327 * @offset - the offset of the CSR within bar0 1328 * 1329 * This routine selects the appropriate base address 1330 * based on the indicated offset. 1331 */ 1332 static inline void __iomem *hfi1_addr_from_offset( 1333 const struct hfi1_devdata *dd, 1334 u32 offset) 1335 { 1336 if (offset >= dd->base2_start) 1337 return dd->kregbase2 + (offset - dd->base2_start); 1338 return dd->kregbase1 + offset; 1339 } 1340 1341 /** 1342 * read_csr - read CSR at the indicated offset 1343 * @dd - the dd device 1344 * @offset - the offset of the CSR within bar0 1345 * 1346 * Return: the value read or all FF's if there 1347 * is no mapping 1348 */ 1349 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) 1350 { 1351 if (dd->flags & HFI1_PRESENT) 1352 return readq(hfi1_addr_from_offset(dd, offset)); 1353 return -1; 1354 } 1355 1356 /** 1357 * write_csr - write CSR at the indicated offset 1358 * @dd - the dd device 1359 * @offset - the offset of the CSR within bar0 1360 * @value - value to write 1361 */ 1362 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) 1363 { 1364 if (dd->flags & HFI1_PRESENT) { 1365 void __iomem *base = hfi1_addr_from_offset(dd, offset); 1366 1367 /* avoid write to RcvArray */ 1368 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start)) 1369 return; 1370 writeq(value, base); 1371 } 1372 } 1373 1374 /** 1375 * get_csr_addr - return te iomem address for offset 1376 * @dd - the dd device 1377 * @offset - the offset of the CSR within bar0 1378 * 1379 * Return: The iomem address to use in subsequent 1380 * writeq/readq operations. 1381 */ 1382 void __iomem *get_csr_addr( 1383 const struct hfi1_devdata *dd, 1384 u32 offset) 1385 { 1386 if (dd->flags & HFI1_PRESENT) 1387 return hfi1_addr_from_offset(dd, offset); 1388 return NULL; 1389 } 1390 1391 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr, 1392 int mode, u64 value) 1393 { 1394 u64 ret; 1395 1396 if (mode == CNTR_MODE_R) { 1397 ret = read_csr(dd, csr); 1398 } else if (mode == CNTR_MODE_W) { 1399 write_csr(dd, csr, value); 1400 ret = value; 1401 } else { 1402 dd_dev_err(dd, "Invalid cntr register access mode"); 1403 return 0; 1404 } 1405 1406 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode); 1407 return ret; 1408 } 1409 1410 /* Dev Access */ 1411 static u64 dev_access_u32_csr(const struct cntr_entry *entry, 1412 void *context, int vl, int mode, u64 data) 1413 { 1414 struct hfi1_devdata *dd = context; 1415 u64 csr = entry->csr; 1416 1417 if (entry->flags & CNTR_SDMA) { 1418 if (vl == CNTR_INVALID_VL) 1419 return 0; 1420 csr += 0x100 * vl; 1421 } else { 1422 if (vl != CNTR_INVALID_VL) 1423 return 0; 1424 } 1425 return read_write_csr(dd, csr, mode, data); 1426 } 1427 1428 static u64 access_sde_err_cnt(const struct cntr_entry *entry, 1429 void *context, int idx, int mode, u64 data) 1430 { 1431 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1432 1433 if (dd->per_sdma && idx < dd->num_sdma) 1434 return dd->per_sdma[idx].err_cnt; 1435 return 0; 1436 } 1437 1438 static u64 access_sde_int_cnt(const struct cntr_entry *entry, 1439 void *context, int idx, int mode, u64 data) 1440 { 1441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1442 1443 if (dd->per_sdma && idx < dd->num_sdma) 1444 return dd->per_sdma[idx].sdma_int_cnt; 1445 return 0; 1446 } 1447 1448 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry, 1449 void *context, int idx, int mode, u64 data) 1450 { 1451 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1452 1453 if (dd->per_sdma && idx < dd->num_sdma) 1454 return dd->per_sdma[idx].idle_int_cnt; 1455 return 0; 1456 } 1457 1458 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry, 1459 void *context, int idx, int mode, 1460 u64 data) 1461 { 1462 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1463 1464 if (dd->per_sdma && idx < dd->num_sdma) 1465 return dd->per_sdma[idx].progress_int_cnt; 1466 return 0; 1467 } 1468 1469 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context, 1470 int vl, int mode, u64 data) 1471 { 1472 struct hfi1_devdata *dd = context; 1473 1474 u64 val = 0; 1475 u64 csr = entry->csr; 1476 1477 if (entry->flags & CNTR_VL) { 1478 if (vl == CNTR_INVALID_VL) 1479 return 0; 1480 csr += 8 * vl; 1481 } else { 1482 if (vl != CNTR_INVALID_VL) 1483 return 0; 1484 } 1485 1486 val = read_write_csr(dd, csr, mode, data); 1487 return val; 1488 } 1489 1490 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context, 1491 int vl, int mode, u64 data) 1492 { 1493 struct hfi1_devdata *dd = context; 1494 u32 csr = entry->csr; 1495 int ret = 0; 1496 1497 if (vl != CNTR_INVALID_VL) 1498 return 0; 1499 if (mode == CNTR_MODE_R) 1500 ret = read_lcb_csr(dd, csr, &data); 1501 else if (mode == CNTR_MODE_W) 1502 ret = write_lcb_csr(dd, csr, data); 1503 1504 if (ret) { 1505 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr); 1506 return 0; 1507 } 1508 1509 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode); 1510 return data; 1511 } 1512 1513 /* Port Access */ 1514 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context, 1515 int vl, int mode, u64 data) 1516 { 1517 struct hfi1_pportdata *ppd = context; 1518 1519 if (vl != CNTR_INVALID_VL) 1520 return 0; 1521 return read_write_csr(ppd->dd, entry->csr, mode, data); 1522 } 1523 1524 static u64 port_access_u64_csr(const struct cntr_entry *entry, 1525 void *context, int vl, int mode, u64 data) 1526 { 1527 struct hfi1_pportdata *ppd = context; 1528 u64 val; 1529 u64 csr = entry->csr; 1530 1531 if (entry->flags & CNTR_VL) { 1532 if (vl == CNTR_INVALID_VL) 1533 return 0; 1534 csr += 8 * vl; 1535 } else { 1536 if (vl != CNTR_INVALID_VL) 1537 return 0; 1538 } 1539 val = read_write_csr(ppd->dd, csr, mode, data); 1540 return val; 1541 } 1542 1543 /* Software defined */ 1544 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode, 1545 u64 data) 1546 { 1547 u64 ret; 1548 1549 if (mode == CNTR_MODE_R) { 1550 ret = *cntr; 1551 } else if (mode == CNTR_MODE_W) { 1552 *cntr = data; 1553 ret = data; 1554 } else { 1555 dd_dev_err(dd, "Invalid cntr sw access mode"); 1556 return 0; 1557 } 1558 1559 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode); 1560 1561 return ret; 1562 } 1563 1564 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context, 1565 int vl, int mode, u64 data) 1566 { 1567 struct hfi1_pportdata *ppd = context; 1568 1569 if (vl != CNTR_INVALID_VL) 1570 return 0; 1571 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data); 1572 } 1573 1574 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context, 1575 int vl, int mode, u64 data) 1576 { 1577 struct hfi1_pportdata *ppd = context; 1578 1579 if (vl != CNTR_INVALID_VL) 1580 return 0; 1581 return read_write_sw(ppd->dd, &ppd->link_up, mode, data); 1582 } 1583 1584 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry, 1585 void *context, int vl, int mode, 1586 u64 data) 1587 { 1588 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1589 1590 if (vl != CNTR_INVALID_VL) 1591 return 0; 1592 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data); 1593 } 1594 1595 static u64 access_sw_xmit_discards(const struct cntr_entry *entry, 1596 void *context, int vl, int mode, u64 data) 1597 { 1598 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1599 u64 zero = 0; 1600 u64 *counter; 1601 1602 if (vl == CNTR_INVALID_VL) 1603 counter = &ppd->port_xmit_discards; 1604 else if (vl >= 0 && vl < C_VL_COUNT) 1605 counter = &ppd->port_xmit_discards_vl[vl]; 1606 else 1607 counter = &zero; 1608 1609 return read_write_sw(ppd->dd, counter, mode, data); 1610 } 1611 1612 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry, 1613 void *context, int vl, int mode, 1614 u64 data) 1615 { 1616 struct hfi1_pportdata *ppd = context; 1617 1618 if (vl != CNTR_INVALID_VL) 1619 return 0; 1620 1621 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors, 1622 mode, data); 1623 } 1624 1625 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry, 1626 void *context, int vl, int mode, u64 data) 1627 { 1628 struct hfi1_pportdata *ppd = context; 1629 1630 if (vl != CNTR_INVALID_VL) 1631 return 0; 1632 1633 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors, 1634 mode, data); 1635 } 1636 1637 u64 get_all_cpu_total(u64 __percpu *cntr) 1638 { 1639 int cpu; 1640 u64 counter = 0; 1641 1642 for_each_possible_cpu(cpu) 1643 counter += *per_cpu_ptr(cntr, cpu); 1644 return counter; 1645 } 1646 1647 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val, 1648 u64 __percpu *cntr, 1649 int vl, int mode, u64 data) 1650 { 1651 u64 ret = 0; 1652 1653 if (vl != CNTR_INVALID_VL) 1654 return 0; 1655 1656 if (mode == CNTR_MODE_R) { 1657 ret = get_all_cpu_total(cntr) - *z_val; 1658 } else if (mode == CNTR_MODE_W) { 1659 /* A write can only zero the counter */ 1660 if (data == 0) 1661 *z_val = get_all_cpu_total(cntr); 1662 else 1663 dd_dev_err(dd, "Per CPU cntrs can only be zeroed"); 1664 } else { 1665 dd_dev_err(dd, "Invalid cntr sw cpu access mode"); 1666 return 0; 1667 } 1668 1669 return ret; 1670 } 1671 1672 static u64 access_sw_cpu_intr(const struct cntr_entry *entry, 1673 void *context, int vl, int mode, u64 data) 1674 { 1675 struct hfi1_devdata *dd = context; 1676 1677 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl, 1678 mode, data); 1679 } 1680 1681 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry, 1682 void *context, int vl, int mode, u64 data) 1683 { 1684 struct hfi1_devdata *dd = context; 1685 1686 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl, 1687 mode, data); 1688 } 1689 1690 static u64 access_sw_pio_wait(const struct cntr_entry *entry, 1691 void *context, int vl, int mode, u64 data) 1692 { 1693 struct hfi1_devdata *dd = context; 1694 1695 return dd->verbs_dev.n_piowait; 1696 } 1697 1698 static u64 access_sw_pio_drain(const struct cntr_entry *entry, 1699 void *context, int vl, int mode, u64 data) 1700 { 1701 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1702 1703 return dd->verbs_dev.n_piodrain; 1704 } 1705 1706 static u64 access_sw_ctx0_seq_drop(const struct cntr_entry *entry, 1707 void *context, int vl, int mode, u64 data) 1708 { 1709 struct hfi1_devdata *dd = context; 1710 1711 return dd->ctx0_seq_drop; 1712 } 1713 1714 static u64 access_sw_vtx_wait(const struct cntr_entry *entry, 1715 void *context, int vl, int mode, u64 data) 1716 { 1717 struct hfi1_devdata *dd = context; 1718 1719 return dd->verbs_dev.n_txwait; 1720 } 1721 1722 static u64 access_sw_kmem_wait(const struct cntr_entry *entry, 1723 void *context, int vl, int mode, u64 data) 1724 { 1725 struct hfi1_devdata *dd = context; 1726 1727 return dd->verbs_dev.n_kmem_wait; 1728 } 1729 1730 static u64 access_sw_send_schedule(const struct cntr_entry *entry, 1731 void *context, int vl, int mode, u64 data) 1732 { 1733 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1734 1735 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl, 1736 mode, data); 1737 } 1738 1739 /* Software counters for the error status bits within MISC_ERR_STATUS */ 1740 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry, 1741 void *context, int vl, int mode, 1742 u64 data) 1743 { 1744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1745 1746 return dd->misc_err_status_cnt[12]; 1747 } 1748 1749 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry, 1750 void *context, int vl, int mode, 1751 u64 data) 1752 { 1753 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1754 1755 return dd->misc_err_status_cnt[11]; 1756 } 1757 1758 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry, 1759 void *context, int vl, int mode, 1760 u64 data) 1761 { 1762 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1763 1764 return dd->misc_err_status_cnt[10]; 1765 } 1766 1767 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry, 1768 void *context, int vl, 1769 int mode, u64 data) 1770 { 1771 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1772 1773 return dd->misc_err_status_cnt[9]; 1774 } 1775 1776 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry, 1777 void *context, int vl, int mode, 1778 u64 data) 1779 { 1780 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1781 1782 return dd->misc_err_status_cnt[8]; 1783 } 1784 1785 static u64 access_misc_efuse_read_bad_addr_err_cnt( 1786 const struct cntr_entry *entry, 1787 void *context, int vl, int mode, u64 data) 1788 { 1789 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1790 1791 return dd->misc_err_status_cnt[7]; 1792 } 1793 1794 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry, 1795 void *context, int vl, 1796 int mode, u64 data) 1797 { 1798 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1799 1800 return dd->misc_err_status_cnt[6]; 1801 } 1802 1803 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry, 1804 void *context, int vl, int mode, 1805 u64 data) 1806 { 1807 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1808 1809 return dd->misc_err_status_cnt[5]; 1810 } 1811 1812 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry, 1813 void *context, int vl, int mode, 1814 u64 data) 1815 { 1816 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1817 1818 return dd->misc_err_status_cnt[4]; 1819 } 1820 1821 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry, 1822 void *context, int vl, 1823 int mode, u64 data) 1824 { 1825 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1826 1827 return dd->misc_err_status_cnt[3]; 1828 } 1829 1830 static u64 access_misc_csr_write_bad_addr_err_cnt( 1831 const struct cntr_entry *entry, 1832 void *context, int vl, int mode, u64 data) 1833 { 1834 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1835 1836 return dd->misc_err_status_cnt[2]; 1837 } 1838 1839 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1840 void *context, int vl, 1841 int mode, u64 data) 1842 { 1843 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1844 1845 return dd->misc_err_status_cnt[1]; 1846 } 1847 1848 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry, 1849 void *context, int vl, int mode, 1850 u64 data) 1851 { 1852 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1853 1854 return dd->misc_err_status_cnt[0]; 1855 } 1856 1857 /* 1858 * Software counter for the aggregate of 1859 * individual CceErrStatus counters 1860 */ 1861 static u64 access_sw_cce_err_status_aggregated_cnt( 1862 const struct cntr_entry *entry, 1863 void *context, int vl, int mode, u64 data) 1864 { 1865 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1866 1867 return dd->sw_cce_err_status_aggregate; 1868 } 1869 1870 /* 1871 * Software counters corresponding to each of the 1872 * error status bits within CceErrStatus 1873 */ 1874 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry, 1875 void *context, int vl, int mode, 1876 u64 data) 1877 { 1878 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1879 1880 return dd->cce_err_status_cnt[40]; 1881 } 1882 1883 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry, 1884 void *context, int vl, int mode, 1885 u64 data) 1886 { 1887 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1888 1889 return dd->cce_err_status_cnt[39]; 1890 } 1891 1892 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry, 1893 void *context, int vl, int mode, 1894 u64 data) 1895 { 1896 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1897 1898 return dd->cce_err_status_cnt[38]; 1899 } 1900 1901 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry, 1902 void *context, int vl, int mode, 1903 u64 data) 1904 { 1905 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1906 1907 return dd->cce_err_status_cnt[37]; 1908 } 1909 1910 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry, 1911 void *context, int vl, int mode, 1912 u64 data) 1913 { 1914 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1915 1916 return dd->cce_err_status_cnt[36]; 1917 } 1918 1919 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt( 1920 const struct cntr_entry *entry, 1921 void *context, int vl, int mode, u64 data) 1922 { 1923 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1924 1925 return dd->cce_err_status_cnt[35]; 1926 } 1927 1928 static u64 access_cce_rcpl_async_fifo_parity_err_cnt( 1929 const struct cntr_entry *entry, 1930 void *context, int vl, int mode, u64 data) 1931 { 1932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1933 1934 return dd->cce_err_status_cnt[34]; 1935 } 1936 1937 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry, 1938 void *context, int vl, 1939 int mode, u64 data) 1940 { 1941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1942 1943 return dd->cce_err_status_cnt[33]; 1944 } 1945 1946 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1947 void *context, int vl, int mode, 1948 u64 data) 1949 { 1950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1951 1952 return dd->cce_err_status_cnt[32]; 1953 } 1954 1955 static u64 access_la_triggered_cnt(const struct cntr_entry *entry, 1956 void *context, int vl, int mode, u64 data) 1957 { 1958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1959 1960 return dd->cce_err_status_cnt[31]; 1961 } 1962 1963 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry, 1964 void *context, int vl, int mode, 1965 u64 data) 1966 { 1967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1968 1969 return dd->cce_err_status_cnt[30]; 1970 } 1971 1972 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry, 1973 void *context, int vl, int mode, 1974 u64 data) 1975 { 1976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1977 1978 return dd->cce_err_status_cnt[29]; 1979 } 1980 1981 static u64 access_pcic_transmit_back_parity_err_cnt( 1982 const struct cntr_entry *entry, 1983 void *context, int vl, int mode, u64 data) 1984 { 1985 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1986 1987 return dd->cce_err_status_cnt[28]; 1988 } 1989 1990 static u64 access_pcic_transmit_front_parity_err_cnt( 1991 const struct cntr_entry *entry, 1992 void *context, int vl, int mode, u64 data) 1993 { 1994 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1995 1996 return dd->cce_err_status_cnt[27]; 1997 } 1998 1999 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry, 2000 void *context, int vl, int mode, 2001 u64 data) 2002 { 2003 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2004 2005 return dd->cce_err_status_cnt[26]; 2006 } 2007 2008 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2009 void *context, int vl, int mode, 2010 u64 data) 2011 { 2012 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2013 2014 return dd->cce_err_status_cnt[25]; 2015 } 2016 2017 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry, 2018 void *context, int vl, int mode, 2019 u64 data) 2020 { 2021 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2022 2023 return dd->cce_err_status_cnt[24]; 2024 } 2025 2026 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2027 void *context, int vl, int mode, 2028 u64 data) 2029 { 2030 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2031 2032 return dd->cce_err_status_cnt[23]; 2033 } 2034 2035 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry, 2036 void *context, int vl, 2037 int mode, u64 data) 2038 { 2039 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2040 2041 return dd->cce_err_status_cnt[22]; 2042 } 2043 2044 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry, 2045 void *context, int vl, int mode, 2046 u64 data) 2047 { 2048 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2049 2050 return dd->cce_err_status_cnt[21]; 2051 } 2052 2053 static u64 access_pcic_n_post_dat_q_parity_err_cnt( 2054 const struct cntr_entry *entry, 2055 void *context, int vl, int mode, u64 data) 2056 { 2057 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2058 2059 return dd->cce_err_status_cnt[20]; 2060 } 2061 2062 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry, 2063 void *context, int vl, 2064 int mode, u64 data) 2065 { 2066 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2067 2068 return dd->cce_err_status_cnt[19]; 2069 } 2070 2071 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2072 void *context, int vl, int mode, 2073 u64 data) 2074 { 2075 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2076 2077 return dd->cce_err_status_cnt[18]; 2078 } 2079 2080 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2081 void *context, int vl, int mode, 2082 u64 data) 2083 { 2084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2085 2086 return dd->cce_err_status_cnt[17]; 2087 } 2088 2089 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2090 void *context, int vl, int mode, 2091 u64 data) 2092 { 2093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2094 2095 return dd->cce_err_status_cnt[16]; 2096 } 2097 2098 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2099 void *context, int vl, int mode, 2100 u64 data) 2101 { 2102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2103 2104 return dd->cce_err_status_cnt[15]; 2105 } 2106 2107 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry, 2108 void *context, int vl, 2109 int mode, u64 data) 2110 { 2111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2112 2113 return dd->cce_err_status_cnt[14]; 2114 } 2115 2116 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry, 2117 void *context, int vl, int mode, 2118 u64 data) 2119 { 2120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2121 2122 return dd->cce_err_status_cnt[13]; 2123 } 2124 2125 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt( 2126 const struct cntr_entry *entry, 2127 void *context, int vl, int mode, u64 data) 2128 { 2129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2130 2131 return dd->cce_err_status_cnt[12]; 2132 } 2133 2134 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt( 2135 const struct cntr_entry *entry, 2136 void *context, int vl, int mode, u64 data) 2137 { 2138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2139 2140 return dd->cce_err_status_cnt[11]; 2141 } 2142 2143 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt( 2144 const struct cntr_entry *entry, 2145 void *context, int vl, int mode, u64 data) 2146 { 2147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2148 2149 return dd->cce_err_status_cnt[10]; 2150 } 2151 2152 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt( 2153 const struct cntr_entry *entry, 2154 void *context, int vl, int mode, u64 data) 2155 { 2156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2157 2158 return dd->cce_err_status_cnt[9]; 2159 } 2160 2161 static u64 access_cce_cli2_async_fifo_parity_err_cnt( 2162 const struct cntr_entry *entry, 2163 void *context, int vl, int mode, u64 data) 2164 { 2165 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2166 2167 return dd->cce_err_status_cnt[8]; 2168 } 2169 2170 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry, 2171 void *context, int vl, 2172 int mode, u64 data) 2173 { 2174 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2175 2176 return dd->cce_err_status_cnt[7]; 2177 } 2178 2179 static u64 access_cce_cli0_async_fifo_parity_err_cnt( 2180 const struct cntr_entry *entry, 2181 void *context, int vl, int mode, u64 data) 2182 { 2183 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2184 2185 return dd->cce_err_status_cnt[6]; 2186 } 2187 2188 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry, 2189 void *context, int vl, int mode, 2190 u64 data) 2191 { 2192 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2193 2194 return dd->cce_err_status_cnt[5]; 2195 } 2196 2197 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry, 2198 void *context, int vl, int mode, 2199 u64 data) 2200 { 2201 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2202 2203 return dd->cce_err_status_cnt[4]; 2204 } 2205 2206 static u64 access_cce_trgt_async_fifo_parity_err_cnt( 2207 const struct cntr_entry *entry, 2208 void *context, int vl, int mode, u64 data) 2209 { 2210 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2211 2212 return dd->cce_err_status_cnt[3]; 2213 } 2214 2215 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2216 void *context, int vl, 2217 int mode, u64 data) 2218 { 2219 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2220 2221 return dd->cce_err_status_cnt[2]; 2222 } 2223 2224 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2225 void *context, int vl, 2226 int mode, u64 data) 2227 { 2228 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2229 2230 return dd->cce_err_status_cnt[1]; 2231 } 2232 2233 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry, 2234 void *context, int vl, int mode, 2235 u64 data) 2236 { 2237 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2238 2239 return dd->cce_err_status_cnt[0]; 2240 } 2241 2242 /* 2243 * Software counters corresponding to each of the 2244 * error status bits within RcvErrStatus 2245 */ 2246 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry, 2247 void *context, int vl, int mode, 2248 u64 data) 2249 { 2250 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2251 2252 return dd->rcv_err_status_cnt[63]; 2253 } 2254 2255 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2256 void *context, int vl, 2257 int mode, u64 data) 2258 { 2259 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2260 2261 return dd->rcv_err_status_cnt[62]; 2262 } 2263 2264 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2265 void *context, int vl, int mode, 2266 u64 data) 2267 { 2268 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2269 2270 return dd->rcv_err_status_cnt[61]; 2271 } 2272 2273 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry, 2274 void *context, int vl, int mode, 2275 u64 data) 2276 { 2277 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2278 2279 return dd->rcv_err_status_cnt[60]; 2280 } 2281 2282 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2283 void *context, int vl, 2284 int mode, u64 data) 2285 { 2286 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2287 2288 return dd->rcv_err_status_cnt[59]; 2289 } 2290 2291 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2292 void *context, int vl, 2293 int mode, u64 data) 2294 { 2295 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2296 2297 return dd->rcv_err_status_cnt[58]; 2298 } 2299 2300 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry, 2301 void *context, int vl, int mode, 2302 u64 data) 2303 { 2304 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2305 2306 return dd->rcv_err_status_cnt[57]; 2307 } 2308 2309 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry, 2310 void *context, int vl, int mode, 2311 u64 data) 2312 { 2313 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2314 2315 return dd->rcv_err_status_cnt[56]; 2316 } 2317 2318 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry, 2319 void *context, int vl, int mode, 2320 u64 data) 2321 { 2322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2323 2324 return dd->rcv_err_status_cnt[55]; 2325 } 2326 2327 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt( 2328 const struct cntr_entry *entry, 2329 void *context, int vl, int mode, u64 data) 2330 { 2331 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2332 2333 return dd->rcv_err_status_cnt[54]; 2334 } 2335 2336 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt( 2337 const struct cntr_entry *entry, 2338 void *context, int vl, int mode, u64 data) 2339 { 2340 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2341 2342 return dd->rcv_err_status_cnt[53]; 2343 } 2344 2345 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry, 2346 void *context, int vl, 2347 int mode, u64 data) 2348 { 2349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2350 2351 return dd->rcv_err_status_cnt[52]; 2352 } 2353 2354 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry, 2355 void *context, int vl, 2356 int mode, u64 data) 2357 { 2358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2359 2360 return dd->rcv_err_status_cnt[51]; 2361 } 2362 2363 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry, 2364 void *context, int vl, 2365 int mode, u64 data) 2366 { 2367 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2368 2369 return dd->rcv_err_status_cnt[50]; 2370 } 2371 2372 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry, 2373 void *context, int vl, 2374 int mode, u64 data) 2375 { 2376 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2377 2378 return dd->rcv_err_status_cnt[49]; 2379 } 2380 2381 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry, 2382 void *context, int vl, 2383 int mode, u64 data) 2384 { 2385 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2386 2387 return dd->rcv_err_status_cnt[48]; 2388 } 2389 2390 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry, 2391 void *context, int vl, 2392 int mode, u64 data) 2393 { 2394 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2395 2396 return dd->rcv_err_status_cnt[47]; 2397 } 2398 2399 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry, 2400 void *context, int vl, int mode, 2401 u64 data) 2402 { 2403 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2404 2405 return dd->rcv_err_status_cnt[46]; 2406 } 2407 2408 static u64 access_rx_hq_intr_csr_parity_err_cnt( 2409 const struct cntr_entry *entry, 2410 void *context, int vl, int mode, u64 data) 2411 { 2412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2413 2414 return dd->rcv_err_status_cnt[45]; 2415 } 2416 2417 static u64 access_rx_lookup_csr_parity_err_cnt( 2418 const struct cntr_entry *entry, 2419 void *context, int vl, int mode, u64 data) 2420 { 2421 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2422 2423 return dd->rcv_err_status_cnt[44]; 2424 } 2425 2426 static u64 access_rx_lookup_rcv_array_cor_err_cnt( 2427 const struct cntr_entry *entry, 2428 void *context, int vl, int mode, u64 data) 2429 { 2430 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2431 2432 return dd->rcv_err_status_cnt[43]; 2433 } 2434 2435 static u64 access_rx_lookup_rcv_array_unc_err_cnt( 2436 const struct cntr_entry *entry, 2437 void *context, int vl, int mode, u64 data) 2438 { 2439 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2440 2441 return dd->rcv_err_status_cnt[42]; 2442 } 2443 2444 static u64 access_rx_lookup_des_part2_parity_err_cnt( 2445 const struct cntr_entry *entry, 2446 void *context, int vl, int mode, u64 data) 2447 { 2448 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2449 2450 return dd->rcv_err_status_cnt[41]; 2451 } 2452 2453 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt( 2454 const struct cntr_entry *entry, 2455 void *context, int vl, int mode, u64 data) 2456 { 2457 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2458 2459 return dd->rcv_err_status_cnt[40]; 2460 } 2461 2462 static u64 access_rx_lookup_des_part1_unc_err_cnt( 2463 const struct cntr_entry *entry, 2464 void *context, int vl, int mode, u64 data) 2465 { 2466 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2467 2468 return dd->rcv_err_status_cnt[39]; 2469 } 2470 2471 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt( 2472 const struct cntr_entry *entry, 2473 void *context, int vl, int mode, u64 data) 2474 { 2475 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2476 2477 return dd->rcv_err_status_cnt[38]; 2478 } 2479 2480 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt( 2481 const struct cntr_entry *entry, 2482 void *context, int vl, int mode, u64 data) 2483 { 2484 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2485 2486 return dd->rcv_err_status_cnt[37]; 2487 } 2488 2489 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt( 2490 const struct cntr_entry *entry, 2491 void *context, int vl, int mode, u64 data) 2492 { 2493 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2494 2495 return dd->rcv_err_status_cnt[36]; 2496 } 2497 2498 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt( 2499 const struct cntr_entry *entry, 2500 void *context, int vl, int mode, u64 data) 2501 { 2502 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2503 2504 return dd->rcv_err_status_cnt[35]; 2505 } 2506 2507 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt( 2508 const struct cntr_entry *entry, 2509 void *context, int vl, int mode, u64 data) 2510 { 2511 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2512 2513 return dd->rcv_err_status_cnt[34]; 2514 } 2515 2516 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt( 2517 const struct cntr_entry *entry, 2518 void *context, int vl, int mode, u64 data) 2519 { 2520 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2521 2522 return dd->rcv_err_status_cnt[33]; 2523 } 2524 2525 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry, 2526 void *context, int vl, int mode, 2527 u64 data) 2528 { 2529 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2530 2531 return dd->rcv_err_status_cnt[32]; 2532 } 2533 2534 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry, 2535 void *context, int vl, int mode, 2536 u64 data) 2537 { 2538 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2539 2540 return dd->rcv_err_status_cnt[31]; 2541 } 2542 2543 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry, 2544 void *context, int vl, int mode, 2545 u64 data) 2546 { 2547 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2548 2549 return dd->rcv_err_status_cnt[30]; 2550 } 2551 2552 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry, 2553 void *context, int vl, int mode, 2554 u64 data) 2555 { 2556 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2557 2558 return dd->rcv_err_status_cnt[29]; 2559 } 2560 2561 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry, 2562 void *context, int vl, 2563 int mode, u64 data) 2564 { 2565 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2566 2567 return dd->rcv_err_status_cnt[28]; 2568 } 2569 2570 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt( 2571 const struct cntr_entry *entry, 2572 void *context, int vl, int mode, u64 data) 2573 { 2574 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2575 2576 return dd->rcv_err_status_cnt[27]; 2577 } 2578 2579 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt( 2580 const struct cntr_entry *entry, 2581 void *context, int vl, int mode, u64 data) 2582 { 2583 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2584 2585 return dd->rcv_err_status_cnt[26]; 2586 } 2587 2588 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt( 2589 const struct cntr_entry *entry, 2590 void *context, int vl, int mode, u64 data) 2591 { 2592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2593 2594 return dd->rcv_err_status_cnt[25]; 2595 } 2596 2597 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt( 2598 const struct cntr_entry *entry, 2599 void *context, int vl, int mode, u64 data) 2600 { 2601 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2602 2603 return dd->rcv_err_status_cnt[24]; 2604 } 2605 2606 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt( 2607 const struct cntr_entry *entry, 2608 void *context, int vl, int mode, u64 data) 2609 { 2610 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2611 2612 return dd->rcv_err_status_cnt[23]; 2613 } 2614 2615 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt( 2616 const struct cntr_entry *entry, 2617 void *context, int vl, int mode, u64 data) 2618 { 2619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2620 2621 return dd->rcv_err_status_cnt[22]; 2622 } 2623 2624 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt( 2625 const struct cntr_entry *entry, 2626 void *context, int vl, int mode, u64 data) 2627 { 2628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2629 2630 return dd->rcv_err_status_cnt[21]; 2631 } 2632 2633 static u64 access_rx_rbuf_block_list_read_cor_err_cnt( 2634 const struct cntr_entry *entry, 2635 void *context, int vl, int mode, u64 data) 2636 { 2637 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2638 2639 return dd->rcv_err_status_cnt[20]; 2640 } 2641 2642 static u64 access_rx_rbuf_block_list_read_unc_err_cnt( 2643 const struct cntr_entry *entry, 2644 void *context, int vl, int mode, u64 data) 2645 { 2646 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2647 2648 return dd->rcv_err_status_cnt[19]; 2649 } 2650 2651 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry, 2652 void *context, int vl, 2653 int mode, u64 data) 2654 { 2655 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2656 2657 return dd->rcv_err_status_cnt[18]; 2658 } 2659 2660 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry, 2661 void *context, int vl, 2662 int mode, u64 data) 2663 { 2664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2665 2666 return dd->rcv_err_status_cnt[17]; 2667 } 2668 2669 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt( 2670 const struct cntr_entry *entry, 2671 void *context, int vl, int mode, u64 data) 2672 { 2673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2674 2675 return dd->rcv_err_status_cnt[16]; 2676 } 2677 2678 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt( 2679 const struct cntr_entry *entry, 2680 void *context, int vl, int mode, u64 data) 2681 { 2682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2683 2684 return dd->rcv_err_status_cnt[15]; 2685 } 2686 2687 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry, 2688 void *context, int vl, 2689 int mode, u64 data) 2690 { 2691 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2692 2693 return dd->rcv_err_status_cnt[14]; 2694 } 2695 2696 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry, 2697 void *context, int vl, 2698 int mode, u64 data) 2699 { 2700 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2701 2702 return dd->rcv_err_status_cnt[13]; 2703 } 2704 2705 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2706 void *context, int vl, int mode, 2707 u64 data) 2708 { 2709 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2710 2711 return dd->rcv_err_status_cnt[12]; 2712 } 2713 2714 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry, 2715 void *context, int vl, int mode, 2716 u64 data) 2717 { 2718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2719 2720 return dd->rcv_err_status_cnt[11]; 2721 } 2722 2723 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry, 2724 void *context, int vl, int mode, 2725 u64 data) 2726 { 2727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2728 2729 return dd->rcv_err_status_cnt[10]; 2730 } 2731 2732 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry, 2733 void *context, int vl, int mode, 2734 u64 data) 2735 { 2736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2737 2738 return dd->rcv_err_status_cnt[9]; 2739 } 2740 2741 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry, 2742 void *context, int vl, int mode, 2743 u64 data) 2744 { 2745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2746 2747 return dd->rcv_err_status_cnt[8]; 2748 } 2749 2750 static u64 access_rx_rcv_qp_map_table_cor_err_cnt( 2751 const struct cntr_entry *entry, 2752 void *context, int vl, int mode, u64 data) 2753 { 2754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2755 2756 return dd->rcv_err_status_cnt[7]; 2757 } 2758 2759 static u64 access_rx_rcv_qp_map_table_unc_err_cnt( 2760 const struct cntr_entry *entry, 2761 void *context, int vl, int mode, u64 data) 2762 { 2763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2764 2765 return dd->rcv_err_status_cnt[6]; 2766 } 2767 2768 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry, 2769 void *context, int vl, int mode, 2770 u64 data) 2771 { 2772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2773 2774 return dd->rcv_err_status_cnt[5]; 2775 } 2776 2777 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry, 2778 void *context, int vl, int mode, 2779 u64 data) 2780 { 2781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2782 2783 return dd->rcv_err_status_cnt[4]; 2784 } 2785 2786 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry, 2787 void *context, int vl, int mode, 2788 u64 data) 2789 { 2790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2791 2792 return dd->rcv_err_status_cnt[3]; 2793 } 2794 2795 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry, 2796 void *context, int vl, int mode, 2797 u64 data) 2798 { 2799 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2800 2801 return dd->rcv_err_status_cnt[2]; 2802 } 2803 2804 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry, 2805 void *context, int vl, int mode, 2806 u64 data) 2807 { 2808 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2809 2810 return dd->rcv_err_status_cnt[1]; 2811 } 2812 2813 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry, 2814 void *context, int vl, int mode, 2815 u64 data) 2816 { 2817 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2818 2819 return dd->rcv_err_status_cnt[0]; 2820 } 2821 2822 /* 2823 * Software counters corresponding to each of the 2824 * error status bits within SendPioErrStatus 2825 */ 2826 static u64 access_pio_pec_sop_head_parity_err_cnt( 2827 const struct cntr_entry *entry, 2828 void *context, int vl, int mode, u64 data) 2829 { 2830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2831 2832 return dd->send_pio_err_status_cnt[35]; 2833 } 2834 2835 static u64 access_pio_pcc_sop_head_parity_err_cnt( 2836 const struct cntr_entry *entry, 2837 void *context, int vl, int mode, u64 data) 2838 { 2839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2840 2841 return dd->send_pio_err_status_cnt[34]; 2842 } 2843 2844 static u64 access_pio_last_returned_cnt_parity_err_cnt( 2845 const struct cntr_entry *entry, 2846 void *context, int vl, int mode, u64 data) 2847 { 2848 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2849 2850 return dd->send_pio_err_status_cnt[33]; 2851 } 2852 2853 static u64 access_pio_current_free_cnt_parity_err_cnt( 2854 const struct cntr_entry *entry, 2855 void *context, int vl, int mode, u64 data) 2856 { 2857 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2858 2859 return dd->send_pio_err_status_cnt[32]; 2860 } 2861 2862 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry, 2863 void *context, int vl, int mode, 2864 u64 data) 2865 { 2866 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2867 2868 return dd->send_pio_err_status_cnt[31]; 2869 } 2870 2871 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry, 2872 void *context, int vl, int mode, 2873 u64 data) 2874 { 2875 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2876 2877 return dd->send_pio_err_status_cnt[30]; 2878 } 2879 2880 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry, 2881 void *context, int vl, int mode, 2882 u64 data) 2883 { 2884 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2885 2886 return dd->send_pio_err_status_cnt[29]; 2887 } 2888 2889 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt( 2890 const struct cntr_entry *entry, 2891 void *context, int vl, int mode, u64 data) 2892 { 2893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2894 2895 return dd->send_pio_err_status_cnt[28]; 2896 } 2897 2898 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry, 2899 void *context, int vl, int mode, 2900 u64 data) 2901 { 2902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2903 2904 return dd->send_pio_err_status_cnt[27]; 2905 } 2906 2907 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry, 2908 void *context, int vl, int mode, 2909 u64 data) 2910 { 2911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2912 2913 return dd->send_pio_err_status_cnt[26]; 2914 } 2915 2916 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry, 2917 void *context, int vl, 2918 int mode, u64 data) 2919 { 2920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2921 2922 return dd->send_pio_err_status_cnt[25]; 2923 } 2924 2925 static u64 access_pio_block_qw_count_parity_err_cnt( 2926 const struct cntr_entry *entry, 2927 void *context, int vl, int mode, u64 data) 2928 { 2929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2930 2931 return dd->send_pio_err_status_cnt[24]; 2932 } 2933 2934 static u64 access_pio_write_qw_valid_parity_err_cnt( 2935 const struct cntr_entry *entry, 2936 void *context, int vl, int mode, u64 data) 2937 { 2938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2939 2940 return dd->send_pio_err_status_cnt[23]; 2941 } 2942 2943 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry, 2944 void *context, int vl, int mode, 2945 u64 data) 2946 { 2947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2948 2949 return dd->send_pio_err_status_cnt[22]; 2950 } 2951 2952 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry, 2953 void *context, int vl, 2954 int mode, u64 data) 2955 { 2956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2957 2958 return dd->send_pio_err_status_cnt[21]; 2959 } 2960 2961 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry, 2962 void *context, int vl, 2963 int mode, u64 data) 2964 { 2965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2966 2967 return dd->send_pio_err_status_cnt[20]; 2968 } 2969 2970 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry, 2971 void *context, int vl, 2972 int mode, u64 data) 2973 { 2974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2975 2976 return dd->send_pio_err_status_cnt[19]; 2977 } 2978 2979 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt( 2980 const struct cntr_entry *entry, 2981 void *context, int vl, int mode, u64 data) 2982 { 2983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2984 2985 return dd->send_pio_err_status_cnt[18]; 2986 } 2987 2988 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry, 2989 void *context, int vl, int mode, 2990 u64 data) 2991 { 2992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2993 2994 return dd->send_pio_err_status_cnt[17]; 2995 } 2996 2997 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry, 2998 void *context, int vl, int mode, 2999 u64 data) 3000 { 3001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3002 3003 return dd->send_pio_err_status_cnt[16]; 3004 } 3005 3006 static u64 access_pio_credit_ret_fifo_parity_err_cnt( 3007 const struct cntr_entry *entry, 3008 void *context, int vl, int mode, u64 data) 3009 { 3010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3011 3012 return dd->send_pio_err_status_cnt[15]; 3013 } 3014 3015 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt( 3016 const struct cntr_entry *entry, 3017 void *context, int vl, int mode, u64 data) 3018 { 3019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3020 3021 return dd->send_pio_err_status_cnt[14]; 3022 } 3023 3024 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt( 3025 const struct cntr_entry *entry, 3026 void *context, int vl, int mode, u64 data) 3027 { 3028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3029 3030 return dd->send_pio_err_status_cnt[13]; 3031 } 3032 3033 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt( 3034 const struct cntr_entry *entry, 3035 void *context, int vl, int mode, u64 data) 3036 { 3037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3038 3039 return dd->send_pio_err_status_cnt[12]; 3040 } 3041 3042 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt( 3043 const struct cntr_entry *entry, 3044 void *context, int vl, int mode, u64 data) 3045 { 3046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3047 3048 return dd->send_pio_err_status_cnt[11]; 3049 } 3050 3051 static u64 access_pio_sm_pkt_reset_parity_err_cnt( 3052 const struct cntr_entry *entry, 3053 void *context, int vl, int mode, u64 data) 3054 { 3055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3056 3057 return dd->send_pio_err_status_cnt[10]; 3058 } 3059 3060 static u64 access_pio_pkt_evict_fifo_parity_err_cnt( 3061 const struct cntr_entry *entry, 3062 void *context, int vl, int mode, u64 data) 3063 { 3064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3065 3066 return dd->send_pio_err_status_cnt[9]; 3067 } 3068 3069 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt( 3070 const struct cntr_entry *entry, 3071 void *context, int vl, int mode, u64 data) 3072 { 3073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3074 3075 return dd->send_pio_err_status_cnt[8]; 3076 } 3077 3078 static u64 access_pio_sbrdctl_crrel_parity_err_cnt( 3079 const struct cntr_entry *entry, 3080 void *context, int vl, int mode, u64 data) 3081 { 3082 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3083 3084 return dd->send_pio_err_status_cnt[7]; 3085 } 3086 3087 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry, 3088 void *context, int vl, int mode, 3089 u64 data) 3090 { 3091 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3092 3093 return dd->send_pio_err_status_cnt[6]; 3094 } 3095 3096 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry, 3097 void *context, int vl, int mode, 3098 u64 data) 3099 { 3100 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3101 3102 return dd->send_pio_err_status_cnt[5]; 3103 } 3104 3105 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry, 3106 void *context, int vl, int mode, 3107 u64 data) 3108 { 3109 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3110 3111 return dd->send_pio_err_status_cnt[4]; 3112 } 3113 3114 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry, 3115 void *context, int vl, int mode, 3116 u64 data) 3117 { 3118 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3119 3120 return dd->send_pio_err_status_cnt[3]; 3121 } 3122 3123 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry, 3124 void *context, int vl, int mode, 3125 u64 data) 3126 { 3127 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3128 3129 return dd->send_pio_err_status_cnt[2]; 3130 } 3131 3132 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry, 3133 void *context, int vl, 3134 int mode, u64 data) 3135 { 3136 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3137 3138 return dd->send_pio_err_status_cnt[1]; 3139 } 3140 3141 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry, 3142 void *context, int vl, int mode, 3143 u64 data) 3144 { 3145 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3146 3147 return dd->send_pio_err_status_cnt[0]; 3148 } 3149 3150 /* 3151 * Software counters corresponding to each of the 3152 * error status bits within SendDmaErrStatus 3153 */ 3154 static u64 access_sdma_pcie_req_tracking_cor_err_cnt( 3155 const struct cntr_entry *entry, 3156 void *context, int vl, int mode, u64 data) 3157 { 3158 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3159 3160 return dd->send_dma_err_status_cnt[3]; 3161 } 3162 3163 static u64 access_sdma_pcie_req_tracking_unc_err_cnt( 3164 const struct cntr_entry *entry, 3165 void *context, int vl, int mode, u64 data) 3166 { 3167 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3168 3169 return dd->send_dma_err_status_cnt[2]; 3170 } 3171 3172 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry, 3173 void *context, int vl, int mode, 3174 u64 data) 3175 { 3176 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3177 3178 return dd->send_dma_err_status_cnt[1]; 3179 } 3180 3181 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry, 3182 void *context, int vl, int mode, 3183 u64 data) 3184 { 3185 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3186 3187 return dd->send_dma_err_status_cnt[0]; 3188 } 3189 3190 /* 3191 * Software counters corresponding to each of the 3192 * error status bits within SendEgressErrStatus 3193 */ 3194 static u64 access_tx_read_pio_memory_csr_unc_err_cnt( 3195 const struct cntr_entry *entry, 3196 void *context, int vl, int mode, u64 data) 3197 { 3198 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3199 3200 return dd->send_egress_err_status_cnt[63]; 3201 } 3202 3203 static u64 access_tx_read_sdma_memory_csr_err_cnt( 3204 const struct cntr_entry *entry, 3205 void *context, int vl, int mode, u64 data) 3206 { 3207 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3208 3209 return dd->send_egress_err_status_cnt[62]; 3210 } 3211 3212 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry, 3213 void *context, int vl, int mode, 3214 u64 data) 3215 { 3216 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3217 3218 return dd->send_egress_err_status_cnt[61]; 3219 } 3220 3221 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry, 3222 void *context, int vl, 3223 int mode, u64 data) 3224 { 3225 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3226 3227 return dd->send_egress_err_status_cnt[60]; 3228 } 3229 3230 static u64 access_tx_read_sdma_memory_cor_err_cnt( 3231 const struct cntr_entry *entry, 3232 void *context, int vl, int mode, u64 data) 3233 { 3234 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3235 3236 return dd->send_egress_err_status_cnt[59]; 3237 } 3238 3239 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry, 3240 void *context, int vl, int mode, 3241 u64 data) 3242 { 3243 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3244 3245 return dd->send_egress_err_status_cnt[58]; 3246 } 3247 3248 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry, 3249 void *context, int vl, int mode, 3250 u64 data) 3251 { 3252 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3253 3254 return dd->send_egress_err_status_cnt[57]; 3255 } 3256 3257 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry, 3258 void *context, int vl, int mode, 3259 u64 data) 3260 { 3261 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3262 3263 return dd->send_egress_err_status_cnt[56]; 3264 } 3265 3266 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry, 3267 void *context, int vl, int mode, 3268 u64 data) 3269 { 3270 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3271 3272 return dd->send_egress_err_status_cnt[55]; 3273 } 3274 3275 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry, 3276 void *context, int vl, int mode, 3277 u64 data) 3278 { 3279 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3280 3281 return dd->send_egress_err_status_cnt[54]; 3282 } 3283 3284 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry, 3285 void *context, int vl, int mode, 3286 u64 data) 3287 { 3288 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3289 3290 return dd->send_egress_err_status_cnt[53]; 3291 } 3292 3293 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry, 3294 void *context, int vl, int mode, 3295 u64 data) 3296 { 3297 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3298 3299 return dd->send_egress_err_status_cnt[52]; 3300 } 3301 3302 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry, 3303 void *context, int vl, int mode, 3304 u64 data) 3305 { 3306 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3307 3308 return dd->send_egress_err_status_cnt[51]; 3309 } 3310 3311 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry, 3312 void *context, int vl, int mode, 3313 u64 data) 3314 { 3315 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3316 3317 return dd->send_egress_err_status_cnt[50]; 3318 } 3319 3320 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry, 3321 void *context, int vl, int mode, 3322 u64 data) 3323 { 3324 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3325 3326 return dd->send_egress_err_status_cnt[49]; 3327 } 3328 3329 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry, 3330 void *context, int vl, int mode, 3331 u64 data) 3332 { 3333 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3334 3335 return dd->send_egress_err_status_cnt[48]; 3336 } 3337 3338 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry, 3339 void *context, int vl, int mode, 3340 u64 data) 3341 { 3342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3343 3344 return dd->send_egress_err_status_cnt[47]; 3345 } 3346 3347 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry, 3348 void *context, int vl, int mode, 3349 u64 data) 3350 { 3351 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3352 3353 return dd->send_egress_err_status_cnt[46]; 3354 } 3355 3356 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry, 3357 void *context, int vl, int mode, 3358 u64 data) 3359 { 3360 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3361 3362 return dd->send_egress_err_status_cnt[45]; 3363 } 3364 3365 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry, 3366 void *context, int vl, 3367 int mode, u64 data) 3368 { 3369 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3370 3371 return dd->send_egress_err_status_cnt[44]; 3372 } 3373 3374 static u64 access_tx_read_sdma_memory_unc_err_cnt( 3375 const struct cntr_entry *entry, 3376 void *context, int vl, int mode, u64 data) 3377 { 3378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3379 3380 return dd->send_egress_err_status_cnt[43]; 3381 } 3382 3383 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry, 3384 void *context, int vl, int mode, 3385 u64 data) 3386 { 3387 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3388 3389 return dd->send_egress_err_status_cnt[42]; 3390 } 3391 3392 static u64 access_tx_credit_return_partiy_err_cnt( 3393 const struct cntr_entry *entry, 3394 void *context, int vl, int mode, u64 data) 3395 { 3396 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3397 3398 return dd->send_egress_err_status_cnt[41]; 3399 } 3400 3401 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt( 3402 const struct cntr_entry *entry, 3403 void *context, int vl, int mode, u64 data) 3404 { 3405 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3406 3407 return dd->send_egress_err_status_cnt[40]; 3408 } 3409 3410 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt( 3411 const struct cntr_entry *entry, 3412 void *context, int vl, int mode, u64 data) 3413 { 3414 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3415 3416 return dd->send_egress_err_status_cnt[39]; 3417 } 3418 3419 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt( 3420 const struct cntr_entry *entry, 3421 void *context, int vl, int mode, u64 data) 3422 { 3423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3424 3425 return dd->send_egress_err_status_cnt[38]; 3426 } 3427 3428 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt( 3429 const struct cntr_entry *entry, 3430 void *context, int vl, int mode, u64 data) 3431 { 3432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3433 3434 return dd->send_egress_err_status_cnt[37]; 3435 } 3436 3437 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt( 3438 const struct cntr_entry *entry, 3439 void *context, int vl, int mode, u64 data) 3440 { 3441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3442 3443 return dd->send_egress_err_status_cnt[36]; 3444 } 3445 3446 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt( 3447 const struct cntr_entry *entry, 3448 void *context, int vl, int mode, u64 data) 3449 { 3450 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3451 3452 return dd->send_egress_err_status_cnt[35]; 3453 } 3454 3455 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt( 3456 const struct cntr_entry *entry, 3457 void *context, int vl, int mode, u64 data) 3458 { 3459 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3460 3461 return dd->send_egress_err_status_cnt[34]; 3462 } 3463 3464 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt( 3465 const struct cntr_entry *entry, 3466 void *context, int vl, int mode, u64 data) 3467 { 3468 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3469 3470 return dd->send_egress_err_status_cnt[33]; 3471 } 3472 3473 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt( 3474 const struct cntr_entry *entry, 3475 void *context, int vl, int mode, u64 data) 3476 { 3477 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3478 3479 return dd->send_egress_err_status_cnt[32]; 3480 } 3481 3482 static u64 access_tx_sdma15_disallowed_packet_err_cnt( 3483 const struct cntr_entry *entry, 3484 void *context, int vl, int mode, u64 data) 3485 { 3486 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3487 3488 return dd->send_egress_err_status_cnt[31]; 3489 } 3490 3491 static u64 access_tx_sdma14_disallowed_packet_err_cnt( 3492 const struct cntr_entry *entry, 3493 void *context, int vl, int mode, u64 data) 3494 { 3495 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3496 3497 return dd->send_egress_err_status_cnt[30]; 3498 } 3499 3500 static u64 access_tx_sdma13_disallowed_packet_err_cnt( 3501 const struct cntr_entry *entry, 3502 void *context, int vl, int mode, u64 data) 3503 { 3504 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3505 3506 return dd->send_egress_err_status_cnt[29]; 3507 } 3508 3509 static u64 access_tx_sdma12_disallowed_packet_err_cnt( 3510 const struct cntr_entry *entry, 3511 void *context, int vl, int mode, u64 data) 3512 { 3513 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3514 3515 return dd->send_egress_err_status_cnt[28]; 3516 } 3517 3518 static u64 access_tx_sdma11_disallowed_packet_err_cnt( 3519 const struct cntr_entry *entry, 3520 void *context, int vl, int mode, u64 data) 3521 { 3522 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3523 3524 return dd->send_egress_err_status_cnt[27]; 3525 } 3526 3527 static u64 access_tx_sdma10_disallowed_packet_err_cnt( 3528 const struct cntr_entry *entry, 3529 void *context, int vl, int mode, u64 data) 3530 { 3531 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3532 3533 return dd->send_egress_err_status_cnt[26]; 3534 } 3535 3536 static u64 access_tx_sdma9_disallowed_packet_err_cnt( 3537 const struct cntr_entry *entry, 3538 void *context, int vl, int mode, u64 data) 3539 { 3540 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3541 3542 return dd->send_egress_err_status_cnt[25]; 3543 } 3544 3545 static u64 access_tx_sdma8_disallowed_packet_err_cnt( 3546 const struct cntr_entry *entry, 3547 void *context, int vl, int mode, u64 data) 3548 { 3549 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3550 3551 return dd->send_egress_err_status_cnt[24]; 3552 } 3553 3554 static u64 access_tx_sdma7_disallowed_packet_err_cnt( 3555 const struct cntr_entry *entry, 3556 void *context, int vl, int mode, u64 data) 3557 { 3558 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3559 3560 return dd->send_egress_err_status_cnt[23]; 3561 } 3562 3563 static u64 access_tx_sdma6_disallowed_packet_err_cnt( 3564 const struct cntr_entry *entry, 3565 void *context, int vl, int mode, u64 data) 3566 { 3567 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3568 3569 return dd->send_egress_err_status_cnt[22]; 3570 } 3571 3572 static u64 access_tx_sdma5_disallowed_packet_err_cnt( 3573 const struct cntr_entry *entry, 3574 void *context, int vl, int mode, u64 data) 3575 { 3576 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3577 3578 return dd->send_egress_err_status_cnt[21]; 3579 } 3580 3581 static u64 access_tx_sdma4_disallowed_packet_err_cnt( 3582 const struct cntr_entry *entry, 3583 void *context, int vl, int mode, u64 data) 3584 { 3585 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3586 3587 return dd->send_egress_err_status_cnt[20]; 3588 } 3589 3590 static u64 access_tx_sdma3_disallowed_packet_err_cnt( 3591 const struct cntr_entry *entry, 3592 void *context, int vl, int mode, u64 data) 3593 { 3594 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3595 3596 return dd->send_egress_err_status_cnt[19]; 3597 } 3598 3599 static u64 access_tx_sdma2_disallowed_packet_err_cnt( 3600 const struct cntr_entry *entry, 3601 void *context, int vl, int mode, u64 data) 3602 { 3603 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3604 3605 return dd->send_egress_err_status_cnt[18]; 3606 } 3607 3608 static u64 access_tx_sdma1_disallowed_packet_err_cnt( 3609 const struct cntr_entry *entry, 3610 void *context, int vl, int mode, u64 data) 3611 { 3612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3613 3614 return dd->send_egress_err_status_cnt[17]; 3615 } 3616 3617 static u64 access_tx_sdma0_disallowed_packet_err_cnt( 3618 const struct cntr_entry *entry, 3619 void *context, int vl, int mode, u64 data) 3620 { 3621 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3622 3623 return dd->send_egress_err_status_cnt[16]; 3624 } 3625 3626 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry, 3627 void *context, int vl, int mode, 3628 u64 data) 3629 { 3630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3631 3632 return dd->send_egress_err_status_cnt[15]; 3633 } 3634 3635 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry, 3636 void *context, int vl, 3637 int mode, u64 data) 3638 { 3639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3640 3641 return dd->send_egress_err_status_cnt[14]; 3642 } 3643 3644 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry, 3645 void *context, int vl, int mode, 3646 u64 data) 3647 { 3648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3649 3650 return dd->send_egress_err_status_cnt[13]; 3651 } 3652 3653 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry, 3654 void *context, int vl, int mode, 3655 u64 data) 3656 { 3657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3658 3659 return dd->send_egress_err_status_cnt[12]; 3660 } 3661 3662 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt( 3663 const struct cntr_entry *entry, 3664 void *context, int vl, int mode, u64 data) 3665 { 3666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3667 3668 return dd->send_egress_err_status_cnt[11]; 3669 } 3670 3671 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry, 3672 void *context, int vl, int mode, 3673 u64 data) 3674 { 3675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3676 3677 return dd->send_egress_err_status_cnt[10]; 3678 } 3679 3680 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry, 3681 void *context, int vl, int mode, 3682 u64 data) 3683 { 3684 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3685 3686 return dd->send_egress_err_status_cnt[9]; 3687 } 3688 3689 static u64 access_tx_sdma_launch_intf_parity_err_cnt( 3690 const struct cntr_entry *entry, 3691 void *context, int vl, int mode, u64 data) 3692 { 3693 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3694 3695 return dd->send_egress_err_status_cnt[8]; 3696 } 3697 3698 static u64 access_tx_pio_launch_intf_parity_err_cnt( 3699 const struct cntr_entry *entry, 3700 void *context, int vl, int mode, u64 data) 3701 { 3702 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3703 3704 return dd->send_egress_err_status_cnt[7]; 3705 } 3706 3707 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry, 3708 void *context, int vl, int mode, 3709 u64 data) 3710 { 3711 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3712 3713 return dd->send_egress_err_status_cnt[6]; 3714 } 3715 3716 static u64 access_tx_incorrect_link_state_err_cnt( 3717 const struct cntr_entry *entry, 3718 void *context, int vl, int mode, u64 data) 3719 { 3720 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3721 3722 return dd->send_egress_err_status_cnt[5]; 3723 } 3724 3725 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry, 3726 void *context, int vl, int mode, 3727 u64 data) 3728 { 3729 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3730 3731 return dd->send_egress_err_status_cnt[4]; 3732 } 3733 3734 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt( 3735 const struct cntr_entry *entry, 3736 void *context, int vl, int mode, u64 data) 3737 { 3738 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3739 3740 return dd->send_egress_err_status_cnt[3]; 3741 } 3742 3743 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry, 3744 void *context, int vl, int mode, 3745 u64 data) 3746 { 3747 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3748 3749 return dd->send_egress_err_status_cnt[2]; 3750 } 3751 3752 static u64 access_tx_pkt_integrity_mem_unc_err_cnt( 3753 const struct cntr_entry *entry, 3754 void *context, int vl, int mode, u64 data) 3755 { 3756 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3757 3758 return dd->send_egress_err_status_cnt[1]; 3759 } 3760 3761 static u64 access_tx_pkt_integrity_mem_cor_err_cnt( 3762 const struct cntr_entry *entry, 3763 void *context, int vl, int mode, u64 data) 3764 { 3765 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3766 3767 return dd->send_egress_err_status_cnt[0]; 3768 } 3769 3770 /* 3771 * Software counters corresponding to each of the 3772 * error status bits within SendErrStatus 3773 */ 3774 static u64 access_send_csr_write_bad_addr_err_cnt( 3775 const struct cntr_entry *entry, 3776 void *context, int vl, int mode, u64 data) 3777 { 3778 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3779 3780 return dd->send_err_status_cnt[2]; 3781 } 3782 3783 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 3784 void *context, int vl, 3785 int mode, u64 data) 3786 { 3787 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3788 3789 return dd->send_err_status_cnt[1]; 3790 } 3791 3792 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry, 3793 void *context, int vl, int mode, 3794 u64 data) 3795 { 3796 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3797 3798 return dd->send_err_status_cnt[0]; 3799 } 3800 3801 /* 3802 * Software counters corresponding to each of the 3803 * error status bits within SendCtxtErrStatus 3804 */ 3805 static u64 access_pio_write_out_of_bounds_err_cnt( 3806 const struct cntr_entry *entry, 3807 void *context, int vl, int mode, u64 data) 3808 { 3809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3810 3811 return dd->sw_ctxt_err_status_cnt[4]; 3812 } 3813 3814 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry, 3815 void *context, int vl, int mode, 3816 u64 data) 3817 { 3818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3819 3820 return dd->sw_ctxt_err_status_cnt[3]; 3821 } 3822 3823 static u64 access_pio_write_crosses_boundary_err_cnt( 3824 const struct cntr_entry *entry, 3825 void *context, int vl, int mode, u64 data) 3826 { 3827 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3828 3829 return dd->sw_ctxt_err_status_cnt[2]; 3830 } 3831 3832 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry, 3833 void *context, int vl, 3834 int mode, u64 data) 3835 { 3836 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3837 3838 return dd->sw_ctxt_err_status_cnt[1]; 3839 } 3840 3841 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry, 3842 void *context, int vl, int mode, 3843 u64 data) 3844 { 3845 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3846 3847 return dd->sw_ctxt_err_status_cnt[0]; 3848 } 3849 3850 /* 3851 * Software counters corresponding to each of the 3852 * error status bits within SendDmaEngErrStatus 3853 */ 3854 static u64 access_sdma_header_request_fifo_cor_err_cnt( 3855 const struct cntr_entry *entry, 3856 void *context, int vl, int mode, u64 data) 3857 { 3858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3859 3860 return dd->sw_send_dma_eng_err_status_cnt[23]; 3861 } 3862 3863 static u64 access_sdma_header_storage_cor_err_cnt( 3864 const struct cntr_entry *entry, 3865 void *context, int vl, int mode, u64 data) 3866 { 3867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3868 3869 return dd->sw_send_dma_eng_err_status_cnt[22]; 3870 } 3871 3872 static u64 access_sdma_packet_tracking_cor_err_cnt( 3873 const struct cntr_entry *entry, 3874 void *context, int vl, int mode, u64 data) 3875 { 3876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3877 3878 return dd->sw_send_dma_eng_err_status_cnt[21]; 3879 } 3880 3881 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry, 3882 void *context, int vl, int mode, 3883 u64 data) 3884 { 3885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3886 3887 return dd->sw_send_dma_eng_err_status_cnt[20]; 3888 } 3889 3890 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry, 3891 void *context, int vl, int mode, 3892 u64 data) 3893 { 3894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3895 3896 return dd->sw_send_dma_eng_err_status_cnt[19]; 3897 } 3898 3899 static u64 access_sdma_header_request_fifo_unc_err_cnt( 3900 const struct cntr_entry *entry, 3901 void *context, int vl, int mode, u64 data) 3902 { 3903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3904 3905 return dd->sw_send_dma_eng_err_status_cnt[18]; 3906 } 3907 3908 static u64 access_sdma_header_storage_unc_err_cnt( 3909 const struct cntr_entry *entry, 3910 void *context, int vl, int mode, u64 data) 3911 { 3912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3913 3914 return dd->sw_send_dma_eng_err_status_cnt[17]; 3915 } 3916 3917 static u64 access_sdma_packet_tracking_unc_err_cnt( 3918 const struct cntr_entry *entry, 3919 void *context, int vl, int mode, u64 data) 3920 { 3921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3922 3923 return dd->sw_send_dma_eng_err_status_cnt[16]; 3924 } 3925 3926 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry, 3927 void *context, int vl, int mode, 3928 u64 data) 3929 { 3930 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3931 3932 return dd->sw_send_dma_eng_err_status_cnt[15]; 3933 } 3934 3935 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry, 3936 void *context, int vl, int mode, 3937 u64 data) 3938 { 3939 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3940 3941 return dd->sw_send_dma_eng_err_status_cnt[14]; 3942 } 3943 3944 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry, 3945 void *context, int vl, int mode, 3946 u64 data) 3947 { 3948 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3949 3950 return dd->sw_send_dma_eng_err_status_cnt[13]; 3951 } 3952 3953 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry, 3954 void *context, int vl, int mode, 3955 u64 data) 3956 { 3957 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3958 3959 return dd->sw_send_dma_eng_err_status_cnt[12]; 3960 } 3961 3962 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry, 3963 void *context, int vl, int mode, 3964 u64 data) 3965 { 3966 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3967 3968 return dd->sw_send_dma_eng_err_status_cnt[11]; 3969 } 3970 3971 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry, 3972 void *context, int vl, int mode, 3973 u64 data) 3974 { 3975 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3976 3977 return dd->sw_send_dma_eng_err_status_cnt[10]; 3978 } 3979 3980 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry, 3981 void *context, int vl, int mode, 3982 u64 data) 3983 { 3984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3985 3986 return dd->sw_send_dma_eng_err_status_cnt[9]; 3987 } 3988 3989 static u64 access_sdma_packet_desc_overflow_err_cnt( 3990 const struct cntr_entry *entry, 3991 void *context, int vl, int mode, u64 data) 3992 { 3993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3994 3995 return dd->sw_send_dma_eng_err_status_cnt[8]; 3996 } 3997 3998 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry, 3999 void *context, int vl, 4000 int mode, u64 data) 4001 { 4002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4003 4004 return dd->sw_send_dma_eng_err_status_cnt[7]; 4005 } 4006 4007 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry, 4008 void *context, int vl, int mode, u64 data) 4009 { 4010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4011 4012 return dd->sw_send_dma_eng_err_status_cnt[6]; 4013 } 4014 4015 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry, 4016 void *context, int vl, int mode, 4017 u64 data) 4018 { 4019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4020 4021 return dd->sw_send_dma_eng_err_status_cnt[5]; 4022 } 4023 4024 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry, 4025 void *context, int vl, int mode, 4026 u64 data) 4027 { 4028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4029 4030 return dd->sw_send_dma_eng_err_status_cnt[4]; 4031 } 4032 4033 static u64 access_sdma_tail_out_of_bounds_err_cnt( 4034 const struct cntr_entry *entry, 4035 void *context, int vl, int mode, u64 data) 4036 { 4037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4038 4039 return dd->sw_send_dma_eng_err_status_cnt[3]; 4040 } 4041 4042 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry, 4043 void *context, int vl, int mode, 4044 u64 data) 4045 { 4046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4047 4048 return dd->sw_send_dma_eng_err_status_cnt[2]; 4049 } 4050 4051 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry, 4052 void *context, int vl, int mode, 4053 u64 data) 4054 { 4055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4056 4057 return dd->sw_send_dma_eng_err_status_cnt[1]; 4058 } 4059 4060 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry, 4061 void *context, int vl, int mode, 4062 u64 data) 4063 { 4064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4065 4066 return dd->sw_send_dma_eng_err_status_cnt[0]; 4067 } 4068 4069 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry, 4070 void *context, int vl, int mode, 4071 u64 data) 4072 { 4073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4074 4075 u64 val = 0; 4076 u64 csr = entry->csr; 4077 4078 val = read_write_csr(dd, csr, mode, data); 4079 if (mode == CNTR_MODE_R) { 4080 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ? 4081 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors; 4082 } else if (mode == CNTR_MODE_W) { 4083 dd->sw_rcv_bypass_packet_errors = 0; 4084 } else { 4085 dd_dev_err(dd, "Invalid cntr register access mode"); 4086 return 0; 4087 } 4088 return val; 4089 } 4090 4091 #define def_access_sw_cpu(cntr) \ 4092 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \ 4093 void *context, int vl, int mode, u64 data) \ 4094 { \ 4095 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4096 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \ 4097 ppd->ibport_data.rvp.cntr, vl, \ 4098 mode, data); \ 4099 } 4100 4101 def_access_sw_cpu(rc_acks); 4102 def_access_sw_cpu(rc_qacks); 4103 def_access_sw_cpu(rc_delayed_comp); 4104 4105 #define def_access_ibp_counter(cntr) \ 4106 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \ 4107 void *context, int vl, int mode, u64 data) \ 4108 { \ 4109 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4110 \ 4111 if (vl != CNTR_INVALID_VL) \ 4112 return 0; \ 4113 \ 4114 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \ 4115 mode, data); \ 4116 } 4117 4118 def_access_ibp_counter(loop_pkts); 4119 def_access_ibp_counter(rc_resends); 4120 def_access_ibp_counter(rnr_naks); 4121 def_access_ibp_counter(other_naks); 4122 def_access_ibp_counter(rc_timeouts); 4123 def_access_ibp_counter(pkt_drops); 4124 def_access_ibp_counter(dmawait); 4125 def_access_ibp_counter(rc_seqnak); 4126 def_access_ibp_counter(rc_dupreq); 4127 def_access_ibp_counter(rdma_seq); 4128 def_access_ibp_counter(unaligned); 4129 def_access_ibp_counter(seq_naks); 4130 def_access_ibp_counter(rc_crwaits); 4131 4132 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = { 4133 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH), 4134 [C_RX_LEN_ERR] = RXE32_DEV_CNTR_ELEM(RxLenErr, RCV_LENGTH_ERR_CNT, CNTR_SYNTH), 4135 [C_RX_SHORT_ERR] = RXE32_DEV_CNTR_ELEM(RxShrErr, RCV_SHORT_ERR_CNT, CNTR_SYNTH), 4136 [C_RX_ICRC_ERR] = RXE32_DEV_CNTR_ELEM(RxICrcErr, RCV_ICRC_ERR_CNT, CNTR_SYNTH), 4137 [C_RX_EBP] = RXE32_DEV_CNTR_ELEM(RxEbpCnt, RCV_EBP_CNT, CNTR_SYNTH), 4138 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT, 4139 CNTR_NORMAL), 4140 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT, 4141 CNTR_NORMAL), 4142 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs, 4143 RCV_TID_FLOW_GEN_MISMATCH_CNT, 4144 CNTR_NORMAL), 4145 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL, 4146 CNTR_NORMAL), 4147 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs, 4148 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL), 4149 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt, 4150 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL), 4151 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT, 4152 CNTR_NORMAL), 4153 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT, 4154 CNTR_NORMAL), 4155 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT, 4156 CNTR_NORMAL), 4157 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT, 4158 CNTR_NORMAL), 4159 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT, 4160 CNTR_NORMAL), 4161 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT, 4162 CNTR_NORMAL), 4163 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt, 4164 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL), 4165 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt, 4166 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL), 4167 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT, 4168 CNTR_SYNTH), 4169 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH, 4170 access_dc_rcv_err_cnt), 4171 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT, 4172 CNTR_SYNTH), 4173 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT, 4174 CNTR_SYNTH), 4175 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT, 4176 CNTR_SYNTH), 4177 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts, 4178 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH), 4179 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts, 4180 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT, 4181 CNTR_SYNTH), 4182 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr, 4183 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH), 4184 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT, 4185 CNTR_SYNTH), 4186 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT, 4187 CNTR_SYNTH), 4188 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT, 4189 CNTR_SYNTH), 4190 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT, 4191 CNTR_SYNTH), 4192 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT, 4193 CNTR_SYNTH), 4194 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT, 4195 CNTR_SYNTH), 4196 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT, 4197 CNTR_SYNTH), 4198 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT, 4199 CNTR_SYNTH | CNTR_VL), 4200 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT, 4201 CNTR_SYNTH | CNTR_VL), 4202 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH), 4203 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT, 4204 CNTR_SYNTH | CNTR_VL), 4205 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH), 4206 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT, 4207 CNTR_SYNTH | CNTR_VL), 4208 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT, 4209 CNTR_SYNTH), 4210 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT, 4211 CNTR_SYNTH | CNTR_VL), 4212 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT, 4213 CNTR_SYNTH), 4214 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT, 4215 CNTR_SYNTH | CNTR_VL), 4216 [C_DC_TOTAL_CRC] = 4217 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR, 4218 CNTR_SYNTH), 4219 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0, 4220 CNTR_SYNTH), 4221 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1, 4222 CNTR_SYNTH), 4223 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2, 4224 CNTR_SYNTH), 4225 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3, 4226 CNTR_SYNTH), 4227 [C_DC_CRC_MULT_LN] = 4228 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN, 4229 CNTR_SYNTH), 4230 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT, 4231 CNTR_SYNTH), 4232 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT, 4233 CNTR_SYNTH), 4234 [C_DC_SEQ_CRC_CNT] = 4235 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT, 4236 CNTR_SYNTH), 4237 [C_DC_ESC0_ONLY_CNT] = 4238 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT, 4239 CNTR_SYNTH), 4240 [C_DC_ESC0_PLUS1_CNT] = 4241 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT, 4242 CNTR_SYNTH), 4243 [C_DC_ESC0_PLUS2_CNT] = 4244 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT, 4245 CNTR_SYNTH), 4246 [C_DC_REINIT_FROM_PEER_CNT] = 4247 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 4248 CNTR_SYNTH), 4249 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT, 4250 CNTR_SYNTH), 4251 [C_DC_MISC_FLG_CNT] = 4252 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT, 4253 CNTR_SYNTH), 4254 [C_DC_PRF_GOOD_LTP_CNT] = 4255 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH), 4256 [C_DC_PRF_ACCEPTED_LTP_CNT] = 4257 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT, 4258 CNTR_SYNTH), 4259 [C_DC_PRF_RX_FLIT_CNT] = 4260 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH), 4261 [C_DC_PRF_TX_FLIT_CNT] = 4262 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH), 4263 [C_DC_PRF_CLK_CNTR] = 4264 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH), 4265 [C_DC_PG_DBG_FLIT_CRDTS_CNT] = 4266 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH), 4267 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] = 4268 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT, 4269 CNTR_SYNTH), 4270 [C_DC_PG_STS_TX_SBE_CNT] = 4271 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH), 4272 [C_DC_PG_STS_TX_MBE_CNT] = 4273 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT, 4274 CNTR_SYNTH), 4275 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL, 4276 access_sw_cpu_intr), 4277 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL, 4278 access_sw_cpu_rcv_limit), 4279 [C_SW_CTX0_SEQ_DROP] = CNTR_ELEM("SeqDrop0", 0, 0, CNTR_NORMAL, 4280 access_sw_ctx0_seq_drop), 4281 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL, 4282 access_sw_vtx_wait), 4283 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL, 4284 access_sw_pio_wait), 4285 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL, 4286 access_sw_pio_drain), 4287 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL, 4288 access_sw_kmem_wait), 4289 [C_SW_TID_WAIT] = CNTR_ELEM("TidWait", 0, 0, CNTR_NORMAL, 4290 hfi1_access_sw_tid_wait), 4291 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL, 4292 access_sw_send_schedule), 4293 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn", 4294 SEND_DMA_DESC_FETCHED_CNT, 0, 4295 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4296 dev_access_u32_csr), 4297 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0, 4298 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4299 access_sde_int_cnt), 4300 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0, 4301 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4302 access_sde_err_cnt), 4303 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0, 4304 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4305 access_sde_idle_int_cnt), 4306 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0, 4307 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4308 access_sde_progress_int_cnt), 4309 /* MISC_ERR_STATUS */ 4310 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0, 4311 CNTR_NORMAL, 4312 access_misc_pll_lock_fail_err_cnt), 4313 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0, 4314 CNTR_NORMAL, 4315 access_misc_mbist_fail_err_cnt), 4316 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0, 4317 CNTR_NORMAL, 4318 access_misc_invalid_eep_cmd_err_cnt), 4319 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0, 4320 CNTR_NORMAL, 4321 access_misc_efuse_done_parity_err_cnt), 4322 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0, 4323 CNTR_NORMAL, 4324 access_misc_efuse_write_err_cnt), 4325 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0, 4326 0, CNTR_NORMAL, 4327 access_misc_efuse_read_bad_addr_err_cnt), 4328 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0, 4329 CNTR_NORMAL, 4330 access_misc_efuse_csr_parity_err_cnt), 4331 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0, 4332 CNTR_NORMAL, 4333 access_misc_fw_auth_failed_err_cnt), 4334 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0, 4335 CNTR_NORMAL, 4336 access_misc_key_mismatch_err_cnt), 4337 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0, 4338 CNTR_NORMAL, 4339 access_misc_sbus_write_failed_err_cnt), 4340 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0, 4341 CNTR_NORMAL, 4342 access_misc_csr_write_bad_addr_err_cnt), 4343 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0, 4344 CNTR_NORMAL, 4345 access_misc_csr_read_bad_addr_err_cnt), 4346 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0, 4347 CNTR_NORMAL, 4348 access_misc_csr_parity_err_cnt), 4349 /* CceErrStatus */ 4350 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0, 4351 CNTR_NORMAL, 4352 access_sw_cce_err_status_aggregated_cnt), 4353 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0, 4354 CNTR_NORMAL, 4355 access_cce_msix_csr_parity_err_cnt), 4356 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0, 4357 CNTR_NORMAL, 4358 access_cce_int_map_unc_err_cnt), 4359 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0, 4360 CNTR_NORMAL, 4361 access_cce_int_map_cor_err_cnt), 4362 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0, 4363 CNTR_NORMAL, 4364 access_cce_msix_table_unc_err_cnt), 4365 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0, 4366 CNTR_NORMAL, 4367 access_cce_msix_table_cor_err_cnt), 4368 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0, 4369 0, CNTR_NORMAL, 4370 access_cce_rxdma_conv_fifo_parity_err_cnt), 4371 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0, 4372 0, CNTR_NORMAL, 4373 access_cce_rcpl_async_fifo_parity_err_cnt), 4374 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0, 4375 CNTR_NORMAL, 4376 access_cce_seg_write_bad_addr_err_cnt), 4377 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0, 4378 CNTR_NORMAL, 4379 access_cce_seg_read_bad_addr_err_cnt), 4380 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0, 4381 CNTR_NORMAL, 4382 access_la_triggered_cnt), 4383 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0, 4384 CNTR_NORMAL, 4385 access_cce_trgt_cpl_timeout_err_cnt), 4386 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0, 4387 CNTR_NORMAL, 4388 access_pcic_receive_parity_err_cnt), 4389 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0, 4390 CNTR_NORMAL, 4391 access_pcic_transmit_back_parity_err_cnt), 4392 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0, 4393 0, CNTR_NORMAL, 4394 access_pcic_transmit_front_parity_err_cnt), 4395 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0, 4396 CNTR_NORMAL, 4397 access_pcic_cpl_dat_q_unc_err_cnt), 4398 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0, 4399 CNTR_NORMAL, 4400 access_pcic_cpl_hd_q_unc_err_cnt), 4401 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0, 4402 CNTR_NORMAL, 4403 access_pcic_post_dat_q_unc_err_cnt), 4404 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0, 4405 CNTR_NORMAL, 4406 access_pcic_post_hd_q_unc_err_cnt), 4407 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0, 4408 CNTR_NORMAL, 4409 access_pcic_retry_sot_mem_unc_err_cnt), 4410 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0, 4411 CNTR_NORMAL, 4412 access_pcic_retry_mem_unc_err), 4413 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0, 4414 CNTR_NORMAL, 4415 access_pcic_n_post_dat_q_parity_err_cnt), 4416 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0, 4417 CNTR_NORMAL, 4418 access_pcic_n_post_h_q_parity_err_cnt), 4419 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0, 4420 CNTR_NORMAL, 4421 access_pcic_cpl_dat_q_cor_err_cnt), 4422 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0, 4423 CNTR_NORMAL, 4424 access_pcic_cpl_hd_q_cor_err_cnt), 4425 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0, 4426 CNTR_NORMAL, 4427 access_pcic_post_dat_q_cor_err_cnt), 4428 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0, 4429 CNTR_NORMAL, 4430 access_pcic_post_hd_q_cor_err_cnt), 4431 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0, 4432 CNTR_NORMAL, 4433 access_pcic_retry_sot_mem_cor_err_cnt), 4434 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0, 4435 CNTR_NORMAL, 4436 access_pcic_retry_mem_cor_err_cnt), 4437 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM( 4438 "CceCli1AsyncFifoDbgParityError", 0, 0, 4439 CNTR_NORMAL, 4440 access_cce_cli1_async_fifo_dbg_parity_err_cnt), 4441 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM( 4442 "CceCli1AsyncFifoRxdmaParityError", 0, 0, 4443 CNTR_NORMAL, 4444 access_cce_cli1_async_fifo_rxdma_parity_err_cnt 4445 ), 4446 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM( 4447 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0, 4448 CNTR_NORMAL, 4449 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt), 4450 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM( 4451 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0, 4452 CNTR_NORMAL, 4453 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt), 4454 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0, 4455 0, CNTR_NORMAL, 4456 access_cce_cli2_async_fifo_parity_err_cnt), 4457 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0, 4458 CNTR_NORMAL, 4459 access_cce_csr_cfg_bus_parity_err_cnt), 4460 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0, 4461 0, CNTR_NORMAL, 4462 access_cce_cli0_async_fifo_parity_err_cnt), 4463 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0, 4464 CNTR_NORMAL, 4465 access_cce_rspd_data_parity_err_cnt), 4466 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0, 4467 CNTR_NORMAL, 4468 access_cce_trgt_access_err_cnt), 4469 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0, 4470 0, CNTR_NORMAL, 4471 access_cce_trgt_async_fifo_parity_err_cnt), 4472 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0, 4473 CNTR_NORMAL, 4474 access_cce_csr_write_bad_addr_err_cnt), 4475 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0, 4476 CNTR_NORMAL, 4477 access_cce_csr_read_bad_addr_err_cnt), 4478 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0, 4479 CNTR_NORMAL, 4480 access_ccs_csr_parity_err_cnt), 4481 4482 /* RcvErrStatus */ 4483 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0, 4484 CNTR_NORMAL, 4485 access_rx_csr_parity_err_cnt), 4486 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0, 4487 CNTR_NORMAL, 4488 access_rx_csr_write_bad_addr_err_cnt), 4489 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0, 4490 CNTR_NORMAL, 4491 access_rx_csr_read_bad_addr_err_cnt), 4492 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0, 4493 CNTR_NORMAL, 4494 access_rx_dma_csr_unc_err_cnt), 4495 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0, 4496 CNTR_NORMAL, 4497 access_rx_dma_dq_fsm_encoding_err_cnt), 4498 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0, 4499 CNTR_NORMAL, 4500 access_rx_dma_eq_fsm_encoding_err_cnt), 4501 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0, 4502 CNTR_NORMAL, 4503 access_rx_dma_csr_parity_err_cnt), 4504 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0, 4505 CNTR_NORMAL, 4506 access_rx_rbuf_data_cor_err_cnt), 4507 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0, 4508 CNTR_NORMAL, 4509 access_rx_rbuf_data_unc_err_cnt), 4510 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0, 4511 CNTR_NORMAL, 4512 access_rx_dma_data_fifo_rd_cor_err_cnt), 4513 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0, 4514 CNTR_NORMAL, 4515 access_rx_dma_data_fifo_rd_unc_err_cnt), 4516 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0, 4517 CNTR_NORMAL, 4518 access_rx_dma_hdr_fifo_rd_cor_err_cnt), 4519 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0, 4520 CNTR_NORMAL, 4521 access_rx_dma_hdr_fifo_rd_unc_err_cnt), 4522 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0, 4523 CNTR_NORMAL, 4524 access_rx_rbuf_desc_part2_cor_err_cnt), 4525 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0, 4526 CNTR_NORMAL, 4527 access_rx_rbuf_desc_part2_unc_err_cnt), 4528 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0, 4529 CNTR_NORMAL, 4530 access_rx_rbuf_desc_part1_cor_err_cnt), 4531 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0, 4532 CNTR_NORMAL, 4533 access_rx_rbuf_desc_part1_unc_err_cnt), 4534 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0, 4535 CNTR_NORMAL, 4536 access_rx_hq_intr_fsm_err_cnt), 4537 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0, 4538 CNTR_NORMAL, 4539 access_rx_hq_intr_csr_parity_err_cnt), 4540 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0, 4541 CNTR_NORMAL, 4542 access_rx_lookup_csr_parity_err_cnt), 4543 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0, 4544 CNTR_NORMAL, 4545 access_rx_lookup_rcv_array_cor_err_cnt), 4546 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0, 4547 CNTR_NORMAL, 4548 access_rx_lookup_rcv_array_unc_err_cnt), 4549 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0, 4550 0, CNTR_NORMAL, 4551 access_rx_lookup_des_part2_parity_err_cnt), 4552 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0, 4553 0, CNTR_NORMAL, 4554 access_rx_lookup_des_part1_unc_cor_err_cnt), 4555 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0, 4556 CNTR_NORMAL, 4557 access_rx_lookup_des_part1_unc_err_cnt), 4558 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0, 4559 CNTR_NORMAL, 4560 access_rx_rbuf_next_free_buf_cor_err_cnt), 4561 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0, 4562 CNTR_NORMAL, 4563 access_rx_rbuf_next_free_buf_unc_err_cnt), 4564 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM( 4565 "RxRbufFlInitWrAddrParityErr", 0, 0, 4566 CNTR_NORMAL, 4567 access_rbuf_fl_init_wr_addr_parity_err_cnt), 4568 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0, 4569 0, CNTR_NORMAL, 4570 access_rx_rbuf_fl_initdone_parity_err_cnt), 4571 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0, 4572 0, CNTR_NORMAL, 4573 access_rx_rbuf_fl_write_addr_parity_err_cnt), 4574 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0, 4575 CNTR_NORMAL, 4576 access_rx_rbuf_fl_rd_addr_parity_err_cnt), 4577 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0, 4578 CNTR_NORMAL, 4579 access_rx_rbuf_empty_err_cnt), 4580 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0, 4581 CNTR_NORMAL, 4582 access_rx_rbuf_full_err_cnt), 4583 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0, 4584 CNTR_NORMAL, 4585 access_rbuf_bad_lookup_err_cnt), 4586 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0, 4587 CNTR_NORMAL, 4588 access_rbuf_ctx_id_parity_err_cnt), 4589 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0, 4590 CNTR_NORMAL, 4591 access_rbuf_csr_qeopdw_parity_err_cnt), 4592 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM( 4593 "RxRbufCsrQNumOfPktParityErr", 0, 0, 4594 CNTR_NORMAL, 4595 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt), 4596 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM( 4597 "RxRbufCsrQTlPtrParityErr", 0, 0, 4598 CNTR_NORMAL, 4599 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt), 4600 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0, 4601 0, CNTR_NORMAL, 4602 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt), 4603 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0, 4604 0, CNTR_NORMAL, 4605 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt), 4606 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr", 4607 0, 0, CNTR_NORMAL, 4608 access_rx_rbuf_csr_q_next_buf_parity_err_cnt), 4609 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0, 4610 0, CNTR_NORMAL, 4611 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt), 4612 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM( 4613 "RxRbufCsrQHeadBufNumParityErr", 0, 0, 4614 CNTR_NORMAL, 4615 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt), 4616 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0, 4617 0, CNTR_NORMAL, 4618 access_rx_rbuf_block_list_read_cor_err_cnt), 4619 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0, 4620 0, CNTR_NORMAL, 4621 access_rx_rbuf_block_list_read_unc_err_cnt), 4622 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0, 4623 CNTR_NORMAL, 4624 access_rx_rbuf_lookup_des_cor_err_cnt), 4625 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0, 4626 CNTR_NORMAL, 4627 access_rx_rbuf_lookup_des_unc_err_cnt), 4628 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM( 4629 "RxRbufLookupDesRegUncCorErr", 0, 0, 4630 CNTR_NORMAL, 4631 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt), 4632 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0, 4633 CNTR_NORMAL, 4634 access_rx_rbuf_lookup_des_reg_unc_err_cnt), 4635 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0, 4636 CNTR_NORMAL, 4637 access_rx_rbuf_free_list_cor_err_cnt), 4638 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0, 4639 CNTR_NORMAL, 4640 access_rx_rbuf_free_list_unc_err_cnt), 4641 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0, 4642 CNTR_NORMAL, 4643 access_rx_rcv_fsm_encoding_err_cnt), 4644 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0, 4645 CNTR_NORMAL, 4646 access_rx_dma_flag_cor_err_cnt), 4647 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0, 4648 CNTR_NORMAL, 4649 access_rx_dma_flag_unc_err_cnt), 4650 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0, 4651 CNTR_NORMAL, 4652 access_rx_dc_sop_eop_parity_err_cnt), 4653 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0, 4654 CNTR_NORMAL, 4655 access_rx_rcv_csr_parity_err_cnt), 4656 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0, 4657 CNTR_NORMAL, 4658 access_rx_rcv_qp_map_table_cor_err_cnt), 4659 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0, 4660 CNTR_NORMAL, 4661 access_rx_rcv_qp_map_table_unc_err_cnt), 4662 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0, 4663 CNTR_NORMAL, 4664 access_rx_rcv_data_cor_err_cnt), 4665 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0, 4666 CNTR_NORMAL, 4667 access_rx_rcv_data_unc_err_cnt), 4668 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0, 4669 CNTR_NORMAL, 4670 access_rx_rcv_hdr_cor_err_cnt), 4671 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0, 4672 CNTR_NORMAL, 4673 access_rx_rcv_hdr_unc_err_cnt), 4674 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0, 4675 CNTR_NORMAL, 4676 access_rx_dc_intf_parity_err_cnt), 4677 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0, 4678 CNTR_NORMAL, 4679 access_rx_dma_csr_cor_err_cnt), 4680 /* SendPioErrStatus */ 4681 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0, 4682 CNTR_NORMAL, 4683 access_pio_pec_sop_head_parity_err_cnt), 4684 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0, 4685 CNTR_NORMAL, 4686 access_pio_pcc_sop_head_parity_err_cnt), 4687 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr", 4688 0, 0, CNTR_NORMAL, 4689 access_pio_last_returned_cnt_parity_err_cnt), 4690 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0, 4691 0, CNTR_NORMAL, 4692 access_pio_current_free_cnt_parity_err_cnt), 4693 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0, 4694 CNTR_NORMAL, 4695 access_pio_reserved_31_err_cnt), 4696 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0, 4697 CNTR_NORMAL, 4698 access_pio_reserved_30_err_cnt), 4699 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0, 4700 CNTR_NORMAL, 4701 access_pio_ppmc_sop_len_err_cnt), 4702 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0, 4703 CNTR_NORMAL, 4704 access_pio_ppmc_bqc_mem_parity_err_cnt), 4705 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0, 4706 CNTR_NORMAL, 4707 access_pio_vl_fifo_parity_err_cnt), 4708 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0, 4709 CNTR_NORMAL, 4710 access_pio_vlf_sop_parity_err_cnt), 4711 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0, 4712 CNTR_NORMAL, 4713 access_pio_vlf_v1_len_parity_err_cnt), 4714 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0, 4715 CNTR_NORMAL, 4716 access_pio_block_qw_count_parity_err_cnt), 4717 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0, 4718 CNTR_NORMAL, 4719 access_pio_write_qw_valid_parity_err_cnt), 4720 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0, 4721 CNTR_NORMAL, 4722 access_pio_state_machine_err_cnt), 4723 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0, 4724 CNTR_NORMAL, 4725 access_pio_write_data_parity_err_cnt), 4726 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0, 4727 CNTR_NORMAL, 4728 access_pio_host_addr_mem_cor_err_cnt), 4729 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0, 4730 CNTR_NORMAL, 4731 access_pio_host_addr_mem_unc_err_cnt), 4732 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0, 4733 CNTR_NORMAL, 4734 access_pio_pkt_evict_sm_or_arb_sm_err_cnt), 4735 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0, 4736 CNTR_NORMAL, 4737 access_pio_init_sm_in_err_cnt), 4738 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0, 4739 CNTR_NORMAL, 4740 access_pio_ppmc_pbl_fifo_err_cnt), 4741 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0, 4742 0, CNTR_NORMAL, 4743 access_pio_credit_ret_fifo_parity_err_cnt), 4744 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0, 4745 CNTR_NORMAL, 4746 access_pio_v1_len_mem_bank1_cor_err_cnt), 4747 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0, 4748 CNTR_NORMAL, 4749 access_pio_v1_len_mem_bank0_cor_err_cnt), 4750 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0, 4751 CNTR_NORMAL, 4752 access_pio_v1_len_mem_bank1_unc_err_cnt), 4753 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0, 4754 CNTR_NORMAL, 4755 access_pio_v1_len_mem_bank0_unc_err_cnt), 4756 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0, 4757 CNTR_NORMAL, 4758 access_pio_sm_pkt_reset_parity_err_cnt), 4759 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0, 4760 CNTR_NORMAL, 4761 access_pio_pkt_evict_fifo_parity_err_cnt), 4762 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM( 4763 "PioSbrdctrlCrrelFifoParityErr", 0, 0, 4764 CNTR_NORMAL, 4765 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt), 4766 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0, 4767 CNTR_NORMAL, 4768 access_pio_sbrdctl_crrel_parity_err_cnt), 4769 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0, 4770 CNTR_NORMAL, 4771 access_pio_pec_fifo_parity_err_cnt), 4772 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0, 4773 CNTR_NORMAL, 4774 access_pio_pcc_fifo_parity_err_cnt), 4775 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0, 4776 CNTR_NORMAL, 4777 access_pio_sb_mem_fifo1_err_cnt), 4778 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0, 4779 CNTR_NORMAL, 4780 access_pio_sb_mem_fifo0_err_cnt), 4781 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0, 4782 CNTR_NORMAL, 4783 access_pio_csr_parity_err_cnt), 4784 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0, 4785 CNTR_NORMAL, 4786 access_pio_write_addr_parity_err_cnt), 4787 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0, 4788 CNTR_NORMAL, 4789 access_pio_write_bad_ctxt_err_cnt), 4790 /* SendDmaErrStatus */ 4791 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0, 4792 0, CNTR_NORMAL, 4793 access_sdma_pcie_req_tracking_cor_err_cnt), 4794 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0, 4795 0, CNTR_NORMAL, 4796 access_sdma_pcie_req_tracking_unc_err_cnt), 4797 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0, 4798 CNTR_NORMAL, 4799 access_sdma_csr_parity_err_cnt), 4800 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0, 4801 CNTR_NORMAL, 4802 access_sdma_rpy_tag_err_cnt), 4803 /* SendEgressErrStatus */ 4804 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0, 4805 CNTR_NORMAL, 4806 access_tx_read_pio_memory_csr_unc_err_cnt), 4807 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0, 4808 0, CNTR_NORMAL, 4809 access_tx_read_sdma_memory_csr_err_cnt), 4810 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0, 4811 CNTR_NORMAL, 4812 access_tx_egress_fifo_cor_err_cnt), 4813 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0, 4814 CNTR_NORMAL, 4815 access_tx_read_pio_memory_cor_err_cnt), 4816 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0, 4817 CNTR_NORMAL, 4818 access_tx_read_sdma_memory_cor_err_cnt), 4819 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0, 4820 CNTR_NORMAL, 4821 access_tx_sb_hdr_cor_err_cnt), 4822 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0, 4823 CNTR_NORMAL, 4824 access_tx_credit_overrun_err_cnt), 4825 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0, 4826 CNTR_NORMAL, 4827 access_tx_launch_fifo8_cor_err_cnt), 4828 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0, 4829 CNTR_NORMAL, 4830 access_tx_launch_fifo7_cor_err_cnt), 4831 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0, 4832 CNTR_NORMAL, 4833 access_tx_launch_fifo6_cor_err_cnt), 4834 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0, 4835 CNTR_NORMAL, 4836 access_tx_launch_fifo5_cor_err_cnt), 4837 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0, 4838 CNTR_NORMAL, 4839 access_tx_launch_fifo4_cor_err_cnt), 4840 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0, 4841 CNTR_NORMAL, 4842 access_tx_launch_fifo3_cor_err_cnt), 4843 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0, 4844 CNTR_NORMAL, 4845 access_tx_launch_fifo2_cor_err_cnt), 4846 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0, 4847 CNTR_NORMAL, 4848 access_tx_launch_fifo1_cor_err_cnt), 4849 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0, 4850 CNTR_NORMAL, 4851 access_tx_launch_fifo0_cor_err_cnt), 4852 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0, 4853 CNTR_NORMAL, 4854 access_tx_credit_return_vl_err_cnt), 4855 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0, 4856 CNTR_NORMAL, 4857 access_tx_hcrc_insertion_err_cnt), 4858 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0, 4859 CNTR_NORMAL, 4860 access_tx_egress_fifo_unc_err_cnt), 4861 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0, 4862 CNTR_NORMAL, 4863 access_tx_read_pio_memory_unc_err_cnt), 4864 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0, 4865 CNTR_NORMAL, 4866 access_tx_read_sdma_memory_unc_err_cnt), 4867 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0, 4868 CNTR_NORMAL, 4869 access_tx_sb_hdr_unc_err_cnt), 4870 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0, 4871 CNTR_NORMAL, 4872 access_tx_credit_return_partiy_err_cnt), 4873 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr", 4874 0, 0, CNTR_NORMAL, 4875 access_tx_launch_fifo8_unc_or_parity_err_cnt), 4876 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr", 4877 0, 0, CNTR_NORMAL, 4878 access_tx_launch_fifo7_unc_or_parity_err_cnt), 4879 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr", 4880 0, 0, CNTR_NORMAL, 4881 access_tx_launch_fifo6_unc_or_parity_err_cnt), 4882 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr", 4883 0, 0, CNTR_NORMAL, 4884 access_tx_launch_fifo5_unc_or_parity_err_cnt), 4885 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr", 4886 0, 0, CNTR_NORMAL, 4887 access_tx_launch_fifo4_unc_or_parity_err_cnt), 4888 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr", 4889 0, 0, CNTR_NORMAL, 4890 access_tx_launch_fifo3_unc_or_parity_err_cnt), 4891 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr", 4892 0, 0, CNTR_NORMAL, 4893 access_tx_launch_fifo2_unc_or_parity_err_cnt), 4894 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr", 4895 0, 0, CNTR_NORMAL, 4896 access_tx_launch_fifo1_unc_or_parity_err_cnt), 4897 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr", 4898 0, 0, CNTR_NORMAL, 4899 access_tx_launch_fifo0_unc_or_parity_err_cnt), 4900 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr", 4901 0, 0, CNTR_NORMAL, 4902 access_tx_sdma15_disallowed_packet_err_cnt), 4903 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr", 4904 0, 0, CNTR_NORMAL, 4905 access_tx_sdma14_disallowed_packet_err_cnt), 4906 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr", 4907 0, 0, CNTR_NORMAL, 4908 access_tx_sdma13_disallowed_packet_err_cnt), 4909 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr", 4910 0, 0, CNTR_NORMAL, 4911 access_tx_sdma12_disallowed_packet_err_cnt), 4912 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr", 4913 0, 0, CNTR_NORMAL, 4914 access_tx_sdma11_disallowed_packet_err_cnt), 4915 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr", 4916 0, 0, CNTR_NORMAL, 4917 access_tx_sdma10_disallowed_packet_err_cnt), 4918 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr", 4919 0, 0, CNTR_NORMAL, 4920 access_tx_sdma9_disallowed_packet_err_cnt), 4921 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr", 4922 0, 0, CNTR_NORMAL, 4923 access_tx_sdma8_disallowed_packet_err_cnt), 4924 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr", 4925 0, 0, CNTR_NORMAL, 4926 access_tx_sdma7_disallowed_packet_err_cnt), 4927 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr", 4928 0, 0, CNTR_NORMAL, 4929 access_tx_sdma6_disallowed_packet_err_cnt), 4930 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr", 4931 0, 0, CNTR_NORMAL, 4932 access_tx_sdma5_disallowed_packet_err_cnt), 4933 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr", 4934 0, 0, CNTR_NORMAL, 4935 access_tx_sdma4_disallowed_packet_err_cnt), 4936 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr", 4937 0, 0, CNTR_NORMAL, 4938 access_tx_sdma3_disallowed_packet_err_cnt), 4939 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr", 4940 0, 0, CNTR_NORMAL, 4941 access_tx_sdma2_disallowed_packet_err_cnt), 4942 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr", 4943 0, 0, CNTR_NORMAL, 4944 access_tx_sdma1_disallowed_packet_err_cnt), 4945 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr", 4946 0, 0, CNTR_NORMAL, 4947 access_tx_sdma0_disallowed_packet_err_cnt), 4948 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0, 4949 CNTR_NORMAL, 4950 access_tx_config_parity_err_cnt), 4951 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0, 4952 CNTR_NORMAL, 4953 access_tx_sbrd_ctl_csr_parity_err_cnt), 4954 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0, 4955 CNTR_NORMAL, 4956 access_tx_launch_csr_parity_err_cnt), 4957 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0, 4958 CNTR_NORMAL, 4959 access_tx_illegal_vl_err_cnt), 4960 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM( 4961 "TxSbrdCtlStateMachineParityErr", 0, 0, 4962 CNTR_NORMAL, 4963 access_tx_sbrd_ctl_state_machine_parity_err_cnt), 4964 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0, 4965 CNTR_NORMAL, 4966 access_egress_reserved_10_err_cnt), 4967 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0, 4968 CNTR_NORMAL, 4969 access_egress_reserved_9_err_cnt), 4970 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr", 4971 0, 0, CNTR_NORMAL, 4972 access_tx_sdma_launch_intf_parity_err_cnt), 4973 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0, 4974 CNTR_NORMAL, 4975 access_tx_pio_launch_intf_parity_err_cnt), 4976 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0, 4977 CNTR_NORMAL, 4978 access_egress_reserved_6_err_cnt), 4979 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0, 4980 CNTR_NORMAL, 4981 access_tx_incorrect_link_state_err_cnt), 4982 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0, 4983 CNTR_NORMAL, 4984 access_tx_linkdown_err_cnt), 4985 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM( 4986 "EgressFifoUnderrunOrParityErr", 0, 0, 4987 CNTR_NORMAL, 4988 access_tx_egress_fifi_underrun_or_parity_err_cnt), 4989 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0, 4990 CNTR_NORMAL, 4991 access_egress_reserved_2_err_cnt), 4992 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0, 4993 CNTR_NORMAL, 4994 access_tx_pkt_integrity_mem_unc_err_cnt), 4995 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0, 4996 CNTR_NORMAL, 4997 access_tx_pkt_integrity_mem_cor_err_cnt), 4998 /* SendErrStatus */ 4999 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0, 5000 CNTR_NORMAL, 5001 access_send_csr_write_bad_addr_err_cnt), 5002 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0, 5003 CNTR_NORMAL, 5004 access_send_csr_read_bad_addr_err_cnt), 5005 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0, 5006 CNTR_NORMAL, 5007 access_send_csr_parity_cnt), 5008 /* SendCtxtErrStatus */ 5009 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0, 5010 CNTR_NORMAL, 5011 access_pio_write_out_of_bounds_err_cnt), 5012 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0, 5013 CNTR_NORMAL, 5014 access_pio_write_overflow_err_cnt), 5015 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr", 5016 0, 0, CNTR_NORMAL, 5017 access_pio_write_crosses_boundary_err_cnt), 5018 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0, 5019 CNTR_NORMAL, 5020 access_pio_disallowed_packet_err_cnt), 5021 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0, 5022 CNTR_NORMAL, 5023 access_pio_inconsistent_sop_err_cnt), 5024 /* SendDmaEngErrStatus */ 5025 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr", 5026 0, 0, CNTR_NORMAL, 5027 access_sdma_header_request_fifo_cor_err_cnt), 5028 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0, 5029 CNTR_NORMAL, 5030 access_sdma_header_storage_cor_err_cnt), 5031 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0, 5032 CNTR_NORMAL, 5033 access_sdma_packet_tracking_cor_err_cnt), 5034 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0, 5035 CNTR_NORMAL, 5036 access_sdma_assembly_cor_err_cnt), 5037 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0, 5038 CNTR_NORMAL, 5039 access_sdma_desc_table_cor_err_cnt), 5040 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr", 5041 0, 0, CNTR_NORMAL, 5042 access_sdma_header_request_fifo_unc_err_cnt), 5043 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0, 5044 CNTR_NORMAL, 5045 access_sdma_header_storage_unc_err_cnt), 5046 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0, 5047 CNTR_NORMAL, 5048 access_sdma_packet_tracking_unc_err_cnt), 5049 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0, 5050 CNTR_NORMAL, 5051 access_sdma_assembly_unc_err_cnt), 5052 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0, 5053 CNTR_NORMAL, 5054 access_sdma_desc_table_unc_err_cnt), 5055 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0, 5056 CNTR_NORMAL, 5057 access_sdma_timeout_err_cnt), 5058 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0, 5059 CNTR_NORMAL, 5060 access_sdma_header_length_err_cnt), 5061 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0, 5062 CNTR_NORMAL, 5063 access_sdma_header_address_err_cnt), 5064 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0, 5065 CNTR_NORMAL, 5066 access_sdma_header_select_err_cnt), 5067 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0, 5068 CNTR_NORMAL, 5069 access_sdma_reserved_9_err_cnt), 5070 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0, 5071 CNTR_NORMAL, 5072 access_sdma_packet_desc_overflow_err_cnt), 5073 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0, 5074 CNTR_NORMAL, 5075 access_sdma_length_mismatch_err_cnt), 5076 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0, 5077 CNTR_NORMAL, 5078 access_sdma_halt_err_cnt), 5079 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0, 5080 CNTR_NORMAL, 5081 access_sdma_mem_read_err_cnt), 5082 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0, 5083 CNTR_NORMAL, 5084 access_sdma_first_desc_err_cnt), 5085 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0, 5086 CNTR_NORMAL, 5087 access_sdma_tail_out_of_bounds_err_cnt), 5088 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0, 5089 CNTR_NORMAL, 5090 access_sdma_too_long_err_cnt), 5091 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0, 5092 CNTR_NORMAL, 5093 access_sdma_gen_mismatch_err_cnt), 5094 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0, 5095 CNTR_NORMAL, 5096 access_sdma_wrong_dw_err_cnt), 5097 }; 5098 5099 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = { 5100 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT, 5101 CNTR_NORMAL), 5102 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT, 5103 CNTR_NORMAL), 5104 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT, 5105 CNTR_NORMAL), 5106 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT, 5107 CNTR_NORMAL), 5108 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT, 5109 CNTR_NORMAL), 5110 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT, 5111 CNTR_NORMAL), 5112 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT, 5113 CNTR_NORMAL), 5114 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL), 5115 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL), 5116 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH), 5117 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT, 5118 CNTR_SYNTH | CNTR_VL), 5119 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT, 5120 CNTR_SYNTH | CNTR_VL), 5121 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT, 5122 CNTR_SYNTH | CNTR_VL), 5123 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL), 5124 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL), 5125 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5126 access_sw_link_dn_cnt), 5127 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5128 access_sw_link_up_cnt), 5129 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL, 5130 access_sw_unknown_frame_cnt), 5131 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5132 access_sw_xmit_discards), 5133 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0, 5134 CNTR_SYNTH | CNTR_32BIT | CNTR_VL, 5135 access_sw_xmit_discards), 5136 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH, 5137 access_xmit_constraint_errs), 5138 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH, 5139 access_rcv_constraint_errs), 5140 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts), 5141 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends), 5142 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks), 5143 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks), 5144 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts), 5145 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops), 5146 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait), 5147 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak), 5148 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq), 5149 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq), 5150 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned), 5151 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks), 5152 [C_SW_IBP_RC_CRWAITS] = SW_IBP_CNTR(RcCrWait, rc_crwaits), 5153 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL, 5154 access_sw_cpu_rc_acks), 5155 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL, 5156 access_sw_cpu_rc_qacks), 5157 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL, 5158 access_sw_cpu_rc_delayed_comp), 5159 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1), 5160 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3), 5161 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5), 5162 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7), 5163 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9), 5164 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11), 5165 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13), 5166 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15), 5167 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17), 5168 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19), 5169 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21), 5170 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23), 5171 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25), 5172 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27), 5173 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29), 5174 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31), 5175 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33), 5176 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35), 5177 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37), 5178 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39), 5179 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41), 5180 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43), 5181 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45), 5182 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47), 5183 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49), 5184 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51), 5185 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53), 5186 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55), 5187 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57), 5188 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59), 5189 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61), 5190 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63), 5191 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65), 5192 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67), 5193 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69), 5194 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71), 5195 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73), 5196 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75), 5197 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77), 5198 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79), 5199 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81), 5200 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83), 5201 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85), 5202 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87), 5203 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89), 5204 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91), 5205 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93), 5206 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95), 5207 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97), 5208 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99), 5209 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101), 5210 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103), 5211 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105), 5212 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107), 5213 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109), 5214 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111), 5215 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113), 5216 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115), 5217 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117), 5218 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119), 5219 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121), 5220 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123), 5221 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125), 5222 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127), 5223 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129), 5224 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131), 5225 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133), 5226 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135), 5227 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137), 5228 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139), 5229 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141), 5230 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143), 5231 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145), 5232 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147), 5233 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149), 5234 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151), 5235 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153), 5236 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155), 5237 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157), 5238 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159), 5239 }; 5240 5241 /* ======================================================================== */ 5242 5243 /* return true if this is chip revision revision a */ 5244 int is_ax(struct hfi1_devdata *dd) 5245 { 5246 u8 chip_rev_minor = 5247 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5248 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5249 return (chip_rev_minor & 0xf0) == 0; 5250 } 5251 5252 /* return true if this is chip revision revision b */ 5253 int is_bx(struct hfi1_devdata *dd) 5254 { 5255 u8 chip_rev_minor = 5256 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5257 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5258 return (chip_rev_minor & 0xF0) == 0x10; 5259 } 5260 5261 /* return true is kernel urg disabled for rcd */ 5262 bool is_urg_masked(struct hfi1_ctxtdata *rcd) 5263 { 5264 u64 mask; 5265 u32 is = IS_RCVURGENT_START + rcd->ctxt; 5266 u8 bit = is % 64; 5267 5268 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64))); 5269 return !(mask & BIT_ULL(bit)); 5270 } 5271 5272 /* 5273 * Append string s to buffer buf. Arguments curp and len are the current 5274 * position and remaining length, respectively. 5275 * 5276 * return 0 on success, 1 on out of room 5277 */ 5278 static int append_str(char *buf, char **curp, int *lenp, const char *s) 5279 { 5280 char *p = *curp; 5281 int len = *lenp; 5282 int result = 0; /* success */ 5283 char c; 5284 5285 /* add a comma, if first in the buffer */ 5286 if (p != buf) { 5287 if (len == 0) { 5288 result = 1; /* out of room */ 5289 goto done; 5290 } 5291 *p++ = ','; 5292 len--; 5293 } 5294 5295 /* copy the string */ 5296 while ((c = *s++) != 0) { 5297 if (len == 0) { 5298 result = 1; /* out of room */ 5299 goto done; 5300 } 5301 *p++ = c; 5302 len--; 5303 } 5304 5305 done: 5306 /* write return values */ 5307 *curp = p; 5308 *lenp = len; 5309 5310 return result; 5311 } 5312 5313 /* 5314 * Using the given flag table, print a comma separated string into 5315 * the buffer. End in '*' if the buffer is too short. 5316 */ 5317 static char *flag_string(char *buf, int buf_len, u64 flags, 5318 struct flag_table *table, int table_size) 5319 { 5320 char extra[32]; 5321 char *p = buf; 5322 int len = buf_len; 5323 int no_room = 0; 5324 int i; 5325 5326 /* make sure there is at least 2 so we can form "*" */ 5327 if (len < 2) 5328 return ""; 5329 5330 len--; /* leave room for a nul */ 5331 for (i = 0; i < table_size; i++) { 5332 if (flags & table[i].flag) { 5333 no_room = append_str(buf, &p, &len, table[i].str); 5334 if (no_room) 5335 break; 5336 flags &= ~table[i].flag; 5337 } 5338 } 5339 5340 /* any undocumented bits left? */ 5341 if (!no_room && flags) { 5342 snprintf(extra, sizeof(extra), "bits 0x%llx", flags); 5343 no_room = append_str(buf, &p, &len, extra); 5344 } 5345 5346 /* add * if ran out of room */ 5347 if (no_room) { 5348 /* may need to back up to add space for a '*' */ 5349 if (len == 0) 5350 --p; 5351 *p++ = '*'; 5352 } 5353 5354 /* add final nul - space already allocated above */ 5355 *p = 0; 5356 return buf; 5357 } 5358 5359 /* first 8 CCE error interrupt source names */ 5360 static const char * const cce_misc_names[] = { 5361 "CceErrInt", /* 0 */ 5362 "RxeErrInt", /* 1 */ 5363 "MiscErrInt", /* 2 */ 5364 "Reserved3", /* 3 */ 5365 "PioErrInt", /* 4 */ 5366 "SDmaErrInt", /* 5 */ 5367 "EgressErrInt", /* 6 */ 5368 "TxeErrInt" /* 7 */ 5369 }; 5370 5371 /* 5372 * Return the miscellaneous error interrupt name. 5373 */ 5374 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source) 5375 { 5376 if (source < ARRAY_SIZE(cce_misc_names)) 5377 strncpy(buf, cce_misc_names[source], bsize); 5378 else 5379 snprintf(buf, bsize, "Reserved%u", 5380 source + IS_GENERAL_ERR_START); 5381 5382 return buf; 5383 } 5384 5385 /* 5386 * Return the SDMA engine error interrupt name. 5387 */ 5388 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source) 5389 { 5390 snprintf(buf, bsize, "SDmaEngErrInt%u", source); 5391 return buf; 5392 } 5393 5394 /* 5395 * Return the send context error interrupt name. 5396 */ 5397 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source) 5398 { 5399 snprintf(buf, bsize, "SendCtxtErrInt%u", source); 5400 return buf; 5401 } 5402 5403 static const char * const various_names[] = { 5404 "PbcInt", 5405 "GpioAssertInt", 5406 "Qsfp1Int", 5407 "Qsfp2Int", 5408 "TCritInt" 5409 }; 5410 5411 /* 5412 * Return the various interrupt name. 5413 */ 5414 static char *is_various_name(char *buf, size_t bsize, unsigned int source) 5415 { 5416 if (source < ARRAY_SIZE(various_names)) 5417 strncpy(buf, various_names[source], bsize); 5418 else 5419 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START); 5420 return buf; 5421 } 5422 5423 /* 5424 * Return the DC interrupt name. 5425 */ 5426 static char *is_dc_name(char *buf, size_t bsize, unsigned int source) 5427 { 5428 static const char * const dc_int_names[] = { 5429 "common", 5430 "lcb", 5431 "8051", 5432 "lbm" /* local block merge */ 5433 }; 5434 5435 if (source < ARRAY_SIZE(dc_int_names)) 5436 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]); 5437 else 5438 snprintf(buf, bsize, "DCInt%u", source); 5439 return buf; 5440 } 5441 5442 static const char * const sdma_int_names[] = { 5443 "SDmaInt", 5444 "SdmaIdleInt", 5445 "SdmaProgressInt", 5446 }; 5447 5448 /* 5449 * Return the SDMA engine interrupt name. 5450 */ 5451 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source) 5452 { 5453 /* what interrupt */ 5454 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 5455 /* which engine */ 5456 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 5457 5458 if (likely(what < 3)) 5459 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which); 5460 else 5461 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source); 5462 return buf; 5463 } 5464 5465 /* 5466 * Return the receive available interrupt name. 5467 */ 5468 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source) 5469 { 5470 snprintf(buf, bsize, "RcvAvailInt%u", source); 5471 return buf; 5472 } 5473 5474 /* 5475 * Return the receive urgent interrupt name. 5476 */ 5477 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source) 5478 { 5479 snprintf(buf, bsize, "RcvUrgentInt%u", source); 5480 return buf; 5481 } 5482 5483 /* 5484 * Return the send credit interrupt name. 5485 */ 5486 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source) 5487 { 5488 snprintf(buf, bsize, "SendCreditInt%u", source); 5489 return buf; 5490 } 5491 5492 /* 5493 * Return the reserved interrupt name. 5494 */ 5495 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source) 5496 { 5497 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START); 5498 return buf; 5499 } 5500 5501 static char *cce_err_status_string(char *buf, int buf_len, u64 flags) 5502 { 5503 return flag_string(buf, buf_len, flags, 5504 cce_err_status_flags, 5505 ARRAY_SIZE(cce_err_status_flags)); 5506 } 5507 5508 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags) 5509 { 5510 return flag_string(buf, buf_len, flags, 5511 rxe_err_status_flags, 5512 ARRAY_SIZE(rxe_err_status_flags)); 5513 } 5514 5515 static char *misc_err_status_string(char *buf, int buf_len, u64 flags) 5516 { 5517 return flag_string(buf, buf_len, flags, misc_err_status_flags, 5518 ARRAY_SIZE(misc_err_status_flags)); 5519 } 5520 5521 static char *pio_err_status_string(char *buf, int buf_len, u64 flags) 5522 { 5523 return flag_string(buf, buf_len, flags, 5524 pio_err_status_flags, 5525 ARRAY_SIZE(pio_err_status_flags)); 5526 } 5527 5528 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags) 5529 { 5530 return flag_string(buf, buf_len, flags, 5531 sdma_err_status_flags, 5532 ARRAY_SIZE(sdma_err_status_flags)); 5533 } 5534 5535 static char *egress_err_status_string(char *buf, int buf_len, u64 flags) 5536 { 5537 return flag_string(buf, buf_len, flags, 5538 egress_err_status_flags, 5539 ARRAY_SIZE(egress_err_status_flags)); 5540 } 5541 5542 static char *egress_err_info_string(char *buf, int buf_len, u64 flags) 5543 { 5544 return flag_string(buf, buf_len, flags, 5545 egress_err_info_flags, 5546 ARRAY_SIZE(egress_err_info_flags)); 5547 } 5548 5549 static char *send_err_status_string(char *buf, int buf_len, u64 flags) 5550 { 5551 return flag_string(buf, buf_len, flags, 5552 send_err_status_flags, 5553 ARRAY_SIZE(send_err_status_flags)); 5554 } 5555 5556 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5557 { 5558 char buf[96]; 5559 int i = 0; 5560 5561 /* 5562 * For most these errors, there is nothing that can be done except 5563 * report or record it. 5564 */ 5565 dd_dev_info(dd, "CCE Error: %s\n", 5566 cce_err_status_string(buf, sizeof(buf), reg)); 5567 5568 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) && 5569 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) { 5570 /* this error requires a manual drop into SPC freeze mode */ 5571 /* then a fix up */ 5572 start_freeze_handling(dd->pport, FREEZE_SELF); 5573 } 5574 5575 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) { 5576 if (reg & (1ull << i)) { 5577 incr_cntr64(&dd->cce_err_status_cnt[i]); 5578 /* maintain a counter over all cce_err_status errors */ 5579 incr_cntr64(&dd->sw_cce_err_status_aggregate); 5580 } 5581 } 5582 } 5583 5584 /* 5585 * Check counters for receive errors that do not have an interrupt 5586 * associated with them. 5587 */ 5588 #define RCVERR_CHECK_TIME 10 5589 static void update_rcverr_timer(struct timer_list *t) 5590 { 5591 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer); 5592 struct hfi1_pportdata *ppd = dd->pport; 5593 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL); 5594 5595 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt && 5596 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) { 5597 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__); 5598 set_link_down_reason( 5599 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0, 5600 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN); 5601 queue_work(ppd->link_wq, &ppd->link_bounce_work); 5602 } 5603 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt; 5604 5605 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5606 } 5607 5608 static int init_rcverr(struct hfi1_devdata *dd) 5609 { 5610 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0); 5611 /* Assume the hardware counter has been reset */ 5612 dd->rcv_ovfl_cnt = 0; 5613 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5614 } 5615 5616 static void free_rcverr(struct hfi1_devdata *dd) 5617 { 5618 if (dd->rcverr_timer.function) 5619 del_timer_sync(&dd->rcverr_timer); 5620 } 5621 5622 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5623 { 5624 char buf[96]; 5625 int i = 0; 5626 5627 dd_dev_info(dd, "Receive Error: %s\n", 5628 rxe_err_status_string(buf, sizeof(buf), reg)); 5629 5630 if (reg & ALL_RXE_FREEZE_ERR) { 5631 int flags = 0; 5632 5633 /* 5634 * Freeze mode recovery is disabled for the errors 5635 * in RXE_FREEZE_ABORT_MASK 5636 */ 5637 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK)) 5638 flags = FREEZE_ABORT; 5639 5640 start_freeze_handling(dd->pport, flags); 5641 } 5642 5643 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) { 5644 if (reg & (1ull << i)) 5645 incr_cntr64(&dd->rcv_err_status_cnt[i]); 5646 } 5647 } 5648 5649 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5650 { 5651 char buf[96]; 5652 int i = 0; 5653 5654 dd_dev_info(dd, "Misc Error: %s", 5655 misc_err_status_string(buf, sizeof(buf), reg)); 5656 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) { 5657 if (reg & (1ull << i)) 5658 incr_cntr64(&dd->misc_err_status_cnt[i]); 5659 } 5660 } 5661 5662 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5663 { 5664 char buf[96]; 5665 int i = 0; 5666 5667 dd_dev_info(dd, "PIO Error: %s\n", 5668 pio_err_status_string(buf, sizeof(buf), reg)); 5669 5670 if (reg & ALL_PIO_FREEZE_ERR) 5671 start_freeze_handling(dd->pport, 0); 5672 5673 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) { 5674 if (reg & (1ull << i)) 5675 incr_cntr64(&dd->send_pio_err_status_cnt[i]); 5676 } 5677 } 5678 5679 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5680 { 5681 char buf[96]; 5682 int i = 0; 5683 5684 dd_dev_info(dd, "SDMA Error: %s\n", 5685 sdma_err_status_string(buf, sizeof(buf), reg)); 5686 5687 if (reg & ALL_SDMA_FREEZE_ERR) 5688 start_freeze_handling(dd->pport, 0); 5689 5690 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) { 5691 if (reg & (1ull << i)) 5692 incr_cntr64(&dd->send_dma_err_status_cnt[i]); 5693 } 5694 } 5695 5696 static inline void __count_port_discards(struct hfi1_pportdata *ppd) 5697 { 5698 incr_cntr64(&ppd->port_xmit_discards); 5699 } 5700 5701 static void count_port_inactive(struct hfi1_devdata *dd) 5702 { 5703 __count_port_discards(dd->pport); 5704 } 5705 5706 /* 5707 * We have had a "disallowed packet" error during egress. Determine the 5708 * integrity check which failed, and update relevant error counter, etc. 5709 * 5710 * Note that the SEND_EGRESS_ERR_INFO register has only a single 5711 * bit of state per integrity check, and so we can miss the reason for an 5712 * egress error if more than one packet fails the same integrity check 5713 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO. 5714 */ 5715 static void handle_send_egress_err_info(struct hfi1_devdata *dd, 5716 int vl) 5717 { 5718 struct hfi1_pportdata *ppd = dd->pport; 5719 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ 5720 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); 5721 char buf[96]; 5722 5723 /* clear down all observed info as quickly as possible after read */ 5724 write_csr(dd, SEND_EGRESS_ERR_INFO, info); 5725 5726 dd_dev_info(dd, 5727 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n", 5728 info, egress_err_info_string(buf, sizeof(buf), info), src); 5729 5730 /* Eventually add other counters for each bit */ 5731 if (info & PORT_DISCARD_EGRESS_ERRS) { 5732 int weight, i; 5733 5734 /* 5735 * Count all applicable bits as individual errors and 5736 * attribute them to the packet that triggered this handler. 5737 * This may not be completely accurate due to limitations 5738 * on the available hardware error information. There is 5739 * a single information register and any number of error 5740 * packets may have occurred and contributed to it before 5741 * this routine is called. This means that: 5742 * a) If multiple packets with the same error occur before 5743 * this routine is called, earlier packets are missed. 5744 * There is only a single bit for each error type. 5745 * b) Errors may not be attributed to the correct VL. 5746 * The driver is attributing all bits in the info register 5747 * to the packet that triggered this call, but bits 5748 * could be an accumulation of different packets with 5749 * different VLs. 5750 * c) A single error packet may have multiple counts attached 5751 * to it. There is no way for the driver to know if 5752 * multiple bits set in the info register are due to a 5753 * single packet or multiple packets. The driver assumes 5754 * multiple packets. 5755 */ 5756 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS); 5757 for (i = 0; i < weight; i++) { 5758 __count_port_discards(ppd); 5759 if (vl >= 0 && vl < TXE_NUM_DATA_VL) 5760 incr_cntr64(&ppd->port_xmit_discards_vl[vl]); 5761 else if (vl == 15) 5762 incr_cntr64(&ppd->port_xmit_discards_vl 5763 [C_VL_15]); 5764 } 5765 } 5766 } 5767 5768 /* 5769 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5770 * register. Does it represent a 'port inactive' error? 5771 */ 5772 static inline int port_inactive_err(u64 posn) 5773 { 5774 return (posn >= SEES(TX_LINKDOWN) && 5775 posn <= SEES(TX_INCORRECT_LINK_STATE)); 5776 } 5777 5778 /* 5779 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5780 * register. Does it represent a 'disallowed packet' error? 5781 */ 5782 static inline int disallowed_pkt_err(int posn) 5783 { 5784 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) && 5785 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET)); 5786 } 5787 5788 /* 5789 * Input value is a bit position of one of the SDMA engine disallowed 5790 * packet errors. Return which engine. Use of this must be guarded by 5791 * disallowed_pkt_err(). 5792 */ 5793 static inline int disallowed_pkt_engine(int posn) 5794 { 5795 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET); 5796 } 5797 5798 /* 5799 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot 5800 * be done. 5801 */ 5802 static int engine_to_vl(struct hfi1_devdata *dd, int engine) 5803 { 5804 struct sdma_vl_map *m; 5805 int vl; 5806 5807 /* range check */ 5808 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES) 5809 return -1; 5810 5811 rcu_read_lock(); 5812 m = rcu_dereference(dd->sdma_map); 5813 vl = m->engine_to_vl[engine]; 5814 rcu_read_unlock(); 5815 5816 return vl; 5817 } 5818 5819 /* 5820 * Translate the send context (sofware index) into a VL. Return -1 if the 5821 * translation cannot be done. 5822 */ 5823 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index) 5824 { 5825 struct send_context_info *sci; 5826 struct send_context *sc; 5827 int i; 5828 5829 sci = &dd->send_contexts[sw_index]; 5830 5831 /* there is no information for user (PSM) and ack contexts */ 5832 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15)) 5833 return -1; 5834 5835 sc = sci->sc; 5836 if (!sc) 5837 return -1; 5838 if (dd->vld[15].sc == sc) 5839 return 15; 5840 for (i = 0; i < num_vls; i++) 5841 if (dd->vld[i].sc == sc) 5842 return i; 5843 5844 return -1; 5845 } 5846 5847 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5848 { 5849 u64 reg_copy = reg, handled = 0; 5850 char buf[96]; 5851 int i = 0; 5852 5853 if (reg & ALL_TXE_EGRESS_FREEZE_ERR) 5854 start_freeze_handling(dd->pport, 0); 5855 else if (is_ax(dd) && 5856 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) && 5857 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) 5858 start_freeze_handling(dd->pport, 0); 5859 5860 while (reg_copy) { 5861 int posn = fls64(reg_copy); 5862 /* fls64() returns a 1-based offset, we want it zero based */ 5863 int shift = posn - 1; 5864 u64 mask = 1ULL << shift; 5865 5866 if (port_inactive_err(shift)) { 5867 count_port_inactive(dd); 5868 handled |= mask; 5869 } else if (disallowed_pkt_err(shift)) { 5870 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift)); 5871 5872 handle_send_egress_err_info(dd, vl); 5873 handled |= mask; 5874 } 5875 reg_copy &= ~mask; 5876 } 5877 5878 reg &= ~handled; 5879 5880 if (reg) 5881 dd_dev_info(dd, "Egress Error: %s\n", 5882 egress_err_status_string(buf, sizeof(buf), reg)); 5883 5884 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) { 5885 if (reg & (1ull << i)) 5886 incr_cntr64(&dd->send_egress_err_status_cnt[i]); 5887 } 5888 } 5889 5890 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5891 { 5892 char buf[96]; 5893 int i = 0; 5894 5895 dd_dev_info(dd, "Send Error: %s\n", 5896 send_err_status_string(buf, sizeof(buf), reg)); 5897 5898 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) { 5899 if (reg & (1ull << i)) 5900 incr_cntr64(&dd->send_err_status_cnt[i]); 5901 } 5902 } 5903 5904 /* 5905 * The maximum number of times the error clear down will loop before 5906 * blocking a repeating error. This value is arbitrary. 5907 */ 5908 #define MAX_CLEAR_COUNT 20 5909 5910 /* 5911 * Clear and handle an error register. All error interrupts are funneled 5912 * through here to have a central location to correctly handle single- 5913 * or multi-shot errors. 5914 * 5915 * For non per-context registers, call this routine with a context value 5916 * of 0 so the per-context offset is zero. 5917 * 5918 * If the handler loops too many times, assume that something is wrong 5919 * and can't be fixed, so mask the error bits. 5920 */ 5921 static void interrupt_clear_down(struct hfi1_devdata *dd, 5922 u32 context, 5923 const struct err_reg_info *eri) 5924 { 5925 u64 reg; 5926 u32 count; 5927 5928 /* read in a loop until no more errors are seen */ 5929 count = 0; 5930 while (1) { 5931 reg = read_kctxt_csr(dd, context, eri->status); 5932 if (reg == 0) 5933 break; 5934 write_kctxt_csr(dd, context, eri->clear, reg); 5935 if (likely(eri->handler)) 5936 eri->handler(dd, context, reg); 5937 count++; 5938 if (count > MAX_CLEAR_COUNT) { 5939 u64 mask; 5940 5941 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n", 5942 eri->desc, reg); 5943 /* 5944 * Read-modify-write so any other masked bits 5945 * remain masked. 5946 */ 5947 mask = read_kctxt_csr(dd, context, eri->mask); 5948 mask &= ~reg; 5949 write_kctxt_csr(dd, context, eri->mask, mask); 5950 break; 5951 } 5952 } 5953 } 5954 5955 /* 5956 * CCE block "misc" interrupt. Source is < 16. 5957 */ 5958 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source) 5959 { 5960 const struct err_reg_info *eri = &misc_errs[source]; 5961 5962 if (eri->handler) { 5963 interrupt_clear_down(dd, 0, eri); 5964 } else { 5965 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n", 5966 source); 5967 } 5968 } 5969 5970 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags) 5971 { 5972 return flag_string(buf, buf_len, flags, 5973 sc_err_status_flags, 5974 ARRAY_SIZE(sc_err_status_flags)); 5975 } 5976 5977 /* 5978 * Send context error interrupt. Source (hw_context) is < 160. 5979 * 5980 * All send context errors cause the send context to halt. The normal 5981 * clear-down mechanism cannot be used because we cannot clear the 5982 * error bits until several other long-running items are done first. 5983 * This is OK because with the context halted, nothing else is going 5984 * to happen on it anyway. 5985 */ 5986 static void is_sendctxt_err_int(struct hfi1_devdata *dd, 5987 unsigned int hw_context) 5988 { 5989 struct send_context_info *sci; 5990 struct send_context *sc; 5991 char flags[96]; 5992 u64 status; 5993 u32 sw_index; 5994 int i = 0; 5995 unsigned long irq_flags; 5996 5997 sw_index = dd->hw_to_sw[hw_context]; 5998 if (sw_index >= dd->num_send_contexts) { 5999 dd_dev_err(dd, 6000 "out of range sw index %u for send context %u\n", 6001 sw_index, hw_context); 6002 return; 6003 } 6004 sci = &dd->send_contexts[sw_index]; 6005 spin_lock_irqsave(&dd->sc_lock, irq_flags); 6006 sc = sci->sc; 6007 if (!sc) { 6008 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__, 6009 sw_index, hw_context); 6010 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 6011 return; 6012 } 6013 6014 /* tell the software that a halt has begun */ 6015 sc_stop(sc, SCF_HALTED); 6016 6017 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS); 6018 6019 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context, 6020 send_context_err_status_string(flags, sizeof(flags), 6021 status)); 6022 6023 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK) 6024 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index)); 6025 6026 /* 6027 * Automatically restart halted kernel contexts out of interrupt 6028 * context. User contexts must ask the driver to restart the context. 6029 */ 6030 if (sc->type != SC_USER) 6031 queue_work(dd->pport->hfi1_wq, &sc->halt_work); 6032 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 6033 6034 /* 6035 * Update the counters for the corresponding status bits. 6036 * Note that these particular counters are aggregated over all 6037 * 160 contexts. 6038 */ 6039 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) { 6040 if (status & (1ull << i)) 6041 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]); 6042 } 6043 } 6044 6045 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 6046 unsigned int source, u64 status) 6047 { 6048 struct sdma_engine *sde; 6049 int i = 0; 6050 6051 sde = &dd->per_sdma[source]; 6052 #ifdef CONFIG_SDMA_VERBOSITY 6053 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6054 slashstrip(__FILE__), __LINE__, __func__); 6055 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n", 6056 sde->this_idx, source, (unsigned long long)status); 6057 #endif 6058 sde->err_cnt++; 6059 sdma_engine_error(sde, status); 6060 6061 /* 6062 * Update the counters for the corresponding status bits. 6063 * Note that these particular counters are aggregated over 6064 * all 16 DMA engines. 6065 */ 6066 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) { 6067 if (status & (1ull << i)) 6068 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]); 6069 } 6070 } 6071 6072 /* 6073 * CCE block SDMA error interrupt. Source is < 16. 6074 */ 6075 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source) 6076 { 6077 #ifdef CONFIG_SDMA_VERBOSITY 6078 struct sdma_engine *sde = &dd->per_sdma[source]; 6079 6080 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6081 slashstrip(__FILE__), __LINE__, __func__); 6082 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx, 6083 source); 6084 sdma_dumpstate(sde); 6085 #endif 6086 interrupt_clear_down(dd, source, &sdma_eng_err); 6087 } 6088 6089 /* 6090 * CCE block "various" interrupt. Source is < 8. 6091 */ 6092 static void is_various_int(struct hfi1_devdata *dd, unsigned int source) 6093 { 6094 const struct err_reg_info *eri = &various_err[source]; 6095 6096 /* 6097 * TCritInt cannot go through interrupt_clear_down() 6098 * because it is not a second tier interrupt. The handler 6099 * should be called directly. 6100 */ 6101 if (source == TCRIT_INT_SOURCE) 6102 handle_temp_err(dd); 6103 else if (eri->handler) 6104 interrupt_clear_down(dd, 0, eri); 6105 else 6106 dd_dev_info(dd, 6107 "%s: Unimplemented/reserved interrupt %d\n", 6108 __func__, source); 6109 } 6110 6111 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg) 6112 { 6113 /* src_ctx is always zero */ 6114 struct hfi1_pportdata *ppd = dd->pport; 6115 unsigned long flags; 6116 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 6117 6118 if (reg & QSFP_HFI0_MODPRST_N) { 6119 if (!qsfp_mod_present(ppd)) { 6120 dd_dev_info(dd, "%s: QSFP module removed\n", 6121 __func__); 6122 6123 ppd->driver_link_ready = 0; 6124 /* 6125 * Cable removed, reset all our information about the 6126 * cache and cable capabilities 6127 */ 6128 6129 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6130 /* 6131 * We don't set cache_refresh_required here as we expect 6132 * an interrupt when a cable is inserted 6133 */ 6134 ppd->qsfp_info.cache_valid = 0; 6135 ppd->qsfp_info.reset_needed = 0; 6136 ppd->qsfp_info.limiting_active = 0; 6137 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6138 flags); 6139 /* Invert the ModPresent pin now to detect plug-in */ 6140 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6141 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6142 6143 if ((ppd->offline_disabled_reason > 6144 HFI1_ODR_MASK( 6145 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) || 6146 (ppd->offline_disabled_reason == 6147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))) 6148 ppd->offline_disabled_reason = 6149 HFI1_ODR_MASK( 6150 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED); 6151 6152 if (ppd->host_link_state == HLS_DN_POLL) { 6153 /* 6154 * The link is still in POLL. This means 6155 * that the normal link down processing 6156 * will not happen. We have to do it here 6157 * before turning the DC off. 6158 */ 6159 queue_work(ppd->link_wq, &ppd->link_down_work); 6160 } 6161 } else { 6162 dd_dev_info(dd, "%s: QSFP module inserted\n", 6163 __func__); 6164 6165 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6166 ppd->qsfp_info.cache_valid = 0; 6167 ppd->qsfp_info.cache_refresh_required = 1; 6168 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6169 flags); 6170 6171 /* 6172 * Stop inversion of ModPresent pin to detect 6173 * removal of the cable 6174 */ 6175 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N; 6176 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6177 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6178 6179 ppd->offline_disabled_reason = 6180 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 6181 } 6182 } 6183 6184 if (reg & QSFP_HFI0_INT_N) { 6185 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n", 6186 __func__); 6187 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6188 ppd->qsfp_info.check_interrupt_flags = 1; 6189 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags); 6190 } 6191 6192 /* Schedule the QSFP work only if there is a cable attached. */ 6193 if (qsfp_mod_present(ppd)) 6194 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work); 6195 } 6196 6197 static int request_host_lcb_access(struct hfi1_devdata *dd) 6198 { 6199 int ret; 6200 6201 ret = do_8051_command(dd, HCMD_MISC, 6202 (u64)HCMD_MISC_REQUEST_LCB_ACCESS << 6203 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6204 if (ret != HCMD_SUCCESS) { 6205 dd_dev_err(dd, "%s: command failed with error %d\n", 6206 __func__, ret); 6207 } 6208 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6209 } 6210 6211 static int request_8051_lcb_access(struct hfi1_devdata *dd) 6212 { 6213 int ret; 6214 6215 ret = do_8051_command(dd, HCMD_MISC, 6216 (u64)HCMD_MISC_GRANT_LCB_ACCESS << 6217 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6218 if (ret != HCMD_SUCCESS) { 6219 dd_dev_err(dd, "%s: command failed with error %d\n", 6220 __func__, ret); 6221 } 6222 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6223 } 6224 6225 /* 6226 * Set the LCB selector - allow host access. The DCC selector always 6227 * points to the host. 6228 */ 6229 static inline void set_host_lcb_access(struct hfi1_devdata *dd) 6230 { 6231 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6232 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK | 6233 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK); 6234 } 6235 6236 /* 6237 * Clear the LCB selector - allow 8051 access. The DCC selector always 6238 * points to the host. 6239 */ 6240 static inline void set_8051_lcb_access(struct hfi1_devdata *dd) 6241 { 6242 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6243 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK); 6244 } 6245 6246 /* 6247 * Acquire LCB access from the 8051. If the host already has access, 6248 * just increment a counter. Otherwise, inform the 8051 that the 6249 * host is taking access. 6250 * 6251 * Returns: 6252 * 0 on success 6253 * -EBUSY if the 8051 has control and cannot be disturbed 6254 * -errno if unable to acquire access from the 8051 6255 */ 6256 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6257 { 6258 struct hfi1_pportdata *ppd = dd->pport; 6259 int ret = 0; 6260 6261 /* 6262 * Use the host link state lock so the operation of this routine 6263 * { link state check, selector change, count increment } can occur 6264 * as a unit against a link state change. Otherwise there is a 6265 * race between the state change and the count increment. 6266 */ 6267 if (sleep_ok) { 6268 mutex_lock(&ppd->hls_lock); 6269 } else { 6270 while (!mutex_trylock(&ppd->hls_lock)) 6271 udelay(1); 6272 } 6273 6274 /* this access is valid only when the link is up */ 6275 if (ppd->host_link_state & HLS_DOWN) { 6276 dd_dev_info(dd, "%s: link state %s not up\n", 6277 __func__, link_state_name(ppd->host_link_state)); 6278 ret = -EBUSY; 6279 goto done; 6280 } 6281 6282 if (dd->lcb_access_count == 0) { 6283 ret = request_host_lcb_access(dd); 6284 if (ret) { 6285 dd_dev_err(dd, 6286 "%s: unable to acquire LCB access, err %d\n", 6287 __func__, ret); 6288 goto done; 6289 } 6290 set_host_lcb_access(dd); 6291 } 6292 dd->lcb_access_count++; 6293 done: 6294 mutex_unlock(&ppd->hls_lock); 6295 return ret; 6296 } 6297 6298 /* 6299 * Release LCB access by decrementing the use count. If the count is moving 6300 * from 1 to 0, inform 8051 that it has control back. 6301 * 6302 * Returns: 6303 * 0 on success 6304 * -errno if unable to release access to the 8051 6305 */ 6306 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6307 { 6308 int ret = 0; 6309 6310 /* 6311 * Use the host link state lock because the acquire needed it. 6312 * Here, we only need to keep { selector change, count decrement } 6313 * as a unit. 6314 */ 6315 if (sleep_ok) { 6316 mutex_lock(&dd->pport->hls_lock); 6317 } else { 6318 while (!mutex_trylock(&dd->pport->hls_lock)) 6319 udelay(1); 6320 } 6321 6322 if (dd->lcb_access_count == 0) { 6323 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n", 6324 __func__); 6325 goto done; 6326 } 6327 6328 if (dd->lcb_access_count == 1) { 6329 set_8051_lcb_access(dd); 6330 ret = request_8051_lcb_access(dd); 6331 if (ret) { 6332 dd_dev_err(dd, 6333 "%s: unable to release LCB access, err %d\n", 6334 __func__, ret); 6335 /* restore host access if the grant didn't work */ 6336 set_host_lcb_access(dd); 6337 goto done; 6338 } 6339 } 6340 dd->lcb_access_count--; 6341 done: 6342 mutex_unlock(&dd->pport->hls_lock); 6343 return ret; 6344 } 6345 6346 /* 6347 * Initialize LCB access variables and state. Called during driver load, 6348 * after most of the initialization is finished. 6349 * 6350 * The DC default is LCB access on for the host. The driver defaults to 6351 * leaving access to the 8051. Assign access now - this constrains the call 6352 * to this routine to be after all LCB set-up is done. In particular, after 6353 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts() 6354 */ 6355 static void init_lcb_access(struct hfi1_devdata *dd) 6356 { 6357 dd->lcb_access_count = 0; 6358 } 6359 6360 /* 6361 * Write a response back to a 8051 request. 6362 */ 6363 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data) 6364 { 6365 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 6366 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK | 6367 (u64)return_code << 6368 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT | 6369 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 6370 } 6371 6372 /* 6373 * Handle host requests from the 8051. 6374 */ 6375 static void handle_8051_request(struct hfi1_pportdata *ppd) 6376 { 6377 struct hfi1_devdata *dd = ppd->dd; 6378 u64 reg; 6379 u16 data = 0; 6380 u8 type; 6381 6382 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); 6383 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0) 6384 return; /* no request */ 6385 6386 /* zero out COMPLETED so the response is seen */ 6387 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); 6388 6389 /* extract request details */ 6390 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT) 6391 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK; 6392 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT) 6393 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK; 6394 6395 switch (type) { 6396 case HREQ_LOAD_CONFIG: 6397 case HREQ_SAVE_CONFIG: 6398 case HREQ_READ_CONFIG: 6399 case HREQ_SET_TX_EQ_ABS: 6400 case HREQ_SET_TX_EQ_REL: 6401 case HREQ_ENABLE: 6402 dd_dev_info(dd, "8051 request: request 0x%x not supported\n", 6403 type); 6404 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6405 break; 6406 case HREQ_LCB_RESET: 6407 /* Put the LCB, RX FPE and TX FPE into reset */ 6408 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); 6409 /* Make sure the write completed */ 6410 (void)read_csr(dd, DCC_CFG_RESET); 6411 /* Hold the reset long enough to take effect */ 6412 udelay(1); 6413 /* Take the LCB, RX FPE and TX FPE out of reset */ 6414 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6415 hreq_response(dd, HREQ_SUCCESS, 0); 6416 6417 break; 6418 case HREQ_CONFIG_DONE: 6419 hreq_response(dd, HREQ_SUCCESS, 0); 6420 break; 6421 6422 case HREQ_INTERFACE_TEST: 6423 hreq_response(dd, HREQ_SUCCESS, data); 6424 break; 6425 default: 6426 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type); 6427 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6428 break; 6429 } 6430 } 6431 6432 /* 6433 * Set up allocation unit vaulue. 6434 */ 6435 void set_up_vau(struct hfi1_devdata *dd, u8 vau) 6436 { 6437 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6438 6439 /* do not modify other values in the register */ 6440 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK; 6441 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT; 6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6443 } 6444 6445 /* 6446 * Set up initial VL15 credits of the remote. Assumes the rest of 6447 * the CM credit registers are zero from a previous global or credit reset. 6448 * Shared limit for VL15 will always be 0. 6449 */ 6450 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf) 6451 { 6452 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6453 6454 /* set initial values for total and shared credit limit */ 6455 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK | 6456 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK); 6457 6458 /* 6459 * Set total limit to be equal to VL15 credits. 6460 * Leave shared limit at 0. 6461 */ 6462 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 6463 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6464 6465 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf 6466 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); 6467 } 6468 6469 /* 6470 * Zero all credit details from the previous connection and 6471 * reset the CM manager's internal counters. 6472 */ 6473 void reset_link_credits(struct hfi1_devdata *dd) 6474 { 6475 int i; 6476 6477 /* remove all previous VL credit limits */ 6478 for (i = 0; i < TXE_NUM_DATA_VL; i++) 6479 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 6480 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 6481 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); 6482 /* reset the CM block */ 6483 pio_send_control(dd, PSC_CM_RESET); 6484 /* reset cached value */ 6485 dd->vl15buf_cached = 0; 6486 } 6487 6488 /* convert a vCU to a CU */ 6489 static u32 vcu_to_cu(u8 vcu) 6490 { 6491 return 1 << vcu; 6492 } 6493 6494 /* convert a CU to a vCU */ 6495 static u8 cu_to_vcu(u32 cu) 6496 { 6497 return ilog2(cu); 6498 } 6499 6500 /* convert a vAU to an AU */ 6501 static u32 vau_to_au(u8 vau) 6502 { 6503 return 8 * (1 << vau); 6504 } 6505 6506 static void set_linkup_defaults(struct hfi1_pportdata *ppd) 6507 { 6508 ppd->sm_trap_qp = 0x0; 6509 ppd->sa_qp = 0x1; 6510 } 6511 6512 /* 6513 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset. 6514 */ 6515 static void lcb_shutdown(struct hfi1_devdata *dd, int abort) 6516 { 6517 u64 reg; 6518 6519 /* clear lcb run: LCB_CFG_RUN.EN = 0 */ 6520 write_csr(dd, DC_LCB_CFG_RUN, 0); 6521 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */ 6522 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 6523 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT); 6524 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */ 6525 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); 6526 reg = read_csr(dd, DCC_CFG_RESET); 6527 write_csr(dd, DCC_CFG_RESET, reg | 6528 DCC_CFG_RESET_RESET_LCB | DCC_CFG_RESET_RESET_RX_FPE); 6529 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ 6530 if (!abort) { 6531 udelay(1); /* must hold for the longer of 16cclks or 20ns */ 6532 write_csr(dd, DCC_CFG_RESET, reg); 6533 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6534 } 6535 } 6536 6537 /* 6538 * This routine should be called after the link has been transitioned to 6539 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into 6540 * reset). 6541 * 6542 * The expectation is that the caller of this routine would have taken 6543 * care of properly transitioning the link into the correct state. 6544 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6545 * before calling this function. 6546 */ 6547 static void _dc_shutdown(struct hfi1_devdata *dd) 6548 { 6549 lockdep_assert_held(&dd->dc8051_lock); 6550 6551 if (dd->dc_shutdown) 6552 return; 6553 6554 dd->dc_shutdown = 1; 6555 /* Shutdown the LCB */ 6556 lcb_shutdown(dd, 1); 6557 /* 6558 * Going to OFFLINE would have causes the 8051 to put the 6559 * SerDes into reset already. Just need to shut down the 8051, 6560 * itself. 6561 */ 6562 write_csr(dd, DC_DC8051_CFG_RST, 0x1); 6563 } 6564 6565 static void dc_shutdown(struct hfi1_devdata *dd) 6566 { 6567 mutex_lock(&dd->dc8051_lock); 6568 _dc_shutdown(dd); 6569 mutex_unlock(&dd->dc8051_lock); 6570 } 6571 6572 /* 6573 * Calling this after the DC has been brought out of reset should not 6574 * do any damage. 6575 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6576 * before calling this function. 6577 */ 6578 static void _dc_start(struct hfi1_devdata *dd) 6579 { 6580 lockdep_assert_held(&dd->dc8051_lock); 6581 6582 if (!dd->dc_shutdown) 6583 return; 6584 6585 /* Take the 8051 out of reset */ 6586 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 6587 /* Wait until 8051 is ready */ 6588 if (wait_fm_ready(dd, TIMEOUT_8051_START)) 6589 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n", 6590 __func__); 6591 6592 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */ 6593 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6594 /* lcb_shutdown() with abort=1 does not restore these */ 6595 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6596 dd->dc_shutdown = 0; 6597 } 6598 6599 static void dc_start(struct hfi1_devdata *dd) 6600 { 6601 mutex_lock(&dd->dc8051_lock); 6602 _dc_start(dd); 6603 mutex_unlock(&dd->dc8051_lock); 6604 } 6605 6606 /* 6607 * These LCB adjustments are for the Aurora SerDes core in the FPGA. 6608 */ 6609 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd) 6610 { 6611 u64 rx_radr, tx_radr; 6612 u32 version; 6613 6614 if (dd->icode != ICODE_FPGA_EMULATION) 6615 return; 6616 6617 /* 6618 * These LCB defaults on emulator _s are good, nothing to do here: 6619 * LCB_CFG_TX_FIFOS_RADR 6620 * LCB_CFG_RX_FIFOS_RADR 6621 * LCB_CFG_LN_DCLK 6622 * LCB_CFG_IGNORE_LOST_RCLK 6623 */ 6624 if (is_emulator_s(dd)) 6625 return; 6626 /* else this is _p */ 6627 6628 version = emulator_rev(dd); 6629 if (!is_ax(dd)) 6630 version = 0x2d; /* all B0 use 0x2d or higher settings */ 6631 6632 if (version <= 0x12) { 6633 /* release 0x12 and below */ 6634 6635 /* 6636 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9 6637 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9 6638 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa 6639 */ 6640 rx_radr = 6641 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6642 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6643 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6644 /* 6645 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default) 6646 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6 6647 */ 6648 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6649 } else if (version <= 0x18) { 6650 /* release 0x13 up to 0x18 */ 6651 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6652 rx_radr = 6653 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6654 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6655 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6656 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6657 } else if (version == 0x19) { 6658 /* release 0x19 */ 6659 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */ 6660 rx_radr = 6661 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6662 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6663 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6664 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6665 } else if (version == 0x1a) { 6666 /* release 0x1a */ 6667 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6668 rx_radr = 6669 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6670 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6671 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6672 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6673 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); 6674 } else { 6675 /* release 0x1b and higher */ 6676 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */ 6677 rx_radr = 6678 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6679 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6680 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6681 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6682 } 6683 6684 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); 6685 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */ 6686 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 6687 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 6688 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); 6689 } 6690 6691 /* 6692 * Handle a SMA idle message 6693 * 6694 * This is a work-queue function outside of the interrupt. 6695 */ 6696 void handle_sma_message(struct work_struct *work) 6697 { 6698 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6699 sma_message_work); 6700 struct hfi1_devdata *dd = ppd->dd; 6701 u64 msg; 6702 int ret; 6703 6704 /* 6705 * msg is bytes 1-4 of the 40-bit idle message - the command code 6706 * is stripped off 6707 */ 6708 ret = read_idle_sma(dd, &msg); 6709 if (ret) 6710 return; 6711 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg); 6712 /* 6713 * React to the SMA message. Byte[1] (0 for us) is the command. 6714 */ 6715 switch (msg & 0xff) { 6716 case SMA_IDLE_ARM: 6717 /* 6718 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6719 * State Transitions 6720 * 6721 * Only expected in INIT or ARMED, discard otherwise. 6722 */ 6723 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED)) 6724 ppd->neighbor_normal = 1; 6725 break; 6726 case SMA_IDLE_ACTIVE: 6727 /* 6728 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6729 * State Transitions 6730 * 6731 * Can activate the node. Discard otherwise. 6732 */ 6733 if (ppd->host_link_state == HLS_UP_ARMED && 6734 ppd->is_active_optimize_enabled) { 6735 ppd->neighbor_normal = 1; 6736 ret = set_link_state(ppd, HLS_UP_ACTIVE); 6737 if (ret) 6738 dd_dev_err( 6739 dd, 6740 "%s: received Active SMA idle message, couldn't set link to Active\n", 6741 __func__); 6742 } 6743 break; 6744 default: 6745 dd_dev_err(dd, 6746 "%s: received unexpected SMA idle message 0x%llx\n", 6747 __func__, msg); 6748 break; 6749 } 6750 } 6751 6752 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear) 6753 { 6754 u64 rcvctrl; 6755 unsigned long flags; 6756 6757 spin_lock_irqsave(&dd->rcvctrl_lock, flags); 6758 rcvctrl = read_csr(dd, RCV_CTRL); 6759 rcvctrl |= add; 6760 rcvctrl &= ~clear; 6761 write_csr(dd, RCV_CTRL, rcvctrl); 6762 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags); 6763 } 6764 6765 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add) 6766 { 6767 adjust_rcvctrl(dd, add, 0); 6768 } 6769 6770 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear) 6771 { 6772 adjust_rcvctrl(dd, 0, clear); 6773 } 6774 6775 /* 6776 * Called from all interrupt handlers to start handling an SPC freeze. 6777 */ 6778 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags) 6779 { 6780 struct hfi1_devdata *dd = ppd->dd; 6781 struct send_context *sc; 6782 int i; 6783 int sc_flags; 6784 6785 if (flags & FREEZE_SELF) 6786 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6787 6788 /* enter frozen mode */ 6789 dd->flags |= HFI1_FROZEN; 6790 6791 /* notify all SDMA engines that they are going into a freeze */ 6792 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN)); 6793 6794 sc_flags = SCF_FROZEN | SCF_HALTED | (flags & FREEZE_LINK_DOWN ? 6795 SCF_LINK_DOWN : 0); 6796 /* do halt pre-handling on all enabled send contexts */ 6797 for (i = 0; i < dd->num_send_contexts; i++) { 6798 sc = dd->send_contexts[i].sc; 6799 if (sc && (sc->flags & SCF_ENABLED)) 6800 sc_stop(sc, sc_flags); 6801 } 6802 6803 /* Send context are frozen. Notify user space */ 6804 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT); 6805 6806 if (flags & FREEZE_ABORT) { 6807 dd_dev_err(dd, 6808 "Aborted freeze recovery. Please REBOOT system\n"); 6809 return; 6810 } 6811 /* queue non-interrupt handler */ 6812 queue_work(ppd->hfi1_wq, &ppd->freeze_work); 6813 } 6814 6815 /* 6816 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen, 6817 * depending on the "freeze" parameter. 6818 * 6819 * No need to return an error if it times out, our only option 6820 * is to proceed anyway. 6821 */ 6822 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze) 6823 { 6824 unsigned long timeout; 6825 u64 reg; 6826 6827 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT); 6828 while (1) { 6829 reg = read_csr(dd, CCE_STATUS); 6830 if (freeze) { 6831 /* waiting until all indicators are set */ 6832 if ((reg & ALL_FROZE) == ALL_FROZE) 6833 return; /* all done */ 6834 } else { 6835 /* waiting until all indicators are clear */ 6836 if ((reg & ALL_FROZE) == 0) 6837 return; /* all done */ 6838 } 6839 6840 if (time_after(jiffies, timeout)) { 6841 dd_dev_err(dd, 6842 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing", 6843 freeze ? "" : "un", reg & ALL_FROZE, 6844 freeze ? ALL_FROZE : 0ull); 6845 return; 6846 } 6847 usleep_range(80, 120); 6848 } 6849 } 6850 6851 /* 6852 * Do all freeze handling for the RXE block. 6853 */ 6854 static void rxe_freeze(struct hfi1_devdata *dd) 6855 { 6856 int i; 6857 struct hfi1_ctxtdata *rcd; 6858 6859 /* disable port */ 6860 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6861 6862 /* disable all receive contexts */ 6863 for (i = 0; i < dd->num_rcv_contexts; i++) { 6864 rcd = hfi1_rcd_get_by_index(dd, i); 6865 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd); 6866 hfi1_rcd_put(rcd); 6867 } 6868 } 6869 6870 /* 6871 * Unfreeze handling for the RXE block - kernel contexts only. 6872 * This will also enable the port. User contexts will do unfreeze 6873 * handling on a per-context basis as they call into the driver. 6874 * 6875 */ 6876 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd) 6877 { 6878 u32 rcvmask; 6879 u16 i; 6880 struct hfi1_ctxtdata *rcd; 6881 6882 /* enable all kernel contexts */ 6883 for (i = 0; i < dd->num_rcv_contexts; i++) { 6884 rcd = hfi1_rcd_get_by_index(dd, i); 6885 6886 /* Ensure all non-user contexts(including vnic) are enabled */ 6887 if (!rcd || 6888 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) { 6889 hfi1_rcd_put(rcd); 6890 continue; 6891 } 6892 rcvmask = HFI1_RCVCTRL_CTXT_ENB; 6893 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */ 6894 rcvmask |= hfi1_rcvhdrtail_kvaddr(rcd) ? 6895 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 6896 hfi1_rcvctrl(dd, rcvmask, rcd); 6897 hfi1_rcd_put(rcd); 6898 } 6899 6900 /* enable port */ 6901 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6902 } 6903 6904 /* 6905 * Non-interrupt SPC freeze handling. 6906 * 6907 * This is a work-queue function outside of the triggering interrupt. 6908 */ 6909 void handle_freeze(struct work_struct *work) 6910 { 6911 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6912 freeze_work); 6913 struct hfi1_devdata *dd = ppd->dd; 6914 6915 /* wait for freeze indicators on all affected blocks */ 6916 wait_for_freeze_status(dd, 1); 6917 6918 /* SPC is now frozen */ 6919 6920 /* do send PIO freeze steps */ 6921 pio_freeze(dd); 6922 6923 /* do send DMA freeze steps */ 6924 sdma_freeze(dd); 6925 6926 /* do send egress freeze steps - nothing to do */ 6927 6928 /* do receive freeze steps */ 6929 rxe_freeze(dd); 6930 6931 /* 6932 * Unfreeze the hardware - clear the freeze, wait for each 6933 * block's frozen bit to clear, then clear the frozen flag. 6934 */ 6935 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6936 wait_for_freeze_status(dd, 0); 6937 6938 if (is_ax(dd)) { 6939 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6940 wait_for_freeze_status(dd, 1); 6941 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6942 wait_for_freeze_status(dd, 0); 6943 } 6944 6945 /* do send PIO unfreeze steps for kernel contexts */ 6946 pio_kernel_unfreeze(dd); 6947 6948 /* do send DMA unfreeze steps */ 6949 sdma_unfreeze(dd); 6950 6951 /* do send egress unfreeze steps - nothing to do */ 6952 6953 /* do receive unfreeze steps for kernel contexts */ 6954 rxe_kernel_unfreeze(dd); 6955 6956 /* 6957 * The unfreeze procedure touches global device registers when 6958 * it disables and re-enables RXE. Mark the device unfrozen 6959 * after all that is done so other parts of the driver waiting 6960 * for the device to unfreeze don't do things out of order. 6961 * 6962 * The above implies that the meaning of HFI1_FROZEN flag is 6963 * "Device has gone into freeze mode and freeze mode handling 6964 * is still in progress." 6965 * 6966 * The flag will be removed when freeze mode processing has 6967 * completed. 6968 */ 6969 dd->flags &= ~HFI1_FROZEN; 6970 wake_up(&dd->event_queue); 6971 6972 /* no longer frozen */ 6973 } 6974 6975 /** 6976 * update_xmit_counters - update PortXmitWait/PortVlXmitWait 6977 * counters. 6978 * @ppd: info of physical Hfi port 6979 * @link_width: new link width after link up or downgrade 6980 * 6981 * Update the PortXmitWait and PortVlXmitWait counters after 6982 * a link up or downgrade event to reflect a link width change. 6983 */ 6984 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width) 6985 { 6986 int i; 6987 u16 tx_width; 6988 u16 link_speed; 6989 6990 tx_width = tx_link_width(link_width); 6991 link_speed = get_link_speed(ppd->link_speed_active); 6992 6993 /* 6994 * There are C_VL_COUNT number of PortVLXmitWait counters. 6995 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter. 6996 */ 6997 for (i = 0; i < C_VL_COUNT + 1; i++) 6998 get_xmit_wait_counters(ppd, tx_width, link_speed, i); 6999 } 7000 7001 /* 7002 * Handle a link up interrupt from the 8051. 7003 * 7004 * This is a work-queue function outside of the interrupt. 7005 */ 7006 void handle_link_up(struct work_struct *work) 7007 { 7008 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7009 link_up_work); 7010 struct hfi1_devdata *dd = ppd->dd; 7011 7012 set_link_state(ppd, HLS_UP_INIT); 7013 7014 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */ 7015 read_ltp_rtt(dd); 7016 /* 7017 * OPA specifies that certain counters are cleared on a transition 7018 * to link up, so do that. 7019 */ 7020 clear_linkup_counters(dd); 7021 /* 7022 * And (re)set link up default values. 7023 */ 7024 set_linkup_defaults(ppd); 7025 7026 /* 7027 * Set VL15 credits. Use cached value from verify cap interrupt. 7028 * In case of quick linkup or simulator, vl15 value will be set by 7029 * handle_linkup_change. VerifyCap interrupt handler will not be 7030 * called in those scenarios. 7031 */ 7032 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) 7033 set_up_vl15(dd, dd->vl15buf_cached); 7034 7035 /* enforce link speed enabled */ 7036 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) { 7037 /* oops - current speed is not enabled, bounce */ 7038 dd_dev_err(dd, 7039 "Link speed active 0x%x is outside enabled 0x%x, downing link\n", 7040 ppd->link_speed_active, ppd->link_speed_enabled); 7041 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0, 7042 OPA_LINKDOWN_REASON_SPEED_POLICY); 7043 set_link_state(ppd, HLS_DN_OFFLINE); 7044 start_link(ppd); 7045 } 7046 } 7047 7048 /* 7049 * Several pieces of LNI information were cached for SMA in ppd. 7050 * Reset these on link down 7051 */ 7052 static void reset_neighbor_info(struct hfi1_pportdata *ppd) 7053 { 7054 ppd->neighbor_guid = 0; 7055 ppd->neighbor_port_number = 0; 7056 ppd->neighbor_type = 0; 7057 ppd->neighbor_fm_security = 0; 7058 } 7059 7060 static const char * const link_down_reason_strs[] = { 7061 [OPA_LINKDOWN_REASON_NONE] = "None", 7062 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0", 7063 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length", 7064 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long", 7065 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short", 7066 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID", 7067 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID", 7068 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2", 7069 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC", 7070 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8", 7071 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail", 7072 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10", 7073 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error", 7074 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15", 7075 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker", 7076 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14", 7077 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15", 7078 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance", 7079 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance", 7080 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance", 7081 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack", 7082 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker", 7083 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt", 7084 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit", 7085 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit", 7086 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24", 7087 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25", 7088 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26", 7089 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27", 7090 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28", 7091 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29", 7092 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30", 7093 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] = 7094 "Excessive buffer overrun", 7095 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown", 7096 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot", 7097 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown", 7098 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce", 7099 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy", 7100 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy", 7101 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected", 7102 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] = 7103 "Local media not installed", 7104 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed", 7105 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config", 7106 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] = 7107 "End to end not installed", 7108 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy", 7109 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy", 7110 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy", 7111 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management", 7112 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled", 7113 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient" 7114 }; 7115 7116 /* return the neighbor link down reason string */ 7117 static const char *link_down_reason_str(u8 reason) 7118 { 7119 const char *str = NULL; 7120 7121 if (reason < ARRAY_SIZE(link_down_reason_strs)) 7122 str = link_down_reason_strs[reason]; 7123 if (!str) 7124 str = "(invalid)"; 7125 7126 return str; 7127 } 7128 7129 /* 7130 * Handle a link down interrupt from the 8051. 7131 * 7132 * This is a work-queue function outside of the interrupt. 7133 */ 7134 void handle_link_down(struct work_struct *work) 7135 { 7136 u8 lcl_reason, neigh_reason = 0; 7137 u8 link_down_reason; 7138 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7139 link_down_work); 7140 int was_up; 7141 static const char ldr_str[] = "Link down reason: "; 7142 7143 if ((ppd->host_link_state & 7144 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) && 7145 ppd->port_type == PORT_TYPE_FIXED) 7146 ppd->offline_disabled_reason = 7147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED); 7148 7149 /* Go offline first, then deal with reading/writing through 8051 */ 7150 was_up = !!(ppd->host_link_state & HLS_UP); 7151 set_link_state(ppd, HLS_DN_OFFLINE); 7152 xchg(&ppd->is_link_down_queued, 0); 7153 7154 if (was_up) { 7155 lcl_reason = 0; 7156 /* link down reason is only valid if the link was up */ 7157 read_link_down_reason(ppd->dd, &link_down_reason); 7158 switch (link_down_reason) { 7159 case LDR_LINK_TRANSFER_ACTIVE_LOW: 7160 /* the link went down, no idle message reason */ 7161 dd_dev_info(ppd->dd, "%sUnexpected link down\n", 7162 ldr_str); 7163 break; 7164 case LDR_RECEIVED_LINKDOWN_IDLE_MSG: 7165 /* 7166 * The neighbor reason is only valid if an idle message 7167 * was received for it. 7168 */ 7169 read_planned_down_reason_code(ppd->dd, &neigh_reason); 7170 dd_dev_info(ppd->dd, 7171 "%sNeighbor link down message %d, %s\n", 7172 ldr_str, neigh_reason, 7173 link_down_reason_str(neigh_reason)); 7174 break; 7175 case LDR_RECEIVED_HOST_OFFLINE_REQ: 7176 dd_dev_info(ppd->dd, 7177 "%sHost requested link to go offline\n", 7178 ldr_str); 7179 break; 7180 default: 7181 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n", 7182 ldr_str, link_down_reason); 7183 break; 7184 } 7185 7186 /* 7187 * If no reason, assume peer-initiated but missed 7188 * LinkGoingDown idle flits. 7189 */ 7190 if (neigh_reason == 0) 7191 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN; 7192 } else { 7193 /* went down while polling or going up */ 7194 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT; 7195 } 7196 7197 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0); 7198 7199 /* inform the SMA when the link transitions from up to down */ 7200 if (was_up && ppd->local_link_down_reason.sma == 0 && 7201 ppd->neigh_link_down_reason.sma == 0) { 7202 ppd->local_link_down_reason.sma = 7203 ppd->local_link_down_reason.latest; 7204 ppd->neigh_link_down_reason.sma = 7205 ppd->neigh_link_down_reason.latest; 7206 } 7207 7208 reset_neighbor_info(ppd); 7209 7210 /* disable the port */ 7211 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 7212 7213 /* 7214 * If there is no cable attached, turn the DC off. Otherwise, 7215 * start the link bring up. 7216 */ 7217 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) 7218 dc_shutdown(ppd->dd); 7219 else 7220 start_link(ppd); 7221 } 7222 7223 void handle_link_bounce(struct work_struct *work) 7224 { 7225 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7226 link_bounce_work); 7227 7228 /* 7229 * Only do something if the link is currently up. 7230 */ 7231 if (ppd->host_link_state & HLS_UP) { 7232 set_link_state(ppd, HLS_DN_OFFLINE); 7233 start_link(ppd); 7234 } else { 7235 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n", 7236 __func__, link_state_name(ppd->host_link_state)); 7237 } 7238 } 7239 7240 /* 7241 * Mask conversion: Capability exchange to Port LTP. The capability 7242 * exchange has an implicit 16b CRC that is mandatory. 7243 */ 7244 static int cap_to_port_ltp(int cap) 7245 { 7246 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */ 7247 7248 if (cap & CAP_CRC_14B) 7249 port_ltp |= PORT_LTP_CRC_MODE_14; 7250 if (cap & CAP_CRC_48B) 7251 port_ltp |= PORT_LTP_CRC_MODE_48; 7252 if (cap & CAP_CRC_12B_16B_PER_LANE) 7253 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE; 7254 7255 return port_ltp; 7256 } 7257 7258 /* 7259 * Convert an OPA Port LTP mask to capability mask 7260 */ 7261 int port_ltp_to_cap(int port_ltp) 7262 { 7263 int cap_mask = 0; 7264 7265 if (port_ltp & PORT_LTP_CRC_MODE_14) 7266 cap_mask |= CAP_CRC_14B; 7267 if (port_ltp & PORT_LTP_CRC_MODE_48) 7268 cap_mask |= CAP_CRC_48B; 7269 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE) 7270 cap_mask |= CAP_CRC_12B_16B_PER_LANE; 7271 7272 return cap_mask; 7273 } 7274 7275 /* 7276 * Convert a single DC LCB CRC mode to an OPA Port LTP mask. 7277 */ 7278 static int lcb_to_port_ltp(int lcb_crc) 7279 { 7280 int port_ltp = 0; 7281 7282 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE) 7283 port_ltp = PORT_LTP_CRC_MODE_PER_LANE; 7284 else if (lcb_crc == LCB_CRC_48B) 7285 port_ltp = PORT_LTP_CRC_MODE_48; 7286 else if (lcb_crc == LCB_CRC_14B) 7287 port_ltp = PORT_LTP_CRC_MODE_14; 7288 else 7289 port_ltp = PORT_LTP_CRC_MODE_16; 7290 7291 return port_ltp; 7292 } 7293 7294 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd) 7295 { 7296 if (ppd->pkeys[2] != 0) { 7297 ppd->pkeys[2] = 0; 7298 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0); 7299 hfi1_event_pkey_change(ppd->dd, ppd->port); 7300 } 7301 } 7302 7303 /* 7304 * Convert the given link width to the OPA link width bitmask. 7305 */ 7306 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width) 7307 { 7308 switch (width) { 7309 case 0: 7310 /* 7311 * Simulator and quick linkup do not set the width. 7312 * Just set it to 4x without complaint. 7313 */ 7314 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup) 7315 return OPA_LINK_WIDTH_4X; 7316 return 0; /* no lanes up */ 7317 case 1: return OPA_LINK_WIDTH_1X; 7318 case 2: return OPA_LINK_WIDTH_2X; 7319 case 3: return OPA_LINK_WIDTH_3X; 7320 default: 7321 dd_dev_info(dd, "%s: invalid width %d, using 4\n", 7322 __func__, width); 7323 /* fall through */ 7324 case 4: return OPA_LINK_WIDTH_4X; 7325 } 7326 } 7327 7328 /* 7329 * Do a population count on the bottom nibble. 7330 */ 7331 static const u8 bit_counts[16] = { 7332 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 7333 }; 7334 7335 static inline u8 nibble_to_count(u8 nibble) 7336 { 7337 return bit_counts[nibble & 0xf]; 7338 } 7339 7340 /* 7341 * Read the active lane information from the 8051 registers and return 7342 * their widths. 7343 * 7344 * Active lane information is found in these 8051 registers: 7345 * enable_lane_tx 7346 * enable_lane_rx 7347 */ 7348 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width, 7349 u16 *rx_width) 7350 { 7351 u16 tx, rx; 7352 u8 enable_lane_rx; 7353 u8 enable_lane_tx; 7354 u8 tx_polarity_inversion; 7355 u8 rx_polarity_inversion; 7356 u8 max_rate; 7357 7358 /* read the active lanes */ 7359 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 7360 &rx_polarity_inversion, &max_rate); 7361 read_local_lni(dd, &enable_lane_rx); 7362 7363 /* convert to counts */ 7364 tx = nibble_to_count(enable_lane_tx); 7365 rx = nibble_to_count(enable_lane_rx); 7366 7367 /* 7368 * Set link_speed_active here, overriding what was set in 7369 * handle_verify_cap(). The ASIC 8051 firmware does not correctly 7370 * set the max_rate field in handle_verify_cap until v0.19. 7371 */ 7372 if ((dd->icode == ICODE_RTL_SILICON) && 7373 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) { 7374 /* max_rate: 0 = 12.5G, 1 = 25G */ 7375 switch (max_rate) { 7376 case 0: 7377 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G; 7378 break; 7379 default: 7380 dd_dev_err(dd, 7381 "%s: unexpected max rate %d, using 25Gb\n", 7382 __func__, (int)max_rate); 7383 /* fall through */ 7384 case 1: 7385 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G; 7386 break; 7387 } 7388 } 7389 7390 dd_dev_info(dd, 7391 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n", 7392 enable_lane_tx, tx, enable_lane_rx, rx); 7393 *tx_width = link_width_to_bits(dd, tx); 7394 *rx_width = link_width_to_bits(dd, rx); 7395 } 7396 7397 /* 7398 * Read verify_cap_local_fm_link_width[1] to obtain the link widths. 7399 * Valid after the end of VerifyCap and during LinkUp. Does not change 7400 * after link up. I.e. look elsewhere for downgrade information. 7401 * 7402 * Bits are: 7403 * + bits [7:4] contain the number of active transmitters 7404 * + bits [3:0] contain the number of active receivers 7405 * These are numbers 1 through 4 and can be different values if the 7406 * link is asymmetric. 7407 * 7408 * verify_cap_local_fm_link_width[0] retains its original value. 7409 */ 7410 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width, 7411 u16 *rx_width) 7412 { 7413 u16 widths, tx, rx; 7414 u8 misc_bits, local_flags; 7415 u16 active_tx, active_rx; 7416 7417 read_vc_local_link_mode(dd, &misc_bits, &local_flags, &widths); 7418 tx = widths >> 12; 7419 rx = (widths >> 8) & 0xf; 7420 7421 *tx_width = link_width_to_bits(dd, tx); 7422 *rx_width = link_width_to_bits(dd, rx); 7423 7424 /* print the active widths */ 7425 get_link_widths(dd, &active_tx, &active_rx); 7426 } 7427 7428 /* 7429 * Set ppd->link_width_active and ppd->link_width_downgrade_active using 7430 * hardware information when the link first comes up. 7431 * 7432 * The link width is not available until after VerifyCap.AllFramesReceived 7433 * (the trigger for handle_verify_cap), so this is outside that routine 7434 * and should be called when the 8051 signals linkup. 7435 */ 7436 void get_linkup_link_widths(struct hfi1_pportdata *ppd) 7437 { 7438 u16 tx_width, rx_width; 7439 7440 /* get end-of-LNI link widths */ 7441 get_linkup_widths(ppd->dd, &tx_width, &rx_width); 7442 7443 /* use tx_width as the link is supposed to be symmetric on link up */ 7444 ppd->link_width_active = tx_width; 7445 /* link width downgrade active (LWD.A) starts out matching LW.A */ 7446 ppd->link_width_downgrade_tx_active = ppd->link_width_active; 7447 ppd->link_width_downgrade_rx_active = ppd->link_width_active; 7448 /* per OPA spec, on link up LWD.E resets to LWD.S */ 7449 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported; 7450 /* cache the active egress rate (units {10^6 bits/sec]) */ 7451 ppd->current_egress_rate = active_egress_rate(ppd); 7452 } 7453 7454 /* 7455 * Handle a verify capabilities interrupt from the 8051. 7456 * 7457 * This is a work-queue function outside of the interrupt. 7458 */ 7459 void handle_verify_cap(struct work_struct *work) 7460 { 7461 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7462 link_vc_work); 7463 struct hfi1_devdata *dd = ppd->dd; 7464 u64 reg; 7465 u8 power_management; 7466 u8 continuous; 7467 u8 vcu; 7468 u8 vau; 7469 u8 z; 7470 u16 vl15buf; 7471 u16 link_widths; 7472 u16 crc_mask; 7473 u16 crc_val; 7474 u16 device_id; 7475 u16 active_tx, active_rx; 7476 u8 partner_supported_crc; 7477 u8 remote_tx_rate; 7478 u8 device_rev; 7479 7480 set_link_state(ppd, HLS_VERIFY_CAP); 7481 7482 lcb_shutdown(dd, 0); 7483 adjust_lcb_for_fpga_serdes(dd); 7484 7485 read_vc_remote_phy(dd, &power_management, &continuous); 7486 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf, 7487 &partner_supported_crc); 7488 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths); 7489 read_remote_device_id(dd, &device_id, &device_rev); 7490 7491 /* print the active widths */ 7492 get_link_widths(dd, &active_tx, &active_rx); 7493 dd_dev_info(dd, 7494 "Peer PHY: power management 0x%x, continuous updates 0x%x\n", 7495 (int)power_management, (int)continuous); 7496 dd_dev_info(dd, 7497 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n", 7498 (int)vau, (int)z, (int)vcu, (int)vl15buf, 7499 (int)partner_supported_crc); 7500 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n", 7501 (u32)remote_tx_rate, (u32)link_widths); 7502 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n", 7503 (u32)device_id, (u32)device_rev); 7504 /* 7505 * The peer vAU value just read is the peer receiver value. HFI does 7506 * not support a transmit vAU of 0 (AU == 8). We advertised that 7507 * with Z=1 in the fabric capabilities sent to the peer. The peer 7508 * will see our Z=1, and, if it advertised a vAU of 0, will move its 7509 * receive to vAU of 1 (AU == 16). Do the same here. We do not care 7510 * about the peer Z value - our sent vAU is 3 (hardwired) and is not 7511 * subject to the Z value exception. 7512 */ 7513 if (vau == 0) 7514 vau = 1; 7515 set_up_vau(dd, vau); 7516 7517 /* 7518 * Set VL15 credits to 0 in global credit register. Cache remote VL15 7519 * credits value and wait for link-up interrupt ot set it. 7520 */ 7521 set_up_vl15(dd, 0); 7522 dd->vl15buf_cached = vl15buf; 7523 7524 /* set up the LCB CRC mode */ 7525 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc; 7526 7527 /* order is important: use the lowest bit in common */ 7528 if (crc_mask & CAP_CRC_14B) 7529 crc_val = LCB_CRC_14B; 7530 else if (crc_mask & CAP_CRC_48B) 7531 crc_val = LCB_CRC_48B; 7532 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE) 7533 crc_val = LCB_CRC_12B_16B_PER_LANE; 7534 else 7535 crc_val = LCB_CRC_16B; 7536 7537 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val); 7538 write_csr(dd, DC_LCB_CFG_CRC_MODE, 7539 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT); 7540 7541 /* set (14b only) or clear sideband credit */ 7542 reg = read_csr(dd, SEND_CM_CTRL); 7543 if (crc_val == LCB_CRC_14B && crc_14b_sideband) { 7544 write_csr(dd, SEND_CM_CTRL, 7545 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7546 } else { 7547 write_csr(dd, SEND_CM_CTRL, 7548 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7549 } 7550 7551 ppd->link_speed_active = 0; /* invalid value */ 7552 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 7553 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */ 7554 switch (remote_tx_rate) { 7555 case 0: 7556 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7557 break; 7558 case 1: 7559 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7560 break; 7561 } 7562 } else { 7563 /* actual rate is highest bit of the ANDed rates */ 7564 u8 rate = remote_tx_rate & ppd->local_tx_rate; 7565 7566 if (rate & 2) 7567 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7568 else if (rate & 1) 7569 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7570 } 7571 if (ppd->link_speed_active == 0) { 7572 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n", 7573 __func__, (int)remote_tx_rate); 7574 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7575 } 7576 7577 /* 7578 * Cache the values of the supported, enabled, and active 7579 * LTP CRC modes to return in 'portinfo' queries. But the bit 7580 * flags that are returned in the portinfo query differ from 7581 * what's in the link_crc_mask, crc_sizes, and crc_val 7582 * variables. Convert these here. 7583 */ 7584 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 7585 /* supported crc modes */ 7586 ppd->port_ltp_crc_mode |= 7587 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4; 7588 /* enabled crc modes */ 7589 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val); 7590 /* active crc mode */ 7591 7592 /* set up the remote credit return table */ 7593 assign_remote_cm_au_table(dd, vcu); 7594 7595 /* 7596 * The LCB is reset on entry to handle_verify_cap(), so this must 7597 * be applied on every link up. 7598 * 7599 * Adjust LCB error kill enable to kill the link if 7600 * these RBUF errors are seen: 7601 * REPLAY_BUF_MBE_SMASK 7602 * FLIT_INPUT_BUF_MBE_SMASK 7603 */ 7604 if (is_ax(dd)) { /* fixed in B0 */ 7605 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); 7606 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 7607 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK; 7608 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); 7609 } 7610 7611 /* pull LCB fifos out of reset - all fifo clocks must be stable */ 7612 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 7613 7614 /* give 8051 access to the LCB CSRs */ 7615 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 7616 set_8051_lcb_access(dd); 7617 7618 /* tell the 8051 to go to LinkUp */ 7619 set_link_state(ppd, HLS_GOING_UP); 7620 } 7621 7622 /** 7623 * apply_link_downgrade_policy - Apply the link width downgrade enabled 7624 * policy against the current active link widths. 7625 * @ppd: info of physical Hfi port 7626 * @refresh_widths: True indicates link downgrade event 7627 * @return: True indicates a successful link downgrade. False indicates 7628 * link downgrade event failed and the link will bounce back to 7629 * default link width. 7630 * 7631 * Called when the enabled policy changes or the active link widths 7632 * change. 7633 * Refresh_widths indicates that a link downgrade occurred. The 7634 * link_downgraded variable is set by refresh_widths and 7635 * determines the success/failure of the policy application. 7636 */ 7637 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, 7638 bool refresh_widths) 7639 { 7640 int do_bounce = 0; 7641 int tries; 7642 u16 lwde; 7643 u16 tx, rx; 7644 bool link_downgraded = refresh_widths; 7645 7646 /* use the hls lock to avoid a race with actual link up */ 7647 tries = 0; 7648 retry: 7649 mutex_lock(&ppd->hls_lock); 7650 /* only apply if the link is up */ 7651 if (ppd->host_link_state & HLS_DOWN) { 7652 /* still going up..wait and retry */ 7653 if (ppd->host_link_state & HLS_GOING_UP) { 7654 if (++tries < 1000) { 7655 mutex_unlock(&ppd->hls_lock); 7656 usleep_range(100, 120); /* arbitrary */ 7657 goto retry; 7658 } 7659 dd_dev_err(ppd->dd, 7660 "%s: giving up waiting for link state change\n", 7661 __func__); 7662 } 7663 goto done; 7664 } 7665 7666 lwde = ppd->link_width_downgrade_enabled; 7667 7668 if (refresh_widths) { 7669 get_link_widths(ppd->dd, &tx, &rx); 7670 ppd->link_width_downgrade_tx_active = tx; 7671 ppd->link_width_downgrade_rx_active = rx; 7672 } 7673 7674 if (ppd->link_width_downgrade_tx_active == 0 || 7675 ppd->link_width_downgrade_rx_active == 0) { 7676 /* the 8051 reported a dead link as a downgrade */ 7677 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n"); 7678 link_downgraded = false; 7679 } else if (lwde == 0) { 7680 /* downgrade is disabled */ 7681 7682 /* bounce if not at starting active width */ 7683 if ((ppd->link_width_active != 7684 ppd->link_width_downgrade_tx_active) || 7685 (ppd->link_width_active != 7686 ppd->link_width_downgrade_rx_active)) { 7687 dd_dev_err(ppd->dd, 7688 "Link downgrade is disabled and link has downgraded, downing link\n"); 7689 dd_dev_err(ppd->dd, 7690 " original 0x%x, tx active 0x%x, rx active 0x%x\n", 7691 ppd->link_width_active, 7692 ppd->link_width_downgrade_tx_active, 7693 ppd->link_width_downgrade_rx_active); 7694 do_bounce = 1; 7695 link_downgraded = false; 7696 } 7697 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 || 7698 (lwde & ppd->link_width_downgrade_rx_active) == 0) { 7699 /* Tx or Rx is outside the enabled policy */ 7700 dd_dev_err(ppd->dd, 7701 "Link is outside of downgrade allowed, downing link\n"); 7702 dd_dev_err(ppd->dd, 7703 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n", 7704 lwde, ppd->link_width_downgrade_tx_active, 7705 ppd->link_width_downgrade_rx_active); 7706 do_bounce = 1; 7707 link_downgraded = false; 7708 } 7709 7710 done: 7711 mutex_unlock(&ppd->hls_lock); 7712 7713 if (do_bounce) { 7714 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0, 7715 OPA_LINKDOWN_REASON_WIDTH_POLICY); 7716 set_link_state(ppd, HLS_DN_OFFLINE); 7717 start_link(ppd); 7718 } 7719 7720 return link_downgraded; 7721 } 7722 7723 /* 7724 * Handle a link downgrade interrupt from the 8051. 7725 * 7726 * This is a work-queue function outside of the interrupt. 7727 */ 7728 void handle_link_downgrade(struct work_struct *work) 7729 { 7730 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7731 link_downgrade_work); 7732 7733 dd_dev_info(ppd->dd, "8051: Link width downgrade\n"); 7734 if (apply_link_downgrade_policy(ppd, true)) 7735 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active); 7736 } 7737 7738 static char *dcc_err_string(char *buf, int buf_len, u64 flags) 7739 { 7740 return flag_string(buf, buf_len, flags, dcc_err_flags, 7741 ARRAY_SIZE(dcc_err_flags)); 7742 } 7743 7744 static char *lcb_err_string(char *buf, int buf_len, u64 flags) 7745 { 7746 return flag_string(buf, buf_len, flags, lcb_err_flags, 7747 ARRAY_SIZE(lcb_err_flags)); 7748 } 7749 7750 static char *dc8051_err_string(char *buf, int buf_len, u64 flags) 7751 { 7752 return flag_string(buf, buf_len, flags, dc8051_err_flags, 7753 ARRAY_SIZE(dc8051_err_flags)); 7754 } 7755 7756 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags) 7757 { 7758 return flag_string(buf, buf_len, flags, dc8051_info_err_flags, 7759 ARRAY_SIZE(dc8051_info_err_flags)); 7760 } 7761 7762 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags) 7763 { 7764 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags, 7765 ARRAY_SIZE(dc8051_info_host_msg_flags)); 7766 } 7767 7768 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg) 7769 { 7770 struct hfi1_pportdata *ppd = dd->pport; 7771 u64 info, err, host_msg; 7772 int queue_link_down = 0; 7773 char buf[96]; 7774 7775 /* look at the flags */ 7776 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) { 7777 /* 8051 information set by firmware */ 7778 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */ 7779 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); 7780 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT) 7781 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK; 7782 host_msg = (info >> 7783 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT) 7784 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK; 7785 7786 /* 7787 * Handle error flags. 7788 */ 7789 if (err & FAILED_LNI) { 7790 /* 7791 * LNI error indications are cleared by the 8051 7792 * only when starting polling. Only pay attention 7793 * to them when in the states that occur during 7794 * LNI. 7795 */ 7796 if (ppd->host_link_state 7797 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 7798 queue_link_down = 1; 7799 dd_dev_info(dd, "Link error: %s\n", 7800 dc8051_info_err_string(buf, 7801 sizeof(buf), 7802 err & 7803 FAILED_LNI)); 7804 } 7805 err &= ~(u64)FAILED_LNI; 7806 } 7807 /* unknown frames can happen durning LNI, just count */ 7808 if (err & UNKNOWN_FRAME) { 7809 ppd->unknown_frame_count++; 7810 err &= ~(u64)UNKNOWN_FRAME; 7811 } 7812 if (err) { 7813 /* report remaining errors, but do not do anything */ 7814 dd_dev_err(dd, "8051 info error: %s\n", 7815 dc8051_info_err_string(buf, sizeof(buf), 7816 err)); 7817 } 7818 7819 /* 7820 * Handle host message flags. 7821 */ 7822 if (host_msg & HOST_REQ_DONE) { 7823 /* 7824 * Presently, the driver does a busy wait for 7825 * host requests to complete. This is only an 7826 * informational message. 7827 * NOTE: The 8051 clears the host message 7828 * information *on the next 8051 command*. 7829 * Therefore, when linkup is achieved, 7830 * this flag will still be set. 7831 */ 7832 host_msg &= ~(u64)HOST_REQ_DONE; 7833 } 7834 if (host_msg & BC_SMA_MSG) { 7835 queue_work(ppd->link_wq, &ppd->sma_message_work); 7836 host_msg &= ~(u64)BC_SMA_MSG; 7837 } 7838 if (host_msg & LINKUP_ACHIEVED) { 7839 dd_dev_info(dd, "8051: Link up\n"); 7840 queue_work(ppd->link_wq, &ppd->link_up_work); 7841 host_msg &= ~(u64)LINKUP_ACHIEVED; 7842 } 7843 if (host_msg & EXT_DEVICE_CFG_REQ) { 7844 handle_8051_request(ppd); 7845 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ; 7846 } 7847 if (host_msg & VERIFY_CAP_FRAME) { 7848 queue_work(ppd->link_wq, &ppd->link_vc_work); 7849 host_msg &= ~(u64)VERIFY_CAP_FRAME; 7850 } 7851 if (host_msg & LINK_GOING_DOWN) { 7852 const char *extra = ""; 7853 /* no downgrade action needed if going down */ 7854 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7855 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7856 extra = " (ignoring downgrade)"; 7857 } 7858 dd_dev_info(dd, "8051: Link down%s\n", extra); 7859 queue_link_down = 1; 7860 host_msg &= ~(u64)LINK_GOING_DOWN; 7861 } 7862 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7863 queue_work(ppd->link_wq, &ppd->link_downgrade_work); 7864 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7865 } 7866 if (host_msg) { 7867 /* report remaining messages, but do not do anything */ 7868 dd_dev_info(dd, "8051 info host message: %s\n", 7869 dc8051_info_host_msg_string(buf, 7870 sizeof(buf), 7871 host_msg)); 7872 } 7873 7874 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK; 7875 } 7876 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) { 7877 /* 7878 * Lost the 8051 heartbeat. If this happens, we 7879 * receive constant interrupts about it. Disable 7880 * the interrupt after the first. 7881 */ 7882 dd_dev_err(dd, "Lost 8051 heartbeat\n"); 7883 write_csr(dd, DC_DC8051_ERR_EN, 7884 read_csr(dd, DC_DC8051_ERR_EN) & 7885 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK); 7886 7887 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK; 7888 } 7889 if (reg) { 7890 /* report the error, but do not do anything */ 7891 dd_dev_err(dd, "8051 error: %s\n", 7892 dc8051_err_string(buf, sizeof(buf), reg)); 7893 } 7894 7895 if (queue_link_down) { 7896 /* 7897 * if the link is already going down or disabled, do not 7898 * queue another. If there's a link down entry already 7899 * queued, don't queue another one. 7900 */ 7901 if ((ppd->host_link_state & 7902 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) || 7903 ppd->link_enabled == 0) { 7904 dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n", 7905 __func__, ppd->host_link_state, 7906 ppd->link_enabled); 7907 } else { 7908 if (xchg(&ppd->is_link_down_queued, 1) == 1) 7909 dd_dev_info(dd, 7910 "%s: link down request already queued\n", 7911 __func__); 7912 else 7913 queue_work(ppd->link_wq, &ppd->link_down_work); 7914 } 7915 } 7916 } 7917 7918 static const char * const fm_config_txt[] = { 7919 [0] = 7920 "BadHeadDist: Distance violation between two head flits", 7921 [1] = 7922 "BadTailDist: Distance violation between two tail flits", 7923 [2] = 7924 "BadCtrlDist: Distance violation between two credit control flits", 7925 [3] = 7926 "BadCrdAck: Credits return for unsupported VL", 7927 [4] = 7928 "UnsupportedVLMarker: Received VL Marker", 7929 [5] = 7930 "BadPreempt: Exceeded the preemption nesting level", 7931 [6] = 7932 "BadControlFlit: Received unsupported control flit", 7933 /* no 7 */ 7934 [8] = 7935 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL", 7936 }; 7937 7938 static const char * const port_rcv_txt[] = { 7939 [1] = 7940 "BadPktLen: Illegal PktLen", 7941 [2] = 7942 "PktLenTooLong: Packet longer than PktLen", 7943 [3] = 7944 "PktLenTooShort: Packet shorter than PktLen", 7945 [4] = 7946 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)", 7947 [5] = 7948 "BadDLID: Illegal DLID (0, doesn't match HFI)", 7949 [6] = 7950 "BadL2: Illegal L2 opcode", 7951 [7] = 7952 "BadSC: Unsupported SC", 7953 [9] = 7954 "BadRC: Illegal RC", 7955 [11] = 7956 "PreemptError: Preempting with same VL", 7957 [12] = 7958 "PreemptVL15: Preempting a VL15 packet", 7959 }; 7960 7961 #define OPA_LDR_FMCONFIG_OFFSET 16 7962 #define OPA_LDR_PORTRCV_OFFSET 0 7963 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 7964 { 7965 u64 info, hdr0, hdr1; 7966 const char *extra; 7967 char buf[96]; 7968 struct hfi1_pportdata *ppd = dd->pport; 7969 u8 lcl_reason = 0; 7970 int do_bounce = 0; 7971 7972 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) { 7973 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) { 7974 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); 7975 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK; 7976 /* set status bit */ 7977 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK; 7978 } 7979 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK; 7980 } 7981 7982 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) { 7983 struct hfi1_pportdata *ppd = dd->pport; 7984 /* this counter saturates at (2^32) - 1 */ 7985 if (ppd->link_downed < (u32)UINT_MAX) 7986 ppd->link_downed++; 7987 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK; 7988 } 7989 7990 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) { 7991 u8 reason_valid = 1; 7992 7993 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); 7994 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) { 7995 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK; 7996 /* set status bit */ 7997 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK; 7998 } 7999 switch (info) { 8000 case 0: 8001 case 1: 8002 case 2: 8003 case 3: 8004 case 4: 8005 case 5: 8006 case 6: 8007 extra = fm_config_txt[info]; 8008 break; 8009 case 8: 8010 extra = fm_config_txt[info]; 8011 if (ppd->port_error_action & 8012 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) { 8013 do_bounce = 1; 8014 /* 8015 * lcl_reason cannot be derived from info 8016 * for this error 8017 */ 8018 lcl_reason = 8019 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER; 8020 } 8021 break; 8022 default: 8023 reason_valid = 0; 8024 snprintf(buf, sizeof(buf), "reserved%lld", info); 8025 extra = buf; 8026 break; 8027 } 8028 8029 if (reason_valid && !do_bounce) { 8030 do_bounce = ppd->port_error_action & 8031 (1 << (OPA_LDR_FMCONFIG_OFFSET + info)); 8032 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST; 8033 } 8034 8035 /* just report this */ 8036 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n", 8037 extra); 8038 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK; 8039 } 8040 8041 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) { 8042 u8 reason_valid = 1; 8043 8044 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); 8045 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); 8046 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); 8047 if (!(dd->err_info_rcvport.status_and_code & 8048 OPA_EI_STATUS_SMASK)) { 8049 dd->err_info_rcvport.status_and_code = 8050 info & OPA_EI_CODE_SMASK; 8051 /* set status bit */ 8052 dd->err_info_rcvport.status_and_code |= 8053 OPA_EI_STATUS_SMASK; 8054 /* 8055 * save first 2 flits in the packet that caused 8056 * the error 8057 */ 8058 dd->err_info_rcvport.packet_flit1 = hdr0; 8059 dd->err_info_rcvport.packet_flit2 = hdr1; 8060 } 8061 switch (info) { 8062 case 1: 8063 case 2: 8064 case 3: 8065 case 4: 8066 case 5: 8067 case 6: 8068 case 7: 8069 case 9: 8070 case 11: 8071 case 12: 8072 extra = port_rcv_txt[info]; 8073 break; 8074 default: 8075 reason_valid = 0; 8076 snprintf(buf, sizeof(buf), "reserved%lld", info); 8077 extra = buf; 8078 break; 8079 } 8080 8081 if (reason_valid && !do_bounce) { 8082 do_bounce = ppd->port_error_action & 8083 (1 << (OPA_LDR_PORTRCV_OFFSET + info)); 8084 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0; 8085 } 8086 8087 /* just report this */ 8088 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n" 8089 " hdr0 0x%llx, hdr1 0x%llx\n", 8090 extra, hdr0, hdr1); 8091 8092 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK; 8093 } 8094 8095 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) { 8096 /* informative only */ 8097 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n"); 8098 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK; 8099 } 8100 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) { 8101 /* informative only */ 8102 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n"); 8103 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK; 8104 } 8105 8106 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev))) 8107 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK; 8108 8109 /* report any remaining errors */ 8110 if (reg) 8111 dd_dev_info_ratelimited(dd, "DCC Error: %s\n", 8112 dcc_err_string(buf, sizeof(buf), reg)); 8113 8114 if (lcl_reason == 0) 8115 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN; 8116 8117 if (do_bounce) { 8118 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n", 8119 __func__); 8120 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason); 8121 queue_work(ppd->link_wq, &ppd->link_bounce_work); 8122 } 8123 } 8124 8125 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 8126 { 8127 char buf[96]; 8128 8129 dd_dev_info(dd, "LCB Error: %s\n", 8130 lcb_err_string(buf, sizeof(buf), reg)); 8131 } 8132 8133 /* 8134 * CCE block DC interrupt. Source is < 8. 8135 */ 8136 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source) 8137 { 8138 const struct err_reg_info *eri = &dc_errs[source]; 8139 8140 if (eri->handler) { 8141 interrupt_clear_down(dd, 0, eri); 8142 } else if (source == 3 /* dc_lbm_int */) { 8143 /* 8144 * This indicates that a parity error has occurred on the 8145 * address/control lines presented to the LBM. The error 8146 * is a single pulse, there is no associated error flag, 8147 * and it is non-maskable. This is because if a parity 8148 * error occurs on the request the request is dropped. 8149 * This should never occur, but it is nice to know if it 8150 * ever does. 8151 */ 8152 dd_dev_err(dd, "Parity error in DC LBM block\n"); 8153 } else { 8154 dd_dev_err(dd, "Invalid DC interrupt %u\n", source); 8155 } 8156 } 8157 8158 /* 8159 * TX block send credit interrupt. Source is < 160. 8160 */ 8161 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source) 8162 { 8163 sc_group_release_update(dd, source); 8164 } 8165 8166 /* 8167 * TX block SDMA interrupt. Source is < 48. 8168 * 8169 * SDMA interrupts are grouped by type: 8170 * 8171 * 0 - N-1 = SDma 8172 * N - 2N-1 = SDmaProgress 8173 * 2N - 3N-1 = SDmaIdle 8174 */ 8175 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source) 8176 { 8177 /* what interrupt */ 8178 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 8179 /* which engine */ 8180 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 8181 8182 #ifdef CONFIG_SDMA_VERBOSITY 8183 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which, 8184 slashstrip(__FILE__), __LINE__, __func__); 8185 sdma_dumpstate(&dd->per_sdma[which]); 8186 #endif 8187 8188 if (likely(what < 3 && which < dd->num_sdma)) { 8189 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source); 8190 } else { 8191 /* should not happen */ 8192 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source); 8193 } 8194 } 8195 8196 /** 8197 * is_rcv_avail_int() - User receive context available IRQ handler 8198 * @dd: valid dd 8199 * @source: logical IRQ source (offset from IS_RCVAVAIL_START) 8200 * 8201 * RX block receive available interrupt. Source is < 160. 8202 * 8203 * This is the general interrupt handler for user (PSM) receive contexts, 8204 * and can only be used for non-threaded IRQs. 8205 */ 8206 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source) 8207 { 8208 struct hfi1_ctxtdata *rcd; 8209 char *err_detail; 8210 8211 if (likely(source < dd->num_rcv_contexts)) { 8212 rcd = hfi1_rcd_get_by_index(dd, source); 8213 if (rcd) { 8214 handle_user_interrupt(rcd); 8215 hfi1_rcd_put(rcd); 8216 return; /* OK */ 8217 } 8218 /* received an interrupt, but no rcd */ 8219 err_detail = "dataless"; 8220 } else { 8221 /* received an interrupt, but are not using that context */ 8222 err_detail = "out of range"; 8223 } 8224 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n", 8225 err_detail, source); 8226 } 8227 8228 /** 8229 * is_rcv_urgent_int() - User receive context urgent IRQ handler 8230 * @dd: valid dd 8231 * @source: logical IRQ source (offset from IS_RCVURGENT_START) 8232 * 8233 * RX block receive urgent interrupt. Source is < 160. 8234 * 8235 * NOTE: kernel receive contexts specifically do NOT enable this IRQ. 8236 */ 8237 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source) 8238 { 8239 struct hfi1_ctxtdata *rcd; 8240 char *err_detail; 8241 8242 if (likely(source < dd->num_rcv_contexts)) { 8243 rcd = hfi1_rcd_get_by_index(dd, source); 8244 if (rcd) { 8245 handle_user_interrupt(rcd); 8246 hfi1_rcd_put(rcd); 8247 return; /* OK */ 8248 } 8249 /* received an interrupt, but no rcd */ 8250 err_detail = "dataless"; 8251 } else { 8252 /* received an interrupt, but are not using that context */ 8253 err_detail = "out of range"; 8254 } 8255 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n", 8256 err_detail, source); 8257 } 8258 8259 /* 8260 * Reserved range interrupt. Should not be called in normal operation. 8261 */ 8262 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source) 8263 { 8264 char name[64]; 8265 8266 dd_dev_err(dd, "unexpected %s interrupt\n", 8267 is_reserved_name(name, sizeof(name), source)); 8268 } 8269 8270 static const struct is_table is_table[] = { 8271 /* 8272 * start end 8273 * name func interrupt func 8274 */ 8275 { IS_GENERAL_ERR_START, IS_GENERAL_ERR_END, 8276 is_misc_err_name, is_misc_err_int }, 8277 { IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END, 8278 is_sdma_eng_err_name, is_sdma_eng_err_int }, 8279 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, 8280 is_sendctxt_err_name, is_sendctxt_err_int }, 8281 { IS_SDMA_START, IS_SDMA_IDLE_END, 8282 is_sdma_eng_name, is_sdma_eng_int }, 8283 { IS_VARIOUS_START, IS_VARIOUS_END, 8284 is_various_name, is_various_int }, 8285 { IS_DC_START, IS_DC_END, 8286 is_dc_name, is_dc_int }, 8287 { IS_RCVAVAIL_START, IS_RCVAVAIL_END, 8288 is_rcv_avail_name, is_rcv_avail_int }, 8289 { IS_RCVURGENT_START, IS_RCVURGENT_END, 8290 is_rcv_urgent_name, is_rcv_urgent_int }, 8291 { IS_SENDCREDIT_START, IS_SENDCREDIT_END, 8292 is_send_credit_name, is_send_credit_int}, 8293 { IS_RESERVED_START, IS_RESERVED_END, 8294 is_reserved_name, is_reserved_int}, 8295 }; 8296 8297 /* 8298 * Interrupt source interrupt - called when the given source has an interrupt. 8299 * Source is a bit index into an array of 64-bit integers. 8300 */ 8301 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source) 8302 { 8303 const struct is_table *entry; 8304 8305 /* avoids a double compare by walking the table in-order */ 8306 for (entry = &is_table[0]; entry->is_name; entry++) { 8307 if (source <= entry->end) { 8308 trace_hfi1_interrupt(dd, entry, source); 8309 entry->is_int(dd, source - entry->start); 8310 return; 8311 } 8312 } 8313 /* fell off the end */ 8314 dd_dev_err(dd, "invalid interrupt source %u\n", source); 8315 } 8316 8317 /** 8318 * gerneral_interrupt() - General interrupt handler 8319 * @irq: MSIx IRQ vector 8320 * @data: hfi1 devdata 8321 * 8322 * This is able to correctly handle all non-threaded interrupts. Receive 8323 * context DATA IRQs are threaded and are not supported by this handler. 8324 * 8325 */ 8326 irqreturn_t general_interrupt(int irq, void *data) 8327 { 8328 struct hfi1_devdata *dd = data; 8329 u64 regs[CCE_NUM_INT_CSRS]; 8330 u32 bit; 8331 int i; 8332 irqreturn_t handled = IRQ_NONE; 8333 8334 this_cpu_inc(*dd->int_counter); 8335 8336 /* phase 1: scan and clear all handled interrupts */ 8337 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 8338 if (dd->gi_mask[i] == 0) { 8339 regs[i] = 0; /* used later */ 8340 continue; 8341 } 8342 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & 8343 dd->gi_mask[i]; 8344 /* only clear if anything is set */ 8345 if (regs[i]) 8346 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); 8347 } 8348 8349 /* phase 2: call the appropriate handler */ 8350 for_each_set_bit(bit, (unsigned long *)®s[0], 8351 CCE_NUM_INT_CSRS * 64) { 8352 is_interrupt(dd, bit); 8353 handled = IRQ_HANDLED; 8354 } 8355 8356 return handled; 8357 } 8358 8359 irqreturn_t sdma_interrupt(int irq, void *data) 8360 { 8361 struct sdma_engine *sde = data; 8362 struct hfi1_devdata *dd = sde->dd; 8363 u64 status; 8364 8365 #ifdef CONFIG_SDMA_VERBOSITY 8366 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 8367 slashstrip(__FILE__), __LINE__, __func__); 8368 sdma_dumpstate(sde); 8369 #endif 8370 8371 this_cpu_inc(*dd->int_counter); 8372 8373 /* This read_csr is really bad in the hot path */ 8374 status = read_csr(dd, 8375 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64))) 8376 & sde->imask; 8377 if (likely(status)) { 8378 /* clear the interrupt(s) */ 8379 write_csr(dd, 8380 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)), 8381 status); 8382 8383 /* handle the interrupt(s) */ 8384 sdma_engine_interrupt(sde, status); 8385 } else { 8386 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n", 8387 sde->this_idx); 8388 } 8389 return IRQ_HANDLED; 8390 } 8391 8392 /* 8393 * Clear the receive interrupt. Use a read of the interrupt clear CSR 8394 * to insure that the write completed. This does NOT guarantee that 8395 * queued DMA writes to memory from the chip are pushed. 8396 */ 8397 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd) 8398 { 8399 struct hfi1_devdata *dd = rcd->dd; 8400 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg); 8401 8402 write_csr(dd, addr, rcd->imask); 8403 /* force the above write on the chip and get a value back */ 8404 (void)read_csr(dd, addr); 8405 } 8406 8407 /* force the receive interrupt */ 8408 void force_recv_intr(struct hfi1_ctxtdata *rcd) 8409 { 8410 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); 8411 } 8412 8413 /* 8414 * Return non-zero if a packet is present. 8415 * 8416 * This routine is called when rechecking for packets after the RcvAvail 8417 * interrupt has been cleared down. First, do a quick check of memory for 8418 * a packet present. If not found, use an expensive CSR read of the context 8419 * tail to determine the actual tail. The CSR read is necessary because there 8420 * is no method to push pending DMAs to memory other than an interrupt and we 8421 * are trying to determine if we need to force an interrupt. 8422 */ 8423 static inline int check_packet_present(struct hfi1_ctxtdata *rcd) 8424 { 8425 u32 tail; 8426 8427 if (hfi1_packet_present(rcd)) 8428 return 1; 8429 8430 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */ 8431 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 8432 return hfi1_rcd_head(rcd) != tail; 8433 } 8434 8435 /** 8436 * Common code for receive contexts interrupt handlers. 8437 * Update traces, increment kernel IRQ counter and 8438 * setup ASPM when needed. 8439 */ 8440 static void receive_interrupt_common(struct hfi1_ctxtdata *rcd) 8441 { 8442 struct hfi1_devdata *dd = rcd->dd; 8443 8444 trace_hfi1_receive_interrupt(dd, rcd); 8445 this_cpu_inc(*dd->int_counter); 8446 aspm_ctx_disable(rcd); 8447 } 8448 8449 /** 8450 * __hfi1_rcd_eoi_intr() - Make HW issue receive interrupt 8451 * when there are packets present in the queue. When calling 8452 * with interrupts enabled please use hfi1_rcd_eoi_intr. 8453 * 8454 * @rcd: valid receive context 8455 */ 8456 static void __hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd) 8457 { 8458 clear_recv_intr(rcd); 8459 if (check_packet_present(rcd)) 8460 force_recv_intr(rcd); 8461 } 8462 8463 /** 8464 * hfi1_rcd_eoi_intr() - End of Interrupt processing action 8465 * 8466 * @rcd: Ptr to hfi1_ctxtdata of receive context 8467 * 8468 * Hold IRQs so we can safely clear the interrupt and 8469 * recheck for a packet that may have arrived after the previous 8470 * check and the interrupt clear. If a packet arrived, force another 8471 * interrupt. This routine can be called at the end of receive packet 8472 * processing in interrupt service routines, interrupt service thread 8473 * and softirqs 8474 */ 8475 static void hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd) 8476 { 8477 unsigned long flags; 8478 8479 local_irq_save(flags); 8480 __hfi1_rcd_eoi_intr(rcd); 8481 local_irq_restore(flags); 8482 } 8483 8484 /** 8485 * hfi1_netdev_rx_napi - napi poll function to move eoi inline 8486 * @napi - pointer to napi object 8487 * @budget - netdev budget 8488 */ 8489 int hfi1_netdev_rx_napi(struct napi_struct *napi, int budget) 8490 { 8491 struct hfi1_netdev_rxq *rxq = container_of(napi, 8492 struct hfi1_netdev_rxq, napi); 8493 struct hfi1_ctxtdata *rcd = rxq->rcd; 8494 int work_done = 0; 8495 8496 work_done = rcd->do_interrupt(rcd, budget); 8497 8498 if (work_done < budget) { 8499 napi_complete_done(napi, work_done); 8500 hfi1_rcd_eoi_intr(rcd); 8501 } 8502 8503 return work_done; 8504 } 8505 8506 /* Receive packet napi handler for netdevs VNIC and AIP */ 8507 irqreturn_t receive_context_interrupt_napi(int irq, void *data) 8508 { 8509 struct hfi1_ctxtdata *rcd = data; 8510 8511 receive_interrupt_common(rcd); 8512 8513 if (likely(rcd->napi)) { 8514 if (likely(napi_schedule_prep(rcd->napi))) 8515 __napi_schedule_irqoff(rcd->napi); 8516 else 8517 __hfi1_rcd_eoi_intr(rcd); 8518 } else { 8519 WARN_ONCE(1, "Napi IRQ handler without napi set up ctxt=%d\n", 8520 rcd->ctxt); 8521 __hfi1_rcd_eoi_intr(rcd); 8522 } 8523 8524 return IRQ_HANDLED; 8525 } 8526 8527 /* 8528 * Receive packet IRQ handler. This routine expects to be on its own IRQ. 8529 * This routine will try to handle packets immediately (latency), but if 8530 * it finds too many, it will invoke the thread handler (bandwitdh). The 8531 * chip receive interrupt is *not* cleared down until this or the thread (if 8532 * invoked) is finished. The intent is to avoid extra interrupts while we 8533 * are processing packets anyway. 8534 */ 8535 irqreturn_t receive_context_interrupt(int irq, void *data) 8536 { 8537 struct hfi1_ctxtdata *rcd = data; 8538 int disposition; 8539 8540 receive_interrupt_common(rcd); 8541 8542 /* receive interrupt remains blocked while processing packets */ 8543 disposition = rcd->do_interrupt(rcd, 0); 8544 8545 /* 8546 * Too many packets were seen while processing packets in this 8547 * IRQ handler. Invoke the handler thread. The receive interrupt 8548 * remains blocked. 8549 */ 8550 if (disposition == RCV_PKT_LIMIT) 8551 return IRQ_WAKE_THREAD; 8552 8553 __hfi1_rcd_eoi_intr(rcd); 8554 return IRQ_HANDLED; 8555 } 8556 8557 /* 8558 * Receive packet thread handler. This expects to be invoked with the 8559 * receive interrupt still blocked. 8560 */ 8561 irqreturn_t receive_context_thread(int irq, void *data) 8562 { 8563 struct hfi1_ctxtdata *rcd = data; 8564 8565 /* receive interrupt is still blocked from the IRQ handler */ 8566 (void)rcd->do_interrupt(rcd, 1); 8567 8568 hfi1_rcd_eoi_intr(rcd); 8569 8570 return IRQ_HANDLED; 8571 } 8572 8573 /* ========================================================================= */ 8574 8575 u32 read_physical_state(struct hfi1_devdata *dd) 8576 { 8577 u64 reg; 8578 8579 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 8580 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT) 8581 & DC_DC8051_STS_CUR_STATE_PORT_MASK; 8582 } 8583 8584 u32 read_logical_state(struct hfi1_devdata *dd) 8585 { 8586 u64 reg; 8587 8588 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8589 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT) 8590 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK; 8591 } 8592 8593 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate) 8594 { 8595 u64 reg; 8596 8597 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8598 /* clear current state, set new state */ 8599 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK; 8600 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT; 8601 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); 8602 } 8603 8604 /* 8605 * Use the 8051 to read a LCB CSR. 8606 */ 8607 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data) 8608 { 8609 u32 regno; 8610 int ret; 8611 8612 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 8613 if (acquire_lcb_access(dd, 0) == 0) { 8614 *data = read_csr(dd, addr); 8615 release_lcb_access(dd, 0); 8616 return 0; 8617 } 8618 return -EBUSY; 8619 } 8620 8621 /* register is an index of LCB registers: (offset - base) / 8 */ 8622 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8623 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data); 8624 if (ret != HCMD_SUCCESS) 8625 return -EBUSY; 8626 return 0; 8627 } 8628 8629 /* 8630 * Provide a cache for some of the LCB registers in case the LCB is 8631 * unavailable. 8632 * (The LCB is unavailable in certain link states, for example.) 8633 */ 8634 struct lcb_datum { 8635 u32 off; 8636 u64 val; 8637 }; 8638 8639 static struct lcb_datum lcb_cache[] = { 8640 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0}, 8641 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 }, 8642 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 }, 8643 }; 8644 8645 static void update_lcb_cache(struct hfi1_devdata *dd) 8646 { 8647 int i; 8648 int ret; 8649 u64 val; 8650 8651 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8652 ret = read_lcb_csr(dd, lcb_cache[i].off, &val); 8653 8654 /* Update if we get good data */ 8655 if (likely(ret != -EBUSY)) 8656 lcb_cache[i].val = val; 8657 } 8658 } 8659 8660 static int read_lcb_cache(u32 off, u64 *val) 8661 { 8662 int i; 8663 8664 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8665 if (lcb_cache[i].off == off) { 8666 *val = lcb_cache[i].val; 8667 return 0; 8668 } 8669 } 8670 8671 pr_warn("%s bad offset 0x%x\n", __func__, off); 8672 return -1; 8673 } 8674 8675 /* 8676 * Read an LCB CSR. Access may not be in host control, so check. 8677 * Return 0 on success, -EBUSY on failure. 8678 */ 8679 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data) 8680 { 8681 struct hfi1_pportdata *ppd = dd->pport; 8682 8683 /* if up, go through the 8051 for the value */ 8684 if (ppd->host_link_state & HLS_UP) 8685 return read_lcb_via_8051(dd, addr, data); 8686 /* if going up or down, check the cache, otherwise, no access */ 8687 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) { 8688 if (read_lcb_cache(addr, data)) 8689 return -EBUSY; 8690 return 0; 8691 } 8692 8693 /* otherwise, host has access */ 8694 *data = read_csr(dd, addr); 8695 return 0; 8696 } 8697 8698 /* 8699 * Use the 8051 to write a LCB CSR. 8700 */ 8701 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data) 8702 { 8703 u32 regno; 8704 int ret; 8705 8706 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || 8707 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) { 8708 if (acquire_lcb_access(dd, 0) == 0) { 8709 write_csr(dd, addr, data); 8710 release_lcb_access(dd, 0); 8711 return 0; 8712 } 8713 return -EBUSY; 8714 } 8715 8716 /* register is an index of LCB registers: (offset - base) / 8 */ 8717 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8718 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data); 8719 if (ret != HCMD_SUCCESS) 8720 return -EBUSY; 8721 return 0; 8722 } 8723 8724 /* 8725 * Write an LCB CSR. Access may not be in host control, so check. 8726 * Return 0 on success, -EBUSY on failure. 8727 */ 8728 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data) 8729 { 8730 struct hfi1_pportdata *ppd = dd->pport; 8731 8732 /* if up, go through the 8051 for the value */ 8733 if (ppd->host_link_state & HLS_UP) 8734 return write_lcb_via_8051(dd, addr, data); 8735 /* if going up or down, no access */ 8736 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) 8737 return -EBUSY; 8738 /* otherwise, host has access */ 8739 write_csr(dd, addr, data); 8740 return 0; 8741 } 8742 8743 /* 8744 * Returns: 8745 * < 0 = Linux error, not able to get access 8746 * > 0 = 8051 command RETURN_CODE 8747 */ 8748 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 8749 u64 *out_data) 8750 { 8751 u64 reg, completed; 8752 int return_code; 8753 unsigned long timeout; 8754 8755 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data); 8756 8757 mutex_lock(&dd->dc8051_lock); 8758 8759 /* We can't send any commands to the 8051 if it's in reset */ 8760 if (dd->dc_shutdown) { 8761 return_code = -ENODEV; 8762 goto fail; 8763 } 8764 8765 /* 8766 * If an 8051 host command timed out previously, then the 8051 is 8767 * stuck. 8768 * 8769 * On first timeout, attempt to reset and restart the entire DC 8770 * block (including 8051). (Is this too big of a hammer?) 8771 * 8772 * If the 8051 times out a second time, the reset did not bring it 8773 * back to healthy life. In that case, fail any subsequent commands. 8774 */ 8775 if (dd->dc8051_timed_out) { 8776 if (dd->dc8051_timed_out > 1) { 8777 dd_dev_err(dd, 8778 "Previous 8051 host command timed out, skipping command %u\n", 8779 type); 8780 return_code = -ENXIO; 8781 goto fail; 8782 } 8783 _dc_shutdown(dd); 8784 _dc_start(dd); 8785 } 8786 8787 /* 8788 * If there is no timeout, then the 8051 command interface is 8789 * waiting for a command. 8790 */ 8791 8792 /* 8793 * When writing a LCB CSR, out_data contains the full value to 8794 * to be written, while in_data contains the relative LCB 8795 * address in 7:0. Do the work here, rather than the caller, 8796 * of distrubting the write data to where it needs to go: 8797 * 8798 * Write data 8799 * 39:00 -> in_data[47:8] 8800 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE 8801 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA 8802 */ 8803 if (type == HCMD_WRITE_LCB_CSR) { 8804 in_data |= ((*out_data) & 0xffffffffffull) << 8; 8805 /* must preserve COMPLETED - it is tied to hardware */ 8806 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); 8807 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK; 8808 reg |= ((((*out_data) >> 40) & 0xff) << 8809 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT) 8810 | ((((*out_data) >> 48) & 0xffff) << 8811 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 8812 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); 8813 } 8814 8815 /* 8816 * Do two writes: the first to stabilize the type and req_data, the 8817 * second to activate. 8818 */ 8819 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK) 8820 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8821 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK) 8822 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT; 8823 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8824 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK; 8825 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8826 8827 /* wait for completion, alternate: interrupt */ 8828 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT); 8829 while (1) { 8830 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); 8831 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK; 8832 if (completed) 8833 break; 8834 if (time_after(jiffies, timeout)) { 8835 dd->dc8051_timed_out++; 8836 dd_dev_err(dd, "8051 host command %u timeout\n", type); 8837 if (out_data) 8838 *out_data = 0; 8839 return_code = -ETIMEDOUT; 8840 goto fail; 8841 } 8842 udelay(2); 8843 } 8844 8845 if (out_data) { 8846 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT) 8847 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK; 8848 if (type == HCMD_READ_LCB_CSR) { 8849 /* top 16 bits are in a different register */ 8850 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) 8851 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK) 8852 << (48 8853 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT); 8854 } 8855 } 8856 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT) 8857 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK; 8858 dd->dc8051_timed_out = 0; 8859 /* 8860 * Clear command for next user. 8861 */ 8862 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); 8863 8864 fail: 8865 mutex_unlock(&dd->dc8051_lock); 8866 return return_code; 8867 } 8868 8869 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state) 8870 { 8871 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL); 8872 } 8873 8874 int load_8051_config(struct hfi1_devdata *dd, u8 field_id, 8875 u8 lane_id, u32 config_data) 8876 { 8877 u64 data; 8878 int ret; 8879 8880 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT 8881 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT 8882 | (u64)config_data << LOAD_DATA_DATA_SHIFT; 8883 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL); 8884 if (ret != HCMD_SUCCESS) { 8885 dd_dev_err(dd, 8886 "load 8051 config: field id %d, lane %d, err %d\n", 8887 (int)field_id, (int)lane_id, ret); 8888 } 8889 return ret; 8890 } 8891 8892 /* 8893 * Read the 8051 firmware "registers". Use the RAM directly. Always 8894 * set the result, even on error. 8895 * Return 0 on success, -errno on failure 8896 */ 8897 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id, 8898 u32 *result) 8899 { 8900 u64 big_data; 8901 u32 addr; 8902 int ret; 8903 8904 /* address start depends on the lane_id */ 8905 if (lane_id < 4) 8906 addr = (4 * NUM_GENERAL_FIELDS) 8907 + (lane_id * 4 * NUM_LANE_FIELDS); 8908 else 8909 addr = 0; 8910 addr += field_id * 4; 8911 8912 /* read is in 8-byte chunks, hardware will truncate the address down */ 8913 ret = read_8051_data(dd, addr, 8, &big_data); 8914 8915 if (ret == 0) { 8916 /* extract the 4 bytes we want */ 8917 if (addr & 0x4) 8918 *result = (u32)(big_data >> 32); 8919 else 8920 *result = (u32)big_data; 8921 } else { 8922 *result = 0; 8923 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n", 8924 __func__, lane_id, field_id); 8925 } 8926 8927 return ret; 8928 } 8929 8930 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management, 8931 u8 continuous) 8932 { 8933 u32 frame; 8934 8935 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 8936 | power_management << POWER_MANAGEMENT_SHIFT; 8937 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY, 8938 GENERAL_CONFIG, frame); 8939 } 8940 8941 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu, 8942 u16 vl15buf, u8 crc_sizes) 8943 { 8944 u32 frame; 8945 8946 frame = (u32)vau << VAU_SHIFT 8947 | (u32)z << Z_SHIFT 8948 | (u32)vcu << VCU_SHIFT 8949 | (u32)vl15buf << VL15BUF_SHIFT 8950 | (u32)crc_sizes << CRC_SIZES_SHIFT; 8951 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC, 8952 GENERAL_CONFIG, frame); 8953 } 8954 8955 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 8956 u8 *flag_bits, u16 *link_widths) 8957 { 8958 u32 frame; 8959 8960 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8961 &frame); 8962 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK; 8963 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK; 8964 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8965 } 8966 8967 static int write_vc_local_link_mode(struct hfi1_devdata *dd, 8968 u8 misc_bits, 8969 u8 flag_bits, 8970 u16 link_widths) 8971 { 8972 u32 frame; 8973 8974 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT 8975 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT 8976 | (u32)link_widths << LINK_WIDTH_SHIFT; 8977 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8978 frame); 8979 } 8980 8981 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id, 8982 u8 device_rev) 8983 { 8984 u32 frame; 8985 8986 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT) 8987 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT); 8988 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame); 8989 } 8990 8991 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 8992 u8 *device_rev) 8993 { 8994 u32 frame; 8995 8996 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame); 8997 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK; 8998 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT) 8999 & REMOTE_DEVICE_REV_MASK; 9000 } 9001 9002 int write_host_interface_version(struct hfi1_devdata *dd, u8 version) 9003 { 9004 u32 frame; 9005 u32 mask; 9006 9007 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); 9008 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame); 9009 /* Clear, then set field */ 9010 frame &= ~mask; 9011 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT); 9012 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, 9013 frame); 9014 } 9015 9016 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 9017 u8 *ver_patch) 9018 { 9019 u32 frame; 9020 9021 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame); 9022 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) & 9023 STS_FM_VERSION_MAJOR_MASK; 9024 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) & 9025 STS_FM_VERSION_MINOR_MASK; 9026 9027 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame); 9028 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) & 9029 STS_FM_VERSION_PATCH_MASK; 9030 } 9031 9032 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 9033 u8 *continuous) 9034 { 9035 u32 frame; 9036 9037 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame); 9038 *power_management = (frame >> POWER_MANAGEMENT_SHIFT) 9039 & POWER_MANAGEMENT_MASK; 9040 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT) 9041 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK; 9042 } 9043 9044 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 9045 u8 *vcu, u16 *vl15buf, u8 *crc_sizes) 9046 { 9047 u32 frame; 9048 9049 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame); 9050 *vau = (frame >> VAU_SHIFT) & VAU_MASK; 9051 *z = (frame >> Z_SHIFT) & Z_MASK; 9052 *vcu = (frame >> VCU_SHIFT) & VCU_MASK; 9053 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK; 9054 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK; 9055 } 9056 9057 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 9058 u8 *remote_tx_rate, 9059 u16 *link_widths) 9060 { 9061 u32 frame; 9062 9063 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG, 9064 &frame); 9065 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT) 9066 & REMOTE_TX_RATE_MASK; 9067 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 9068 } 9069 9070 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx) 9071 { 9072 u32 frame; 9073 9074 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame); 9075 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK; 9076 } 9077 9078 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls) 9079 { 9080 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls); 9081 } 9082 9083 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs) 9084 { 9085 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs); 9086 } 9087 9088 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality) 9089 { 9090 u32 frame; 9091 int ret; 9092 9093 *link_quality = 0; 9094 if (dd->pport->host_link_state & HLS_UP) { 9095 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, 9096 &frame); 9097 if (ret == 0) 9098 *link_quality = (frame >> LINK_QUALITY_SHIFT) 9099 & LINK_QUALITY_MASK; 9100 } 9101 } 9102 9103 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc) 9104 { 9105 u32 frame; 9106 9107 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame); 9108 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK; 9109 } 9110 9111 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr) 9112 { 9113 u32 frame; 9114 9115 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame); 9116 *ldr = (frame & 0xff); 9117 } 9118 9119 static int read_tx_settings(struct hfi1_devdata *dd, 9120 u8 *enable_lane_tx, 9121 u8 *tx_polarity_inversion, 9122 u8 *rx_polarity_inversion, 9123 u8 *max_rate) 9124 { 9125 u32 frame; 9126 int ret; 9127 9128 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame); 9129 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT) 9130 & ENABLE_LANE_TX_MASK; 9131 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT) 9132 & TX_POLARITY_INVERSION_MASK; 9133 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT) 9134 & RX_POLARITY_INVERSION_MASK; 9135 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK; 9136 return ret; 9137 } 9138 9139 static int write_tx_settings(struct hfi1_devdata *dd, 9140 u8 enable_lane_tx, 9141 u8 tx_polarity_inversion, 9142 u8 rx_polarity_inversion, 9143 u8 max_rate) 9144 { 9145 u32 frame; 9146 9147 /* no need to mask, all variable sizes match field widths */ 9148 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT 9149 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT 9150 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT 9151 | max_rate << MAX_RATE_SHIFT; 9152 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame); 9153 } 9154 9155 /* 9156 * Read an idle LCB message. 9157 * 9158 * Returns 0 on success, -EINVAL on error 9159 */ 9160 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out) 9161 { 9162 int ret; 9163 9164 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out); 9165 if (ret != HCMD_SUCCESS) { 9166 dd_dev_err(dd, "read idle message: type %d, err %d\n", 9167 (u32)type, ret); 9168 return -EINVAL; 9169 } 9170 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out); 9171 /* return only the payload as we already know the type */ 9172 *data_out >>= IDLE_PAYLOAD_SHIFT; 9173 return 0; 9174 } 9175 9176 /* 9177 * Read an idle SMA message. To be done in response to a notification from 9178 * the 8051. 9179 * 9180 * Returns 0 on success, -EINVAL on error 9181 */ 9182 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data) 9183 { 9184 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT, 9185 data); 9186 } 9187 9188 /* 9189 * Send an idle LCB message. 9190 * 9191 * Returns 0 on success, -EINVAL on error 9192 */ 9193 static int send_idle_message(struct hfi1_devdata *dd, u64 data) 9194 { 9195 int ret; 9196 9197 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data); 9198 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL); 9199 if (ret != HCMD_SUCCESS) { 9200 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n", 9201 data, ret); 9202 return -EINVAL; 9203 } 9204 return 0; 9205 } 9206 9207 /* 9208 * Send an idle SMA message. 9209 * 9210 * Returns 0 on success, -EINVAL on error 9211 */ 9212 int send_idle_sma(struct hfi1_devdata *dd, u64 message) 9213 { 9214 u64 data; 9215 9216 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) | 9217 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT); 9218 return send_idle_message(dd, data); 9219 } 9220 9221 /* 9222 * Initialize the LCB then do a quick link up. This may or may not be 9223 * in loopback. 9224 * 9225 * return 0 on success, -errno on error 9226 */ 9227 static int do_quick_linkup(struct hfi1_devdata *dd) 9228 { 9229 int ret; 9230 9231 lcb_shutdown(dd, 0); 9232 9233 if (loopback) { 9234 /* LCB_CFG_LOOPBACK.VAL = 2 */ 9235 /* LCB_CFG_LANE_WIDTH.VAL = 0 */ 9236 write_csr(dd, DC_LCB_CFG_LOOPBACK, 9237 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT); 9238 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 9239 } 9240 9241 /* start the LCBs */ 9242 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */ 9243 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 9244 9245 /* simulator only loopback steps */ 9246 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 9247 /* LCB_CFG_RUN.EN = 1 */ 9248 write_csr(dd, DC_LCB_CFG_RUN, 9249 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 9250 9251 ret = wait_link_transfer_active(dd, 10); 9252 if (ret) 9253 return ret; 9254 9255 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 9256 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT); 9257 } 9258 9259 if (!loopback) { 9260 /* 9261 * When doing quick linkup and not in loopback, both 9262 * sides must be done with LCB set-up before either 9263 * starts the quick linkup. Put a delay here so that 9264 * both sides can be started and have a chance to be 9265 * done with LCB set up before resuming. 9266 */ 9267 dd_dev_err(dd, 9268 "Pausing for peer to be finished with LCB set up\n"); 9269 msleep(5000); 9270 dd_dev_err(dd, "Continuing with quick linkup\n"); 9271 } 9272 9273 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 9274 set_8051_lcb_access(dd); 9275 9276 /* 9277 * State "quick" LinkUp request sets the physical link state to 9278 * LinkUp without a verify capability sequence. 9279 * This state is in simulator v37 and later. 9280 */ 9281 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP); 9282 if (ret != HCMD_SUCCESS) { 9283 dd_dev_err(dd, 9284 "%s: set physical link state to quick LinkUp failed with return %d\n", 9285 __func__, ret); 9286 9287 set_host_lcb_access(dd); 9288 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 9289 9290 if (ret >= 0) 9291 ret = -EINVAL; 9292 return ret; 9293 } 9294 9295 return 0; /* success */ 9296 } 9297 9298 /* 9299 * Do all special steps to set up loopback. 9300 */ 9301 static int init_loopback(struct hfi1_devdata *dd) 9302 { 9303 dd_dev_info(dd, "Entering loopback mode\n"); 9304 9305 /* all loopbacks should disable self GUID check */ 9306 write_csr(dd, DC_DC8051_CFG_MODE, 9307 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); 9308 9309 /* 9310 * The simulator has only one loopback option - LCB. Switch 9311 * to that option, which includes quick link up. 9312 * 9313 * Accept all valid loopback values. 9314 */ 9315 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) && 9316 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB || 9317 loopback == LOOPBACK_CABLE)) { 9318 loopback = LOOPBACK_LCB; 9319 quick_linkup = 1; 9320 return 0; 9321 } 9322 9323 /* 9324 * SerDes loopback init sequence is handled in set_local_link_attributes 9325 */ 9326 if (loopback == LOOPBACK_SERDES) 9327 return 0; 9328 9329 /* LCB loopback - handled at poll time */ 9330 if (loopback == LOOPBACK_LCB) { 9331 quick_linkup = 1; /* LCB is always quick linkup */ 9332 9333 /* not supported in emulation due to emulation RTL changes */ 9334 if (dd->icode == ICODE_FPGA_EMULATION) { 9335 dd_dev_err(dd, 9336 "LCB loopback not supported in emulation\n"); 9337 return -EINVAL; 9338 } 9339 return 0; 9340 } 9341 9342 /* external cable loopback requires no extra steps */ 9343 if (loopback == LOOPBACK_CABLE) 9344 return 0; 9345 9346 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback); 9347 return -EINVAL; 9348 } 9349 9350 /* 9351 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits 9352 * used in the Verify Capability link width attribute. 9353 */ 9354 static u16 opa_to_vc_link_widths(u16 opa_widths) 9355 { 9356 int i; 9357 u16 result = 0; 9358 9359 static const struct link_bits { 9360 u16 from; 9361 u16 to; 9362 } opa_link_xlate[] = { 9363 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) }, 9364 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) }, 9365 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) }, 9366 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) }, 9367 }; 9368 9369 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) { 9370 if (opa_widths & opa_link_xlate[i].from) 9371 result |= opa_link_xlate[i].to; 9372 } 9373 return result; 9374 } 9375 9376 /* 9377 * Set link attributes before moving to polling. 9378 */ 9379 static int set_local_link_attributes(struct hfi1_pportdata *ppd) 9380 { 9381 struct hfi1_devdata *dd = ppd->dd; 9382 u8 enable_lane_tx; 9383 u8 tx_polarity_inversion; 9384 u8 rx_polarity_inversion; 9385 int ret; 9386 u32 misc_bits = 0; 9387 /* reset our fabric serdes to clear any lingering problems */ 9388 fabric_serdes_reset(dd); 9389 9390 /* set the local tx rate - need to read-modify-write */ 9391 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 9392 &rx_polarity_inversion, &ppd->local_tx_rate); 9393 if (ret) 9394 goto set_local_link_attributes_fail; 9395 9396 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 9397 /* set the tx rate to the fastest enabled */ 9398 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9399 ppd->local_tx_rate = 1; 9400 else 9401 ppd->local_tx_rate = 0; 9402 } else { 9403 /* set the tx rate to all enabled */ 9404 ppd->local_tx_rate = 0; 9405 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9406 ppd->local_tx_rate |= 2; 9407 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G) 9408 ppd->local_tx_rate |= 1; 9409 } 9410 9411 enable_lane_tx = 0xF; /* enable all four lanes */ 9412 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion, 9413 rx_polarity_inversion, ppd->local_tx_rate); 9414 if (ret != HCMD_SUCCESS) 9415 goto set_local_link_attributes_fail; 9416 9417 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION); 9418 if (ret != HCMD_SUCCESS) { 9419 dd_dev_err(dd, 9420 "Failed to set host interface version, return 0x%x\n", 9421 ret); 9422 goto set_local_link_attributes_fail; 9423 } 9424 9425 /* 9426 * DC supports continuous updates. 9427 */ 9428 ret = write_vc_local_phy(dd, 9429 0 /* no power management */, 9430 1 /* continuous updates */); 9431 if (ret != HCMD_SUCCESS) 9432 goto set_local_link_attributes_fail; 9433 9434 /* z=1 in the next call: AU of 0 is not supported by the hardware */ 9435 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init, 9436 ppd->port_crc_mode_enabled); 9437 if (ret != HCMD_SUCCESS) 9438 goto set_local_link_attributes_fail; 9439 9440 /* 9441 * SerDes loopback init sequence requires 9442 * setting bit 0 of MISC_CONFIG_BITS 9443 */ 9444 if (loopback == LOOPBACK_SERDES) 9445 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT; 9446 9447 /* 9448 * An external device configuration request is used to reset the LCB 9449 * to retry to obtain operational lanes when the first attempt is 9450 * unsuccesful. 9451 */ 9452 if (dd->dc8051_ver >= dc8051_ver(1, 25, 0)) 9453 misc_bits |= 1 << EXT_CFG_LCB_RESET_SUPPORTED_SHIFT; 9454 9455 ret = write_vc_local_link_mode(dd, misc_bits, 0, 9456 opa_to_vc_link_widths( 9457 ppd->link_width_enabled)); 9458 if (ret != HCMD_SUCCESS) 9459 goto set_local_link_attributes_fail; 9460 9461 /* let peer know who we are */ 9462 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev); 9463 if (ret == HCMD_SUCCESS) 9464 return 0; 9465 9466 set_local_link_attributes_fail: 9467 dd_dev_err(dd, 9468 "Failed to set local link attributes, return 0x%x\n", 9469 ret); 9470 return ret; 9471 } 9472 9473 /* 9474 * Call this to start the link. 9475 * Do not do anything if the link is disabled. 9476 * Returns 0 if link is disabled, moved to polling, or the driver is not ready. 9477 */ 9478 int start_link(struct hfi1_pportdata *ppd) 9479 { 9480 /* 9481 * Tune the SerDes to a ballpark setting for optimal signal and bit 9482 * error rate. Needs to be done before starting the link. 9483 */ 9484 tune_serdes(ppd); 9485 9486 if (!ppd->driver_link_ready) { 9487 dd_dev_info(ppd->dd, 9488 "%s: stopping link start because driver is not ready\n", 9489 __func__); 9490 return 0; 9491 } 9492 9493 /* 9494 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the 9495 * pkey table can be configured properly if the HFI unit is connected 9496 * to switch port with MgmtAllowed=NO 9497 */ 9498 clear_full_mgmt_pkey(ppd); 9499 9500 return set_link_state(ppd, HLS_DN_POLL); 9501 } 9502 9503 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd) 9504 { 9505 struct hfi1_devdata *dd = ppd->dd; 9506 u64 mask; 9507 unsigned long timeout; 9508 9509 /* 9510 * Some QSFP cables have a quirk that asserts the IntN line as a side 9511 * effect of power up on plug-in. We ignore this false positive 9512 * interrupt until the module has finished powering up by waiting for 9513 * a minimum timeout of the module inrush initialization time of 9514 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the 9515 * module have stabilized. 9516 */ 9517 msleep(500); 9518 9519 /* 9520 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1) 9521 */ 9522 timeout = jiffies + msecs_to_jiffies(2000); 9523 while (1) { 9524 mask = read_csr(dd, dd->hfi1_id ? 9525 ASIC_QSFP2_IN : ASIC_QSFP1_IN); 9526 if (!(mask & QSFP_HFI0_INT_N)) 9527 break; 9528 if (time_after(jiffies, timeout)) { 9529 dd_dev_info(dd, "%s: No IntN detected, reset complete\n", 9530 __func__); 9531 break; 9532 } 9533 udelay(2); 9534 } 9535 } 9536 9537 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable) 9538 { 9539 struct hfi1_devdata *dd = ppd->dd; 9540 u64 mask; 9541 9542 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); 9543 if (enable) { 9544 /* 9545 * Clear the status register to avoid an immediate interrupt 9546 * when we re-enable the IntN pin 9547 */ 9548 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9549 QSFP_HFI0_INT_N); 9550 mask |= (u64)QSFP_HFI0_INT_N; 9551 } else { 9552 mask &= ~(u64)QSFP_HFI0_INT_N; 9553 } 9554 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); 9555 } 9556 9557 int reset_qsfp(struct hfi1_pportdata *ppd) 9558 { 9559 struct hfi1_devdata *dd = ppd->dd; 9560 u64 mask, qsfp_mask; 9561 9562 /* Disable INT_N from triggering QSFP interrupts */ 9563 set_qsfp_int_n(ppd, 0); 9564 9565 /* Reset the QSFP */ 9566 mask = (u64)QSFP_HFI0_RESET_N; 9567 9568 qsfp_mask = read_csr(dd, 9569 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT); 9570 qsfp_mask &= ~mask; 9571 write_csr(dd, 9572 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9573 9574 udelay(10); 9575 9576 qsfp_mask |= mask; 9577 write_csr(dd, 9578 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9579 9580 wait_for_qsfp_init(ppd); 9581 9582 /* 9583 * Allow INT_N to trigger the QSFP interrupt to watch 9584 * for alarms and warnings 9585 */ 9586 set_qsfp_int_n(ppd, 1); 9587 9588 /* 9589 * After the reset, AOC transmitters are enabled by default. They need 9590 * to be turned off to complete the QSFP setup before they can be 9591 * enabled again. 9592 */ 9593 return set_qsfp_tx(ppd, 0); 9594 } 9595 9596 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd, 9597 u8 *qsfp_interrupt_status) 9598 { 9599 struct hfi1_devdata *dd = ppd->dd; 9600 9601 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) || 9602 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING)) 9603 dd_dev_err(dd, "%s: QSFP cable temperature too high\n", 9604 __func__); 9605 9606 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) || 9607 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING)) 9608 dd_dev_err(dd, "%s: QSFP cable temperature too low\n", 9609 __func__); 9610 9611 /* 9612 * The remaining alarms/warnings don't matter if the link is down. 9613 */ 9614 if (ppd->host_link_state & HLS_DOWN) 9615 return 0; 9616 9617 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) || 9618 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING)) 9619 dd_dev_err(dd, "%s: QSFP supply voltage too high\n", 9620 __func__); 9621 9622 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) || 9623 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING)) 9624 dd_dev_err(dd, "%s: QSFP supply voltage too low\n", 9625 __func__); 9626 9627 /* Byte 2 is vendor specific */ 9628 9629 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) || 9630 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING)) 9631 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n", 9632 __func__); 9633 9634 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) || 9635 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING)) 9636 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n", 9637 __func__); 9638 9639 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) || 9640 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING)) 9641 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n", 9642 __func__); 9643 9644 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) || 9645 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING)) 9646 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n", 9647 __func__); 9648 9649 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) || 9650 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING)) 9651 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n", 9652 __func__); 9653 9654 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) || 9655 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING)) 9656 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n", 9657 __func__); 9658 9659 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) || 9660 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING)) 9661 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n", 9662 __func__); 9663 9664 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) || 9665 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING)) 9666 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n", 9667 __func__); 9668 9669 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) || 9670 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING)) 9671 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n", 9672 __func__); 9673 9674 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) || 9675 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING)) 9676 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n", 9677 __func__); 9678 9679 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) || 9680 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING)) 9681 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n", 9682 __func__); 9683 9684 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) || 9685 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING)) 9686 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n", 9687 __func__); 9688 9689 /* Bytes 9-10 and 11-12 are reserved */ 9690 /* Bytes 13-15 are vendor specific */ 9691 9692 return 0; 9693 } 9694 9695 /* This routine will only be scheduled if the QSFP module present is asserted */ 9696 void qsfp_event(struct work_struct *work) 9697 { 9698 struct qsfp_data *qd; 9699 struct hfi1_pportdata *ppd; 9700 struct hfi1_devdata *dd; 9701 9702 qd = container_of(work, struct qsfp_data, qsfp_work); 9703 ppd = qd->ppd; 9704 dd = ppd->dd; 9705 9706 /* Sanity check */ 9707 if (!qsfp_mod_present(ppd)) 9708 return; 9709 9710 if (ppd->host_link_state == HLS_DN_DISABLE) { 9711 dd_dev_info(ppd->dd, 9712 "%s: stopping link start because link is disabled\n", 9713 __func__); 9714 return; 9715 } 9716 9717 /* 9718 * Turn DC back on after cable has been re-inserted. Up until 9719 * now, the DC has been in reset to save power. 9720 */ 9721 dc_start(dd); 9722 9723 if (qd->cache_refresh_required) { 9724 set_qsfp_int_n(ppd, 0); 9725 9726 wait_for_qsfp_init(ppd); 9727 9728 /* 9729 * Allow INT_N to trigger the QSFP interrupt to watch 9730 * for alarms and warnings 9731 */ 9732 set_qsfp_int_n(ppd, 1); 9733 9734 start_link(ppd); 9735 } 9736 9737 if (qd->check_interrupt_flags) { 9738 u8 qsfp_interrupt_status[16] = {0,}; 9739 9740 if (one_qsfp_read(ppd, dd->hfi1_id, 6, 9741 &qsfp_interrupt_status[0], 16) != 16) { 9742 dd_dev_info(dd, 9743 "%s: Failed to read status of QSFP module\n", 9744 __func__); 9745 } else { 9746 unsigned long flags; 9747 9748 handle_qsfp_error_conditions( 9749 ppd, qsfp_interrupt_status); 9750 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 9751 ppd->qsfp_info.check_interrupt_flags = 0; 9752 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 9753 flags); 9754 } 9755 } 9756 } 9757 9758 void init_qsfp_int(struct hfi1_devdata *dd) 9759 { 9760 struct hfi1_pportdata *ppd = dd->pport; 9761 u64 qsfp_mask; 9762 9763 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 9764 /* Clear current status to avoid spurious interrupts */ 9765 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9766 qsfp_mask); 9767 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, 9768 qsfp_mask); 9769 9770 set_qsfp_int_n(ppd, 0); 9771 9772 /* Handle active low nature of INT_N and MODPRST_N pins */ 9773 if (qsfp_mod_present(ppd)) 9774 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N; 9775 write_csr(dd, 9776 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT, 9777 qsfp_mask); 9778 9779 /* Enable the appropriate QSFP IRQ source */ 9780 if (!dd->hfi1_id) 9781 set_intr_bits(dd, QSFP1_INT, QSFP1_INT, true); 9782 else 9783 set_intr_bits(dd, QSFP2_INT, QSFP2_INT, true); 9784 } 9785 9786 /* 9787 * Do a one-time initialize of the LCB block. 9788 */ 9789 static void init_lcb(struct hfi1_devdata *dd) 9790 { 9791 /* simulator does not correctly handle LCB cclk loopback, skip */ 9792 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 9793 return; 9794 9795 /* the DC has been reset earlier in the driver load */ 9796 9797 /* set LCB for cclk loopback on the port */ 9798 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); 9799 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); 9800 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); 9801 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 9802 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); 9803 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); 9804 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); 9805 } 9806 9807 /* 9808 * Perform a test read on the QSFP. Return 0 on success, -ERRNO 9809 * on error. 9810 */ 9811 static int test_qsfp_read(struct hfi1_pportdata *ppd) 9812 { 9813 int ret; 9814 u8 status; 9815 9816 /* 9817 * Report success if not a QSFP or, if it is a QSFP, but the cable is 9818 * not present 9819 */ 9820 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd)) 9821 return 0; 9822 9823 /* read byte 2, the status byte */ 9824 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1); 9825 if (ret < 0) 9826 return ret; 9827 if (ret != 1) 9828 return -EIO; 9829 9830 return 0; /* success */ 9831 } 9832 9833 /* 9834 * Values for QSFP retry. 9835 * 9836 * Give up after 10s (20 x 500ms). The overall timeout was empirically 9837 * arrived at from experience on a large cluster. 9838 */ 9839 #define MAX_QSFP_RETRIES 20 9840 #define QSFP_RETRY_WAIT 500 /* msec */ 9841 9842 /* 9843 * Try a QSFP read. If it fails, schedule a retry for later. 9844 * Called on first link activation after driver load. 9845 */ 9846 static void try_start_link(struct hfi1_pportdata *ppd) 9847 { 9848 if (test_qsfp_read(ppd)) { 9849 /* read failed */ 9850 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) { 9851 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n"); 9852 return; 9853 } 9854 dd_dev_info(ppd->dd, 9855 "QSFP not responding, waiting and retrying %d\n", 9856 (int)ppd->qsfp_retry_count); 9857 ppd->qsfp_retry_count++; 9858 queue_delayed_work(ppd->link_wq, &ppd->start_link_work, 9859 msecs_to_jiffies(QSFP_RETRY_WAIT)); 9860 return; 9861 } 9862 ppd->qsfp_retry_count = 0; 9863 9864 start_link(ppd); 9865 } 9866 9867 /* 9868 * Workqueue function to start the link after a delay. 9869 */ 9870 void handle_start_link(struct work_struct *work) 9871 { 9872 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 9873 start_link_work.work); 9874 try_start_link(ppd); 9875 } 9876 9877 int bringup_serdes(struct hfi1_pportdata *ppd) 9878 { 9879 struct hfi1_devdata *dd = ppd->dd; 9880 u64 guid; 9881 int ret; 9882 9883 if (HFI1_CAP_IS_KSET(EXTENDED_PSN)) 9884 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK); 9885 9886 guid = ppd->guids[HFI1_PORT_GUID_INDEX]; 9887 if (!guid) { 9888 if (dd->base_guid) 9889 guid = dd->base_guid + ppd->port - 1; 9890 ppd->guids[HFI1_PORT_GUID_INDEX] = guid; 9891 } 9892 9893 /* Set linkinit_reason on power up per OPA spec */ 9894 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP; 9895 9896 /* one-time init of the LCB */ 9897 init_lcb(dd); 9898 9899 if (loopback) { 9900 ret = init_loopback(dd); 9901 if (ret < 0) 9902 return ret; 9903 } 9904 9905 get_port_type(ppd); 9906 if (ppd->port_type == PORT_TYPE_QSFP) { 9907 set_qsfp_int_n(ppd, 0); 9908 wait_for_qsfp_init(ppd); 9909 set_qsfp_int_n(ppd, 1); 9910 } 9911 9912 try_start_link(ppd); 9913 return 0; 9914 } 9915 9916 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd) 9917 { 9918 struct hfi1_devdata *dd = ppd->dd; 9919 9920 /* 9921 * Shut down the link and keep it down. First turn off that the 9922 * driver wants to allow the link to be up (driver_link_ready). 9923 * Then make sure the link is not automatically restarted 9924 * (link_enabled). Cancel any pending restart. And finally 9925 * go offline. 9926 */ 9927 ppd->driver_link_ready = 0; 9928 ppd->link_enabled = 0; 9929 9930 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */ 9931 flush_delayed_work(&ppd->start_link_work); 9932 cancel_delayed_work_sync(&ppd->start_link_work); 9933 9934 ppd->offline_disabled_reason = 9935 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT); 9936 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0, 9937 OPA_LINKDOWN_REASON_REBOOT); 9938 set_link_state(ppd, HLS_DN_OFFLINE); 9939 9940 /* disable the port */ 9941 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 9942 cancel_work_sync(&ppd->freeze_work); 9943 } 9944 9945 static inline int init_cpu_counters(struct hfi1_devdata *dd) 9946 { 9947 struct hfi1_pportdata *ppd; 9948 int i; 9949 9950 ppd = (struct hfi1_pportdata *)(dd + 1); 9951 for (i = 0; i < dd->num_pports; i++, ppd++) { 9952 ppd->ibport_data.rvp.rc_acks = NULL; 9953 ppd->ibport_data.rvp.rc_qacks = NULL; 9954 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64); 9955 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64); 9956 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64); 9957 if (!ppd->ibport_data.rvp.rc_acks || 9958 !ppd->ibport_data.rvp.rc_delayed_comp || 9959 !ppd->ibport_data.rvp.rc_qacks) 9960 return -ENOMEM; 9961 } 9962 9963 return 0; 9964 } 9965 9966 /* 9967 * index is the index into the receive array 9968 */ 9969 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, 9970 u32 type, unsigned long pa, u16 order) 9971 { 9972 u64 reg; 9973 9974 if (!(dd->flags & HFI1_PRESENT)) 9975 goto done; 9976 9977 if (type == PT_INVALID || type == PT_INVALID_FLUSH) { 9978 pa = 0; 9979 order = 0; 9980 } else if (type > PT_INVALID) { 9981 dd_dev_err(dd, 9982 "unexpected receive array type %u for index %u, not handled\n", 9983 type, index); 9984 goto done; 9985 } 9986 trace_hfi1_put_tid(dd, index, type, pa, order); 9987 9988 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */ 9989 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK 9990 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT 9991 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK) 9992 << RCV_ARRAY_RT_ADDR_SHIFT; 9993 trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg); 9994 writeq(reg, dd->rcvarray_wc + (index * 8)); 9995 9996 if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3) 9997 /* 9998 * Eager entries are written and flushed 9999 * 10000 * Expected entries are flushed every 4 writes 10001 */ 10002 flush_wc(); 10003 done: 10004 return; 10005 } 10006 10007 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd) 10008 { 10009 struct hfi1_devdata *dd = rcd->dd; 10010 u32 i; 10011 10012 /* this could be optimized */ 10013 for (i = rcd->eager_base; i < rcd->eager_base + 10014 rcd->egrbufs.alloced; i++) 10015 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 10016 10017 for (i = rcd->expected_base; 10018 i < rcd->expected_base + rcd->expected_count; i++) 10019 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 10020 } 10021 10022 static const char * const ib_cfg_name_strings[] = { 10023 "HFI1_IB_CFG_LIDLMC", 10024 "HFI1_IB_CFG_LWID_DG_ENB", 10025 "HFI1_IB_CFG_LWID_ENB", 10026 "HFI1_IB_CFG_LWID", 10027 "HFI1_IB_CFG_SPD_ENB", 10028 "HFI1_IB_CFG_SPD", 10029 "HFI1_IB_CFG_RXPOL_ENB", 10030 "HFI1_IB_CFG_LREV_ENB", 10031 "HFI1_IB_CFG_LINKLATENCY", 10032 "HFI1_IB_CFG_HRTBT", 10033 "HFI1_IB_CFG_OP_VLS", 10034 "HFI1_IB_CFG_VL_HIGH_CAP", 10035 "HFI1_IB_CFG_VL_LOW_CAP", 10036 "HFI1_IB_CFG_OVERRUN_THRESH", 10037 "HFI1_IB_CFG_PHYERR_THRESH", 10038 "HFI1_IB_CFG_LINKDEFAULT", 10039 "HFI1_IB_CFG_PKEYS", 10040 "HFI1_IB_CFG_MTU", 10041 "HFI1_IB_CFG_LSTATE", 10042 "HFI1_IB_CFG_VL_HIGH_LIMIT", 10043 "HFI1_IB_CFG_PMA_TICKS", 10044 "HFI1_IB_CFG_PORT" 10045 }; 10046 10047 static const char *ib_cfg_name(int which) 10048 { 10049 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings)) 10050 return "invalid"; 10051 return ib_cfg_name_strings[which]; 10052 } 10053 10054 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which) 10055 { 10056 struct hfi1_devdata *dd = ppd->dd; 10057 int val = 0; 10058 10059 switch (which) { 10060 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */ 10061 val = ppd->link_width_enabled; 10062 break; 10063 case HFI1_IB_CFG_LWID: /* currently active Link-width */ 10064 val = ppd->link_width_active; 10065 break; 10066 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 10067 val = ppd->link_speed_enabled; 10068 break; 10069 case HFI1_IB_CFG_SPD: /* current Link speed */ 10070 val = ppd->link_speed_active; 10071 break; 10072 10073 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */ 10074 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */ 10075 case HFI1_IB_CFG_LINKLATENCY: 10076 goto unimplemented; 10077 10078 case HFI1_IB_CFG_OP_VLS: 10079 val = ppd->actual_vls_operational; 10080 break; 10081 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */ 10082 val = VL_ARB_HIGH_PRIO_TABLE_SIZE; 10083 break; 10084 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */ 10085 val = VL_ARB_LOW_PRIO_TABLE_SIZE; 10086 break; 10087 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 10088 val = ppd->overrun_threshold; 10089 break; 10090 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 10091 val = ppd->phy_error_threshold; 10092 break; 10093 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 10094 val = HLS_DEFAULT; 10095 break; 10096 10097 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */ 10098 case HFI1_IB_CFG_PMA_TICKS: 10099 default: 10100 unimplemented: 10101 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 10102 dd_dev_info( 10103 dd, 10104 "%s: which %s: not implemented\n", 10105 __func__, 10106 ib_cfg_name(which)); 10107 break; 10108 } 10109 10110 return val; 10111 } 10112 10113 /* 10114 * The largest MAD packet size. 10115 */ 10116 #define MAX_MAD_PACKET 2048 10117 10118 /* 10119 * Return the maximum header bytes that can go on the _wire_ 10120 * for this device. This count includes the ICRC which is 10121 * not part of the packet held in memory but it is appended 10122 * by the HW. 10123 * This is dependent on the device's receive header entry size. 10124 * HFI allows this to be set per-receive context, but the 10125 * driver presently enforces a global value. 10126 */ 10127 u32 lrh_max_header_bytes(struct hfi1_devdata *dd) 10128 { 10129 /* 10130 * The maximum non-payload (MTU) bytes in LRH.PktLen are 10131 * the Receive Header Entry Size minus the PBC (or RHF) size 10132 * plus one DW for the ICRC appended by HW. 10133 * 10134 * dd->rcd[0].rcvhdrqentsize is in DW. 10135 * We use rcd[0] as all context will have the same value. Also, 10136 * the first kernel context would have been allocated by now so 10137 * we are guaranteed a valid value. 10138 */ 10139 return (get_hdrqentsize(dd->rcd[0]) - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2; 10140 } 10141 10142 /* 10143 * Set Send Length 10144 * @ppd - per port data 10145 * 10146 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck* 10147 * registers compare against LRH.PktLen, so use the max bytes included 10148 * in the LRH. 10149 * 10150 * This routine changes all VL values except VL15, which it maintains at 10151 * the same value. 10152 */ 10153 static void set_send_length(struct hfi1_pportdata *ppd) 10154 { 10155 struct hfi1_devdata *dd = ppd->dd; 10156 u32 max_hb = lrh_max_header_bytes(dd), dcmtu; 10157 u32 maxvlmtu = dd->vld[15].mtu; 10158 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2) 10159 & SEND_LEN_CHECK1_LEN_VL15_MASK) << 10160 SEND_LEN_CHECK1_LEN_VL15_SHIFT; 10161 int i, j; 10162 u32 thres; 10163 10164 for (i = 0; i < ppd->vls_supported; i++) { 10165 if (dd->vld[i].mtu > maxvlmtu) 10166 maxvlmtu = dd->vld[i].mtu; 10167 if (i <= 3) 10168 len1 |= (((dd->vld[i].mtu + max_hb) >> 2) 10169 & SEND_LEN_CHECK0_LEN_VL0_MASK) << 10170 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT); 10171 else 10172 len2 |= (((dd->vld[i].mtu + max_hb) >> 2) 10173 & SEND_LEN_CHECK1_LEN_VL4_MASK) << 10174 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT); 10175 } 10176 write_csr(dd, SEND_LEN_CHECK0, len1); 10177 write_csr(dd, SEND_LEN_CHECK1, len2); 10178 /* adjust kernel credit return thresholds based on new MTUs */ 10179 /* all kernel receive contexts have the same hdrqentsize */ 10180 for (i = 0; i < ppd->vls_supported; i++) { 10181 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50), 10182 sc_mtu_to_threshold(dd->vld[i].sc, 10183 dd->vld[i].mtu, 10184 get_hdrqentsize(dd->rcd[0]))); 10185 for (j = 0; j < INIT_SC_PER_VL; j++) 10186 sc_set_cr_threshold( 10187 pio_select_send_context_vl(dd, j, i), 10188 thres); 10189 } 10190 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50), 10191 sc_mtu_to_threshold(dd->vld[15].sc, 10192 dd->vld[15].mtu, 10193 dd->rcd[0]->rcvhdrqentsize)); 10194 sc_set_cr_threshold(dd->vld[15].sc, thres); 10195 10196 /* Adjust maximum MTU for the port in DC */ 10197 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 : 10198 (ilog2(maxvlmtu >> 8) + 1); 10199 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); 10200 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK; 10201 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) << 10202 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT; 10203 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); 10204 } 10205 10206 static void set_lidlmc(struct hfi1_pportdata *ppd) 10207 { 10208 int i; 10209 u64 sreg = 0; 10210 struct hfi1_devdata *dd = ppd->dd; 10211 u32 mask = ~((1U << ppd->lmc) - 1); 10212 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); 10213 u32 lid; 10214 10215 /* 10216 * Program 0 in CSR if port lid is extended. This prevents 10217 * 9B packets being sent out for large lids. 10218 */ 10219 lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid; 10220 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 10221 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK); 10222 c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK) 10223 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) | 10224 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK) 10225 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT); 10226 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); 10227 10228 /* 10229 * Iterate over all the send contexts and set their SLID check 10230 */ 10231 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) << 10232 SEND_CTXT_CHECK_SLID_MASK_SHIFT) | 10233 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) << 10234 SEND_CTXT_CHECK_SLID_VALUE_SHIFT); 10235 10236 for (i = 0; i < chip_send_contexts(dd); i++) { 10237 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x", 10238 i, (u32)sreg); 10239 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg); 10240 } 10241 10242 /* Now we have to do the same thing for the sdma engines */ 10243 sdma_update_lmc(dd, mask, lid); 10244 } 10245 10246 static const char *state_completed_string(u32 completed) 10247 { 10248 static const char * const state_completed[] = { 10249 "EstablishComm", 10250 "OptimizeEQ", 10251 "VerifyCap" 10252 }; 10253 10254 if (completed < ARRAY_SIZE(state_completed)) 10255 return state_completed[completed]; 10256 10257 return "unknown"; 10258 } 10259 10260 static const char all_lanes_dead_timeout_expired[] = 10261 "All lanes were inactive – was the interconnect media removed?"; 10262 static const char tx_out_of_policy[] = 10263 "Passing lanes on local port do not meet the local link width policy"; 10264 static const char no_state_complete[] = 10265 "State timeout occurred before link partner completed the state"; 10266 static const char * const state_complete_reasons[] = { 10267 [0x00] = "Reason unknown", 10268 [0x01] = "Link was halted by driver, refer to LinkDownReason", 10269 [0x02] = "Link partner reported failure", 10270 [0x10] = "Unable to achieve frame sync on any lane", 10271 [0x11] = 10272 "Unable to find a common bit rate with the link partner", 10273 [0x12] = 10274 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy", 10275 [0x13] = 10276 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy", 10277 [0x14] = no_state_complete, 10278 [0x15] = 10279 "State timeout occurred before link partner identified equalization presets", 10280 [0x16] = 10281 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy", 10282 [0x17] = tx_out_of_policy, 10283 [0x20] = all_lanes_dead_timeout_expired, 10284 [0x21] = 10285 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy", 10286 [0x22] = no_state_complete, 10287 [0x23] = 10288 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy", 10289 [0x24] = tx_out_of_policy, 10290 [0x30] = all_lanes_dead_timeout_expired, 10291 [0x31] = 10292 "State timeout occurred waiting for host to process received frames", 10293 [0x32] = no_state_complete, 10294 [0x33] = 10295 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy", 10296 [0x34] = tx_out_of_policy, 10297 [0x35] = "Negotiated link width is mutually exclusive", 10298 [0x36] = 10299 "Timed out before receiving verifycap frames in VerifyCap.Exchange", 10300 [0x37] = "Unable to resolve secure data exchange", 10301 }; 10302 10303 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd, 10304 u32 code) 10305 { 10306 const char *str = NULL; 10307 10308 if (code < ARRAY_SIZE(state_complete_reasons)) 10309 str = state_complete_reasons[code]; 10310 10311 if (str) 10312 return str; 10313 return "Reserved"; 10314 } 10315 10316 /* describe the given last state complete frame */ 10317 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame, 10318 const char *prefix) 10319 { 10320 struct hfi1_devdata *dd = ppd->dd; 10321 u32 success; 10322 u32 state; 10323 u32 reason; 10324 u32 lanes; 10325 10326 /* 10327 * Decode frame: 10328 * [ 0: 0] - success 10329 * [ 3: 1] - state 10330 * [ 7: 4] - next state timeout 10331 * [15: 8] - reason code 10332 * [31:16] - lanes 10333 */ 10334 success = frame & 0x1; 10335 state = (frame >> 1) & 0x7; 10336 reason = (frame >> 8) & 0xff; 10337 lanes = (frame >> 16) & 0xffff; 10338 10339 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n", 10340 prefix, frame); 10341 dd_dev_err(dd, " last reported state state: %s (0x%x)\n", 10342 state_completed_string(state), state); 10343 dd_dev_err(dd, " state successfully completed: %s\n", 10344 success ? "yes" : "no"); 10345 dd_dev_err(dd, " fail reason 0x%x: %s\n", 10346 reason, state_complete_reason_code_string(ppd, reason)); 10347 dd_dev_err(dd, " passing lane mask: 0x%x", lanes); 10348 } 10349 10350 /* 10351 * Read the last state complete frames and explain them. This routine 10352 * expects to be called if the link went down during link negotiation 10353 * and initialization (LNI). That is, anywhere between polling and link up. 10354 */ 10355 static void check_lni_states(struct hfi1_pportdata *ppd) 10356 { 10357 u32 last_local_state; 10358 u32 last_remote_state; 10359 10360 read_last_local_state(ppd->dd, &last_local_state); 10361 read_last_remote_state(ppd->dd, &last_remote_state); 10362 10363 /* 10364 * Don't report anything if there is nothing to report. A value of 10365 * 0 means the link was taken down while polling and there was no 10366 * training in-process. 10367 */ 10368 if (last_local_state == 0 && last_remote_state == 0) 10369 return; 10370 10371 decode_state_complete(ppd, last_local_state, "transmitted"); 10372 decode_state_complete(ppd, last_remote_state, "received"); 10373 } 10374 10375 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */ 10376 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms) 10377 { 10378 u64 reg; 10379 unsigned long timeout; 10380 10381 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */ 10382 timeout = jiffies + msecs_to_jiffies(wait_ms); 10383 while (1) { 10384 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); 10385 if (reg) 10386 break; 10387 if (time_after(jiffies, timeout)) { 10388 dd_dev_err(dd, 10389 "timeout waiting for LINK_TRANSFER_ACTIVE\n"); 10390 return -ETIMEDOUT; 10391 } 10392 udelay(2); 10393 } 10394 return 0; 10395 } 10396 10397 /* called when the logical link state is not down as it should be */ 10398 static void force_logical_link_state_down(struct hfi1_pportdata *ppd) 10399 { 10400 struct hfi1_devdata *dd = ppd->dd; 10401 10402 /* 10403 * Bring link up in LCB loopback 10404 */ 10405 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10406 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 10407 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 10408 10409 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 10410 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); 10411 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 10412 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); 10413 10414 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 10415 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); 10416 udelay(3); 10417 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); 10418 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 10419 10420 wait_link_transfer_active(dd, 100); 10421 10422 /* 10423 * Bring the link down again. 10424 */ 10425 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10426 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); 10427 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); 10428 10429 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n"); 10430 } 10431 10432 /* 10433 * Helper for set_link_state(). Do not call except from that routine. 10434 * Expects ppd->hls_mutex to be held. 10435 * 10436 * @rem_reason value to be sent to the neighbor 10437 * 10438 * LinkDownReasons only set if transition succeeds. 10439 */ 10440 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason) 10441 { 10442 struct hfi1_devdata *dd = ppd->dd; 10443 u32 previous_state; 10444 int offline_state_ret; 10445 int ret; 10446 10447 update_lcb_cache(dd); 10448 10449 previous_state = ppd->host_link_state; 10450 ppd->host_link_state = HLS_GOING_OFFLINE; 10451 10452 /* start offline transition */ 10453 ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE); 10454 10455 if (ret != HCMD_SUCCESS) { 10456 dd_dev_err(dd, 10457 "Failed to transition to Offline link state, return %d\n", 10458 ret); 10459 return -EINVAL; 10460 } 10461 if (ppd->offline_disabled_reason == 10462 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)) 10463 ppd->offline_disabled_reason = 10464 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 10465 10466 offline_state_ret = wait_phys_link_offline_substates(ppd, 10000); 10467 if (offline_state_ret < 0) 10468 return offline_state_ret; 10469 10470 /* Disabling AOC transmitters */ 10471 if (ppd->port_type == PORT_TYPE_QSFP && 10472 ppd->qsfp_info.limiting_active && 10473 qsfp_mod_present(ppd)) { 10474 int ret; 10475 10476 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT); 10477 if (ret == 0) { 10478 set_qsfp_tx(ppd, 0); 10479 release_chip_resource(dd, qsfp_resource(dd)); 10480 } else { 10481 /* not fatal, but should warn */ 10482 dd_dev_err(dd, 10483 "Unable to acquire lock to turn off QSFP TX\n"); 10484 } 10485 } 10486 10487 /* 10488 * Wait for the offline.Quiet transition if it hasn't happened yet. It 10489 * can take a while for the link to go down. 10490 */ 10491 if (offline_state_ret != PLS_OFFLINE_QUIET) { 10492 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000); 10493 if (ret < 0) 10494 return ret; 10495 } 10496 10497 /* 10498 * Now in charge of LCB - must be after the physical state is 10499 * offline.quiet and before host_link_state is changed. 10500 */ 10501 set_host_lcb_access(dd); 10502 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 10503 10504 /* make sure the logical state is also down */ 10505 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000); 10506 if (ret) 10507 force_logical_link_state_down(ppd); 10508 10509 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */ 10510 update_statusp(ppd, IB_PORT_DOWN); 10511 10512 /* 10513 * The LNI has a mandatory wait time after the physical state 10514 * moves to Offline.Quiet. The wait time may be different 10515 * depending on how the link went down. The 8051 firmware 10516 * will observe the needed wait time and only move to ready 10517 * when that is completed. The largest of the quiet timeouts 10518 * is 6s, so wait that long and then at least 0.5s more for 10519 * other transitions, and another 0.5s for a buffer. 10520 */ 10521 ret = wait_fm_ready(dd, 7000); 10522 if (ret) { 10523 dd_dev_err(dd, 10524 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n"); 10525 /* state is really offline, so make it so */ 10526 ppd->host_link_state = HLS_DN_OFFLINE; 10527 return ret; 10528 } 10529 10530 /* 10531 * The state is now offline and the 8051 is ready to accept host 10532 * requests. 10533 * - change our state 10534 * - notify others if we were previously in a linkup state 10535 */ 10536 ppd->host_link_state = HLS_DN_OFFLINE; 10537 if (previous_state & HLS_UP) { 10538 /* went down while link was up */ 10539 handle_linkup_change(dd, 0); 10540 } else if (previous_state 10541 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 10542 /* went down while attempting link up */ 10543 check_lni_states(ppd); 10544 10545 /* The QSFP doesn't need to be reset on LNI failure */ 10546 ppd->qsfp_info.reset_needed = 0; 10547 } 10548 10549 /* the active link width (downgrade) is 0 on link down */ 10550 ppd->link_width_active = 0; 10551 ppd->link_width_downgrade_tx_active = 0; 10552 ppd->link_width_downgrade_rx_active = 0; 10553 ppd->current_egress_rate = 0; 10554 return 0; 10555 } 10556 10557 /* return the link state name */ 10558 static const char *link_state_name(u32 state) 10559 { 10560 const char *name; 10561 int n = ilog2(state); 10562 static const char * const names[] = { 10563 [__HLS_UP_INIT_BP] = "INIT", 10564 [__HLS_UP_ARMED_BP] = "ARMED", 10565 [__HLS_UP_ACTIVE_BP] = "ACTIVE", 10566 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF", 10567 [__HLS_DN_POLL_BP] = "POLL", 10568 [__HLS_DN_DISABLE_BP] = "DISABLE", 10569 [__HLS_DN_OFFLINE_BP] = "OFFLINE", 10570 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP", 10571 [__HLS_GOING_UP_BP] = "GOING_UP", 10572 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE", 10573 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN" 10574 }; 10575 10576 name = n < ARRAY_SIZE(names) ? names[n] : NULL; 10577 return name ? name : "unknown"; 10578 } 10579 10580 /* return the link state reason name */ 10581 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state) 10582 { 10583 if (state == HLS_UP_INIT) { 10584 switch (ppd->linkinit_reason) { 10585 case OPA_LINKINIT_REASON_LINKUP: 10586 return "(LINKUP)"; 10587 case OPA_LINKINIT_REASON_FLAPPING: 10588 return "(FLAPPING)"; 10589 case OPA_LINKINIT_OUTSIDE_POLICY: 10590 return "(OUTSIDE_POLICY)"; 10591 case OPA_LINKINIT_QUARANTINED: 10592 return "(QUARANTINED)"; 10593 case OPA_LINKINIT_INSUFIC_CAPABILITY: 10594 return "(INSUFIC_CAPABILITY)"; 10595 default: 10596 break; 10597 } 10598 } 10599 return ""; 10600 } 10601 10602 /* 10603 * driver_pstate - convert the driver's notion of a port's 10604 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*). 10605 * Return -1 (converted to a u32) to indicate error. 10606 */ 10607 u32 driver_pstate(struct hfi1_pportdata *ppd) 10608 { 10609 switch (ppd->host_link_state) { 10610 case HLS_UP_INIT: 10611 case HLS_UP_ARMED: 10612 case HLS_UP_ACTIVE: 10613 return IB_PORTPHYSSTATE_LINKUP; 10614 case HLS_DN_POLL: 10615 return IB_PORTPHYSSTATE_POLLING; 10616 case HLS_DN_DISABLE: 10617 return IB_PORTPHYSSTATE_DISABLED; 10618 case HLS_DN_OFFLINE: 10619 return OPA_PORTPHYSSTATE_OFFLINE; 10620 case HLS_VERIFY_CAP: 10621 return IB_PORTPHYSSTATE_TRAINING; 10622 case HLS_GOING_UP: 10623 return IB_PORTPHYSSTATE_TRAINING; 10624 case HLS_GOING_OFFLINE: 10625 return OPA_PORTPHYSSTATE_OFFLINE; 10626 case HLS_LINK_COOLDOWN: 10627 return OPA_PORTPHYSSTATE_OFFLINE; 10628 case HLS_DN_DOWNDEF: 10629 default: 10630 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10631 ppd->host_link_state); 10632 return -1; 10633 } 10634 } 10635 10636 /* 10637 * driver_lstate - convert the driver's notion of a port's 10638 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1 10639 * (converted to a u32) to indicate error. 10640 */ 10641 u32 driver_lstate(struct hfi1_pportdata *ppd) 10642 { 10643 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN)) 10644 return IB_PORT_DOWN; 10645 10646 switch (ppd->host_link_state & HLS_UP) { 10647 case HLS_UP_INIT: 10648 return IB_PORT_INIT; 10649 case HLS_UP_ARMED: 10650 return IB_PORT_ARMED; 10651 case HLS_UP_ACTIVE: 10652 return IB_PORT_ACTIVE; 10653 default: 10654 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10655 ppd->host_link_state); 10656 return -1; 10657 } 10658 } 10659 10660 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 10661 u8 neigh_reason, u8 rem_reason) 10662 { 10663 if (ppd->local_link_down_reason.latest == 0 && 10664 ppd->neigh_link_down_reason.latest == 0) { 10665 ppd->local_link_down_reason.latest = lcl_reason; 10666 ppd->neigh_link_down_reason.latest = neigh_reason; 10667 ppd->remote_link_down_reason = rem_reason; 10668 } 10669 } 10670 10671 /** 10672 * data_vls_operational() - Verify if data VL BCT credits and MTU 10673 * are both set. 10674 * @ppd: pointer to hfi1_pportdata structure 10675 * 10676 * Return: true - Ok, false -otherwise. 10677 */ 10678 static inline bool data_vls_operational(struct hfi1_pportdata *ppd) 10679 { 10680 int i; 10681 u64 reg; 10682 10683 if (!ppd->actual_vls_operational) 10684 return false; 10685 10686 for (i = 0; i < ppd->vls_supported; i++) { 10687 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i)); 10688 if ((reg && !ppd->dd->vld[i].mtu) || 10689 (!reg && ppd->dd->vld[i].mtu)) 10690 return false; 10691 } 10692 10693 return true; 10694 } 10695 10696 /* 10697 * Change the physical and/or logical link state. 10698 * 10699 * Do not call this routine while inside an interrupt. It contains 10700 * calls to routines that can take multiple seconds to finish. 10701 * 10702 * Returns 0 on success, -errno on failure. 10703 */ 10704 int set_link_state(struct hfi1_pportdata *ppd, u32 state) 10705 { 10706 struct hfi1_devdata *dd = ppd->dd; 10707 struct ib_event event = {.device = NULL}; 10708 int ret1, ret = 0; 10709 int orig_new_state, poll_bounce; 10710 10711 mutex_lock(&ppd->hls_lock); 10712 10713 orig_new_state = state; 10714 if (state == HLS_DN_DOWNDEF) 10715 state = HLS_DEFAULT; 10716 10717 /* interpret poll -> poll as a link bounce */ 10718 poll_bounce = ppd->host_link_state == HLS_DN_POLL && 10719 state == HLS_DN_POLL; 10720 10721 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__, 10722 link_state_name(ppd->host_link_state), 10723 link_state_name(orig_new_state), 10724 poll_bounce ? "(bounce) " : "", 10725 link_state_reason_name(ppd, state)); 10726 10727 /* 10728 * If we're going to a (HLS_*) link state that implies the logical 10729 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then 10730 * reset is_sm_config_started to 0. 10731 */ 10732 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE))) 10733 ppd->is_sm_config_started = 0; 10734 10735 /* 10736 * Do nothing if the states match. Let a poll to poll link bounce 10737 * go through. 10738 */ 10739 if (ppd->host_link_state == state && !poll_bounce) 10740 goto done; 10741 10742 switch (state) { 10743 case HLS_UP_INIT: 10744 if (ppd->host_link_state == HLS_DN_POLL && 10745 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) { 10746 /* 10747 * Quick link up jumps from polling to here. 10748 * 10749 * Whether in normal or loopback mode, the 10750 * simulator jumps from polling to link up. 10751 * Accept that here. 10752 */ 10753 /* OK */ 10754 } else if (ppd->host_link_state != HLS_GOING_UP) { 10755 goto unexpected; 10756 } 10757 10758 /* 10759 * Wait for Link_Up physical state. 10760 * Physical and Logical states should already be 10761 * be transitioned to LinkUp and LinkInit respectively. 10762 */ 10763 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000); 10764 if (ret) { 10765 dd_dev_err(dd, 10766 "%s: physical state did not change to LINK-UP\n", 10767 __func__); 10768 break; 10769 } 10770 10771 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000); 10772 if (ret) { 10773 dd_dev_err(dd, 10774 "%s: logical state did not change to INIT\n", 10775 __func__); 10776 break; 10777 } 10778 10779 /* clear old transient LINKINIT_REASON code */ 10780 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR) 10781 ppd->linkinit_reason = 10782 OPA_LINKINIT_REASON_LINKUP; 10783 10784 /* enable the port */ 10785 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 10786 10787 handle_linkup_change(dd, 1); 10788 pio_kernel_linkup(dd); 10789 10790 /* 10791 * After link up, a new link width will have been set. 10792 * Update the xmit counters with regards to the new 10793 * link width. 10794 */ 10795 update_xmit_counters(ppd, ppd->link_width_active); 10796 10797 ppd->host_link_state = HLS_UP_INIT; 10798 update_statusp(ppd, IB_PORT_INIT); 10799 break; 10800 case HLS_UP_ARMED: 10801 if (ppd->host_link_state != HLS_UP_INIT) 10802 goto unexpected; 10803 10804 if (!data_vls_operational(ppd)) { 10805 dd_dev_err(dd, 10806 "%s: Invalid data VL credits or mtu\n", 10807 __func__); 10808 ret = -EINVAL; 10809 break; 10810 } 10811 10812 set_logical_state(dd, LSTATE_ARMED); 10813 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000); 10814 if (ret) { 10815 dd_dev_err(dd, 10816 "%s: logical state did not change to ARMED\n", 10817 __func__); 10818 break; 10819 } 10820 ppd->host_link_state = HLS_UP_ARMED; 10821 update_statusp(ppd, IB_PORT_ARMED); 10822 /* 10823 * The simulator does not currently implement SMA messages, 10824 * so neighbor_normal is not set. Set it here when we first 10825 * move to Armed. 10826 */ 10827 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 10828 ppd->neighbor_normal = 1; 10829 break; 10830 case HLS_UP_ACTIVE: 10831 if (ppd->host_link_state != HLS_UP_ARMED) 10832 goto unexpected; 10833 10834 set_logical_state(dd, LSTATE_ACTIVE); 10835 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000); 10836 if (ret) { 10837 dd_dev_err(dd, 10838 "%s: logical state did not change to ACTIVE\n", 10839 __func__); 10840 } else { 10841 /* tell all engines to go running */ 10842 sdma_all_running(dd); 10843 ppd->host_link_state = HLS_UP_ACTIVE; 10844 update_statusp(ppd, IB_PORT_ACTIVE); 10845 10846 /* Signal the IB layer that the port has went active */ 10847 event.device = &dd->verbs_dev.rdi.ibdev; 10848 event.element.port_num = ppd->port; 10849 event.event = IB_EVENT_PORT_ACTIVE; 10850 } 10851 break; 10852 case HLS_DN_POLL: 10853 if ((ppd->host_link_state == HLS_DN_DISABLE || 10854 ppd->host_link_state == HLS_DN_OFFLINE) && 10855 dd->dc_shutdown) 10856 dc_start(dd); 10857 /* Hand LED control to the DC */ 10858 write_csr(dd, DCC_CFG_LED_CNTRL, 0); 10859 10860 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10861 u8 tmp = ppd->link_enabled; 10862 10863 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10864 if (ret) { 10865 ppd->link_enabled = tmp; 10866 break; 10867 } 10868 ppd->remote_link_down_reason = 0; 10869 10870 if (ppd->driver_link_ready) 10871 ppd->link_enabled = 1; 10872 } 10873 10874 set_all_slowpath(ppd->dd); 10875 ret = set_local_link_attributes(ppd); 10876 if (ret) 10877 break; 10878 10879 ppd->port_error_action = 0; 10880 10881 if (quick_linkup) { 10882 /* quick linkup does not go into polling */ 10883 ret = do_quick_linkup(dd); 10884 } else { 10885 ret1 = set_physical_link_state(dd, PLS_POLLING); 10886 if (!ret1) 10887 ret1 = wait_phys_link_out_of_offline(ppd, 10888 3000); 10889 if (ret1 != HCMD_SUCCESS) { 10890 dd_dev_err(dd, 10891 "Failed to transition to Polling link state, return 0x%x\n", 10892 ret1); 10893 ret = -EINVAL; 10894 } 10895 } 10896 10897 /* 10898 * Change the host link state after requesting DC8051 to 10899 * change its physical state so that we can ignore any 10900 * interrupt with stale LNI(XX) error, which will not be 10901 * cleared until DC8051 transitions to Polling state. 10902 */ 10903 ppd->host_link_state = HLS_DN_POLL; 10904 ppd->offline_disabled_reason = 10905 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE); 10906 /* 10907 * If an error occurred above, go back to offline. The 10908 * caller may reschedule another attempt. 10909 */ 10910 if (ret) 10911 goto_offline(ppd, 0); 10912 else 10913 log_physical_state(ppd, PLS_POLLING); 10914 break; 10915 case HLS_DN_DISABLE: 10916 /* link is disabled */ 10917 ppd->link_enabled = 0; 10918 10919 /* allow any state to transition to disabled */ 10920 10921 /* must transition to offline first */ 10922 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10923 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10924 if (ret) 10925 break; 10926 ppd->remote_link_down_reason = 0; 10927 } 10928 10929 if (!dd->dc_shutdown) { 10930 ret1 = set_physical_link_state(dd, PLS_DISABLED); 10931 if (ret1 != HCMD_SUCCESS) { 10932 dd_dev_err(dd, 10933 "Failed to transition to Disabled link state, return 0x%x\n", 10934 ret1); 10935 ret = -EINVAL; 10936 break; 10937 } 10938 ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000); 10939 if (ret) { 10940 dd_dev_err(dd, 10941 "%s: physical state did not change to DISABLED\n", 10942 __func__); 10943 break; 10944 } 10945 dc_shutdown(dd); 10946 } 10947 ppd->host_link_state = HLS_DN_DISABLE; 10948 break; 10949 case HLS_DN_OFFLINE: 10950 if (ppd->host_link_state == HLS_DN_DISABLE) 10951 dc_start(dd); 10952 10953 /* allow any state to transition to offline */ 10954 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10955 if (!ret) 10956 ppd->remote_link_down_reason = 0; 10957 break; 10958 case HLS_VERIFY_CAP: 10959 if (ppd->host_link_state != HLS_DN_POLL) 10960 goto unexpected; 10961 ppd->host_link_state = HLS_VERIFY_CAP; 10962 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP); 10963 break; 10964 case HLS_GOING_UP: 10965 if (ppd->host_link_state != HLS_VERIFY_CAP) 10966 goto unexpected; 10967 10968 ret1 = set_physical_link_state(dd, PLS_LINKUP); 10969 if (ret1 != HCMD_SUCCESS) { 10970 dd_dev_err(dd, 10971 "Failed to transition to link up state, return 0x%x\n", 10972 ret1); 10973 ret = -EINVAL; 10974 break; 10975 } 10976 ppd->host_link_state = HLS_GOING_UP; 10977 break; 10978 10979 case HLS_GOING_OFFLINE: /* transient within goto_offline() */ 10980 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */ 10981 default: 10982 dd_dev_info(dd, "%s: state 0x%x: not supported\n", 10983 __func__, state); 10984 ret = -EINVAL; 10985 break; 10986 } 10987 10988 goto done; 10989 10990 unexpected: 10991 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n", 10992 __func__, link_state_name(ppd->host_link_state), 10993 link_state_name(state)); 10994 ret = -EINVAL; 10995 10996 done: 10997 mutex_unlock(&ppd->hls_lock); 10998 10999 if (event.device) 11000 ib_dispatch_event(&event); 11001 11002 return ret; 11003 } 11004 11005 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val) 11006 { 11007 u64 reg; 11008 int ret = 0; 11009 11010 switch (which) { 11011 case HFI1_IB_CFG_LIDLMC: 11012 set_lidlmc(ppd); 11013 break; 11014 case HFI1_IB_CFG_VL_HIGH_LIMIT: 11015 /* 11016 * The VL Arbitrator high limit is sent in units of 4k 11017 * bytes, while HFI stores it in units of 64 bytes. 11018 */ 11019 val *= 4096 / 64; 11020 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) 11021 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT; 11022 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); 11023 break; 11024 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 11025 /* HFI only supports POLL as the default link down state */ 11026 if (val != HLS_DN_POLL) 11027 ret = -EINVAL; 11028 break; 11029 case HFI1_IB_CFG_OP_VLS: 11030 if (ppd->vls_operational != val) { 11031 ppd->vls_operational = val; 11032 if (!ppd->port) 11033 ret = -EINVAL; 11034 } 11035 break; 11036 /* 11037 * For link width, link width downgrade, and speed enable, always AND 11038 * the setting with what is actually supported. This has two benefits. 11039 * First, enabled can't have unsupported values, no matter what the 11040 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean 11041 * "fill in with your supported value" have all the bits in the 11042 * field set, so simply ANDing with supported has the desired result. 11043 */ 11044 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */ 11045 ppd->link_width_enabled = val & ppd->link_width_supported; 11046 break; 11047 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */ 11048 ppd->link_width_downgrade_enabled = 11049 val & ppd->link_width_downgrade_supported; 11050 break; 11051 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 11052 ppd->link_speed_enabled = val & ppd->link_speed_supported; 11053 break; 11054 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 11055 /* 11056 * HFI does not follow IB specs, save this value 11057 * so we can report it, if asked. 11058 */ 11059 ppd->overrun_threshold = val; 11060 break; 11061 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 11062 /* 11063 * HFI does not follow IB specs, save this value 11064 * so we can report it, if asked. 11065 */ 11066 ppd->phy_error_threshold = val; 11067 break; 11068 11069 case HFI1_IB_CFG_MTU: 11070 set_send_length(ppd); 11071 break; 11072 11073 case HFI1_IB_CFG_PKEYS: 11074 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 11075 set_partition_keys(ppd); 11076 break; 11077 11078 default: 11079 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 11080 dd_dev_info(ppd->dd, 11081 "%s: which %s, val 0x%x: not implemented\n", 11082 __func__, ib_cfg_name(which), val); 11083 break; 11084 } 11085 return ret; 11086 } 11087 11088 /* begin functions related to vl arbitration table caching */ 11089 static void init_vl_arb_caches(struct hfi1_pportdata *ppd) 11090 { 11091 int i; 11092 11093 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 11094 VL_ARB_LOW_PRIO_TABLE_SIZE); 11095 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 11096 VL_ARB_HIGH_PRIO_TABLE_SIZE); 11097 11098 /* 11099 * Note that we always return values directly from the 11100 * 'vl_arb_cache' (and do no CSR reads) in response to a 11101 * 'Get(VLArbTable)'. This is obviously correct after a 11102 * 'Set(VLArbTable)', since the cache will then be up to 11103 * date. But it's also correct prior to any 'Set(VLArbTable)' 11104 * since then both the cache, and the relevant h/w registers 11105 * will be zeroed. 11106 */ 11107 11108 for (i = 0; i < MAX_PRIO_TABLE; i++) 11109 spin_lock_init(&ppd->vl_arb_cache[i].lock); 11110 } 11111 11112 /* 11113 * vl_arb_lock_cache 11114 * 11115 * All other vl_arb_* functions should be called only after locking 11116 * the cache. 11117 */ 11118 static inline struct vl_arb_cache * 11119 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx) 11120 { 11121 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE) 11122 return NULL; 11123 spin_lock(&ppd->vl_arb_cache[idx].lock); 11124 return &ppd->vl_arb_cache[idx]; 11125 } 11126 11127 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx) 11128 { 11129 spin_unlock(&ppd->vl_arb_cache[idx].lock); 11130 } 11131 11132 static void vl_arb_get_cache(struct vl_arb_cache *cache, 11133 struct ib_vl_weight_elem *vl) 11134 { 11135 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11136 } 11137 11138 static void vl_arb_set_cache(struct vl_arb_cache *cache, 11139 struct ib_vl_weight_elem *vl) 11140 { 11141 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11142 } 11143 11144 static int vl_arb_match_cache(struct vl_arb_cache *cache, 11145 struct ib_vl_weight_elem *vl) 11146 { 11147 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11148 } 11149 11150 /* end functions related to vl arbitration table caching */ 11151 11152 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target, 11153 u32 size, struct ib_vl_weight_elem *vl) 11154 { 11155 struct hfi1_devdata *dd = ppd->dd; 11156 u64 reg; 11157 unsigned int i, is_up = 0; 11158 int drain, ret = 0; 11159 11160 mutex_lock(&ppd->hls_lock); 11161 11162 if (ppd->host_link_state & HLS_UP) 11163 is_up = 1; 11164 11165 drain = !is_ax(dd) && is_up; 11166 11167 if (drain) 11168 /* 11169 * Before adjusting VL arbitration weights, empty per-VL 11170 * FIFOs, otherwise a packet whose VL weight is being 11171 * set to 0 could get stuck in a FIFO with no chance to 11172 * egress. 11173 */ 11174 ret = stop_drain_data_vls(dd); 11175 11176 if (ret) { 11177 dd_dev_err( 11178 dd, 11179 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n", 11180 __func__); 11181 goto err; 11182 } 11183 11184 for (i = 0; i < size; i++, vl++) { 11185 /* 11186 * NOTE: The low priority shift and mask are used here, but 11187 * they are the same for both the low and high registers. 11188 */ 11189 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK) 11190 << SEND_LOW_PRIORITY_LIST_VL_SHIFT) 11191 | (((u64)vl->weight 11192 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK) 11193 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT); 11194 write_csr(dd, target + (i * 8), reg); 11195 } 11196 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE); 11197 11198 if (drain) 11199 open_fill_data_vls(dd); /* reopen all VLs */ 11200 11201 err: 11202 mutex_unlock(&ppd->hls_lock); 11203 11204 return ret; 11205 } 11206 11207 /* 11208 * Read one credit merge VL register. 11209 */ 11210 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr, 11211 struct vl_limit *vll) 11212 { 11213 u64 reg = read_csr(dd, csr); 11214 11215 vll->dedicated = cpu_to_be16( 11216 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT) 11217 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK); 11218 vll->shared = cpu_to_be16( 11219 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT) 11220 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK); 11221 } 11222 11223 /* 11224 * Read the current credit merge limits. 11225 */ 11226 static int get_buffer_control(struct hfi1_devdata *dd, 11227 struct buffer_control *bc, u16 *overall_limit) 11228 { 11229 u64 reg; 11230 int i; 11231 11232 /* not all entries are filled in */ 11233 memset(bc, 0, sizeof(*bc)); 11234 11235 /* OPA and HFI have a 1-1 mapping */ 11236 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11237 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]); 11238 11239 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */ 11240 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]); 11241 11242 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11243 bc->overall_shared_limit = cpu_to_be16( 11244 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) 11245 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK); 11246 if (overall_limit) 11247 *overall_limit = (reg 11248 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) 11249 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK; 11250 return sizeof(struct buffer_control); 11251 } 11252 11253 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11254 { 11255 u64 reg; 11256 int i; 11257 11258 /* each register contains 16 SC->VLnt mappings, 4 bits each */ 11259 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); 11260 for (i = 0; i < sizeof(u64); i++) { 11261 u8 byte = *(((u8 *)®) + i); 11262 11263 dp->vlnt[2 * i] = byte & 0xf; 11264 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4; 11265 } 11266 11267 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); 11268 for (i = 0; i < sizeof(u64); i++) { 11269 u8 byte = *(((u8 *)®) + i); 11270 11271 dp->vlnt[16 + (2 * i)] = byte & 0xf; 11272 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4; 11273 } 11274 return sizeof(struct sc2vlnt); 11275 } 11276 11277 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems, 11278 struct ib_vl_weight_elem *vl) 11279 { 11280 unsigned int i; 11281 11282 for (i = 0; i < nelems; i++, vl++) { 11283 vl->vl = 0xf; 11284 vl->weight = 0; 11285 } 11286 } 11287 11288 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11289 { 11290 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, 11291 DC_SC_VL_VAL(15_0, 11292 0, dp->vlnt[0] & 0xf, 11293 1, dp->vlnt[1] & 0xf, 11294 2, dp->vlnt[2] & 0xf, 11295 3, dp->vlnt[3] & 0xf, 11296 4, dp->vlnt[4] & 0xf, 11297 5, dp->vlnt[5] & 0xf, 11298 6, dp->vlnt[6] & 0xf, 11299 7, dp->vlnt[7] & 0xf, 11300 8, dp->vlnt[8] & 0xf, 11301 9, dp->vlnt[9] & 0xf, 11302 10, dp->vlnt[10] & 0xf, 11303 11, dp->vlnt[11] & 0xf, 11304 12, dp->vlnt[12] & 0xf, 11305 13, dp->vlnt[13] & 0xf, 11306 14, dp->vlnt[14] & 0xf, 11307 15, dp->vlnt[15] & 0xf)); 11308 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, 11309 DC_SC_VL_VAL(31_16, 11310 16, dp->vlnt[16] & 0xf, 11311 17, dp->vlnt[17] & 0xf, 11312 18, dp->vlnt[18] & 0xf, 11313 19, dp->vlnt[19] & 0xf, 11314 20, dp->vlnt[20] & 0xf, 11315 21, dp->vlnt[21] & 0xf, 11316 22, dp->vlnt[22] & 0xf, 11317 23, dp->vlnt[23] & 0xf, 11318 24, dp->vlnt[24] & 0xf, 11319 25, dp->vlnt[25] & 0xf, 11320 26, dp->vlnt[26] & 0xf, 11321 27, dp->vlnt[27] & 0xf, 11322 28, dp->vlnt[28] & 0xf, 11323 29, dp->vlnt[29] & 0xf, 11324 30, dp->vlnt[30] & 0xf, 11325 31, dp->vlnt[31] & 0xf)); 11326 } 11327 11328 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what, 11329 u16 limit) 11330 { 11331 if (limit != 0) 11332 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n", 11333 what, (int)limit, idx); 11334 } 11335 11336 /* change only the shared limit portion of SendCmGLobalCredit */ 11337 static void set_global_shared(struct hfi1_devdata *dd, u16 limit) 11338 { 11339 u64 reg; 11340 11341 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11342 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK; 11343 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT; 11344 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11345 } 11346 11347 /* change only the total credit limit portion of SendCmGLobalCredit */ 11348 static void set_global_limit(struct hfi1_devdata *dd, u16 limit) 11349 { 11350 u64 reg; 11351 11352 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11353 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK; 11354 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 11355 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11356 } 11357 11358 /* set the given per-VL shared limit */ 11359 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit) 11360 { 11361 u64 reg; 11362 u32 addr; 11363 11364 if (vl < TXE_NUM_DATA_VL) 11365 addr = SEND_CM_CREDIT_VL + (8 * vl); 11366 else 11367 addr = SEND_CM_CREDIT_VL15; 11368 11369 reg = read_csr(dd, addr); 11370 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK; 11371 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT; 11372 write_csr(dd, addr, reg); 11373 } 11374 11375 /* set the given per-VL dedicated limit */ 11376 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit) 11377 { 11378 u64 reg; 11379 u32 addr; 11380 11381 if (vl < TXE_NUM_DATA_VL) 11382 addr = SEND_CM_CREDIT_VL + (8 * vl); 11383 else 11384 addr = SEND_CM_CREDIT_VL15; 11385 11386 reg = read_csr(dd, addr); 11387 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK; 11388 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT; 11389 write_csr(dd, addr, reg); 11390 } 11391 11392 /* spin until the given per-VL status mask bits clear */ 11393 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask, 11394 const char *which) 11395 { 11396 unsigned long timeout; 11397 u64 reg; 11398 11399 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT); 11400 while (1) { 11401 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; 11402 11403 if (reg == 0) 11404 return; /* success */ 11405 if (time_after(jiffies, timeout)) 11406 break; /* timed out */ 11407 udelay(1); 11408 } 11409 11410 dd_dev_err(dd, 11411 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n", 11412 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); 11413 /* 11414 * If this occurs, it is likely there was a credit loss on the link. 11415 * The only recovery from that is a link bounce. 11416 */ 11417 dd_dev_err(dd, 11418 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n"); 11419 } 11420 11421 /* 11422 * The number of credits on the VLs may be changed while everything 11423 * is "live", but the following algorithm must be followed due to 11424 * how the hardware is actually implemented. In particular, 11425 * Return_Credit_Status[] is the only correct status check. 11426 * 11427 * if (reducing Global_Shared_Credit_Limit or any shared limit changing) 11428 * set Global_Shared_Credit_Limit = 0 11429 * use_all_vl = 1 11430 * mask0 = all VLs that are changing either dedicated or shared limits 11431 * set Shared_Limit[mask0] = 0 11432 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0 11433 * if (changing any dedicated limit) 11434 * mask1 = all VLs that are lowering dedicated limits 11435 * lower Dedicated_Limit[mask1] 11436 * spin until Return_Credit_Status[mask1] == 0 11437 * raise Dedicated_Limits 11438 * raise Shared_Limits 11439 * raise Global_Shared_Credit_Limit 11440 * 11441 * lower = if the new limit is lower, set the limit to the new value 11442 * raise = if the new limit is higher than the current value (may be changed 11443 * earlier in the algorithm), set the new limit to the new value 11444 */ 11445 int set_buffer_control(struct hfi1_pportdata *ppd, 11446 struct buffer_control *new_bc) 11447 { 11448 struct hfi1_devdata *dd = ppd->dd; 11449 u64 changing_mask, ld_mask, stat_mask; 11450 int change_count; 11451 int i, use_all_mask; 11452 int this_shared_changing; 11453 int vl_count = 0, ret; 11454 /* 11455 * A0: add the variable any_shared_limit_changing below and in the 11456 * algorithm above. If removing A0 support, it can be removed. 11457 */ 11458 int any_shared_limit_changing; 11459 struct buffer_control cur_bc; 11460 u8 changing[OPA_MAX_VLS]; 11461 u8 lowering_dedicated[OPA_MAX_VLS]; 11462 u16 cur_total; 11463 u32 new_total = 0; 11464 const u64 all_mask = 11465 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK 11466 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK 11467 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK 11468 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK 11469 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK 11470 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK 11471 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK 11472 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK 11473 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK; 11474 11475 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15) 11476 #define NUM_USABLE_VLS 16 /* look at VL15 and less */ 11477 11478 /* find the new total credits, do sanity check on unused VLs */ 11479 for (i = 0; i < OPA_MAX_VLS; i++) { 11480 if (valid_vl(i)) { 11481 new_total += be16_to_cpu(new_bc->vl[i].dedicated); 11482 continue; 11483 } 11484 nonzero_msg(dd, i, "dedicated", 11485 be16_to_cpu(new_bc->vl[i].dedicated)); 11486 nonzero_msg(dd, i, "shared", 11487 be16_to_cpu(new_bc->vl[i].shared)); 11488 new_bc->vl[i].dedicated = 0; 11489 new_bc->vl[i].shared = 0; 11490 } 11491 new_total += be16_to_cpu(new_bc->overall_shared_limit); 11492 11493 /* fetch the current values */ 11494 get_buffer_control(dd, &cur_bc, &cur_total); 11495 11496 /* 11497 * Create the masks we will use. 11498 */ 11499 memset(changing, 0, sizeof(changing)); 11500 memset(lowering_dedicated, 0, sizeof(lowering_dedicated)); 11501 /* 11502 * NOTE: Assumes that the individual VL bits are adjacent and in 11503 * increasing order 11504 */ 11505 stat_mask = 11506 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK; 11507 changing_mask = 0; 11508 ld_mask = 0; 11509 change_count = 0; 11510 any_shared_limit_changing = 0; 11511 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) { 11512 if (!valid_vl(i)) 11513 continue; 11514 this_shared_changing = new_bc->vl[i].shared 11515 != cur_bc.vl[i].shared; 11516 if (this_shared_changing) 11517 any_shared_limit_changing = 1; 11518 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated || 11519 this_shared_changing) { 11520 changing[i] = 1; 11521 changing_mask |= stat_mask; 11522 change_count++; 11523 } 11524 if (be16_to_cpu(new_bc->vl[i].dedicated) < 11525 be16_to_cpu(cur_bc.vl[i].dedicated)) { 11526 lowering_dedicated[i] = 1; 11527 ld_mask |= stat_mask; 11528 } 11529 } 11530 11531 /* bracket the credit change with a total adjustment */ 11532 if (new_total > cur_total) 11533 set_global_limit(dd, new_total); 11534 11535 /* 11536 * Start the credit change algorithm. 11537 */ 11538 use_all_mask = 0; 11539 if ((be16_to_cpu(new_bc->overall_shared_limit) < 11540 be16_to_cpu(cur_bc.overall_shared_limit)) || 11541 (is_ax(dd) && any_shared_limit_changing)) { 11542 set_global_shared(dd, 0); 11543 cur_bc.overall_shared_limit = 0; 11544 use_all_mask = 1; 11545 } 11546 11547 for (i = 0; i < NUM_USABLE_VLS; i++) { 11548 if (!valid_vl(i)) 11549 continue; 11550 11551 if (changing[i]) { 11552 set_vl_shared(dd, i, 0); 11553 cur_bc.vl[i].shared = 0; 11554 } 11555 } 11556 11557 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask, 11558 "shared"); 11559 11560 if (change_count > 0) { 11561 for (i = 0; i < NUM_USABLE_VLS; i++) { 11562 if (!valid_vl(i)) 11563 continue; 11564 11565 if (lowering_dedicated[i]) { 11566 set_vl_dedicated(dd, i, 11567 be16_to_cpu(new_bc-> 11568 vl[i].dedicated)); 11569 cur_bc.vl[i].dedicated = 11570 new_bc->vl[i].dedicated; 11571 } 11572 } 11573 11574 wait_for_vl_status_clear(dd, ld_mask, "dedicated"); 11575 11576 /* now raise all dedicated that are going up */ 11577 for (i = 0; i < NUM_USABLE_VLS; i++) { 11578 if (!valid_vl(i)) 11579 continue; 11580 11581 if (be16_to_cpu(new_bc->vl[i].dedicated) > 11582 be16_to_cpu(cur_bc.vl[i].dedicated)) 11583 set_vl_dedicated(dd, i, 11584 be16_to_cpu(new_bc-> 11585 vl[i].dedicated)); 11586 } 11587 } 11588 11589 /* next raise all shared that are going up */ 11590 for (i = 0; i < NUM_USABLE_VLS; i++) { 11591 if (!valid_vl(i)) 11592 continue; 11593 11594 if (be16_to_cpu(new_bc->vl[i].shared) > 11595 be16_to_cpu(cur_bc.vl[i].shared)) 11596 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared)); 11597 } 11598 11599 /* finally raise the global shared */ 11600 if (be16_to_cpu(new_bc->overall_shared_limit) > 11601 be16_to_cpu(cur_bc.overall_shared_limit)) 11602 set_global_shared(dd, 11603 be16_to_cpu(new_bc->overall_shared_limit)); 11604 11605 /* bracket the credit change with a total adjustment */ 11606 if (new_total < cur_total) 11607 set_global_limit(dd, new_total); 11608 11609 /* 11610 * Determine the actual number of operational VLS using the number of 11611 * dedicated and shared credits for each VL. 11612 */ 11613 if (change_count > 0) { 11614 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11615 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 || 11616 be16_to_cpu(new_bc->vl[i].shared) > 0) 11617 vl_count++; 11618 ppd->actual_vls_operational = vl_count; 11619 ret = sdma_map_init(dd, ppd->port - 1, vl_count ? 11620 ppd->actual_vls_operational : 11621 ppd->vls_operational, 11622 NULL); 11623 if (ret == 0) 11624 ret = pio_map_init(dd, ppd->port - 1, vl_count ? 11625 ppd->actual_vls_operational : 11626 ppd->vls_operational, NULL); 11627 if (ret) 11628 return ret; 11629 } 11630 return 0; 11631 } 11632 11633 /* 11634 * Read the given fabric manager table. Return the size of the 11635 * table (in bytes) on success, and a negative error code on 11636 * failure. 11637 */ 11638 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t) 11639 11640 { 11641 int size; 11642 struct vl_arb_cache *vlc; 11643 11644 switch (which) { 11645 case FM_TBL_VL_HIGH_ARB: 11646 size = 256; 11647 /* 11648 * OPA specifies 128 elements (of 2 bytes each), though 11649 * HFI supports only 16 elements in h/w. 11650 */ 11651 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11652 vl_arb_get_cache(vlc, t); 11653 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11654 break; 11655 case FM_TBL_VL_LOW_ARB: 11656 size = 256; 11657 /* 11658 * OPA specifies 128 elements (of 2 bytes each), though 11659 * HFI supports only 16 elements in h/w. 11660 */ 11661 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11662 vl_arb_get_cache(vlc, t); 11663 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11664 break; 11665 case FM_TBL_BUFFER_CONTROL: 11666 size = get_buffer_control(ppd->dd, t, NULL); 11667 break; 11668 case FM_TBL_SC2VLNT: 11669 size = get_sc2vlnt(ppd->dd, t); 11670 break; 11671 case FM_TBL_VL_PREEMPT_ELEMS: 11672 size = 256; 11673 /* OPA specifies 128 elements, of 2 bytes each */ 11674 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t); 11675 break; 11676 case FM_TBL_VL_PREEMPT_MATRIX: 11677 size = 256; 11678 /* 11679 * OPA specifies that this is the same size as the VL 11680 * arbitration tables (i.e., 256 bytes). 11681 */ 11682 break; 11683 default: 11684 return -EINVAL; 11685 } 11686 return size; 11687 } 11688 11689 /* 11690 * Write the given fabric manager table. 11691 */ 11692 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t) 11693 { 11694 int ret = 0; 11695 struct vl_arb_cache *vlc; 11696 11697 switch (which) { 11698 case FM_TBL_VL_HIGH_ARB: 11699 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11700 if (vl_arb_match_cache(vlc, t)) { 11701 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11702 break; 11703 } 11704 vl_arb_set_cache(vlc, t); 11705 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11706 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST, 11707 VL_ARB_HIGH_PRIO_TABLE_SIZE, t); 11708 break; 11709 case FM_TBL_VL_LOW_ARB: 11710 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11711 if (vl_arb_match_cache(vlc, t)) { 11712 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11713 break; 11714 } 11715 vl_arb_set_cache(vlc, t); 11716 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11717 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST, 11718 VL_ARB_LOW_PRIO_TABLE_SIZE, t); 11719 break; 11720 case FM_TBL_BUFFER_CONTROL: 11721 ret = set_buffer_control(ppd, t); 11722 break; 11723 case FM_TBL_SC2VLNT: 11724 set_sc2vlnt(ppd->dd, t); 11725 break; 11726 default: 11727 ret = -EINVAL; 11728 } 11729 return ret; 11730 } 11731 11732 /* 11733 * Disable all data VLs. 11734 * 11735 * Return 0 if disabled, non-zero if the VLs cannot be disabled. 11736 */ 11737 static int disable_data_vls(struct hfi1_devdata *dd) 11738 { 11739 if (is_ax(dd)) 11740 return 1; 11741 11742 pio_send_control(dd, PSC_DATA_VL_DISABLE); 11743 11744 return 0; 11745 } 11746 11747 /* 11748 * open_fill_data_vls() - the counterpart to stop_drain_data_vls(). 11749 * Just re-enables all data VLs (the "fill" part happens 11750 * automatically - the name was chosen for symmetry with 11751 * stop_drain_data_vls()). 11752 * 11753 * Return 0 if successful, non-zero if the VLs cannot be enabled. 11754 */ 11755 int open_fill_data_vls(struct hfi1_devdata *dd) 11756 { 11757 if (is_ax(dd)) 11758 return 1; 11759 11760 pio_send_control(dd, PSC_DATA_VL_ENABLE); 11761 11762 return 0; 11763 } 11764 11765 /* 11766 * drain_data_vls() - assumes that disable_data_vls() has been called, 11767 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA 11768 * engines to drop to 0. 11769 */ 11770 static void drain_data_vls(struct hfi1_devdata *dd) 11771 { 11772 sc_wait(dd); 11773 sdma_wait(dd); 11774 pause_for_credit_return(dd); 11775 } 11776 11777 /* 11778 * stop_drain_data_vls() - disable, then drain all per-VL fifos. 11779 * 11780 * Use open_fill_data_vls() to resume using data VLs. This pair is 11781 * meant to be used like this: 11782 * 11783 * stop_drain_data_vls(dd); 11784 * // do things with per-VL resources 11785 * open_fill_data_vls(dd); 11786 */ 11787 int stop_drain_data_vls(struct hfi1_devdata *dd) 11788 { 11789 int ret; 11790 11791 ret = disable_data_vls(dd); 11792 if (ret == 0) 11793 drain_data_vls(dd); 11794 11795 return ret; 11796 } 11797 11798 /* 11799 * Convert a nanosecond time to a cclock count. No matter how slow 11800 * the cclock, a non-zero ns will always have a non-zero result. 11801 */ 11802 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns) 11803 { 11804 u32 cclocks; 11805 11806 if (dd->icode == ICODE_FPGA_EMULATION) 11807 cclocks = (ns * 1000) / FPGA_CCLOCK_PS; 11808 else /* simulation pretends to be ASIC */ 11809 cclocks = (ns * 1000) / ASIC_CCLOCK_PS; 11810 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */ 11811 cclocks = 1; 11812 return cclocks; 11813 } 11814 11815 /* 11816 * Convert a cclock count to nanoseconds. Not matter how slow 11817 * the cclock, a non-zero cclocks will always have a non-zero result. 11818 */ 11819 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks) 11820 { 11821 u32 ns; 11822 11823 if (dd->icode == ICODE_FPGA_EMULATION) 11824 ns = (cclocks * FPGA_CCLOCK_PS) / 1000; 11825 else /* simulation pretends to be ASIC */ 11826 ns = (cclocks * ASIC_CCLOCK_PS) / 1000; 11827 if (cclocks && !ns) 11828 ns = 1; 11829 return ns; 11830 } 11831 11832 /* 11833 * Dynamically adjust the receive interrupt timeout for a context based on 11834 * incoming packet rate. 11835 * 11836 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero. 11837 */ 11838 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts) 11839 { 11840 struct hfi1_devdata *dd = rcd->dd; 11841 u32 timeout = rcd->rcvavail_timeout; 11842 11843 /* 11844 * This algorithm doubles or halves the timeout depending on whether 11845 * the number of packets received in this interrupt were less than or 11846 * greater equal the interrupt count. 11847 * 11848 * The calculations below do not allow a steady state to be achieved. 11849 * Only at the endpoints it is possible to have an unchanging 11850 * timeout. 11851 */ 11852 if (npkts < rcv_intr_count) { 11853 /* 11854 * Not enough packets arrived before the timeout, adjust 11855 * timeout downward. 11856 */ 11857 if (timeout < 2) /* already at minimum? */ 11858 return; 11859 timeout >>= 1; 11860 } else { 11861 /* 11862 * More than enough packets arrived before the timeout, adjust 11863 * timeout upward. 11864 */ 11865 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */ 11866 return; 11867 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr); 11868 } 11869 11870 rcd->rcvavail_timeout = timeout; 11871 /* 11872 * timeout cannot be larger than rcv_intr_timeout_csr which has already 11873 * been verified to be in range 11874 */ 11875 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT, 11876 (u64)timeout << 11877 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11878 } 11879 11880 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, 11881 u32 intr_adjust, u32 npkts) 11882 { 11883 struct hfi1_devdata *dd = rcd->dd; 11884 u64 reg; 11885 u32 ctxt = rcd->ctxt; 11886 11887 /* 11888 * Need to write timeout register before updating RcvHdrHead to ensure 11889 * that a new value is used when the HW decides to restart counting. 11890 */ 11891 if (intr_adjust) 11892 adjust_rcv_timeout(rcd, npkts); 11893 if (updegr) { 11894 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK) 11895 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT; 11896 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg); 11897 } 11898 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) | 11899 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK) 11900 << RCV_HDR_HEAD_HEAD_SHIFT); 11901 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11902 } 11903 11904 u32 hdrqempty(struct hfi1_ctxtdata *rcd) 11905 { 11906 u32 head, tail; 11907 11908 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD) 11909 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT; 11910 11911 if (hfi1_rcvhdrtail_kvaddr(rcd)) 11912 tail = get_rcvhdrtail(rcd); 11913 else 11914 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 11915 11916 return head == tail; 11917 } 11918 11919 /* 11920 * Context Control and Receive Array encoding for buffer size: 11921 * 0x0 invalid 11922 * 0x1 4 KB 11923 * 0x2 8 KB 11924 * 0x3 16 KB 11925 * 0x4 32 KB 11926 * 0x5 64 KB 11927 * 0x6 128 KB 11928 * 0x7 256 KB 11929 * 0x8 512 KB (Receive Array only) 11930 * 0x9 1 MB (Receive Array only) 11931 * 0xa 2 MB (Receive Array only) 11932 * 11933 * 0xB-0xF - reserved (Receive Array only) 11934 * 11935 * 11936 * This routine assumes that the value has already been sanity checked. 11937 */ 11938 static u32 encoded_size(u32 size) 11939 { 11940 switch (size) { 11941 case 4 * 1024: return 0x1; 11942 case 8 * 1024: return 0x2; 11943 case 16 * 1024: return 0x3; 11944 case 32 * 1024: return 0x4; 11945 case 64 * 1024: return 0x5; 11946 case 128 * 1024: return 0x6; 11947 case 256 * 1024: return 0x7; 11948 case 512 * 1024: return 0x8; 11949 case 1 * 1024 * 1024: return 0x9; 11950 case 2 * 1024 * 1024: return 0xa; 11951 } 11952 return 0x1; /* if invalid, go with the minimum size */ 11953 } 11954 11955 /** 11956 * encode_rcv_header_entry_size - return chip specific encoding for size 11957 * @size: size in dwords 11958 * 11959 * Convert a receive header entry size that to the encoding used in the CSR. 11960 * 11961 * Return a zero if the given size is invalid, otherwise the encoding. 11962 */ 11963 u8 encode_rcv_header_entry_size(u8 size) 11964 { 11965 /* there are only 3 valid receive header entry sizes */ 11966 if (size == 2) 11967 return 1; 11968 if (size == 16) 11969 return 2; 11970 if (size == 32) 11971 return 4; 11972 return 0; /* invalid */ 11973 } 11974 11975 /** 11976 * hfi1_validate_rcvhdrcnt - validate hdrcnt 11977 * @dd: the device data 11978 * @thecnt: the header count 11979 */ 11980 int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt) 11981 { 11982 if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { 11983 dd_dev_err(dd, "Receive header queue count too small\n"); 11984 return -EINVAL; 11985 } 11986 11987 if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) { 11988 dd_dev_err(dd, 11989 "Receive header queue count cannot be greater than %u\n", 11990 HFI1_MAX_HDRQ_EGRBUF_CNT); 11991 return -EINVAL; 11992 } 11993 11994 if (thecnt % HDRQ_INCREMENT) { 11995 dd_dev_err(dd, "Receive header queue count %d must be divisible by %lu\n", 11996 thecnt, HDRQ_INCREMENT); 11997 return -EINVAL; 11998 } 11999 12000 return 0; 12001 } 12002 12003 /** 12004 * set_hdrq_regs - set header queue registers for context 12005 * @dd: the device data 12006 * @ctxt: the context 12007 * @entsize: the dword entry size 12008 * @hdrcnt: the number of header entries 12009 */ 12010 void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt) 12011 { 12012 u64 reg; 12013 12014 reg = (((u64)hdrcnt >> HDRQ_SIZE_SHIFT) & RCV_HDR_CNT_CNT_MASK) << 12015 RCV_HDR_CNT_CNT_SHIFT; 12016 write_kctxt_csr(dd, ctxt, RCV_HDR_CNT, reg); 12017 reg = ((u64)encode_rcv_header_entry_size(entsize) & 12018 RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) << 12019 RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT; 12020 write_kctxt_csr(dd, ctxt, RCV_HDR_ENT_SIZE, reg); 12021 reg = ((u64)DEFAULT_RCVHDRSIZE & RCV_HDR_SIZE_HDR_SIZE_MASK) << 12022 RCV_HDR_SIZE_HDR_SIZE_SHIFT; 12023 write_kctxt_csr(dd, ctxt, RCV_HDR_SIZE, reg); 12024 12025 /* 12026 * Program dummy tail address for every receive context 12027 * before enabling any receive context 12028 */ 12029 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12030 dd->rcvhdrtail_dummy_dma); 12031 } 12032 12033 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, 12034 struct hfi1_ctxtdata *rcd) 12035 { 12036 u64 rcvctrl, reg; 12037 int did_enable = 0; 12038 u16 ctxt; 12039 12040 if (!rcd) 12041 return; 12042 12043 ctxt = rcd->ctxt; 12044 12045 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op); 12046 12047 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL); 12048 /* if the context already enabled, don't do the extra steps */ 12049 if ((op & HFI1_RCVCTRL_CTXT_ENB) && 12050 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) { 12051 /* reset the tail and hdr addresses, and sequence count */ 12052 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR, 12053 rcd->rcvhdrq_dma); 12054 if (hfi1_rcvhdrtail_kvaddr(rcd)) 12055 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12056 rcd->rcvhdrqtailaddr_dma); 12057 hfi1_set_seq_cnt(rcd, 1); 12058 12059 /* reset the cached receive header queue head value */ 12060 hfi1_set_rcd_head(rcd, 0); 12061 12062 /* 12063 * Zero the receive header queue so we don't get false 12064 * positives when checking the sequence number. The 12065 * sequence numbers could land exactly on the same spot. 12066 * E.g. a rcd restart before the receive header wrapped. 12067 */ 12068 memset(rcd->rcvhdrq, 0, rcvhdrq_size(rcd)); 12069 12070 /* starting timeout */ 12071 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr; 12072 12073 /* enable the context */ 12074 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK; 12075 12076 /* clean the egr buffer size first */ 12077 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 12078 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size) 12079 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK) 12080 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT; 12081 12082 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */ 12083 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0); 12084 did_enable = 1; 12085 12086 /* zero RcvEgrIndexHead */ 12087 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0); 12088 12089 /* set eager count and base index */ 12090 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT) 12091 & RCV_EGR_CTRL_EGR_CNT_MASK) 12092 << RCV_EGR_CTRL_EGR_CNT_SHIFT) | 12093 (((rcd->eager_base >> RCV_SHIFT) 12094 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK) 12095 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT); 12096 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg); 12097 12098 /* 12099 * Set TID (expected) count and base index. 12100 * rcd->expected_count is set to individual RcvArray entries, 12101 * not pairs, and the CSR takes a pair-count in groups of 12102 * four, so divide by 8. 12103 */ 12104 reg = (((rcd->expected_count >> RCV_SHIFT) 12105 & RCV_TID_CTRL_TID_PAIR_CNT_MASK) 12106 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) | 12107 (((rcd->expected_base >> RCV_SHIFT) 12108 & RCV_TID_CTRL_TID_BASE_INDEX_MASK) 12109 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT); 12110 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg); 12111 if (ctxt == HFI1_CTRL_CTXT) 12112 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); 12113 } 12114 if (op & HFI1_RCVCTRL_CTXT_DIS) { 12115 write_csr(dd, RCV_VL15, 0); 12116 /* 12117 * When receive context is being disabled turn on tail 12118 * update with a dummy tail address and then disable 12119 * receive context. 12120 */ 12121 if (dd->rcvhdrtail_dummy_dma) { 12122 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12123 dd->rcvhdrtail_dummy_dma); 12124 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */ 12125 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 12126 } 12127 12128 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK; 12129 } 12130 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB) { 12131 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt, 12132 IS_RCVAVAIL_START + rcd->ctxt, true); 12133 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 12134 } 12135 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS) { 12136 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt, 12137 IS_RCVAVAIL_START + rcd->ctxt, false); 12138 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 12139 } 12140 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && hfi1_rcvhdrtail_kvaddr(rcd)) 12141 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 12142 if (op & HFI1_RCVCTRL_TAILUPD_DIS) { 12143 /* See comment on RcvCtxtCtrl.TailUpd above */ 12144 if (!(op & HFI1_RCVCTRL_CTXT_DIS)) 12145 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK; 12146 } 12147 if (op & HFI1_RCVCTRL_TIDFLOW_ENB) 12148 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 12149 if (op & HFI1_RCVCTRL_TIDFLOW_DIS) 12150 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 12151 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) { 12152 /* 12153 * In one-packet-per-eager mode, the size comes from 12154 * the RcvArray entry. 12155 */ 12156 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 12157 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 12158 } 12159 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS) 12160 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 12161 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB) 12162 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 12163 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS) 12164 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 12165 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB) 12166 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 12167 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS) 12168 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 12169 if (op & HFI1_RCVCTRL_URGENT_ENB) 12170 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt, 12171 IS_RCVURGENT_START + rcd->ctxt, true); 12172 if (op & HFI1_RCVCTRL_URGENT_DIS) 12173 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt, 12174 IS_RCVURGENT_START + rcd->ctxt, false); 12175 12176 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl); 12177 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcvctrl); 12178 12179 /* work around sticky RcvCtxtStatus.BlockedRHQFull */ 12180 if (did_enable && 12181 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) { 12182 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 12183 if (reg != 0) { 12184 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n", 12185 ctxt, reg); 12186 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 12187 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10); 12188 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00); 12189 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 12190 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 12191 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n", 12192 ctxt, reg, reg == 0 ? "not" : "still"); 12193 } 12194 } 12195 12196 if (did_enable) { 12197 /* 12198 * The interrupt timeout and count must be set after 12199 * the context is enabled to take effect. 12200 */ 12201 /* set interrupt timeout */ 12202 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT, 12203 (u64)rcd->rcvavail_timeout << 12204 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 12205 12206 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */ 12207 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT; 12208 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 12209 } 12210 12211 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS)) 12212 /* 12213 * If the context has been disabled and the Tail Update has 12214 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address 12215 * so it doesn't contain an address that is invalid. 12216 */ 12217 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12218 dd->rcvhdrtail_dummy_dma); 12219 } 12220 12221 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp) 12222 { 12223 int ret; 12224 u64 val = 0; 12225 12226 if (namep) { 12227 ret = dd->cntrnameslen; 12228 *namep = dd->cntrnames; 12229 } else { 12230 const struct cntr_entry *entry; 12231 int i, j; 12232 12233 ret = (dd->ndevcntrs) * sizeof(u64); 12234 12235 /* Get the start of the block of counters */ 12236 *cntrp = dd->cntrs; 12237 12238 /* 12239 * Now go and fill in each counter in the block. 12240 */ 12241 for (i = 0; i < DEV_CNTR_LAST; i++) { 12242 entry = &dev_cntrs[i]; 12243 hfi1_cdbg(CNTR, "reading %s", entry->name); 12244 if (entry->flags & CNTR_DISABLED) { 12245 /* Nothing */ 12246 hfi1_cdbg(CNTR, "\tDisabled\n"); 12247 } else { 12248 if (entry->flags & CNTR_VL) { 12249 hfi1_cdbg(CNTR, "\tPer VL\n"); 12250 for (j = 0; j < C_VL_COUNT; j++) { 12251 val = entry->rw_cntr(entry, 12252 dd, j, 12253 CNTR_MODE_R, 12254 0); 12255 hfi1_cdbg( 12256 CNTR, 12257 "\t\tRead 0x%llx for %d\n", 12258 val, j); 12259 dd->cntrs[entry->offset + j] = 12260 val; 12261 } 12262 } else if (entry->flags & CNTR_SDMA) { 12263 hfi1_cdbg(CNTR, 12264 "\t Per SDMA Engine\n"); 12265 for (j = 0; j < chip_sdma_engines(dd); 12266 j++) { 12267 val = 12268 entry->rw_cntr(entry, dd, j, 12269 CNTR_MODE_R, 0); 12270 hfi1_cdbg(CNTR, 12271 "\t\tRead 0x%llx for %d\n", 12272 val, j); 12273 dd->cntrs[entry->offset + j] = 12274 val; 12275 } 12276 } else { 12277 val = entry->rw_cntr(entry, dd, 12278 CNTR_INVALID_VL, 12279 CNTR_MODE_R, 0); 12280 dd->cntrs[entry->offset] = val; 12281 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12282 } 12283 } 12284 } 12285 } 12286 return ret; 12287 } 12288 12289 /* 12290 * Used by sysfs to create files for hfi stats to read 12291 */ 12292 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp) 12293 { 12294 int ret; 12295 u64 val = 0; 12296 12297 if (namep) { 12298 ret = ppd->dd->portcntrnameslen; 12299 *namep = ppd->dd->portcntrnames; 12300 } else { 12301 const struct cntr_entry *entry; 12302 int i, j; 12303 12304 ret = ppd->dd->nportcntrs * sizeof(u64); 12305 *cntrp = ppd->cntrs; 12306 12307 for (i = 0; i < PORT_CNTR_LAST; i++) { 12308 entry = &port_cntrs[i]; 12309 hfi1_cdbg(CNTR, "reading %s", entry->name); 12310 if (entry->flags & CNTR_DISABLED) { 12311 /* Nothing */ 12312 hfi1_cdbg(CNTR, "\tDisabled\n"); 12313 continue; 12314 } 12315 12316 if (entry->flags & CNTR_VL) { 12317 hfi1_cdbg(CNTR, "\tPer VL"); 12318 for (j = 0; j < C_VL_COUNT; j++) { 12319 val = entry->rw_cntr(entry, ppd, j, 12320 CNTR_MODE_R, 12321 0); 12322 hfi1_cdbg( 12323 CNTR, 12324 "\t\tRead 0x%llx for %d", 12325 val, j); 12326 ppd->cntrs[entry->offset + j] = val; 12327 } 12328 } else { 12329 val = entry->rw_cntr(entry, ppd, 12330 CNTR_INVALID_VL, 12331 CNTR_MODE_R, 12332 0); 12333 ppd->cntrs[entry->offset] = val; 12334 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12335 } 12336 } 12337 } 12338 return ret; 12339 } 12340 12341 static void free_cntrs(struct hfi1_devdata *dd) 12342 { 12343 struct hfi1_pportdata *ppd; 12344 int i; 12345 12346 if (dd->synth_stats_timer.function) 12347 del_timer_sync(&dd->synth_stats_timer); 12348 ppd = (struct hfi1_pportdata *)(dd + 1); 12349 for (i = 0; i < dd->num_pports; i++, ppd++) { 12350 kfree(ppd->cntrs); 12351 kfree(ppd->scntrs); 12352 free_percpu(ppd->ibport_data.rvp.rc_acks); 12353 free_percpu(ppd->ibport_data.rvp.rc_qacks); 12354 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp); 12355 ppd->cntrs = NULL; 12356 ppd->scntrs = NULL; 12357 ppd->ibport_data.rvp.rc_acks = NULL; 12358 ppd->ibport_data.rvp.rc_qacks = NULL; 12359 ppd->ibport_data.rvp.rc_delayed_comp = NULL; 12360 } 12361 kfree(dd->portcntrnames); 12362 dd->portcntrnames = NULL; 12363 kfree(dd->cntrs); 12364 dd->cntrs = NULL; 12365 kfree(dd->scntrs); 12366 dd->scntrs = NULL; 12367 kfree(dd->cntrnames); 12368 dd->cntrnames = NULL; 12369 if (dd->update_cntr_wq) { 12370 destroy_workqueue(dd->update_cntr_wq); 12371 dd->update_cntr_wq = NULL; 12372 } 12373 } 12374 12375 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry, 12376 u64 *psval, void *context, int vl) 12377 { 12378 u64 val; 12379 u64 sval = *psval; 12380 12381 if (entry->flags & CNTR_DISABLED) { 12382 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12383 return 0; 12384 } 12385 12386 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12387 12388 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0); 12389 12390 /* If its a synthetic counter there is more work we need to do */ 12391 if (entry->flags & CNTR_SYNTH) { 12392 if (sval == CNTR_MAX) { 12393 /* No need to read already saturated */ 12394 return CNTR_MAX; 12395 } 12396 12397 if (entry->flags & CNTR_32BIT) { 12398 /* 32bit counters can wrap multiple times */ 12399 u64 upper = sval >> 32; 12400 u64 lower = (sval << 32) >> 32; 12401 12402 if (lower > val) { /* hw wrapped */ 12403 if (upper == CNTR_32BIT_MAX) 12404 val = CNTR_MAX; 12405 else 12406 upper++; 12407 } 12408 12409 if (val != CNTR_MAX) 12410 val = (upper << 32) | val; 12411 12412 } else { 12413 /* If we rolled we are saturated */ 12414 if ((val < sval) || (val > CNTR_MAX)) 12415 val = CNTR_MAX; 12416 } 12417 } 12418 12419 *psval = val; 12420 12421 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12422 12423 return val; 12424 } 12425 12426 static u64 write_dev_port_cntr(struct hfi1_devdata *dd, 12427 struct cntr_entry *entry, 12428 u64 *psval, void *context, int vl, u64 data) 12429 { 12430 u64 val; 12431 12432 if (entry->flags & CNTR_DISABLED) { 12433 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12434 return 0; 12435 } 12436 12437 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12438 12439 if (entry->flags & CNTR_SYNTH) { 12440 *psval = data; 12441 if (entry->flags & CNTR_32BIT) { 12442 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12443 (data << 32) >> 32); 12444 val = data; /* return the full 64bit value */ 12445 } else { 12446 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12447 data); 12448 } 12449 } else { 12450 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data); 12451 } 12452 12453 *psval = val; 12454 12455 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12456 12457 return val; 12458 } 12459 12460 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl) 12461 { 12462 struct cntr_entry *entry; 12463 u64 *sval; 12464 12465 entry = &dev_cntrs[index]; 12466 sval = dd->scntrs + entry->offset; 12467 12468 if (vl != CNTR_INVALID_VL) 12469 sval += vl; 12470 12471 return read_dev_port_cntr(dd, entry, sval, dd, vl); 12472 } 12473 12474 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data) 12475 { 12476 struct cntr_entry *entry; 12477 u64 *sval; 12478 12479 entry = &dev_cntrs[index]; 12480 sval = dd->scntrs + entry->offset; 12481 12482 if (vl != CNTR_INVALID_VL) 12483 sval += vl; 12484 12485 return write_dev_port_cntr(dd, entry, sval, dd, vl, data); 12486 } 12487 12488 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl) 12489 { 12490 struct cntr_entry *entry; 12491 u64 *sval; 12492 12493 entry = &port_cntrs[index]; 12494 sval = ppd->scntrs + entry->offset; 12495 12496 if (vl != CNTR_INVALID_VL) 12497 sval += vl; 12498 12499 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12500 (index <= C_RCV_HDR_OVF_LAST)) { 12501 /* We do not want to bother for disabled contexts */ 12502 return 0; 12503 } 12504 12505 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl); 12506 } 12507 12508 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data) 12509 { 12510 struct cntr_entry *entry; 12511 u64 *sval; 12512 12513 entry = &port_cntrs[index]; 12514 sval = ppd->scntrs + entry->offset; 12515 12516 if (vl != CNTR_INVALID_VL) 12517 sval += vl; 12518 12519 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12520 (index <= C_RCV_HDR_OVF_LAST)) { 12521 /* We do not want to bother for disabled contexts */ 12522 return 0; 12523 } 12524 12525 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data); 12526 } 12527 12528 static void do_update_synth_timer(struct work_struct *work) 12529 { 12530 u64 cur_tx; 12531 u64 cur_rx; 12532 u64 total_flits; 12533 u8 update = 0; 12534 int i, j, vl; 12535 struct hfi1_pportdata *ppd; 12536 struct cntr_entry *entry; 12537 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata, 12538 update_cntr_work); 12539 12540 /* 12541 * Rather than keep beating on the CSRs pick a minimal set that we can 12542 * check to watch for potential roll over. We can do this by looking at 12543 * the number of flits sent/recv. If the total flits exceeds 32bits then 12544 * we have to iterate all the counters and update. 12545 */ 12546 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12547 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12548 12549 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12550 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12551 12552 hfi1_cdbg( 12553 CNTR, 12554 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n", 12555 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx); 12556 12557 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) { 12558 /* 12559 * May not be strictly necessary to update but it won't hurt and 12560 * simplifies the logic here. 12561 */ 12562 update = 1; 12563 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating", 12564 dd->unit); 12565 } else { 12566 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx); 12567 hfi1_cdbg(CNTR, 12568 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit, 12569 total_flits, (u64)CNTR_32BIT_MAX); 12570 if (total_flits >= CNTR_32BIT_MAX) { 12571 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating", 12572 dd->unit); 12573 update = 1; 12574 } 12575 } 12576 12577 if (update) { 12578 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit); 12579 for (i = 0; i < DEV_CNTR_LAST; i++) { 12580 entry = &dev_cntrs[i]; 12581 if (entry->flags & CNTR_VL) { 12582 for (vl = 0; vl < C_VL_COUNT; vl++) 12583 read_dev_cntr(dd, i, vl); 12584 } else { 12585 read_dev_cntr(dd, i, CNTR_INVALID_VL); 12586 } 12587 } 12588 ppd = (struct hfi1_pportdata *)(dd + 1); 12589 for (i = 0; i < dd->num_pports; i++, ppd++) { 12590 for (j = 0; j < PORT_CNTR_LAST; j++) { 12591 entry = &port_cntrs[j]; 12592 if (entry->flags & CNTR_VL) { 12593 for (vl = 0; vl < C_VL_COUNT; vl++) 12594 read_port_cntr(ppd, j, vl); 12595 } else { 12596 read_port_cntr(ppd, j, CNTR_INVALID_VL); 12597 } 12598 } 12599 } 12600 12601 /* 12602 * We want the value in the register. The goal is to keep track 12603 * of the number of "ticks" not the counter value. In other 12604 * words if the register rolls we want to notice it and go ahead 12605 * and force an update. 12606 */ 12607 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12608 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12609 CNTR_MODE_R, 0); 12610 12611 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12612 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12613 CNTR_MODE_R, 0); 12614 12615 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx", 12616 dd->unit, dd->last_tx, dd->last_rx); 12617 12618 } else { 12619 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit); 12620 } 12621 } 12622 12623 static void update_synth_timer(struct timer_list *t) 12624 { 12625 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer); 12626 12627 queue_work(dd->update_cntr_wq, &dd->update_cntr_work); 12628 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12629 } 12630 12631 #define C_MAX_NAME 16 /* 15 chars + one for /0 */ 12632 static int init_cntrs(struct hfi1_devdata *dd) 12633 { 12634 int i, rcv_ctxts, j; 12635 size_t sz; 12636 char *p; 12637 char name[C_MAX_NAME]; 12638 struct hfi1_pportdata *ppd; 12639 const char *bit_type_32 = ",32"; 12640 const int bit_type_32_sz = strlen(bit_type_32); 12641 u32 sdma_engines = chip_sdma_engines(dd); 12642 12643 /* set up the stats timer; the add_timer is done at the end */ 12644 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0); 12645 12646 /***********************/ 12647 /* per device counters */ 12648 /***********************/ 12649 12650 /* size names and determine how many we have*/ 12651 dd->ndevcntrs = 0; 12652 sz = 0; 12653 12654 for (i = 0; i < DEV_CNTR_LAST; i++) { 12655 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12656 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name); 12657 continue; 12658 } 12659 12660 if (dev_cntrs[i].flags & CNTR_VL) { 12661 dev_cntrs[i].offset = dd->ndevcntrs; 12662 for (j = 0; j < C_VL_COUNT; j++) { 12663 snprintf(name, C_MAX_NAME, "%s%d", 12664 dev_cntrs[i].name, vl_from_idx(j)); 12665 sz += strlen(name); 12666 /* Add ",32" for 32-bit counters */ 12667 if (dev_cntrs[i].flags & CNTR_32BIT) 12668 sz += bit_type_32_sz; 12669 sz++; 12670 dd->ndevcntrs++; 12671 } 12672 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12673 dev_cntrs[i].offset = dd->ndevcntrs; 12674 for (j = 0; j < sdma_engines; j++) { 12675 snprintf(name, C_MAX_NAME, "%s%d", 12676 dev_cntrs[i].name, j); 12677 sz += strlen(name); 12678 /* Add ",32" for 32-bit counters */ 12679 if (dev_cntrs[i].flags & CNTR_32BIT) 12680 sz += bit_type_32_sz; 12681 sz++; 12682 dd->ndevcntrs++; 12683 } 12684 } else { 12685 /* +1 for newline. */ 12686 sz += strlen(dev_cntrs[i].name) + 1; 12687 /* Add ",32" for 32-bit counters */ 12688 if (dev_cntrs[i].flags & CNTR_32BIT) 12689 sz += bit_type_32_sz; 12690 dev_cntrs[i].offset = dd->ndevcntrs; 12691 dd->ndevcntrs++; 12692 } 12693 } 12694 12695 /* allocate space for the counter values */ 12696 dd->cntrs = kcalloc(dd->ndevcntrs + num_driver_cntrs, sizeof(u64), 12697 GFP_KERNEL); 12698 if (!dd->cntrs) 12699 goto bail; 12700 12701 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12702 if (!dd->scntrs) 12703 goto bail; 12704 12705 /* allocate space for the counter names */ 12706 dd->cntrnameslen = sz; 12707 dd->cntrnames = kmalloc(sz, GFP_KERNEL); 12708 if (!dd->cntrnames) 12709 goto bail; 12710 12711 /* fill in the names */ 12712 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) { 12713 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12714 /* Nothing */ 12715 } else if (dev_cntrs[i].flags & CNTR_VL) { 12716 for (j = 0; j < C_VL_COUNT; j++) { 12717 snprintf(name, C_MAX_NAME, "%s%d", 12718 dev_cntrs[i].name, 12719 vl_from_idx(j)); 12720 memcpy(p, name, strlen(name)); 12721 p += strlen(name); 12722 12723 /* Counter is 32 bits */ 12724 if (dev_cntrs[i].flags & CNTR_32BIT) { 12725 memcpy(p, bit_type_32, bit_type_32_sz); 12726 p += bit_type_32_sz; 12727 } 12728 12729 *p++ = '\n'; 12730 } 12731 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12732 for (j = 0; j < sdma_engines; j++) { 12733 snprintf(name, C_MAX_NAME, "%s%d", 12734 dev_cntrs[i].name, j); 12735 memcpy(p, name, strlen(name)); 12736 p += strlen(name); 12737 12738 /* Counter is 32 bits */ 12739 if (dev_cntrs[i].flags & CNTR_32BIT) { 12740 memcpy(p, bit_type_32, bit_type_32_sz); 12741 p += bit_type_32_sz; 12742 } 12743 12744 *p++ = '\n'; 12745 } 12746 } else { 12747 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name)); 12748 p += strlen(dev_cntrs[i].name); 12749 12750 /* Counter is 32 bits */ 12751 if (dev_cntrs[i].flags & CNTR_32BIT) { 12752 memcpy(p, bit_type_32, bit_type_32_sz); 12753 p += bit_type_32_sz; 12754 } 12755 12756 *p++ = '\n'; 12757 } 12758 } 12759 12760 /*********************/ 12761 /* per port counters */ 12762 /*********************/ 12763 12764 /* 12765 * Go through the counters for the overflows and disable the ones we 12766 * don't need. This varies based on platform so we need to do it 12767 * dynamically here. 12768 */ 12769 rcv_ctxts = dd->num_rcv_contexts; 12770 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts; 12771 i <= C_RCV_HDR_OVF_LAST; i++) { 12772 port_cntrs[i].flags |= CNTR_DISABLED; 12773 } 12774 12775 /* size port counter names and determine how many we have*/ 12776 sz = 0; 12777 dd->nportcntrs = 0; 12778 for (i = 0; i < PORT_CNTR_LAST; i++) { 12779 if (port_cntrs[i].flags & CNTR_DISABLED) { 12780 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name); 12781 continue; 12782 } 12783 12784 if (port_cntrs[i].flags & CNTR_VL) { 12785 port_cntrs[i].offset = dd->nportcntrs; 12786 for (j = 0; j < C_VL_COUNT; j++) { 12787 snprintf(name, C_MAX_NAME, "%s%d", 12788 port_cntrs[i].name, vl_from_idx(j)); 12789 sz += strlen(name); 12790 /* Add ",32" for 32-bit counters */ 12791 if (port_cntrs[i].flags & CNTR_32BIT) 12792 sz += bit_type_32_sz; 12793 sz++; 12794 dd->nportcntrs++; 12795 } 12796 } else { 12797 /* +1 for newline */ 12798 sz += strlen(port_cntrs[i].name) + 1; 12799 /* Add ",32" for 32-bit counters */ 12800 if (port_cntrs[i].flags & CNTR_32BIT) 12801 sz += bit_type_32_sz; 12802 port_cntrs[i].offset = dd->nportcntrs; 12803 dd->nportcntrs++; 12804 } 12805 } 12806 12807 /* allocate space for the counter names */ 12808 dd->portcntrnameslen = sz; 12809 dd->portcntrnames = kmalloc(sz, GFP_KERNEL); 12810 if (!dd->portcntrnames) 12811 goto bail; 12812 12813 /* fill in port cntr names */ 12814 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) { 12815 if (port_cntrs[i].flags & CNTR_DISABLED) 12816 continue; 12817 12818 if (port_cntrs[i].flags & CNTR_VL) { 12819 for (j = 0; j < C_VL_COUNT; j++) { 12820 snprintf(name, C_MAX_NAME, "%s%d", 12821 port_cntrs[i].name, vl_from_idx(j)); 12822 memcpy(p, name, strlen(name)); 12823 p += strlen(name); 12824 12825 /* Counter is 32 bits */ 12826 if (port_cntrs[i].flags & CNTR_32BIT) { 12827 memcpy(p, bit_type_32, bit_type_32_sz); 12828 p += bit_type_32_sz; 12829 } 12830 12831 *p++ = '\n'; 12832 } 12833 } else { 12834 memcpy(p, port_cntrs[i].name, 12835 strlen(port_cntrs[i].name)); 12836 p += strlen(port_cntrs[i].name); 12837 12838 /* Counter is 32 bits */ 12839 if (port_cntrs[i].flags & CNTR_32BIT) { 12840 memcpy(p, bit_type_32, bit_type_32_sz); 12841 p += bit_type_32_sz; 12842 } 12843 12844 *p++ = '\n'; 12845 } 12846 } 12847 12848 /* allocate per port storage for counter values */ 12849 ppd = (struct hfi1_pportdata *)(dd + 1); 12850 for (i = 0; i < dd->num_pports; i++, ppd++) { 12851 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12852 if (!ppd->cntrs) 12853 goto bail; 12854 12855 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12856 if (!ppd->scntrs) 12857 goto bail; 12858 } 12859 12860 /* CPU counters need to be allocated and zeroed */ 12861 if (init_cpu_counters(dd)) 12862 goto bail; 12863 12864 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d", 12865 WQ_MEM_RECLAIM, dd->unit); 12866 if (!dd->update_cntr_wq) 12867 goto bail; 12868 12869 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer); 12870 12871 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12872 return 0; 12873 bail: 12874 free_cntrs(dd); 12875 return -ENOMEM; 12876 } 12877 12878 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate) 12879 { 12880 switch (chip_lstate) { 12881 default: 12882 dd_dev_err(dd, 12883 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n", 12884 chip_lstate); 12885 /* fall through */ 12886 case LSTATE_DOWN: 12887 return IB_PORT_DOWN; 12888 case LSTATE_INIT: 12889 return IB_PORT_INIT; 12890 case LSTATE_ARMED: 12891 return IB_PORT_ARMED; 12892 case LSTATE_ACTIVE: 12893 return IB_PORT_ACTIVE; 12894 } 12895 } 12896 12897 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate) 12898 { 12899 /* look at the HFI meta-states only */ 12900 switch (chip_pstate & 0xf0) { 12901 default: 12902 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n", 12903 chip_pstate); 12904 /* fall through */ 12905 case PLS_DISABLED: 12906 return IB_PORTPHYSSTATE_DISABLED; 12907 case PLS_OFFLINE: 12908 return OPA_PORTPHYSSTATE_OFFLINE; 12909 case PLS_POLLING: 12910 return IB_PORTPHYSSTATE_POLLING; 12911 case PLS_CONFIGPHY: 12912 return IB_PORTPHYSSTATE_TRAINING; 12913 case PLS_LINKUP: 12914 return IB_PORTPHYSSTATE_LINKUP; 12915 case PLS_PHYTEST: 12916 return IB_PORTPHYSSTATE_PHY_TEST; 12917 } 12918 } 12919 12920 /* return the OPA port logical state name */ 12921 const char *opa_lstate_name(u32 lstate) 12922 { 12923 static const char * const port_logical_names[] = { 12924 "PORT_NOP", 12925 "PORT_DOWN", 12926 "PORT_INIT", 12927 "PORT_ARMED", 12928 "PORT_ACTIVE", 12929 "PORT_ACTIVE_DEFER", 12930 }; 12931 if (lstate < ARRAY_SIZE(port_logical_names)) 12932 return port_logical_names[lstate]; 12933 return "unknown"; 12934 } 12935 12936 /* return the OPA port physical state name */ 12937 const char *opa_pstate_name(u32 pstate) 12938 { 12939 static const char * const port_physical_names[] = { 12940 "PHYS_NOP", 12941 "reserved1", 12942 "PHYS_POLL", 12943 "PHYS_DISABLED", 12944 "PHYS_TRAINING", 12945 "PHYS_LINKUP", 12946 "PHYS_LINK_ERR_RECOVER", 12947 "PHYS_PHY_TEST", 12948 "reserved8", 12949 "PHYS_OFFLINE", 12950 "PHYS_GANGED", 12951 "PHYS_TEST", 12952 }; 12953 if (pstate < ARRAY_SIZE(port_physical_names)) 12954 return port_physical_names[pstate]; 12955 return "unknown"; 12956 } 12957 12958 /** 12959 * update_statusp - Update userspace status flag 12960 * @ppd: Port data structure 12961 * @state: port state information 12962 * 12963 * Actual port status is determined by the host_link_state value 12964 * in the ppd. 12965 * 12966 * host_link_state MUST be updated before updating the user space 12967 * statusp. 12968 */ 12969 static void update_statusp(struct hfi1_pportdata *ppd, u32 state) 12970 { 12971 /* 12972 * Set port status flags in the page mapped into userspace 12973 * memory. Do it here to ensure a reliable state - this is 12974 * the only function called by all state handling code. 12975 * Always set the flags due to the fact that the cache value 12976 * might have been changed explicitly outside of this 12977 * function. 12978 */ 12979 if (ppd->statusp) { 12980 switch (state) { 12981 case IB_PORT_DOWN: 12982 case IB_PORT_INIT: 12983 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 12984 HFI1_STATUS_IB_READY); 12985 break; 12986 case IB_PORT_ARMED: 12987 *ppd->statusp |= HFI1_STATUS_IB_CONF; 12988 break; 12989 case IB_PORT_ACTIVE: 12990 *ppd->statusp |= HFI1_STATUS_IB_READY; 12991 break; 12992 } 12993 } 12994 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n", 12995 opa_lstate_name(state), state); 12996 } 12997 12998 /** 12999 * wait_logical_linkstate - wait for an IB link state change to occur 13000 * @ppd: port device 13001 * @state: the state to wait for 13002 * @msecs: the number of milliseconds to wait 13003 * 13004 * Wait up to msecs milliseconds for IB link state change to occur. 13005 * For now, take the easy polling route. 13006 * Returns 0 if state reached, otherwise -ETIMEDOUT. 13007 */ 13008 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 13009 int msecs) 13010 { 13011 unsigned long timeout; 13012 u32 new_state; 13013 13014 timeout = jiffies + msecs_to_jiffies(msecs); 13015 while (1) { 13016 new_state = chip_to_opa_lstate(ppd->dd, 13017 read_logical_state(ppd->dd)); 13018 if (new_state == state) 13019 break; 13020 if (time_after(jiffies, timeout)) { 13021 dd_dev_err(ppd->dd, 13022 "timeout waiting for link state 0x%x\n", 13023 state); 13024 return -ETIMEDOUT; 13025 } 13026 msleep(20); 13027 } 13028 13029 return 0; 13030 } 13031 13032 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state) 13033 { 13034 u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state); 13035 13036 dd_dev_info(ppd->dd, 13037 "physical state changed to %s (0x%x), phy 0x%x\n", 13038 opa_pstate_name(ib_pstate), ib_pstate, state); 13039 } 13040 13041 /* 13042 * Read the physical hardware link state and check if it matches host 13043 * drivers anticipated state. 13044 */ 13045 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state) 13046 { 13047 u32 read_state = read_physical_state(ppd->dd); 13048 13049 if (read_state == state) { 13050 log_state_transition(ppd, state); 13051 } else { 13052 dd_dev_err(ppd->dd, 13053 "anticipated phy link state 0x%x, read 0x%x\n", 13054 state, read_state); 13055 } 13056 } 13057 13058 /* 13059 * wait_physical_linkstate - wait for an physical link state change to occur 13060 * @ppd: port device 13061 * @state: the state to wait for 13062 * @msecs: the number of milliseconds to wait 13063 * 13064 * Wait up to msecs milliseconds for physical link state change to occur. 13065 * Returns 0 if state reached, otherwise -ETIMEDOUT. 13066 */ 13067 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 13068 int msecs) 13069 { 13070 u32 read_state; 13071 unsigned long timeout; 13072 13073 timeout = jiffies + msecs_to_jiffies(msecs); 13074 while (1) { 13075 read_state = read_physical_state(ppd->dd); 13076 if (read_state == state) 13077 break; 13078 if (time_after(jiffies, timeout)) { 13079 dd_dev_err(ppd->dd, 13080 "timeout waiting for phy link state 0x%x\n", 13081 state); 13082 return -ETIMEDOUT; 13083 } 13084 usleep_range(1950, 2050); /* sleep 2ms-ish */ 13085 } 13086 13087 log_state_transition(ppd, state); 13088 return 0; 13089 } 13090 13091 /* 13092 * wait_phys_link_offline_quiet_substates - wait for any offline substate 13093 * @ppd: port device 13094 * @msecs: the number of milliseconds to wait 13095 * 13096 * Wait up to msecs milliseconds for any offline physical link 13097 * state change to occur. 13098 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 13099 */ 13100 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 13101 int msecs) 13102 { 13103 u32 read_state; 13104 unsigned long timeout; 13105 13106 timeout = jiffies + msecs_to_jiffies(msecs); 13107 while (1) { 13108 read_state = read_physical_state(ppd->dd); 13109 if ((read_state & 0xF0) == PLS_OFFLINE) 13110 break; 13111 if (time_after(jiffies, timeout)) { 13112 dd_dev_err(ppd->dd, 13113 "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n", 13114 read_state, msecs); 13115 return -ETIMEDOUT; 13116 } 13117 usleep_range(1950, 2050); /* sleep 2ms-ish */ 13118 } 13119 13120 log_state_transition(ppd, read_state); 13121 return read_state; 13122 } 13123 13124 /* 13125 * wait_phys_link_out_of_offline - wait for any out of offline state 13126 * @ppd: port device 13127 * @msecs: the number of milliseconds to wait 13128 * 13129 * Wait up to msecs milliseconds for any out of offline physical link 13130 * state change to occur. 13131 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 13132 */ 13133 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd, 13134 int msecs) 13135 { 13136 u32 read_state; 13137 unsigned long timeout; 13138 13139 timeout = jiffies + msecs_to_jiffies(msecs); 13140 while (1) { 13141 read_state = read_physical_state(ppd->dd); 13142 if ((read_state & 0xF0) != PLS_OFFLINE) 13143 break; 13144 if (time_after(jiffies, timeout)) { 13145 dd_dev_err(ppd->dd, 13146 "timeout waiting for phy link out of offline. Read state 0x%x, %dms\n", 13147 read_state, msecs); 13148 return -ETIMEDOUT; 13149 } 13150 usleep_range(1950, 2050); /* sleep 2ms-ish */ 13151 } 13152 13153 log_state_transition(ppd, read_state); 13154 return read_state; 13155 } 13156 13157 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ 13158 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 13159 13160 #define SET_STATIC_RATE_CONTROL_SMASK(r) \ 13161 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 13162 13163 void hfi1_init_ctxt(struct send_context *sc) 13164 { 13165 if (sc) { 13166 struct hfi1_devdata *dd = sc->dd; 13167 u64 reg; 13168 u8 set = (sc->type == SC_USER ? 13169 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) : 13170 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)); 13171 reg = read_kctxt_csr(dd, sc->hw_context, 13172 SEND_CTXT_CHECK_ENABLE); 13173 if (set) 13174 CLEAR_STATIC_RATE_CONTROL_SMASK(reg); 13175 else 13176 SET_STATIC_RATE_CONTROL_SMASK(reg); 13177 write_kctxt_csr(dd, sc->hw_context, 13178 SEND_CTXT_CHECK_ENABLE, reg); 13179 } 13180 } 13181 13182 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp) 13183 { 13184 int ret = 0; 13185 u64 reg; 13186 13187 if (dd->icode != ICODE_RTL_SILICON) { 13188 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 13189 dd_dev_info(dd, "%s: tempsense not supported by HW\n", 13190 __func__); 13191 return -EINVAL; 13192 } 13193 reg = read_csr(dd, ASIC_STS_THERM); 13194 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) & 13195 ASIC_STS_THERM_CURR_TEMP_MASK); 13196 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) & 13197 ASIC_STS_THERM_LO_TEMP_MASK); 13198 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) & 13199 ASIC_STS_THERM_HI_TEMP_MASK); 13200 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) & 13201 ASIC_STS_THERM_CRIT_TEMP_MASK); 13202 /* triggers is a 3-bit value - 1 bit per trigger. */ 13203 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7); 13204 13205 return ret; 13206 } 13207 13208 /* ========================================================================= */ 13209 13210 /** 13211 * read_mod_write() - Calculate the IRQ register index and set/clear the bits 13212 * @dd: valid devdata 13213 * @src: IRQ source to determine register index from 13214 * @bits: the bits to set or clear 13215 * @set: true == set the bits, false == clear the bits 13216 * 13217 */ 13218 static void read_mod_write(struct hfi1_devdata *dd, u16 src, u64 bits, 13219 bool set) 13220 { 13221 u64 reg; 13222 u16 idx = src / BITS_PER_REGISTER; 13223 13224 spin_lock(&dd->irq_src_lock); 13225 reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); 13226 if (set) 13227 reg |= bits; 13228 else 13229 reg &= ~bits; 13230 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); 13231 spin_unlock(&dd->irq_src_lock); 13232 } 13233 13234 /** 13235 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources 13236 * @dd: valid devdata 13237 * @first: first IRQ source to set/clear 13238 * @last: last IRQ source (inclusive) to set/clear 13239 * @set: true == set the bits, false == clear the bits 13240 * 13241 * If first == last, set the exact source. 13242 */ 13243 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set) 13244 { 13245 u64 bits = 0; 13246 u64 bit; 13247 u16 src; 13248 13249 if (first > NUM_INTERRUPT_SOURCES || last > NUM_INTERRUPT_SOURCES) 13250 return -EINVAL; 13251 13252 if (last < first) 13253 return -ERANGE; 13254 13255 for (src = first; src <= last; src++) { 13256 bit = src % BITS_PER_REGISTER; 13257 /* wrapped to next register? */ 13258 if (!bit && bits) { 13259 read_mod_write(dd, src - 1, bits, set); 13260 bits = 0; 13261 } 13262 bits |= BIT_ULL(bit); 13263 } 13264 read_mod_write(dd, last, bits, set); 13265 13266 return 0; 13267 } 13268 13269 /* 13270 * Clear all interrupt sources on the chip. 13271 */ 13272 void clear_all_interrupts(struct hfi1_devdata *dd) 13273 { 13274 int i; 13275 13276 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13277 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); 13278 13279 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); 13280 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); 13281 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); 13282 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); 13283 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); 13284 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); 13285 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); 13286 for (i = 0; i < chip_send_contexts(dd); i++) 13287 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0); 13288 for (i = 0; i < chip_sdma_engines(dd); i++) 13289 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0); 13290 13291 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); 13292 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); 13293 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); 13294 } 13295 13296 /* 13297 * Remap the interrupt source from the general handler to the given MSI-X 13298 * interrupt. 13299 */ 13300 void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr) 13301 { 13302 u64 reg; 13303 int m, n; 13304 13305 /* clear from the handled mask of the general interrupt */ 13306 m = isrc / 64; 13307 n = isrc % 64; 13308 if (likely(m < CCE_NUM_INT_CSRS)) { 13309 dd->gi_mask[m] &= ~((u64)1 << n); 13310 } else { 13311 dd_dev_err(dd, "remap interrupt err\n"); 13312 return; 13313 } 13314 13315 /* direct the chip source to the given MSI-X interrupt */ 13316 m = isrc / 8; 13317 n = isrc % 8; 13318 reg = read_csr(dd, CCE_INT_MAP + (8 * m)); 13319 reg &= ~((u64)0xff << (8 * n)); 13320 reg |= ((u64)msix_intr & 0xff) << (8 * n); 13321 write_csr(dd, CCE_INT_MAP + (8 * m), reg); 13322 } 13323 13324 void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr) 13325 { 13326 /* 13327 * SDMA engine interrupt sources grouped by type, rather than 13328 * engine. Per-engine interrupts are as follows: 13329 * SDMA 13330 * SDMAProgress 13331 * SDMAIdle 13332 */ 13333 remap_intr(dd, IS_SDMA_START + engine, msix_intr); 13334 remap_intr(dd, IS_SDMA_PROGRESS_START + engine, msix_intr); 13335 remap_intr(dd, IS_SDMA_IDLE_START + engine, msix_intr); 13336 } 13337 13338 /* 13339 * Set the general handler to accept all interrupts, remap all 13340 * chip interrupts back to MSI-X 0. 13341 */ 13342 void reset_interrupts(struct hfi1_devdata *dd) 13343 { 13344 int i; 13345 13346 /* all interrupts handled by the general handler */ 13347 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13348 dd->gi_mask[i] = ~(u64)0; 13349 13350 /* all chip interrupts map to MSI-X 0 */ 13351 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13352 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13353 } 13354 13355 /** 13356 * set_up_interrupts() - Initialize the IRQ resources and state 13357 * @dd: valid devdata 13358 * 13359 */ 13360 static int set_up_interrupts(struct hfi1_devdata *dd) 13361 { 13362 int ret; 13363 13364 /* mask all interrupts */ 13365 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false); 13366 13367 /* clear all pending interrupts */ 13368 clear_all_interrupts(dd); 13369 13370 /* reset general handler mask, chip MSI-X mappings */ 13371 reset_interrupts(dd); 13372 13373 /* ask for MSI-X interrupts */ 13374 ret = msix_initialize(dd); 13375 if (ret) 13376 return ret; 13377 13378 ret = msix_request_irqs(dd); 13379 if (ret) 13380 msix_clean_up_interrupts(dd); 13381 13382 return ret; 13383 } 13384 13385 /* 13386 * Set up context values in dd. Sets: 13387 * 13388 * num_rcv_contexts - number of contexts being used 13389 * n_krcv_queues - number of kernel contexts 13390 * first_dyn_alloc_ctxt - first dynamically allocated context 13391 * in array of contexts 13392 * freectxts - number of free user contexts 13393 * num_send_contexts - number of PIO send contexts being used 13394 * num_netdev_contexts - number of contexts reserved for netdev 13395 */ 13396 static int set_up_context_variables(struct hfi1_devdata *dd) 13397 { 13398 unsigned long num_kernel_contexts; 13399 u16 num_netdev_contexts; 13400 int ret; 13401 unsigned ngroups; 13402 int rmt_count; 13403 int user_rmt_reduced; 13404 u32 n_usr_ctxts; 13405 u32 send_contexts = chip_send_contexts(dd); 13406 u32 rcv_contexts = chip_rcv_contexts(dd); 13407 13408 /* 13409 * Kernel receive contexts: 13410 * - Context 0 - control context (VL15/multicast/error) 13411 * - Context 1 - first kernel context 13412 * - Context 2 - second kernel context 13413 * ... 13414 */ 13415 if (n_krcvqs) 13416 /* 13417 * n_krcvqs is the sum of module parameter kernel receive 13418 * contexts, krcvqs[]. It does not include the control 13419 * context, so add that. 13420 */ 13421 num_kernel_contexts = n_krcvqs + 1; 13422 else 13423 num_kernel_contexts = DEFAULT_KRCVQS + 1; 13424 /* 13425 * Every kernel receive context needs an ACK send context. 13426 * one send context is allocated for each VL{0-7} and VL15 13427 */ 13428 if (num_kernel_contexts > (send_contexts - num_vls - 1)) { 13429 dd_dev_err(dd, 13430 "Reducing # kernel rcv contexts to: %d, from %lu\n", 13431 send_contexts - num_vls - 1, 13432 num_kernel_contexts); 13433 num_kernel_contexts = send_contexts - num_vls - 1; 13434 } 13435 13436 /* 13437 * User contexts: 13438 * - default to 1 user context per real (non-HT) CPU core if 13439 * num_user_contexts is negative 13440 */ 13441 if (num_user_contexts < 0) 13442 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask); 13443 else 13444 n_usr_ctxts = num_user_contexts; 13445 /* 13446 * Adjust the counts given a global max. 13447 */ 13448 if (num_kernel_contexts + n_usr_ctxts > rcv_contexts) { 13449 dd_dev_err(dd, 13450 "Reducing # user receive contexts to: %u, from %u\n", 13451 (u32)(rcv_contexts - num_kernel_contexts), 13452 n_usr_ctxts); 13453 /* recalculate */ 13454 n_usr_ctxts = rcv_contexts - num_kernel_contexts; 13455 } 13456 13457 num_netdev_contexts = 13458 hfi1_num_netdev_contexts(dd, rcv_contexts - 13459 (num_kernel_contexts + n_usr_ctxts), 13460 &node_affinity.real_cpu_mask); 13461 /* 13462 * The RMT entries are currently allocated as shown below: 13463 * 1. QOS (0 to 128 entries); 13464 * 2. FECN (num_kernel_context - 1 + num_user_contexts + 13465 * num_netdev_contexts); 13466 * 3. netdev (num_netdev_contexts). 13467 * It should be noted that FECN oversubscribe num_netdev_contexts 13468 * entries of RMT because both netdev and PSM could allocate any receive 13469 * context between dd->first_dyn_alloc_text and dd->num_rcv_contexts, 13470 * and PSM FECN must reserve an RMT entry for each possible PSM receive 13471 * context. 13472 */ 13473 rmt_count = qos_rmt_entries(dd, NULL, NULL) + (num_netdev_contexts * 2); 13474 if (HFI1_CAP_IS_KSET(TID_RDMA)) 13475 rmt_count += num_kernel_contexts - 1; 13476 if (rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) { 13477 user_rmt_reduced = NUM_MAP_ENTRIES - rmt_count; 13478 dd_dev_err(dd, 13479 "RMT size is reducing the number of user receive contexts from %u to %d\n", 13480 n_usr_ctxts, 13481 user_rmt_reduced); 13482 /* recalculate */ 13483 n_usr_ctxts = user_rmt_reduced; 13484 } 13485 13486 /* the first N are kernel contexts, the rest are user/netdev contexts */ 13487 dd->num_rcv_contexts = 13488 num_kernel_contexts + n_usr_ctxts + num_netdev_contexts; 13489 dd->n_krcv_queues = num_kernel_contexts; 13490 dd->first_dyn_alloc_ctxt = num_kernel_contexts; 13491 dd->num_netdev_contexts = num_netdev_contexts; 13492 dd->num_user_contexts = n_usr_ctxts; 13493 dd->freectxts = n_usr_ctxts; 13494 dd_dev_info(dd, 13495 "rcv contexts: chip %d, used %d (kernel %d, netdev %u, user %u)\n", 13496 rcv_contexts, 13497 (int)dd->num_rcv_contexts, 13498 (int)dd->n_krcv_queues, 13499 dd->num_netdev_contexts, 13500 dd->num_user_contexts); 13501 13502 /* 13503 * Receive array allocation: 13504 * All RcvArray entries are divided into groups of 8. This 13505 * is required by the hardware and will speed up writes to 13506 * consecutive entries by using write-combining of the entire 13507 * cacheline. 13508 * 13509 * The number of groups are evenly divided among all contexts. 13510 * any left over groups will be given to the first N user 13511 * contexts. 13512 */ 13513 dd->rcv_entries.group_size = RCV_INCREMENT; 13514 ngroups = chip_rcv_array_count(dd) / dd->rcv_entries.group_size; 13515 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts; 13516 dd->rcv_entries.nctxt_extra = ngroups - 13517 (dd->num_rcv_contexts * dd->rcv_entries.ngroups); 13518 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n", 13519 dd->rcv_entries.ngroups, 13520 dd->rcv_entries.nctxt_extra); 13521 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size > 13522 MAX_EAGER_ENTRIES * 2) { 13523 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) / 13524 dd->rcv_entries.group_size; 13525 dd_dev_info(dd, 13526 "RcvArray group count too high, change to %u\n", 13527 dd->rcv_entries.ngroups); 13528 dd->rcv_entries.nctxt_extra = 0; 13529 } 13530 /* 13531 * PIO send contexts 13532 */ 13533 ret = init_sc_pools_and_sizes(dd); 13534 if (ret >= 0) { /* success */ 13535 dd->num_send_contexts = ret; 13536 dd_dev_info( 13537 dd, 13538 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n", 13539 send_contexts, 13540 dd->num_send_contexts, 13541 dd->sc_sizes[SC_KERNEL].count, 13542 dd->sc_sizes[SC_ACK].count, 13543 dd->sc_sizes[SC_USER].count, 13544 dd->sc_sizes[SC_VL15].count); 13545 ret = 0; /* success */ 13546 } 13547 13548 return ret; 13549 } 13550 13551 /* 13552 * Set the device/port partition key table. The MAD code 13553 * will ensure that, at least, the partial management 13554 * partition key is present in the table. 13555 */ 13556 static void set_partition_keys(struct hfi1_pportdata *ppd) 13557 { 13558 struct hfi1_devdata *dd = ppd->dd; 13559 u64 reg = 0; 13560 int i; 13561 13562 dd_dev_info(dd, "Setting partition keys\n"); 13563 for (i = 0; i < hfi1_get_npkeys(dd); i++) { 13564 reg |= (ppd->pkeys[i] & 13565 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) << 13566 ((i % 4) * 13567 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT); 13568 /* Each register holds 4 PKey values. */ 13569 if ((i % 4) == 3) { 13570 write_csr(dd, RCV_PARTITION_KEY + 13571 ((i - 3) * 2), reg); 13572 reg = 0; 13573 } 13574 } 13575 13576 /* Always enable HW pkeys check when pkeys table is set */ 13577 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK); 13578 } 13579 13580 /* 13581 * These CSRs and memories are uninitialized on reset and must be 13582 * written before reading to set the ECC/parity bits. 13583 * 13584 * NOTE: All user context CSRs that are not mmaped write-only 13585 * (e.g. the TID flows) must be initialized even if the driver never 13586 * reads them. 13587 */ 13588 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd) 13589 { 13590 int i, j; 13591 13592 /* CceIntMap */ 13593 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13594 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13595 13596 /* SendCtxtCreditReturnAddr */ 13597 for (i = 0; i < chip_send_contexts(dd); i++) 13598 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13599 13600 /* PIO Send buffers */ 13601 /* SDMA Send buffers */ 13602 /* 13603 * These are not normally read, and (presently) have no method 13604 * to be read, so are not pre-initialized 13605 */ 13606 13607 /* RcvHdrAddr */ 13608 /* RcvHdrTailAddr */ 13609 /* RcvTidFlowTable */ 13610 for (i = 0; i < chip_rcv_contexts(dd); i++) { 13611 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13612 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13613 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) 13614 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0); 13615 } 13616 13617 /* RcvArray */ 13618 for (i = 0; i < chip_rcv_array_count(dd); i++) 13619 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0); 13620 13621 /* RcvQPMapTable */ 13622 for (i = 0; i < 32; i++) 13623 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13624 } 13625 13626 /* 13627 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus. 13628 */ 13629 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits, 13630 u64 ctrl_bits) 13631 { 13632 unsigned long timeout; 13633 u64 reg; 13634 13635 /* is the condition present? */ 13636 reg = read_csr(dd, CCE_STATUS); 13637 if ((reg & status_bits) == 0) 13638 return; 13639 13640 /* clear the condition */ 13641 write_csr(dd, CCE_CTRL, ctrl_bits); 13642 13643 /* wait for the condition to clear */ 13644 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT); 13645 while (1) { 13646 reg = read_csr(dd, CCE_STATUS); 13647 if ((reg & status_bits) == 0) 13648 return; 13649 if (time_after(jiffies, timeout)) { 13650 dd_dev_err(dd, 13651 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n", 13652 status_bits, reg & status_bits); 13653 return; 13654 } 13655 udelay(1); 13656 } 13657 } 13658 13659 /* set CCE CSRs to chip reset defaults */ 13660 static void reset_cce_csrs(struct hfi1_devdata *dd) 13661 { 13662 int i; 13663 13664 /* CCE_REVISION read-only */ 13665 /* CCE_REVISION2 read-only */ 13666 /* CCE_CTRL - bits clear automatically */ 13667 /* CCE_STATUS read-only, use CceCtrl to clear */ 13668 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK); 13669 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK); 13670 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK); 13671 for (i = 0; i < CCE_NUM_SCRATCH; i++) 13672 write_csr(dd, CCE_SCRATCH + (8 * i), 0); 13673 /* CCE_ERR_STATUS read-only */ 13674 write_csr(dd, CCE_ERR_MASK, 0); 13675 write_csr(dd, CCE_ERR_CLEAR, ~0ull); 13676 /* CCE_ERR_FORCE leave alone */ 13677 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++) 13678 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); 13679 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); 13680 /* CCE_PCIE_CTRL leave alone */ 13681 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) { 13682 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); 13683 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), 13684 CCE_MSIX_TABLE_UPPER_RESETCSR); 13685 } 13686 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) { 13687 /* CCE_MSIX_PBA read-only */ 13688 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); 13689 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); 13690 } 13691 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13692 write_csr(dd, CCE_INT_MAP, 0); 13693 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 13694 /* CCE_INT_STATUS read-only */ 13695 write_csr(dd, CCE_INT_MASK + (8 * i), 0); 13696 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); 13697 /* CCE_INT_FORCE leave alone */ 13698 /* CCE_INT_BLOCKED read-only */ 13699 } 13700 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++) 13701 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); 13702 } 13703 13704 /* set MISC CSRs to chip reset defaults */ 13705 static void reset_misc_csrs(struct hfi1_devdata *dd) 13706 { 13707 int i; 13708 13709 for (i = 0; i < 32; i++) { 13710 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); 13711 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); 13712 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); 13713 } 13714 /* 13715 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can 13716 * only be written 128-byte chunks 13717 */ 13718 /* init RSA engine to clear lingering errors */ 13719 write_csr(dd, MISC_CFG_RSA_CMD, 1); 13720 write_csr(dd, MISC_CFG_RSA_MU, 0); 13721 write_csr(dd, MISC_CFG_FW_CTRL, 0); 13722 /* MISC_STS_8051_DIGEST read-only */ 13723 /* MISC_STS_SBM_DIGEST read-only */ 13724 /* MISC_STS_PCIE_DIGEST read-only */ 13725 /* MISC_STS_FAB_DIGEST read-only */ 13726 /* MISC_ERR_STATUS read-only */ 13727 write_csr(dd, MISC_ERR_MASK, 0); 13728 write_csr(dd, MISC_ERR_CLEAR, ~0ull); 13729 /* MISC_ERR_FORCE leave alone */ 13730 } 13731 13732 /* set TXE CSRs to chip reset defaults */ 13733 static void reset_txe_csrs(struct hfi1_devdata *dd) 13734 { 13735 int i; 13736 13737 /* 13738 * TXE Kernel CSRs 13739 */ 13740 write_csr(dd, SEND_CTRL, 0); 13741 __cm_reset(dd, 0); /* reset CM internal state */ 13742 /* SEND_CONTEXTS read-only */ 13743 /* SEND_DMA_ENGINES read-only */ 13744 /* SEND_PIO_MEM_SIZE read-only */ 13745 /* SEND_DMA_MEM_SIZE read-only */ 13746 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); 13747 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */ 13748 /* SEND_PIO_ERR_STATUS read-only */ 13749 write_csr(dd, SEND_PIO_ERR_MASK, 0); 13750 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); 13751 /* SEND_PIO_ERR_FORCE leave alone */ 13752 /* SEND_DMA_ERR_STATUS read-only */ 13753 write_csr(dd, SEND_DMA_ERR_MASK, 0); 13754 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); 13755 /* SEND_DMA_ERR_FORCE leave alone */ 13756 /* SEND_EGRESS_ERR_STATUS read-only */ 13757 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); 13758 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); 13759 /* SEND_EGRESS_ERR_FORCE leave alone */ 13760 write_csr(dd, SEND_BTH_QP, 0); 13761 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); 13762 write_csr(dd, SEND_SC2VLT0, 0); 13763 write_csr(dd, SEND_SC2VLT1, 0); 13764 write_csr(dd, SEND_SC2VLT2, 0); 13765 write_csr(dd, SEND_SC2VLT3, 0); 13766 write_csr(dd, SEND_LEN_CHECK0, 0); 13767 write_csr(dd, SEND_LEN_CHECK1, 0); 13768 /* SEND_ERR_STATUS read-only */ 13769 write_csr(dd, SEND_ERR_MASK, 0); 13770 write_csr(dd, SEND_ERR_CLEAR, ~0ull); 13771 /* SEND_ERR_FORCE read-only */ 13772 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++) 13773 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); 13774 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++) 13775 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); 13776 for (i = 0; i < chip_send_contexts(dd) / NUM_CONTEXTS_PER_SET; i++) 13777 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); 13778 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++) 13779 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); 13780 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++) 13781 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); 13782 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); 13783 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); 13784 /* SEND_CM_CREDIT_USED_STATUS read-only */ 13785 write_csr(dd, SEND_CM_TIMER_CTRL, 0); 13786 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); 13787 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); 13788 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); 13789 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); 13790 for (i = 0; i < TXE_NUM_DATA_VL; i++) 13791 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 13792 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 13793 /* SEND_CM_CREDIT_USED_VL read-only */ 13794 /* SEND_CM_CREDIT_USED_VL15 read-only */ 13795 /* SEND_EGRESS_CTXT_STATUS read-only */ 13796 /* SEND_EGRESS_SEND_DMA_STATUS read-only */ 13797 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); 13798 /* SEND_EGRESS_ERR_INFO read-only */ 13799 /* SEND_EGRESS_ERR_SOURCE read-only */ 13800 13801 /* 13802 * TXE Per-Context CSRs 13803 */ 13804 for (i = 0; i < chip_send_contexts(dd); i++) { 13805 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 13806 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0); 13807 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13808 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0); 13809 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0); 13810 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull); 13811 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0); 13812 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0); 13813 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0); 13814 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0); 13815 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0); 13816 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0); 13817 } 13818 13819 /* 13820 * TXE Per-SDMA CSRs 13821 */ 13822 for (i = 0; i < chip_sdma_engines(dd); i++) { 13823 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 13824 /* SEND_DMA_STATUS read-only */ 13825 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0); 13826 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0); 13827 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0); 13828 /* SEND_DMA_HEAD read-only */ 13829 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0); 13830 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0); 13831 /* SEND_DMA_IDLE_CNT read-only */ 13832 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0); 13833 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0); 13834 /* SEND_DMA_DESC_FETCHED_CNT read-only */ 13835 /* SEND_DMA_ENG_ERR_STATUS read-only */ 13836 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0); 13837 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull); 13838 /* SEND_DMA_ENG_ERR_FORCE leave alone */ 13839 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0); 13840 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0); 13841 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0); 13842 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0); 13843 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0); 13844 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0); 13845 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0); 13846 } 13847 } 13848 13849 /* 13850 * Expect on entry: 13851 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0 13852 */ 13853 static void init_rbufs(struct hfi1_devdata *dd) 13854 { 13855 u64 reg; 13856 int count; 13857 13858 /* 13859 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are 13860 * clear. 13861 */ 13862 count = 0; 13863 while (1) { 13864 reg = read_csr(dd, RCV_STATUS); 13865 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 13866 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0) 13867 break; 13868 /* 13869 * Give up after 1ms - maximum wait time. 13870 * 13871 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at 13872 * 250MB/s bandwidth. Lower rate to 66% for overhead to get: 13873 * 136 KB / (66% * 250MB/s) = 844us 13874 */ 13875 if (count++ > 500) { 13876 dd_dev_err(dd, 13877 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n", 13878 __func__, reg); 13879 break; 13880 } 13881 udelay(2); /* do not busy-wait the CSR */ 13882 } 13883 13884 /* start the init - expect RcvCtrl to be 0 */ 13885 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); 13886 13887 /* 13888 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief 13889 * period after the write before RcvStatus.RxRbufInitDone is valid. 13890 * The delay in the first run through the loop below is sufficient and 13891 * required before the first read of RcvStatus.RxRbufInintDone. 13892 */ 13893 read_csr(dd, RCV_CTRL); 13894 13895 /* wait for the init to finish */ 13896 count = 0; 13897 while (1) { 13898 /* delay is required first time through - see above */ 13899 udelay(2); /* do not busy-wait the CSR */ 13900 reg = read_csr(dd, RCV_STATUS); 13901 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK)) 13902 break; 13903 13904 /* give up after 100us - slowest possible at 33MHz is 73us */ 13905 if (count++ > 50) { 13906 dd_dev_err(dd, 13907 "%s: RcvStatus.RxRbufInit not set, continuing\n", 13908 __func__); 13909 break; 13910 } 13911 } 13912 } 13913 13914 /* set RXE CSRs to chip reset defaults */ 13915 static void reset_rxe_csrs(struct hfi1_devdata *dd) 13916 { 13917 int i, j; 13918 13919 /* 13920 * RXE Kernel CSRs 13921 */ 13922 write_csr(dd, RCV_CTRL, 0); 13923 init_rbufs(dd); 13924 /* RCV_STATUS read-only */ 13925 /* RCV_CONTEXTS read-only */ 13926 /* RCV_ARRAY_CNT read-only */ 13927 /* RCV_BUF_SIZE read-only */ 13928 write_csr(dd, RCV_BTH_QP, 0); 13929 write_csr(dd, RCV_MULTICAST, 0); 13930 write_csr(dd, RCV_BYPASS, 0); 13931 write_csr(dd, RCV_VL15, 0); 13932 /* this is a clear-down */ 13933 write_csr(dd, RCV_ERR_INFO, 13934 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK); 13935 /* RCV_ERR_STATUS read-only */ 13936 write_csr(dd, RCV_ERR_MASK, 0); 13937 write_csr(dd, RCV_ERR_CLEAR, ~0ull); 13938 /* RCV_ERR_FORCE leave alone */ 13939 for (i = 0; i < 32; i++) 13940 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13941 for (i = 0; i < 4; i++) 13942 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); 13943 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++) 13944 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); 13945 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++) 13946 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); 13947 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) 13948 clear_rsm_rule(dd, i); 13949 for (i = 0; i < 32; i++) 13950 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); 13951 13952 /* 13953 * RXE Kernel and User Per-Context CSRs 13954 */ 13955 for (i = 0; i < chip_rcv_contexts(dd); i++) { 13956 /* kernel */ 13957 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0); 13958 /* RCV_CTXT_STATUS read-only */ 13959 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0); 13960 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0); 13961 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0); 13962 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13963 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0); 13964 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0); 13965 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0); 13966 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13967 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0); 13968 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0); 13969 13970 /* user */ 13971 /* RCV_HDR_TAIL read-only */ 13972 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0); 13973 /* RCV_EGR_INDEX_TAIL read-only */ 13974 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0); 13975 /* RCV_EGR_OFFSET_TAIL read-only */ 13976 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) { 13977 write_uctxt_csr(dd, i, 13978 RCV_TID_FLOW_TABLE + (8 * j), 0); 13979 } 13980 } 13981 } 13982 13983 /* 13984 * Set sc2vl tables. 13985 * 13986 * They power on to zeros, so to avoid send context errors 13987 * they need to be set: 13988 * 13989 * SC 0-7 -> VL 0-7 (respectively) 13990 * SC 15 -> VL 15 13991 * otherwise 13992 * -> VL 0 13993 */ 13994 static void init_sc2vl_tables(struct hfi1_devdata *dd) 13995 { 13996 int i; 13997 /* init per architecture spec, constrained by hardware capability */ 13998 13999 /* HFI maps sent packets */ 14000 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( 14001 0, 14002 0, 0, 1, 1, 14003 2, 2, 3, 3, 14004 4, 4, 5, 5, 14005 6, 6, 7, 7)); 14006 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( 14007 1, 14008 8, 0, 9, 0, 14009 10, 0, 11, 0, 14010 12, 0, 13, 0, 14011 14, 0, 15, 15)); 14012 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( 14013 2, 14014 16, 0, 17, 0, 14015 18, 0, 19, 0, 14016 20, 0, 21, 0, 14017 22, 0, 23, 0)); 14018 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( 14019 3, 14020 24, 0, 25, 0, 14021 26, 0, 27, 0, 14022 28, 0, 29, 0, 14023 30, 0, 31, 0)); 14024 14025 /* DC maps received packets */ 14026 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( 14027 15_0, 14028 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 14029 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15)); 14030 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( 14031 31_16, 14032 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0, 14033 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0)); 14034 14035 /* initialize the cached sc2vl values consistently with h/w */ 14036 for (i = 0; i < 32; i++) { 14037 if (i < 8 || i == 15) 14038 *((u8 *)(dd->sc2vl) + i) = (u8)i; 14039 else 14040 *((u8 *)(dd->sc2vl) + i) = 0; 14041 } 14042 } 14043 14044 /* 14045 * Read chip sizes and then reset parts to sane, disabled, values. We cannot 14046 * depend on the chip going through a power-on reset - a driver may be loaded 14047 * and unloaded many times. 14048 * 14049 * Do not write any CSR values to the chip in this routine - there may be 14050 * a reset following the (possible) FLR in this routine. 14051 * 14052 */ 14053 static int init_chip(struct hfi1_devdata *dd) 14054 { 14055 int i; 14056 int ret = 0; 14057 14058 /* 14059 * Put the HFI CSRs in a known state. 14060 * Combine this with a DC reset. 14061 * 14062 * Stop the device from doing anything while we do a 14063 * reset. We know there are no other active users of 14064 * the device since we are now in charge. Turn off 14065 * off all outbound and inbound traffic and make sure 14066 * the device does not generate any interrupts. 14067 */ 14068 14069 /* disable send contexts and SDMA engines */ 14070 write_csr(dd, SEND_CTRL, 0); 14071 for (i = 0; i < chip_send_contexts(dd); i++) 14072 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 14073 for (i = 0; i < chip_sdma_engines(dd); i++) 14074 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 14075 /* disable port (turn off RXE inbound traffic) and contexts */ 14076 write_csr(dd, RCV_CTRL, 0); 14077 for (i = 0; i < chip_rcv_contexts(dd); i++) 14078 write_csr(dd, RCV_CTXT_CTRL, 0); 14079 /* mask all interrupt sources */ 14080 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 14081 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 14082 14083 /* 14084 * DC Reset: do a full DC reset before the register clear. 14085 * A recommended length of time to hold is one CSR read, 14086 * so reread the CceDcCtrl. Then, hold the DC in reset 14087 * across the clear. 14088 */ 14089 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 14090 (void)read_csr(dd, CCE_DC_CTRL); 14091 14092 if (use_flr) { 14093 /* 14094 * A FLR will reset the SPC core and part of the PCIe. 14095 * The parts that need to be restored have already been 14096 * saved. 14097 */ 14098 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14099 14100 /* do the FLR, the DC reset will remain */ 14101 pcie_flr(dd->pcidev); 14102 14103 /* restore command and BARs */ 14104 ret = restore_pci_variables(dd); 14105 if (ret) { 14106 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14107 __func__); 14108 return ret; 14109 } 14110 14111 if (is_ax(dd)) { 14112 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14113 pcie_flr(dd->pcidev); 14114 ret = restore_pci_variables(dd); 14115 if (ret) { 14116 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14117 __func__); 14118 return ret; 14119 } 14120 } 14121 } else { 14122 dd_dev_info(dd, "Resetting CSRs with writes\n"); 14123 reset_cce_csrs(dd); 14124 reset_txe_csrs(dd); 14125 reset_rxe_csrs(dd); 14126 reset_misc_csrs(dd); 14127 } 14128 /* clear the DC reset */ 14129 write_csr(dd, CCE_DC_CTRL, 0); 14130 14131 /* Set the LED off */ 14132 setextled(dd, 0); 14133 14134 /* 14135 * Clear the QSFP reset. 14136 * An FLR enforces a 0 on all out pins. The driver does not touch 14137 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and 14138 * anything plugged constantly in reset, if it pays attention 14139 * to RESET_N. 14140 * Prime examples of this are optical cables. Set all pins high. 14141 * I2CCLK and I2CDAT will change per direction, and INT_N and 14142 * MODPRS_N are input only and their value is ignored. 14143 */ 14144 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); 14145 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); 14146 init_chip_resources(dd); 14147 return ret; 14148 } 14149 14150 static void init_early_variables(struct hfi1_devdata *dd) 14151 { 14152 int i; 14153 14154 /* assign link credit variables */ 14155 dd->vau = CM_VAU; 14156 dd->link_credits = CM_GLOBAL_CREDITS; 14157 if (is_ax(dd)) 14158 dd->link_credits--; 14159 dd->vcu = cu_to_vcu(hfi1_cu); 14160 /* enough room for 8 MAD packets plus header - 17K */ 14161 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau); 14162 if (dd->vl15_init > dd->link_credits) 14163 dd->vl15_init = dd->link_credits; 14164 14165 write_uninitialized_csrs_and_memories(dd); 14166 14167 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 14168 for (i = 0; i < dd->num_pports; i++) { 14169 struct hfi1_pportdata *ppd = &dd->pport[i]; 14170 14171 set_partition_keys(ppd); 14172 } 14173 init_sc2vl_tables(dd); 14174 } 14175 14176 static void init_kdeth_qp(struct hfi1_devdata *dd) 14177 { 14178 write_csr(dd, SEND_BTH_QP, 14179 (RVT_KDETH_QP_PREFIX & SEND_BTH_QP_KDETH_QP_MASK) << 14180 SEND_BTH_QP_KDETH_QP_SHIFT); 14181 14182 write_csr(dd, RCV_BTH_QP, 14183 (RVT_KDETH_QP_PREFIX & RCV_BTH_QP_KDETH_QP_MASK) << 14184 RCV_BTH_QP_KDETH_QP_SHIFT); 14185 } 14186 14187 /** 14188 * hfi1_get_qp_map 14189 * @dd: device data 14190 * @idx: index to read 14191 */ 14192 u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx) 14193 { 14194 u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8); 14195 14196 reg >>= (idx % 8) * 8; 14197 return reg; 14198 } 14199 14200 /** 14201 * init_qpmap_table 14202 * @dd - device data 14203 * @first_ctxt - first context 14204 * @last_ctxt - first context 14205 * 14206 * This return sets the qpn mapping table that 14207 * is indexed by qpn[8:1]. 14208 * 14209 * The routine will round robin the 256 settings 14210 * from first_ctxt to last_ctxt. 14211 * 14212 * The first/last looks ahead to having specialized 14213 * receive contexts for mgmt and bypass. Normal 14214 * verbs traffic will assumed to be on a range 14215 * of receive contexts. 14216 */ 14217 static void init_qpmap_table(struct hfi1_devdata *dd, 14218 u32 first_ctxt, 14219 u32 last_ctxt) 14220 { 14221 u64 reg = 0; 14222 u64 regno = RCV_QP_MAP_TABLE; 14223 int i; 14224 u64 ctxt = first_ctxt; 14225 14226 for (i = 0; i < 256; i++) { 14227 reg |= ctxt << (8 * (i % 8)); 14228 ctxt++; 14229 if (ctxt > last_ctxt) 14230 ctxt = first_ctxt; 14231 if (i % 8 == 7) { 14232 write_csr(dd, regno, reg); 14233 reg = 0; 14234 regno += 8; 14235 } 14236 } 14237 14238 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 14239 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK); 14240 } 14241 14242 struct rsm_map_table { 14243 u64 map[NUM_MAP_REGS]; 14244 unsigned int used; 14245 }; 14246 14247 struct rsm_rule_data { 14248 u8 offset; 14249 u8 pkt_type; 14250 u32 field1_off; 14251 u32 field2_off; 14252 u32 index1_off; 14253 u32 index1_width; 14254 u32 index2_off; 14255 u32 index2_width; 14256 u32 mask1; 14257 u32 value1; 14258 u32 mask2; 14259 u32 value2; 14260 }; 14261 14262 /* 14263 * Return an initialized RMT map table for users to fill in. OK if it 14264 * returns NULL, indicating no table. 14265 */ 14266 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd) 14267 { 14268 struct rsm_map_table *rmt; 14269 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */ 14270 14271 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL); 14272 if (rmt) { 14273 memset(rmt->map, rxcontext, sizeof(rmt->map)); 14274 rmt->used = 0; 14275 } 14276 14277 return rmt; 14278 } 14279 14280 /* 14281 * Write the final RMT map table to the chip and free the table. OK if 14282 * table is NULL. 14283 */ 14284 static void complete_rsm_map_table(struct hfi1_devdata *dd, 14285 struct rsm_map_table *rmt) 14286 { 14287 int i; 14288 14289 if (rmt) { 14290 /* write table to chip */ 14291 for (i = 0; i < NUM_MAP_REGS; i++) 14292 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); 14293 14294 /* enable RSM */ 14295 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14296 } 14297 } 14298 14299 /* Is a receive side mapping rule */ 14300 static bool has_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14301 { 14302 return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0; 14303 } 14304 14305 /* 14306 * Add a receive side mapping rule. 14307 */ 14308 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index, 14309 struct rsm_rule_data *rrd) 14310 { 14311 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 14312 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT | 14313 1ull << rule_index | /* enable bit */ 14314 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT); 14315 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 14316 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT | 14317 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT | 14318 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT | 14319 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT | 14320 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT | 14321 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT); 14322 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 14323 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT | 14324 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT | 14325 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT | 14326 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT); 14327 } 14328 14329 /* 14330 * Clear a receive side mapping rule. 14331 */ 14332 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14333 { 14334 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); 14335 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); 14336 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); 14337 } 14338 14339 /* return the number of RSM map table entries that will be used for QOS */ 14340 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 14341 unsigned int *np) 14342 { 14343 int i; 14344 unsigned int m, n; 14345 u8 max_by_vl = 0; 14346 14347 /* is QOS active at all? */ 14348 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS || 14349 num_vls == 1 || 14350 krcvqsset <= 1) 14351 goto no_qos; 14352 14353 /* determine bits for qpn */ 14354 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++) 14355 if (krcvqs[i] > max_by_vl) 14356 max_by_vl = krcvqs[i]; 14357 if (max_by_vl > 32) 14358 goto no_qos; 14359 m = ilog2(__roundup_pow_of_two(max_by_vl)); 14360 14361 /* determine bits for vl */ 14362 n = ilog2(__roundup_pow_of_two(num_vls)); 14363 14364 /* reject if too much is used */ 14365 if ((m + n) > 7) 14366 goto no_qos; 14367 14368 if (mp) 14369 *mp = m; 14370 if (np) 14371 *np = n; 14372 14373 return 1 << (m + n); 14374 14375 no_qos: 14376 if (mp) 14377 *mp = 0; 14378 if (np) 14379 *np = 0; 14380 return 0; 14381 } 14382 14383 /** 14384 * init_qos - init RX qos 14385 * @dd - device data 14386 * @rmt - RSM map table 14387 * 14388 * This routine initializes Rule 0 and the RSM map table to implement 14389 * quality of service (qos). 14390 * 14391 * If all of the limit tests succeed, qos is applied based on the array 14392 * interpretation of krcvqs where entry 0 is VL0. 14393 * 14394 * The number of vl bits (n) and the number of qpn bits (m) are computed to 14395 * feed both the RSM map table and the single rule. 14396 */ 14397 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt) 14398 { 14399 struct rsm_rule_data rrd; 14400 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m; 14401 unsigned int rmt_entries; 14402 u64 reg; 14403 14404 if (!rmt) 14405 goto bail; 14406 rmt_entries = qos_rmt_entries(dd, &m, &n); 14407 if (rmt_entries == 0) 14408 goto bail; 14409 qpns_per_vl = 1 << m; 14410 14411 /* enough room in the map table? */ 14412 rmt_entries = 1 << (m + n); 14413 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES) 14414 goto bail; 14415 14416 /* add qos entries to the the RSM map table */ 14417 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) { 14418 unsigned tctxt; 14419 14420 for (qpn = 0, tctxt = ctxt; 14421 krcvqs[i] && qpn < qpns_per_vl; qpn++) { 14422 unsigned idx, regoff, regidx; 14423 14424 /* generate the index the hardware will produce */ 14425 idx = rmt->used + ((qpn << n) ^ i); 14426 regoff = (idx % 8) * 8; 14427 regidx = idx / 8; 14428 /* replace default with context number */ 14429 reg = rmt->map[regidx]; 14430 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 14431 << regoff); 14432 reg |= (u64)(tctxt++) << regoff; 14433 rmt->map[regidx] = reg; 14434 if (tctxt == ctxt + krcvqs[i]) 14435 tctxt = ctxt; 14436 } 14437 ctxt += krcvqs[i]; 14438 } 14439 14440 rrd.offset = rmt->used; 14441 rrd.pkt_type = 2; 14442 rrd.field1_off = LRH_BTH_MATCH_OFFSET; 14443 rrd.field2_off = LRH_SC_MATCH_OFFSET; 14444 rrd.index1_off = LRH_SC_SELECT_OFFSET; 14445 rrd.index1_width = n; 14446 rrd.index2_off = QPN_SELECT_OFFSET; 14447 rrd.index2_width = m + n; 14448 rrd.mask1 = LRH_BTH_MASK; 14449 rrd.value1 = LRH_BTH_VALUE; 14450 rrd.mask2 = LRH_SC_MASK; 14451 rrd.value2 = LRH_SC_VALUE; 14452 14453 /* add rule 0 */ 14454 add_rsm_rule(dd, RSM_INS_VERBS, &rrd); 14455 14456 /* mark RSM map entries as used */ 14457 rmt->used += rmt_entries; 14458 /* map everything else to the mcast/err/vl15 context */ 14459 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT); 14460 dd->qos_shift = n + 1; 14461 return; 14462 bail: 14463 dd->qos_shift = 1; 14464 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1); 14465 } 14466 14467 static void init_fecn_handling(struct hfi1_devdata *dd, 14468 struct rsm_map_table *rmt) 14469 { 14470 struct rsm_rule_data rrd; 14471 u64 reg; 14472 int i, idx, regoff, regidx, start; 14473 u8 offset; 14474 u32 total_cnt; 14475 14476 if (HFI1_CAP_IS_KSET(TID_RDMA)) 14477 /* Exclude context 0 */ 14478 start = 1; 14479 else 14480 start = dd->first_dyn_alloc_ctxt; 14481 14482 total_cnt = dd->num_rcv_contexts - start; 14483 14484 /* there needs to be enough room in the map table */ 14485 if (rmt->used + total_cnt >= NUM_MAP_ENTRIES) { 14486 dd_dev_err(dd, "FECN handling disabled - too many contexts allocated\n"); 14487 return; 14488 } 14489 14490 /* 14491 * RSM will extract the destination context as an index into the 14492 * map table. The destination contexts are a sequential block 14493 * in the range start...num_rcv_contexts-1 (inclusive). 14494 * Map entries are accessed as offset + extracted value. Adjust 14495 * the added offset so this sequence can be placed anywhere in 14496 * the table - as long as the entries themselves do not wrap. 14497 * There are only enough bits in offset for the table size, so 14498 * start with that to allow for a "negative" offset. 14499 */ 14500 offset = (u8)(NUM_MAP_ENTRIES + rmt->used - start); 14501 14502 for (i = start, idx = rmt->used; i < dd->num_rcv_contexts; 14503 i++, idx++) { 14504 /* replace with identity mapping */ 14505 regoff = (idx % 8) * 8; 14506 regidx = idx / 8; 14507 reg = rmt->map[regidx]; 14508 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff); 14509 reg |= (u64)i << regoff; 14510 rmt->map[regidx] = reg; 14511 } 14512 14513 /* 14514 * For RSM intercept of Expected FECN packets: 14515 * o packet type 0 - expected 14516 * o match on F (bit 95), using select/match 1, and 14517 * o match on SH (bit 133), using select/match 2. 14518 * 14519 * Use index 1 to extract the 8-bit receive context from DestQP 14520 * (start at bit 64). Use that as the RSM map table index. 14521 */ 14522 rrd.offset = offset; 14523 rrd.pkt_type = 0; 14524 rrd.field1_off = 95; 14525 rrd.field2_off = 133; 14526 rrd.index1_off = 64; 14527 rrd.index1_width = 8; 14528 rrd.index2_off = 0; 14529 rrd.index2_width = 0; 14530 rrd.mask1 = 1; 14531 rrd.value1 = 1; 14532 rrd.mask2 = 1; 14533 rrd.value2 = 1; 14534 14535 /* add rule 1 */ 14536 add_rsm_rule(dd, RSM_INS_FECN, &rrd); 14537 14538 rmt->used += total_cnt; 14539 } 14540 14541 static inline bool hfi1_is_rmt_full(int start, int spare) 14542 { 14543 return (start + spare) > NUM_MAP_ENTRIES; 14544 } 14545 14546 static bool hfi1_netdev_update_rmt(struct hfi1_devdata *dd) 14547 { 14548 u8 i, j; 14549 u8 ctx_id = 0; 14550 u64 reg; 14551 u32 regoff; 14552 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd); 14553 int ctxt_count = hfi1_netdev_ctxt_count(dd); 14554 14555 /* We already have contexts mapped in RMT */ 14556 if (has_rsm_rule(dd, RSM_INS_VNIC) || has_rsm_rule(dd, RSM_INS_AIP)) { 14557 dd_dev_info(dd, "Contexts are already mapped in RMT\n"); 14558 return true; 14559 } 14560 14561 if (hfi1_is_rmt_full(rmt_start, NUM_NETDEV_MAP_ENTRIES)) { 14562 dd_dev_err(dd, "Not enough RMT entries used = %d\n", 14563 rmt_start); 14564 return false; 14565 } 14566 14567 dev_dbg(&(dd)->pcidev->dev, "RMT start = %d, end %d\n", 14568 rmt_start, 14569 rmt_start + NUM_NETDEV_MAP_ENTRIES); 14570 14571 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */ 14572 regoff = RCV_RSM_MAP_TABLE + (rmt_start / 8) * 8; 14573 reg = read_csr(dd, regoff); 14574 for (i = 0; i < NUM_NETDEV_MAP_ENTRIES; i++) { 14575 /* Update map register with netdev context */ 14576 j = (rmt_start + i) % 8; 14577 reg &= ~(0xffllu << (j * 8)); 14578 reg |= (u64)hfi1_netdev_get_ctxt(dd, ctx_id++)->ctxt << (j * 8); 14579 /* Wrap up netdev ctx index */ 14580 ctx_id %= ctxt_count; 14581 /* Write back map register */ 14582 if (j == 7 || ((i + 1) == NUM_NETDEV_MAP_ENTRIES)) { 14583 dev_dbg(&(dd)->pcidev->dev, 14584 "RMT[%d] =0x%llx\n", 14585 regoff - RCV_RSM_MAP_TABLE, reg); 14586 14587 write_csr(dd, regoff, reg); 14588 regoff += 8; 14589 if (i < (NUM_NETDEV_MAP_ENTRIES - 1)) 14590 reg = read_csr(dd, regoff); 14591 } 14592 } 14593 14594 return true; 14595 } 14596 14597 static void hfi1_enable_rsm_rule(struct hfi1_devdata *dd, 14598 int rule, struct rsm_rule_data *rrd) 14599 { 14600 if (!hfi1_netdev_update_rmt(dd)) { 14601 dd_dev_err(dd, "Failed to update RMT for RSM%d rule\n", rule); 14602 return; 14603 } 14604 14605 add_rsm_rule(dd, rule, rrd); 14606 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14607 } 14608 14609 void hfi1_init_aip_rsm(struct hfi1_devdata *dd) 14610 { 14611 /* 14612 * go through with the initialisation only if this rule actually doesn't 14613 * exist yet 14614 */ 14615 if (atomic_fetch_inc(&dd->ipoib_rsm_usr_num) == 0) { 14616 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd); 14617 struct rsm_rule_data rrd = { 14618 .offset = rmt_start, 14619 .pkt_type = IB_PACKET_TYPE, 14620 .field1_off = LRH_BTH_MATCH_OFFSET, 14621 .mask1 = LRH_BTH_MASK, 14622 .value1 = LRH_BTH_VALUE, 14623 .field2_off = BTH_DESTQP_MATCH_OFFSET, 14624 .mask2 = BTH_DESTQP_MASK, 14625 .value2 = BTH_DESTQP_VALUE, 14626 .index1_off = DETH_AIP_SQPN_SELECT_OFFSET + 14627 ilog2(NUM_NETDEV_MAP_ENTRIES), 14628 .index1_width = ilog2(NUM_NETDEV_MAP_ENTRIES), 14629 .index2_off = DETH_AIP_SQPN_SELECT_OFFSET, 14630 .index2_width = ilog2(NUM_NETDEV_MAP_ENTRIES) 14631 }; 14632 14633 hfi1_enable_rsm_rule(dd, RSM_INS_AIP, &rrd); 14634 } 14635 } 14636 14637 /* Initialize RSM for VNIC */ 14638 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd) 14639 { 14640 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd); 14641 struct rsm_rule_data rrd = { 14642 /* Add rule for vnic */ 14643 .offset = rmt_start, 14644 .pkt_type = 4, 14645 /* Match 16B packets */ 14646 .field1_off = L2_TYPE_MATCH_OFFSET, 14647 .mask1 = L2_TYPE_MASK, 14648 .value1 = L2_16B_VALUE, 14649 /* Match ETH L4 packets */ 14650 .field2_off = L4_TYPE_MATCH_OFFSET, 14651 .mask2 = L4_16B_TYPE_MASK, 14652 .value2 = L4_16B_ETH_VALUE, 14653 /* Calc context from veswid and entropy */ 14654 .index1_off = L4_16B_HDR_VESWID_OFFSET, 14655 .index1_width = ilog2(NUM_NETDEV_MAP_ENTRIES), 14656 .index2_off = L2_16B_ENTROPY_OFFSET, 14657 .index2_width = ilog2(NUM_NETDEV_MAP_ENTRIES) 14658 }; 14659 14660 hfi1_enable_rsm_rule(dd, RSM_INS_VNIC, &rrd); 14661 } 14662 14663 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd) 14664 { 14665 clear_rsm_rule(dd, RSM_INS_VNIC); 14666 } 14667 14668 void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd) 14669 { 14670 /* only actually clear the rule if it's the last user asking to do so */ 14671 if (atomic_fetch_add_unless(&dd->ipoib_rsm_usr_num, -1, 0) == 1) 14672 clear_rsm_rule(dd, RSM_INS_AIP); 14673 } 14674 14675 static int init_rxe(struct hfi1_devdata *dd) 14676 { 14677 struct rsm_map_table *rmt; 14678 u64 val; 14679 14680 /* enable all receive errors */ 14681 write_csr(dd, RCV_ERR_MASK, ~0ull); 14682 14683 rmt = alloc_rsm_map_table(dd); 14684 if (!rmt) 14685 return -ENOMEM; 14686 14687 /* set up QOS, including the QPN map table */ 14688 init_qos(dd, rmt); 14689 init_fecn_handling(dd, rmt); 14690 complete_rsm_map_table(dd, rmt); 14691 /* record number of used rsm map entries for netdev */ 14692 hfi1_netdev_set_free_rmt_idx(dd, rmt->used); 14693 kfree(rmt); 14694 14695 /* 14696 * make sure RcvCtrl.RcvWcb <= PCIe Device Control 14697 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config 14698 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one 14699 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and 14700 * Max_PayLoad_Size set to its minimum of 128. 14701 * 14702 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0 14703 * (64 bytes). Max_Payload_Size is possibly modified upward in 14704 * tune_pcie_caps() which is called after this routine. 14705 */ 14706 14707 /* Have 16 bytes (4DW) of bypass header available in header queue */ 14708 val = read_csr(dd, RCV_BYPASS); 14709 val &= ~RCV_BYPASS_HDR_SIZE_SMASK; 14710 val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) << 14711 RCV_BYPASS_HDR_SIZE_SHIFT); 14712 write_csr(dd, RCV_BYPASS, val); 14713 return 0; 14714 } 14715 14716 static void init_other(struct hfi1_devdata *dd) 14717 { 14718 /* enable all CCE errors */ 14719 write_csr(dd, CCE_ERR_MASK, ~0ull); 14720 /* enable *some* Misc errors */ 14721 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); 14722 /* enable all DC errors, except LCB */ 14723 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); 14724 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); 14725 } 14726 14727 /* 14728 * Fill out the given AU table using the given CU. A CU is defined in terms 14729 * AUs. The table is a an encoding: given the index, how many AUs does that 14730 * represent? 14731 * 14732 * NOTE: Assumes that the register layout is the same for the 14733 * local and remote tables. 14734 */ 14735 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu, 14736 u32 csr0to3, u32 csr4to7) 14737 { 14738 write_csr(dd, csr0to3, 14739 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT | 14740 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT | 14741 2ull * cu << 14742 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT | 14743 4ull * cu << 14744 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT); 14745 write_csr(dd, csr4to7, 14746 8ull * cu << 14747 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT | 14748 16ull * cu << 14749 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT | 14750 32ull * cu << 14751 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT | 14752 64ull * cu << 14753 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT); 14754 } 14755 14756 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14757 { 14758 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3, 14759 SEND_CM_LOCAL_AU_TABLE4_TO7); 14760 } 14761 14762 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14763 { 14764 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3, 14765 SEND_CM_REMOTE_AU_TABLE4_TO7); 14766 } 14767 14768 static void init_txe(struct hfi1_devdata *dd) 14769 { 14770 int i; 14771 14772 /* enable all PIO, SDMA, general, and Egress errors */ 14773 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); 14774 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); 14775 write_csr(dd, SEND_ERR_MASK, ~0ull); 14776 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); 14777 14778 /* enable all per-context and per-SDMA engine errors */ 14779 for (i = 0; i < chip_send_contexts(dd); i++) 14780 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull); 14781 for (i = 0; i < chip_sdma_engines(dd); i++) 14782 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull); 14783 14784 /* set the local CU to AU mapping */ 14785 assign_local_cm_au_table(dd, dd->vcu); 14786 14787 /* 14788 * Set reasonable default for Credit Return Timer 14789 * Don't set on Simulator - causes it to choke. 14790 */ 14791 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 14792 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); 14793 } 14794 14795 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14796 u16 jkey) 14797 { 14798 u8 hw_ctxt; 14799 u64 reg; 14800 14801 if (!rcd || !rcd->sc) 14802 return -EINVAL; 14803 14804 hw_ctxt = rcd->sc->hw_context; 14805 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */ 14806 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) << 14807 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT); 14808 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */ 14809 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY)) 14810 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK; 14811 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg); 14812 /* 14813 * Enable send-side J_KEY integrity check, unless this is A0 h/w 14814 */ 14815 if (!is_ax(dd)) { 14816 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14817 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14818 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14819 } 14820 14821 /* Enable J_KEY check on receive context. */ 14822 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK | 14823 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) << 14824 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT); 14825 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg); 14826 14827 return 0; 14828 } 14829 14830 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 14831 { 14832 u8 hw_ctxt; 14833 u64 reg; 14834 14835 if (!rcd || !rcd->sc) 14836 return -EINVAL; 14837 14838 hw_ctxt = rcd->sc->hw_context; 14839 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0); 14840 /* 14841 * Disable send-side J_KEY integrity check, unless this is A0 h/w. 14842 * This check would not have been enabled for A0 h/w, see 14843 * set_ctxt_jkey(). 14844 */ 14845 if (!is_ax(dd)) { 14846 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14847 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14848 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14849 } 14850 /* Turn off the J_KEY on the receive side */ 14851 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0); 14852 14853 return 0; 14854 } 14855 14856 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14857 u16 pkey) 14858 { 14859 u8 hw_ctxt; 14860 u64 reg; 14861 14862 if (!rcd || !rcd->sc) 14863 return -EINVAL; 14864 14865 hw_ctxt = rcd->sc->hw_context; 14866 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) << 14867 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT; 14868 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg); 14869 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14870 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14871 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK; 14872 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14873 14874 return 0; 14875 } 14876 14877 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt) 14878 { 14879 u8 hw_ctxt; 14880 u64 reg; 14881 14882 if (!ctxt || !ctxt->sc) 14883 return -EINVAL; 14884 14885 hw_ctxt = ctxt->sc->hw_context; 14886 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14887 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14888 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14889 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0); 14890 14891 return 0; 14892 } 14893 14894 /* 14895 * Start doing the clean up the the chip. Our clean up happens in multiple 14896 * stages and this is just the first. 14897 */ 14898 void hfi1_start_cleanup(struct hfi1_devdata *dd) 14899 { 14900 aspm_exit(dd); 14901 free_cntrs(dd); 14902 free_rcverr(dd); 14903 finish_chip_resources(dd); 14904 } 14905 14906 #define HFI_BASE_GUID(dev) \ 14907 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT)) 14908 14909 /* 14910 * Information can be shared between the two HFIs on the same ASIC 14911 * in the same OS. This function finds the peer device and sets 14912 * up a shared structure. 14913 */ 14914 static int init_asic_data(struct hfi1_devdata *dd) 14915 { 14916 unsigned long index; 14917 struct hfi1_devdata *peer; 14918 struct hfi1_asic_data *asic_data; 14919 int ret = 0; 14920 14921 /* pre-allocate the asic structure in case we are the first device */ 14922 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL); 14923 if (!asic_data) 14924 return -ENOMEM; 14925 14926 xa_lock_irq(&hfi1_dev_table); 14927 /* Find our peer device */ 14928 xa_for_each(&hfi1_dev_table, index, peer) { 14929 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(peer)) && 14930 dd->unit != peer->unit) 14931 break; 14932 } 14933 14934 if (peer) { 14935 /* use already allocated structure */ 14936 dd->asic_data = peer->asic_data; 14937 kfree(asic_data); 14938 } else { 14939 dd->asic_data = asic_data; 14940 mutex_init(&dd->asic_data->asic_resource_mutex); 14941 } 14942 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */ 14943 xa_unlock_irq(&hfi1_dev_table); 14944 14945 /* first one through - set up i2c devices */ 14946 if (!peer) 14947 ret = set_up_i2c(dd, dd->asic_data); 14948 14949 return ret; 14950 } 14951 14952 /* 14953 * Set dd->boardname. Use a generic name if a name is not returned from 14954 * EFI variable space. 14955 * 14956 * Return 0 on success, -ENOMEM if space could not be allocated. 14957 */ 14958 static int obtain_boardname(struct hfi1_devdata *dd) 14959 { 14960 /* generic board description */ 14961 const char generic[] = 14962 "Intel Omni-Path Host Fabric Interface Adapter 100 Series"; 14963 unsigned long size; 14964 int ret; 14965 14966 ret = read_hfi1_efi_var(dd, "description", &size, 14967 (void **)&dd->boardname); 14968 if (ret) { 14969 dd_dev_info(dd, "Board description not found\n"); 14970 /* use generic description */ 14971 dd->boardname = kstrdup(generic, GFP_KERNEL); 14972 if (!dd->boardname) 14973 return -ENOMEM; 14974 } 14975 return 0; 14976 } 14977 14978 /* 14979 * Check the interrupt registers to make sure that they are mapped correctly. 14980 * It is intended to help user identify any mismapping by VMM when the driver 14981 * is running in a VM. This function should only be called before interrupt 14982 * is set up properly. 14983 * 14984 * Return 0 on success, -EINVAL on failure. 14985 */ 14986 static int check_int_registers(struct hfi1_devdata *dd) 14987 { 14988 u64 reg; 14989 u64 all_bits = ~(u64)0; 14990 u64 mask; 14991 14992 /* Clear CceIntMask[0] to avoid raising any interrupts */ 14993 mask = read_csr(dd, CCE_INT_MASK); 14994 write_csr(dd, CCE_INT_MASK, 0ull); 14995 reg = read_csr(dd, CCE_INT_MASK); 14996 if (reg) 14997 goto err_exit; 14998 14999 /* Clear all interrupt status bits */ 15000 write_csr(dd, CCE_INT_CLEAR, all_bits); 15001 reg = read_csr(dd, CCE_INT_STATUS); 15002 if (reg) 15003 goto err_exit; 15004 15005 /* Set all interrupt status bits */ 15006 write_csr(dd, CCE_INT_FORCE, all_bits); 15007 reg = read_csr(dd, CCE_INT_STATUS); 15008 if (reg != all_bits) 15009 goto err_exit; 15010 15011 /* Restore the interrupt mask */ 15012 write_csr(dd, CCE_INT_CLEAR, all_bits); 15013 write_csr(dd, CCE_INT_MASK, mask); 15014 15015 return 0; 15016 err_exit: 15017 write_csr(dd, CCE_INT_MASK, mask); 15018 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n"); 15019 return -EINVAL; 15020 } 15021 15022 /** 15023 * hfi1_init_dd() - Initialize most of the dd structure. 15024 * @dev: the pci_dev for hfi1_ib device 15025 * @ent: pci_device_id struct for this dev 15026 * 15027 * This is global, and is called directly at init to set up the 15028 * chip-specific function pointers for later use. 15029 */ 15030 int hfi1_init_dd(struct hfi1_devdata *dd) 15031 { 15032 struct pci_dev *pdev = dd->pcidev; 15033 struct hfi1_pportdata *ppd; 15034 u64 reg; 15035 int i, ret; 15036 static const char * const inames[] = { /* implementation names */ 15037 "RTL silicon", 15038 "RTL VCS simulation", 15039 "RTL FPGA emulation", 15040 "Functional simulator" 15041 }; 15042 struct pci_dev *parent = pdev->bus->self; 15043 u32 sdma_engines = chip_sdma_engines(dd); 15044 15045 ppd = dd->pport; 15046 for (i = 0; i < dd->num_pports; i++, ppd++) { 15047 int vl; 15048 /* init common fields */ 15049 hfi1_init_pportdata(pdev, ppd, dd, 0, 1); 15050 /* DC supports 4 link widths */ 15051 ppd->link_width_supported = 15052 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X | 15053 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X; 15054 ppd->link_width_downgrade_supported = 15055 ppd->link_width_supported; 15056 /* start out enabling only 4X */ 15057 ppd->link_width_enabled = OPA_LINK_WIDTH_4X; 15058 ppd->link_width_downgrade_enabled = 15059 ppd->link_width_downgrade_supported; 15060 /* link width active is 0 when link is down */ 15061 /* link width downgrade active is 0 when link is down */ 15062 15063 if (num_vls < HFI1_MIN_VLS_SUPPORTED || 15064 num_vls > HFI1_MAX_VLS_SUPPORTED) { 15065 dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n", 15066 num_vls, HFI1_MAX_VLS_SUPPORTED); 15067 num_vls = HFI1_MAX_VLS_SUPPORTED; 15068 } 15069 ppd->vls_supported = num_vls; 15070 ppd->vls_operational = ppd->vls_supported; 15071 /* Set the default MTU. */ 15072 for (vl = 0; vl < num_vls; vl++) 15073 dd->vld[vl].mtu = hfi1_max_mtu; 15074 dd->vld[15].mtu = MAX_MAD_PACKET; 15075 /* 15076 * Set the initial values to reasonable default, will be set 15077 * for real when link is up. 15078 */ 15079 ppd->overrun_threshold = 0x4; 15080 ppd->phy_error_threshold = 0xf; 15081 ppd->port_crc_mode_enabled = link_crc_mask; 15082 /* initialize supported LTP CRC mode */ 15083 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 15084 /* initialize enabled LTP CRC mode */ 15085 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4; 15086 /* start in offline */ 15087 ppd->host_link_state = HLS_DN_OFFLINE; 15088 init_vl_arb_caches(ppd); 15089 } 15090 15091 /* 15092 * Do remaining PCIe setup and save PCIe values in dd. 15093 * Any error printing is already done by the init code. 15094 * On return, we have the chip mapped. 15095 */ 15096 ret = hfi1_pcie_ddinit(dd, pdev); 15097 if (ret < 0) 15098 goto bail_free; 15099 15100 /* Save PCI space registers to rewrite after device reset */ 15101 ret = save_pci_variables(dd); 15102 if (ret < 0) 15103 goto bail_cleanup; 15104 15105 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT) 15106 & CCE_REVISION_CHIP_REV_MAJOR_MASK; 15107 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT) 15108 & CCE_REVISION_CHIP_REV_MINOR_MASK; 15109 15110 /* 15111 * Check interrupt registers mapping if the driver has no access to 15112 * the upstream component. In this case, it is likely that the driver 15113 * is running in a VM. 15114 */ 15115 if (!parent) { 15116 ret = check_int_registers(dd); 15117 if (ret) 15118 goto bail_cleanup; 15119 } 15120 15121 /* 15122 * obtain the hardware ID - NOT related to unit, which is a 15123 * software enumeration 15124 */ 15125 reg = read_csr(dd, CCE_REVISION2); 15126 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT) 15127 & CCE_REVISION2_HFI_ID_MASK; 15128 /* the variable size will remove unwanted bits */ 15129 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT; 15130 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT; 15131 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n", 15132 dd->icode < ARRAY_SIZE(inames) ? 15133 inames[dd->icode] : "unknown", (int)dd->irev); 15134 15135 /* speeds the hardware can support */ 15136 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G; 15137 /* speeds allowed to run at */ 15138 dd->pport->link_speed_enabled = dd->pport->link_speed_supported; 15139 /* give a reasonable active value, will be set on link up */ 15140 dd->pport->link_speed_active = OPA_LINK_SPEED_25G; 15141 15142 /* fix up link widths for emulation _p */ 15143 ppd = dd->pport; 15144 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) { 15145 ppd->link_width_supported = 15146 ppd->link_width_enabled = 15147 ppd->link_width_downgrade_supported = 15148 ppd->link_width_downgrade_enabled = 15149 OPA_LINK_WIDTH_1X; 15150 } 15151 /* insure num_vls isn't larger than number of sdma engines */ 15152 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > sdma_engines) { 15153 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n", 15154 num_vls, sdma_engines); 15155 num_vls = sdma_engines; 15156 ppd->vls_supported = sdma_engines; 15157 ppd->vls_operational = ppd->vls_supported; 15158 } 15159 15160 /* 15161 * Convert the ns parameter to the 64 * cclocks used in the CSR. 15162 * Limit the max if larger than the field holds. If timeout is 15163 * non-zero, then the calculated field will be at least 1. 15164 * 15165 * Must be after icode is set up - the cclock rate depends 15166 * on knowing the hardware being used. 15167 */ 15168 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64; 15169 if (dd->rcv_intr_timeout_csr > 15170 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK) 15171 dd->rcv_intr_timeout_csr = 15172 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK; 15173 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout) 15174 dd->rcv_intr_timeout_csr = 1; 15175 15176 /* needs to be done before we look for the peer device */ 15177 read_guid(dd); 15178 15179 /* set up shared ASIC data with peer device */ 15180 ret = init_asic_data(dd); 15181 if (ret) 15182 goto bail_cleanup; 15183 15184 /* obtain chip sizes, reset chip CSRs */ 15185 ret = init_chip(dd); 15186 if (ret) 15187 goto bail_cleanup; 15188 15189 /* read in the PCIe link speed information */ 15190 ret = pcie_speeds(dd); 15191 if (ret) 15192 goto bail_cleanup; 15193 15194 /* call before get_platform_config(), after init_chip_resources() */ 15195 ret = eprom_init(dd); 15196 if (ret) 15197 goto bail_free_rcverr; 15198 15199 /* Needs to be called before hfi1_firmware_init */ 15200 get_platform_config(dd); 15201 15202 /* read in firmware */ 15203 ret = hfi1_firmware_init(dd); 15204 if (ret) 15205 goto bail_cleanup; 15206 15207 /* 15208 * In general, the PCIe Gen3 transition must occur after the 15209 * chip has been idled (so it won't initiate any PCIe transactions 15210 * e.g. an interrupt) and before the driver changes any registers 15211 * (the transition will reset the registers). 15212 * 15213 * In particular, place this call after: 15214 * - init_chip() - the chip will not initiate any PCIe transactions 15215 * - pcie_speeds() - reads the current link speed 15216 * - hfi1_firmware_init() - the needed firmware is ready to be 15217 * downloaded 15218 */ 15219 ret = do_pcie_gen3_transition(dd); 15220 if (ret) 15221 goto bail_cleanup; 15222 15223 /* 15224 * This should probably occur in hfi1_pcie_init(), but historically 15225 * occurs after the do_pcie_gen3_transition() code. 15226 */ 15227 tune_pcie_caps(dd); 15228 15229 /* start setting dd values and adjusting CSRs */ 15230 init_early_variables(dd); 15231 15232 parse_platform_config(dd); 15233 15234 ret = obtain_boardname(dd); 15235 if (ret) 15236 goto bail_cleanup; 15237 15238 snprintf(dd->boardversion, BOARD_VERS_MAX, 15239 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n", 15240 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN, 15241 (u32)dd->majrev, 15242 (u32)dd->minrev, 15243 (dd->revision >> CCE_REVISION_SW_SHIFT) 15244 & CCE_REVISION_SW_MASK); 15245 15246 /* alloc netdev data */ 15247 if (hfi1_netdev_alloc(dd)) 15248 goto bail_cleanup; 15249 15250 ret = set_up_context_variables(dd); 15251 if (ret) 15252 goto bail_cleanup; 15253 15254 /* set initial RXE CSRs */ 15255 ret = init_rxe(dd); 15256 if (ret) 15257 goto bail_cleanup; 15258 15259 /* set initial TXE CSRs */ 15260 init_txe(dd); 15261 /* set initial non-RXE, non-TXE CSRs */ 15262 init_other(dd); 15263 /* set up KDETH QP prefix in both RX and TX CSRs */ 15264 init_kdeth_qp(dd); 15265 15266 ret = hfi1_dev_affinity_init(dd); 15267 if (ret) 15268 goto bail_cleanup; 15269 15270 /* send contexts must be set up before receive contexts */ 15271 ret = init_send_contexts(dd); 15272 if (ret) 15273 goto bail_cleanup; 15274 15275 ret = hfi1_create_kctxts(dd); 15276 if (ret) 15277 goto bail_cleanup; 15278 15279 /* 15280 * Initialize aspm, to be done after gen3 transition and setting up 15281 * contexts and before enabling interrupts 15282 */ 15283 aspm_init(dd); 15284 15285 ret = init_pervl_scs(dd); 15286 if (ret) 15287 goto bail_cleanup; 15288 15289 /* sdma init */ 15290 for (i = 0; i < dd->num_pports; ++i) { 15291 ret = sdma_init(dd, i); 15292 if (ret) 15293 goto bail_cleanup; 15294 } 15295 15296 /* use contexts created by hfi1_create_kctxts */ 15297 ret = set_up_interrupts(dd); 15298 if (ret) 15299 goto bail_cleanup; 15300 15301 ret = hfi1_comp_vectors_set_up(dd); 15302 if (ret) 15303 goto bail_clear_intr; 15304 15305 /* set up LCB access - must be after set_up_interrupts() */ 15306 init_lcb_access(dd); 15307 15308 /* 15309 * Serial number is created from the base guid: 15310 * [27:24] = base guid [38:35] 15311 * [23: 0] = base guid [23: 0] 15312 */ 15313 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n", 15314 (dd->base_guid & 0xFFFFFF) | 15315 ((dd->base_guid >> 11) & 0xF000000)); 15316 15317 dd->oui1 = dd->base_guid >> 56 & 0xFF; 15318 dd->oui2 = dd->base_guid >> 48 & 0xFF; 15319 dd->oui3 = dd->base_guid >> 40 & 0xFF; 15320 15321 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */ 15322 if (ret) 15323 goto bail_clear_intr; 15324 15325 thermal_init(dd); 15326 15327 ret = init_cntrs(dd); 15328 if (ret) 15329 goto bail_clear_intr; 15330 15331 ret = init_rcverr(dd); 15332 if (ret) 15333 goto bail_free_cntrs; 15334 15335 init_completion(&dd->user_comp); 15336 15337 /* The user refcount starts with one to inidicate an active device */ 15338 atomic_set(&dd->user_refcount, 1); 15339 15340 goto bail; 15341 15342 bail_free_rcverr: 15343 free_rcverr(dd); 15344 bail_free_cntrs: 15345 free_cntrs(dd); 15346 bail_clear_intr: 15347 hfi1_comp_vectors_clean_up(dd); 15348 msix_clean_up_interrupts(dd); 15349 bail_cleanup: 15350 hfi1_netdev_free(dd); 15351 hfi1_pcie_ddcleanup(dd); 15352 bail_free: 15353 hfi1_free_devdata(dd); 15354 bail: 15355 return ret; 15356 } 15357 15358 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate, 15359 u32 dw_len) 15360 { 15361 u32 delta_cycles; 15362 u32 current_egress_rate = ppd->current_egress_rate; 15363 /* rates here are in units of 10^6 bits/sec */ 15364 15365 if (desired_egress_rate == -1) 15366 return 0; /* shouldn't happen */ 15367 15368 if (desired_egress_rate >= current_egress_rate) 15369 return 0; /* we can't help go faster, only slower */ 15370 15371 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) - 15372 egress_cycles(dw_len * 4, current_egress_rate); 15373 15374 return (u16)delta_cycles; 15375 } 15376 15377 /** 15378 * create_pbc - build a pbc for transmission 15379 * @flags: special case flags or-ed in built pbc 15380 * @srate: static rate 15381 * @vl: vl 15382 * @dwlen: dword length (header words + data words + pbc words) 15383 * 15384 * Create a PBC with the given flags, rate, VL, and length. 15385 * 15386 * NOTE: The PBC created will not insert any HCRC - all callers but one are 15387 * for verbs, which does not use this PSM feature. The lone other caller 15388 * is for the diagnostic interface which calls this if the user does not 15389 * supply their own PBC. 15390 */ 15391 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, 15392 u32 dw_len) 15393 { 15394 u64 pbc, delay = 0; 15395 15396 if (unlikely(srate_mbs)) 15397 delay = delay_cycles(ppd, srate_mbs, dw_len); 15398 15399 pbc = flags 15400 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT) 15401 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT) 15402 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT 15403 | (dw_len & PBC_LENGTH_DWS_MASK) 15404 << PBC_LENGTH_DWS_SHIFT; 15405 15406 return pbc; 15407 } 15408 15409 #define SBUS_THERMAL 0x4f 15410 #define SBUS_THERM_MONITOR_MODE 0x1 15411 15412 #define THERM_FAILURE(dev, ret, reason) \ 15413 dd_dev_err((dd), \ 15414 "Thermal sensor initialization failed: %s (%d)\n", \ 15415 (reason), (ret)) 15416 15417 /* 15418 * Initialize the thermal sensor. 15419 * 15420 * After initialization, enable polling of thermal sensor through 15421 * SBus interface. In order for this to work, the SBus Master 15422 * firmware has to be loaded due to the fact that the HW polling 15423 * logic uses SBus interrupts, which are not supported with 15424 * default firmware. Otherwise, no data will be returned through 15425 * the ASIC_STS_THERM CSR. 15426 */ 15427 static int thermal_init(struct hfi1_devdata *dd) 15428 { 15429 int ret = 0; 15430 15431 if (dd->icode != ICODE_RTL_SILICON || 15432 check_chip_resource(dd, CR_THERM_INIT, NULL)) 15433 return ret; 15434 15435 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 15436 if (ret) { 15437 THERM_FAILURE(dd, ret, "Acquire SBus"); 15438 return ret; 15439 } 15440 15441 dd_dev_info(dd, "Initializing thermal sensor\n"); 15442 /* Disable polling of thermal readings */ 15443 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 15444 msleep(100); 15445 /* Thermal Sensor Initialization */ 15446 /* Step 1: Reset the Thermal SBus Receiver */ 15447 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15448 RESET_SBUS_RECEIVER, 0); 15449 if (ret) { 15450 THERM_FAILURE(dd, ret, "Bus Reset"); 15451 goto done; 15452 } 15453 /* Step 2: Set Reset bit in Thermal block */ 15454 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15455 WRITE_SBUS_RECEIVER, 0x1); 15456 if (ret) { 15457 THERM_FAILURE(dd, ret, "Therm Block Reset"); 15458 goto done; 15459 } 15460 /* Step 3: Write clock divider value (100MHz -> 2MHz) */ 15461 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1, 15462 WRITE_SBUS_RECEIVER, 0x32); 15463 if (ret) { 15464 THERM_FAILURE(dd, ret, "Write Clock Div"); 15465 goto done; 15466 } 15467 /* Step 4: Select temperature mode */ 15468 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3, 15469 WRITE_SBUS_RECEIVER, 15470 SBUS_THERM_MONITOR_MODE); 15471 if (ret) { 15472 THERM_FAILURE(dd, ret, "Write Mode Sel"); 15473 goto done; 15474 } 15475 /* Step 5: De-assert block reset and start conversion */ 15476 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15477 WRITE_SBUS_RECEIVER, 0x2); 15478 if (ret) { 15479 THERM_FAILURE(dd, ret, "Write Reset Deassert"); 15480 goto done; 15481 } 15482 /* Step 5.1: Wait for first conversion (21.5ms per spec) */ 15483 msleep(22); 15484 15485 /* Enable polling of thermal readings */ 15486 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 15487 15488 /* Set initialized flag */ 15489 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0); 15490 if (ret) 15491 THERM_FAILURE(dd, ret, "Unable to set thermal init flag"); 15492 15493 done: 15494 release_chip_resource(dd, CR_SBUS); 15495 return ret; 15496 } 15497 15498 static void handle_temp_err(struct hfi1_devdata *dd) 15499 { 15500 struct hfi1_pportdata *ppd = &dd->pport[0]; 15501 /* 15502 * Thermal Critical Interrupt 15503 * Put the device into forced freeze mode, take link down to 15504 * offline, and put DC into reset. 15505 */ 15506 dd_dev_emerg(dd, 15507 "Critical temperature reached! Forcing device into freeze mode!\n"); 15508 dd->flags |= HFI1_FORCED_FREEZE; 15509 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT); 15510 /* 15511 * Shut DC down as much and as quickly as possible. 15512 * 15513 * Step 1: Take the link down to OFFLINE. This will cause the 15514 * 8051 to put the Serdes in reset. However, we don't want to 15515 * go through the entire link state machine since we want to 15516 * shutdown ASAP. Furthermore, this is not a graceful shutdown 15517 * but rather an attempt to save the chip. 15518 * Code below is almost the same as quiet_serdes() but avoids 15519 * all the extra work and the sleeps. 15520 */ 15521 ppd->driver_link_ready = 0; 15522 ppd->link_enabled = 0; 15523 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) | 15524 PLS_OFFLINE); 15525 /* 15526 * Step 2: Shutdown LCB and 8051 15527 * After shutdown, do not restore DC_CFG_RESET value. 15528 */ 15529 dc_shutdown(dd); 15530 } 15531