1 /* 2 * Copyright(c) 2015 - 2020 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 /* 49 * This file contains all of the code that is specific to the HFI chip 50 */ 51 52 #include <linux/pci.h> 53 #include <linux/delay.h> 54 #include <linux/interrupt.h> 55 #include <linux/module.h> 56 57 #include "hfi.h" 58 #include "trace.h" 59 #include "mad.h" 60 #include "pio.h" 61 #include "sdma.h" 62 #include "eprom.h" 63 #include "efivar.h" 64 #include "platform.h" 65 #include "aspm.h" 66 #include "affinity.h" 67 #include "debugfs.h" 68 #include "fault.h" 69 #include "netdev.h" 70 71 uint num_vls = HFI1_MAX_VLS_SUPPORTED; 72 module_param(num_vls, uint, S_IRUGO); 73 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 74 75 /* 76 * Default time to aggregate two 10K packets from the idle state 77 * (timer not running). The timer starts at the end of the first packet, 78 * so only the time for one 10K packet and header plus a bit extra is needed. 79 * 10 * 1024 + 64 header byte = 10304 byte 80 * 10304 byte / 12.5 GB/s = 824.32ns 81 */ 82 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */ 83 module_param(rcv_intr_timeout, uint, S_IRUGO); 84 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns"); 85 86 uint rcv_intr_count = 16; /* same as qib */ 87 module_param(rcv_intr_count, uint, S_IRUGO); 88 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count"); 89 90 ushort link_crc_mask = SUPPORTED_CRCS; 91 module_param(link_crc_mask, ushort, S_IRUGO); 92 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link"); 93 94 uint loopback; 95 module_param_named(loopback, loopback, uint, S_IRUGO); 96 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable"); 97 98 /* Other driver tunables */ 99 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/ 100 static ushort crc_14b_sideband = 1; 101 static uint use_flr = 1; 102 uint quick_linkup; /* skip LNI */ 103 104 struct flag_table { 105 u64 flag; /* the flag */ 106 char *str; /* description string */ 107 u16 extra; /* extra information */ 108 u16 unused0; 109 u32 unused1; 110 }; 111 112 /* str must be a string constant */ 113 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra} 114 #define FLAG_ENTRY0(str, flag) {flag, str, 0} 115 116 /* Send Error Consequences */ 117 #define SEC_WRITE_DROPPED 0x1 118 #define SEC_PACKET_DROPPED 0x2 119 #define SEC_SC_HALTED 0x4 /* per-context only */ 120 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */ 121 122 #define DEFAULT_KRCVQS 2 123 #define MIN_KERNEL_KCTXTS 2 124 #define FIRST_KERNEL_KCTXT 1 125 126 /* 127 * RSM instance allocation 128 * 0 - User Fecn Handling 129 * 1 - Vnic 130 * 2 - AIP 131 * 3 - Verbs 132 */ 133 #define RSM_INS_FECN 0 134 #define RSM_INS_VNIC 1 135 #define RSM_INS_AIP 2 136 #define RSM_INS_VERBS 3 137 138 /* Bit offset into the GUID which carries HFI id information */ 139 #define GUID_HFI_INDEX_SHIFT 39 140 141 /* extract the emulation revision */ 142 #define emulator_rev(dd) ((dd)->irev >> 8) 143 /* parallel and serial emulation versions are 3 and 4 respectively */ 144 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3) 145 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4) 146 147 /* RSM fields for Verbs */ 148 /* packet type */ 149 #define IB_PACKET_TYPE 2ull 150 #define QW_SHIFT 6ull 151 /* QPN[7..1] */ 152 #define QPN_WIDTH 7ull 153 154 /* LRH.BTH: QW 0, OFFSET 48 - for match */ 155 #define LRH_BTH_QW 0ull 156 #define LRH_BTH_BIT_OFFSET 48ull 157 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off)) 158 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET) 159 #define LRH_BTH_SELECT 160 #define LRH_BTH_MASK 3ull 161 #define LRH_BTH_VALUE 2ull 162 163 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */ 164 #define LRH_SC_QW 0ull 165 #define LRH_SC_BIT_OFFSET 56ull 166 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off)) 167 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET) 168 #define LRH_SC_MASK 128ull 169 #define LRH_SC_VALUE 0ull 170 171 /* SC[n..0] QW 0, OFFSET 60 - for select */ 172 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull)) 173 174 /* QPN[m+n:1] QW 1, OFFSET 1 */ 175 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull)) 176 177 /* RSM fields for AIP */ 178 /* LRH.BTH above is reused for this rule */ 179 180 /* BTH.DESTQP: QW 1, OFFSET 16 for match */ 181 #define BTH_DESTQP_QW 1ull 182 #define BTH_DESTQP_BIT_OFFSET 16ull 183 #define BTH_DESTQP_OFFSET(off) ((BTH_DESTQP_QW << QW_SHIFT) | (off)) 184 #define BTH_DESTQP_MATCH_OFFSET BTH_DESTQP_OFFSET(BTH_DESTQP_BIT_OFFSET) 185 #define BTH_DESTQP_MASK 0xFFull 186 #define BTH_DESTQP_VALUE 0x81ull 187 188 /* DETH.SQPN: QW 1 Offset 56 for select */ 189 /* We use 8 most significant Soure QPN bits as entropy fpr AIP */ 190 #define DETH_AIP_SQPN_QW 3ull 191 #define DETH_AIP_SQPN_BIT_OFFSET 56ull 192 #define DETH_AIP_SQPN_OFFSET(off) ((DETH_AIP_SQPN_QW << QW_SHIFT) | (off)) 193 #define DETH_AIP_SQPN_SELECT_OFFSET \ 194 DETH_AIP_SQPN_OFFSET(DETH_AIP_SQPN_BIT_OFFSET) 195 196 /* RSM fields for Vnic */ 197 /* L2_TYPE: QW 0, OFFSET 61 - for match */ 198 #define L2_TYPE_QW 0ull 199 #define L2_TYPE_BIT_OFFSET 61ull 200 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off)) 201 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET) 202 #define L2_TYPE_MASK 3ull 203 #define L2_16B_VALUE 2ull 204 205 /* L4_TYPE QW 1, OFFSET 0 - for match */ 206 #define L4_TYPE_QW 1ull 207 #define L4_TYPE_BIT_OFFSET 0ull 208 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off)) 209 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET) 210 #define L4_16B_TYPE_MASK 0xFFull 211 #define L4_16B_ETH_VALUE 0x78ull 212 213 /* 16B VESWID - for select */ 214 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull)) 215 /* 16B ENTROPY - for select */ 216 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull)) 217 218 /* defines to build power on SC2VL table */ 219 #define SC2VL_VAL( \ 220 num, \ 221 sc0, sc0val, \ 222 sc1, sc1val, \ 223 sc2, sc2val, \ 224 sc3, sc3val, \ 225 sc4, sc4val, \ 226 sc5, sc5val, \ 227 sc6, sc6val, \ 228 sc7, sc7val) \ 229 ( \ 230 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \ 231 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \ 232 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \ 233 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \ 234 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \ 235 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \ 236 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \ 237 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \ 238 ) 239 240 #define DC_SC_VL_VAL( \ 241 range, \ 242 e0, e0val, \ 243 e1, e1val, \ 244 e2, e2val, \ 245 e3, e3val, \ 246 e4, e4val, \ 247 e5, e5val, \ 248 e6, e6val, \ 249 e7, e7val, \ 250 e8, e8val, \ 251 e9, e9val, \ 252 e10, e10val, \ 253 e11, e11val, \ 254 e12, e12val, \ 255 e13, e13val, \ 256 e14, e14val, \ 257 e15, e15val) \ 258 ( \ 259 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \ 260 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \ 261 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \ 262 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \ 263 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \ 264 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \ 265 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \ 266 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \ 267 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \ 268 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \ 269 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \ 270 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \ 271 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \ 272 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \ 273 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \ 274 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \ 275 ) 276 277 /* all CceStatus sub-block freeze bits */ 278 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \ 279 | CCE_STATUS_RXE_FROZE_SMASK \ 280 | CCE_STATUS_TXE_FROZE_SMASK \ 281 | CCE_STATUS_TXE_PIO_FROZE_SMASK) 282 /* all CceStatus sub-block TXE pause bits */ 283 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \ 284 | CCE_STATUS_TXE_PAUSED_SMASK \ 285 | CCE_STATUS_SDMA_PAUSED_SMASK) 286 /* all CceStatus sub-block RXE pause bits */ 287 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK 288 289 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL 290 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF 291 292 /* 293 * CCE Error flags. 294 */ 295 static struct flag_table cce_err_status_flags[] = { 296 /* 0*/ FLAG_ENTRY0("CceCsrParityErr", 297 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK), 298 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr", 299 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK), 300 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr", 301 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK), 302 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr", 303 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK), 304 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr", 305 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK), 306 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr", 307 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK), 308 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr", 309 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK), 310 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr", 311 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK), 312 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr", 313 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK), 314 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 315 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK), 316 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 317 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK), 318 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError", 319 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK), 320 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError", 321 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK), 322 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr", 323 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK), 324 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr", 325 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK), 326 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr", 327 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK), 328 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr", 329 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK), 330 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr", 331 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK), 332 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr", 333 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK), 334 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr", 335 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK), 336 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr", 337 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK), 338 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr", 339 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK), 340 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr", 341 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK), 342 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr", 343 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK), 344 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr", 345 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK), 346 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr", 347 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK), 348 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr", 349 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK), 350 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr", 351 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK), 352 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr", 353 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK), 354 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr", 355 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK), 356 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr", 357 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK), 358 /*31*/ FLAG_ENTRY0("LATriggered", 359 CCE_ERR_STATUS_LA_TRIGGERED_SMASK), 360 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr", 361 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK), 362 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr", 363 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK), 364 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr", 365 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK), 366 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr", 367 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK), 368 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr", 369 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK), 370 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr", 371 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK), 372 /*38*/ FLAG_ENTRY0("CceIntMapCorErr", 373 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK), 374 /*39*/ FLAG_ENTRY0("CceIntMapUncErr", 375 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK), 376 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr", 377 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK), 378 /*41-63 reserved*/ 379 }; 380 381 /* 382 * Misc Error flags 383 */ 384 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK 385 static struct flag_table misc_err_status_flags[] = { 386 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)), 387 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)), 388 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)), 389 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)), 390 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)), 391 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)), 392 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)), 393 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)), 394 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)), 395 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)), 396 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)), 397 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)), 398 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL)) 399 }; 400 401 /* 402 * TXE PIO Error flags and consequences 403 */ 404 static struct flag_table pio_err_status_flags[] = { 405 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt", 406 SEC_WRITE_DROPPED, 407 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK), 408 /* 1*/ FLAG_ENTRY("PioWriteAddrParity", 409 SEC_SPC_FREEZE, 410 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK), 411 /* 2*/ FLAG_ENTRY("PioCsrParity", 412 SEC_SPC_FREEZE, 413 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK), 414 /* 3*/ FLAG_ENTRY("PioSbMemFifo0", 415 SEC_SPC_FREEZE, 416 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK), 417 /* 4*/ FLAG_ENTRY("PioSbMemFifo1", 418 SEC_SPC_FREEZE, 419 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK), 420 /* 5*/ FLAG_ENTRY("PioPccFifoParity", 421 SEC_SPC_FREEZE, 422 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK), 423 /* 6*/ FLAG_ENTRY("PioPecFifoParity", 424 SEC_SPC_FREEZE, 425 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK), 426 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity", 427 SEC_SPC_FREEZE, 428 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK), 429 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity", 430 SEC_SPC_FREEZE, 431 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK), 432 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr", 433 SEC_SPC_FREEZE, 434 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK), 435 /*10*/ FLAG_ENTRY("PioSmPktResetParity", 436 SEC_SPC_FREEZE, 437 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK), 438 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc", 439 SEC_SPC_FREEZE, 440 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK), 441 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc", 442 SEC_SPC_FREEZE, 443 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK), 444 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor", 445 0, 446 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK), 447 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor", 448 0, 449 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK), 450 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity", 451 SEC_SPC_FREEZE, 452 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK), 453 /*16*/ FLAG_ENTRY("PioPpmcPblFifo", 454 SEC_SPC_FREEZE, 455 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK), 456 /*17*/ FLAG_ENTRY("PioInitSmIn", 457 0, 458 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK), 459 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm", 460 SEC_SPC_FREEZE, 461 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK), 462 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc", 463 SEC_SPC_FREEZE, 464 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK), 465 /*20*/ FLAG_ENTRY("PioHostAddrMemCor", 466 0, 467 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK), 468 /*21*/ FLAG_ENTRY("PioWriteDataParity", 469 SEC_SPC_FREEZE, 470 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK), 471 /*22*/ FLAG_ENTRY("PioStateMachine", 472 SEC_SPC_FREEZE, 473 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK), 474 /*23*/ FLAG_ENTRY("PioWriteQwValidParity", 475 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 476 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK), 477 /*24*/ FLAG_ENTRY("PioBlockQwCountParity", 478 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 479 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK), 480 /*25*/ FLAG_ENTRY("PioVlfVlLenParity", 481 SEC_SPC_FREEZE, 482 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK), 483 /*26*/ FLAG_ENTRY("PioVlfSopParity", 484 SEC_SPC_FREEZE, 485 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK), 486 /*27*/ FLAG_ENTRY("PioVlFifoParity", 487 SEC_SPC_FREEZE, 488 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK), 489 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity", 490 SEC_SPC_FREEZE, 491 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK), 492 /*29*/ FLAG_ENTRY("PioPpmcSopLen", 493 SEC_SPC_FREEZE, 494 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK), 495 /*30-31 reserved*/ 496 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity", 497 SEC_SPC_FREEZE, 498 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK), 499 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity", 500 SEC_SPC_FREEZE, 501 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK), 502 /*34*/ FLAG_ENTRY("PioPccSopHeadParity", 503 SEC_SPC_FREEZE, 504 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK), 505 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr", 506 SEC_SPC_FREEZE, 507 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK), 508 /*36-63 reserved*/ 509 }; 510 511 /* TXE PIO errors that cause an SPC freeze */ 512 #define ALL_PIO_FREEZE_ERR \ 513 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \ 514 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \ 515 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \ 516 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \ 517 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \ 518 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \ 519 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \ 520 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 521 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \ 522 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \ 523 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \ 524 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \ 525 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \ 526 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \ 527 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \ 528 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \ 529 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \ 530 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \ 531 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \ 532 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 533 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \ 534 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \ 535 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \ 536 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \ 537 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \ 538 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 539 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 540 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 541 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK) 542 543 /* 544 * TXE SDMA Error flags 545 */ 546 static struct flag_table sdma_err_status_flags[] = { 547 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr", 548 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK), 549 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr", 550 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK), 551 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr", 552 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK), 553 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr", 554 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK), 555 /*04-63 reserved*/ 556 }; 557 558 /* TXE SDMA errors that cause an SPC freeze */ 559 #define ALL_SDMA_FREEZE_ERR \ 560 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \ 561 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \ 562 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK) 563 564 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */ 565 #define PORT_DISCARD_EGRESS_ERRS \ 566 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \ 567 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \ 568 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK) 569 570 /* 571 * TXE Egress Error flags 572 */ 573 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK 574 static struct flag_table egress_err_status_flags[] = { 575 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)), 576 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)), 577 /* 2 reserved */ 578 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr", 579 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)), 580 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)), 581 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)), 582 /* 6 reserved */ 583 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr", 584 SEES(TX_PIO_LAUNCH_INTF_PARITY)), 585 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr", 586 SEES(TX_SDMA_LAUNCH_INTF_PARITY)), 587 /* 9-10 reserved */ 588 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr", 589 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)), 590 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)), 591 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)), 592 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)), 593 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)), 594 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr", 595 SEES(TX_SDMA0_DISALLOWED_PACKET)), 596 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr", 597 SEES(TX_SDMA1_DISALLOWED_PACKET)), 598 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr", 599 SEES(TX_SDMA2_DISALLOWED_PACKET)), 600 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr", 601 SEES(TX_SDMA3_DISALLOWED_PACKET)), 602 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr", 603 SEES(TX_SDMA4_DISALLOWED_PACKET)), 604 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr", 605 SEES(TX_SDMA5_DISALLOWED_PACKET)), 606 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr", 607 SEES(TX_SDMA6_DISALLOWED_PACKET)), 608 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr", 609 SEES(TX_SDMA7_DISALLOWED_PACKET)), 610 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr", 611 SEES(TX_SDMA8_DISALLOWED_PACKET)), 612 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr", 613 SEES(TX_SDMA9_DISALLOWED_PACKET)), 614 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr", 615 SEES(TX_SDMA10_DISALLOWED_PACKET)), 616 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr", 617 SEES(TX_SDMA11_DISALLOWED_PACKET)), 618 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr", 619 SEES(TX_SDMA12_DISALLOWED_PACKET)), 620 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr", 621 SEES(TX_SDMA13_DISALLOWED_PACKET)), 622 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr", 623 SEES(TX_SDMA14_DISALLOWED_PACKET)), 624 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr", 625 SEES(TX_SDMA15_DISALLOWED_PACKET)), 626 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr", 627 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)), 628 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr", 629 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)), 630 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr", 631 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)), 632 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr", 633 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)), 634 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr", 635 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)), 636 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr", 637 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)), 638 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr", 639 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)), 640 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr", 641 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)), 642 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr", 643 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)), 644 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)), 645 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)), 646 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)), 647 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)), 648 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)), 649 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)), 650 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)), 651 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)), 652 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)), 653 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)), 654 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)), 655 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)), 656 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)), 657 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)), 658 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)), 659 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)), 660 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)), 661 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)), 662 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)), 663 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)), 664 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)), 665 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr", 666 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)), 667 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr", 668 SEES(TX_READ_PIO_MEMORY_CSR_UNC)), 669 }; 670 671 /* 672 * TXE Egress Error Info flags 673 */ 674 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK 675 static struct flag_table egress_err_info_flags[] = { 676 /* 0*/ FLAG_ENTRY0("Reserved", 0ull), 677 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)), 678 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 679 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 680 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)), 681 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)), 682 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)), 683 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)), 684 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)), 685 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)), 686 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)), 687 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)), 688 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)), 689 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)), 690 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)), 691 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)), 692 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)), 693 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)), 694 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)), 695 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)), 696 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)), 697 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)), 698 }; 699 700 /* TXE Egress errors that cause an SPC freeze */ 701 #define ALL_TXE_EGRESS_FREEZE_ERR \ 702 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \ 703 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \ 704 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \ 705 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \ 706 | SEES(TX_LAUNCH_CSR_PARITY) \ 707 | SEES(TX_SBRD_CTL_CSR_PARITY) \ 708 | SEES(TX_CONFIG_PARITY) \ 709 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \ 710 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \ 711 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \ 712 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \ 713 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \ 714 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \ 715 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \ 716 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \ 717 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \ 718 | SEES(TX_CREDIT_RETURN_PARITY)) 719 720 /* 721 * TXE Send error flags 722 */ 723 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK 724 static struct flag_table send_err_status_flags[] = { 725 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)), 726 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)), 727 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR)) 728 }; 729 730 /* 731 * TXE Send Context Error flags and consequences 732 */ 733 static struct flag_table sc_err_status_flags[] = { 734 /* 0*/ FLAG_ENTRY("InconsistentSop", 735 SEC_PACKET_DROPPED | SEC_SC_HALTED, 736 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK), 737 /* 1*/ FLAG_ENTRY("DisallowedPacket", 738 SEC_PACKET_DROPPED | SEC_SC_HALTED, 739 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK), 740 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary", 741 SEC_WRITE_DROPPED | SEC_SC_HALTED, 742 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK), 743 /* 3*/ FLAG_ENTRY("WriteOverflow", 744 SEC_WRITE_DROPPED | SEC_SC_HALTED, 745 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK), 746 /* 4*/ FLAG_ENTRY("WriteOutOfBounds", 747 SEC_WRITE_DROPPED | SEC_SC_HALTED, 748 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK), 749 /* 5-63 reserved*/ 750 }; 751 752 /* 753 * RXE Receive Error flags 754 */ 755 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK 756 static struct flag_table rxe_err_status_flags[] = { 757 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)), 758 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)), 759 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)), 760 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)), 761 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)), 762 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)), 763 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)), 764 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)), 765 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)), 766 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)), 767 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)), 768 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)), 769 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)), 770 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)), 771 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)), 772 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)), 773 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr", 774 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)), 775 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)), 776 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)), 777 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr", 778 RXES(RBUF_BLOCK_LIST_READ_UNC)), 779 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr", 780 RXES(RBUF_BLOCK_LIST_READ_COR)), 781 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr", 782 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)), 783 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr", 784 RXES(RBUF_CSR_QENT_CNT_PARITY)), 785 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr", 786 RXES(RBUF_CSR_QNEXT_BUF_PARITY)), 787 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr", 788 RXES(RBUF_CSR_QVLD_BIT_PARITY)), 789 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)), 790 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)), 791 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr", 792 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)), 793 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)), 794 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)), 795 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)), 796 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)), 797 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)), 798 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)), 799 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)), 800 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr", 801 RXES(RBUF_FL_INITDONE_PARITY)), 802 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr", 803 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)), 804 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)), 805 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)), 806 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)), 807 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr", 808 RXES(LOOKUP_DES_PART1_UNC_COR)), 809 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr", 810 RXES(LOOKUP_DES_PART2_PARITY)), 811 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)), 812 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)), 813 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)), 814 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)), 815 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)), 816 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)), 817 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)), 818 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)), 819 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)), 820 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)), 821 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)), 822 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)), 823 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)), 824 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)), 825 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)), 826 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)), 827 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)), 828 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)), 829 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)), 830 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)), 831 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)), 832 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY)) 833 }; 834 835 /* RXE errors that will trigger an SPC freeze */ 836 #define ALL_RXE_FREEZE_ERR \ 837 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \ 838 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \ 839 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \ 840 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \ 841 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \ 842 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \ 843 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \ 844 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \ 845 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \ 846 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 847 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \ 848 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \ 849 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \ 850 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \ 851 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \ 852 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 853 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \ 854 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \ 855 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \ 856 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \ 857 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \ 858 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \ 859 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \ 860 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \ 861 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 862 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \ 863 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \ 864 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 865 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 866 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \ 867 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \ 868 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \ 869 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \ 870 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \ 871 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \ 872 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \ 873 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \ 874 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 875 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \ 876 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \ 877 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 878 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 879 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \ 880 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK) 881 882 #define RXE_FREEZE_ABORT_MASK \ 883 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \ 884 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \ 885 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK) 886 887 /* 888 * DCC Error Flags 889 */ 890 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK 891 static struct flag_table dcc_err_flags[] = { 892 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)), 893 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)), 894 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)), 895 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)), 896 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)), 897 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)), 898 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)), 899 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)), 900 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)), 901 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)), 902 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)), 903 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)), 904 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)), 905 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)), 906 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)), 907 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)), 908 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)), 909 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)), 910 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)), 911 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)), 912 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)), 913 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)), 914 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)), 915 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)), 916 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)), 917 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)), 918 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)), 919 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)), 920 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)), 921 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)), 922 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)), 923 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)), 924 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)), 925 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)), 926 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)), 927 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)), 928 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)), 929 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)), 930 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)), 931 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)), 932 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)), 933 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)), 934 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)), 935 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)), 936 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)), 937 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)), 938 }; 939 940 /* 941 * LCB error flags 942 */ 943 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK 944 static struct flag_table lcb_err_flags[] = { 945 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)), 946 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)), 947 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)), 948 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST", 949 LCBE(ALL_LNS_FAILED_REINIT_TEST)), 950 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)), 951 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)), 952 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)), 953 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)), 954 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)), 955 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)), 956 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)), 957 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)), 958 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)), 959 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER", 960 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)), 961 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)), 962 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)), 963 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)), 964 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)), 965 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)), 966 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE", 967 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)), 968 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)), 969 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)), 970 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)), 971 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)), 972 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)), 973 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)), 974 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP", 975 LCBE(RST_FOR_INCOMPLT_RND_TRIP)), 976 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)), 977 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE", 978 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)), 979 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR", 980 LCBE(REDUNDANT_FLIT_PARITY_ERR)) 981 }; 982 983 /* 984 * DC8051 Error Flags 985 */ 986 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK 987 static struct flag_table dc8051_err_flags[] = { 988 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)), 989 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)), 990 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)), 991 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)), 992 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)), 993 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)), 994 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)), 995 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)), 996 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES", 997 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)), 998 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)), 999 }; 1000 1001 /* 1002 * DC8051 Information Error flags 1003 * 1004 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field. 1005 */ 1006 static struct flag_table dc8051_info_err_flags[] = { 1007 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED), 1008 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME), 1009 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET), 1010 FLAG_ENTRY0("Serdes internal loopback failure", 1011 FAILED_SERDES_INTERNAL_LOOPBACK), 1012 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT), 1013 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING), 1014 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE), 1015 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM), 1016 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ), 1017 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1), 1018 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2), 1019 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT), 1020 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT), 1021 FLAG_ENTRY0("External Device Request Timeout", 1022 EXTERNAL_DEVICE_REQ_TIMEOUT), 1023 }; 1024 1025 /* 1026 * DC8051 Information Host Information flags 1027 * 1028 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field. 1029 */ 1030 static struct flag_table dc8051_info_host_msg_flags[] = { 1031 FLAG_ENTRY0("Host request done", 0x0001), 1032 FLAG_ENTRY0("BC PWR_MGM message", 0x0002), 1033 FLAG_ENTRY0("BC SMA message", 0x0004), 1034 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008), 1035 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010), 1036 FLAG_ENTRY0("External device config request", 0x0020), 1037 FLAG_ENTRY0("VerifyCap all frames received", 0x0040), 1038 FLAG_ENTRY0("LinkUp achieved", 0x0080), 1039 FLAG_ENTRY0("Link going down", 0x0100), 1040 FLAG_ENTRY0("Link width downgraded", 0x0200), 1041 }; 1042 1043 static u32 encoded_size(u32 size); 1044 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate); 1045 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state); 1046 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 1047 u8 *continuous); 1048 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 1049 u8 *vcu, u16 *vl15buf, u8 *crc_sizes); 1050 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 1051 u8 *remote_tx_rate, u16 *link_widths); 1052 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 1053 u8 *flag_bits, u16 *link_widths); 1054 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 1055 u8 *device_rev); 1056 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx); 1057 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx, 1058 u8 *tx_polarity_inversion, 1059 u8 *rx_polarity_inversion, u8 *max_rate); 1060 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 1061 unsigned int context, u64 err_status); 1062 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg); 1063 static void handle_dcc_err(struct hfi1_devdata *dd, 1064 unsigned int context, u64 err_status); 1065 static void handle_lcb_err(struct hfi1_devdata *dd, 1066 unsigned int context, u64 err_status); 1067 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg); 1068 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1069 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1070 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1071 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1072 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1073 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1074 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1075 static void set_partition_keys(struct hfi1_pportdata *ppd); 1076 static const char *link_state_name(u32 state); 1077 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, 1078 u32 state); 1079 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 1080 u64 *out_data); 1081 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data); 1082 static int thermal_init(struct hfi1_devdata *dd); 1083 1084 static void update_statusp(struct hfi1_pportdata *ppd, u32 state); 1085 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 1086 int msecs); 1087 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1088 int msecs); 1089 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state); 1090 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state); 1091 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1092 int msecs); 1093 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd, 1094 int msecs); 1095 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc); 1096 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr); 1097 static void handle_temp_err(struct hfi1_devdata *dd); 1098 static void dc_shutdown(struct hfi1_devdata *dd); 1099 static void dc_start(struct hfi1_devdata *dd); 1100 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 1101 unsigned int *np); 1102 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd); 1103 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms); 1104 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index); 1105 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width); 1106 1107 /* 1108 * Error interrupt table entry. This is used as input to the interrupt 1109 * "clear down" routine used for all second tier error interrupt register. 1110 * Second tier interrupt registers have a single bit representing them 1111 * in the top-level CceIntStatus. 1112 */ 1113 struct err_reg_info { 1114 u32 status; /* status CSR offset */ 1115 u32 clear; /* clear CSR offset */ 1116 u32 mask; /* mask CSR offset */ 1117 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg); 1118 const char *desc; 1119 }; 1120 1121 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START) 1122 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START) 1123 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START) 1124 1125 /* 1126 * Helpers for building HFI and DC error interrupt table entries. Different 1127 * helpers are needed because of inconsistent register names. 1128 */ 1129 #define EE(reg, handler, desc) \ 1130 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ 1131 handler, desc } 1132 #define DC_EE1(reg, handler, desc) \ 1133 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc } 1134 #define DC_EE2(reg, handler, desc) \ 1135 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc } 1136 1137 /* 1138 * Table of the "misc" grouping of error interrupts. Each entry refers to 1139 * another register containing more information. 1140 */ 1141 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = { 1142 /* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"), 1143 /* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"), 1144 /* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"), 1145 /* 3*/ { 0, 0, 0, NULL }, /* reserved */ 1146 /* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"), 1147 /* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"), 1148 /* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"), 1149 /* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr") 1150 /* the rest are reserved */ 1151 }; 1152 1153 /* 1154 * Index into the Various section of the interrupt sources 1155 * corresponding to the Critical Temperature interrupt. 1156 */ 1157 #define TCRIT_INT_SOURCE 4 1158 1159 /* 1160 * SDMA error interrupt entry - refers to another register containing more 1161 * information. 1162 */ 1163 static const struct err_reg_info sdma_eng_err = 1164 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr"); 1165 1166 static const struct err_reg_info various_err[NUM_VARIOUS] = { 1167 /* 0*/ { 0, 0, 0, NULL }, /* PbcInt */ 1168 /* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */ 1169 /* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"), 1170 /* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"), 1171 /* 4*/ { 0, 0, 0, NULL }, /* TCritInt */ 1172 /* rest are reserved */ 1173 }; 1174 1175 /* 1176 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG 1177 * register can not be derived from the MTU value because 10K is not 1178 * a power of 2. Therefore, we need a constant. Everything else can 1179 * be calculated. 1180 */ 1181 #define DCC_CFG_PORT_MTU_CAP_10240 7 1182 1183 /* 1184 * Table of the DC grouping of error interrupts. Each entry refers to 1185 * another register containing more information. 1186 */ 1187 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = { 1188 /* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"), 1189 /* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"), 1190 /* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"), 1191 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */ 1192 /* the rest are reserved */ 1193 }; 1194 1195 struct cntr_entry { 1196 /* 1197 * counter name 1198 */ 1199 char *name; 1200 1201 /* 1202 * csr to read for name (if applicable) 1203 */ 1204 u64 csr; 1205 1206 /* 1207 * offset into dd or ppd to store the counter's value 1208 */ 1209 int offset; 1210 1211 /* 1212 * flags 1213 */ 1214 u8 flags; 1215 1216 /* 1217 * accessor for stat element, context either dd or ppd 1218 */ 1219 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl, 1220 int mode, u64 data); 1221 }; 1222 1223 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0 1224 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159 1225 1226 #define CNTR_ELEM(name, csr, offset, flags, accessor) \ 1227 { \ 1228 name, \ 1229 csr, \ 1230 offset, \ 1231 flags, \ 1232 accessor \ 1233 } 1234 1235 /* 32bit RXE */ 1236 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1237 CNTR_ELEM(#name, \ 1238 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1239 0, flags | CNTR_32BIT, \ 1240 port_access_u32_csr) 1241 1242 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \ 1243 CNTR_ELEM(#name, \ 1244 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1245 0, flags | CNTR_32BIT, \ 1246 dev_access_u32_csr) 1247 1248 /* 64bit RXE */ 1249 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1250 CNTR_ELEM(#name, \ 1251 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1252 0, flags, \ 1253 port_access_u64_csr) 1254 1255 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \ 1256 CNTR_ELEM(#name, \ 1257 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1258 0, flags, \ 1259 dev_access_u64_csr) 1260 1261 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx 1262 #define OVR_ELM(ctx) \ 1263 CNTR_ELEM("RcvHdrOvr" #ctx, \ 1264 (RCV_HDR_OVFL_CNT + ctx * 0x100), \ 1265 0, CNTR_NORMAL, port_access_u64_csr) 1266 1267 /* 32bit TXE */ 1268 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1269 CNTR_ELEM(#name, \ 1270 (counter * 8 + SEND_COUNTER_ARRAY32), \ 1271 0, flags | CNTR_32BIT, \ 1272 port_access_u32_csr) 1273 1274 /* 64bit TXE */ 1275 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1276 CNTR_ELEM(#name, \ 1277 (counter * 8 + SEND_COUNTER_ARRAY64), \ 1278 0, flags, \ 1279 port_access_u64_csr) 1280 1281 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \ 1282 CNTR_ELEM(#name,\ 1283 counter * 8 + SEND_COUNTER_ARRAY64, \ 1284 0, \ 1285 flags, \ 1286 dev_access_u64_csr) 1287 1288 /* CCE */ 1289 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \ 1290 CNTR_ELEM(#name, \ 1291 (counter * 8 + CCE_COUNTER_ARRAY32), \ 1292 0, flags | CNTR_32BIT, \ 1293 dev_access_u32_csr) 1294 1295 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \ 1296 CNTR_ELEM(#name, \ 1297 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \ 1298 0, flags | CNTR_32BIT, \ 1299 dev_access_u32_csr) 1300 1301 /* DC */ 1302 #define DC_PERF_CNTR(name, counter, flags) \ 1303 CNTR_ELEM(#name, \ 1304 counter, \ 1305 0, \ 1306 flags, \ 1307 dev_access_u64_csr) 1308 1309 #define DC_PERF_CNTR_LCB(name, counter, flags) \ 1310 CNTR_ELEM(#name, \ 1311 counter, \ 1312 0, \ 1313 flags, \ 1314 dc_access_lcb_cntr) 1315 1316 /* ibp counters */ 1317 #define SW_IBP_CNTR(name, cntr) \ 1318 CNTR_ELEM(#name, \ 1319 0, \ 1320 0, \ 1321 CNTR_SYNTH, \ 1322 access_ibp_##cntr) 1323 1324 /** 1325 * hfi_addr_from_offset - return addr for readq/writeq 1326 * @dd - the dd device 1327 * @offset - the offset of the CSR within bar0 1328 * 1329 * This routine selects the appropriate base address 1330 * based on the indicated offset. 1331 */ 1332 static inline void __iomem *hfi1_addr_from_offset( 1333 const struct hfi1_devdata *dd, 1334 u32 offset) 1335 { 1336 if (offset >= dd->base2_start) 1337 return dd->kregbase2 + (offset - dd->base2_start); 1338 return dd->kregbase1 + offset; 1339 } 1340 1341 /** 1342 * read_csr - read CSR at the indicated offset 1343 * @dd - the dd device 1344 * @offset - the offset of the CSR within bar0 1345 * 1346 * Return: the value read or all FF's if there 1347 * is no mapping 1348 */ 1349 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) 1350 { 1351 if (dd->flags & HFI1_PRESENT) 1352 return readq(hfi1_addr_from_offset(dd, offset)); 1353 return -1; 1354 } 1355 1356 /** 1357 * write_csr - write CSR at the indicated offset 1358 * @dd - the dd device 1359 * @offset - the offset of the CSR within bar0 1360 * @value - value to write 1361 */ 1362 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) 1363 { 1364 if (dd->flags & HFI1_PRESENT) { 1365 void __iomem *base = hfi1_addr_from_offset(dd, offset); 1366 1367 /* avoid write to RcvArray */ 1368 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start)) 1369 return; 1370 writeq(value, base); 1371 } 1372 } 1373 1374 /** 1375 * get_csr_addr - return te iomem address for offset 1376 * @dd - the dd device 1377 * @offset - the offset of the CSR within bar0 1378 * 1379 * Return: The iomem address to use in subsequent 1380 * writeq/readq operations. 1381 */ 1382 void __iomem *get_csr_addr( 1383 const struct hfi1_devdata *dd, 1384 u32 offset) 1385 { 1386 if (dd->flags & HFI1_PRESENT) 1387 return hfi1_addr_from_offset(dd, offset); 1388 return NULL; 1389 } 1390 1391 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr, 1392 int mode, u64 value) 1393 { 1394 u64 ret; 1395 1396 if (mode == CNTR_MODE_R) { 1397 ret = read_csr(dd, csr); 1398 } else if (mode == CNTR_MODE_W) { 1399 write_csr(dd, csr, value); 1400 ret = value; 1401 } else { 1402 dd_dev_err(dd, "Invalid cntr register access mode"); 1403 return 0; 1404 } 1405 1406 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode); 1407 return ret; 1408 } 1409 1410 /* Dev Access */ 1411 static u64 dev_access_u32_csr(const struct cntr_entry *entry, 1412 void *context, int vl, int mode, u64 data) 1413 { 1414 struct hfi1_devdata *dd = context; 1415 u64 csr = entry->csr; 1416 1417 if (entry->flags & CNTR_SDMA) { 1418 if (vl == CNTR_INVALID_VL) 1419 return 0; 1420 csr += 0x100 * vl; 1421 } else { 1422 if (vl != CNTR_INVALID_VL) 1423 return 0; 1424 } 1425 return read_write_csr(dd, csr, mode, data); 1426 } 1427 1428 static u64 access_sde_err_cnt(const struct cntr_entry *entry, 1429 void *context, int idx, int mode, u64 data) 1430 { 1431 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1432 1433 if (dd->per_sdma && idx < dd->num_sdma) 1434 return dd->per_sdma[idx].err_cnt; 1435 return 0; 1436 } 1437 1438 static u64 access_sde_int_cnt(const struct cntr_entry *entry, 1439 void *context, int idx, int mode, u64 data) 1440 { 1441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1442 1443 if (dd->per_sdma && idx < dd->num_sdma) 1444 return dd->per_sdma[idx].sdma_int_cnt; 1445 return 0; 1446 } 1447 1448 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry, 1449 void *context, int idx, int mode, u64 data) 1450 { 1451 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1452 1453 if (dd->per_sdma && idx < dd->num_sdma) 1454 return dd->per_sdma[idx].idle_int_cnt; 1455 return 0; 1456 } 1457 1458 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry, 1459 void *context, int idx, int mode, 1460 u64 data) 1461 { 1462 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1463 1464 if (dd->per_sdma && idx < dd->num_sdma) 1465 return dd->per_sdma[idx].progress_int_cnt; 1466 return 0; 1467 } 1468 1469 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context, 1470 int vl, int mode, u64 data) 1471 { 1472 struct hfi1_devdata *dd = context; 1473 1474 u64 val = 0; 1475 u64 csr = entry->csr; 1476 1477 if (entry->flags & CNTR_VL) { 1478 if (vl == CNTR_INVALID_VL) 1479 return 0; 1480 csr += 8 * vl; 1481 } else { 1482 if (vl != CNTR_INVALID_VL) 1483 return 0; 1484 } 1485 1486 val = read_write_csr(dd, csr, mode, data); 1487 return val; 1488 } 1489 1490 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context, 1491 int vl, int mode, u64 data) 1492 { 1493 struct hfi1_devdata *dd = context; 1494 u32 csr = entry->csr; 1495 int ret = 0; 1496 1497 if (vl != CNTR_INVALID_VL) 1498 return 0; 1499 if (mode == CNTR_MODE_R) 1500 ret = read_lcb_csr(dd, csr, &data); 1501 else if (mode == CNTR_MODE_W) 1502 ret = write_lcb_csr(dd, csr, data); 1503 1504 if (ret) { 1505 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr); 1506 return 0; 1507 } 1508 1509 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode); 1510 return data; 1511 } 1512 1513 /* Port Access */ 1514 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context, 1515 int vl, int mode, u64 data) 1516 { 1517 struct hfi1_pportdata *ppd = context; 1518 1519 if (vl != CNTR_INVALID_VL) 1520 return 0; 1521 return read_write_csr(ppd->dd, entry->csr, mode, data); 1522 } 1523 1524 static u64 port_access_u64_csr(const struct cntr_entry *entry, 1525 void *context, int vl, int mode, u64 data) 1526 { 1527 struct hfi1_pportdata *ppd = context; 1528 u64 val; 1529 u64 csr = entry->csr; 1530 1531 if (entry->flags & CNTR_VL) { 1532 if (vl == CNTR_INVALID_VL) 1533 return 0; 1534 csr += 8 * vl; 1535 } else { 1536 if (vl != CNTR_INVALID_VL) 1537 return 0; 1538 } 1539 val = read_write_csr(ppd->dd, csr, mode, data); 1540 return val; 1541 } 1542 1543 /* Software defined */ 1544 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode, 1545 u64 data) 1546 { 1547 u64 ret; 1548 1549 if (mode == CNTR_MODE_R) { 1550 ret = *cntr; 1551 } else if (mode == CNTR_MODE_W) { 1552 *cntr = data; 1553 ret = data; 1554 } else { 1555 dd_dev_err(dd, "Invalid cntr sw access mode"); 1556 return 0; 1557 } 1558 1559 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode); 1560 1561 return ret; 1562 } 1563 1564 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context, 1565 int vl, int mode, u64 data) 1566 { 1567 struct hfi1_pportdata *ppd = context; 1568 1569 if (vl != CNTR_INVALID_VL) 1570 return 0; 1571 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data); 1572 } 1573 1574 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context, 1575 int vl, int mode, u64 data) 1576 { 1577 struct hfi1_pportdata *ppd = context; 1578 1579 if (vl != CNTR_INVALID_VL) 1580 return 0; 1581 return read_write_sw(ppd->dd, &ppd->link_up, mode, data); 1582 } 1583 1584 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry, 1585 void *context, int vl, int mode, 1586 u64 data) 1587 { 1588 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1589 1590 if (vl != CNTR_INVALID_VL) 1591 return 0; 1592 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data); 1593 } 1594 1595 static u64 access_sw_xmit_discards(const struct cntr_entry *entry, 1596 void *context, int vl, int mode, u64 data) 1597 { 1598 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1599 u64 zero = 0; 1600 u64 *counter; 1601 1602 if (vl == CNTR_INVALID_VL) 1603 counter = &ppd->port_xmit_discards; 1604 else if (vl >= 0 && vl < C_VL_COUNT) 1605 counter = &ppd->port_xmit_discards_vl[vl]; 1606 else 1607 counter = &zero; 1608 1609 return read_write_sw(ppd->dd, counter, mode, data); 1610 } 1611 1612 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry, 1613 void *context, int vl, int mode, 1614 u64 data) 1615 { 1616 struct hfi1_pportdata *ppd = context; 1617 1618 if (vl != CNTR_INVALID_VL) 1619 return 0; 1620 1621 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors, 1622 mode, data); 1623 } 1624 1625 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry, 1626 void *context, int vl, int mode, u64 data) 1627 { 1628 struct hfi1_pportdata *ppd = context; 1629 1630 if (vl != CNTR_INVALID_VL) 1631 return 0; 1632 1633 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors, 1634 mode, data); 1635 } 1636 1637 u64 get_all_cpu_total(u64 __percpu *cntr) 1638 { 1639 int cpu; 1640 u64 counter = 0; 1641 1642 for_each_possible_cpu(cpu) 1643 counter += *per_cpu_ptr(cntr, cpu); 1644 return counter; 1645 } 1646 1647 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val, 1648 u64 __percpu *cntr, 1649 int vl, int mode, u64 data) 1650 { 1651 u64 ret = 0; 1652 1653 if (vl != CNTR_INVALID_VL) 1654 return 0; 1655 1656 if (mode == CNTR_MODE_R) { 1657 ret = get_all_cpu_total(cntr) - *z_val; 1658 } else if (mode == CNTR_MODE_W) { 1659 /* A write can only zero the counter */ 1660 if (data == 0) 1661 *z_val = get_all_cpu_total(cntr); 1662 else 1663 dd_dev_err(dd, "Per CPU cntrs can only be zeroed"); 1664 } else { 1665 dd_dev_err(dd, "Invalid cntr sw cpu access mode"); 1666 return 0; 1667 } 1668 1669 return ret; 1670 } 1671 1672 static u64 access_sw_cpu_intr(const struct cntr_entry *entry, 1673 void *context, int vl, int mode, u64 data) 1674 { 1675 struct hfi1_devdata *dd = context; 1676 1677 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl, 1678 mode, data); 1679 } 1680 1681 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry, 1682 void *context, int vl, int mode, u64 data) 1683 { 1684 struct hfi1_devdata *dd = context; 1685 1686 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl, 1687 mode, data); 1688 } 1689 1690 static u64 access_sw_pio_wait(const struct cntr_entry *entry, 1691 void *context, int vl, int mode, u64 data) 1692 { 1693 struct hfi1_devdata *dd = context; 1694 1695 return dd->verbs_dev.n_piowait; 1696 } 1697 1698 static u64 access_sw_pio_drain(const struct cntr_entry *entry, 1699 void *context, int vl, int mode, u64 data) 1700 { 1701 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1702 1703 return dd->verbs_dev.n_piodrain; 1704 } 1705 1706 static u64 access_sw_ctx0_seq_drop(const struct cntr_entry *entry, 1707 void *context, int vl, int mode, u64 data) 1708 { 1709 struct hfi1_devdata *dd = context; 1710 1711 return dd->ctx0_seq_drop; 1712 } 1713 1714 static u64 access_sw_vtx_wait(const struct cntr_entry *entry, 1715 void *context, int vl, int mode, u64 data) 1716 { 1717 struct hfi1_devdata *dd = context; 1718 1719 return dd->verbs_dev.n_txwait; 1720 } 1721 1722 static u64 access_sw_kmem_wait(const struct cntr_entry *entry, 1723 void *context, int vl, int mode, u64 data) 1724 { 1725 struct hfi1_devdata *dd = context; 1726 1727 return dd->verbs_dev.n_kmem_wait; 1728 } 1729 1730 static u64 access_sw_send_schedule(const struct cntr_entry *entry, 1731 void *context, int vl, int mode, u64 data) 1732 { 1733 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1734 1735 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl, 1736 mode, data); 1737 } 1738 1739 /* Software counters for the error status bits within MISC_ERR_STATUS */ 1740 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry, 1741 void *context, int vl, int mode, 1742 u64 data) 1743 { 1744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1745 1746 return dd->misc_err_status_cnt[12]; 1747 } 1748 1749 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry, 1750 void *context, int vl, int mode, 1751 u64 data) 1752 { 1753 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1754 1755 return dd->misc_err_status_cnt[11]; 1756 } 1757 1758 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry, 1759 void *context, int vl, int mode, 1760 u64 data) 1761 { 1762 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1763 1764 return dd->misc_err_status_cnt[10]; 1765 } 1766 1767 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry, 1768 void *context, int vl, 1769 int mode, u64 data) 1770 { 1771 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1772 1773 return dd->misc_err_status_cnt[9]; 1774 } 1775 1776 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry, 1777 void *context, int vl, int mode, 1778 u64 data) 1779 { 1780 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1781 1782 return dd->misc_err_status_cnt[8]; 1783 } 1784 1785 static u64 access_misc_efuse_read_bad_addr_err_cnt( 1786 const struct cntr_entry *entry, 1787 void *context, int vl, int mode, u64 data) 1788 { 1789 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1790 1791 return dd->misc_err_status_cnt[7]; 1792 } 1793 1794 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry, 1795 void *context, int vl, 1796 int mode, u64 data) 1797 { 1798 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1799 1800 return dd->misc_err_status_cnt[6]; 1801 } 1802 1803 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry, 1804 void *context, int vl, int mode, 1805 u64 data) 1806 { 1807 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1808 1809 return dd->misc_err_status_cnt[5]; 1810 } 1811 1812 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry, 1813 void *context, int vl, int mode, 1814 u64 data) 1815 { 1816 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1817 1818 return dd->misc_err_status_cnt[4]; 1819 } 1820 1821 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry, 1822 void *context, int vl, 1823 int mode, u64 data) 1824 { 1825 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1826 1827 return dd->misc_err_status_cnt[3]; 1828 } 1829 1830 static u64 access_misc_csr_write_bad_addr_err_cnt( 1831 const struct cntr_entry *entry, 1832 void *context, int vl, int mode, u64 data) 1833 { 1834 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1835 1836 return dd->misc_err_status_cnt[2]; 1837 } 1838 1839 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1840 void *context, int vl, 1841 int mode, u64 data) 1842 { 1843 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1844 1845 return dd->misc_err_status_cnt[1]; 1846 } 1847 1848 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry, 1849 void *context, int vl, int mode, 1850 u64 data) 1851 { 1852 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1853 1854 return dd->misc_err_status_cnt[0]; 1855 } 1856 1857 /* 1858 * Software counter for the aggregate of 1859 * individual CceErrStatus counters 1860 */ 1861 static u64 access_sw_cce_err_status_aggregated_cnt( 1862 const struct cntr_entry *entry, 1863 void *context, int vl, int mode, u64 data) 1864 { 1865 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1866 1867 return dd->sw_cce_err_status_aggregate; 1868 } 1869 1870 /* 1871 * Software counters corresponding to each of the 1872 * error status bits within CceErrStatus 1873 */ 1874 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry, 1875 void *context, int vl, int mode, 1876 u64 data) 1877 { 1878 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1879 1880 return dd->cce_err_status_cnt[40]; 1881 } 1882 1883 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry, 1884 void *context, int vl, int mode, 1885 u64 data) 1886 { 1887 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1888 1889 return dd->cce_err_status_cnt[39]; 1890 } 1891 1892 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry, 1893 void *context, int vl, int mode, 1894 u64 data) 1895 { 1896 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1897 1898 return dd->cce_err_status_cnt[38]; 1899 } 1900 1901 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry, 1902 void *context, int vl, int mode, 1903 u64 data) 1904 { 1905 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1906 1907 return dd->cce_err_status_cnt[37]; 1908 } 1909 1910 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry, 1911 void *context, int vl, int mode, 1912 u64 data) 1913 { 1914 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1915 1916 return dd->cce_err_status_cnt[36]; 1917 } 1918 1919 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt( 1920 const struct cntr_entry *entry, 1921 void *context, int vl, int mode, u64 data) 1922 { 1923 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1924 1925 return dd->cce_err_status_cnt[35]; 1926 } 1927 1928 static u64 access_cce_rcpl_async_fifo_parity_err_cnt( 1929 const struct cntr_entry *entry, 1930 void *context, int vl, int mode, u64 data) 1931 { 1932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1933 1934 return dd->cce_err_status_cnt[34]; 1935 } 1936 1937 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry, 1938 void *context, int vl, 1939 int mode, u64 data) 1940 { 1941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1942 1943 return dd->cce_err_status_cnt[33]; 1944 } 1945 1946 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1947 void *context, int vl, int mode, 1948 u64 data) 1949 { 1950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1951 1952 return dd->cce_err_status_cnt[32]; 1953 } 1954 1955 static u64 access_la_triggered_cnt(const struct cntr_entry *entry, 1956 void *context, int vl, int mode, u64 data) 1957 { 1958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1959 1960 return dd->cce_err_status_cnt[31]; 1961 } 1962 1963 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry, 1964 void *context, int vl, int mode, 1965 u64 data) 1966 { 1967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1968 1969 return dd->cce_err_status_cnt[30]; 1970 } 1971 1972 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry, 1973 void *context, int vl, int mode, 1974 u64 data) 1975 { 1976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1977 1978 return dd->cce_err_status_cnt[29]; 1979 } 1980 1981 static u64 access_pcic_transmit_back_parity_err_cnt( 1982 const struct cntr_entry *entry, 1983 void *context, int vl, int mode, u64 data) 1984 { 1985 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1986 1987 return dd->cce_err_status_cnt[28]; 1988 } 1989 1990 static u64 access_pcic_transmit_front_parity_err_cnt( 1991 const struct cntr_entry *entry, 1992 void *context, int vl, int mode, u64 data) 1993 { 1994 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1995 1996 return dd->cce_err_status_cnt[27]; 1997 } 1998 1999 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry, 2000 void *context, int vl, int mode, 2001 u64 data) 2002 { 2003 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2004 2005 return dd->cce_err_status_cnt[26]; 2006 } 2007 2008 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2009 void *context, int vl, int mode, 2010 u64 data) 2011 { 2012 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2013 2014 return dd->cce_err_status_cnt[25]; 2015 } 2016 2017 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry, 2018 void *context, int vl, int mode, 2019 u64 data) 2020 { 2021 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2022 2023 return dd->cce_err_status_cnt[24]; 2024 } 2025 2026 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2027 void *context, int vl, int mode, 2028 u64 data) 2029 { 2030 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2031 2032 return dd->cce_err_status_cnt[23]; 2033 } 2034 2035 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry, 2036 void *context, int vl, 2037 int mode, u64 data) 2038 { 2039 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2040 2041 return dd->cce_err_status_cnt[22]; 2042 } 2043 2044 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry, 2045 void *context, int vl, int mode, 2046 u64 data) 2047 { 2048 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2049 2050 return dd->cce_err_status_cnt[21]; 2051 } 2052 2053 static u64 access_pcic_n_post_dat_q_parity_err_cnt( 2054 const struct cntr_entry *entry, 2055 void *context, int vl, int mode, u64 data) 2056 { 2057 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2058 2059 return dd->cce_err_status_cnt[20]; 2060 } 2061 2062 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry, 2063 void *context, int vl, 2064 int mode, u64 data) 2065 { 2066 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2067 2068 return dd->cce_err_status_cnt[19]; 2069 } 2070 2071 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2072 void *context, int vl, int mode, 2073 u64 data) 2074 { 2075 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2076 2077 return dd->cce_err_status_cnt[18]; 2078 } 2079 2080 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2081 void *context, int vl, int mode, 2082 u64 data) 2083 { 2084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2085 2086 return dd->cce_err_status_cnt[17]; 2087 } 2088 2089 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2090 void *context, int vl, int mode, 2091 u64 data) 2092 { 2093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2094 2095 return dd->cce_err_status_cnt[16]; 2096 } 2097 2098 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2099 void *context, int vl, int mode, 2100 u64 data) 2101 { 2102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2103 2104 return dd->cce_err_status_cnt[15]; 2105 } 2106 2107 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry, 2108 void *context, int vl, 2109 int mode, u64 data) 2110 { 2111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2112 2113 return dd->cce_err_status_cnt[14]; 2114 } 2115 2116 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry, 2117 void *context, int vl, int mode, 2118 u64 data) 2119 { 2120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2121 2122 return dd->cce_err_status_cnt[13]; 2123 } 2124 2125 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt( 2126 const struct cntr_entry *entry, 2127 void *context, int vl, int mode, u64 data) 2128 { 2129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2130 2131 return dd->cce_err_status_cnt[12]; 2132 } 2133 2134 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt( 2135 const struct cntr_entry *entry, 2136 void *context, int vl, int mode, u64 data) 2137 { 2138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2139 2140 return dd->cce_err_status_cnt[11]; 2141 } 2142 2143 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt( 2144 const struct cntr_entry *entry, 2145 void *context, int vl, int mode, u64 data) 2146 { 2147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2148 2149 return dd->cce_err_status_cnt[10]; 2150 } 2151 2152 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt( 2153 const struct cntr_entry *entry, 2154 void *context, int vl, int mode, u64 data) 2155 { 2156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2157 2158 return dd->cce_err_status_cnt[9]; 2159 } 2160 2161 static u64 access_cce_cli2_async_fifo_parity_err_cnt( 2162 const struct cntr_entry *entry, 2163 void *context, int vl, int mode, u64 data) 2164 { 2165 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2166 2167 return dd->cce_err_status_cnt[8]; 2168 } 2169 2170 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry, 2171 void *context, int vl, 2172 int mode, u64 data) 2173 { 2174 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2175 2176 return dd->cce_err_status_cnt[7]; 2177 } 2178 2179 static u64 access_cce_cli0_async_fifo_parity_err_cnt( 2180 const struct cntr_entry *entry, 2181 void *context, int vl, int mode, u64 data) 2182 { 2183 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2184 2185 return dd->cce_err_status_cnt[6]; 2186 } 2187 2188 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry, 2189 void *context, int vl, int mode, 2190 u64 data) 2191 { 2192 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2193 2194 return dd->cce_err_status_cnt[5]; 2195 } 2196 2197 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry, 2198 void *context, int vl, int mode, 2199 u64 data) 2200 { 2201 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2202 2203 return dd->cce_err_status_cnt[4]; 2204 } 2205 2206 static u64 access_cce_trgt_async_fifo_parity_err_cnt( 2207 const struct cntr_entry *entry, 2208 void *context, int vl, int mode, u64 data) 2209 { 2210 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2211 2212 return dd->cce_err_status_cnt[3]; 2213 } 2214 2215 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2216 void *context, int vl, 2217 int mode, u64 data) 2218 { 2219 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2220 2221 return dd->cce_err_status_cnt[2]; 2222 } 2223 2224 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2225 void *context, int vl, 2226 int mode, u64 data) 2227 { 2228 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2229 2230 return dd->cce_err_status_cnt[1]; 2231 } 2232 2233 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry, 2234 void *context, int vl, int mode, 2235 u64 data) 2236 { 2237 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2238 2239 return dd->cce_err_status_cnt[0]; 2240 } 2241 2242 /* 2243 * Software counters corresponding to each of the 2244 * error status bits within RcvErrStatus 2245 */ 2246 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry, 2247 void *context, int vl, int mode, 2248 u64 data) 2249 { 2250 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2251 2252 return dd->rcv_err_status_cnt[63]; 2253 } 2254 2255 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2256 void *context, int vl, 2257 int mode, u64 data) 2258 { 2259 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2260 2261 return dd->rcv_err_status_cnt[62]; 2262 } 2263 2264 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2265 void *context, int vl, int mode, 2266 u64 data) 2267 { 2268 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2269 2270 return dd->rcv_err_status_cnt[61]; 2271 } 2272 2273 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry, 2274 void *context, int vl, int mode, 2275 u64 data) 2276 { 2277 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2278 2279 return dd->rcv_err_status_cnt[60]; 2280 } 2281 2282 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2283 void *context, int vl, 2284 int mode, u64 data) 2285 { 2286 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2287 2288 return dd->rcv_err_status_cnt[59]; 2289 } 2290 2291 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2292 void *context, int vl, 2293 int mode, u64 data) 2294 { 2295 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2296 2297 return dd->rcv_err_status_cnt[58]; 2298 } 2299 2300 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry, 2301 void *context, int vl, int mode, 2302 u64 data) 2303 { 2304 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2305 2306 return dd->rcv_err_status_cnt[57]; 2307 } 2308 2309 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry, 2310 void *context, int vl, int mode, 2311 u64 data) 2312 { 2313 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2314 2315 return dd->rcv_err_status_cnt[56]; 2316 } 2317 2318 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry, 2319 void *context, int vl, int mode, 2320 u64 data) 2321 { 2322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2323 2324 return dd->rcv_err_status_cnt[55]; 2325 } 2326 2327 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt( 2328 const struct cntr_entry *entry, 2329 void *context, int vl, int mode, u64 data) 2330 { 2331 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2332 2333 return dd->rcv_err_status_cnt[54]; 2334 } 2335 2336 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt( 2337 const struct cntr_entry *entry, 2338 void *context, int vl, int mode, u64 data) 2339 { 2340 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2341 2342 return dd->rcv_err_status_cnt[53]; 2343 } 2344 2345 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry, 2346 void *context, int vl, 2347 int mode, u64 data) 2348 { 2349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2350 2351 return dd->rcv_err_status_cnt[52]; 2352 } 2353 2354 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry, 2355 void *context, int vl, 2356 int mode, u64 data) 2357 { 2358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2359 2360 return dd->rcv_err_status_cnt[51]; 2361 } 2362 2363 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry, 2364 void *context, int vl, 2365 int mode, u64 data) 2366 { 2367 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2368 2369 return dd->rcv_err_status_cnt[50]; 2370 } 2371 2372 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry, 2373 void *context, int vl, 2374 int mode, u64 data) 2375 { 2376 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2377 2378 return dd->rcv_err_status_cnt[49]; 2379 } 2380 2381 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry, 2382 void *context, int vl, 2383 int mode, u64 data) 2384 { 2385 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2386 2387 return dd->rcv_err_status_cnt[48]; 2388 } 2389 2390 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry, 2391 void *context, int vl, 2392 int mode, u64 data) 2393 { 2394 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2395 2396 return dd->rcv_err_status_cnt[47]; 2397 } 2398 2399 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry, 2400 void *context, int vl, int mode, 2401 u64 data) 2402 { 2403 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2404 2405 return dd->rcv_err_status_cnt[46]; 2406 } 2407 2408 static u64 access_rx_hq_intr_csr_parity_err_cnt( 2409 const struct cntr_entry *entry, 2410 void *context, int vl, int mode, u64 data) 2411 { 2412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2413 2414 return dd->rcv_err_status_cnt[45]; 2415 } 2416 2417 static u64 access_rx_lookup_csr_parity_err_cnt( 2418 const struct cntr_entry *entry, 2419 void *context, int vl, int mode, u64 data) 2420 { 2421 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2422 2423 return dd->rcv_err_status_cnt[44]; 2424 } 2425 2426 static u64 access_rx_lookup_rcv_array_cor_err_cnt( 2427 const struct cntr_entry *entry, 2428 void *context, int vl, int mode, u64 data) 2429 { 2430 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2431 2432 return dd->rcv_err_status_cnt[43]; 2433 } 2434 2435 static u64 access_rx_lookup_rcv_array_unc_err_cnt( 2436 const struct cntr_entry *entry, 2437 void *context, int vl, int mode, u64 data) 2438 { 2439 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2440 2441 return dd->rcv_err_status_cnt[42]; 2442 } 2443 2444 static u64 access_rx_lookup_des_part2_parity_err_cnt( 2445 const struct cntr_entry *entry, 2446 void *context, int vl, int mode, u64 data) 2447 { 2448 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2449 2450 return dd->rcv_err_status_cnt[41]; 2451 } 2452 2453 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt( 2454 const struct cntr_entry *entry, 2455 void *context, int vl, int mode, u64 data) 2456 { 2457 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2458 2459 return dd->rcv_err_status_cnt[40]; 2460 } 2461 2462 static u64 access_rx_lookup_des_part1_unc_err_cnt( 2463 const struct cntr_entry *entry, 2464 void *context, int vl, int mode, u64 data) 2465 { 2466 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2467 2468 return dd->rcv_err_status_cnt[39]; 2469 } 2470 2471 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt( 2472 const struct cntr_entry *entry, 2473 void *context, int vl, int mode, u64 data) 2474 { 2475 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2476 2477 return dd->rcv_err_status_cnt[38]; 2478 } 2479 2480 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt( 2481 const struct cntr_entry *entry, 2482 void *context, int vl, int mode, u64 data) 2483 { 2484 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2485 2486 return dd->rcv_err_status_cnt[37]; 2487 } 2488 2489 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt( 2490 const struct cntr_entry *entry, 2491 void *context, int vl, int mode, u64 data) 2492 { 2493 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2494 2495 return dd->rcv_err_status_cnt[36]; 2496 } 2497 2498 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt( 2499 const struct cntr_entry *entry, 2500 void *context, int vl, int mode, u64 data) 2501 { 2502 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2503 2504 return dd->rcv_err_status_cnt[35]; 2505 } 2506 2507 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt( 2508 const struct cntr_entry *entry, 2509 void *context, int vl, int mode, u64 data) 2510 { 2511 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2512 2513 return dd->rcv_err_status_cnt[34]; 2514 } 2515 2516 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt( 2517 const struct cntr_entry *entry, 2518 void *context, int vl, int mode, u64 data) 2519 { 2520 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2521 2522 return dd->rcv_err_status_cnt[33]; 2523 } 2524 2525 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry, 2526 void *context, int vl, int mode, 2527 u64 data) 2528 { 2529 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2530 2531 return dd->rcv_err_status_cnt[32]; 2532 } 2533 2534 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry, 2535 void *context, int vl, int mode, 2536 u64 data) 2537 { 2538 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2539 2540 return dd->rcv_err_status_cnt[31]; 2541 } 2542 2543 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry, 2544 void *context, int vl, int mode, 2545 u64 data) 2546 { 2547 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2548 2549 return dd->rcv_err_status_cnt[30]; 2550 } 2551 2552 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry, 2553 void *context, int vl, int mode, 2554 u64 data) 2555 { 2556 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2557 2558 return dd->rcv_err_status_cnt[29]; 2559 } 2560 2561 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry, 2562 void *context, int vl, 2563 int mode, u64 data) 2564 { 2565 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2566 2567 return dd->rcv_err_status_cnt[28]; 2568 } 2569 2570 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt( 2571 const struct cntr_entry *entry, 2572 void *context, int vl, int mode, u64 data) 2573 { 2574 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2575 2576 return dd->rcv_err_status_cnt[27]; 2577 } 2578 2579 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt( 2580 const struct cntr_entry *entry, 2581 void *context, int vl, int mode, u64 data) 2582 { 2583 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2584 2585 return dd->rcv_err_status_cnt[26]; 2586 } 2587 2588 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt( 2589 const struct cntr_entry *entry, 2590 void *context, int vl, int mode, u64 data) 2591 { 2592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2593 2594 return dd->rcv_err_status_cnt[25]; 2595 } 2596 2597 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt( 2598 const struct cntr_entry *entry, 2599 void *context, int vl, int mode, u64 data) 2600 { 2601 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2602 2603 return dd->rcv_err_status_cnt[24]; 2604 } 2605 2606 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt( 2607 const struct cntr_entry *entry, 2608 void *context, int vl, int mode, u64 data) 2609 { 2610 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2611 2612 return dd->rcv_err_status_cnt[23]; 2613 } 2614 2615 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt( 2616 const struct cntr_entry *entry, 2617 void *context, int vl, int mode, u64 data) 2618 { 2619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2620 2621 return dd->rcv_err_status_cnt[22]; 2622 } 2623 2624 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt( 2625 const struct cntr_entry *entry, 2626 void *context, int vl, int mode, u64 data) 2627 { 2628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2629 2630 return dd->rcv_err_status_cnt[21]; 2631 } 2632 2633 static u64 access_rx_rbuf_block_list_read_cor_err_cnt( 2634 const struct cntr_entry *entry, 2635 void *context, int vl, int mode, u64 data) 2636 { 2637 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2638 2639 return dd->rcv_err_status_cnt[20]; 2640 } 2641 2642 static u64 access_rx_rbuf_block_list_read_unc_err_cnt( 2643 const struct cntr_entry *entry, 2644 void *context, int vl, int mode, u64 data) 2645 { 2646 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2647 2648 return dd->rcv_err_status_cnt[19]; 2649 } 2650 2651 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry, 2652 void *context, int vl, 2653 int mode, u64 data) 2654 { 2655 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2656 2657 return dd->rcv_err_status_cnt[18]; 2658 } 2659 2660 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry, 2661 void *context, int vl, 2662 int mode, u64 data) 2663 { 2664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2665 2666 return dd->rcv_err_status_cnt[17]; 2667 } 2668 2669 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt( 2670 const struct cntr_entry *entry, 2671 void *context, int vl, int mode, u64 data) 2672 { 2673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2674 2675 return dd->rcv_err_status_cnt[16]; 2676 } 2677 2678 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt( 2679 const struct cntr_entry *entry, 2680 void *context, int vl, int mode, u64 data) 2681 { 2682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2683 2684 return dd->rcv_err_status_cnt[15]; 2685 } 2686 2687 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry, 2688 void *context, int vl, 2689 int mode, u64 data) 2690 { 2691 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2692 2693 return dd->rcv_err_status_cnt[14]; 2694 } 2695 2696 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry, 2697 void *context, int vl, 2698 int mode, u64 data) 2699 { 2700 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2701 2702 return dd->rcv_err_status_cnt[13]; 2703 } 2704 2705 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2706 void *context, int vl, int mode, 2707 u64 data) 2708 { 2709 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2710 2711 return dd->rcv_err_status_cnt[12]; 2712 } 2713 2714 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry, 2715 void *context, int vl, int mode, 2716 u64 data) 2717 { 2718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2719 2720 return dd->rcv_err_status_cnt[11]; 2721 } 2722 2723 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry, 2724 void *context, int vl, int mode, 2725 u64 data) 2726 { 2727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2728 2729 return dd->rcv_err_status_cnt[10]; 2730 } 2731 2732 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry, 2733 void *context, int vl, int mode, 2734 u64 data) 2735 { 2736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2737 2738 return dd->rcv_err_status_cnt[9]; 2739 } 2740 2741 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry, 2742 void *context, int vl, int mode, 2743 u64 data) 2744 { 2745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2746 2747 return dd->rcv_err_status_cnt[8]; 2748 } 2749 2750 static u64 access_rx_rcv_qp_map_table_cor_err_cnt( 2751 const struct cntr_entry *entry, 2752 void *context, int vl, int mode, u64 data) 2753 { 2754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2755 2756 return dd->rcv_err_status_cnt[7]; 2757 } 2758 2759 static u64 access_rx_rcv_qp_map_table_unc_err_cnt( 2760 const struct cntr_entry *entry, 2761 void *context, int vl, int mode, u64 data) 2762 { 2763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2764 2765 return dd->rcv_err_status_cnt[6]; 2766 } 2767 2768 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry, 2769 void *context, int vl, int mode, 2770 u64 data) 2771 { 2772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2773 2774 return dd->rcv_err_status_cnt[5]; 2775 } 2776 2777 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry, 2778 void *context, int vl, int mode, 2779 u64 data) 2780 { 2781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2782 2783 return dd->rcv_err_status_cnt[4]; 2784 } 2785 2786 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry, 2787 void *context, int vl, int mode, 2788 u64 data) 2789 { 2790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2791 2792 return dd->rcv_err_status_cnt[3]; 2793 } 2794 2795 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry, 2796 void *context, int vl, int mode, 2797 u64 data) 2798 { 2799 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2800 2801 return dd->rcv_err_status_cnt[2]; 2802 } 2803 2804 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry, 2805 void *context, int vl, int mode, 2806 u64 data) 2807 { 2808 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2809 2810 return dd->rcv_err_status_cnt[1]; 2811 } 2812 2813 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry, 2814 void *context, int vl, int mode, 2815 u64 data) 2816 { 2817 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2818 2819 return dd->rcv_err_status_cnt[0]; 2820 } 2821 2822 /* 2823 * Software counters corresponding to each of the 2824 * error status bits within SendPioErrStatus 2825 */ 2826 static u64 access_pio_pec_sop_head_parity_err_cnt( 2827 const struct cntr_entry *entry, 2828 void *context, int vl, int mode, u64 data) 2829 { 2830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2831 2832 return dd->send_pio_err_status_cnt[35]; 2833 } 2834 2835 static u64 access_pio_pcc_sop_head_parity_err_cnt( 2836 const struct cntr_entry *entry, 2837 void *context, int vl, int mode, u64 data) 2838 { 2839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2840 2841 return dd->send_pio_err_status_cnt[34]; 2842 } 2843 2844 static u64 access_pio_last_returned_cnt_parity_err_cnt( 2845 const struct cntr_entry *entry, 2846 void *context, int vl, int mode, u64 data) 2847 { 2848 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2849 2850 return dd->send_pio_err_status_cnt[33]; 2851 } 2852 2853 static u64 access_pio_current_free_cnt_parity_err_cnt( 2854 const struct cntr_entry *entry, 2855 void *context, int vl, int mode, u64 data) 2856 { 2857 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2858 2859 return dd->send_pio_err_status_cnt[32]; 2860 } 2861 2862 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry, 2863 void *context, int vl, int mode, 2864 u64 data) 2865 { 2866 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2867 2868 return dd->send_pio_err_status_cnt[31]; 2869 } 2870 2871 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry, 2872 void *context, int vl, int mode, 2873 u64 data) 2874 { 2875 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2876 2877 return dd->send_pio_err_status_cnt[30]; 2878 } 2879 2880 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry, 2881 void *context, int vl, int mode, 2882 u64 data) 2883 { 2884 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2885 2886 return dd->send_pio_err_status_cnt[29]; 2887 } 2888 2889 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt( 2890 const struct cntr_entry *entry, 2891 void *context, int vl, int mode, u64 data) 2892 { 2893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2894 2895 return dd->send_pio_err_status_cnt[28]; 2896 } 2897 2898 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry, 2899 void *context, int vl, int mode, 2900 u64 data) 2901 { 2902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2903 2904 return dd->send_pio_err_status_cnt[27]; 2905 } 2906 2907 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry, 2908 void *context, int vl, int mode, 2909 u64 data) 2910 { 2911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2912 2913 return dd->send_pio_err_status_cnt[26]; 2914 } 2915 2916 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry, 2917 void *context, int vl, 2918 int mode, u64 data) 2919 { 2920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2921 2922 return dd->send_pio_err_status_cnt[25]; 2923 } 2924 2925 static u64 access_pio_block_qw_count_parity_err_cnt( 2926 const struct cntr_entry *entry, 2927 void *context, int vl, int mode, u64 data) 2928 { 2929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2930 2931 return dd->send_pio_err_status_cnt[24]; 2932 } 2933 2934 static u64 access_pio_write_qw_valid_parity_err_cnt( 2935 const struct cntr_entry *entry, 2936 void *context, int vl, int mode, u64 data) 2937 { 2938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2939 2940 return dd->send_pio_err_status_cnt[23]; 2941 } 2942 2943 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry, 2944 void *context, int vl, int mode, 2945 u64 data) 2946 { 2947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2948 2949 return dd->send_pio_err_status_cnt[22]; 2950 } 2951 2952 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry, 2953 void *context, int vl, 2954 int mode, u64 data) 2955 { 2956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2957 2958 return dd->send_pio_err_status_cnt[21]; 2959 } 2960 2961 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry, 2962 void *context, int vl, 2963 int mode, u64 data) 2964 { 2965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2966 2967 return dd->send_pio_err_status_cnt[20]; 2968 } 2969 2970 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry, 2971 void *context, int vl, 2972 int mode, u64 data) 2973 { 2974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2975 2976 return dd->send_pio_err_status_cnt[19]; 2977 } 2978 2979 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt( 2980 const struct cntr_entry *entry, 2981 void *context, int vl, int mode, u64 data) 2982 { 2983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2984 2985 return dd->send_pio_err_status_cnt[18]; 2986 } 2987 2988 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry, 2989 void *context, int vl, int mode, 2990 u64 data) 2991 { 2992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2993 2994 return dd->send_pio_err_status_cnt[17]; 2995 } 2996 2997 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry, 2998 void *context, int vl, int mode, 2999 u64 data) 3000 { 3001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3002 3003 return dd->send_pio_err_status_cnt[16]; 3004 } 3005 3006 static u64 access_pio_credit_ret_fifo_parity_err_cnt( 3007 const struct cntr_entry *entry, 3008 void *context, int vl, int mode, u64 data) 3009 { 3010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3011 3012 return dd->send_pio_err_status_cnt[15]; 3013 } 3014 3015 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt( 3016 const struct cntr_entry *entry, 3017 void *context, int vl, int mode, u64 data) 3018 { 3019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3020 3021 return dd->send_pio_err_status_cnt[14]; 3022 } 3023 3024 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt( 3025 const struct cntr_entry *entry, 3026 void *context, int vl, int mode, u64 data) 3027 { 3028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3029 3030 return dd->send_pio_err_status_cnt[13]; 3031 } 3032 3033 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt( 3034 const struct cntr_entry *entry, 3035 void *context, int vl, int mode, u64 data) 3036 { 3037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3038 3039 return dd->send_pio_err_status_cnt[12]; 3040 } 3041 3042 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt( 3043 const struct cntr_entry *entry, 3044 void *context, int vl, int mode, u64 data) 3045 { 3046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3047 3048 return dd->send_pio_err_status_cnt[11]; 3049 } 3050 3051 static u64 access_pio_sm_pkt_reset_parity_err_cnt( 3052 const struct cntr_entry *entry, 3053 void *context, int vl, int mode, u64 data) 3054 { 3055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3056 3057 return dd->send_pio_err_status_cnt[10]; 3058 } 3059 3060 static u64 access_pio_pkt_evict_fifo_parity_err_cnt( 3061 const struct cntr_entry *entry, 3062 void *context, int vl, int mode, u64 data) 3063 { 3064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3065 3066 return dd->send_pio_err_status_cnt[9]; 3067 } 3068 3069 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt( 3070 const struct cntr_entry *entry, 3071 void *context, int vl, int mode, u64 data) 3072 { 3073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3074 3075 return dd->send_pio_err_status_cnt[8]; 3076 } 3077 3078 static u64 access_pio_sbrdctl_crrel_parity_err_cnt( 3079 const struct cntr_entry *entry, 3080 void *context, int vl, int mode, u64 data) 3081 { 3082 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3083 3084 return dd->send_pio_err_status_cnt[7]; 3085 } 3086 3087 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry, 3088 void *context, int vl, int mode, 3089 u64 data) 3090 { 3091 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3092 3093 return dd->send_pio_err_status_cnt[6]; 3094 } 3095 3096 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry, 3097 void *context, int vl, int mode, 3098 u64 data) 3099 { 3100 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3101 3102 return dd->send_pio_err_status_cnt[5]; 3103 } 3104 3105 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry, 3106 void *context, int vl, int mode, 3107 u64 data) 3108 { 3109 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3110 3111 return dd->send_pio_err_status_cnt[4]; 3112 } 3113 3114 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry, 3115 void *context, int vl, int mode, 3116 u64 data) 3117 { 3118 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3119 3120 return dd->send_pio_err_status_cnt[3]; 3121 } 3122 3123 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry, 3124 void *context, int vl, int mode, 3125 u64 data) 3126 { 3127 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3128 3129 return dd->send_pio_err_status_cnt[2]; 3130 } 3131 3132 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry, 3133 void *context, int vl, 3134 int mode, u64 data) 3135 { 3136 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3137 3138 return dd->send_pio_err_status_cnt[1]; 3139 } 3140 3141 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry, 3142 void *context, int vl, int mode, 3143 u64 data) 3144 { 3145 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3146 3147 return dd->send_pio_err_status_cnt[0]; 3148 } 3149 3150 /* 3151 * Software counters corresponding to each of the 3152 * error status bits within SendDmaErrStatus 3153 */ 3154 static u64 access_sdma_pcie_req_tracking_cor_err_cnt( 3155 const struct cntr_entry *entry, 3156 void *context, int vl, int mode, u64 data) 3157 { 3158 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3159 3160 return dd->send_dma_err_status_cnt[3]; 3161 } 3162 3163 static u64 access_sdma_pcie_req_tracking_unc_err_cnt( 3164 const struct cntr_entry *entry, 3165 void *context, int vl, int mode, u64 data) 3166 { 3167 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3168 3169 return dd->send_dma_err_status_cnt[2]; 3170 } 3171 3172 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry, 3173 void *context, int vl, int mode, 3174 u64 data) 3175 { 3176 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3177 3178 return dd->send_dma_err_status_cnt[1]; 3179 } 3180 3181 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry, 3182 void *context, int vl, int mode, 3183 u64 data) 3184 { 3185 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3186 3187 return dd->send_dma_err_status_cnt[0]; 3188 } 3189 3190 /* 3191 * Software counters corresponding to each of the 3192 * error status bits within SendEgressErrStatus 3193 */ 3194 static u64 access_tx_read_pio_memory_csr_unc_err_cnt( 3195 const struct cntr_entry *entry, 3196 void *context, int vl, int mode, u64 data) 3197 { 3198 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3199 3200 return dd->send_egress_err_status_cnt[63]; 3201 } 3202 3203 static u64 access_tx_read_sdma_memory_csr_err_cnt( 3204 const struct cntr_entry *entry, 3205 void *context, int vl, int mode, u64 data) 3206 { 3207 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3208 3209 return dd->send_egress_err_status_cnt[62]; 3210 } 3211 3212 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry, 3213 void *context, int vl, int mode, 3214 u64 data) 3215 { 3216 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3217 3218 return dd->send_egress_err_status_cnt[61]; 3219 } 3220 3221 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry, 3222 void *context, int vl, 3223 int mode, u64 data) 3224 { 3225 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3226 3227 return dd->send_egress_err_status_cnt[60]; 3228 } 3229 3230 static u64 access_tx_read_sdma_memory_cor_err_cnt( 3231 const struct cntr_entry *entry, 3232 void *context, int vl, int mode, u64 data) 3233 { 3234 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3235 3236 return dd->send_egress_err_status_cnt[59]; 3237 } 3238 3239 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry, 3240 void *context, int vl, int mode, 3241 u64 data) 3242 { 3243 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3244 3245 return dd->send_egress_err_status_cnt[58]; 3246 } 3247 3248 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry, 3249 void *context, int vl, int mode, 3250 u64 data) 3251 { 3252 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3253 3254 return dd->send_egress_err_status_cnt[57]; 3255 } 3256 3257 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry, 3258 void *context, int vl, int mode, 3259 u64 data) 3260 { 3261 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3262 3263 return dd->send_egress_err_status_cnt[56]; 3264 } 3265 3266 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry, 3267 void *context, int vl, int mode, 3268 u64 data) 3269 { 3270 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3271 3272 return dd->send_egress_err_status_cnt[55]; 3273 } 3274 3275 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry, 3276 void *context, int vl, int mode, 3277 u64 data) 3278 { 3279 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3280 3281 return dd->send_egress_err_status_cnt[54]; 3282 } 3283 3284 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry, 3285 void *context, int vl, int mode, 3286 u64 data) 3287 { 3288 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3289 3290 return dd->send_egress_err_status_cnt[53]; 3291 } 3292 3293 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry, 3294 void *context, int vl, int mode, 3295 u64 data) 3296 { 3297 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3298 3299 return dd->send_egress_err_status_cnt[52]; 3300 } 3301 3302 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry, 3303 void *context, int vl, int mode, 3304 u64 data) 3305 { 3306 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3307 3308 return dd->send_egress_err_status_cnt[51]; 3309 } 3310 3311 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry, 3312 void *context, int vl, int mode, 3313 u64 data) 3314 { 3315 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3316 3317 return dd->send_egress_err_status_cnt[50]; 3318 } 3319 3320 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry, 3321 void *context, int vl, int mode, 3322 u64 data) 3323 { 3324 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3325 3326 return dd->send_egress_err_status_cnt[49]; 3327 } 3328 3329 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry, 3330 void *context, int vl, int mode, 3331 u64 data) 3332 { 3333 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3334 3335 return dd->send_egress_err_status_cnt[48]; 3336 } 3337 3338 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry, 3339 void *context, int vl, int mode, 3340 u64 data) 3341 { 3342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3343 3344 return dd->send_egress_err_status_cnt[47]; 3345 } 3346 3347 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry, 3348 void *context, int vl, int mode, 3349 u64 data) 3350 { 3351 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3352 3353 return dd->send_egress_err_status_cnt[46]; 3354 } 3355 3356 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry, 3357 void *context, int vl, int mode, 3358 u64 data) 3359 { 3360 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3361 3362 return dd->send_egress_err_status_cnt[45]; 3363 } 3364 3365 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry, 3366 void *context, int vl, 3367 int mode, u64 data) 3368 { 3369 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3370 3371 return dd->send_egress_err_status_cnt[44]; 3372 } 3373 3374 static u64 access_tx_read_sdma_memory_unc_err_cnt( 3375 const struct cntr_entry *entry, 3376 void *context, int vl, int mode, u64 data) 3377 { 3378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3379 3380 return dd->send_egress_err_status_cnt[43]; 3381 } 3382 3383 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry, 3384 void *context, int vl, int mode, 3385 u64 data) 3386 { 3387 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3388 3389 return dd->send_egress_err_status_cnt[42]; 3390 } 3391 3392 static u64 access_tx_credit_return_partiy_err_cnt( 3393 const struct cntr_entry *entry, 3394 void *context, int vl, int mode, u64 data) 3395 { 3396 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3397 3398 return dd->send_egress_err_status_cnt[41]; 3399 } 3400 3401 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt( 3402 const struct cntr_entry *entry, 3403 void *context, int vl, int mode, u64 data) 3404 { 3405 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3406 3407 return dd->send_egress_err_status_cnt[40]; 3408 } 3409 3410 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt( 3411 const struct cntr_entry *entry, 3412 void *context, int vl, int mode, u64 data) 3413 { 3414 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3415 3416 return dd->send_egress_err_status_cnt[39]; 3417 } 3418 3419 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt( 3420 const struct cntr_entry *entry, 3421 void *context, int vl, int mode, u64 data) 3422 { 3423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3424 3425 return dd->send_egress_err_status_cnt[38]; 3426 } 3427 3428 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt( 3429 const struct cntr_entry *entry, 3430 void *context, int vl, int mode, u64 data) 3431 { 3432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3433 3434 return dd->send_egress_err_status_cnt[37]; 3435 } 3436 3437 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt( 3438 const struct cntr_entry *entry, 3439 void *context, int vl, int mode, u64 data) 3440 { 3441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3442 3443 return dd->send_egress_err_status_cnt[36]; 3444 } 3445 3446 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt( 3447 const struct cntr_entry *entry, 3448 void *context, int vl, int mode, u64 data) 3449 { 3450 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3451 3452 return dd->send_egress_err_status_cnt[35]; 3453 } 3454 3455 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt( 3456 const struct cntr_entry *entry, 3457 void *context, int vl, int mode, u64 data) 3458 { 3459 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3460 3461 return dd->send_egress_err_status_cnt[34]; 3462 } 3463 3464 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt( 3465 const struct cntr_entry *entry, 3466 void *context, int vl, int mode, u64 data) 3467 { 3468 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3469 3470 return dd->send_egress_err_status_cnt[33]; 3471 } 3472 3473 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt( 3474 const struct cntr_entry *entry, 3475 void *context, int vl, int mode, u64 data) 3476 { 3477 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3478 3479 return dd->send_egress_err_status_cnt[32]; 3480 } 3481 3482 static u64 access_tx_sdma15_disallowed_packet_err_cnt( 3483 const struct cntr_entry *entry, 3484 void *context, int vl, int mode, u64 data) 3485 { 3486 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3487 3488 return dd->send_egress_err_status_cnt[31]; 3489 } 3490 3491 static u64 access_tx_sdma14_disallowed_packet_err_cnt( 3492 const struct cntr_entry *entry, 3493 void *context, int vl, int mode, u64 data) 3494 { 3495 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3496 3497 return dd->send_egress_err_status_cnt[30]; 3498 } 3499 3500 static u64 access_tx_sdma13_disallowed_packet_err_cnt( 3501 const struct cntr_entry *entry, 3502 void *context, int vl, int mode, u64 data) 3503 { 3504 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3505 3506 return dd->send_egress_err_status_cnt[29]; 3507 } 3508 3509 static u64 access_tx_sdma12_disallowed_packet_err_cnt( 3510 const struct cntr_entry *entry, 3511 void *context, int vl, int mode, u64 data) 3512 { 3513 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3514 3515 return dd->send_egress_err_status_cnt[28]; 3516 } 3517 3518 static u64 access_tx_sdma11_disallowed_packet_err_cnt( 3519 const struct cntr_entry *entry, 3520 void *context, int vl, int mode, u64 data) 3521 { 3522 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3523 3524 return dd->send_egress_err_status_cnt[27]; 3525 } 3526 3527 static u64 access_tx_sdma10_disallowed_packet_err_cnt( 3528 const struct cntr_entry *entry, 3529 void *context, int vl, int mode, u64 data) 3530 { 3531 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3532 3533 return dd->send_egress_err_status_cnt[26]; 3534 } 3535 3536 static u64 access_tx_sdma9_disallowed_packet_err_cnt( 3537 const struct cntr_entry *entry, 3538 void *context, int vl, int mode, u64 data) 3539 { 3540 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3541 3542 return dd->send_egress_err_status_cnt[25]; 3543 } 3544 3545 static u64 access_tx_sdma8_disallowed_packet_err_cnt( 3546 const struct cntr_entry *entry, 3547 void *context, int vl, int mode, u64 data) 3548 { 3549 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3550 3551 return dd->send_egress_err_status_cnt[24]; 3552 } 3553 3554 static u64 access_tx_sdma7_disallowed_packet_err_cnt( 3555 const struct cntr_entry *entry, 3556 void *context, int vl, int mode, u64 data) 3557 { 3558 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3559 3560 return dd->send_egress_err_status_cnt[23]; 3561 } 3562 3563 static u64 access_tx_sdma6_disallowed_packet_err_cnt( 3564 const struct cntr_entry *entry, 3565 void *context, int vl, int mode, u64 data) 3566 { 3567 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3568 3569 return dd->send_egress_err_status_cnt[22]; 3570 } 3571 3572 static u64 access_tx_sdma5_disallowed_packet_err_cnt( 3573 const struct cntr_entry *entry, 3574 void *context, int vl, int mode, u64 data) 3575 { 3576 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3577 3578 return dd->send_egress_err_status_cnt[21]; 3579 } 3580 3581 static u64 access_tx_sdma4_disallowed_packet_err_cnt( 3582 const struct cntr_entry *entry, 3583 void *context, int vl, int mode, u64 data) 3584 { 3585 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3586 3587 return dd->send_egress_err_status_cnt[20]; 3588 } 3589 3590 static u64 access_tx_sdma3_disallowed_packet_err_cnt( 3591 const struct cntr_entry *entry, 3592 void *context, int vl, int mode, u64 data) 3593 { 3594 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3595 3596 return dd->send_egress_err_status_cnt[19]; 3597 } 3598 3599 static u64 access_tx_sdma2_disallowed_packet_err_cnt( 3600 const struct cntr_entry *entry, 3601 void *context, int vl, int mode, u64 data) 3602 { 3603 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3604 3605 return dd->send_egress_err_status_cnt[18]; 3606 } 3607 3608 static u64 access_tx_sdma1_disallowed_packet_err_cnt( 3609 const struct cntr_entry *entry, 3610 void *context, int vl, int mode, u64 data) 3611 { 3612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3613 3614 return dd->send_egress_err_status_cnt[17]; 3615 } 3616 3617 static u64 access_tx_sdma0_disallowed_packet_err_cnt( 3618 const struct cntr_entry *entry, 3619 void *context, int vl, int mode, u64 data) 3620 { 3621 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3622 3623 return dd->send_egress_err_status_cnt[16]; 3624 } 3625 3626 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry, 3627 void *context, int vl, int mode, 3628 u64 data) 3629 { 3630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3631 3632 return dd->send_egress_err_status_cnt[15]; 3633 } 3634 3635 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry, 3636 void *context, int vl, 3637 int mode, u64 data) 3638 { 3639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3640 3641 return dd->send_egress_err_status_cnt[14]; 3642 } 3643 3644 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry, 3645 void *context, int vl, int mode, 3646 u64 data) 3647 { 3648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3649 3650 return dd->send_egress_err_status_cnt[13]; 3651 } 3652 3653 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry, 3654 void *context, int vl, int mode, 3655 u64 data) 3656 { 3657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3658 3659 return dd->send_egress_err_status_cnt[12]; 3660 } 3661 3662 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt( 3663 const struct cntr_entry *entry, 3664 void *context, int vl, int mode, u64 data) 3665 { 3666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3667 3668 return dd->send_egress_err_status_cnt[11]; 3669 } 3670 3671 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry, 3672 void *context, int vl, int mode, 3673 u64 data) 3674 { 3675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3676 3677 return dd->send_egress_err_status_cnt[10]; 3678 } 3679 3680 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry, 3681 void *context, int vl, int mode, 3682 u64 data) 3683 { 3684 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3685 3686 return dd->send_egress_err_status_cnt[9]; 3687 } 3688 3689 static u64 access_tx_sdma_launch_intf_parity_err_cnt( 3690 const struct cntr_entry *entry, 3691 void *context, int vl, int mode, u64 data) 3692 { 3693 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3694 3695 return dd->send_egress_err_status_cnt[8]; 3696 } 3697 3698 static u64 access_tx_pio_launch_intf_parity_err_cnt( 3699 const struct cntr_entry *entry, 3700 void *context, int vl, int mode, u64 data) 3701 { 3702 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3703 3704 return dd->send_egress_err_status_cnt[7]; 3705 } 3706 3707 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry, 3708 void *context, int vl, int mode, 3709 u64 data) 3710 { 3711 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3712 3713 return dd->send_egress_err_status_cnt[6]; 3714 } 3715 3716 static u64 access_tx_incorrect_link_state_err_cnt( 3717 const struct cntr_entry *entry, 3718 void *context, int vl, int mode, u64 data) 3719 { 3720 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3721 3722 return dd->send_egress_err_status_cnt[5]; 3723 } 3724 3725 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry, 3726 void *context, int vl, int mode, 3727 u64 data) 3728 { 3729 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3730 3731 return dd->send_egress_err_status_cnt[4]; 3732 } 3733 3734 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt( 3735 const struct cntr_entry *entry, 3736 void *context, int vl, int mode, u64 data) 3737 { 3738 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3739 3740 return dd->send_egress_err_status_cnt[3]; 3741 } 3742 3743 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry, 3744 void *context, int vl, int mode, 3745 u64 data) 3746 { 3747 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3748 3749 return dd->send_egress_err_status_cnt[2]; 3750 } 3751 3752 static u64 access_tx_pkt_integrity_mem_unc_err_cnt( 3753 const struct cntr_entry *entry, 3754 void *context, int vl, int mode, u64 data) 3755 { 3756 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3757 3758 return dd->send_egress_err_status_cnt[1]; 3759 } 3760 3761 static u64 access_tx_pkt_integrity_mem_cor_err_cnt( 3762 const struct cntr_entry *entry, 3763 void *context, int vl, int mode, u64 data) 3764 { 3765 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3766 3767 return dd->send_egress_err_status_cnt[0]; 3768 } 3769 3770 /* 3771 * Software counters corresponding to each of the 3772 * error status bits within SendErrStatus 3773 */ 3774 static u64 access_send_csr_write_bad_addr_err_cnt( 3775 const struct cntr_entry *entry, 3776 void *context, int vl, int mode, u64 data) 3777 { 3778 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3779 3780 return dd->send_err_status_cnt[2]; 3781 } 3782 3783 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 3784 void *context, int vl, 3785 int mode, u64 data) 3786 { 3787 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3788 3789 return dd->send_err_status_cnt[1]; 3790 } 3791 3792 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry, 3793 void *context, int vl, int mode, 3794 u64 data) 3795 { 3796 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3797 3798 return dd->send_err_status_cnt[0]; 3799 } 3800 3801 /* 3802 * Software counters corresponding to each of the 3803 * error status bits within SendCtxtErrStatus 3804 */ 3805 static u64 access_pio_write_out_of_bounds_err_cnt( 3806 const struct cntr_entry *entry, 3807 void *context, int vl, int mode, u64 data) 3808 { 3809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3810 3811 return dd->sw_ctxt_err_status_cnt[4]; 3812 } 3813 3814 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry, 3815 void *context, int vl, int mode, 3816 u64 data) 3817 { 3818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3819 3820 return dd->sw_ctxt_err_status_cnt[3]; 3821 } 3822 3823 static u64 access_pio_write_crosses_boundary_err_cnt( 3824 const struct cntr_entry *entry, 3825 void *context, int vl, int mode, u64 data) 3826 { 3827 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3828 3829 return dd->sw_ctxt_err_status_cnt[2]; 3830 } 3831 3832 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry, 3833 void *context, int vl, 3834 int mode, u64 data) 3835 { 3836 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3837 3838 return dd->sw_ctxt_err_status_cnt[1]; 3839 } 3840 3841 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry, 3842 void *context, int vl, int mode, 3843 u64 data) 3844 { 3845 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3846 3847 return dd->sw_ctxt_err_status_cnt[0]; 3848 } 3849 3850 /* 3851 * Software counters corresponding to each of the 3852 * error status bits within SendDmaEngErrStatus 3853 */ 3854 static u64 access_sdma_header_request_fifo_cor_err_cnt( 3855 const struct cntr_entry *entry, 3856 void *context, int vl, int mode, u64 data) 3857 { 3858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3859 3860 return dd->sw_send_dma_eng_err_status_cnt[23]; 3861 } 3862 3863 static u64 access_sdma_header_storage_cor_err_cnt( 3864 const struct cntr_entry *entry, 3865 void *context, int vl, int mode, u64 data) 3866 { 3867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3868 3869 return dd->sw_send_dma_eng_err_status_cnt[22]; 3870 } 3871 3872 static u64 access_sdma_packet_tracking_cor_err_cnt( 3873 const struct cntr_entry *entry, 3874 void *context, int vl, int mode, u64 data) 3875 { 3876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3877 3878 return dd->sw_send_dma_eng_err_status_cnt[21]; 3879 } 3880 3881 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry, 3882 void *context, int vl, int mode, 3883 u64 data) 3884 { 3885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3886 3887 return dd->sw_send_dma_eng_err_status_cnt[20]; 3888 } 3889 3890 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry, 3891 void *context, int vl, int mode, 3892 u64 data) 3893 { 3894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3895 3896 return dd->sw_send_dma_eng_err_status_cnt[19]; 3897 } 3898 3899 static u64 access_sdma_header_request_fifo_unc_err_cnt( 3900 const struct cntr_entry *entry, 3901 void *context, int vl, int mode, u64 data) 3902 { 3903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3904 3905 return dd->sw_send_dma_eng_err_status_cnt[18]; 3906 } 3907 3908 static u64 access_sdma_header_storage_unc_err_cnt( 3909 const struct cntr_entry *entry, 3910 void *context, int vl, int mode, u64 data) 3911 { 3912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3913 3914 return dd->sw_send_dma_eng_err_status_cnt[17]; 3915 } 3916 3917 static u64 access_sdma_packet_tracking_unc_err_cnt( 3918 const struct cntr_entry *entry, 3919 void *context, int vl, int mode, u64 data) 3920 { 3921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3922 3923 return dd->sw_send_dma_eng_err_status_cnt[16]; 3924 } 3925 3926 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry, 3927 void *context, int vl, int mode, 3928 u64 data) 3929 { 3930 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3931 3932 return dd->sw_send_dma_eng_err_status_cnt[15]; 3933 } 3934 3935 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry, 3936 void *context, int vl, int mode, 3937 u64 data) 3938 { 3939 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3940 3941 return dd->sw_send_dma_eng_err_status_cnt[14]; 3942 } 3943 3944 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry, 3945 void *context, int vl, int mode, 3946 u64 data) 3947 { 3948 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3949 3950 return dd->sw_send_dma_eng_err_status_cnt[13]; 3951 } 3952 3953 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry, 3954 void *context, int vl, int mode, 3955 u64 data) 3956 { 3957 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3958 3959 return dd->sw_send_dma_eng_err_status_cnt[12]; 3960 } 3961 3962 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry, 3963 void *context, int vl, int mode, 3964 u64 data) 3965 { 3966 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3967 3968 return dd->sw_send_dma_eng_err_status_cnt[11]; 3969 } 3970 3971 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry, 3972 void *context, int vl, int mode, 3973 u64 data) 3974 { 3975 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3976 3977 return dd->sw_send_dma_eng_err_status_cnt[10]; 3978 } 3979 3980 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry, 3981 void *context, int vl, int mode, 3982 u64 data) 3983 { 3984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3985 3986 return dd->sw_send_dma_eng_err_status_cnt[9]; 3987 } 3988 3989 static u64 access_sdma_packet_desc_overflow_err_cnt( 3990 const struct cntr_entry *entry, 3991 void *context, int vl, int mode, u64 data) 3992 { 3993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3994 3995 return dd->sw_send_dma_eng_err_status_cnt[8]; 3996 } 3997 3998 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry, 3999 void *context, int vl, 4000 int mode, u64 data) 4001 { 4002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4003 4004 return dd->sw_send_dma_eng_err_status_cnt[7]; 4005 } 4006 4007 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry, 4008 void *context, int vl, int mode, u64 data) 4009 { 4010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4011 4012 return dd->sw_send_dma_eng_err_status_cnt[6]; 4013 } 4014 4015 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry, 4016 void *context, int vl, int mode, 4017 u64 data) 4018 { 4019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4020 4021 return dd->sw_send_dma_eng_err_status_cnt[5]; 4022 } 4023 4024 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry, 4025 void *context, int vl, int mode, 4026 u64 data) 4027 { 4028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4029 4030 return dd->sw_send_dma_eng_err_status_cnt[4]; 4031 } 4032 4033 static u64 access_sdma_tail_out_of_bounds_err_cnt( 4034 const struct cntr_entry *entry, 4035 void *context, int vl, int mode, u64 data) 4036 { 4037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4038 4039 return dd->sw_send_dma_eng_err_status_cnt[3]; 4040 } 4041 4042 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry, 4043 void *context, int vl, int mode, 4044 u64 data) 4045 { 4046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4047 4048 return dd->sw_send_dma_eng_err_status_cnt[2]; 4049 } 4050 4051 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry, 4052 void *context, int vl, int mode, 4053 u64 data) 4054 { 4055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4056 4057 return dd->sw_send_dma_eng_err_status_cnt[1]; 4058 } 4059 4060 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry, 4061 void *context, int vl, int mode, 4062 u64 data) 4063 { 4064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4065 4066 return dd->sw_send_dma_eng_err_status_cnt[0]; 4067 } 4068 4069 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry, 4070 void *context, int vl, int mode, 4071 u64 data) 4072 { 4073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4074 4075 u64 val = 0; 4076 u64 csr = entry->csr; 4077 4078 val = read_write_csr(dd, csr, mode, data); 4079 if (mode == CNTR_MODE_R) { 4080 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ? 4081 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors; 4082 } else if (mode == CNTR_MODE_W) { 4083 dd->sw_rcv_bypass_packet_errors = 0; 4084 } else { 4085 dd_dev_err(dd, "Invalid cntr register access mode"); 4086 return 0; 4087 } 4088 return val; 4089 } 4090 4091 #define def_access_sw_cpu(cntr) \ 4092 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \ 4093 void *context, int vl, int mode, u64 data) \ 4094 { \ 4095 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4096 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \ 4097 ppd->ibport_data.rvp.cntr, vl, \ 4098 mode, data); \ 4099 } 4100 4101 def_access_sw_cpu(rc_acks); 4102 def_access_sw_cpu(rc_qacks); 4103 def_access_sw_cpu(rc_delayed_comp); 4104 4105 #define def_access_ibp_counter(cntr) \ 4106 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \ 4107 void *context, int vl, int mode, u64 data) \ 4108 { \ 4109 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4110 \ 4111 if (vl != CNTR_INVALID_VL) \ 4112 return 0; \ 4113 \ 4114 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \ 4115 mode, data); \ 4116 } 4117 4118 def_access_ibp_counter(loop_pkts); 4119 def_access_ibp_counter(rc_resends); 4120 def_access_ibp_counter(rnr_naks); 4121 def_access_ibp_counter(other_naks); 4122 def_access_ibp_counter(rc_timeouts); 4123 def_access_ibp_counter(pkt_drops); 4124 def_access_ibp_counter(dmawait); 4125 def_access_ibp_counter(rc_seqnak); 4126 def_access_ibp_counter(rc_dupreq); 4127 def_access_ibp_counter(rdma_seq); 4128 def_access_ibp_counter(unaligned); 4129 def_access_ibp_counter(seq_naks); 4130 def_access_ibp_counter(rc_crwaits); 4131 4132 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = { 4133 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH), 4134 [C_RX_LEN_ERR] = RXE32_DEV_CNTR_ELEM(RxLenErr, RCV_LENGTH_ERR_CNT, CNTR_SYNTH), 4135 [C_RX_SHORT_ERR] = RXE32_DEV_CNTR_ELEM(RxShrErr, RCV_SHORT_ERR_CNT, CNTR_SYNTH), 4136 [C_RX_ICRC_ERR] = RXE32_DEV_CNTR_ELEM(RxICrcErr, RCV_ICRC_ERR_CNT, CNTR_SYNTH), 4137 [C_RX_EBP] = RXE32_DEV_CNTR_ELEM(RxEbpCnt, RCV_EBP_CNT, CNTR_SYNTH), 4138 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT, 4139 CNTR_NORMAL), 4140 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT, 4141 CNTR_NORMAL), 4142 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs, 4143 RCV_TID_FLOW_GEN_MISMATCH_CNT, 4144 CNTR_NORMAL), 4145 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL, 4146 CNTR_NORMAL), 4147 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs, 4148 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL), 4149 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt, 4150 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL), 4151 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT, 4152 CNTR_NORMAL), 4153 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT, 4154 CNTR_NORMAL), 4155 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT, 4156 CNTR_NORMAL), 4157 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT, 4158 CNTR_NORMAL), 4159 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT, 4160 CNTR_NORMAL), 4161 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT, 4162 CNTR_NORMAL), 4163 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt, 4164 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL), 4165 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt, 4166 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL), 4167 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT, 4168 CNTR_SYNTH), 4169 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH, 4170 access_dc_rcv_err_cnt), 4171 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT, 4172 CNTR_SYNTH), 4173 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT, 4174 CNTR_SYNTH), 4175 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT, 4176 CNTR_SYNTH), 4177 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts, 4178 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH), 4179 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts, 4180 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT, 4181 CNTR_SYNTH), 4182 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr, 4183 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH), 4184 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT, 4185 CNTR_SYNTH), 4186 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT, 4187 CNTR_SYNTH), 4188 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT, 4189 CNTR_SYNTH), 4190 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT, 4191 CNTR_SYNTH), 4192 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT, 4193 CNTR_SYNTH), 4194 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT, 4195 CNTR_SYNTH), 4196 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT, 4197 CNTR_SYNTH), 4198 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT, 4199 CNTR_SYNTH | CNTR_VL), 4200 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT, 4201 CNTR_SYNTH | CNTR_VL), 4202 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH), 4203 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT, 4204 CNTR_SYNTH | CNTR_VL), 4205 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH), 4206 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT, 4207 CNTR_SYNTH | CNTR_VL), 4208 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT, 4209 CNTR_SYNTH), 4210 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT, 4211 CNTR_SYNTH | CNTR_VL), 4212 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT, 4213 CNTR_SYNTH), 4214 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT, 4215 CNTR_SYNTH | CNTR_VL), 4216 [C_DC_TOTAL_CRC] = 4217 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR, 4218 CNTR_SYNTH), 4219 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0, 4220 CNTR_SYNTH), 4221 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1, 4222 CNTR_SYNTH), 4223 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2, 4224 CNTR_SYNTH), 4225 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3, 4226 CNTR_SYNTH), 4227 [C_DC_CRC_MULT_LN] = 4228 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN, 4229 CNTR_SYNTH), 4230 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT, 4231 CNTR_SYNTH), 4232 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT, 4233 CNTR_SYNTH), 4234 [C_DC_SEQ_CRC_CNT] = 4235 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT, 4236 CNTR_SYNTH), 4237 [C_DC_ESC0_ONLY_CNT] = 4238 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT, 4239 CNTR_SYNTH), 4240 [C_DC_ESC0_PLUS1_CNT] = 4241 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT, 4242 CNTR_SYNTH), 4243 [C_DC_ESC0_PLUS2_CNT] = 4244 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT, 4245 CNTR_SYNTH), 4246 [C_DC_REINIT_FROM_PEER_CNT] = 4247 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 4248 CNTR_SYNTH), 4249 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT, 4250 CNTR_SYNTH), 4251 [C_DC_MISC_FLG_CNT] = 4252 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT, 4253 CNTR_SYNTH), 4254 [C_DC_PRF_GOOD_LTP_CNT] = 4255 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH), 4256 [C_DC_PRF_ACCEPTED_LTP_CNT] = 4257 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT, 4258 CNTR_SYNTH), 4259 [C_DC_PRF_RX_FLIT_CNT] = 4260 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH), 4261 [C_DC_PRF_TX_FLIT_CNT] = 4262 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH), 4263 [C_DC_PRF_CLK_CNTR] = 4264 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH), 4265 [C_DC_PG_DBG_FLIT_CRDTS_CNT] = 4266 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH), 4267 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] = 4268 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT, 4269 CNTR_SYNTH), 4270 [C_DC_PG_STS_TX_SBE_CNT] = 4271 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH), 4272 [C_DC_PG_STS_TX_MBE_CNT] = 4273 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT, 4274 CNTR_SYNTH), 4275 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL, 4276 access_sw_cpu_intr), 4277 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL, 4278 access_sw_cpu_rcv_limit), 4279 [C_SW_CTX0_SEQ_DROP] = CNTR_ELEM("SeqDrop0", 0, 0, CNTR_NORMAL, 4280 access_sw_ctx0_seq_drop), 4281 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL, 4282 access_sw_vtx_wait), 4283 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL, 4284 access_sw_pio_wait), 4285 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL, 4286 access_sw_pio_drain), 4287 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL, 4288 access_sw_kmem_wait), 4289 [C_SW_TID_WAIT] = CNTR_ELEM("TidWait", 0, 0, CNTR_NORMAL, 4290 hfi1_access_sw_tid_wait), 4291 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL, 4292 access_sw_send_schedule), 4293 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn", 4294 SEND_DMA_DESC_FETCHED_CNT, 0, 4295 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4296 dev_access_u32_csr), 4297 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0, 4298 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4299 access_sde_int_cnt), 4300 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0, 4301 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4302 access_sde_err_cnt), 4303 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0, 4304 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4305 access_sde_idle_int_cnt), 4306 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0, 4307 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4308 access_sde_progress_int_cnt), 4309 /* MISC_ERR_STATUS */ 4310 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0, 4311 CNTR_NORMAL, 4312 access_misc_pll_lock_fail_err_cnt), 4313 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0, 4314 CNTR_NORMAL, 4315 access_misc_mbist_fail_err_cnt), 4316 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0, 4317 CNTR_NORMAL, 4318 access_misc_invalid_eep_cmd_err_cnt), 4319 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0, 4320 CNTR_NORMAL, 4321 access_misc_efuse_done_parity_err_cnt), 4322 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0, 4323 CNTR_NORMAL, 4324 access_misc_efuse_write_err_cnt), 4325 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0, 4326 0, CNTR_NORMAL, 4327 access_misc_efuse_read_bad_addr_err_cnt), 4328 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0, 4329 CNTR_NORMAL, 4330 access_misc_efuse_csr_parity_err_cnt), 4331 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0, 4332 CNTR_NORMAL, 4333 access_misc_fw_auth_failed_err_cnt), 4334 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0, 4335 CNTR_NORMAL, 4336 access_misc_key_mismatch_err_cnt), 4337 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0, 4338 CNTR_NORMAL, 4339 access_misc_sbus_write_failed_err_cnt), 4340 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0, 4341 CNTR_NORMAL, 4342 access_misc_csr_write_bad_addr_err_cnt), 4343 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0, 4344 CNTR_NORMAL, 4345 access_misc_csr_read_bad_addr_err_cnt), 4346 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0, 4347 CNTR_NORMAL, 4348 access_misc_csr_parity_err_cnt), 4349 /* CceErrStatus */ 4350 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0, 4351 CNTR_NORMAL, 4352 access_sw_cce_err_status_aggregated_cnt), 4353 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0, 4354 CNTR_NORMAL, 4355 access_cce_msix_csr_parity_err_cnt), 4356 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0, 4357 CNTR_NORMAL, 4358 access_cce_int_map_unc_err_cnt), 4359 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0, 4360 CNTR_NORMAL, 4361 access_cce_int_map_cor_err_cnt), 4362 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0, 4363 CNTR_NORMAL, 4364 access_cce_msix_table_unc_err_cnt), 4365 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0, 4366 CNTR_NORMAL, 4367 access_cce_msix_table_cor_err_cnt), 4368 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0, 4369 0, CNTR_NORMAL, 4370 access_cce_rxdma_conv_fifo_parity_err_cnt), 4371 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0, 4372 0, CNTR_NORMAL, 4373 access_cce_rcpl_async_fifo_parity_err_cnt), 4374 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0, 4375 CNTR_NORMAL, 4376 access_cce_seg_write_bad_addr_err_cnt), 4377 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0, 4378 CNTR_NORMAL, 4379 access_cce_seg_read_bad_addr_err_cnt), 4380 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0, 4381 CNTR_NORMAL, 4382 access_la_triggered_cnt), 4383 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0, 4384 CNTR_NORMAL, 4385 access_cce_trgt_cpl_timeout_err_cnt), 4386 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0, 4387 CNTR_NORMAL, 4388 access_pcic_receive_parity_err_cnt), 4389 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0, 4390 CNTR_NORMAL, 4391 access_pcic_transmit_back_parity_err_cnt), 4392 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0, 4393 0, CNTR_NORMAL, 4394 access_pcic_transmit_front_parity_err_cnt), 4395 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0, 4396 CNTR_NORMAL, 4397 access_pcic_cpl_dat_q_unc_err_cnt), 4398 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0, 4399 CNTR_NORMAL, 4400 access_pcic_cpl_hd_q_unc_err_cnt), 4401 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0, 4402 CNTR_NORMAL, 4403 access_pcic_post_dat_q_unc_err_cnt), 4404 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0, 4405 CNTR_NORMAL, 4406 access_pcic_post_hd_q_unc_err_cnt), 4407 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0, 4408 CNTR_NORMAL, 4409 access_pcic_retry_sot_mem_unc_err_cnt), 4410 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0, 4411 CNTR_NORMAL, 4412 access_pcic_retry_mem_unc_err), 4413 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0, 4414 CNTR_NORMAL, 4415 access_pcic_n_post_dat_q_parity_err_cnt), 4416 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0, 4417 CNTR_NORMAL, 4418 access_pcic_n_post_h_q_parity_err_cnt), 4419 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0, 4420 CNTR_NORMAL, 4421 access_pcic_cpl_dat_q_cor_err_cnt), 4422 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0, 4423 CNTR_NORMAL, 4424 access_pcic_cpl_hd_q_cor_err_cnt), 4425 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0, 4426 CNTR_NORMAL, 4427 access_pcic_post_dat_q_cor_err_cnt), 4428 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0, 4429 CNTR_NORMAL, 4430 access_pcic_post_hd_q_cor_err_cnt), 4431 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0, 4432 CNTR_NORMAL, 4433 access_pcic_retry_sot_mem_cor_err_cnt), 4434 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0, 4435 CNTR_NORMAL, 4436 access_pcic_retry_mem_cor_err_cnt), 4437 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM( 4438 "CceCli1AsyncFifoDbgParityError", 0, 0, 4439 CNTR_NORMAL, 4440 access_cce_cli1_async_fifo_dbg_parity_err_cnt), 4441 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM( 4442 "CceCli1AsyncFifoRxdmaParityError", 0, 0, 4443 CNTR_NORMAL, 4444 access_cce_cli1_async_fifo_rxdma_parity_err_cnt 4445 ), 4446 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM( 4447 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0, 4448 CNTR_NORMAL, 4449 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt), 4450 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM( 4451 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0, 4452 CNTR_NORMAL, 4453 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt), 4454 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0, 4455 0, CNTR_NORMAL, 4456 access_cce_cli2_async_fifo_parity_err_cnt), 4457 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0, 4458 CNTR_NORMAL, 4459 access_cce_csr_cfg_bus_parity_err_cnt), 4460 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0, 4461 0, CNTR_NORMAL, 4462 access_cce_cli0_async_fifo_parity_err_cnt), 4463 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0, 4464 CNTR_NORMAL, 4465 access_cce_rspd_data_parity_err_cnt), 4466 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0, 4467 CNTR_NORMAL, 4468 access_cce_trgt_access_err_cnt), 4469 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0, 4470 0, CNTR_NORMAL, 4471 access_cce_trgt_async_fifo_parity_err_cnt), 4472 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0, 4473 CNTR_NORMAL, 4474 access_cce_csr_write_bad_addr_err_cnt), 4475 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0, 4476 CNTR_NORMAL, 4477 access_cce_csr_read_bad_addr_err_cnt), 4478 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0, 4479 CNTR_NORMAL, 4480 access_ccs_csr_parity_err_cnt), 4481 4482 /* RcvErrStatus */ 4483 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0, 4484 CNTR_NORMAL, 4485 access_rx_csr_parity_err_cnt), 4486 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0, 4487 CNTR_NORMAL, 4488 access_rx_csr_write_bad_addr_err_cnt), 4489 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0, 4490 CNTR_NORMAL, 4491 access_rx_csr_read_bad_addr_err_cnt), 4492 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0, 4493 CNTR_NORMAL, 4494 access_rx_dma_csr_unc_err_cnt), 4495 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0, 4496 CNTR_NORMAL, 4497 access_rx_dma_dq_fsm_encoding_err_cnt), 4498 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0, 4499 CNTR_NORMAL, 4500 access_rx_dma_eq_fsm_encoding_err_cnt), 4501 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0, 4502 CNTR_NORMAL, 4503 access_rx_dma_csr_parity_err_cnt), 4504 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0, 4505 CNTR_NORMAL, 4506 access_rx_rbuf_data_cor_err_cnt), 4507 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0, 4508 CNTR_NORMAL, 4509 access_rx_rbuf_data_unc_err_cnt), 4510 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0, 4511 CNTR_NORMAL, 4512 access_rx_dma_data_fifo_rd_cor_err_cnt), 4513 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0, 4514 CNTR_NORMAL, 4515 access_rx_dma_data_fifo_rd_unc_err_cnt), 4516 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0, 4517 CNTR_NORMAL, 4518 access_rx_dma_hdr_fifo_rd_cor_err_cnt), 4519 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0, 4520 CNTR_NORMAL, 4521 access_rx_dma_hdr_fifo_rd_unc_err_cnt), 4522 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0, 4523 CNTR_NORMAL, 4524 access_rx_rbuf_desc_part2_cor_err_cnt), 4525 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0, 4526 CNTR_NORMAL, 4527 access_rx_rbuf_desc_part2_unc_err_cnt), 4528 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0, 4529 CNTR_NORMAL, 4530 access_rx_rbuf_desc_part1_cor_err_cnt), 4531 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0, 4532 CNTR_NORMAL, 4533 access_rx_rbuf_desc_part1_unc_err_cnt), 4534 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0, 4535 CNTR_NORMAL, 4536 access_rx_hq_intr_fsm_err_cnt), 4537 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0, 4538 CNTR_NORMAL, 4539 access_rx_hq_intr_csr_parity_err_cnt), 4540 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0, 4541 CNTR_NORMAL, 4542 access_rx_lookup_csr_parity_err_cnt), 4543 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0, 4544 CNTR_NORMAL, 4545 access_rx_lookup_rcv_array_cor_err_cnt), 4546 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0, 4547 CNTR_NORMAL, 4548 access_rx_lookup_rcv_array_unc_err_cnt), 4549 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0, 4550 0, CNTR_NORMAL, 4551 access_rx_lookup_des_part2_parity_err_cnt), 4552 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0, 4553 0, CNTR_NORMAL, 4554 access_rx_lookup_des_part1_unc_cor_err_cnt), 4555 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0, 4556 CNTR_NORMAL, 4557 access_rx_lookup_des_part1_unc_err_cnt), 4558 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0, 4559 CNTR_NORMAL, 4560 access_rx_rbuf_next_free_buf_cor_err_cnt), 4561 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0, 4562 CNTR_NORMAL, 4563 access_rx_rbuf_next_free_buf_unc_err_cnt), 4564 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM( 4565 "RxRbufFlInitWrAddrParityErr", 0, 0, 4566 CNTR_NORMAL, 4567 access_rbuf_fl_init_wr_addr_parity_err_cnt), 4568 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0, 4569 0, CNTR_NORMAL, 4570 access_rx_rbuf_fl_initdone_parity_err_cnt), 4571 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0, 4572 0, CNTR_NORMAL, 4573 access_rx_rbuf_fl_write_addr_parity_err_cnt), 4574 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0, 4575 CNTR_NORMAL, 4576 access_rx_rbuf_fl_rd_addr_parity_err_cnt), 4577 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0, 4578 CNTR_NORMAL, 4579 access_rx_rbuf_empty_err_cnt), 4580 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0, 4581 CNTR_NORMAL, 4582 access_rx_rbuf_full_err_cnt), 4583 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0, 4584 CNTR_NORMAL, 4585 access_rbuf_bad_lookup_err_cnt), 4586 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0, 4587 CNTR_NORMAL, 4588 access_rbuf_ctx_id_parity_err_cnt), 4589 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0, 4590 CNTR_NORMAL, 4591 access_rbuf_csr_qeopdw_parity_err_cnt), 4592 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM( 4593 "RxRbufCsrQNumOfPktParityErr", 0, 0, 4594 CNTR_NORMAL, 4595 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt), 4596 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM( 4597 "RxRbufCsrQTlPtrParityErr", 0, 0, 4598 CNTR_NORMAL, 4599 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt), 4600 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0, 4601 0, CNTR_NORMAL, 4602 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt), 4603 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0, 4604 0, CNTR_NORMAL, 4605 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt), 4606 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr", 4607 0, 0, CNTR_NORMAL, 4608 access_rx_rbuf_csr_q_next_buf_parity_err_cnt), 4609 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0, 4610 0, CNTR_NORMAL, 4611 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt), 4612 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM( 4613 "RxRbufCsrQHeadBufNumParityErr", 0, 0, 4614 CNTR_NORMAL, 4615 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt), 4616 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0, 4617 0, CNTR_NORMAL, 4618 access_rx_rbuf_block_list_read_cor_err_cnt), 4619 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0, 4620 0, CNTR_NORMAL, 4621 access_rx_rbuf_block_list_read_unc_err_cnt), 4622 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0, 4623 CNTR_NORMAL, 4624 access_rx_rbuf_lookup_des_cor_err_cnt), 4625 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0, 4626 CNTR_NORMAL, 4627 access_rx_rbuf_lookup_des_unc_err_cnt), 4628 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM( 4629 "RxRbufLookupDesRegUncCorErr", 0, 0, 4630 CNTR_NORMAL, 4631 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt), 4632 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0, 4633 CNTR_NORMAL, 4634 access_rx_rbuf_lookup_des_reg_unc_err_cnt), 4635 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0, 4636 CNTR_NORMAL, 4637 access_rx_rbuf_free_list_cor_err_cnt), 4638 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0, 4639 CNTR_NORMAL, 4640 access_rx_rbuf_free_list_unc_err_cnt), 4641 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0, 4642 CNTR_NORMAL, 4643 access_rx_rcv_fsm_encoding_err_cnt), 4644 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0, 4645 CNTR_NORMAL, 4646 access_rx_dma_flag_cor_err_cnt), 4647 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0, 4648 CNTR_NORMAL, 4649 access_rx_dma_flag_unc_err_cnt), 4650 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0, 4651 CNTR_NORMAL, 4652 access_rx_dc_sop_eop_parity_err_cnt), 4653 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0, 4654 CNTR_NORMAL, 4655 access_rx_rcv_csr_parity_err_cnt), 4656 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0, 4657 CNTR_NORMAL, 4658 access_rx_rcv_qp_map_table_cor_err_cnt), 4659 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0, 4660 CNTR_NORMAL, 4661 access_rx_rcv_qp_map_table_unc_err_cnt), 4662 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0, 4663 CNTR_NORMAL, 4664 access_rx_rcv_data_cor_err_cnt), 4665 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0, 4666 CNTR_NORMAL, 4667 access_rx_rcv_data_unc_err_cnt), 4668 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0, 4669 CNTR_NORMAL, 4670 access_rx_rcv_hdr_cor_err_cnt), 4671 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0, 4672 CNTR_NORMAL, 4673 access_rx_rcv_hdr_unc_err_cnt), 4674 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0, 4675 CNTR_NORMAL, 4676 access_rx_dc_intf_parity_err_cnt), 4677 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0, 4678 CNTR_NORMAL, 4679 access_rx_dma_csr_cor_err_cnt), 4680 /* SendPioErrStatus */ 4681 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0, 4682 CNTR_NORMAL, 4683 access_pio_pec_sop_head_parity_err_cnt), 4684 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0, 4685 CNTR_NORMAL, 4686 access_pio_pcc_sop_head_parity_err_cnt), 4687 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr", 4688 0, 0, CNTR_NORMAL, 4689 access_pio_last_returned_cnt_parity_err_cnt), 4690 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0, 4691 0, CNTR_NORMAL, 4692 access_pio_current_free_cnt_parity_err_cnt), 4693 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0, 4694 CNTR_NORMAL, 4695 access_pio_reserved_31_err_cnt), 4696 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0, 4697 CNTR_NORMAL, 4698 access_pio_reserved_30_err_cnt), 4699 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0, 4700 CNTR_NORMAL, 4701 access_pio_ppmc_sop_len_err_cnt), 4702 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0, 4703 CNTR_NORMAL, 4704 access_pio_ppmc_bqc_mem_parity_err_cnt), 4705 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0, 4706 CNTR_NORMAL, 4707 access_pio_vl_fifo_parity_err_cnt), 4708 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0, 4709 CNTR_NORMAL, 4710 access_pio_vlf_sop_parity_err_cnt), 4711 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0, 4712 CNTR_NORMAL, 4713 access_pio_vlf_v1_len_parity_err_cnt), 4714 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0, 4715 CNTR_NORMAL, 4716 access_pio_block_qw_count_parity_err_cnt), 4717 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0, 4718 CNTR_NORMAL, 4719 access_pio_write_qw_valid_parity_err_cnt), 4720 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0, 4721 CNTR_NORMAL, 4722 access_pio_state_machine_err_cnt), 4723 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0, 4724 CNTR_NORMAL, 4725 access_pio_write_data_parity_err_cnt), 4726 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0, 4727 CNTR_NORMAL, 4728 access_pio_host_addr_mem_cor_err_cnt), 4729 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0, 4730 CNTR_NORMAL, 4731 access_pio_host_addr_mem_unc_err_cnt), 4732 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0, 4733 CNTR_NORMAL, 4734 access_pio_pkt_evict_sm_or_arb_sm_err_cnt), 4735 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0, 4736 CNTR_NORMAL, 4737 access_pio_init_sm_in_err_cnt), 4738 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0, 4739 CNTR_NORMAL, 4740 access_pio_ppmc_pbl_fifo_err_cnt), 4741 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0, 4742 0, CNTR_NORMAL, 4743 access_pio_credit_ret_fifo_parity_err_cnt), 4744 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0, 4745 CNTR_NORMAL, 4746 access_pio_v1_len_mem_bank1_cor_err_cnt), 4747 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0, 4748 CNTR_NORMAL, 4749 access_pio_v1_len_mem_bank0_cor_err_cnt), 4750 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0, 4751 CNTR_NORMAL, 4752 access_pio_v1_len_mem_bank1_unc_err_cnt), 4753 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0, 4754 CNTR_NORMAL, 4755 access_pio_v1_len_mem_bank0_unc_err_cnt), 4756 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0, 4757 CNTR_NORMAL, 4758 access_pio_sm_pkt_reset_parity_err_cnt), 4759 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0, 4760 CNTR_NORMAL, 4761 access_pio_pkt_evict_fifo_parity_err_cnt), 4762 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM( 4763 "PioSbrdctrlCrrelFifoParityErr", 0, 0, 4764 CNTR_NORMAL, 4765 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt), 4766 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0, 4767 CNTR_NORMAL, 4768 access_pio_sbrdctl_crrel_parity_err_cnt), 4769 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0, 4770 CNTR_NORMAL, 4771 access_pio_pec_fifo_parity_err_cnt), 4772 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0, 4773 CNTR_NORMAL, 4774 access_pio_pcc_fifo_parity_err_cnt), 4775 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0, 4776 CNTR_NORMAL, 4777 access_pio_sb_mem_fifo1_err_cnt), 4778 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0, 4779 CNTR_NORMAL, 4780 access_pio_sb_mem_fifo0_err_cnt), 4781 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0, 4782 CNTR_NORMAL, 4783 access_pio_csr_parity_err_cnt), 4784 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0, 4785 CNTR_NORMAL, 4786 access_pio_write_addr_parity_err_cnt), 4787 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0, 4788 CNTR_NORMAL, 4789 access_pio_write_bad_ctxt_err_cnt), 4790 /* SendDmaErrStatus */ 4791 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0, 4792 0, CNTR_NORMAL, 4793 access_sdma_pcie_req_tracking_cor_err_cnt), 4794 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0, 4795 0, CNTR_NORMAL, 4796 access_sdma_pcie_req_tracking_unc_err_cnt), 4797 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0, 4798 CNTR_NORMAL, 4799 access_sdma_csr_parity_err_cnt), 4800 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0, 4801 CNTR_NORMAL, 4802 access_sdma_rpy_tag_err_cnt), 4803 /* SendEgressErrStatus */ 4804 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0, 4805 CNTR_NORMAL, 4806 access_tx_read_pio_memory_csr_unc_err_cnt), 4807 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0, 4808 0, CNTR_NORMAL, 4809 access_tx_read_sdma_memory_csr_err_cnt), 4810 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0, 4811 CNTR_NORMAL, 4812 access_tx_egress_fifo_cor_err_cnt), 4813 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0, 4814 CNTR_NORMAL, 4815 access_tx_read_pio_memory_cor_err_cnt), 4816 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0, 4817 CNTR_NORMAL, 4818 access_tx_read_sdma_memory_cor_err_cnt), 4819 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0, 4820 CNTR_NORMAL, 4821 access_tx_sb_hdr_cor_err_cnt), 4822 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0, 4823 CNTR_NORMAL, 4824 access_tx_credit_overrun_err_cnt), 4825 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0, 4826 CNTR_NORMAL, 4827 access_tx_launch_fifo8_cor_err_cnt), 4828 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0, 4829 CNTR_NORMAL, 4830 access_tx_launch_fifo7_cor_err_cnt), 4831 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0, 4832 CNTR_NORMAL, 4833 access_tx_launch_fifo6_cor_err_cnt), 4834 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0, 4835 CNTR_NORMAL, 4836 access_tx_launch_fifo5_cor_err_cnt), 4837 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0, 4838 CNTR_NORMAL, 4839 access_tx_launch_fifo4_cor_err_cnt), 4840 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0, 4841 CNTR_NORMAL, 4842 access_tx_launch_fifo3_cor_err_cnt), 4843 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0, 4844 CNTR_NORMAL, 4845 access_tx_launch_fifo2_cor_err_cnt), 4846 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0, 4847 CNTR_NORMAL, 4848 access_tx_launch_fifo1_cor_err_cnt), 4849 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0, 4850 CNTR_NORMAL, 4851 access_tx_launch_fifo0_cor_err_cnt), 4852 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0, 4853 CNTR_NORMAL, 4854 access_tx_credit_return_vl_err_cnt), 4855 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0, 4856 CNTR_NORMAL, 4857 access_tx_hcrc_insertion_err_cnt), 4858 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0, 4859 CNTR_NORMAL, 4860 access_tx_egress_fifo_unc_err_cnt), 4861 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0, 4862 CNTR_NORMAL, 4863 access_tx_read_pio_memory_unc_err_cnt), 4864 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0, 4865 CNTR_NORMAL, 4866 access_tx_read_sdma_memory_unc_err_cnt), 4867 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0, 4868 CNTR_NORMAL, 4869 access_tx_sb_hdr_unc_err_cnt), 4870 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0, 4871 CNTR_NORMAL, 4872 access_tx_credit_return_partiy_err_cnt), 4873 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr", 4874 0, 0, CNTR_NORMAL, 4875 access_tx_launch_fifo8_unc_or_parity_err_cnt), 4876 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr", 4877 0, 0, CNTR_NORMAL, 4878 access_tx_launch_fifo7_unc_or_parity_err_cnt), 4879 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr", 4880 0, 0, CNTR_NORMAL, 4881 access_tx_launch_fifo6_unc_or_parity_err_cnt), 4882 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr", 4883 0, 0, CNTR_NORMAL, 4884 access_tx_launch_fifo5_unc_or_parity_err_cnt), 4885 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr", 4886 0, 0, CNTR_NORMAL, 4887 access_tx_launch_fifo4_unc_or_parity_err_cnt), 4888 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr", 4889 0, 0, CNTR_NORMAL, 4890 access_tx_launch_fifo3_unc_or_parity_err_cnt), 4891 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr", 4892 0, 0, CNTR_NORMAL, 4893 access_tx_launch_fifo2_unc_or_parity_err_cnt), 4894 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr", 4895 0, 0, CNTR_NORMAL, 4896 access_tx_launch_fifo1_unc_or_parity_err_cnt), 4897 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr", 4898 0, 0, CNTR_NORMAL, 4899 access_tx_launch_fifo0_unc_or_parity_err_cnt), 4900 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr", 4901 0, 0, CNTR_NORMAL, 4902 access_tx_sdma15_disallowed_packet_err_cnt), 4903 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr", 4904 0, 0, CNTR_NORMAL, 4905 access_tx_sdma14_disallowed_packet_err_cnt), 4906 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr", 4907 0, 0, CNTR_NORMAL, 4908 access_tx_sdma13_disallowed_packet_err_cnt), 4909 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr", 4910 0, 0, CNTR_NORMAL, 4911 access_tx_sdma12_disallowed_packet_err_cnt), 4912 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr", 4913 0, 0, CNTR_NORMAL, 4914 access_tx_sdma11_disallowed_packet_err_cnt), 4915 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr", 4916 0, 0, CNTR_NORMAL, 4917 access_tx_sdma10_disallowed_packet_err_cnt), 4918 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr", 4919 0, 0, CNTR_NORMAL, 4920 access_tx_sdma9_disallowed_packet_err_cnt), 4921 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr", 4922 0, 0, CNTR_NORMAL, 4923 access_tx_sdma8_disallowed_packet_err_cnt), 4924 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr", 4925 0, 0, CNTR_NORMAL, 4926 access_tx_sdma7_disallowed_packet_err_cnt), 4927 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr", 4928 0, 0, CNTR_NORMAL, 4929 access_tx_sdma6_disallowed_packet_err_cnt), 4930 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr", 4931 0, 0, CNTR_NORMAL, 4932 access_tx_sdma5_disallowed_packet_err_cnt), 4933 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr", 4934 0, 0, CNTR_NORMAL, 4935 access_tx_sdma4_disallowed_packet_err_cnt), 4936 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr", 4937 0, 0, CNTR_NORMAL, 4938 access_tx_sdma3_disallowed_packet_err_cnt), 4939 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr", 4940 0, 0, CNTR_NORMAL, 4941 access_tx_sdma2_disallowed_packet_err_cnt), 4942 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr", 4943 0, 0, CNTR_NORMAL, 4944 access_tx_sdma1_disallowed_packet_err_cnt), 4945 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr", 4946 0, 0, CNTR_NORMAL, 4947 access_tx_sdma0_disallowed_packet_err_cnt), 4948 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0, 4949 CNTR_NORMAL, 4950 access_tx_config_parity_err_cnt), 4951 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0, 4952 CNTR_NORMAL, 4953 access_tx_sbrd_ctl_csr_parity_err_cnt), 4954 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0, 4955 CNTR_NORMAL, 4956 access_tx_launch_csr_parity_err_cnt), 4957 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0, 4958 CNTR_NORMAL, 4959 access_tx_illegal_vl_err_cnt), 4960 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM( 4961 "TxSbrdCtlStateMachineParityErr", 0, 0, 4962 CNTR_NORMAL, 4963 access_tx_sbrd_ctl_state_machine_parity_err_cnt), 4964 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0, 4965 CNTR_NORMAL, 4966 access_egress_reserved_10_err_cnt), 4967 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0, 4968 CNTR_NORMAL, 4969 access_egress_reserved_9_err_cnt), 4970 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr", 4971 0, 0, CNTR_NORMAL, 4972 access_tx_sdma_launch_intf_parity_err_cnt), 4973 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0, 4974 CNTR_NORMAL, 4975 access_tx_pio_launch_intf_parity_err_cnt), 4976 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0, 4977 CNTR_NORMAL, 4978 access_egress_reserved_6_err_cnt), 4979 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0, 4980 CNTR_NORMAL, 4981 access_tx_incorrect_link_state_err_cnt), 4982 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0, 4983 CNTR_NORMAL, 4984 access_tx_linkdown_err_cnt), 4985 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM( 4986 "EgressFifoUnderrunOrParityErr", 0, 0, 4987 CNTR_NORMAL, 4988 access_tx_egress_fifi_underrun_or_parity_err_cnt), 4989 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0, 4990 CNTR_NORMAL, 4991 access_egress_reserved_2_err_cnt), 4992 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0, 4993 CNTR_NORMAL, 4994 access_tx_pkt_integrity_mem_unc_err_cnt), 4995 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0, 4996 CNTR_NORMAL, 4997 access_tx_pkt_integrity_mem_cor_err_cnt), 4998 /* SendErrStatus */ 4999 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0, 5000 CNTR_NORMAL, 5001 access_send_csr_write_bad_addr_err_cnt), 5002 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0, 5003 CNTR_NORMAL, 5004 access_send_csr_read_bad_addr_err_cnt), 5005 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0, 5006 CNTR_NORMAL, 5007 access_send_csr_parity_cnt), 5008 /* SendCtxtErrStatus */ 5009 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0, 5010 CNTR_NORMAL, 5011 access_pio_write_out_of_bounds_err_cnt), 5012 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0, 5013 CNTR_NORMAL, 5014 access_pio_write_overflow_err_cnt), 5015 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr", 5016 0, 0, CNTR_NORMAL, 5017 access_pio_write_crosses_boundary_err_cnt), 5018 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0, 5019 CNTR_NORMAL, 5020 access_pio_disallowed_packet_err_cnt), 5021 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0, 5022 CNTR_NORMAL, 5023 access_pio_inconsistent_sop_err_cnt), 5024 /* SendDmaEngErrStatus */ 5025 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr", 5026 0, 0, CNTR_NORMAL, 5027 access_sdma_header_request_fifo_cor_err_cnt), 5028 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0, 5029 CNTR_NORMAL, 5030 access_sdma_header_storage_cor_err_cnt), 5031 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0, 5032 CNTR_NORMAL, 5033 access_sdma_packet_tracking_cor_err_cnt), 5034 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0, 5035 CNTR_NORMAL, 5036 access_sdma_assembly_cor_err_cnt), 5037 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0, 5038 CNTR_NORMAL, 5039 access_sdma_desc_table_cor_err_cnt), 5040 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr", 5041 0, 0, CNTR_NORMAL, 5042 access_sdma_header_request_fifo_unc_err_cnt), 5043 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0, 5044 CNTR_NORMAL, 5045 access_sdma_header_storage_unc_err_cnt), 5046 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0, 5047 CNTR_NORMAL, 5048 access_sdma_packet_tracking_unc_err_cnt), 5049 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0, 5050 CNTR_NORMAL, 5051 access_sdma_assembly_unc_err_cnt), 5052 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0, 5053 CNTR_NORMAL, 5054 access_sdma_desc_table_unc_err_cnt), 5055 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0, 5056 CNTR_NORMAL, 5057 access_sdma_timeout_err_cnt), 5058 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0, 5059 CNTR_NORMAL, 5060 access_sdma_header_length_err_cnt), 5061 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0, 5062 CNTR_NORMAL, 5063 access_sdma_header_address_err_cnt), 5064 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0, 5065 CNTR_NORMAL, 5066 access_sdma_header_select_err_cnt), 5067 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0, 5068 CNTR_NORMAL, 5069 access_sdma_reserved_9_err_cnt), 5070 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0, 5071 CNTR_NORMAL, 5072 access_sdma_packet_desc_overflow_err_cnt), 5073 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0, 5074 CNTR_NORMAL, 5075 access_sdma_length_mismatch_err_cnt), 5076 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0, 5077 CNTR_NORMAL, 5078 access_sdma_halt_err_cnt), 5079 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0, 5080 CNTR_NORMAL, 5081 access_sdma_mem_read_err_cnt), 5082 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0, 5083 CNTR_NORMAL, 5084 access_sdma_first_desc_err_cnt), 5085 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0, 5086 CNTR_NORMAL, 5087 access_sdma_tail_out_of_bounds_err_cnt), 5088 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0, 5089 CNTR_NORMAL, 5090 access_sdma_too_long_err_cnt), 5091 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0, 5092 CNTR_NORMAL, 5093 access_sdma_gen_mismatch_err_cnt), 5094 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0, 5095 CNTR_NORMAL, 5096 access_sdma_wrong_dw_err_cnt), 5097 }; 5098 5099 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = { 5100 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT, 5101 CNTR_NORMAL), 5102 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT, 5103 CNTR_NORMAL), 5104 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT, 5105 CNTR_NORMAL), 5106 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT, 5107 CNTR_NORMAL), 5108 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT, 5109 CNTR_NORMAL), 5110 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT, 5111 CNTR_NORMAL), 5112 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT, 5113 CNTR_NORMAL), 5114 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL), 5115 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL), 5116 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH), 5117 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT, 5118 CNTR_SYNTH | CNTR_VL), 5119 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT, 5120 CNTR_SYNTH | CNTR_VL), 5121 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT, 5122 CNTR_SYNTH | CNTR_VL), 5123 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL), 5124 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL), 5125 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5126 access_sw_link_dn_cnt), 5127 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5128 access_sw_link_up_cnt), 5129 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL, 5130 access_sw_unknown_frame_cnt), 5131 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5132 access_sw_xmit_discards), 5133 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0, 5134 CNTR_SYNTH | CNTR_32BIT | CNTR_VL, 5135 access_sw_xmit_discards), 5136 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH, 5137 access_xmit_constraint_errs), 5138 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH, 5139 access_rcv_constraint_errs), 5140 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts), 5141 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends), 5142 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks), 5143 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks), 5144 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts), 5145 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops), 5146 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait), 5147 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak), 5148 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq), 5149 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq), 5150 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned), 5151 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks), 5152 [C_SW_IBP_RC_CRWAITS] = SW_IBP_CNTR(RcCrWait, rc_crwaits), 5153 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL, 5154 access_sw_cpu_rc_acks), 5155 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL, 5156 access_sw_cpu_rc_qacks), 5157 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL, 5158 access_sw_cpu_rc_delayed_comp), 5159 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1), 5160 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3), 5161 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5), 5162 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7), 5163 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9), 5164 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11), 5165 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13), 5166 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15), 5167 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17), 5168 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19), 5169 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21), 5170 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23), 5171 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25), 5172 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27), 5173 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29), 5174 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31), 5175 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33), 5176 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35), 5177 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37), 5178 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39), 5179 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41), 5180 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43), 5181 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45), 5182 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47), 5183 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49), 5184 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51), 5185 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53), 5186 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55), 5187 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57), 5188 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59), 5189 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61), 5190 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63), 5191 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65), 5192 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67), 5193 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69), 5194 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71), 5195 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73), 5196 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75), 5197 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77), 5198 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79), 5199 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81), 5200 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83), 5201 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85), 5202 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87), 5203 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89), 5204 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91), 5205 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93), 5206 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95), 5207 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97), 5208 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99), 5209 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101), 5210 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103), 5211 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105), 5212 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107), 5213 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109), 5214 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111), 5215 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113), 5216 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115), 5217 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117), 5218 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119), 5219 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121), 5220 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123), 5221 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125), 5222 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127), 5223 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129), 5224 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131), 5225 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133), 5226 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135), 5227 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137), 5228 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139), 5229 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141), 5230 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143), 5231 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145), 5232 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147), 5233 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149), 5234 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151), 5235 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153), 5236 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155), 5237 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157), 5238 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159), 5239 }; 5240 5241 /* ======================================================================== */ 5242 5243 /* return true if this is chip revision revision a */ 5244 int is_ax(struct hfi1_devdata *dd) 5245 { 5246 u8 chip_rev_minor = 5247 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5248 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5249 return (chip_rev_minor & 0xf0) == 0; 5250 } 5251 5252 /* return true if this is chip revision revision b */ 5253 int is_bx(struct hfi1_devdata *dd) 5254 { 5255 u8 chip_rev_minor = 5256 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5257 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5258 return (chip_rev_minor & 0xF0) == 0x10; 5259 } 5260 5261 /* return true is kernel urg disabled for rcd */ 5262 bool is_urg_masked(struct hfi1_ctxtdata *rcd) 5263 { 5264 u64 mask; 5265 u32 is = IS_RCVURGENT_START + rcd->ctxt; 5266 u8 bit = is % 64; 5267 5268 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64))); 5269 return !(mask & BIT_ULL(bit)); 5270 } 5271 5272 /* 5273 * Append string s to buffer buf. Arguments curp and len are the current 5274 * position and remaining length, respectively. 5275 * 5276 * return 0 on success, 1 on out of room 5277 */ 5278 static int append_str(char *buf, char **curp, int *lenp, const char *s) 5279 { 5280 char *p = *curp; 5281 int len = *lenp; 5282 int result = 0; /* success */ 5283 char c; 5284 5285 /* add a comma, if first in the buffer */ 5286 if (p != buf) { 5287 if (len == 0) { 5288 result = 1; /* out of room */ 5289 goto done; 5290 } 5291 *p++ = ','; 5292 len--; 5293 } 5294 5295 /* copy the string */ 5296 while ((c = *s++) != 0) { 5297 if (len == 0) { 5298 result = 1; /* out of room */ 5299 goto done; 5300 } 5301 *p++ = c; 5302 len--; 5303 } 5304 5305 done: 5306 /* write return values */ 5307 *curp = p; 5308 *lenp = len; 5309 5310 return result; 5311 } 5312 5313 /* 5314 * Using the given flag table, print a comma separated string into 5315 * the buffer. End in '*' if the buffer is too short. 5316 */ 5317 static char *flag_string(char *buf, int buf_len, u64 flags, 5318 struct flag_table *table, int table_size) 5319 { 5320 char extra[32]; 5321 char *p = buf; 5322 int len = buf_len; 5323 int no_room = 0; 5324 int i; 5325 5326 /* make sure there is at least 2 so we can form "*" */ 5327 if (len < 2) 5328 return ""; 5329 5330 len--; /* leave room for a nul */ 5331 for (i = 0; i < table_size; i++) { 5332 if (flags & table[i].flag) { 5333 no_room = append_str(buf, &p, &len, table[i].str); 5334 if (no_room) 5335 break; 5336 flags &= ~table[i].flag; 5337 } 5338 } 5339 5340 /* any undocumented bits left? */ 5341 if (!no_room && flags) { 5342 snprintf(extra, sizeof(extra), "bits 0x%llx", flags); 5343 no_room = append_str(buf, &p, &len, extra); 5344 } 5345 5346 /* add * if ran out of room */ 5347 if (no_room) { 5348 /* may need to back up to add space for a '*' */ 5349 if (len == 0) 5350 --p; 5351 *p++ = '*'; 5352 } 5353 5354 /* add final nul - space already allocated above */ 5355 *p = 0; 5356 return buf; 5357 } 5358 5359 /* first 8 CCE error interrupt source names */ 5360 static const char * const cce_misc_names[] = { 5361 "CceErrInt", /* 0 */ 5362 "RxeErrInt", /* 1 */ 5363 "MiscErrInt", /* 2 */ 5364 "Reserved3", /* 3 */ 5365 "PioErrInt", /* 4 */ 5366 "SDmaErrInt", /* 5 */ 5367 "EgressErrInt", /* 6 */ 5368 "TxeErrInt" /* 7 */ 5369 }; 5370 5371 /* 5372 * Return the miscellaneous error interrupt name. 5373 */ 5374 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source) 5375 { 5376 if (source < ARRAY_SIZE(cce_misc_names)) 5377 strncpy(buf, cce_misc_names[source], bsize); 5378 else 5379 snprintf(buf, bsize, "Reserved%u", 5380 source + IS_GENERAL_ERR_START); 5381 5382 return buf; 5383 } 5384 5385 /* 5386 * Return the SDMA engine error interrupt name. 5387 */ 5388 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source) 5389 { 5390 snprintf(buf, bsize, "SDmaEngErrInt%u", source); 5391 return buf; 5392 } 5393 5394 /* 5395 * Return the send context error interrupt name. 5396 */ 5397 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source) 5398 { 5399 snprintf(buf, bsize, "SendCtxtErrInt%u", source); 5400 return buf; 5401 } 5402 5403 static const char * const various_names[] = { 5404 "PbcInt", 5405 "GpioAssertInt", 5406 "Qsfp1Int", 5407 "Qsfp2Int", 5408 "TCritInt" 5409 }; 5410 5411 /* 5412 * Return the various interrupt name. 5413 */ 5414 static char *is_various_name(char *buf, size_t bsize, unsigned int source) 5415 { 5416 if (source < ARRAY_SIZE(various_names)) 5417 strncpy(buf, various_names[source], bsize); 5418 else 5419 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START); 5420 return buf; 5421 } 5422 5423 /* 5424 * Return the DC interrupt name. 5425 */ 5426 static char *is_dc_name(char *buf, size_t bsize, unsigned int source) 5427 { 5428 static const char * const dc_int_names[] = { 5429 "common", 5430 "lcb", 5431 "8051", 5432 "lbm" /* local block merge */ 5433 }; 5434 5435 if (source < ARRAY_SIZE(dc_int_names)) 5436 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]); 5437 else 5438 snprintf(buf, bsize, "DCInt%u", source); 5439 return buf; 5440 } 5441 5442 static const char * const sdma_int_names[] = { 5443 "SDmaInt", 5444 "SdmaIdleInt", 5445 "SdmaProgressInt", 5446 }; 5447 5448 /* 5449 * Return the SDMA engine interrupt name. 5450 */ 5451 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source) 5452 { 5453 /* what interrupt */ 5454 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 5455 /* which engine */ 5456 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 5457 5458 if (likely(what < 3)) 5459 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which); 5460 else 5461 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source); 5462 return buf; 5463 } 5464 5465 /* 5466 * Return the receive available interrupt name. 5467 */ 5468 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source) 5469 { 5470 snprintf(buf, bsize, "RcvAvailInt%u", source); 5471 return buf; 5472 } 5473 5474 /* 5475 * Return the receive urgent interrupt name. 5476 */ 5477 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source) 5478 { 5479 snprintf(buf, bsize, "RcvUrgentInt%u", source); 5480 return buf; 5481 } 5482 5483 /* 5484 * Return the send credit interrupt name. 5485 */ 5486 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source) 5487 { 5488 snprintf(buf, bsize, "SendCreditInt%u", source); 5489 return buf; 5490 } 5491 5492 /* 5493 * Return the reserved interrupt name. 5494 */ 5495 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source) 5496 { 5497 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START); 5498 return buf; 5499 } 5500 5501 static char *cce_err_status_string(char *buf, int buf_len, u64 flags) 5502 { 5503 return flag_string(buf, buf_len, flags, 5504 cce_err_status_flags, 5505 ARRAY_SIZE(cce_err_status_flags)); 5506 } 5507 5508 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags) 5509 { 5510 return flag_string(buf, buf_len, flags, 5511 rxe_err_status_flags, 5512 ARRAY_SIZE(rxe_err_status_flags)); 5513 } 5514 5515 static char *misc_err_status_string(char *buf, int buf_len, u64 flags) 5516 { 5517 return flag_string(buf, buf_len, flags, misc_err_status_flags, 5518 ARRAY_SIZE(misc_err_status_flags)); 5519 } 5520 5521 static char *pio_err_status_string(char *buf, int buf_len, u64 flags) 5522 { 5523 return flag_string(buf, buf_len, flags, 5524 pio_err_status_flags, 5525 ARRAY_SIZE(pio_err_status_flags)); 5526 } 5527 5528 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags) 5529 { 5530 return flag_string(buf, buf_len, flags, 5531 sdma_err_status_flags, 5532 ARRAY_SIZE(sdma_err_status_flags)); 5533 } 5534 5535 static char *egress_err_status_string(char *buf, int buf_len, u64 flags) 5536 { 5537 return flag_string(buf, buf_len, flags, 5538 egress_err_status_flags, 5539 ARRAY_SIZE(egress_err_status_flags)); 5540 } 5541 5542 static char *egress_err_info_string(char *buf, int buf_len, u64 flags) 5543 { 5544 return flag_string(buf, buf_len, flags, 5545 egress_err_info_flags, 5546 ARRAY_SIZE(egress_err_info_flags)); 5547 } 5548 5549 static char *send_err_status_string(char *buf, int buf_len, u64 flags) 5550 { 5551 return flag_string(buf, buf_len, flags, 5552 send_err_status_flags, 5553 ARRAY_SIZE(send_err_status_flags)); 5554 } 5555 5556 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5557 { 5558 char buf[96]; 5559 int i = 0; 5560 5561 /* 5562 * For most these errors, there is nothing that can be done except 5563 * report or record it. 5564 */ 5565 dd_dev_info(dd, "CCE Error: %s\n", 5566 cce_err_status_string(buf, sizeof(buf), reg)); 5567 5568 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) && 5569 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) { 5570 /* this error requires a manual drop into SPC freeze mode */ 5571 /* then a fix up */ 5572 start_freeze_handling(dd->pport, FREEZE_SELF); 5573 } 5574 5575 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) { 5576 if (reg & (1ull << i)) { 5577 incr_cntr64(&dd->cce_err_status_cnt[i]); 5578 /* maintain a counter over all cce_err_status errors */ 5579 incr_cntr64(&dd->sw_cce_err_status_aggregate); 5580 } 5581 } 5582 } 5583 5584 /* 5585 * Check counters for receive errors that do not have an interrupt 5586 * associated with them. 5587 */ 5588 #define RCVERR_CHECK_TIME 10 5589 static void update_rcverr_timer(struct timer_list *t) 5590 { 5591 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer); 5592 struct hfi1_pportdata *ppd = dd->pport; 5593 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL); 5594 5595 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt && 5596 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) { 5597 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__); 5598 set_link_down_reason( 5599 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0, 5600 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN); 5601 queue_work(ppd->link_wq, &ppd->link_bounce_work); 5602 } 5603 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt; 5604 5605 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5606 } 5607 5608 static int init_rcverr(struct hfi1_devdata *dd) 5609 { 5610 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0); 5611 /* Assume the hardware counter has been reset */ 5612 dd->rcv_ovfl_cnt = 0; 5613 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5614 } 5615 5616 static void free_rcverr(struct hfi1_devdata *dd) 5617 { 5618 if (dd->rcverr_timer.function) 5619 del_timer_sync(&dd->rcverr_timer); 5620 } 5621 5622 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5623 { 5624 char buf[96]; 5625 int i = 0; 5626 5627 dd_dev_info(dd, "Receive Error: %s\n", 5628 rxe_err_status_string(buf, sizeof(buf), reg)); 5629 5630 if (reg & ALL_RXE_FREEZE_ERR) { 5631 int flags = 0; 5632 5633 /* 5634 * Freeze mode recovery is disabled for the errors 5635 * in RXE_FREEZE_ABORT_MASK 5636 */ 5637 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK)) 5638 flags = FREEZE_ABORT; 5639 5640 start_freeze_handling(dd->pport, flags); 5641 } 5642 5643 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) { 5644 if (reg & (1ull << i)) 5645 incr_cntr64(&dd->rcv_err_status_cnt[i]); 5646 } 5647 } 5648 5649 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5650 { 5651 char buf[96]; 5652 int i = 0; 5653 5654 dd_dev_info(dd, "Misc Error: %s", 5655 misc_err_status_string(buf, sizeof(buf), reg)); 5656 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) { 5657 if (reg & (1ull << i)) 5658 incr_cntr64(&dd->misc_err_status_cnt[i]); 5659 } 5660 } 5661 5662 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5663 { 5664 char buf[96]; 5665 int i = 0; 5666 5667 dd_dev_info(dd, "PIO Error: %s\n", 5668 pio_err_status_string(buf, sizeof(buf), reg)); 5669 5670 if (reg & ALL_PIO_FREEZE_ERR) 5671 start_freeze_handling(dd->pport, 0); 5672 5673 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) { 5674 if (reg & (1ull << i)) 5675 incr_cntr64(&dd->send_pio_err_status_cnt[i]); 5676 } 5677 } 5678 5679 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5680 { 5681 char buf[96]; 5682 int i = 0; 5683 5684 dd_dev_info(dd, "SDMA Error: %s\n", 5685 sdma_err_status_string(buf, sizeof(buf), reg)); 5686 5687 if (reg & ALL_SDMA_FREEZE_ERR) 5688 start_freeze_handling(dd->pport, 0); 5689 5690 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) { 5691 if (reg & (1ull << i)) 5692 incr_cntr64(&dd->send_dma_err_status_cnt[i]); 5693 } 5694 } 5695 5696 static inline void __count_port_discards(struct hfi1_pportdata *ppd) 5697 { 5698 incr_cntr64(&ppd->port_xmit_discards); 5699 } 5700 5701 static void count_port_inactive(struct hfi1_devdata *dd) 5702 { 5703 __count_port_discards(dd->pport); 5704 } 5705 5706 /* 5707 * We have had a "disallowed packet" error during egress. Determine the 5708 * integrity check which failed, and update relevant error counter, etc. 5709 * 5710 * Note that the SEND_EGRESS_ERR_INFO register has only a single 5711 * bit of state per integrity check, and so we can miss the reason for an 5712 * egress error if more than one packet fails the same integrity check 5713 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO. 5714 */ 5715 static void handle_send_egress_err_info(struct hfi1_devdata *dd, 5716 int vl) 5717 { 5718 struct hfi1_pportdata *ppd = dd->pport; 5719 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ 5720 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); 5721 char buf[96]; 5722 5723 /* clear down all observed info as quickly as possible after read */ 5724 write_csr(dd, SEND_EGRESS_ERR_INFO, info); 5725 5726 dd_dev_info(dd, 5727 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n", 5728 info, egress_err_info_string(buf, sizeof(buf), info), src); 5729 5730 /* Eventually add other counters for each bit */ 5731 if (info & PORT_DISCARD_EGRESS_ERRS) { 5732 int weight, i; 5733 5734 /* 5735 * Count all applicable bits as individual errors and 5736 * attribute them to the packet that triggered this handler. 5737 * This may not be completely accurate due to limitations 5738 * on the available hardware error information. There is 5739 * a single information register and any number of error 5740 * packets may have occurred and contributed to it before 5741 * this routine is called. This means that: 5742 * a) If multiple packets with the same error occur before 5743 * this routine is called, earlier packets are missed. 5744 * There is only a single bit for each error type. 5745 * b) Errors may not be attributed to the correct VL. 5746 * The driver is attributing all bits in the info register 5747 * to the packet that triggered this call, but bits 5748 * could be an accumulation of different packets with 5749 * different VLs. 5750 * c) A single error packet may have multiple counts attached 5751 * to it. There is no way for the driver to know if 5752 * multiple bits set in the info register are due to a 5753 * single packet or multiple packets. The driver assumes 5754 * multiple packets. 5755 */ 5756 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS); 5757 for (i = 0; i < weight; i++) { 5758 __count_port_discards(ppd); 5759 if (vl >= 0 && vl < TXE_NUM_DATA_VL) 5760 incr_cntr64(&ppd->port_xmit_discards_vl[vl]); 5761 else if (vl == 15) 5762 incr_cntr64(&ppd->port_xmit_discards_vl 5763 [C_VL_15]); 5764 } 5765 } 5766 } 5767 5768 /* 5769 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5770 * register. Does it represent a 'port inactive' error? 5771 */ 5772 static inline int port_inactive_err(u64 posn) 5773 { 5774 return (posn >= SEES(TX_LINKDOWN) && 5775 posn <= SEES(TX_INCORRECT_LINK_STATE)); 5776 } 5777 5778 /* 5779 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5780 * register. Does it represent a 'disallowed packet' error? 5781 */ 5782 static inline int disallowed_pkt_err(int posn) 5783 { 5784 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) && 5785 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET)); 5786 } 5787 5788 /* 5789 * Input value is a bit position of one of the SDMA engine disallowed 5790 * packet errors. Return which engine. Use of this must be guarded by 5791 * disallowed_pkt_err(). 5792 */ 5793 static inline int disallowed_pkt_engine(int posn) 5794 { 5795 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET); 5796 } 5797 5798 /* 5799 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot 5800 * be done. 5801 */ 5802 static int engine_to_vl(struct hfi1_devdata *dd, int engine) 5803 { 5804 struct sdma_vl_map *m; 5805 int vl; 5806 5807 /* range check */ 5808 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES) 5809 return -1; 5810 5811 rcu_read_lock(); 5812 m = rcu_dereference(dd->sdma_map); 5813 vl = m->engine_to_vl[engine]; 5814 rcu_read_unlock(); 5815 5816 return vl; 5817 } 5818 5819 /* 5820 * Translate the send context (sofware index) into a VL. Return -1 if the 5821 * translation cannot be done. 5822 */ 5823 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index) 5824 { 5825 struct send_context_info *sci; 5826 struct send_context *sc; 5827 int i; 5828 5829 sci = &dd->send_contexts[sw_index]; 5830 5831 /* there is no information for user (PSM) and ack contexts */ 5832 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15)) 5833 return -1; 5834 5835 sc = sci->sc; 5836 if (!sc) 5837 return -1; 5838 if (dd->vld[15].sc == sc) 5839 return 15; 5840 for (i = 0; i < num_vls; i++) 5841 if (dd->vld[i].sc == sc) 5842 return i; 5843 5844 return -1; 5845 } 5846 5847 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5848 { 5849 u64 reg_copy = reg, handled = 0; 5850 char buf[96]; 5851 int i = 0; 5852 5853 if (reg & ALL_TXE_EGRESS_FREEZE_ERR) 5854 start_freeze_handling(dd->pport, 0); 5855 else if (is_ax(dd) && 5856 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) && 5857 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) 5858 start_freeze_handling(dd->pport, 0); 5859 5860 while (reg_copy) { 5861 int posn = fls64(reg_copy); 5862 /* fls64() returns a 1-based offset, we want it zero based */ 5863 int shift = posn - 1; 5864 u64 mask = 1ULL << shift; 5865 5866 if (port_inactive_err(shift)) { 5867 count_port_inactive(dd); 5868 handled |= mask; 5869 } else if (disallowed_pkt_err(shift)) { 5870 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift)); 5871 5872 handle_send_egress_err_info(dd, vl); 5873 handled |= mask; 5874 } 5875 reg_copy &= ~mask; 5876 } 5877 5878 reg &= ~handled; 5879 5880 if (reg) 5881 dd_dev_info(dd, "Egress Error: %s\n", 5882 egress_err_status_string(buf, sizeof(buf), reg)); 5883 5884 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) { 5885 if (reg & (1ull << i)) 5886 incr_cntr64(&dd->send_egress_err_status_cnt[i]); 5887 } 5888 } 5889 5890 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5891 { 5892 char buf[96]; 5893 int i = 0; 5894 5895 dd_dev_info(dd, "Send Error: %s\n", 5896 send_err_status_string(buf, sizeof(buf), reg)); 5897 5898 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) { 5899 if (reg & (1ull << i)) 5900 incr_cntr64(&dd->send_err_status_cnt[i]); 5901 } 5902 } 5903 5904 /* 5905 * The maximum number of times the error clear down will loop before 5906 * blocking a repeating error. This value is arbitrary. 5907 */ 5908 #define MAX_CLEAR_COUNT 20 5909 5910 /* 5911 * Clear and handle an error register. All error interrupts are funneled 5912 * through here to have a central location to correctly handle single- 5913 * or multi-shot errors. 5914 * 5915 * For non per-context registers, call this routine with a context value 5916 * of 0 so the per-context offset is zero. 5917 * 5918 * If the handler loops too many times, assume that something is wrong 5919 * and can't be fixed, so mask the error bits. 5920 */ 5921 static void interrupt_clear_down(struct hfi1_devdata *dd, 5922 u32 context, 5923 const struct err_reg_info *eri) 5924 { 5925 u64 reg; 5926 u32 count; 5927 5928 /* read in a loop until no more errors are seen */ 5929 count = 0; 5930 while (1) { 5931 reg = read_kctxt_csr(dd, context, eri->status); 5932 if (reg == 0) 5933 break; 5934 write_kctxt_csr(dd, context, eri->clear, reg); 5935 if (likely(eri->handler)) 5936 eri->handler(dd, context, reg); 5937 count++; 5938 if (count > MAX_CLEAR_COUNT) { 5939 u64 mask; 5940 5941 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n", 5942 eri->desc, reg); 5943 /* 5944 * Read-modify-write so any other masked bits 5945 * remain masked. 5946 */ 5947 mask = read_kctxt_csr(dd, context, eri->mask); 5948 mask &= ~reg; 5949 write_kctxt_csr(dd, context, eri->mask, mask); 5950 break; 5951 } 5952 } 5953 } 5954 5955 /* 5956 * CCE block "misc" interrupt. Source is < 16. 5957 */ 5958 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source) 5959 { 5960 const struct err_reg_info *eri = &misc_errs[source]; 5961 5962 if (eri->handler) { 5963 interrupt_clear_down(dd, 0, eri); 5964 } else { 5965 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n", 5966 source); 5967 } 5968 } 5969 5970 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags) 5971 { 5972 return flag_string(buf, buf_len, flags, 5973 sc_err_status_flags, 5974 ARRAY_SIZE(sc_err_status_flags)); 5975 } 5976 5977 /* 5978 * Send context error interrupt. Source (hw_context) is < 160. 5979 * 5980 * All send context errors cause the send context to halt. The normal 5981 * clear-down mechanism cannot be used because we cannot clear the 5982 * error bits until several other long-running items are done first. 5983 * This is OK because with the context halted, nothing else is going 5984 * to happen on it anyway. 5985 */ 5986 static void is_sendctxt_err_int(struct hfi1_devdata *dd, 5987 unsigned int hw_context) 5988 { 5989 struct send_context_info *sci; 5990 struct send_context *sc; 5991 char flags[96]; 5992 u64 status; 5993 u32 sw_index; 5994 int i = 0; 5995 unsigned long irq_flags; 5996 5997 sw_index = dd->hw_to_sw[hw_context]; 5998 if (sw_index >= dd->num_send_contexts) { 5999 dd_dev_err(dd, 6000 "out of range sw index %u for send context %u\n", 6001 sw_index, hw_context); 6002 return; 6003 } 6004 sci = &dd->send_contexts[sw_index]; 6005 spin_lock_irqsave(&dd->sc_lock, irq_flags); 6006 sc = sci->sc; 6007 if (!sc) { 6008 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__, 6009 sw_index, hw_context); 6010 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 6011 return; 6012 } 6013 6014 /* tell the software that a halt has begun */ 6015 sc_stop(sc, SCF_HALTED); 6016 6017 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS); 6018 6019 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context, 6020 send_context_err_status_string(flags, sizeof(flags), 6021 status)); 6022 6023 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK) 6024 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index)); 6025 6026 /* 6027 * Automatically restart halted kernel contexts out of interrupt 6028 * context. User contexts must ask the driver to restart the context. 6029 */ 6030 if (sc->type != SC_USER) 6031 queue_work(dd->pport->hfi1_wq, &sc->halt_work); 6032 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 6033 6034 /* 6035 * Update the counters for the corresponding status bits. 6036 * Note that these particular counters are aggregated over all 6037 * 160 contexts. 6038 */ 6039 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) { 6040 if (status & (1ull << i)) 6041 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]); 6042 } 6043 } 6044 6045 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 6046 unsigned int source, u64 status) 6047 { 6048 struct sdma_engine *sde; 6049 int i = 0; 6050 6051 sde = &dd->per_sdma[source]; 6052 #ifdef CONFIG_SDMA_VERBOSITY 6053 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6054 slashstrip(__FILE__), __LINE__, __func__); 6055 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n", 6056 sde->this_idx, source, (unsigned long long)status); 6057 #endif 6058 sde->err_cnt++; 6059 sdma_engine_error(sde, status); 6060 6061 /* 6062 * Update the counters for the corresponding status bits. 6063 * Note that these particular counters are aggregated over 6064 * all 16 DMA engines. 6065 */ 6066 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) { 6067 if (status & (1ull << i)) 6068 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]); 6069 } 6070 } 6071 6072 /* 6073 * CCE block SDMA error interrupt. Source is < 16. 6074 */ 6075 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source) 6076 { 6077 #ifdef CONFIG_SDMA_VERBOSITY 6078 struct sdma_engine *sde = &dd->per_sdma[source]; 6079 6080 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6081 slashstrip(__FILE__), __LINE__, __func__); 6082 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx, 6083 source); 6084 sdma_dumpstate(sde); 6085 #endif 6086 interrupt_clear_down(dd, source, &sdma_eng_err); 6087 } 6088 6089 /* 6090 * CCE block "various" interrupt. Source is < 8. 6091 */ 6092 static void is_various_int(struct hfi1_devdata *dd, unsigned int source) 6093 { 6094 const struct err_reg_info *eri = &various_err[source]; 6095 6096 /* 6097 * TCritInt cannot go through interrupt_clear_down() 6098 * because it is not a second tier interrupt. The handler 6099 * should be called directly. 6100 */ 6101 if (source == TCRIT_INT_SOURCE) 6102 handle_temp_err(dd); 6103 else if (eri->handler) 6104 interrupt_clear_down(dd, 0, eri); 6105 else 6106 dd_dev_info(dd, 6107 "%s: Unimplemented/reserved interrupt %d\n", 6108 __func__, source); 6109 } 6110 6111 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg) 6112 { 6113 /* src_ctx is always zero */ 6114 struct hfi1_pportdata *ppd = dd->pport; 6115 unsigned long flags; 6116 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 6117 6118 if (reg & QSFP_HFI0_MODPRST_N) { 6119 if (!qsfp_mod_present(ppd)) { 6120 dd_dev_info(dd, "%s: QSFP module removed\n", 6121 __func__); 6122 6123 ppd->driver_link_ready = 0; 6124 /* 6125 * Cable removed, reset all our information about the 6126 * cache and cable capabilities 6127 */ 6128 6129 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6130 /* 6131 * We don't set cache_refresh_required here as we expect 6132 * an interrupt when a cable is inserted 6133 */ 6134 ppd->qsfp_info.cache_valid = 0; 6135 ppd->qsfp_info.reset_needed = 0; 6136 ppd->qsfp_info.limiting_active = 0; 6137 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6138 flags); 6139 /* Invert the ModPresent pin now to detect plug-in */ 6140 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6141 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6142 6143 if ((ppd->offline_disabled_reason > 6144 HFI1_ODR_MASK( 6145 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) || 6146 (ppd->offline_disabled_reason == 6147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))) 6148 ppd->offline_disabled_reason = 6149 HFI1_ODR_MASK( 6150 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED); 6151 6152 if (ppd->host_link_state == HLS_DN_POLL) { 6153 /* 6154 * The link is still in POLL. This means 6155 * that the normal link down processing 6156 * will not happen. We have to do it here 6157 * before turning the DC off. 6158 */ 6159 queue_work(ppd->link_wq, &ppd->link_down_work); 6160 } 6161 } else { 6162 dd_dev_info(dd, "%s: QSFP module inserted\n", 6163 __func__); 6164 6165 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6166 ppd->qsfp_info.cache_valid = 0; 6167 ppd->qsfp_info.cache_refresh_required = 1; 6168 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6169 flags); 6170 6171 /* 6172 * Stop inversion of ModPresent pin to detect 6173 * removal of the cable 6174 */ 6175 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N; 6176 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6177 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6178 6179 ppd->offline_disabled_reason = 6180 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 6181 } 6182 } 6183 6184 if (reg & QSFP_HFI0_INT_N) { 6185 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n", 6186 __func__); 6187 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6188 ppd->qsfp_info.check_interrupt_flags = 1; 6189 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags); 6190 } 6191 6192 /* Schedule the QSFP work only if there is a cable attached. */ 6193 if (qsfp_mod_present(ppd)) 6194 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work); 6195 } 6196 6197 static int request_host_lcb_access(struct hfi1_devdata *dd) 6198 { 6199 int ret; 6200 6201 ret = do_8051_command(dd, HCMD_MISC, 6202 (u64)HCMD_MISC_REQUEST_LCB_ACCESS << 6203 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6204 if (ret != HCMD_SUCCESS) { 6205 dd_dev_err(dd, "%s: command failed with error %d\n", 6206 __func__, ret); 6207 } 6208 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6209 } 6210 6211 static int request_8051_lcb_access(struct hfi1_devdata *dd) 6212 { 6213 int ret; 6214 6215 ret = do_8051_command(dd, HCMD_MISC, 6216 (u64)HCMD_MISC_GRANT_LCB_ACCESS << 6217 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6218 if (ret != HCMD_SUCCESS) { 6219 dd_dev_err(dd, "%s: command failed with error %d\n", 6220 __func__, ret); 6221 } 6222 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6223 } 6224 6225 /* 6226 * Set the LCB selector - allow host access. The DCC selector always 6227 * points to the host. 6228 */ 6229 static inline void set_host_lcb_access(struct hfi1_devdata *dd) 6230 { 6231 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6232 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK | 6233 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK); 6234 } 6235 6236 /* 6237 * Clear the LCB selector - allow 8051 access. The DCC selector always 6238 * points to the host. 6239 */ 6240 static inline void set_8051_lcb_access(struct hfi1_devdata *dd) 6241 { 6242 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6243 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK); 6244 } 6245 6246 /* 6247 * Acquire LCB access from the 8051. If the host already has access, 6248 * just increment a counter. Otherwise, inform the 8051 that the 6249 * host is taking access. 6250 * 6251 * Returns: 6252 * 0 on success 6253 * -EBUSY if the 8051 has control and cannot be disturbed 6254 * -errno if unable to acquire access from the 8051 6255 */ 6256 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6257 { 6258 struct hfi1_pportdata *ppd = dd->pport; 6259 int ret = 0; 6260 6261 /* 6262 * Use the host link state lock so the operation of this routine 6263 * { link state check, selector change, count increment } can occur 6264 * as a unit against a link state change. Otherwise there is a 6265 * race between the state change and the count increment. 6266 */ 6267 if (sleep_ok) { 6268 mutex_lock(&ppd->hls_lock); 6269 } else { 6270 while (!mutex_trylock(&ppd->hls_lock)) 6271 udelay(1); 6272 } 6273 6274 /* this access is valid only when the link is up */ 6275 if (ppd->host_link_state & HLS_DOWN) { 6276 dd_dev_info(dd, "%s: link state %s not up\n", 6277 __func__, link_state_name(ppd->host_link_state)); 6278 ret = -EBUSY; 6279 goto done; 6280 } 6281 6282 if (dd->lcb_access_count == 0) { 6283 ret = request_host_lcb_access(dd); 6284 if (ret) { 6285 dd_dev_err(dd, 6286 "%s: unable to acquire LCB access, err %d\n", 6287 __func__, ret); 6288 goto done; 6289 } 6290 set_host_lcb_access(dd); 6291 } 6292 dd->lcb_access_count++; 6293 done: 6294 mutex_unlock(&ppd->hls_lock); 6295 return ret; 6296 } 6297 6298 /* 6299 * Release LCB access by decrementing the use count. If the count is moving 6300 * from 1 to 0, inform 8051 that it has control back. 6301 * 6302 * Returns: 6303 * 0 on success 6304 * -errno if unable to release access to the 8051 6305 */ 6306 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6307 { 6308 int ret = 0; 6309 6310 /* 6311 * Use the host link state lock because the acquire needed it. 6312 * Here, we only need to keep { selector change, count decrement } 6313 * as a unit. 6314 */ 6315 if (sleep_ok) { 6316 mutex_lock(&dd->pport->hls_lock); 6317 } else { 6318 while (!mutex_trylock(&dd->pport->hls_lock)) 6319 udelay(1); 6320 } 6321 6322 if (dd->lcb_access_count == 0) { 6323 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n", 6324 __func__); 6325 goto done; 6326 } 6327 6328 if (dd->lcb_access_count == 1) { 6329 set_8051_lcb_access(dd); 6330 ret = request_8051_lcb_access(dd); 6331 if (ret) { 6332 dd_dev_err(dd, 6333 "%s: unable to release LCB access, err %d\n", 6334 __func__, ret); 6335 /* restore host access if the grant didn't work */ 6336 set_host_lcb_access(dd); 6337 goto done; 6338 } 6339 } 6340 dd->lcb_access_count--; 6341 done: 6342 mutex_unlock(&dd->pport->hls_lock); 6343 return ret; 6344 } 6345 6346 /* 6347 * Initialize LCB access variables and state. Called during driver load, 6348 * after most of the initialization is finished. 6349 * 6350 * The DC default is LCB access on for the host. The driver defaults to 6351 * leaving access to the 8051. Assign access now - this constrains the call 6352 * to this routine to be after all LCB set-up is done. In particular, after 6353 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts() 6354 */ 6355 static void init_lcb_access(struct hfi1_devdata *dd) 6356 { 6357 dd->lcb_access_count = 0; 6358 } 6359 6360 /* 6361 * Write a response back to a 8051 request. 6362 */ 6363 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data) 6364 { 6365 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 6366 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK | 6367 (u64)return_code << 6368 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT | 6369 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 6370 } 6371 6372 /* 6373 * Handle host requests from the 8051. 6374 */ 6375 static void handle_8051_request(struct hfi1_pportdata *ppd) 6376 { 6377 struct hfi1_devdata *dd = ppd->dd; 6378 u64 reg; 6379 u16 data = 0; 6380 u8 type; 6381 6382 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); 6383 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0) 6384 return; /* no request */ 6385 6386 /* zero out COMPLETED so the response is seen */ 6387 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); 6388 6389 /* extract request details */ 6390 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT) 6391 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK; 6392 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT) 6393 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK; 6394 6395 switch (type) { 6396 case HREQ_LOAD_CONFIG: 6397 case HREQ_SAVE_CONFIG: 6398 case HREQ_READ_CONFIG: 6399 case HREQ_SET_TX_EQ_ABS: 6400 case HREQ_SET_TX_EQ_REL: 6401 case HREQ_ENABLE: 6402 dd_dev_info(dd, "8051 request: request 0x%x not supported\n", 6403 type); 6404 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6405 break; 6406 case HREQ_LCB_RESET: 6407 /* Put the LCB, RX FPE and TX FPE into reset */ 6408 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); 6409 /* Make sure the write completed */ 6410 (void)read_csr(dd, DCC_CFG_RESET); 6411 /* Hold the reset long enough to take effect */ 6412 udelay(1); 6413 /* Take the LCB, RX FPE and TX FPE out of reset */ 6414 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6415 hreq_response(dd, HREQ_SUCCESS, 0); 6416 6417 break; 6418 case HREQ_CONFIG_DONE: 6419 hreq_response(dd, HREQ_SUCCESS, 0); 6420 break; 6421 6422 case HREQ_INTERFACE_TEST: 6423 hreq_response(dd, HREQ_SUCCESS, data); 6424 break; 6425 default: 6426 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type); 6427 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6428 break; 6429 } 6430 } 6431 6432 /* 6433 * Set up allocation unit vaulue. 6434 */ 6435 void set_up_vau(struct hfi1_devdata *dd, u8 vau) 6436 { 6437 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6438 6439 /* do not modify other values in the register */ 6440 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK; 6441 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT; 6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6443 } 6444 6445 /* 6446 * Set up initial VL15 credits of the remote. Assumes the rest of 6447 * the CM credit registers are zero from a previous global or credit reset. 6448 * Shared limit for VL15 will always be 0. 6449 */ 6450 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf) 6451 { 6452 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6453 6454 /* set initial values for total and shared credit limit */ 6455 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK | 6456 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK); 6457 6458 /* 6459 * Set total limit to be equal to VL15 credits. 6460 * Leave shared limit at 0. 6461 */ 6462 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 6463 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6464 6465 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf 6466 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); 6467 } 6468 6469 /* 6470 * Zero all credit details from the previous connection and 6471 * reset the CM manager's internal counters. 6472 */ 6473 void reset_link_credits(struct hfi1_devdata *dd) 6474 { 6475 int i; 6476 6477 /* remove all previous VL credit limits */ 6478 for (i = 0; i < TXE_NUM_DATA_VL; i++) 6479 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 6480 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 6481 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); 6482 /* reset the CM block */ 6483 pio_send_control(dd, PSC_CM_RESET); 6484 /* reset cached value */ 6485 dd->vl15buf_cached = 0; 6486 } 6487 6488 /* convert a vCU to a CU */ 6489 static u32 vcu_to_cu(u8 vcu) 6490 { 6491 return 1 << vcu; 6492 } 6493 6494 /* convert a CU to a vCU */ 6495 static u8 cu_to_vcu(u32 cu) 6496 { 6497 return ilog2(cu); 6498 } 6499 6500 /* convert a vAU to an AU */ 6501 static u32 vau_to_au(u8 vau) 6502 { 6503 return 8 * (1 << vau); 6504 } 6505 6506 static void set_linkup_defaults(struct hfi1_pportdata *ppd) 6507 { 6508 ppd->sm_trap_qp = 0x0; 6509 ppd->sa_qp = 0x1; 6510 } 6511 6512 /* 6513 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset. 6514 */ 6515 static void lcb_shutdown(struct hfi1_devdata *dd, int abort) 6516 { 6517 u64 reg; 6518 6519 /* clear lcb run: LCB_CFG_RUN.EN = 0 */ 6520 write_csr(dd, DC_LCB_CFG_RUN, 0); 6521 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */ 6522 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 6523 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT); 6524 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */ 6525 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); 6526 reg = read_csr(dd, DCC_CFG_RESET); 6527 write_csr(dd, DCC_CFG_RESET, reg | 6528 DCC_CFG_RESET_RESET_LCB | DCC_CFG_RESET_RESET_RX_FPE); 6529 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ 6530 if (!abort) { 6531 udelay(1); /* must hold for the longer of 16cclks or 20ns */ 6532 write_csr(dd, DCC_CFG_RESET, reg); 6533 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6534 } 6535 } 6536 6537 /* 6538 * This routine should be called after the link has been transitioned to 6539 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into 6540 * reset). 6541 * 6542 * The expectation is that the caller of this routine would have taken 6543 * care of properly transitioning the link into the correct state. 6544 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6545 * before calling this function. 6546 */ 6547 static void _dc_shutdown(struct hfi1_devdata *dd) 6548 { 6549 lockdep_assert_held(&dd->dc8051_lock); 6550 6551 if (dd->dc_shutdown) 6552 return; 6553 6554 dd->dc_shutdown = 1; 6555 /* Shutdown the LCB */ 6556 lcb_shutdown(dd, 1); 6557 /* 6558 * Going to OFFLINE would have causes the 8051 to put the 6559 * SerDes into reset already. Just need to shut down the 8051, 6560 * itself. 6561 */ 6562 write_csr(dd, DC_DC8051_CFG_RST, 0x1); 6563 } 6564 6565 static void dc_shutdown(struct hfi1_devdata *dd) 6566 { 6567 mutex_lock(&dd->dc8051_lock); 6568 _dc_shutdown(dd); 6569 mutex_unlock(&dd->dc8051_lock); 6570 } 6571 6572 /* 6573 * Calling this after the DC has been brought out of reset should not 6574 * do any damage. 6575 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6576 * before calling this function. 6577 */ 6578 static void _dc_start(struct hfi1_devdata *dd) 6579 { 6580 lockdep_assert_held(&dd->dc8051_lock); 6581 6582 if (!dd->dc_shutdown) 6583 return; 6584 6585 /* Take the 8051 out of reset */ 6586 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 6587 /* Wait until 8051 is ready */ 6588 if (wait_fm_ready(dd, TIMEOUT_8051_START)) 6589 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n", 6590 __func__); 6591 6592 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */ 6593 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6594 /* lcb_shutdown() with abort=1 does not restore these */ 6595 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6596 dd->dc_shutdown = 0; 6597 } 6598 6599 static void dc_start(struct hfi1_devdata *dd) 6600 { 6601 mutex_lock(&dd->dc8051_lock); 6602 _dc_start(dd); 6603 mutex_unlock(&dd->dc8051_lock); 6604 } 6605 6606 /* 6607 * These LCB adjustments are for the Aurora SerDes core in the FPGA. 6608 */ 6609 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd) 6610 { 6611 u64 rx_radr, tx_radr; 6612 u32 version; 6613 6614 if (dd->icode != ICODE_FPGA_EMULATION) 6615 return; 6616 6617 /* 6618 * These LCB defaults on emulator _s are good, nothing to do here: 6619 * LCB_CFG_TX_FIFOS_RADR 6620 * LCB_CFG_RX_FIFOS_RADR 6621 * LCB_CFG_LN_DCLK 6622 * LCB_CFG_IGNORE_LOST_RCLK 6623 */ 6624 if (is_emulator_s(dd)) 6625 return; 6626 /* else this is _p */ 6627 6628 version = emulator_rev(dd); 6629 if (!is_ax(dd)) 6630 version = 0x2d; /* all B0 use 0x2d or higher settings */ 6631 6632 if (version <= 0x12) { 6633 /* release 0x12 and below */ 6634 6635 /* 6636 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9 6637 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9 6638 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa 6639 */ 6640 rx_radr = 6641 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6642 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6643 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6644 /* 6645 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default) 6646 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6 6647 */ 6648 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6649 } else if (version <= 0x18) { 6650 /* release 0x13 up to 0x18 */ 6651 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6652 rx_radr = 6653 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6654 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6655 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6656 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6657 } else if (version == 0x19) { 6658 /* release 0x19 */ 6659 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */ 6660 rx_radr = 6661 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6662 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6663 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6664 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6665 } else if (version == 0x1a) { 6666 /* release 0x1a */ 6667 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6668 rx_radr = 6669 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6670 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6671 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6672 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6673 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); 6674 } else { 6675 /* release 0x1b and higher */ 6676 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */ 6677 rx_radr = 6678 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6679 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6680 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6681 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6682 } 6683 6684 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); 6685 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */ 6686 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 6687 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 6688 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); 6689 } 6690 6691 /* 6692 * Handle a SMA idle message 6693 * 6694 * This is a work-queue function outside of the interrupt. 6695 */ 6696 void handle_sma_message(struct work_struct *work) 6697 { 6698 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6699 sma_message_work); 6700 struct hfi1_devdata *dd = ppd->dd; 6701 u64 msg; 6702 int ret; 6703 6704 /* 6705 * msg is bytes 1-4 of the 40-bit idle message - the command code 6706 * is stripped off 6707 */ 6708 ret = read_idle_sma(dd, &msg); 6709 if (ret) 6710 return; 6711 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg); 6712 /* 6713 * React to the SMA message. Byte[1] (0 for us) is the command. 6714 */ 6715 switch (msg & 0xff) { 6716 case SMA_IDLE_ARM: 6717 /* 6718 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6719 * State Transitions 6720 * 6721 * Only expected in INIT or ARMED, discard otherwise. 6722 */ 6723 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED)) 6724 ppd->neighbor_normal = 1; 6725 break; 6726 case SMA_IDLE_ACTIVE: 6727 /* 6728 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6729 * State Transitions 6730 * 6731 * Can activate the node. Discard otherwise. 6732 */ 6733 if (ppd->host_link_state == HLS_UP_ARMED && 6734 ppd->is_active_optimize_enabled) { 6735 ppd->neighbor_normal = 1; 6736 ret = set_link_state(ppd, HLS_UP_ACTIVE); 6737 if (ret) 6738 dd_dev_err( 6739 dd, 6740 "%s: received Active SMA idle message, couldn't set link to Active\n", 6741 __func__); 6742 } 6743 break; 6744 default: 6745 dd_dev_err(dd, 6746 "%s: received unexpected SMA idle message 0x%llx\n", 6747 __func__, msg); 6748 break; 6749 } 6750 } 6751 6752 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear) 6753 { 6754 u64 rcvctrl; 6755 unsigned long flags; 6756 6757 spin_lock_irqsave(&dd->rcvctrl_lock, flags); 6758 rcvctrl = read_csr(dd, RCV_CTRL); 6759 rcvctrl |= add; 6760 rcvctrl &= ~clear; 6761 write_csr(dd, RCV_CTRL, rcvctrl); 6762 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags); 6763 } 6764 6765 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add) 6766 { 6767 adjust_rcvctrl(dd, add, 0); 6768 } 6769 6770 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear) 6771 { 6772 adjust_rcvctrl(dd, 0, clear); 6773 } 6774 6775 /* 6776 * Called from all interrupt handlers to start handling an SPC freeze. 6777 */ 6778 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags) 6779 { 6780 struct hfi1_devdata *dd = ppd->dd; 6781 struct send_context *sc; 6782 int i; 6783 int sc_flags; 6784 6785 if (flags & FREEZE_SELF) 6786 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6787 6788 /* enter frozen mode */ 6789 dd->flags |= HFI1_FROZEN; 6790 6791 /* notify all SDMA engines that they are going into a freeze */ 6792 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN)); 6793 6794 sc_flags = SCF_FROZEN | SCF_HALTED | (flags & FREEZE_LINK_DOWN ? 6795 SCF_LINK_DOWN : 0); 6796 /* do halt pre-handling on all enabled send contexts */ 6797 for (i = 0; i < dd->num_send_contexts; i++) { 6798 sc = dd->send_contexts[i].sc; 6799 if (sc && (sc->flags & SCF_ENABLED)) 6800 sc_stop(sc, sc_flags); 6801 } 6802 6803 /* Send context are frozen. Notify user space */ 6804 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT); 6805 6806 if (flags & FREEZE_ABORT) { 6807 dd_dev_err(dd, 6808 "Aborted freeze recovery. Please REBOOT system\n"); 6809 return; 6810 } 6811 /* queue non-interrupt handler */ 6812 queue_work(ppd->hfi1_wq, &ppd->freeze_work); 6813 } 6814 6815 /* 6816 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen, 6817 * depending on the "freeze" parameter. 6818 * 6819 * No need to return an error if it times out, our only option 6820 * is to proceed anyway. 6821 */ 6822 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze) 6823 { 6824 unsigned long timeout; 6825 u64 reg; 6826 6827 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT); 6828 while (1) { 6829 reg = read_csr(dd, CCE_STATUS); 6830 if (freeze) { 6831 /* waiting until all indicators are set */ 6832 if ((reg & ALL_FROZE) == ALL_FROZE) 6833 return; /* all done */ 6834 } else { 6835 /* waiting until all indicators are clear */ 6836 if ((reg & ALL_FROZE) == 0) 6837 return; /* all done */ 6838 } 6839 6840 if (time_after(jiffies, timeout)) { 6841 dd_dev_err(dd, 6842 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing", 6843 freeze ? "" : "un", reg & ALL_FROZE, 6844 freeze ? ALL_FROZE : 0ull); 6845 return; 6846 } 6847 usleep_range(80, 120); 6848 } 6849 } 6850 6851 /* 6852 * Do all freeze handling for the RXE block. 6853 */ 6854 static void rxe_freeze(struct hfi1_devdata *dd) 6855 { 6856 int i; 6857 struct hfi1_ctxtdata *rcd; 6858 6859 /* disable port */ 6860 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6861 6862 /* disable all receive contexts */ 6863 for (i = 0; i < dd->num_rcv_contexts; i++) { 6864 rcd = hfi1_rcd_get_by_index(dd, i); 6865 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd); 6866 hfi1_rcd_put(rcd); 6867 } 6868 } 6869 6870 /* 6871 * Unfreeze handling for the RXE block - kernel contexts only. 6872 * This will also enable the port. User contexts will do unfreeze 6873 * handling on a per-context basis as they call into the driver. 6874 * 6875 */ 6876 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd) 6877 { 6878 u32 rcvmask; 6879 u16 i; 6880 struct hfi1_ctxtdata *rcd; 6881 6882 /* enable all kernel contexts */ 6883 for (i = 0; i < dd->num_rcv_contexts; i++) { 6884 rcd = hfi1_rcd_get_by_index(dd, i); 6885 6886 /* Ensure all non-user contexts(including vnic) are enabled */ 6887 if (!rcd || 6888 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) { 6889 hfi1_rcd_put(rcd); 6890 continue; 6891 } 6892 rcvmask = HFI1_RCVCTRL_CTXT_ENB; 6893 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */ 6894 rcvmask |= hfi1_rcvhdrtail_kvaddr(rcd) ? 6895 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 6896 hfi1_rcvctrl(dd, rcvmask, rcd); 6897 hfi1_rcd_put(rcd); 6898 } 6899 6900 /* enable port */ 6901 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6902 } 6903 6904 /* 6905 * Non-interrupt SPC freeze handling. 6906 * 6907 * This is a work-queue function outside of the triggering interrupt. 6908 */ 6909 void handle_freeze(struct work_struct *work) 6910 { 6911 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6912 freeze_work); 6913 struct hfi1_devdata *dd = ppd->dd; 6914 6915 /* wait for freeze indicators on all affected blocks */ 6916 wait_for_freeze_status(dd, 1); 6917 6918 /* SPC is now frozen */ 6919 6920 /* do send PIO freeze steps */ 6921 pio_freeze(dd); 6922 6923 /* do send DMA freeze steps */ 6924 sdma_freeze(dd); 6925 6926 /* do send egress freeze steps - nothing to do */ 6927 6928 /* do receive freeze steps */ 6929 rxe_freeze(dd); 6930 6931 /* 6932 * Unfreeze the hardware - clear the freeze, wait for each 6933 * block's frozen bit to clear, then clear the frozen flag. 6934 */ 6935 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6936 wait_for_freeze_status(dd, 0); 6937 6938 if (is_ax(dd)) { 6939 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6940 wait_for_freeze_status(dd, 1); 6941 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6942 wait_for_freeze_status(dd, 0); 6943 } 6944 6945 /* do send PIO unfreeze steps for kernel contexts */ 6946 pio_kernel_unfreeze(dd); 6947 6948 /* do send DMA unfreeze steps */ 6949 sdma_unfreeze(dd); 6950 6951 /* do send egress unfreeze steps - nothing to do */ 6952 6953 /* do receive unfreeze steps for kernel contexts */ 6954 rxe_kernel_unfreeze(dd); 6955 6956 /* 6957 * The unfreeze procedure touches global device registers when 6958 * it disables and re-enables RXE. Mark the device unfrozen 6959 * after all that is done so other parts of the driver waiting 6960 * for the device to unfreeze don't do things out of order. 6961 * 6962 * The above implies that the meaning of HFI1_FROZEN flag is 6963 * "Device has gone into freeze mode and freeze mode handling 6964 * is still in progress." 6965 * 6966 * The flag will be removed when freeze mode processing has 6967 * completed. 6968 */ 6969 dd->flags &= ~HFI1_FROZEN; 6970 wake_up(&dd->event_queue); 6971 6972 /* no longer frozen */ 6973 } 6974 6975 /** 6976 * update_xmit_counters - update PortXmitWait/PortVlXmitWait 6977 * counters. 6978 * @ppd: info of physical Hfi port 6979 * @link_width: new link width after link up or downgrade 6980 * 6981 * Update the PortXmitWait and PortVlXmitWait counters after 6982 * a link up or downgrade event to reflect a link width change. 6983 */ 6984 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width) 6985 { 6986 int i; 6987 u16 tx_width; 6988 u16 link_speed; 6989 6990 tx_width = tx_link_width(link_width); 6991 link_speed = get_link_speed(ppd->link_speed_active); 6992 6993 /* 6994 * There are C_VL_COUNT number of PortVLXmitWait counters. 6995 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter. 6996 */ 6997 for (i = 0; i < C_VL_COUNT + 1; i++) 6998 get_xmit_wait_counters(ppd, tx_width, link_speed, i); 6999 } 7000 7001 /* 7002 * Handle a link up interrupt from the 8051. 7003 * 7004 * This is a work-queue function outside of the interrupt. 7005 */ 7006 void handle_link_up(struct work_struct *work) 7007 { 7008 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7009 link_up_work); 7010 struct hfi1_devdata *dd = ppd->dd; 7011 7012 set_link_state(ppd, HLS_UP_INIT); 7013 7014 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */ 7015 read_ltp_rtt(dd); 7016 /* 7017 * OPA specifies that certain counters are cleared on a transition 7018 * to link up, so do that. 7019 */ 7020 clear_linkup_counters(dd); 7021 /* 7022 * And (re)set link up default values. 7023 */ 7024 set_linkup_defaults(ppd); 7025 7026 /* 7027 * Set VL15 credits. Use cached value from verify cap interrupt. 7028 * In case of quick linkup or simulator, vl15 value will be set by 7029 * handle_linkup_change. VerifyCap interrupt handler will not be 7030 * called in those scenarios. 7031 */ 7032 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) 7033 set_up_vl15(dd, dd->vl15buf_cached); 7034 7035 /* enforce link speed enabled */ 7036 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) { 7037 /* oops - current speed is not enabled, bounce */ 7038 dd_dev_err(dd, 7039 "Link speed active 0x%x is outside enabled 0x%x, downing link\n", 7040 ppd->link_speed_active, ppd->link_speed_enabled); 7041 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0, 7042 OPA_LINKDOWN_REASON_SPEED_POLICY); 7043 set_link_state(ppd, HLS_DN_OFFLINE); 7044 start_link(ppd); 7045 } 7046 } 7047 7048 /* 7049 * Several pieces of LNI information were cached for SMA in ppd. 7050 * Reset these on link down 7051 */ 7052 static void reset_neighbor_info(struct hfi1_pportdata *ppd) 7053 { 7054 ppd->neighbor_guid = 0; 7055 ppd->neighbor_port_number = 0; 7056 ppd->neighbor_type = 0; 7057 ppd->neighbor_fm_security = 0; 7058 } 7059 7060 static const char * const link_down_reason_strs[] = { 7061 [OPA_LINKDOWN_REASON_NONE] = "None", 7062 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0", 7063 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length", 7064 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long", 7065 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short", 7066 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID", 7067 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID", 7068 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2", 7069 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC", 7070 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8", 7071 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail", 7072 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10", 7073 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error", 7074 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15", 7075 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker", 7076 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14", 7077 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15", 7078 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance", 7079 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance", 7080 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance", 7081 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack", 7082 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker", 7083 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt", 7084 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit", 7085 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit", 7086 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24", 7087 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25", 7088 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26", 7089 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27", 7090 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28", 7091 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29", 7092 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30", 7093 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] = 7094 "Excessive buffer overrun", 7095 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown", 7096 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot", 7097 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown", 7098 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce", 7099 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy", 7100 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy", 7101 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected", 7102 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] = 7103 "Local media not installed", 7104 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed", 7105 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config", 7106 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] = 7107 "End to end not installed", 7108 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy", 7109 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy", 7110 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy", 7111 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management", 7112 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled", 7113 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient" 7114 }; 7115 7116 /* return the neighbor link down reason string */ 7117 static const char *link_down_reason_str(u8 reason) 7118 { 7119 const char *str = NULL; 7120 7121 if (reason < ARRAY_SIZE(link_down_reason_strs)) 7122 str = link_down_reason_strs[reason]; 7123 if (!str) 7124 str = "(invalid)"; 7125 7126 return str; 7127 } 7128 7129 /* 7130 * Handle a link down interrupt from the 8051. 7131 * 7132 * This is a work-queue function outside of the interrupt. 7133 */ 7134 void handle_link_down(struct work_struct *work) 7135 { 7136 u8 lcl_reason, neigh_reason = 0; 7137 u8 link_down_reason; 7138 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7139 link_down_work); 7140 int was_up; 7141 static const char ldr_str[] = "Link down reason: "; 7142 7143 if ((ppd->host_link_state & 7144 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) && 7145 ppd->port_type == PORT_TYPE_FIXED) 7146 ppd->offline_disabled_reason = 7147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED); 7148 7149 /* Go offline first, then deal with reading/writing through 8051 */ 7150 was_up = !!(ppd->host_link_state & HLS_UP); 7151 set_link_state(ppd, HLS_DN_OFFLINE); 7152 xchg(&ppd->is_link_down_queued, 0); 7153 7154 if (was_up) { 7155 lcl_reason = 0; 7156 /* link down reason is only valid if the link was up */ 7157 read_link_down_reason(ppd->dd, &link_down_reason); 7158 switch (link_down_reason) { 7159 case LDR_LINK_TRANSFER_ACTIVE_LOW: 7160 /* the link went down, no idle message reason */ 7161 dd_dev_info(ppd->dd, "%sUnexpected link down\n", 7162 ldr_str); 7163 break; 7164 case LDR_RECEIVED_LINKDOWN_IDLE_MSG: 7165 /* 7166 * The neighbor reason is only valid if an idle message 7167 * was received for it. 7168 */ 7169 read_planned_down_reason_code(ppd->dd, &neigh_reason); 7170 dd_dev_info(ppd->dd, 7171 "%sNeighbor link down message %d, %s\n", 7172 ldr_str, neigh_reason, 7173 link_down_reason_str(neigh_reason)); 7174 break; 7175 case LDR_RECEIVED_HOST_OFFLINE_REQ: 7176 dd_dev_info(ppd->dd, 7177 "%sHost requested link to go offline\n", 7178 ldr_str); 7179 break; 7180 default: 7181 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n", 7182 ldr_str, link_down_reason); 7183 break; 7184 } 7185 7186 /* 7187 * If no reason, assume peer-initiated but missed 7188 * LinkGoingDown idle flits. 7189 */ 7190 if (neigh_reason == 0) 7191 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN; 7192 } else { 7193 /* went down while polling or going up */ 7194 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT; 7195 } 7196 7197 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0); 7198 7199 /* inform the SMA when the link transitions from up to down */ 7200 if (was_up && ppd->local_link_down_reason.sma == 0 && 7201 ppd->neigh_link_down_reason.sma == 0) { 7202 ppd->local_link_down_reason.sma = 7203 ppd->local_link_down_reason.latest; 7204 ppd->neigh_link_down_reason.sma = 7205 ppd->neigh_link_down_reason.latest; 7206 } 7207 7208 reset_neighbor_info(ppd); 7209 7210 /* disable the port */ 7211 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 7212 7213 /* 7214 * If there is no cable attached, turn the DC off. Otherwise, 7215 * start the link bring up. 7216 */ 7217 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) 7218 dc_shutdown(ppd->dd); 7219 else 7220 start_link(ppd); 7221 } 7222 7223 void handle_link_bounce(struct work_struct *work) 7224 { 7225 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7226 link_bounce_work); 7227 7228 /* 7229 * Only do something if the link is currently up. 7230 */ 7231 if (ppd->host_link_state & HLS_UP) { 7232 set_link_state(ppd, HLS_DN_OFFLINE); 7233 start_link(ppd); 7234 } else { 7235 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n", 7236 __func__, link_state_name(ppd->host_link_state)); 7237 } 7238 } 7239 7240 /* 7241 * Mask conversion: Capability exchange to Port LTP. The capability 7242 * exchange has an implicit 16b CRC that is mandatory. 7243 */ 7244 static int cap_to_port_ltp(int cap) 7245 { 7246 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */ 7247 7248 if (cap & CAP_CRC_14B) 7249 port_ltp |= PORT_LTP_CRC_MODE_14; 7250 if (cap & CAP_CRC_48B) 7251 port_ltp |= PORT_LTP_CRC_MODE_48; 7252 if (cap & CAP_CRC_12B_16B_PER_LANE) 7253 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE; 7254 7255 return port_ltp; 7256 } 7257 7258 /* 7259 * Convert an OPA Port LTP mask to capability mask 7260 */ 7261 int port_ltp_to_cap(int port_ltp) 7262 { 7263 int cap_mask = 0; 7264 7265 if (port_ltp & PORT_LTP_CRC_MODE_14) 7266 cap_mask |= CAP_CRC_14B; 7267 if (port_ltp & PORT_LTP_CRC_MODE_48) 7268 cap_mask |= CAP_CRC_48B; 7269 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE) 7270 cap_mask |= CAP_CRC_12B_16B_PER_LANE; 7271 7272 return cap_mask; 7273 } 7274 7275 /* 7276 * Convert a single DC LCB CRC mode to an OPA Port LTP mask. 7277 */ 7278 static int lcb_to_port_ltp(int lcb_crc) 7279 { 7280 int port_ltp = 0; 7281 7282 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE) 7283 port_ltp = PORT_LTP_CRC_MODE_PER_LANE; 7284 else if (lcb_crc == LCB_CRC_48B) 7285 port_ltp = PORT_LTP_CRC_MODE_48; 7286 else if (lcb_crc == LCB_CRC_14B) 7287 port_ltp = PORT_LTP_CRC_MODE_14; 7288 else 7289 port_ltp = PORT_LTP_CRC_MODE_16; 7290 7291 return port_ltp; 7292 } 7293 7294 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd) 7295 { 7296 if (ppd->pkeys[2] != 0) { 7297 ppd->pkeys[2] = 0; 7298 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0); 7299 hfi1_event_pkey_change(ppd->dd, ppd->port); 7300 } 7301 } 7302 7303 /* 7304 * Convert the given link width to the OPA link width bitmask. 7305 */ 7306 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width) 7307 { 7308 switch (width) { 7309 case 0: 7310 /* 7311 * Simulator and quick linkup do not set the width. 7312 * Just set it to 4x without complaint. 7313 */ 7314 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup) 7315 return OPA_LINK_WIDTH_4X; 7316 return 0; /* no lanes up */ 7317 case 1: return OPA_LINK_WIDTH_1X; 7318 case 2: return OPA_LINK_WIDTH_2X; 7319 case 3: return OPA_LINK_WIDTH_3X; 7320 case 4: return OPA_LINK_WIDTH_4X; 7321 default: 7322 dd_dev_info(dd, "%s: invalid width %d, using 4\n", 7323 __func__, width); 7324 return OPA_LINK_WIDTH_4X; 7325 } 7326 } 7327 7328 /* 7329 * Do a population count on the bottom nibble. 7330 */ 7331 static const u8 bit_counts[16] = { 7332 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 7333 }; 7334 7335 static inline u8 nibble_to_count(u8 nibble) 7336 { 7337 return bit_counts[nibble & 0xf]; 7338 } 7339 7340 /* 7341 * Read the active lane information from the 8051 registers and return 7342 * their widths. 7343 * 7344 * Active lane information is found in these 8051 registers: 7345 * enable_lane_tx 7346 * enable_lane_rx 7347 */ 7348 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width, 7349 u16 *rx_width) 7350 { 7351 u16 tx, rx; 7352 u8 enable_lane_rx; 7353 u8 enable_lane_tx; 7354 u8 tx_polarity_inversion; 7355 u8 rx_polarity_inversion; 7356 u8 max_rate; 7357 7358 /* read the active lanes */ 7359 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 7360 &rx_polarity_inversion, &max_rate); 7361 read_local_lni(dd, &enable_lane_rx); 7362 7363 /* convert to counts */ 7364 tx = nibble_to_count(enable_lane_tx); 7365 rx = nibble_to_count(enable_lane_rx); 7366 7367 /* 7368 * Set link_speed_active here, overriding what was set in 7369 * handle_verify_cap(). The ASIC 8051 firmware does not correctly 7370 * set the max_rate field in handle_verify_cap until v0.19. 7371 */ 7372 if ((dd->icode == ICODE_RTL_SILICON) && 7373 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) { 7374 /* max_rate: 0 = 12.5G, 1 = 25G */ 7375 switch (max_rate) { 7376 case 0: 7377 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G; 7378 break; 7379 case 1: 7380 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G; 7381 break; 7382 default: 7383 dd_dev_err(dd, 7384 "%s: unexpected max rate %d, using 25Gb\n", 7385 __func__, (int)max_rate); 7386 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G; 7387 break; 7388 } 7389 } 7390 7391 dd_dev_info(dd, 7392 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n", 7393 enable_lane_tx, tx, enable_lane_rx, rx); 7394 *tx_width = link_width_to_bits(dd, tx); 7395 *rx_width = link_width_to_bits(dd, rx); 7396 } 7397 7398 /* 7399 * Read verify_cap_local_fm_link_width[1] to obtain the link widths. 7400 * Valid after the end of VerifyCap and during LinkUp. Does not change 7401 * after link up. I.e. look elsewhere for downgrade information. 7402 * 7403 * Bits are: 7404 * + bits [7:4] contain the number of active transmitters 7405 * + bits [3:0] contain the number of active receivers 7406 * These are numbers 1 through 4 and can be different values if the 7407 * link is asymmetric. 7408 * 7409 * verify_cap_local_fm_link_width[0] retains its original value. 7410 */ 7411 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width, 7412 u16 *rx_width) 7413 { 7414 u16 widths, tx, rx; 7415 u8 misc_bits, local_flags; 7416 u16 active_tx, active_rx; 7417 7418 read_vc_local_link_mode(dd, &misc_bits, &local_flags, &widths); 7419 tx = widths >> 12; 7420 rx = (widths >> 8) & 0xf; 7421 7422 *tx_width = link_width_to_bits(dd, tx); 7423 *rx_width = link_width_to_bits(dd, rx); 7424 7425 /* print the active widths */ 7426 get_link_widths(dd, &active_tx, &active_rx); 7427 } 7428 7429 /* 7430 * Set ppd->link_width_active and ppd->link_width_downgrade_active using 7431 * hardware information when the link first comes up. 7432 * 7433 * The link width is not available until after VerifyCap.AllFramesReceived 7434 * (the trigger for handle_verify_cap), so this is outside that routine 7435 * and should be called when the 8051 signals linkup. 7436 */ 7437 void get_linkup_link_widths(struct hfi1_pportdata *ppd) 7438 { 7439 u16 tx_width, rx_width; 7440 7441 /* get end-of-LNI link widths */ 7442 get_linkup_widths(ppd->dd, &tx_width, &rx_width); 7443 7444 /* use tx_width as the link is supposed to be symmetric on link up */ 7445 ppd->link_width_active = tx_width; 7446 /* link width downgrade active (LWD.A) starts out matching LW.A */ 7447 ppd->link_width_downgrade_tx_active = ppd->link_width_active; 7448 ppd->link_width_downgrade_rx_active = ppd->link_width_active; 7449 /* per OPA spec, on link up LWD.E resets to LWD.S */ 7450 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported; 7451 /* cache the active egress rate (units {10^6 bits/sec]) */ 7452 ppd->current_egress_rate = active_egress_rate(ppd); 7453 } 7454 7455 /* 7456 * Handle a verify capabilities interrupt from the 8051. 7457 * 7458 * This is a work-queue function outside of the interrupt. 7459 */ 7460 void handle_verify_cap(struct work_struct *work) 7461 { 7462 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7463 link_vc_work); 7464 struct hfi1_devdata *dd = ppd->dd; 7465 u64 reg; 7466 u8 power_management; 7467 u8 continuous; 7468 u8 vcu; 7469 u8 vau; 7470 u8 z; 7471 u16 vl15buf; 7472 u16 link_widths; 7473 u16 crc_mask; 7474 u16 crc_val; 7475 u16 device_id; 7476 u16 active_tx, active_rx; 7477 u8 partner_supported_crc; 7478 u8 remote_tx_rate; 7479 u8 device_rev; 7480 7481 set_link_state(ppd, HLS_VERIFY_CAP); 7482 7483 lcb_shutdown(dd, 0); 7484 adjust_lcb_for_fpga_serdes(dd); 7485 7486 read_vc_remote_phy(dd, &power_management, &continuous); 7487 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf, 7488 &partner_supported_crc); 7489 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths); 7490 read_remote_device_id(dd, &device_id, &device_rev); 7491 7492 /* print the active widths */ 7493 get_link_widths(dd, &active_tx, &active_rx); 7494 dd_dev_info(dd, 7495 "Peer PHY: power management 0x%x, continuous updates 0x%x\n", 7496 (int)power_management, (int)continuous); 7497 dd_dev_info(dd, 7498 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n", 7499 (int)vau, (int)z, (int)vcu, (int)vl15buf, 7500 (int)partner_supported_crc); 7501 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n", 7502 (u32)remote_tx_rate, (u32)link_widths); 7503 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n", 7504 (u32)device_id, (u32)device_rev); 7505 /* 7506 * The peer vAU value just read is the peer receiver value. HFI does 7507 * not support a transmit vAU of 0 (AU == 8). We advertised that 7508 * with Z=1 in the fabric capabilities sent to the peer. The peer 7509 * will see our Z=1, and, if it advertised a vAU of 0, will move its 7510 * receive to vAU of 1 (AU == 16). Do the same here. We do not care 7511 * about the peer Z value - our sent vAU is 3 (hardwired) and is not 7512 * subject to the Z value exception. 7513 */ 7514 if (vau == 0) 7515 vau = 1; 7516 set_up_vau(dd, vau); 7517 7518 /* 7519 * Set VL15 credits to 0 in global credit register. Cache remote VL15 7520 * credits value and wait for link-up interrupt ot set it. 7521 */ 7522 set_up_vl15(dd, 0); 7523 dd->vl15buf_cached = vl15buf; 7524 7525 /* set up the LCB CRC mode */ 7526 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc; 7527 7528 /* order is important: use the lowest bit in common */ 7529 if (crc_mask & CAP_CRC_14B) 7530 crc_val = LCB_CRC_14B; 7531 else if (crc_mask & CAP_CRC_48B) 7532 crc_val = LCB_CRC_48B; 7533 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE) 7534 crc_val = LCB_CRC_12B_16B_PER_LANE; 7535 else 7536 crc_val = LCB_CRC_16B; 7537 7538 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val); 7539 write_csr(dd, DC_LCB_CFG_CRC_MODE, 7540 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT); 7541 7542 /* set (14b only) or clear sideband credit */ 7543 reg = read_csr(dd, SEND_CM_CTRL); 7544 if (crc_val == LCB_CRC_14B && crc_14b_sideband) { 7545 write_csr(dd, SEND_CM_CTRL, 7546 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7547 } else { 7548 write_csr(dd, SEND_CM_CTRL, 7549 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7550 } 7551 7552 ppd->link_speed_active = 0; /* invalid value */ 7553 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 7554 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */ 7555 switch (remote_tx_rate) { 7556 case 0: 7557 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7558 break; 7559 case 1: 7560 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7561 break; 7562 } 7563 } else { 7564 /* actual rate is highest bit of the ANDed rates */ 7565 u8 rate = remote_tx_rate & ppd->local_tx_rate; 7566 7567 if (rate & 2) 7568 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7569 else if (rate & 1) 7570 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7571 } 7572 if (ppd->link_speed_active == 0) { 7573 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n", 7574 __func__, (int)remote_tx_rate); 7575 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7576 } 7577 7578 /* 7579 * Cache the values of the supported, enabled, and active 7580 * LTP CRC modes to return in 'portinfo' queries. But the bit 7581 * flags that are returned in the portinfo query differ from 7582 * what's in the link_crc_mask, crc_sizes, and crc_val 7583 * variables. Convert these here. 7584 */ 7585 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 7586 /* supported crc modes */ 7587 ppd->port_ltp_crc_mode |= 7588 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4; 7589 /* enabled crc modes */ 7590 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val); 7591 /* active crc mode */ 7592 7593 /* set up the remote credit return table */ 7594 assign_remote_cm_au_table(dd, vcu); 7595 7596 /* 7597 * The LCB is reset on entry to handle_verify_cap(), so this must 7598 * be applied on every link up. 7599 * 7600 * Adjust LCB error kill enable to kill the link if 7601 * these RBUF errors are seen: 7602 * REPLAY_BUF_MBE_SMASK 7603 * FLIT_INPUT_BUF_MBE_SMASK 7604 */ 7605 if (is_ax(dd)) { /* fixed in B0 */ 7606 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); 7607 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 7608 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK; 7609 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); 7610 } 7611 7612 /* pull LCB fifos out of reset - all fifo clocks must be stable */ 7613 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 7614 7615 /* give 8051 access to the LCB CSRs */ 7616 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 7617 set_8051_lcb_access(dd); 7618 7619 /* tell the 8051 to go to LinkUp */ 7620 set_link_state(ppd, HLS_GOING_UP); 7621 } 7622 7623 /** 7624 * apply_link_downgrade_policy - Apply the link width downgrade enabled 7625 * policy against the current active link widths. 7626 * @ppd: info of physical Hfi port 7627 * @refresh_widths: True indicates link downgrade event 7628 * @return: True indicates a successful link downgrade. False indicates 7629 * link downgrade event failed and the link will bounce back to 7630 * default link width. 7631 * 7632 * Called when the enabled policy changes or the active link widths 7633 * change. 7634 * Refresh_widths indicates that a link downgrade occurred. The 7635 * link_downgraded variable is set by refresh_widths and 7636 * determines the success/failure of the policy application. 7637 */ 7638 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, 7639 bool refresh_widths) 7640 { 7641 int do_bounce = 0; 7642 int tries; 7643 u16 lwde; 7644 u16 tx, rx; 7645 bool link_downgraded = refresh_widths; 7646 7647 /* use the hls lock to avoid a race with actual link up */ 7648 tries = 0; 7649 retry: 7650 mutex_lock(&ppd->hls_lock); 7651 /* only apply if the link is up */ 7652 if (ppd->host_link_state & HLS_DOWN) { 7653 /* still going up..wait and retry */ 7654 if (ppd->host_link_state & HLS_GOING_UP) { 7655 if (++tries < 1000) { 7656 mutex_unlock(&ppd->hls_lock); 7657 usleep_range(100, 120); /* arbitrary */ 7658 goto retry; 7659 } 7660 dd_dev_err(ppd->dd, 7661 "%s: giving up waiting for link state change\n", 7662 __func__); 7663 } 7664 goto done; 7665 } 7666 7667 lwde = ppd->link_width_downgrade_enabled; 7668 7669 if (refresh_widths) { 7670 get_link_widths(ppd->dd, &tx, &rx); 7671 ppd->link_width_downgrade_tx_active = tx; 7672 ppd->link_width_downgrade_rx_active = rx; 7673 } 7674 7675 if (ppd->link_width_downgrade_tx_active == 0 || 7676 ppd->link_width_downgrade_rx_active == 0) { 7677 /* the 8051 reported a dead link as a downgrade */ 7678 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n"); 7679 link_downgraded = false; 7680 } else if (lwde == 0) { 7681 /* downgrade is disabled */ 7682 7683 /* bounce if not at starting active width */ 7684 if ((ppd->link_width_active != 7685 ppd->link_width_downgrade_tx_active) || 7686 (ppd->link_width_active != 7687 ppd->link_width_downgrade_rx_active)) { 7688 dd_dev_err(ppd->dd, 7689 "Link downgrade is disabled and link has downgraded, downing link\n"); 7690 dd_dev_err(ppd->dd, 7691 " original 0x%x, tx active 0x%x, rx active 0x%x\n", 7692 ppd->link_width_active, 7693 ppd->link_width_downgrade_tx_active, 7694 ppd->link_width_downgrade_rx_active); 7695 do_bounce = 1; 7696 link_downgraded = false; 7697 } 7698 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 || 7699 (lwde & ppd->link_width_downgrade_rx_active) == 0) { 7700 /* Tx or Rx is outside the enabled policy */ 7701 dd_dev_err(ppd->dd, 7702 "Link is outside of downgrade allowed, downing link\n"); 7703 dd_dev_err(ppd->dd, 7704 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n", 7705 lwde, ppd->link_width_downgrade_tx_active, 7706 ppd->link_width_downgrade_rx_active); 7707 do_bounce = 1; 7708 link_downgraded = false; 7709 } 7710 7711 done: 7712 mutex_unlock(&ppd->hls_lock); 7713 7714 if (do_bounce) { 7715 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0, 7716 OPA_LINKDOWN_REASON_WIDTH_POLICY); 7717 set_link_state(ppd, HLS_DN_OFFLINE); 7718 start_link(ppd); 7719 } 7720 7721 return link_downgraded; 7722 } 7723 7724 /* 7725 * Handle a link downgrade interrupt from the 8051. 7726 * 7727 * This is a work-queue function outside of the interrupt. 7728 */ 7729 void handle_link_downgrade(struct work_struct *work) 7730 { 7731 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7732 link_downgrade_work); 7733 7734 dd_dev_info(ppd->dd, "8051: Link width downgrade\n"); 7735 if (apply_link_downgrade_policy(ppd, true)) 7736 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active); 7737 } 7738 7739 static char *dcc_err_string(char *buf, int buf_len, u64 flags) 7740 { 7741 return flag_string(buf, buf_len, flags, dcc_err_flags, 7742 ARRAY_SIZE(dcc_err_flags)); 7743 } 7744 7745 static char *lcb_err_string(char *buf, int buf_len, u64 flags) 7746 { 7747 return flag_string(buf, buf_len, flags, lcb_err_flags, 7748 ARRAY_SIZE(lcb_err_flags)); 7749 } 7750 7751 static char *dc8051_err_string(char *buf, int buf_len, u64 flags) 7752 { 7753 return flag_string(buf, buf_len, flags, dc8051_err_flags, 7754 ARRAY_SIZE(dc8051_err_flags)); 7755 } 7756 7757 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags) 7758 { 7759 return flag_string(buf, buf_len, flags, dc8051_info_err_flags, 7760 ARRAY_SIZE(dc8051_info_err_flags)); 7761 } 7762 7763 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags) 7764 { 7765 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags, 7766 ARRAY_SIZE(dc8051_info_host_msg_flags)); 7767 } 7768 7769 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg) 7770 { 7771 struct hfi1_pportdata *ppd = dd->pport; 7772 u64 info, err, host_msg; 7773 int queue_link_down = 0; 7774 char buf[96]; 7775 7776 /* look at the flags */ 7777 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) { 7778 /* 8051 information set by firmware */ 7779 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */ 7780 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); 7781 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT) 7782 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK; 7783 host_msg = (info >> 7784 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT) 7785 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK; 7786 7787 /* 7788 * Handle error flags. 7789 */ 7790 if (err & FAILED_LNI) { 7791 /* 7792 * LNI error indications are cleared by the 8051 7793 * only when starting polling. Only pay attention 7794 * to them when in the states that occur during 7795 * LNI. 7796 */ 7797 if (ppd->host_link_state 7798 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 7799 queue_link_down = 1; 7800 dd_dev_info(dd, "Link error: %s\n", 7801 dc8051_info_err_string(buf, 7802 sizeof(buf), 7803 err & 7804 FAILED_LNI)); 7805 } 7806 err &= ~(u64)FAILED_LNI; 7807 } 7808 /* unknown frames can happen durning LNI, just count */ 7809 if (err & UNKNOWN_FRAME) { 7810 ppd->unknown_frame_count++; 7811 err &= ~(u64)UNKNOWN_FRAME; 7812 } 7813 if (err) { 7814 /* report remaining errors, but do not do anything */ 7815 dd_dev_err(dd, "8051 info error: %s\n", 7816 dc8051_info_err_string(buf, sizeof(buf), 7817 err)); 7818 } 7819 7820 /* 7821 * Handle host message flags. 7822 */ 7823 if (host_msg & HOST_REQ_DONE) { 7824 /* 7825 * Presently, the driver does a busy wait for 7826 * host requests to complete. This is only an 7827 * informational message. 7828 * NOTE: The 8051 clears the host message 7829 * information *on the next 8051 command*. 7830 * Therefore, when linkup is achieved, 7831 * this flag will still be set. 7832 */ 7833 host_msg &= ~(u64)HOST_REQ_DONE; 7834 } 7835 if (host_msg & BC_SMA_MSG) { 7836 queue_work(ppd->link_wq, &ppd->sma_message_work); 7837 host_msg &= ~(u64)BC_SMA_MSG; 7838 } 7839 if (host_msg & LINKUP_ACHIEVED) { 7840 dd_dev_info(dd, "8051: Link up\n"); 7841 queue_work(ppd->link_wq, &ppd->link_up_work); 7842 host_msg &= ~(u64)LINKUP_ACHIEVED; 7843 } 7844 if (host_msg & EXT_DEVICE_CFG_REQ) { 7845 handle_8051_request(ppd); 7846 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ; 7847 } 7848 if (host_msg & VERIFY_CAP_FRAME) { 7849 queue_work(ppd->link_wq, &ppd->link_vc_work); 7850 host_msg &= ~(u64)VERIFY_CAP_FRAME; 7851 } 7852 if (host_msg & LINK_GOING_DOWN) { 7853 const char *extra = ""; 7854 /* no downgrade action needed if going down */ 7855 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7856 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7857 extra = " (ignoring downgrade)"; 7858 } 7859 dd_dev_info(dd, "8051: Link down%s\n", extra); 7860 queue_link_down = 1; 7861 host_msg &= ~(u64)LINK_GOING_DOWN; 7862 } 7863 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7864 queue_work(ppd->link_wq, &ppd->link_downgrade_work); 7865 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7866 } 7867 if (host_msg) { 7868 /* report remaining messages, but do not do anything */ 7869 dd_dev_info(dd, "8051 info host message: %s\n", 7870 dc8051_info_host_msg_string(buf, 7871 sizeof(buf), 7872 host_msg)); 7873 } 7874 7875 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK; 7876 } 7877 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) { 7878 /* 7879 * Lost the 8051 heartbeat. If this happens, we 7880 * receive constant interrupts about it. Disable 7881 * the interrupt after the first. 7882 */ 7883 dd_dev_err(dd, "Lost 8051 heartbeat\n"); 7884 write_csr(dd, DC_DC8051_ERR_EN, 7885 read_csr(dd, DC_DC8051_ERR_EN) & 7886 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK); 7887 7888 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK; 7889 } 7890 if (reg) { 7891 /* report the error, but do not do anything */ 7892 dd_dev_err(dd, "8051 error: %s\n", 7893 dc8051_err_string(buf, sizeof(buf), reg)); 7894 } 7895 7896 if (queue_link_down) { 7897 /* 7898 * if the link is already going down or disabled, do not 7899 * queue another. If there's a link down entry already 7900 * queued, don't queue another one. 7901 */ 7902 if ((ppd->host_link_state & 7903 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) || 7904 ppd->link_enabled == 0) { 7905 dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n", 7906 __func__, ppd->host_link_state, 7907 ppd->link_enabled); 7908 } else { 7909 if (xchg(&ppd->is_link_down_queued, 1) == 1) 7910 dd_dev_info(dd, 7911 "%s: link down request already queued\n", 7912 __func__); 7913 else 7914 queue_work(ppd->link_wq, &ppd->link_down_work); 7915 } 7916 } 7917 } 7918 7919 static const char * const fm_config_txt[] = { 7920 [0] = 7921 "BadHeadDist: Distance violation between two head flits", 7922 [1] = 7923 "BadTailDist: Distance violation between two tail flits", 7924 [2] = 7925 "BadCtrlDist: Distance violation between two credit control flits", 7926 [3] = 7927 "BadCrdAck: Credits return for unsupported VL", 7928 [4] = 7929 "UnsupportedVLMarker: Received VL Marker", 7930 [5] = 7931 "BadPreempt: Exceeded the preemption nesting level", 7932 [6] = 7933 "BadControlFlit: Received unsupported control flit", 7934 /* no 7 */ 7935 [8] = 7936 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL", 7937 }; 7938 7939 static const char * const port_rcv_txt[] = { 7940 [1] = 7941 "BadPktLen: Illegal PktLen", 7942 [2] = 7943 "PktLenTooLong: Packet longer than PktLen", 7944 [3] = 7945 "PktLenTooShort: Packet shorter than PktLen", 7946 [4] = 7947 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)", 7948 [5] = 7949 "BadDLID: Illegal DLID (0, doesn't match HFI)", 7950 [6] = 7951 "BadL2: Illegal L2 opcode", 7952 [7] = 7953 "BadSC: Unsupported SC", 7954 [9] = 7955 "BadRC: Illegal RC", 7956 [11] = 7957 "PreemptError: Preempting with same VL", 7958 [12] = 7959 "PreemptVL15: Preempting a VL15 packet", 7960 }; 7961 7962 #define OPA_LDR_FMCONFIG_OFFSET 16 7963 #define OPA_LDR_PORTRCV_OFFSET 0 7964 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 7965 { 7966 u64 info, hdr0, hdr1; 7967 const char *extra; 7968 char buf[96]; 7969 struct hfi1_pportdata *ppd = dd->pport; 7970 u8 lcl_reason = 0; 7971 int do_bounce = 0; 7972 7973 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) { 7974 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) { 7975 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); 7976 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK; 7977 /* set status bit */ 7978 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK; 7979 } 7980 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK; 7981 } 7982 7983 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) { 7984 struct hfi1_pportdata *ppd = dd->pport; 7985 /* this counter saturates at (2^32) - 1 */ 7986 if (ppd->link_downed < (u32)UINT_MAX) 7987 ppd->link_downed++; 7988 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK; 7989 } 7990 7991 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) { 7992 u8 reason_valid = 1; 7993 7994 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); 7995 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) { 7996 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK; 7997 /* set status bit */ 7998 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK; 7999 } 8000 switch (info) { 8001 case 0: 8002 case 1: 8003 case 2: 8004 case 3: 8005 case 4: 8006 case 5: 8007 case 6: 8008 extra = fm_config_txt[info]; 8009 break; 8010 case 8: 8011 extra = fm_config_txt[info]; 8012 if (ppd->port_error_action & 8013 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) { 8014 do_bounce = 1; 8015 /* 8016 * lcl_reason cannot be derived from info 8017 * for this error 8018 */ 8019 lcl_reason = 8020 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER; 8021 } 8022 break; 8023 default: 8024 reason_valid = 0; 8025 snprintf(buf, sizeof(buf), "reserved%lld", info); 8026 extra = buf; 8027 break; 8028 } 8029 8030 if (reason_valid && !do_bounce) { 8031 do_bounce = ppd->port_error_action & 8032 (1 << (OPA_LDR_FMCONFIG_OFFSET + info)); 8033 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST; 8034 } 8035 8036 /* just report this */ 8037 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n", 8038 extra); 8039 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK; 8040 } 8041 8042 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) { 8043 u8 reason_valid = 1; 8044 8045 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); 8046 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); 8047 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); 8048 if (!(dd->err_info_rcvport.status_and_code & 8049 OPA_EI_STATUS_SMASK)) { 8050 dd->err_info_rcvport.status_and_code = 8051 info & OPA_EI_CODE_SMASK; 8052 /* set status bit */ 8053 dd->err_info_rcvport.status_and_code |= 8054 OPA_EI_STATUS_SMASK; 8055 /* 8056 * save first 2 flits in the packet that caused 8057 * the error 8058 */ 8059 dd->err_info_rcvport.packet_flit1 = hdr0; 8060 dd->err_info_rcvport.packet_flit2 = hdr1; 8061 } 8062 switch (info) { 8063 case 1: 8064 case 2: 8065 case 3: 8066 case 4: 8067 case 5: 8068 case 6: 8069 case 7: 8070 case 9: 8071 case 11: 8072 case 12: 8073 extra = port_rcv_txt[info]; 8074 break; 8075 default: 8076 reason_valid = 0; 8077 snprintf(buf, sizeof(buf), "reserved%lld", info); 8078 extra = buf; 8079 break; 8080 } 8081 8082 if (reason_valid && !do_bounce) { 8083 do_bounce = ppd->port_error_action & 8084 (1 << (OPA_LDR_PORTRCV_OFFSET + info)); 8085 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0; 8086 } 8087 8088 /* just report this */ 8089 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n" 8090 " hdr0 0x%llx, hdr1 0x%llx\n", 8091 extra, hdr0, hdr1); 8092 8093 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK; 8094 } 8095 8096 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) { 8097 /* informative only */ 8098 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n"); 8099 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK; 8100 } 8101 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) { 8102 /* informative only */ 8103 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n"); 8104 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK; 8105 } 8106 8107 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev))) 8108 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK; 8109 8110 /* report any remaining errors */ 8111 if (reg) 8112 dd_dev_info_ratelimited(dd, "DCC Error: %s\n", 8113 dcc_err_string(buf, sizeof(buf), reg)); 8114 8115 if (lcl_reason == 0) 8116 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN; 8117 8118 if (do_bounce) { 8119 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n", 8120 __func__); 8121 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason); 8122 queue_work(ppd->link_wq, &ppd->link_bounce_work); 8123 } 8124 } 8125 8126 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 8127 { 8128 char buf[96]; 8129 8130 dd_dev_info(dd, "LCB Error: %s\n", 8131 lcb_err_string(buf, sizeof(buf), reg)); 8132 } 8133 8134 /* 8135 * CCE block DC interrupt. Source is < 8. 8136 */ 8137 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source) 8138 { 8139 const struct err_reg_info *eri = &dc_errs[source]; 8140 8141 if (eri->handler) { 8142 interrupt_clear_down(dd, 0, eri); 8143 } else if (source == 3 /* dc_lbm_int */) { 8144 /* 8145 * This indicates that a parity error has occurred on the 8146 * address/control lines presented to the LBM. The error 8147 * is a single pulse, there is no associated error flag, 8148 * and it is non-maskable. This is because if a parity 8149 * error occurs on the request the request is dropped. 8150 * This should never occur, but it is nice to know if it 8151 * ever does. 8152 */ 8153 dd_dev_err(dd, "Parity error in DC LBM block\n"); 8154 } else { 8155 dd_dev_err(dd, "Invalid DC interrupt %u\n", source); 8156 } 8157 } 8158 8159 /* 8160 * TX block send credit interrupt. Source is < 160. 8161 */ 8162 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source) 8163 { 8164 sc_group_release_update(dd, source); 8165 } 8166 8167 /* 8168 * TX block SDMA interrupt. Source is < 48. 8169 * 8170 * SDMA interrupts are grouped by type: 8171 * 8172 * 0 - N-1 = SDma 8173 * N - 2N-1 = SDmaProgress 8174 * 2N - 3N-1 = SDmaIdle 8175 */ 8176 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source) 8177 { 8178 /* what interrupt */ 8179 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 8180 /* which engine */ 8181 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 8182 8183 #ifdef CONFIG_SDMA_VERBOSITY 8184 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which, 8185 slashstrip(__FILE__), __LINE__, __func__); 8186 sdma_dumpstate(&dd->per_sdma[which]); 8187 #endif 8188 8189 if (likely(what < 3 && which < dd->num_sdma)) { 8190 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source); 8191 } else { 8192 /* should not happen */ 8193 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source); 8194 } 8195 } 8196 8197 /** 8198 * is_rcv_avail_int() - User receive context available IRQ handler 8199 * @dd: valid dd 8200 * @source: logical IRQ source (offset from IS_RCVAVAIL_START) 8201 * 8202 * RX block receive available interrupt. Source is < 160. 8203 * 8204 * This is the general interrupt handler for user (PSM) receive contexts, 8205 * and can only be used for non-threaded IRQs. 8206 */ 8207 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source) 8208 { 8209 struct hfi1_ctxtdata *rcd; 8210 char *err_detail; 8211 8212 if (likely(source < dd->num_rcv_contexts)) { 8213 rcd = hfi1_rcd_get_by_index(dd, source); 8214 if (rcd) { 8215 handle_user_interrupt(rcd); 8216 hfi1_rcd_put(rcd); 8217 return; /* OK */ 8218 } 8219 /* received an interrupt, but no rcd */ 8220 err_detail = "dataless"; 8221 } else { 8222 /* received an interrupt, but are not using that context */ 8223 err_detail = "out of range"; 8224 } 8225 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n", 8226 err_detail, source); 8227 } 8228 8229 /** 8230 * is_rcv_urgent_int() - User receive context urgent IRQ handler 8231 * @dd: valid dd 8232 * @source: logical IRQ source (offset from IS_RCVURGENT_START) 8233 * 8234 * RX block receive urgent interrupt. Source is < 160. 8235 * 8236 * NOTE: kernel receive contexts specifically do NOT enable this IRQ. 8237 */ 8238 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source) 8239 { 8240 struct hfi1_ctxtdata *rcd; 8241 char *err_detail; 8242 8243 if (likely(source < dd->num_rcv_contexts)) { 8244 rcd = hfi1_rcd_get_by_index(dd, source); 8245 if (rcd) { 8246 handle_user_interrupt(rcd); 8247 hfi1_rcd_put(rcd); 8248 return; /* OK */ 8249 } 8250 /* received an interrupt, but no rcd */ 8251 err_detail = "dataless"; 8252 } else { 8253 /* received an interrupt, but are not using that context */ 8254 err_detail = "out of range"; 8255 } 8256 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n", 8257 err_detail, source); 8258 } 8259 8260 /* 8261 * Reserved range interrupt. Should not be called in normal operation. 8262 */ 8263 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source) 8264 { 8265 char name[64]; 8266 8267 dd_dev_err(dd, "unexpected %s interrupt\n", 8268 is_reserved_name(name, sizeof(name), source)); 8269 } 8270 8271 static const struct is_table is_table[] = { 8272 /* 8273 * start end 8274 * name func interrupt func 8275 */ 8276 { IS_GENERAL_ERR_START, IS_GENERAL_ERR_END, 8277 is_misc_err_name, is_misc_err_int }, 8278 { IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END, 8279 is_sdma_eng_err_name, is_sdma_eng_err_int }, 8280 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, 8281 is_sendctxt_err_name, is_sendctxt_err_int }, 8282 { IS_SDMA_START, IS_SDMA_IDLE_END, 8283 is_sdma_eng_name, is_sdma_eng_int }, 8284 { IS_VARIOUS_START, IS_VARIOUS_END, 8285 is_various_name, is_various_int }, 8286 { IS_DC_START, IS_DC_END, 8287 is_dc_name, is_dc_int }, 8288 { IS_RCVAVAIL_START, IS_RCVAVAIL_END, 8289 is_rcv_avail_name, is_rcv_avail_int }, 8290 { IS_RCVURGENT_START, IS_RCVURGENT_END, 8291 is_rcv_urgent_name, is_rcv_urgent_int }, 8292 { IS_SENDCREDIT_START, IS_SENDCREDIT_END, 8293 is_send_credit_name, is_send_credit_int}, 8294 { IS_RESERVED_START, IS_RESERVED_END, 8295 is_reserved_name, is_reserved_int}, 8296 }; 8297 8298 /* 8299 * Interrupt source interrupt - called when the given source has an interrupt. 8300 * Source is a bit index into an array of 64-bit integers. 8301 */ 8302 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source) 8303 { 8304 const struct is_table *entry; 8305 8306 /* avoids a double compare by walking the table in-order */ 8307 for (entry = &is_table[0]; entry->is_name; entry++) { 8308 if (source <= entry->end) { 8309 trace_hfi1_interrupt(dd, entry, source); 8310 entry->is_int(dd, source - entry->start); 8311 return; 8312 } 8313 } 8314 /* fell off the end */ 8315 dd_dev_err(dd, "invalid interrupt source %u\n", source); 8316 } 8317 8318 /** 8319 * gerneral_interrupt() - General interrupt handler 8320 * @irq: MSIx IRQ vector 8321 * @data: hfi1 devdata 8322 * 8323 * This is able to correctly handle all non-threaded interrupts. Receive 8324 * context DATA IRQs are threaded and are not supported by this handler. 8325 * 8326 */ 8327 irqreturn_t general_interrupt(int irq, void *data) 8328 { 8329 struct hfi1_devdata *dd = data; 8330 u64 regs[CCE_NUM_INT_CSRS]; 8331 u32 bit; 8332 int i; 8333 irqreturn_t handled = IRQ_NONE; 8334 8335 this_cpu_inc(*dd->int_counter); 8336 8337 /* phase 1: scan and clear all handled interrupts */ 8338 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 8339 if (dd->gi_mask[i] == 0) { 8340 regs[i] = 0; /* used later */ 8341 continue; 8342 } 8343 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & 8344 dd->gi_mask[i]; 8345 /* only clear if anything is set */ 8346 if (regs[i]) 8347 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); 8348 } 8349 8350 /* phase 2: call the appropriate handler */ 8351 for_each_set_bit(bit, (unsigned long *)®s[0], 8352 CCE_NUM_INT_CSRS * 64) { 8353 is_interrupt(dd, bit); 8354 handled = IRQ_HANDLED; 8355 } 8356 8357 return handled; 8358 } 8359 8360 irqreturn_t sdma_interrupt(int irq, void *data) 8361 { 8362 struct sdma_engine *sde = data; 8363 struct hfi1_devdata *dd = sde->dd; 8364 u64 status; 8365 8366 #ifdef CONFIG_SDMA_VERBOSITY 8367 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 8368 slashstrip(__FILE__), __LINE__, __func__); 8369 sdma_dumpstate(sde); 8370 #endif 8371 8372 this_cpu_inc(*dd->int_counter); 8373 8374 /* This read_csr is really bad in the hot path */ 8375 status = read_csr(dd, 8376 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64))) 8377 & sde->imask; 8378 if (likely(status)) { 8379 /* clear the interrupt(s) */ 8380 write_csr(dd, 8381 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)), 8382 status); 8383 8384 /* handle the interrupt(s) */ 8385 sdma_engine_interrupt(sde, status); 8386 } else { 8387 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n", 8388 sde->this_idx); 8389 } 8390 return IRQ_HANDLED; 8391 } 8392 8393 /* 8394 * Clear the receive interrupt. Use a read of the interrupt clear CSR 8395 * to insure that the write completed. This does NOT guarantee that 8396 * queued DMA writes to memory from the chip are pushed. 8397 */ 8398 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd) 8399 { 8400 struct hfi1_devdata *dd = rcd->dd; 8401 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg); 8402 8403 write_csr(dd, addr, rcd->imask); 8404 /* force the above write on the chip and get a value back */ 8405 (void)read_csr(dd, addr); 8406 } 8407 8408 /* force the receive interrupt */ 8409 void force_recv_intr(struct hfi1_ctxtdata *rcd) 8410 { 8411 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); 8412 } 8413 8414 /* 8415 * Return non-zero if a packet is present. 8416 * 8417 * This routine is called when rechecking for packets after the RcvAvail 8418 * interrupt has been cleared down. First, do a quick check of memory for 8419 * a packet present. If not found, use an expensive CSR read of the context 8420 * tail to determine the actual tail. The CSR read is necessary because there 8421 * is no method to push pending DMAs to memory other than an interrupt and we 8422 * are trying to determine if we need to force an interrupt. 8423 */ 8424 static inline int check_packet_present(struct hfi1_ctxtdata *rcd) 8425 { 8426 u32 tail; 8427 8428 if (hfi1_packet_present(rcd)) 8429 return 1; 8430 8431 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */ 8432 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 8433 return hfi1_rcd_head(rcd) != tail; 8434 } 8435 8436 /** 8437 * Common code for receive contexts interrupt handlers. 8438 * Update traces, increment kernel IRQ counter and 8439 * setup ASPM when needed. 8440 */ 8441 static void receive_interrupt_common(struct hfi1_ctxtdata *rcd) 8442 { 8443 struct hfi1_devdata *dd = rcd->dd; 8444 8445 trace_hfi1_receive_interrupt(dd, rcd); 8446 this_cpu_inc(*dd->int_counter); 8447 aspm_ctx_disable(rcd); 8448 } 8449 8450 /** 8451 * __hfi1_rcd_eoi_intr() - Make HW issue receive interrupt 8452 * when there are packets present in the queue. When calling 8453 * with interrupts enabled please use hfi1_rcd_eoi_intr. 8454 * 8455 * @rcd: valid receive context 8456 */ 8457 static void __hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd) 8458 { 8459 clear_recv_intr(rcd); 8460 if (check_packet_present(rcd)) 8461 force_recv_intr(rcd); 8462 } 8463 8464 /** 8465 * hfi1_rcd_eoi_intr() - End of Interrupt processing action 8466 * 8467 * @rcd: Ptr to hfi1_ctxtdata of receive context 8468 * 8469 * Hold IRQs so we can safely clear the interrupt and 8470 * recheck for a packet that may have arrived after the previous 8471 * check and the interrupt clear. If a packet arrived, force another 8472 * interrupt. This routine can be called at the end of receive packet 8473 * processing in interrupt service routines, interrupt service thread 8474 * and softirqs 8475 */ 8476 static void hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd) 8477 { 8478 unsigned long flags; 8479 8480 local_irq_save(flags); 8481 __hfi1_rcd_eoi_intr(rcd); 8482 local_irq_restore(flags); 8483 } 8484 8485 /** 8486 * hfi1_netdev_rx_napi - napi poll function to move eoi inline 8487 * @napi - pointer to napi object 8488 * @budget - netdev budget 8489 */ 8490 int hfi1_netdev_rx_napi(struct napi_struct *napi, int budget) 8491 { 8492 struct hfi1_netdev_rxq *rxq = container_of(napi, 8493 struct hfi1_netdev_rxq, napi); 8494 struct hfi1_ctxtdata *rcd = rxq->rcd; 8495 int work_done = 0; 8496 8497 work_done = rcd->do_interrupt(rcd, budget); 8498 8499 if (work_done < budget) { 8500 napi_complete_done(napi, work_done); 8501 hfi1_rcd_eoi_intr(rcd); 8502 } 8503 8504 return work_done; 8505 } 8506 8507 /* Receive packet napi handler for netdevs VNIC and AIP */ 8508 irqreturn_t receive_context_interrupt_napi(int irq, void *data) 8509 { 8510 struct hfi1_ctxtdata *rcd = data; 8511 8512 receive_interrupt_common(rcd); 8513 8514 if (likely(rcd->napi)) { 8515 if (likely(napi_schedule_prep(rcd->napi))) 8516 __napi_schedule_irqoff(rcd->napi); 8517 else 8518 __hfi1_rcd_eoi_intr(rcd); 8519 } else { 8520 WARN_ONCE(1, "Napi IRQ handler without napi set up ctxt=%d\n", 8521 rcd->ctxt); 8522 __hfi1_rcd_eoi_intr(rcd); 8523 } 8524 8525 return IRQ_HANDLED; 8526 } 8527 8528 /* 8529 * Receive packet IRQ handler. This routine expects to be on its own IRQ. 8530 * This routine will try to handle packets immediately (latency), but if 8531 * it finds too many, it will invoke the thread handler (bandwitdh). The 8532 * chip receive interrupt is *not* cleared down until this or the thread (if 8533 * invoked) is finished. The intent is to avoid extra interrupts while we 8534 * are processing packets anyway. 8535 */ 8536 irqreturn_t receive_context_interrupt(int irq, void *data) 8537 { 8538 struct hfi1_ctxtdata *rcd = data; 8539 int disposition; 8540 8541 receive_interrupt_common(rcd); 8542 8543 /* receive interrupt remains blocked while processing packets */ 8544 disposition = rcd->do_interrupt(rcd, 0); 8545 8546 /* 8547 * Too many packets were seen while processing packets in this 8548 * IRQ handler. Invoke the handler thread. The receive interrupt 8549 * remains blocked. 8550 */ 8551 if (disposition == RCV_PKT_LIMIT) 8552 return IRQ_WAKE_THREAD; 8553 8554 __hfi1_rcd_eoi_intr(rcd); 8555 return IRQ_HANDLED; 8556 } 8557 8558 /* 8559 * Receive packet thread handler. This expects to be invoked with the 8560 * receive interrupt still blocked. 8561 */ 8562 irqreturn_t receive_context_thread(int irq, void *data) 8563 { 8564 struct hfi1_ctxtdata *rcd = data; 8565 8566 /* receive interrupt is still blocked from the IRQ handler */ 8567 (void)rcd->do_interrupt(rcd, 1); 8568 8569 hfi1_rcd_eoi_intr(rcd); 8570 8571 return IRQ_HANDLED; 8572 } 8573 8574 /* ========================================================================= */ 8575 8576 u32 read_physical_state(struct hfi1_devdata *dd) 8577 { 8578 u64 reg; 8579 8580 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 8581 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT) 8582 & DC_DC8051_STS_CUR_STATE_PORT_MASK; 8583 } 8584 8585 u32 read_logical_state(struct hfi1_devdata *dd) 8586 { 8587 u64 reg; 8588 8589 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8590 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT) 8591 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK; 8592 } 8593 8594 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate) 8595 { 8596 u64 reg; 8597 8598 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8599 /* clear current state, set new state */ 8600 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK; 8601 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT; 8602 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); 8603 } 8604 8605 /* 8606 * Use the 8051 to read a LCB CSR. 8607 */ 8608 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data) 8609 { 8610 u32 regno; 8611 int ret; 8612 8613 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 8614 if (acquire_lcb_access(dd, 0) == 0) { 8615 *data = read_csr(dd, addr); 8616 release_lcb_access(dd, 0); 8617 return 0; 8618 } 8619 return -EBUSY; 8620 } 8621 8622 /* register is an index of LCB registers: (offset - base) / 8 */ 8623 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8624 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data); 8625 if (ret != HCMD_SUCCESS) 8626 return -EBUSY; 8627 return 0; 8628 } 8629 8630 /* 8631 * Provide a cache for some of the LCB registers in case the LCB is 8632 * unavailable. 8633 * (The LCB is unavailable in certain link states, for example.) 8634 */ 8635 struct lcb_datum { 8636 u32 off; 8637 u64 val; 8638 }; 8639 8640 static struct lcb_datum lcb_cache[] = { 8641 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0}, 8642 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 }, 8643 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 }, 8644 }; 8645 8646 static void update_lcb_cache(struct hfi1_devdata *dd) 8647 { 8648 int i; 8649 int ret; 8650 u64 val; 8651 8652 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8653 ret = read_lcb_csr(dd, lcb_cache[i].off, &val); 8654 8655 /* Update if we get good data */ 8656 if (likely(ret != -EBUSY)) 8657 lcb_cache[i].val = val; 8658 } 8659 } 8660 8661 static int read_lcb_cache(u32 off, u64 *val) 8662 { 8663 int i; 8664 8665 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8666 if (lcb_cache[i].off == off) { 8667 *val = lcb_cache[i].val; 8668 return 0; 8669 } 8670 } 8671 8672 pr_warn("%s bad offset 0x%x\n", __func__, off); 8673 return -1; 8674 } 8675 8676 /* 8677 * Read an LCB CSR. Access may not be in host control, so check. 8678 * Return 0 on success, -EBUSY on failure. 8679 */ 8680 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data) 8681 { 8682 struct hfi1_pportdata *ppd = dd->pport; 8683 8684 /* if up, go through the 8051 for the value */ 8685 if (ppd->host_link_state & HLS_UP) 8686 return read_lcb_via_8051(dd, addr, data); 8687 /* if going up or down, check the cache, otherwise, no access */ 8688 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) { 8689 if (read_lcb_cache(addr, data)) 8690 return -EBUSY; 8691 return 0; 8692 } 8693 8694 /* otherwise, host has access */ 8695 *data = read_csr(dd, addr); 8696 return 0; 8697 } 8698 8699 /* 8700 * Use the 8051 to write a LCB CSR. 8701 */ 8702 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data) 8703 { 8704 u32 regno; 8705 int ret; 8706 8707 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || 8708 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) { 8709 if (acquire_lcb_access(dd, 0) == 0) { 8710 write_csr(dd, addr, data); 8711 release_lcb_access(dd, 0); 8712 return 0; 8713 } 8714 return -EBUSY; 8715 } 8716 8717 /* register is an index of LCB registers: (offset - base) / 8 */ 8718 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8719 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data); 8720 if (ret != HCMD_SUCCESS) 8721 return -EBUSY; 8722 return 0; 8723 } 8724 8725 /* 8726 * Write an LCB CSR. Access may not be in host control, so check. 8727 * Return 0 on success, -EBUSY on failure. 8728 */ 8729 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data) 8730 { 8731 struct hfi1_pportdata *ppd = dd->pport; 8732 8733 /* if up, go through the 8051 for the value */ 8734 if (ppd->host_link_state & HLS_UP) 8735 return write_lcb_via_8051(dd, addr, data); 8736 /* if going up or down, no access */ 8737 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) 8738 return -EBUSY; 8739 /* otherwise, host has access */ 8740 write_csr(dd, addr, data); 8741 return 0; 8742 } 8743 8744 /* 8745 * Returns: 8746 * < 0 = Linux error, not able to get access 8747 * > 0 = 8051 command RETURN_CODE 8748 */ 8749 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 8750 u64 *out_data) 8751 { 8752 u64 reg, completed; 8753 int return_code; 8754 unsigned long timeout; 8755 8756 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data); 8757 8758 mutex_lock(&dd->dc8051_lock); 8759 8760 /* We can't send any commands to the 8051 if it's in reset */ 8761 if (dd->dc_shutdown) { 8762 return_code = -ENODEV; 8763 goto fail; 8764 } 8765 8766 /* 8767 * If an 8051 host command timed out previously, then the 8051 is 8768 * stuck. 8769 * 8770 * On first timeout, attempt to reset and restart the entire DC 8771 * block (including 8051). (Is this too big of a hammer?) 8772 * 8773 * If the 8051 times out a second time, the reset did not bring it 8774 * back to healthy life. In that case, fail any subsequent commands. 8775 */ 8776 if (dd->dc8051_timed_out) { 8777 if (dd->dc8051_timed_out > 1) { 8778 dd_dev_err(dd, 8779 "Previous 8051 host command timed out, skipping command %u\n", 8780 type); 8781 return_code = -ENXIO; 8782 goto fail; 8783 } 8784 _dc_shutdown(dd); 8785 _dc_start(dd); 8786 } 8787 8788 /* 8789 * If there is no timeout, then the 8051 command interface is 8790 * waiting for a command. 8791 */ 8792 8793 /* 8794 * When writing a LCB CSR, out_data contains the full value to 8795 * to be written, while in_data contains the relative LCB 8796 * address in 7:0. Do the work here, rather than the caller, 8797 * of distrubting the write data to where it needs to go: 8798 * 8799 * Write data 8800 * 39:00 -> in_data[47:8] 8801 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE 8802 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA 8803 */ 8804 if (type == HCMD_WRITE_LCB_CSR) { 8805 in_data |= ((*out_data) & 0xffffffffffull) << 8; 8806 /* must preserve COMPLETED - it is tied to hardware */ 8807 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); 8808 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK; 8809 reg |= ((((*out_data) >> 40) & 0xff) << 8810 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT) 8811 | ((((*out_data) >> 48) & 0xffff) << 8812 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 8813 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); 8814 } 8815 8816 /* 8817 * Do two writes: the first to stabilize the type and req_data, the 8818 * second to activate. 8819 */ 8820 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK) 8821 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8822 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK) 8823 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT; 8824 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8825 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK; 8826 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8827 8828 /* wait for completion, alternate: interrupt */ 8829 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT); 8830 while (1) { 8831 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); 8832 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK; 8833 if (completed) 8834 break; 8835 if (time_after(jiffies, timeout)) { 8836 dd->dc8051_timed_out++; 8837 dd_dev_err(dd, "8051 host command %u timeout\n", type); 8838 if (out_data) 8839 *out_data = 0; 8840 return_code = -ETIMEDOUT; 8841 goto fail; 8842 } 8843 udelay(2); 8844 } 8845 8846 if (out_data) { 8847 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT) 8848 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK; 8849 if (type == HCMD_READ_LCB_CSR) { 8850 /* top 16 bits are in a different register */ 8851 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) 8852 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK) 8853 << (48 8854 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT); 8855 } 8856 } 8857 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT) 8858 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK; 8859 dd->dc8051_timed_out = 0; 8860 /* 8861 * Clear command for next user. 8862 */ 8863 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); 8864 8865 fail: 8866 mutex_unlock(&dd->dc8051_lock); 8867 return return_code; 8868 } 8869 8870 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state) 8871 { 8872 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL); 8873 } 8874 8875 int load_8051_config(struct hfi1_devdata *dd, u8 field_id, 8876 u8 lane_id, u32 config_data) 8877 { 8878 u64 data; 8879 int ret; 8880 8881 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT 8882 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT 8883 | (u64)config_data << LOAD_DATA_DATA_SHIFT; 8884 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL); 8885 if (ret != HCMD_SUCCESS) { 8886 dd_dev_err(dd, 8887 "load 8051 config: field id %d, lane %d, err %d\n", 8888 (int)field_id, (int)lane_id, ret); 8889 } 8890 return ret; 8891 } 8892 8893 /* 8894 * Read the 8051 firmware "registers". Use the RAM directly. Always 8895 * set the result, even on error. 8896 * Return 0 on success, -errno on failure 8897 */ 8898 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id, 8899 u32 *result) 8900 { 8901 u64 big_data; 8902 u32 addr; 8903 int ret; 8904 8905 /* address start depends on the lane_id */ 8906 if (lane_id < 4) 8907 addr = (4 * NUM_GENERAL_FIELDS) 8908 + (lane_id * 4 * NUM_LANE_FIELDS); 8909 else 8910 addr = 0; 8911 addr += field_id * 4; 8912 8913 /* read is in 8-byte chunks, hardware will truncate the address down */ 8914 ret = read_8051_data(dd, addr, 8, &big_data); 8915 8916 if (ret == 0) { 8917 /* extract the 4 bytes we want */ 8918 if (addr & 0x4) 8919 *result = (u32)(big_data >> 32); 8920 else 8921 *result = (u32)big_data; 8922 } else { 8923 *result = 0; 8924 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n", 8925 __func__, lane_id, field_id); 8926 } 8927 8928 return ret; 8929 } 8930 8931 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management, 8932 u8 continuous) 8933 { 8934 u32 frame; 8935 8936 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 8937 | power_management << POWER_MANAGEMENT_SHIFT; 8938 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY, 8939 GENERAL_CONFIG, frame); 8940 } 8941 8942 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu, 8943 u16 vl15buf, u8 crc_sizes) 8944 { 8945 u32 frame; 8946 8947 frame = (u32)vau << VAU_SHIFT 8948 | (u32)z << Z_SHIFT 8949 | (u32)vcu << VCU_SHIFT 8950 | (u32)vl15buf << VL15BUF_SHIFT 8951 | (u32)crc_sizes << CRC_SIZES_SHIFT; 8952 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC, 8953 GENERAL_CONFIG, frame); 8954 } 8955 8956 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 8957 u8 *flag_bits, u16 *link_widths) 8958 { 8959 u32 frame; 8960 8961 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8962 &frame); 8963 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK; 8964 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK; 8965 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8966 } 8967 8968 static int write_vc_local_link_mode(struct hfi1_devdata *dd, 8969 u8 misc_bits, 8970 u8 flag_bits, 8971 u16 link_widths) 8972 { 8973 u32 frame; 8974 8975 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT 8976 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT 8977 | (u32)link_widths << LINK_WIDTH_SHIFT; 8978 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8979 frame); 8980 } 8981 8982 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id, 8983 u8 device_rev) 8984 { 8985 u32 frame; 8986 8987 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT) 8988 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT); 8989 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame); 8990 } 8991 8992 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 8993 u8 *device_rev) 8994 { 8995 u32 frame; 8996 8997 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame); 8998 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK; 8999 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT) 9000 & REMOTE_DEVICE_REV_MASK; 9001 } 9002 9003 int write_host_interface_version(struct hfi1_devdata *dd, u8 version) 9004 { 9005 u32 frame; 9006 u32 mask; 9007 9008 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); 9009 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame); 9010 /* Clear, then set field */ 9011 frame &= ~mask; 9012 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT); 9013 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, 9014 frame); 9015 } 9016 9017 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 9018 u8 *ver_patch) 9019 { 9020 u32 frame; 9021 9022 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame); 9023 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) & 9024 STS_FM_VERSION_MAJOR_MASK; 9025 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) & 9026 STS_FM_VERSION_MINOR_MASK; 9027 9028 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame); 9029 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) & 9030 STS_FM_VERSION_PATCH_MASK; 9031 } 9032 9033 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 9034 u8 *continuous) 9035 { 9036 u32 frame; 9037 9038 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame); 9039 *power_management = (frame >> POWER_MANAGEMENT_SHIFT) 9040 & POWER_MANAGEMENT_MASK; 9041 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT) 9042 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK; 9043 } 9044 9045 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 9046 u8 *vcu, u16 *vl15buf, u8 *crc_sizes) 9047 { 9048 u32 frame; 9049 9050 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame); 9051 *vau = (frame >> VAU_SHIFT) & VAU_MASK; 9052 *z = (frame >> Z_SHIFT) & Z_MASK; 9053 *vcu = (frame >> VCU_SHIFT) & VCU_MASK; 9054 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK; 9055 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK; 9056 } 9057 9058 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 9059 u8 *remote_tx_rate, 9060 u16 *link_widths) 9061 { 9062 u32 frame; 9063 9064 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG, 9065 &frame); 9066 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT) 9067 & REMOTE_TX_RATE_MASK; 9068 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 9069 } 9070 9071 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx) 9072 { 9073 u32 frame; 9074 9075 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame); 9076 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK; 9077 } 9078 9079 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls) 9080 { 9081 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls); 9082 } 9083 9084 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs) 9085 { 9086 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs); 9087 } 9088 9089 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality) 9090 { 9091 u32 frame; 9092 int ret; 9093 9094 *link_quality = 0; 9095 if (dd->pport->host_link_state & HLS_UP) { 9096 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, 9097 &frame); 9098 if (ret == 0) 9099 *link_quality = (frame >> LINK_QUALITY_SHIFT) 9100 & LINK_QUALITY_MASK; 9101 } 9102 } 9103 9104 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc) 9105 { 9106 u32 frame; 9107 9108 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame); 9109 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK; 9110 } 9111 9112 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr) 9113 { 9114 u32 frame; 9115 9116 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame); 9117 *ldr = (frame & 0xff); 9118 } 9119 9120 static int read_tx_settings(struct hfi1_devdata *dd, 9121 u8 *enable_lane_tx, 9122 u8 *tx_polarity_inversion, 9123 u8 *rx_polarity_inversion, 9124 u8 *max_rate) 9125 { 9126 u32 frame; 9127 int ret; 9128 9129 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame); 9130 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT) 9131 & ENABLE_LANE_TX_MASK; 9132 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT) 9133 & TX_POLARITY_INVERSION_MASK; 9134 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT) 9135 & RX_POLARITY_INVERSION_MASK; 9136 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK; 9137 return ret; 9138 } 9139 9140 static int write_tx_settings(struct hfi1_devdata *dd, 9141 u8 enable_lane_tx, 9142 u8 tx_polarity_inversion, 9143 u8 rx_polarity_inversion, 9144 u8 max_rate) 9145 { 9146 u32 frame; 9147 9148 /* no need to mask, all variable sizes match field widths */ 9149 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT 9150 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT 9151 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT 9152 | max_rate << MAX_RATE_SHIFT; 9153 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame); 9154 } 9155 9156 /* 9157 * Read an idle LCB message. 9158 * 9159 * Returns 0 on success, -EINVAL on error 9160 */ 9161 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out) 9162 { 9163 int ret; 9164 9165 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out); 9166 if (ret != HCMD_SUCCESS) { 9167 dd_dev_err(dd, "read idle message: type %d, err %d\n", 9168 (u32)type, ret); 9169 return -EINVAL; 9170 } 9171 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out); 9172 /* return only the payload as we already know the type */ 9173 *data_out >>= IDLE_PAYLOAD_SHIFT; 9174 return 0; 9175 } 9176 9177 /* 9178 * Read an idle SMA message. To be done in response to a notification from 9179 * the 8051. 9180 * 9181 * Returns 0 on success, -EINVAL on error 9182 */ 9183 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data) 9184 { 9185 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT, 9186 data); 9187 } 9188 9189 /* 9190 * Send an idle LCB message. 9191 * 9192 * Returns 0 on success, -EINVAL on error 9193 */ 9194 static int send_idle_message(struct hfi1_devdata *dd, u64 data) 9195 { 9196 int ret; 9197 9198 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data); 9199 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL); 9200 if (ret != HCMD_SUCCESS) { 9201 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n", 9202 data, ret); 9203 return -EINVAL; 9204 } 9205 return 0; 9206 } 9207 9208 /* 9209 * Send an idle SMA message. 9210 * 9211 * Returns 0 on success, -EINVAL on error 9212 */ 9213 int send_idle_sma(struct hfi1_devdata *dd, u64 message) 9214 { 9215 u64 data; 9216 9217 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) | 9218 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT); 9219 return send_idle_message(dd, data); 9220 } 9221 9222 /* 9223 * Initialize the LCB then do a quick link up. This may or may not be 9224 * in loopback. 9225 * 9226 * return 0 on success, -errno on error 9227 */ 9228 static int do_quick_linkup(struct hfi1_devdata *dd) 9229 { 9230 int ret; 9231 9232 lcb_shutdown(dd, 0); 9233 9234 if (loopback) { 9235 /* LCB_CFG_LOOPBACK.VAL = 2 */ 9236 /* LCB_CFG_LANE_WIDTH.VAL = 0 */ 9237 write_csr(dd, DC_LCB_CFG_LOOPBACK, 9238 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT); 9239 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 9240 } 9241 9242 /* start the LCBs */ 9243 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */ 9244 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 9245 9246 /* simulator only loopback steps */ 9247 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 9248 /* LCB_CFG_RUN.EN = 1 */ 9249 write_csr(dd, DC_LCB_CFG_RUN, 9250 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 9251 9252 ret = wait_link_transfer_active(dd, 10); 9253 if (ret) 9254 return ret; 9255 9256 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 9257 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT); 9258 } 9259 9260 if (!loopback) { 9261 /* 9262 * When doing quick linkup and not in loopback, both 9263 * sides must be done with LCB set-up before either 9264 * starts the quick linkup. Put a delay here so that 9265 * both sides can be started and have a chance to be 9266 * done with LCB set up before resuming. 9267 */ 9268 dd_dev_err(dd, 9269 "Pausing for peer to be finished with LCB set up\n"); 9270 msleep(5000); 9271 dd_dev_err(dd, "Continuing with quick linkup\n"); 9272 } 9273 9274 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 9275 set_8051_lcb_access(dd); 9276 9277 /* 9278 * State "quick" LinkUp request sets the physical link state to 9279 * LinkUp without a verify capability sequence. 9280 * This state is in simulator v37 and later. 9281 */ 9282 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP); 9283 if (ret != HCMD_SUCCESS) { 9284 dd_dev_err(dd, 9285 "%s: set physical link state to quick LinkUp failed with return %d\n", 9286 __func__, ret); 9287 9288 set_host_lcb_access(dd); 9289 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 9290 9291 if (ret >= 0) 9292 ret = -EINVAL; 9293 return ret; 9294 } 9295 9296 return 0; /* success */ 9297 } 9298 9299 /* 9300 * Do all special steps to set up loopback. 9301 */ 9302 static int init_loopback(struct hfi1_devdata *dd) 9303 { 9304 dd_dev_info(dd, "Entering loopback mode\n"); 9305 9306 /* all loopbacks should disable self GUID check */ 9307 write_csr(dd, DC_DC8051_CFG_MODE, 9308 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); 9309 9310 /* 9311 * The simulator has only one loopback option - LCB. Switch 9312 * to that option, which includes quick link up. 9313 * 9314 * Accept all valid loopback values. 9315 */ 9316 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) && 9317 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB || 9318 loopback == LOOPBACK_CABLE)) { 9319 loopback = LOOPBACK_LCB; 9320 quick_linkup = 1; 9321 return 0; 9322 } 9323 9324 /* 9325 * SerDes loopback init sequence is handled in set_local_link_attributes 9326 */ 9327 if (loopback == LOOPBACK_SERDES) 9328 return 0; 9329 9330 /* LCB loopback - handled at poll time */ 9331 if (loopback == LOOPBACK_LCB) { 9332 quick_linkup = 1; /* LCB is always quick linkup */ 9333 9334 /* not supported in emulation due to emulation RTL changes */ 9335 if (dd->icode == ICODE_FPGA_EMULATION) { 9336 dd_dev_err(dd, 9337 "LCB loopback not supported in emulation\n"); 9338 return -EINVAL; 9339 } 9340 return 0; 9341 } 9342 9343 /* external cable loopback requires no extra steps */ 9344 if (loopback == LOOPBACK_CABLE) 9345 return 0; 9346 9347 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback); 9348 return -EINVAL; 9349 } 9350 9351 /* 9352 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits 9353 * used in the Verify Capability link width attribute. 9354 */ 9355 static u16 opa_to_vc_link_widths(u16 opa_widths) 9356 { 9357 int i; 9358 u16 result = 0; 9359 9360 static const struct link_bits { 9361 u16 from; 9362 u16 to; 9363 } opa_link_xlate[] = { 9364 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) }, 9365 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) }, 9366 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) }, 9367 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) }, 9368 }; 9369 9370 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) { 9371 if (opa_widths & opa_link_xlate[i].from) 9372 result |= opa_link_xlate[i].to; 9373 } 9374 return result; 9375 } 9376 9377 /* 9378 * Set link attributes before moving to polling. 9379 */ 9380 static int set_local_link_attributes(struct hfi1_pportdata *ppd) 9381 { 9382 struct hfi1_devdata *dd = ppd->dd; 9383 u8 enable_lane_tx; 9384 u8 tx_polarity_inversion; 9385 u8 rx_polarity_inversion; 9386 int ret; 9387 u32 misc_bits = 0; 9388 /* reset our fabric serdes to clear any lingering problems */ 9389 fabric_serdes_reset(dd); 9390 9391 /* set the local tx rate - need to read-modify-write */ 9392 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 9393 &rx_polarity_inversion, &ppd->local_tx_rate); 9394 if (ret) 9395 goto set_local_link_attributes_fail; 9396 9397 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 9398 /* set the tx rate to the fastest enabled */ 9399 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9400 ppd->local_tx_rate = 1; 9401 else 9402 ppd->local_tx_rate = 0; 9403 } else { 9404 /* set the tx rate to all enabled */ 9405 ppd->local_tx_rate = 0; 9406 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9407 ppd->local_tx_rate |= 2; 9408 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G) 9409 ppd->local_tx_rate |= 1; 9410 } 9411 9412 enable_lane_tx = 0xF; /* enable all four lanes */ 9413 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion, 9414 rx_polarity_inversion, ppd->local_tx_rate); 9415 if (ret != HCMD_SUCCESS) 9416 goto set_local_link_attributes_fail; 9417 9418 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION); 9419 if (ret != HCMD_SUCCESS) { 9420 dd_dev_err(dd, 9421 "Failed to set host interface version, return 0x%x\n", 9422 ret); 9423 goto set_local_link_attributes_fail; 9424 } 9425 9426 /* 9427 * DC supports continuous updates. 9428 */ 9429 ret = write_vc_local_phy(dd, 9430 0 /* no power management */, 9431 1 /* continuous updates */); 9432 if (ret != HCMD_SUCCESS) 9433 goto set_local_link_attributes_fail; 9434 9435 /* z=1 in the next call: AU of 0 is not supported by the hardware */ 9436 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init, 9437 ppd->port_crc_mode_enabled); 9438 if (ret != HCMD_SUCCESS) 9439 goto set_local_link_attributes_fail; 9440 9441 /* 9442 * SerDes loopback init sequence requires 9443 * setting bit 0 of MISC_CONFIG_BITS 9444 */ 9445 if (loopback == LOOPBACK_SERDES) 9446 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT; 9447 9448 /* 9449 * An external device configuration request is used to reset the LCB 9450 * to retry to obtain operational lanes when the first attempt is 9451 * unsuccesful. 9452 */ 9453 if (dd->dc8051_ver >= dc8051_ver(1, 25, 0)) 9454 misc_bits |= 1 << EXT_CFG_LCB_RESET_SUPPORTED_SHIFT; 9455 9456 ret = write_vc_local_link_mode(dd, misc_bits, 0, 9457 opa_to_vc_link_widths( 9458 ppd->link_width_enabled)); 9459 if (ret != HCMD_SUCCESS) 9460 goto set_local_link_attributes_fail; 9461 9462 /* let peer know who we are */ 9463 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev); 9464 if (ret == HCMD_SUCCESS) 9465 return 0; 9466 9467 set_local_link_attributes_fail: 9468 dd_dev_err(dd, 9469 "Failed to set local link attributes, return 0x%x\n", 9470 ret); 9471 return ret; 9472 } 9473 9474 /* 9475 * Call this to start the link. 9476 * Do not do anything if the link is disabled. 9477 * Returns 0 if link is disabled, moved to polling, or the driver is not ready. 9478 */ 9479 int start_link(struct hfi1_pportdata *ppd) 9480 { 9481 /* 9482 * Tune the SerDes to a ballpark setting for optimal signal and bit 9483 * error rate. Needs to be done before starting the link. 9484 */ 9485 tune_serdes(ppd); 9486 9487 if (!ppd->driver_link_ready) { 9488 dd_dev_info(ppd->dd, 9489 "%s: stopping link start because driver is not ready\n", 9490 __func__); 9491 return 0; 9492 } 9493 9494 /* 9495 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the 9496 * pkey table can be configured properly if the HFI unit is connected 9497 * to switch port with MgmtAllowed=NO 9498 */ 9499 clear_full_mgmt_pkey(ppd); 9500 9501 return set_link_state(ppd, HLS_DN_POLL); 9502 } 9503 9504 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd) 9505 { 9506 struct hfi1_devdata *dd = ppd->dd; 9507 u64 mask; 9508 unsigned long timeout; 9509 9510 /* 9511 * Some QSFP cables have a quirk that asserts the IntN line as a side 9512 * effect of power up on plug-in. We ignore this false positive 9513 * interrupt until the module has finished powering up by waiting for 9514 * a minimum timeout of the module inrush initialization time of 9515 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the 9516 * module have stabilized. 9517 */ 9518 msleep(500); 9519 9520 /* 9521 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1) 9522 */ 9523 timeout = jiffies + msecs_to_jiffies(2000); 9524 while (1) { 9525 mask = read_csr(dd, dd->hfi1_id ? 9526 ASIC_QSFP2_IN : ASIC_QSFP1_IN); 9527 if (!(mask & QSFP_HFI0_INT_N)) 9528 break; 9529 if (time_after(jiffies, timeout)) { 9530 dd_dev_info(dd, "%s: No IntN detected, reset complete\n", 9531 __func__); 9532 break; 9533 } 9534 udelay(2); 9535 } 9536 } 9537 9538 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable) 9539 { 9540 struct hfi1_devdata *dd = ppd->dd; 9541 u64 mask; 9542 9543 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); 9544 if (enable) { 9545 /* 9546 * Clear the status register to avoid an immediate interrupt 9547 * when we re-enable the IntN pin 9548 */ 9549 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9550 QSFP_HFI0_INT_N); 9551 mask |= (u64)QSFP_HFI0_INT_N; 9552 } else { 9553 mask &= ~(u64)QSFP_HFI0_INT_N; 9554 } 9555 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); 9556 } 9557 9558 int reset_qsfp(struct hfi1_pportdata *ppd) 9559 { 9560 struct hfi1_devdata *dd = ppd->dd; 9561 u64 mask, qsfp_mask; 9562 9563 /* Disable INT_N from triggering QSFP interrupts */ 9564 set_qsfp_int_n(ppd, 0); 9565 9566 /* Reset the QSFP */ 9567 mask = (u64)QSFP_HFI0_RESET_N; 9568 9569 qsfp_mask = read_csr(dd, 9570 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT); 9571 qsfp_mask &= ~mask; 9572 write_csr(dd, 9573 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9574 9575 udelay(10); 9576 9577 qsfp_mask |= mask; 9578 write_csr(dd, 9579 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9580 9581 wait_for_qsfp_init(ppd); 9582 9583 /* 9584 * Allow INT_N to trigger the QSFP interrupt to watch 9585 * for alarms and warnings 9586 */ 9587 set_qsfp_int_n(ppd, 1); 9588 9589 /* 9590 * After the reset, AOC transmitters are enabled by default. They need 9591 * to be turned off to complete the QSFP setup before they can be 9592 * enabled again. 9593 */ 9594 return set_qsfp_tx(ppd, 0); 9595 } 9596 9597 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd, 9598 u8 *qsfp_interrupt_status) 9599 { 9600 struct hfi1_devdata *dd = ppd->dd; 9601 9602 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) || 9603 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING)) 9604 dd_dev_err(dd, "%s: QSFP cable temperature too high\n", 9605 __func__); 9606 9607 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) || 9608 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING)) 9609 dd_dev_err(dd, "%s: QSFP cable temperature too low\n", 9610 __func__); 9611 9612 /* 9613 * The remaining alarms/warnings don't matter if the link is down. 9614 */ 9615 if (ppd->host_link_state & HLS_DOWN) 9616 return 0; 9617 9618 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) || 9619 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING)) 9620 dd_dev_err(dd, "%s: QSFP supply voltage too high\n", 9621 __func__); 9622 9623 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) || 9624 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING)) 9625 dd_dev_err(dd, "%s: QSFP supply voltage too low\n", 9626 __func__); 9627 9628 /* Byte 2 is vendor specific */ 9629 9630 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) || 9631 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING)) 9632 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n", 9633 __func__); 9634 9635 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) || 9636 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING)) 9637 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n", 9638 __func__); 9639 9640 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) || 9641 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING)) 9642 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n", 9643 __func__); 9644 9645 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) || 9646 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING)) 9647 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n", 9648 __func__); 9649 9650 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) || 9651 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING)) 9652 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n", 9653 __func__); 9654 9655 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) || 9656 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING)) 9657 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n", 9658 __func__); 9659 9660 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) || 9661 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING)) 9662 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n", 9663 __func__); 9664 9665 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) || 9666 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING)) 9667 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n", 9668 __func__); 9669 9670 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) || 9671 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING)) 9672 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n", 9673 __func__); 9674 9675 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) || 9676 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING)) 9677 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n", 9678 __func__); 9679 9680 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) || 9681 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING)) 9682 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n", 9683 __func__); 9684 9685 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) || 9686 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING)) 9687 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n", 9688 __func__); 9689 9690 /* Bytes 9-10 and 11-12 are reserved */ 9691 /* Bytes 13-15 are vendor specific */ 9692 9693 return 0; 9694 } 9695 9696 /* This routine will only be scheduled if the QSFP module present is asserted */ 9697 void qsfp_event(struct work_struct *work) 9698 { 9699 struct qsfp_data *qd; 9700 struct hfi1_pportdata *ppd; 9701 struct hfi1_devdata *dd; 9702 9703 qd = container_of(work, struct qsfp_data, qsfp_work); 9704 ppd = qd->ppd; 9705 dd = ppd->dd; 9706 9707 /* Sanity check */ 9708 if (!qsfp_mod_present(ppd)) 9709 return; 9710 9711 if (ppd->host_link_state == HLS_DN_DISABLE) { 9712 dd_dev_info(ppd->dd, 9713 "%s: stopping link start because link is disabled\n", 9714 __func__); 9715 return; 9716 } 9717 9718 /* 9719 * Turn DC back on after cable has been re-inserted. Up until 9720 * now, the DC has been in reset to save power. 9721 */ 9722 dc_start(dd); 9723 9724 if (qd->cache_refresh_required) { 9725 set_qsfp_int_n(ppd, 0); 9726 9727 wait_for_qsfp_init(ppd); 9728 9729 /* 9730 * Allow INT_N to trigger the QSFP interrupt to watch 9731 * for alarms and warnings 9732 */ 9733 set_qsfp_int_n(ppd, 1); 9734 9735 start_link(ppd); 9736 } 9737 9738 if (qd->check_interrupt_flags) { 9739 u8 qsfp_interrupt_status[16] = {0,}; 9740 9741 if (one_qsfp_read(ppd, dd->hfi1_id, 6, 9742 &qsfp_interrupt_status[0], 16) != 16) { 9743 dd_dev_info(dd, 9744 "%s: Failed to read status of QSFP module\n", 9745 __func__); 9746 } else { 9747 unsigned long flags; 9748 9749 handle_qsfp_error_conditions( 9750 ppd, qsfp_interrupt_status); 9751 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 9752 ppd->qsfp_info.check_interrupt_flags = 0; 9753 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 9754 flags); 9755 } 9756 } 9757 } 9758 9759 void init_qsfp_int(struct hfi1_devdata *dd) 9760 { 9761 struct hfi1_pportdata *ppd = dd->pport; 9762 u64 qsfp_mask; 9763 9764 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 9765 /* Clear current status to avoid spurious interrupts */ 9766 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9767 qsfp_mask); 9768 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, 9769 qsfp_mask); 9770 9771 set_qsfp_int_n(ppd, 0); 9772 9773 /* Handle active low nature of INT_N and MODPRST_N pins */ 9774 if (qsfp_mod_present(ppd)) 9775 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N; 9776 write_csr(dd, 9777 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT, 9778 qsfp_mask); 9779 9780 /* Enable the appropriate QSFP IRQ source */ 9781 if (!dd->hfi1_id) 9782 set_intr_bits(dd, QSFP1_INT, QSFP1_INT, true); 9783 else 9784 set_intr_bits(dd, QSFP2_INT, QSFP2_INT, true); 9785 } 9786 9787 /* 9788 * Do a one-time initialize of the LCB block. 9789 */ 9790 static void init_lcb(struct hfi1_devdata *dd) 9791 { 9792 /* simulator does not correctly handle LCB cclk loopback, skip */ 9793 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 9794 return; 9795 9796 /* the DC has been reset earlier in the driver load */ 9797 9798 /* set LCB for cclk loopback on the port */ 9799 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); 9800 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); 9801 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); 9802 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 9803 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); 9804 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); 9805 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); 9806 } 9807 9808 /* 9809 * Perform a test read on the QSFP. Return 0 on success, -ERRNO 9810 * on error. 9811 */ 9812 static int test_qsfp_read(struct hfi1_pportdata *ppd) 9813 { 9814 int ret; 9815 u8 status; 9816 9817 /* 9818 * Report success if not a QSFP or, if it is a QSFP, but the cable is 9819 * not present 9820 */ 9821 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd)) 9822 return 0; 9823 9824 /* read byte 2, the status byte */ 9825 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1); 9826 if (ret < 0) 9827 return ret; 9828 if (ret != 1) 9829 return -EIO; 9830 9831 return 0; /* success */ 9832 } 9833 9834 /* 9835 * Values for QSFP retry. 9836 * 9837 * Give up after 10s (20 x 500ms). The overall timeout was empirically 9838 * arrived at from experience on a large cluster. 9839 */ 9840 #define MAX_QSFP_RETRIES 20 9841 #define QSFP_RETRY_WAIT 500 /* msec */ 9842 9843 /* 9844 * Try a QSFP read. If it fails, schedule a retry for later. 9845 * Called on first link activation after driver load. 9846 */ 9847 static void try_start_link(struct hfi1_pportdata *ppd) 9848 { 9849 if (test_qsfp_read(ppd)) { 9850 /* read failed */ 9851 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) { 9852 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n"); 9853 return; 9854 } 9855 dd_dev_info(ppd->dd, 9856 "QSFP not responding, waiting and retrying %d\n", 9857 (int)ppd->qsfp_retry_count); 9858 ppd->qsfp_retry_count++; 9859 queue_delayed_work(ppd->link_wq, &ppd->start_link_work, 9860 msecs_to_jiffies(QSFP_RETRY_WAIT)); 9861 return; 9862 } 9863 ppd->qsfp_retry_count = 0; 9864 9865 start_link(ppd); 9866 } 9867 9868 /* 9869 * Workqueue function to start the link after a delay. 9870 */ 9871 void handle_start_link(struct work_struct *work) 9872 { 9873 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 9874 start_link_work.work); 9875 try_start_link(ppd); 9876 } 9877 9878 int bringup_serdes(struct hfi1_pportdata *ppd) 9879 { 9880 struct hfi1_devdata *dd = ppd->dd; 9881 u64 guid; 9882 int ret; 9883 9884 if (HFI1_CAP_IS_KSET(EXTENDED_PSN)) 9885 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK); 9886 9887 guid = ppd->guids[HFI1_PORT_GUID_INDEX]; 9888 if (!guid) { 9889 if (dd->base_guid) 9890 guid = dd->base_guid + ppd->port - 1; 9891 ppd->guids[HFI1_PORT_GUID_INDEX] = guid; 9892 } 9893 9894 /* Set linkinit_reason on power up per OPA spec */ 9895 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP; 9896 9897 /* one-time init of the LCB */ 9898 init_lcb(dd); 9899 9900 if (loopback) { 9901 ret = init_loopback(dd); 9902 if (ret < 0) 9903 return ret; 9904 } 9905 9906 get_port_type(ppd); 9907 if (ppd->port_type == PORT_TYPE_QSFP) { 9908 set_qsfp_int_n(ppd, 0); 9909 wait_for_qsfp_init(ppd); 9910 set_qsfp_int_n(ppd, 1); 9911 } 9912 9913 try_start_link(ppd); 9914 return 0; 9915 } 9916 9917 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd) 9918 { 9919 struct hfi1_devdata *dd = ppd->dd; 9920 9921 /* 9922 * Shut down the link and keep it down. First turn off that the 9923 * driver wants to allow the link to be up (driver_link_ready). 9924 * Then make sure the link is not automatically restarted 9925 * (link_enabled). Cancel any pending restart. And finally 9926 * go offline. 9927 */ 9928 ppd->driver_link_ready = 0; 9929 ppd->link_enabled = 0; 9930 9931 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */ 9932 flush_delayed_work(&ppd->start_link_work); 9933 cancel_delayed_work_sync(&ppd->start_link_work); 9934 9935 ppd->offline_disabled_reason = 9936 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT); 9937 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0, 9938 OPA_LINKDOWN_REASON_REBOOT); 9939 set_link_state(ppd, HLS_DN_OFFLINE); 9940 9941 /* disable the port */ 9942 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 9943 cancel_work_sync(&ppd->freeze_work); 9944 } 9945 9946 static inline int init_cpu_counters(struct hfi1_devdata *dd) 9947 { 9948 struct hfi1_pportdata *ppd; 9949 int i; 9950 9951 ppd = (struct hfi1_pportdata *)(dd + 1); 9952 for (i = 0; i < dd->num_pports; i++, ppd++) { 9953 ppd->ibport_data.rvp.rc_acks = NULL; 9954 ppd->ibport_data.rvp.rc_qacks = NULL; 9955 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64); 9956 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64); 9957 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64); 9958 if (!ppd->ibport_data.rvp.rc_acks || 9959 !ppd->ibport_data.rvp.rc_delayed_comp || 9960 !ppd->ibport_data.rvp.rc_qacks) 9961 return -ENOMEM; 9962 } 9963 9964 return 0; 9965 } 9966 9967 /* 9968 * index is the index into the receive array 9969 */ 9970 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, 9971 u32 type, unsigned long pa, u16 order) 9972 { 9973 u64 reg; 9974 9975 if (!(dd->flags & HFI1_PRESENT)) 9976 goto done; 9977 9978 if (type == PT_INVALID || type == PT_INVALID_FLUSH) { 9979 pa = 0; 9980 order = 0; 9981 } else if (type > PT_INVALID) { 9982 dd_dev_err(dd, 9983 "unexpected receive array type %u for index %u, not handled\n", 9984 type, index); 9985 goto done; 9986 } 9987 trace_hfi1_put_tid(dd, index, type, pa, order); 9988 9989 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */ 9990 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK 9991 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT 9992 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK) 9993 << RCV_ARRAY_RT_ADDR_SHIFT; 9994 trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg); 9995 writeq(reg, dd->rcvarray_wc + (index * 8)); 9996 9997 if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3) 9998 /* 9999 * Eager entries are written and flushed 10000 * 10001 * Expected entries are flushed every 4 writes 10002 */ 10003 flush_wc(); 10004 done: 10005 return; 10006 } 10007 10008 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd) 10009 { 10010 struct hfi1_devdata *dd = rcd->dd; 10011 u32 i; 10012 10013 /* this could be optimized */ 10014 for (i = rcd->eager_base; i < rcd->eager_base + 10015 rcd->egrbufs.alloced; i++) 10016 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 10017 10018 for (i = rcd->expected_base; 10019 i < rcd->expected_base + rcd->expected_count; i++) 10020 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 10021 } 10022 10023 static const char * const ib_cfg_name_strings[] = { 10024 "HFI1_IB_CFG_LIDLMC", 10025 "HFI1_IB_CFG_LWID_DG_ENB", 10026 "HFI1_IB_CFG_LWID_ENB", 10027 "HFI1_IB_CFG_LWID", 10028 "HFI1_IB_CFG_SPD_ENB", 10029 "HFI1_IB_CFG_SPD", 10030 "HFI1_IB_CFG_RXPOL_ENB", 10031 "HFI1_IB_CFG_LREV_ENB", 10032 "HFI1_IB_CFG_LINKLATENCY", 10033 "HFI1_IB_CFG_HRTBT", 10034 "HFI1_IB_CFG_OP_VLS", 10035 "HFI1_IB_CFG_VL_HIGH_CAP", 10036 "HFI1_IB_CFG_VL_LOW_CAP", 10037 "HFI1_IB_CFG_OVERRUN_THRESH", 10038 "HFI1_IB_CFG_PHYERR_THRESH", 10039 "HFI1_IB_CFG_LINKDEFAULT", 10040 "HFI1_IB_CFG_PKEYS", 10041 "HFI1_IB_CFG_MTU", 10042 "HFI1_IB_CFG_LSTATE", 10043 "HFI1_IB_CFG_VL_HIGH_LIMIT", 10044 "HFI1_IB_CFG_PMA_TICKS", 10045 "HFI1_IB_CFG_PORT" 10046 }; 10047 10048 static const char *ib_cfg_name(int which) 10049 { 10050 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings)) 10051 return "invalid"; 10052 return ib_cfg_name_strings[which]; 10053 } 10054 10055 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which) 10056 { 10057 struct hfi1_devdata *dd = ppd->dd; 10058 int val = 0; 10059 10060 switch (which) { 10061 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */ 10062 val = ppd->link_width_enabled; 10063 break; 10064 case HFI1_IB_CFG_LWID: /* currently active Link-width */ 10065 val = ppd->link_width_active; 10066 break; 10067 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 10068 val = ppd->link_speed_enabled; 10069 break; 10070 case HFI1_IB_CFG_SPD: /* current Link speed */ 10071 val = ppd->link_speed_active; 10072 break; 10073 10074 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */ 10075 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */ 10076 case HFI1_IB_CFG_LINKLATENCY: 10077 goto unimplemented; 10078 10079 case HFI1_IB_CFG_OP_VLS: 10080 val = ppd->actual_vls_operational; 10081 break; 10082 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */ 10083 val = VL_ARB_HIGH_PRIO_TABLE_SIZE; 10084 break; 10085 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */ 10086 val = VL_ARB_LOW_PRIO_TABLE_SIZE; 10087 break; 10088 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 10089 val = ppd->overrun_threshold; 10090 break; 10091 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 10092 val = ppd->phy_error_threshold; 10093 break; 10094 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 10095 val = HLS_DEFAULT; 10096 break; 10097 10098 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */ 10099 case HFI1_IB_CFG_PMA_TICKS: 10100 default: 10101 unimplemented: 10102 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 10103 dd_dev_info( 10104 dd, 10105 "%s: which %s: not implemented\n", 10106 __func__, 10107 ib_cfg_name(which)); 10108 break; 10109 } 10110 10111 return val; 10112 } 10113 10114 /* 10115 * The largest MAD packet size. 10116 */ 10117 #define MAX_MAD_PACKET 2048 10118 10119 /* 10120 * Return the maximum header bytes that can go on the _wire_ 10121 * for this device. This count includes the ICRC which is 10122 * not part of the packet held in memory but it is appended 10123 * by the HW. 10124 * This is dependent on the device's receive header entry size. 10125 * HFI allows this to be set per-receive context, but the 10126 * driver presently enforces a global value. 10127 */ 10128 u32 lrh_max_header_bytes(struct hfi1_devdata *dd) 10129 { 10130 /* 10131 * The maximum non-payload (MTU) bytes in LRH.PktLen are 10132 * the Receive Header Entry Size minus the PBC (or RHF) size 10133 * plus one DW for the ICRC appended by HW. 10134 * 10135 * dd->rcd[0].rcvhdrqentsize is in DW. 10136 * We use rcd[0] as all context will have the same value. Also, 10137 * the first kernel context would have been allocated by now so 10138 * we are guaranteed a valid value. 10139 */ 10140 return (get_hdrqentsize(dd->rcd[0]) - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2; 10141 } 10142 10143 /* 10144 * Set Send Length 10145 * @ppd - per port data 10146 * 10147 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck* 10148 * registers compare against LRH.PktLen, so use the max bytes included 10149 * in the LRH. 10150 * 10151 * This routine changes all VL values except VL15, which it maintains at 10152 * the same value. 10153 */ 10154 static void set_send_length(struct hfi1_pportdata *ppd) 10155 { 10156 struct hfi1_devdata *dd = ppd->dd; 10157 u32 max_hb = lrh_max_header_bytes(dd), dcmtu; 10158 u32 maxvlmtu = dd->vld[15].mtu; 10159 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2) 10160 & SEND_LEN_CHECK1_LEN_VL15_MASK) << 10161 SEND_LEN_CHECK1_LEN_VL15_SHIFT; 10162 int i, j; 10163 u32 thres; 10164 10165 for (i = 0; i < ppd->vls_supported; i++) { 10166 if (dd->vld[i].mtu > maxvlmtu) 10167 maxvlmtu = dd->vld[i].mtu; 10168 if (i <= 3) 10169 len1 |= (((dd->vld[i].mtu + max_hb) >> 2) 10170 & SEND_LEN_CHECK0_LEN_VL0_MASK) << 10171 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT); 10172 else 10173 len2 |= (((dd->vld[i].mtu + max_hb) >> 2) 10174 & SEND_LEN_CHECK1_LEN_VL4_MASK) << 10175 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT); 10176 } 10177 write_csr(dd, SEND_LEN_CHECK0, len1); 10178 write_csr(dd, SEND_LEN_CHECK1, len2); 10179 /* adjust kernel credit return thresholds based on new MTUs */ 10180 /* all kernel receive contexts have the same hdrqentsize */ 10181 for (i = 0; i < ppd->vls_supported; i++) { 10182 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50), 10183 sc_mtu_to_threshold(dd->vld[i].sc, 10184 dd->vld[i].mtu, 10185 get_hdrqentsize(dd->rcd[0]))); 10186 for (j = 0; j < INIT_SC_PER_VL; j++) 10187 sc_set_cr_threshold( 10188 pio_select_send_context_vl(dd, j, i), 10189 thres); 10190 } 10191 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50), 10192 sc_mtu_to_threshold(dd->vld[15].sc, 10193 dd->vld[15].mtu, 10194 dd->rcd[0]->rcvhdrqentsize)); 10195 sc_set_cr_threshold(dd->vld[15].sc, thres); 10196 10197 /* Adjust maximum MTU for the port in DC */ 10198 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 : 10199 (ilog2(maxvlmtu >> 8) + 1); 10200 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); 10201 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK; 10202 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) << 10203 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT; 10204 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); 10205 } 10206 10207 static void set_lidlmc(struct hfi1_pportdata *ppd) 10208 { 10209 int i; 10210 u64 sreg = 0; 10211 struct hfi1_devdata *dd = ppd->dd; 10212 u32 mask = ~((1U << ppd->lmc) - 1); 10213 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); 10214 u32 lid; 10215 10216 /* 10217 * Program 0 in CSR if port lid is extended. This prevents 10218 * 9B packets being sent out for large lids. 10219 */ 10220 lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid; 10221 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 10222 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK); 10223 c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK) 10224 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) | 10225 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK) 10226 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT); 10227 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); 10228 10229 /* 10230 * Iterate over all the send contexts and set their SLID check 10231 */ 10232 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) << 10233 SEND_CTXT_CHECK_SLID_MASK_SHIFT) | 10234 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) << 10235 SEND_CTXT_CHECK_SLID_VALUE_SHIFT); 10236 10237 for (i = 0; i < chip_send_contexts(dd); i++) { 10238 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x", 10239 i, (u32)sreg); 10240 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg); 10241 } 10242 10243 /* Now we have to do the same thing for the sdma engines */ 10244 sdma_update_lmc(dd, mask, lid); 10245 } 10246 10247 static const char *state_completed_string(u32 completed) 10248 { 10249 static const char * const state_completed[] = { 10250 "EstablishComm", 10251 "OptimizeEQ", 10252 "VerifyCap" 10253 }; 10254 10255 if (completed < ARRAY_SIZE(state_completed)) 10256 return state_completed[completed]; 10257 10258 return "unknown"; 10259 } 10260 10261 static const char all_lanes_dead_timeout_expired[] = 10262 "All lanes were inactive – was the interconnect media removed?"; 10263 static const char tx_out_of_policy[] = 10264 "Passing lanes on local port do not meet the local link width policy"; 10265 static const char no_state_complete[] = 10266 "State timeout occurred before link partner completed the state"; 10267 static const char * const state_complete_reasons[] = { 10268 [0x00] = "Reason unknown", 10269 [0x01] = "Link was halted by driver, refer to LinkDownReason", 10270 [0x02] = "Link partner reported failure", 10271 [0x10] = "Unable to achieve frame sync on any lane", 10272 [0x11] = 10273 "Unable to find a common bit rate with the link partner", 10274 [0x12] = 10275 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy", 10276 [0x13] = 10277 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy", 10278 [0x14] = no_state_complete, 10279 [0x15] = 10280 "State timeout occurred before link partner identified equalization presets", 10281 [0x16] = 10282 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy", 10283 [0x17] = tx_out_of_policy, 10284 [0x20] = all_lanes_dead_timeout_expired, 10285 [0x21] = 10286 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy", 10287 [0x22] = no_state_complete, 10288 [0x23] = 10289 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy", 10290 [0x24] = tx_out_of_policy, 10291 [0x30] = all_lanes_dead_timeout_expired, 10292 [0x31] = 10293 "State timeout occurred waiting for host to process received frames", 10294 [0x32] = no_state_complete, 10295 [0x33] = 10296 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy", 10297 [0x34] = tx_out_of_policy, 10298 [0x35] = "Negotiated link width is mutually exclusive", 10299 [0x36] = 10300 "Timed out before receiving verifycap frames in VerifyCap.Exchange", 10301 [0x37] = "Unable to resolve secure data exchange", 10302 }; 10303 10304 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd, 10305 u32 code) 10306 { 10307 const char *str = NULL; 10308 10309 if (code < ARRAY_SIZE(state_complete_reasons)) 10310 str = state_complete_reasons[code]; 10311 10312 if (str) 10313 return str; 10314 return "Reserved"; 10315 } 10316 10317 /* describe the given last state complete frame */ 10318 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame, 10319 const char *prefix) 10320 { 10321 struct hfi1_devdata *dd = ppd->dd; 10322 u32 success; 10323 u32 state; 10324 u32 reason; 10325 u32 lanes; 10326 10327 /* 10328 * Decode frame: 10329 * [ 0: 0] - success 10330 * [ 3: 1] - state 10331 * [ 7: 4] - next state timeout 10332 * [15: 8] - reason code 10333 * [31:16] - lanes 10334 */ 10335 success = frame & 0x1; 10336 state = (frame >> 1) & 0x7; 10337 reason = (frame >> 8) & 0xff; 10338 lanes = (frame >> 16) & 0xffff; 10339 10340 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n", 10341 prefix, frame); 10342 dd_dev_err(dd, " last reported state state: %s (0x%x)\n", 10343 state_completed_string(state), state); 10344 dd_dev_err(dd, " state successfully completed: %s\n", 10345 success ? "yes" : "no"); 10346 dd_dev_err(dd, " fail reason 0x%x: %s\n", 10347 reason, state_complete_reason_code_string(ppd, reason)); 10348 dd_dev_err(dd, " passing lane mask: 0x%x", lanes); 10349 } 10350 10351 /* 10352 * Read the last state complete frames and explain them. This routine 10353 * expects to be called if the link went down during link negotiation 10354 * and initialization (LNI). That is, anywhere between polling and link up. 10355 */ 10356 static void check_lni_states(struct hfi1_pportdata *ppd) 10357 { 10358 u32 last_local_state; 10359 u32 last_remote_state; 10360 10361 read_last_local_state(ppd->dd, &last_local_state); 10362 read_last_remote_state(ppd->dd, &last_remote_state); 10363 10364 /* 10365 * Don't report anything if there is nothing to report. A value of 10366 * 0 means the link was taken down while polling and there was no 10367 * training in-process. 10368 */ 10369 if (last_local_state == 0 && last_remote_state == 0) 10370 return; 10371 10372 decode_state_complete(ppd, last_local_state, "transmitted"); 10373 decode_state_complete(ppd, last_remote_state, "received"); 10374 } 10375 10376 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */ 10377 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms) 10378 { 10379 u64 reg; 10380 unsigned long timeout; 10381 10382 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */ 10383 timeout = jiffies + msecs_to_jiffies(wait_ms); 10384 while (1) { 10385 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); 10386 if (reg) 10387 break; 10388 if (time_after(jiffies, timeout)) { 10389 dd_dev_err(dd, 10390 "timeout waiting for LINK_TRANSFER_ACTIVE\n"); 10391 return -ETIMEDOUT; 10392 } 10393 udelay(2); 10394 } 10395 return 0; 10396 } 10397 10398 /* called when the logical link state is not down as it should be */ 10399 static void force_logical_link_state_down(struct hfi1_pportdata *ppd) 10400 { 10401 struct hfi1_devdata *dd = ppd->dd; 10402 10403 /* 10404 * Bring link up in LCB loopback 10405 */ 10406 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10407 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 10408 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 10409 10410 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 10411 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); 10412 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 10413 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); 10414 10415 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 10416 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); 10417 udelay(3); 10418 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); 10419 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 10420 10421 wait_link_transfer_active(dd, 100); 10422 10423 /* 10424 * Bring the link down again. 10425 */ 10426 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10427 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); 10428 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); 10429 10430 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n"); 10431 } 10432 10433 /* 10434 * Helper for set_link_state(). Do not call except from that routine. 10435 * Expects ppd->hls_mutex to be held. 10436 * 10437 * @rem_reason value to be sent to the neighbor 10438 * 10439 * LinkDownReasons only set if transition succeeds. 10440 */ 10441 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason) 10442 { 10443 struct hfi1_devdata *dd = ppd->dd; 10444 u32 previous_state; 10445 int offline_state_ret; 10446 int ret; 10447 10448 update_lcb_cache(dd); 10449 10450 previous_state = ppd->host_link_state; 10451 ppd->host_link_state = HLS_GOING_OFFLINE; 10452 10453 /* start offline transition */ 10454 ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE); 10455 10456 if (ret != HCMD_SUCCESS) { 10457 dd_dev_err(dd, 10458 "Failed to transition to Offline link state, return %d\n", 10459 ret); 10460 return -EINVAL; 10461 } 10462 if (ppd->offline_disabled_reason == 10463 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)) 10464 ppd->offline_disabled_reason = 10465 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 10466 10467 offline_state_ret = wait_phys_link_offline_substates(ppd, 10000); 10468 if (offline_state_ret < 0) 10469 return offline_state_ret; 10470 10471 /* Disabling AOC transmitters */ 10472 if (ppd->port_type == PORT_TYPE_QSFP && 10473 ppd->qsfp_info.limiting_active && 10474 qsfp_mod_present(ppd)) { 10475 int ret; 10476 10477 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT); 10478 if (ret == 0) { 10479 set_qsfp_tx(ppd, 0); 10480 release_chip_resource(dd, qsfp_resource(dd)); 10481 } else { 10482 /* not fatal, but should warn */ 10483 dd_dev_err(dd, 10484 "Unable to acquire lock to turn off QSFP TX\n"); 10485 } 10486 } 10487 10488 /* 10489 * Wait for the offline.Quiet transition if it hasn't happened yet. It 10490 * can take a while for the link to go down. 10491 */ 10492 if (offline_state_ret != PLS_OFFLINE_QUIET) { 10493 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000); 10494 if (ret < 0) 10495 return ret; 10496 } 10497 10498 /* 10499 * Now in charge of LCB - must be after the physical state is 10500 * offline.quiet and before host_link_state is changed. 10501 */ 10502 set_host_lcb_access(dd); 10503 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 10504 10505 /* make sure the logical state is also down */ 10506 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000); 10507 if (ret) 10508 force_logical_link_state_down(ppd); 10509 10510 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */ 10511 update_statusp(ppd, IB_PORT_DOWN); 10512 10513 /* 10514 * The LNI has a mandatory wait time after the physical state 10515 * moves to Offline.Quiet. The wait time may be different 10516 * depending on how the link went down. The 8051 firmware 10517 * will observe the needed wait time and only move to ready 10518 * when that is completed. The largest of the quiet timeouts 10519 * is 6s, so wait that long and then at least 0.5s more for 10520 * other transitions, and another 0.5s for a buffer. 10521 */ 10522 ret = wait_fm_ready(dd, 7000); 10523 if (ret) { 10524 dd_dev_err(dd, 10525 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n"); 10526 /* state is really offline, so make it so */ 10527 ppd->host_link_state = HLS_DN_OFFLINE; 10528 return ret; 10529 } 10530 10531 /* 10532 * The state is now offline and the 8051 is ready to accept host 10533 * requests. 10534 * - change our state 10535 * - notify others if we were previously in a linkup state 10536 */ 10537 ppd->host_link_state = HLS_DN_OFFLINE; 10538 if (previous_state & HLS_UP) { 10539 /* went down while link was up */ 10540 handle_linkup_change(dd, 0); 10541 } else if (previous_state 10542 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 10543 /* went down while attempting link up */ 10544 check_lni_states(ppd); 10545 10546 /* The QSFP doesn't need to be reset on LNI failure */ 10547 ppd->qsfp_info.reset_needed = 0; 10548 } 10549 10550 /* the active link width (downgrade) is 0 on link down */ 10551 ppd->link_width_active = 0; 10552 ppd->link_width_downgrade_tx_active = 0; 10553 ppd->link_width_downgrade_rx_active = 0; 10554 ppd->current_egress_rate = 0; 10555 return 0; 10556 } 10557 10558 /* return the link state name */ 10559 static const char *link_state_name(u32 state) 10560 { 10561 const char *name; 10562 int n = ilog2(state); 10563 static const char * const names[] = { 10564 [__HLS_UP_INIT_BP] = "INIT", 10565 [__HLS_UP_ARMED_BP] = "ARMED", 10566 [__HLS_UP_ACTIVE_BP] = "ACTIVE", 10567 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF", 10568 [__HLS_DN_POLL_BP] = "POLL", 10569 [__HLS_DN_DISABLE_BP] = "DISABLE", 10570 [__HLS_DN_OFFLINE_BP] = "OFFLINE", 10571 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP", 10572 [__HLS_GOING_UP_BP] = "GOING_UP", 10573 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE", 10574 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN" 10575 }; 10576 10577 name = n < ARRAY_SIZE(names) ? names[n] : NULL; 10578 return name ? name : "unknown"; 10579 } 10580 10581 /* return the link state reason name */ 10582 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state) 10583 { 10584 if (state == HLS_UP_INIT) { 10585 switch (ppd->linkinit_reason) { 10586 case OPA_LINKINIT_REASON_LINKUP: 10587 return "(LINKUP)"; 10588 case OPA_LINKINIT_REASON_FLAPPING: 10589 return "(FLAPPING)"; 10590 case OPA_LINKINIT_OUTSIDE_POLICY: 10591 return "(OUTSIDE_POLICY)"; 10592 case OPA_LINKINIT_QUARANTINED: 10593 return "(QUARANTINED)"; 10594 case OPA_LINKINIT_INSUFIC_CAPABILITY: 10595 return "(INSUFIC_CAPABILITY)"; 10596 default: 10597 break; 10598 } 10599 } 10600 return ""; 10601 } 10602 10603 /* 10604 * driver_pstate - convert the driver's notion of a port's 10605 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*). 10606 * Return -1 (converted to a u32) to indicate error. 10607 */ 10608 u32 driver_pstate(struct hfi1_pportdata *ppd) 10609 { 10610 switch (ppd->host_link_state) { 10611 case HLS_UP_INIT: 10612 case HLS_UP_ARMED: 10613 case HLS_UP_ACTIVE: 10614 return IB_PORTPHYSSTATE_LINKUP; 10615 case HLS_DN_POLL: 10616 return IB_PORTPHYSSTATE_POLLING; 10617 case HLS_DN_DISABLE: 10618 return IB_PORTPHYSSTATE_DISABLED; 10619 case HLS_DN_OFFLINE: 10620 return OPA_PORTPHYSSTATE_OFFLINE; 10621 case HLS_VERIFY_CAP: 10622 return IB_PORTPHYSSTATE_TRAINING; 10623 case HLS_GOING_UP: 10624 return IB_PORTPHYSSTATE_TRAINING; 10625 case HLS_GOING_OFFLINE: 10626 return OPA_PORTPHYSSTATE_OFFLINE; 10627 case HLS_LINK_COOLDOWN: 10628 return OPA_PORTPHYSSTATE_OFFLINE; 10629 case HLS_DN_DOWNDEF: 10630 default: 10631 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10632 ppd->host_link_state); 10633 return -1; 10634 } 10635 } 10636 10637 /* 10638 * driver_lstate - convert the driver's notion of a port's 10639 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1 10640 * (converted to a u32) to indicate error. 10641 */ 10642 u32 driver_lstate(struct hfi1_pportdata *ppd) 10643 { 10644 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN)) 10645 return IB_PORT_DOWN; 10646 10647 switch (ppd->host_link_state & HLS_UP) { 10648 case HLS_UP_INIT: 10649 return IB_PORT_INIT; 10650 case HLS_UP_ARMED: 10651 return IB_PORT_ARMED; 10652 case HLS_UP_ACTIVE: 10653 return IB_PORT_ACTIVE; 10654 default: 10655 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10656 ppd->host_link_state); 10657 return -1; 10658 } 10659 } 10660 10661 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 10662 u8 neigh_reason, u8 rem_reason) 10663 { 10664 if (ppd->local_link_down_reason.latest == 0 && 10665 ppd->neigh_link_down_reason.latest == 0) { 10666 ppd->local_link_down_reason.latest = lcl_reason; 10667 ppd->neigh_link_down_reason.latest = neigh_reason; 10668 ppd->remote_link_down_reason = rem_reason; 10669 } 10670 } 10671 10672 /** 10673 * data_vls_operational() - Verify if data VL BCT credits and MTU 10674 * are both set. 10675 * @ppd: pointer to hfi1_pportdata structure 10676 * 10677 * Return: true - Ok, false -otherwise. 10678 */ 10679 static inline bool data_vls_operational(struct hfi1_pportdata *ppd) 10680 { 10681 int i; 10682 u64 reg; 10683 10684 if (!ppd->actual_vls_operational) 10685 return false; 10686 10687 for (i = 0; i < ppd->vls_supported; i++) { 10688 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i)); 10689 if ((reg && !ppd->dd->vld[i].mtu) || 10690 (!reg && ppd->dd->vld[i].mtu)) 10691 return false; 10692 } 10693 10694 return true; 10695 } 10696 10697 /* 10698 * Change the physical and/or logical link state. 10699 * 10700 * Do not call this routine while inside an interrupt. It contains 10701 * calls to routines that can take multiple seconds to finish. 10702 * 10703 * Returns 0 on success, -errno on failure. 10704 */ 10705 int set_link_state(struct hfi1_pportdata *ppd, u32 state) 10706 { 10707 struct hfi1_devdata *dd = ppd->dd; 10708 struct ib_event event = {.device = NULL}; 10709 int ret1, ret = 0; 10710 int orig_new_state, poll_bounce; 10711 10712 mutex_lock(&ppd->hls_lock); 10713 10714 orig_new_state = state; 10715 if (state == HLS_DN_DOWNDEF) 10716 state = HLS_DEFAULT; 10717 10718 /* interpret poll -> poll as a link bounce */ 10719 poll_bounce = ppd->host_link_state == HLS_DN_POLL && 10720 state == HLS_DN_POLL; 10721 10722 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__, 10723 link_state_name(ppd->host_link_state), 10724 link_state_name(orig_new_state), 10725 poll_bounce ? "(bounce) " : "", 10726 link_state_reason_name(ppd, state)); 10727 10728 /* 10729 * If we're going to a (HLS_*) link state that implies the logical 10730 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then 10731 * reset is_sm_config_started to 0. 10732 */ 10733 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE))) 10734 ppd->is_sm_config_started = 0; 10735 10736 /* 10737 * Do nothing if the states match. Let a poll to poll link bounce 10738 * go through. 10739 */ 10740 if (ppd->host_link_state == state && !poll_bounce) 10741 goto done; 10742 10743 switch (state) { 10744 case HLS_UP_INIT: 10745 if (ppd->host_link_state == HLS_DN_POLL && 10746 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) { 10747 /* 10748 * Quick link up jumps from polling to here. 10749 * 10750 * Whether in normal or loopback mode, the 10751 * simulator jumps from polling to link up. 10752 * Accept that here. 10753 */ 10754 /* OK */ 10755 } else if (ppd->host_link_state != HLS_GOING_UP) { 10756 goto unexpected; 10757 } 10758 10759 /* 10760 * Wait for Link_Up physical state. 10761 * Physical and Logical states should already be 10762 * be transitioned to LinkUp and LinkInit respectively. 10763 */ 10764 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000); 10765 if (ret) { 10766 dd_dev_err(dd, 10767 "%s: physical state did not change to LINK-UP\n", 10768 __func__); 10769 break; 10770 } 10771 10772 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000); 10773 if (ret) { 10774 dd_dev_err(dd, 10775 "%s: logical state did not change to INIT\n", 10776 __func__); 10777 break; 10778 } 10779 10780 /* clear old transient LINKINIT_REASON code */ 10781 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR) 10782 ppd->linkinit_reason = 10783 OPA_LINKINIT_REASON_LINKUP; 10784 10785 /* enable the port */ 10786 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 10787 10788 handle_linkup_change(dd, 1); 10789 pio_kernel_linkup(dd); 10790 10791 /* 10792 * After link up, a new link width will have been set. 10793 * Update the xmit counters with regards to the new 10794 * link width. 10795 */ 10796 update_xmit_counters(ppd, ppd->link_width_active); 10797 10798 ppd->host_link_state = HLS_UP_INIT; 10799 update_statusp(ppd, IB_PORT_INIT); 10800 break; 10801 case HLS_UP_ARMED: 10802 if (ppd->host_link_state != HLS_UP_INIT) 10803 goto unexpected; 10804 10805 if (!data_vls_operational(ppd)) { 10806 dd_dev_err(dd, 10807 "%s: Invalid data VL credits or mtu\n", 10808 __func__); 10809 ret = -EINVAL; 10810 break; 10811 } 10812 10813 set_logical_state(dd, LSTATE_ARMED); 10814 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000); 10815 if (ret) { 10816 dd_dev_err(dd, 10817 "%s: logical state did not change to ARMED\n", 10818 __func__); 10819 break; 10820 } 10821 ppd->host_link_state = HLS_UP_ARMED; 10822 update_statusp(ppd, IB_PORT_ARMED); 10823 /* 10824 * The simulator does not currently implement SMA messages, 10825 * so neighbor_normal is not set. Set it here when we first 10826 * move to Armed. 10827 */ 10828 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 10829 ppd->neighbor_normal = 1; 10830 break; 10831 case HLS_UP_ACTIVE: 10832 if (ppd->host_link_state != HLS_UP_ARMED) 10833 goto unexpected; 10834 10835 set_logical_state(dd, LSTATE_ACTIVE); 10836 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000); 10837 if (ret) { 10838 dd_dev_err(dd, 10839 "%s: logical state did not change to ACTIVE\n", 10840 __func__); 10841 } else { 10842 /* tell all engines to go running */ 10843 sdma_all_running(dd); 10844 ppd->host_link_state = HLS_UP_ACTIVE; 10845 update_statusp(ppd, IB_PORT_ACTIVE); 10846 10847 /* Signal the IB layer that the port has went active */ 10848 event.device = &dd->verbs_dev.rdi.ibdev; 10849 event.element.port_num = ppd->port; 10850 event.event = IB_EVENT_PORT_ACTIVE; 10851 } 10852 break; 10853 case HLS_DN_POLL: 10854 if ((ppd->host_link_state == HLS_DN_DISABLE || 10855 ppd->host_link_state == HLS_DN_OFFLINE) && 10856 dd->dc_shutdown) 10857 dc_start(dd); 10858 /* Hand LED control to the DC */ 10859 write_csr(dd, DCC_CFG_LED_CNTRL, 0); 10860 10861 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10862 u8 tmp = ppd->link_enabled; 10863 10864 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10865 if (ret) { 10866 ppd->link_enabled = tmp; 10867 break; 10868 } 10869 ppd->remote_link_down_reason = 0; 10870 10871 if (ppd->driver_link_ready) 10872 ppd->link_enabled = 1; 10873 } 10874 10875 set_all_slowpath(ppd->dd); 10876 ret = set_local_link_attributes(ppd); 10877 if (ret) 10878 break; 10879 10880 ppd->port_error_action = 0; 10881 10882 if (quick_linkup) { 10883 /* quick linkup does not go into polling */ 10884 ret = do_quick_linkup(dd); 10885 } else { 10886 ret1 = set_physical_link_state(dd, PLS_POLLING); 10887 if (!ret1) 10888 ret1 = wait_phys_link_out_of_offline(ppd, 10889 3000); 10890 if (ret1 != HCMD_SUCCESS) { 10891 dd_dev_err(dd, 10892 "Failed to transition to Polling link state, return 0x%x\n", 10893 ret1); 10894 ret = -EINVAL; 10895 } 10896 } 10897 10898 /* 10899 * Change the host link state after requesting DC8051 to 10900 * change its physical state so that we can ignore any 10901 * interrupt with stale LNI(XX) error, which will not be 10902 * cleared until DC8051 transitions to Polling state. 10903 */ 10904 ppd->host_link_state = HLS_DN_POLL; 10905 ppd->offline_disabled_reason = 10906 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE); 10907 /* 10908 * If an error occurred above, go back to offline. The 10909 * caller may reschedule another attempt. 10910 */ 10911 if (ret) 10912 goto_offline(ppd, 0); 10913 else 10914 log_physical_state(ppd, PLS_POLLING); 10915 break; 10916 case HLS_DN_DISABLE: 10917 /* link is disabled */ 10918 ppd->link_enabled = 0; 10919 10920 /* allow any state to transition to disabled */ 10921 10922 /* must transition to offline first */ 10923 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10924 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10925 if (ret) 10926 break; 10927 ppd->remote_link_down_reason = 0; 10928 } 10929 10930 if (!dd->dc_shutdown) { 10931 ret1 = set_physical_link_state(dd, PLS_DISABLED); 10932 if (ret1 != HCMD_SUCCESS) { 10933 dd_dev_err(dd, 10934 "Failed to transition to Disabled link state, return 0x%x\n", 10935 ret1); 10936 ret = -EINVAL; 10937 break; 10938 } 10939 ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000); 10940 if (ret) { 10941 dd_dev_err(dd, 10942 "%s: physical state did not change to DISABLED\n", 10943 __func__); 10944 break; 10945 } 10946 dc_shutdown(dd); 10947 } 10948 ppd->host_link_state = HLS_DN_DISABLE; 10949 break; 10950 case HLS_DN_OFFLINE: 10951 if (ppd->host_link_state == HLS_DN_DISABLE) 10952 dc_start(dd); 10953 10954 /* allow any state to transition to offline */ 10955 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10956 if (!ret) 10957 ppd->remote_link_down_reason = 0; 10958 break; 10959 case HLS_VERIFY_CAP: 10960 if (ppd->host_link_state != HLS_DN_POLL) 10961 goto unexpected; 10962 ppd->host_link_state = HLS_VERIFY_CAP; 10963 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP); 10964 break; 10965 case HLS_GOING_UP: 10966 if (ppd->host_link_state != HLS_VERIFY_CAP) 10967 goto unexpected; 10968 10969 ret1 = set_physical_link_state(dd, PLS_LINKUP); 10970 if (ret1 != HCMD_SUCCESS) { 10971 dd_dev_err(dd, 10972 "Failed to transition to link up state, return 0x%x\n", 10973 ret1); 10974 ret = -EINVAL; 10975 break; 10976 } 10977 ppd->host_link_state = HLS_GOING_UP; 10978 break; 10979 10980 case HLS_GOING_OFFLINE: /* transient within goto_offline() */ 10981 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */ 10982 default: 10983 dd_dev_info(dd, "%s: state 0x%x: not supported\n", 10984 __func__, state); 10985 ret = -EINVAL; 10986 break; 10987 } 10988 10989 goto done; 10990 10991 unexpected: 10992 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n", 10993 __func__, link_state_name(ppd->host_link_state), 10994 link_state_name(state)); 10995 ret = -EINVAL; 10996 10997 done: 10998 mutex_unlock(&ppd->hls_lock); 10999 11000 if (event.device) 11001 ib_dispatch_event(&event); 11002 11003 return ret; 11004 } 11005 11006 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val) 11007 { 11008 u64 reg; 11009 int ret = 0; 11010 11011 switch (which) { 11012 case HFI1_IB_CFG_LIDLMC: 11013 set_lidlmc(ppd); 11014 break; 11015 case HFI1_IB_CFG_VL_HIGH_LIMIT: 11016 /* 11017 * The VL Arbitrator high limit is sent in units of 4k 11018 * bytes, while HFI stores it in units of 64 bytes. 11019 */ 11020 val *= 4096 / 64; 11021 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) 11022 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT; 11023 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); 11024 break; 11025 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 11026 /* HFI only supports POLL as the default link down state */ 11027 if (val != HLS_DN_POLL) 11028 ret = -EINVAL; 11029 break; 11030 case HFI1_IB_CFG_OP_VLS: 11031 if (ppd->vls_operational != val) { 11032 ppd->vls_operational = val; 11033 if (!ppd->port) 11034 ret = -EINVAL; 11035 } 11036 break; 11037 /* 11038 * For link width, link width downgrade, and speed enable, always AND 11039 * the setting with what is actually supported. This has two benefits. 11040 * First, enabled can't have unsupported values, no matter what the 11041 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean 11042 * "fill in with your supported value" have all the bits in the 11043 * field set, so simply ANDing with supported has the desired result. 11044 */ 11045 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */ 11046 ppd->link_width_enabled = val & ppd->link_width_supported; 11047 break; 11048 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */ 11049 ppd->link_width_downgrade_enabled = 11050 val & ppd->link_width_downgrade_supported; 11051 break; 11052 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 11053 ppd->link_speed_enabled = val & ppd->link_speed_supported; 11054 break; 11055 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 11056 /* 11057 * HFI does not follow IB specs, save this value 11058 * so we can report it, if asked. 11059 */ 11060 ppd->overrun_threshold = val; 11061 break; 11062 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 11063 /* 11064 * HFI does not follow IB specs, save this value 11065 * so we can report it, if asked. 11066 */ 11067 ppd->phy_error_threshold = val; 11068 break; 11069 11070 case HFI1_IB_CFG_MTU: 11071 set_send_length(ppd); 11072 break; 11073 11074 case HFI1_IB_CFG_PKEYS: 11075 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 11076 set_partition_keys(ppd); 11077 break; 11078 11079 default: 11080 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 11081 dd_dev_info(ppd->dd, 11082 "%s: which %s, val 0x%x: not implemented\n", 11083 __func__, ib_cfg_name(which), val); 11084 break; 11085 } 11086 return ret; 11087 } 11088 11089 /* begin functions related to vl arbitration table caching */ 11090 static void init_vl_arb_caches(struct hfi1_pportdata *ppd) 11091 { 11092 int i; 11093 11094 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 11095 VL_ARB_LOW_PRIO_TABLE_SIZE); 11096 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 11097 VL_ARB_HIGH_PRIO_TABLE_SIZE); 11098 11099 /* 11100 * Note that we always return values directly from the 11101 * 'vl_arb_cache' (and do no CSR reads) in response to a 11102 * 'Get(VLArbTable)'. This is obviously correct after a 11103 * 'Set(VLArbTable)', since the cache will then be up to 11104 * date. But it's also correct prior to any 'Set(VLArbTable)' 11105 * since then both the cache, and the relevant h/w registers 11106 * will be zeroed. 11107 */ 11108 11109 for (i = 0; i < MAX_PRIO_TABLE; i++) 11110 spin_lock_init(&ppd->vl_arb_cache[i].lock); 11111 } 11112 11113 /* 11114 * vl_arb_lock_cache 11115 * 11116 * All other vl_arb_* functions should be called only after locking 11117 * the cache. 11118 */ 11119 static inline struct vl_arb_cache * 11120 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx) 11121 { 11122 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE) 11123 return NULL; 11124 spin_lock(&ppd->vl_arb_cache[idx].lock); 11125 return &ppd->vl_arb_cache[idx]; 11126 } 11127 11128 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx) 11129 { 11130 spin_unlock(&ppd->vl_arb_cache[idx].lock); 11131 } 11132 11133 static void vl_arb_get_cache(struct vl_arb_cache *cache, 11134 struct ib_vl_weight_elem *vl) 11135 { 11136 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11137 } 11138 11139 static void vl_arb_set_cache(struct vl_arb_cache *cache, 11140 struct ib_vl_weight_elem *vl) 11141 { 11142 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11143 } 11144 11145 static int vl_arb_match_cache(struct vl_arb_cache *cache, 11146 struct ib_vl_weight_elem *vl) 11147 { 11148 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11149 } 11150 11151 /* end functions related to vl arbitration table caching */ 11152 11153 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target, 11154 u32 size, struct ib_vl_weight_elem *vl) 11155 { 11156 struct hfi1_devdata *dd = ppd->dd; 11157 u64 reg; 11158 unsigned int i, is_up = 0; 11159 int drain, ret = 0; 11160 11161 mutex_lock(&ppd->hls_lock); 11162 11163 if (ppd->host_link_state & HLS_UP) 11164 is_up = 1; 11165 11166 drain = !is_ax(dd) && is_up; 11167 11168 if (drain) 11169 /* 11170 * Before adjusting VL arbitration weights, empty per-VL 11171 * FIFOs, otherwise a packet whose VL weight is being 11172 * set to 0 could get stuck in a FIFO with no chance to 11173 * egress. 11174 */ 11175 ret = stop_drain_data_vls(dd); 11176 11177 if (ret) { 11178 dd_dev_err( 11179 dd, 11180 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n", 11181 __func__); 11182 goto err; 11183 } 11184 11185 for (i = 0; i < size; i++, vl++) { 11186 /* 11187 * NOTE: The low priority shift and mask are used here, but 11188 * they are the same for both the low and high registers. 11189 */ 11190 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK) 11191 << SEND_LOW_PRIORITY_LIST_VL_SHIFT) 11192 | (((u64)vl->weight 11193 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK) 11194 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT); 11195 write_csr(dd, target + (i * 8), reg); 11196 } 11197 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE); 11198 11199 if (drain) 11200 open_fill_data_vls(dd); /* reopen all VLs */ 11201 11202 err: 11203 mutex_unlock(&ppd->hls_lock); 11204 11205 return ret; 11206 } 11207 11208 /* 11209 * Read one credit merge VL register. 11210 */ 11211 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr, 11212 struct vl_limit *vll) 11213 { 11214 u64 reg = read_csr(dd, csr); 11215 11216 vll->dedicated = cpu_to_be16( 11217 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT) 11218 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK); 11219 vll->shared = cpu_to_be16( 11220 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT) 11221 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK); 11222 } 11223 11224 /* 11225 * Read the current credit merge limits. 11226 */ 11227 static int get_buffer_control(struct hfi1_devdata *dd, 11228 struct buffer_control *bc, u16 *overall_limit) 11229 { 11230 u64 reg; 11231 int i; 11232 11233 /* not all entries are filled in */ 11234 memset(bc, 0, sizeof(*bc)); 11235 11236 /* OPA and HFI have a 1-1 mapping */ 11237 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11238 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]); 11239 11240 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */ 11241 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]); 11242 11243 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11244 bc->overall_shared_limit = cpu_to_be16( 11245 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) 11246 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK); 11247 if (overall_limit) 11248 *overall_limit = (reg 11249 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) 11250 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK; 11251 return sizeof(struct buffer_control); 11252 } 11253 11254 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11255 { 11256 u64 reg; 11257 int i; 11258 11259 /* each register contains 16 SC->VLnt mappings, 4 bits each */ 11260 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); 11261 for (i = 0; i < sizeof(u64); i++) { 11262 u8 byte = *(((u8 *)®) + i); 11263 11264 dp->vlnt[2 * i] = byte & 0xf; 11265 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4; 11266 } 11267 11268 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); 11269 for (i = 0; i < sizeof(u64); i++) { 11270 u8 byte = *(((u8 *)®) + i); 11271 11272 dp->vlnt[16 + (2 * i)] = byte & 0xf; 11273 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4; 11274 } 11275 return sizeof(struct sc2vlnt); 11276 } 11277 11278 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems, 11279 struct ib_vl_weight_elem *vl) 11280 { 11281 unsigned int i; 11282 11283 for (i = 0; i < nelems; i++, vl++) { 11284 vl->vl = 0xf; 11285 vl->weight = 0; 11286 } 11287 } 11288 11289 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11290 { 11291 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, 11292 DC_SC_VL_VAL(15_0, 11293 0, dp->vlnt[0] & 0xf, 11294 1, dp->vlnt[1] & 0xf, 11295 2, dp->vlnt[2] & 0xf, 11296 3, dp->vlnt[3] & 0xf, 11297 4, dp->vlnt[4] & 0xf, 11298 5, dp->vlnt[5] & 0xf, 11299 6, dp->vlnt[6] & 0xf, 11300 7, dp->vlnt[7] & 0xf, 11301 8, dp->vlnt[8] & 0xf, 11302 9, dp->vlnt[9] & 0xf, 11303 10, dp->vlnt[10] & 0xf, 11304 11, dp->vlnt[11] & 0xf, 11305 12, dp->vlnt[12] & 0xf, 11306 13, dp->vlnt[13] & 0xf, 11307 14, dp->vlnt[14] & 0xf, 11308 15, dp->vlnt[15] & 0xf)); 11309 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, 11310 DC_SC_VL_VAL(31_16, 11311 16, dp->vlnt[16] & 0xf, 11312 17, dp->vlnt[17] & 0xf, 11313 18, dp->vlnt[18] & 0xf, 11314 19, dp->vlnt[19] & 0xf, 11315 20, dp->vlnt[20] & 0xf, 11316 21, dp->vlnt[21] & 0xf, 11317 22, dp->vlnt[22] & 0xf, 11318 23, dp->vlnt[23] & 0xf, 11319 24, dp->vlnt[24] & 0xf, 11320 25, dp->vlnt[25] & 0xf, 11321 26, dp->vlnt[26] & 0xf, 11322 27, dp->vlnt[27] & 0xf, 11323 28, dp->vlnt[28] & 0xf, 11324 29, dp->vlnt[29] & 0xf, 11325 30, dp->vlnt[30] & 0xf, 11326 31, dp->vlnt[31] & 0xf)); 11327 } 11328 11329 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what, 11330 u16 limit) 11331 { 11332 if (limit != 0) 11333 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n", 11334 what, (int)limit, idx); 11335 } 11336 11337 /* change only the shared limit portion of SendCmGLobalCredit */ 11338 static void set_global_shared(struct hfi1_devdata *dd, u16 limit) 11339 { 11340 u64 reg; 11341 11342 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11343 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK; 11344 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT; 11345 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11346 } 11347 11348 /* change only the total credit limit portion of SendCmGLobalCredit */ 11349 static void set_global_limit(struct hfi1_devdata *dd, u16 limit) 11350 { 11351 u64 reg; 11352 11353 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11354 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK; 11355 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 11356 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11357 } 11358 11359 /* set the given per-VL shared limit */ 11360 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit) 11361 { 11362 u64 reg; 11363 u32 addr; 11364 11365 if (vl < TXE_NUM_DATA_VL) 11366 addr = SEND_CM_CREDIT_VL + (8 * vl); 11367 else 11368 addr = SEND_CM_CREDIT_VL15; 11369 11370 reg = read_csr(dd, addr); 11371 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK; 11372 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT; 11373 write_csr(dd, addr, reg); 11374 } 11375 11376 /* set the given per-VL dedicated limit */ 11377 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit) 11378 { 11379 u64 reg; 11380 u32 addr; 11381 11382 if (vl < TXE_NUM_DATA_VL) 11383 addr = SEND_CM_CREDIT_VL + (8 * vl); 11384 else 11385 addr = SEND_CM_CREDIT_VL15; 11386 11387 reg = read_csr(dd, addr); 11388 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK; 11389 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT; 11390 write_csr(dd, addr, reg); 11391 } 11392 11393 /* spin until the given per-VL status mask bits clear */ 11394 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask, 11395 const char *which) 11396 { 11397 unsigned long timeout; 11398 u64 reg; 11399 11400 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT); 11401 while (1) { 11402 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; 11403 11404 if (reg == 0) 11405 return; /* success */ 11406 if (time_after(jiffies, timeout)) 11407 break; /* timed out */ 11408 udelay(1); 11409 } 11410 11411 dd_dev_err(dd, 11412 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n", 11413 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); 11414 /* 11415 * If this occurs, it is likely there was a credit loss on the link. 11416 * The only recovery from that is a link bounce. 11417 */ 11418 dd_dev_err(dd, 11419 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n"); 11420 } 11421 11422 /* 11423 * The number of credits on the VLs may be changed while everything 11424 * is "live", but the following algorithm must be followed due to 11425 * how the hardware is actually implemented. In particular, 11426 * Return_Credit_Status[] is the only correct status check. 11427 * 11428 * if (reducing Global_Shared_Credit_Limit or any shared limit changing) 11429 * set Global_Shared_Credit_Limit = 0 11430 * use_all_vl = 1 11431 * mask0 = all VLs that are changing either dedicated or shared limits 11432 * set Shared_Limit[mask0] = 0 11433 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0 11434 * if (changing any dedicated limit) 11435 * mask1 = all VLs that are lowering dedicated limits 11436 * lower Dedicated_Limit[mask1] 11437 * spin until Return_Credit_Status[mask1] == 0 11438 * raise Dedicated_Limits 11439 * raise Shared_Limits 11440 * raise Global_Shared_Credit_Limit 11441 * 11442 * lower = if the new limit is lower, set the limit to the new value 11443 * raise = if the new limit is higher than the current value (may be changed 11444 * earlier in the algorithm), set the new limit to the new value 11445 */ 11446 int set_buffer_control(struct hfi1_pportdata *ppd, 11447 struct buffer_control *new_bc) 11448 { 11449 struct hfi1_devdata *dd = ppd->dd; 11450 u64 changing_mask, ld_mask, stat_mask; 11451 int change_count; 11452 int i, use_all_mask; 11453 int this_shared_changing; 11454 int vl_count = 0, ret; 11455 /* 11456 * A0: add the variable any_shared_limit_changing below and in the 11457 * algorithm above. If removing A0 support, it can be removed. 11458 */ 11459 int any_shared_limit_changing; 11460 struct buffer_control cur_bc; 11461 u8 changing[OPA_MAX_VLS]; 11462 u8 lowering_dedicated[OPA_MAX_VLS]; 11463 u16 cur_total; 11464 u32 new_total = 0; 11465 const u64 all_mask = 11466 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK 11467 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK 11468 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK 11469 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK 11470 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK 11471 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK 11472 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK 11473 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK 11474 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK; 11475 11476 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15) 11477 #define NUM_USABLE_VLS 16 /* look at VL15 and less */ 11478 11479 /* find the new total credits, do sanity check on unused VLs */ 11480 for (i = 0; i < OPA_MAX_VLS; i++) { 11481 if (valid_vl(i)) { 11482 new_total += be16_to_cpu(new_bc->vl[i].dedicated); 11483 continue; 11484 } 11485 nonzero_msg(dd, i, "dedicated", 11486 be16_to_cpu(new_bc->vl[i].dedicated)); 11487 nonzero_msg(dd, i, "shared", 11488 be16_to_cpu(new_bc->vl[i].shared)); 11489 new_bc->vl[i].dedicated = 0; 11490 new_bc->vl[i].shared = 0; 11491 } 11492 new_total += be16_to_cpu(new_bc->overall_shared_limit); 11493 11494 /* fetch the current values */ 11495 get_buffer_control(dd, &cur_bc, &cur_total); 11496 11497 /* 11498 * Create the masks we will use. 11499 */ 11500 memset(changing, 0, sizeof(changing)); 11501 memset(lowering_dedicated, 0, sizeof(lowering_dedicated)); 11502 /* 11503 * NOTE: Assumes that the individual VL bits are adjacent and in 11504 * increasing order 11505 */ 11506 stat_mask = 11507 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK; 11508 changing_mask = 0; 11509 ld_mask = 0; 11510 change_count = 0; 11511 any_shared_limit_changing = 0; 11512 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) { 11513 if (!valid_vl(i)) 11514 continue; 11515 this_shared_changing = new_bc->vl[i].shared 11516 != cur_bc.vl[i].shared; 11517 if (this_shared_changing) 11518 any_shared_limit_changing = 1; 11519 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated || 11520 this_shared_changing) { 11521 changing[i] = 1; 11522 changing_mask |= stat_mask; 11523 change_count++; 11524 } 11525 if (be16_to_cpu(new_bc->vl[i].dedicated) < 11526 be16_to_cpu(cur_bc.vl[i].dedicated)) { 11527 lowering_dedicated[i] = 1; 11528 ld_mask |= stat_mask; 11529 } 11530 } 11531 11532 /* bracket the credit change with a total adjustment */ 11533 if (new_total > cur_total) 11534 set_global_limit(dd, new_total); 11535 11536 /* 11537 * Start the credit change algorithm. 11538 */ 11539 use_all_mask = 0; 11540 if ((be16_to_cpu(new_bc->overall_shared_limit) < 11541 be16_to_cpu(cur_bc.overall_shared_limit)) || 11542 (is_ax(dd) && any_shared_limit_changing)) { 11543 set_global_shared(dd, 0); 11544 cur_bc.overall_shared_limit = 0; 11545 use_all_mask = 1; 11546 } 11547 11548 for (i = 0; i < NUM_USABLE_VLS; i++) { 11549 if (!valid_vl(i)) 11550 continue; 11551 11552 if (changing[i]) { 11553 set_vl_shared(dd, i, 0); 11554 cur_bc.vl[i].shared = 0; 11555 } 11556 } 11557 11558 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask, 11559 "shared"); 11560 11561 if (change_count > 0) { 11562 for (i = 0; i < NUM_USABLE_VLS; i++) { 11563 if (!valid_vl(i)) 11564 continue; 11565 11566 if (lowering_dedicated[i]) { 11567 set_vl_dedicated(dd, i, 11568 be16_to_cpu(new_bc-> 11569 vl[i].dedicated)); 11570 cur_bc.vl[i].dedicated = 11571 new_bc->vl[i].dedicated; 11572 } 11573 } 11574 11575 wait_for_vl_status_clear(dd, ld_mask, "dedicated"); 11576 11577 /* now raise all dedicated that are going up */ 11578 for (i = 0; i < NUM_USABLE_VLS; i++) { 11579 if (!valid_vl(i)) 11580 continue; 11581 11582 if (be16_to_cpu(new_bc->vl[i].dedicated) > 11583 be16_to_cpu(cur_bc.vl[i].dedicated)) 11584 set_vl_dedicated(dd, i, 11585 be16_to_cpu(new_bc-> 11586 vl[i].dedicated)); 11587 } 11588 } 11589 11590 /* next raise all shared that are going up */ 11591 for (i = 0; i < NUM_USABLE_VLS; i++) { 11592 if (!valid_vl(i)) 11593 continue; 11594 11595 if (be16_to_cpu(new_bc->vl[i].shared) > 11596 be16_to_cpu(cur_bc.vl[i].shared)) 11597 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared)); 11598 } 11599 11600 /* finally raise the global shared */ 11601 if (be16_to_cpu(new_bc->overall_shared_limit) > 11602 be16_to_cpu(cur_bc.overall_shared_limit)) 11603 set_global_shared(dd, 11604 be16_to_cpu(new_bc->overall_shared_limit)); 11605 11606 /* bracket the credit change with a total adjustment */ 11607 if (new_total < cur_total) 11608 set_global_limit(dd, new_total); 11609 11610 /* 11611 * Determine the actual number of operational VLS using the number of 11612 * dedicated and shared credits for each VL. 11613 */ 11614 if (change_count > 0) { 11615 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11616 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 || 11617 be16_to_cpu(new_bc->vl[i].shared) > 0) 11618 vl_count++; 11619 ppd->actual_vls_operational = vl_count; 11620 ret = sdma_map_init(dd, ppd->port - 1, vl_count ? 11621 ppd->actual_vls_operational : 11622 ppd->vls_operational, 11623 NULL); 11624 if (ret == 0) 11625 ret = pio_map_init(dd, ppd->port - 1, vl_count ? 11626 ppd->actual_vls_operational : 11627 ppd->vls_operational, NULL); 11628 if (ret) 11629 return ret; 11630 } 11631 return 0; 11632 } 11633 11634 /* 11635 * Read the given fabric manager table. Return the size of the 11636 * table (in bytes) on success, and a negative error code on 11637 * failure. 11638 */ 11639 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t) 11640 11641 { 11642 int size; 11643 struct vl_arb_cache *vlc; 11644 11645 switch (which) { 11646 case FM_TBL_VL_HIGH_ARB: 11647 size = 256; 11648 /* 11649 * OPA specifies 128 elements (of 2 bytes each), though 11650 * HFI supports only 16 elements in h/w. 11651 */ 11652 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11653 vl_arb_get_cache(vlc, t); 11654 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11655 break; 11656 case FM_TBL_VL_LOW_ARB: 11657 size = 256; 11658 /* 11659 * OPA specifies 128 elements (of 2 bytes each), though 11660 * HFI supports only 16 elements in h/w. 11661 */ 11662 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11663 vl_arb_get_cache(vlc, t); 11664 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11665 break; 11666 case FM_TBL_BUFFER_CONTROL: 11667 size = get_buffer_control(ppd->dd, t, NULL); 11668 break; 11669 case FM_TBL_SC2VLNT: 11670 size = get_sc2vlnt(ppd->dd, t); 11671 break; 11672 case FM_TBL_VL_PREEMPT_ELEMS: 11673 size = 256; 11674 /* OPA specifies 128 elements, of 2 bytes each */ 11675 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t); 11676 break; 11677 case FM_TBL_VL_PREEMPT_MATRIX: 11678 size = 256; 11679 /* 11680 * OPA specifies that this is the same size as the VL 11681 * arbitration tables (i.e., 256 bytes). 11682 */ 11683 break; 11684 default: 11685 return -EINVAL; 11686 } 11687 return size; 11688 } 11689 11690 /* 11691 * Write the given fabric manager table. 11692 */ 11693 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t) 11694 { 11695 int ret = 0; 11696 struct vl_arb_cache *vlc; 11697 11698 switch (which) { 11699 case FM_TBL_VL_HIGH_ARB: 11700 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11701 if (vl_arb_match_cache(vlc, t)) { 11702 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11703 break; 11704 } 11705 vl_arb_set_cache(vlc, t); 11706 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11707 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST, 11708 VL_ARB_HIGH_PRIO_TABLE_SIZE, t); 11709 break; 11710 case FM_TBL_VL_LOW_ARB: 11711 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11712 if (vl_arb_match_cache(vlc, t)) { 11713 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11714 break; 11715 } 11716 vl_arb_set_cache(vlc, t); 11717 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11718 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST, 11719 VL_ARB_LOW_PRIO_TABLE_SIZE, t); 11720 break; 11721 case FM_TBL_BUFFER_CONTROL: 11722 ret = set_buffer_control(ppd, t); 11723 break; 11724 case FM_TBL_SC2VLNT: 11725 set_sc2vlnt(ppd->dd, t); 11726 break; 11727 default: 11728 ret = -EINVAL; 11729 } 11730 return ret; 11731 } 11732 11733 /* 11734 * Disable all data VLs. 11735 * 11736 * Return 0 if disabled, non-zero if the VLs cannot be disabled. 11737 */ 11738 static int disable_data_vls(struct hfi1_devdata *dd) 11739 { 11740 if (is_ax(dd)) 11741 return 1; 11742 11743 pio_send_control(dd, PSC_DATA_VL_DISABLE); 11744 11745 return 0; 11746 } 11747 11748 /* 11749 * open_fill_data_vls() - the counterpart to stop_drain_data_vls(). 11750 * Just re-enables all data VLs (the "fill" part happens 11751 * automatically - the name was chosen for symmetry with 11752 * stop_drain_data_vls()). 11753 * 11754 * Return 0 if successful, non-zero if the VLs cannot be enabled. 11755 */ 11756 int open_fill_data_vls(struct hfi1_devdata *dd) 11757 { 11758 if (is_ax(dd)) 11759 return 1; 11760 11761 pio_send_control(dd, PSC_DATA_VL_ENABLE); 11762 11763 return 0; 11764 } 11765 11766 /* 11767 * drain_data_vls() - assumes that disable_data_vls() has been called, 11768 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA 11769 * engines to drop to 0. 11770 */ 11771 static void drain_data_vls(struct hfi1_devdata *dd) 11772 { 11773 sc_wait(dd); 11774 sdma_wait(dd); 11775 pause_for_credit_return(dd); 11776 } 11777 11778 /* 11779 * stop_drain_data_vls() - disable, then drain all per-VL fifos. 11780 * 11781 * Use open_fill_data_vls() to resume using data VLs. This pair is 11782 * meant to be used like this: 11783 * 11784 * stop_drain_data_vls(dd); 11785 * // do things with per-VL resources 11786 * open_fill_data_vls(dd); 11787 */ 11788 int stop_drain_data_vls(struct hfi1_devdata *dd) 11789 { 11790 int ret; 11791 11792 ret = disable_data_vls(dd); 11793 if (ret == 0) 11794 drain_data_vls(dd); 11795 11796 return ret; 11797 } 11798 11799 /* 11800 * Convert a nanosecond time to a cclock count. No matter how slow 11801 * the cclock, a non-zero ns will always have a non-zero result. 11802 */ 11803 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns) 11804 { 11805 u32 cclocks; 11806 11807 if (dd->icode == ICODE_FPGA_EMULATION) 11808 cclocks = (ns * 1000) / FPGA_CCLOCK_PS; 11809 else /* simulation pretends to be ASIC */ 11810 cclocks = (ns * 1000) / ASIC_CCLOCK_PS; 11811 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */ 11812 cclocks = 1; 11813 return cclocks; 11814 } 11815 11816 /* 11817 * Convert a cclock count to nanoseconds. Not matter how slow 11818 * the cclock, a non-zero cclocks will always have a non-zero result. 11819 */ 11820 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks) 11821 { 11822 u32 ns; 11823 11824 if (dd->icode == ICODE_FPGA_EMULATION) 11825 ns = (cclocks * FPGA_CCLOCK_PS) / 1000; 11826 else /* simulation pretends to be ASIC */ 11827 ns = (cclocks * ASIC_CCLOCK_PS) / 1000; 11828 if (cclocks && !ns) 11829 ns = 1; 11830 return ns; 11831 } 11832 11833 /* 11834 * Dynamically adjust the receive interrupt timeout for a context based on 11835 * incoming packet rate. 11836 * 11837 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero. 11838 */ 11839 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts) 11840 { 11841 struct hfi1_devdata *dd = rcd->dd; 11842 u32 timeout = rcd->rcvavail_timeout; 11843 11844 /* 11845 * This algorithm doubles or halves the timeout depending on whether 11846 * the number of packets received in this interrupt were less than or 11847 * greater equal the interrupt count. 11848 * 11849 * The calculations below do not allow a steady state to be achieved. 11850 * Only at the endpoints it is possible to have an unchanging 11851 * timeout. 11852 */ 11853 if (npkts < rcv_intr_count) { 11854 /* 11855 * Not enough packets arrived before the timeout, adjust 11856 * timeout downward. 11857 */ 11858 if (timeout < 2) /* already at minimum? */ 11859 return; 11860 timeout >>= 1; 11861 } else { 11862 /* 11863 * More than enough packets arrived before the timeout, adjust 11864 * timeout upward. 11865 */ 11866 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */ 11867 return; 11868 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr); 11869 } 11870 11871 rcd->rcvavail_timeout = timeout; 11872 /* 11873 * timeout cannot be larger than rcv_intr_timeout_csr which has already 11874 * been verified to be in range 11875 */ 11876 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT, 11877 (u64)timeout << 11878 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11879 } 11880 11881 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, 11882 u32 intr_adjust, u32 npkts) 11883 { 11884 struct hfi1_devdata *dd = rcd->dd; 11885 u64 reg; 11886 u32 ctxt = rcd->ctxt; 11887 11888 /* 11889 * Need to write timeout register before updating RcvHdrHead to ensure 11890 * that a new value is used when the HW decides to restart counting. 11891 */ 11892 if (intr_adjust) 11893 adjust_rcv_timeout(rcd, npkts); 11894 if (updegr) { 11895 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK) 11896 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT; 11897 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg); 11898 } 11899 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) | 11900 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK) 11901 << RCV_HDR_HEAD_HEAD_SHIFT); 11902 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11903 } 11904 11905 u32 hdrqempty(struct hfi1_ctxtdata *rcd) 11906 { 11907 u32 head, tail; 11908 11909 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD) 11910 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT; 11911 11912 if (hfi1_rcvhdrtail_kvaddr(rcd)) 11913 tail = get_rcvhdrtail(rcd); 11914 else 11915 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 11916 11917 return head == tail; 11918 } 11919 11920 /* 11921 * Context Control and Receive Array encoding for buffer size: 11922 * 0x0 invalid 11923 * 0x1 4 KB 11924 * 0x2 8 KB 11925 * 0x3 16 KB 11926 * 0x4 32 KB 11927 * 0x5 64 KB 11928 * 0x6 128 KB 11929 * 0x7 256 KB 11930 * 0x8 512 KB (Receive Array only) 11931 * 0x9 1 MB (Receive Array only) 11932 * 0xa 2 MB (Receive Array only) 11933 * 11934 * 0xB-0xF - reserved (Receive Array only) 11935 * 11936 * 11937 * This routine assumes that the value has already been sanity checked. 11938 */ 11939 static u32 encoded_size(u32 size) 11940 { 11941 switch (size) { 11942 case 4 * 1024: return 0x1; 11943 case 8 * 1024: return 0x2; 11944 case 16 * 1024: return 0x3; 11945 case 32 * 1024: return 0x4; 11946 case 64 * 1024: return 0x5; 11947 case 128 * 1024: return 0x6; 11948 case 256 * 1024: return 0x7; 11949 case 512 * 1024: return 0x8; 11950 case 1 * 1024 * 1024: return 0x9; 11951 case 2 * 1024 * 1024: return 0xa; 11952 } 11953 return 0x1; /* if invalid, go with the minimum size */ 11954 } 11955 11956 /** 11957 * encode_rcv_header_entry_size - return chip specific encoding for size 11958 * @size: size in dwords 11959 * 11960 * Convert a receive header entry size that to the encoding used in the CSR. 11961 * 11962 * Return a zero if the given size is invalid, otherwise the encoding. 11963 */ 11964 u8 encode_rcv_header_entry_size(u8 size) 11965 { 11966 /* there are only 3 valid receive header entry sizes */ 11967 if (size == 2) 11968 return 1; 11969 if (size == 16) 11970 return 2; 11971 if (size == 32) 11972 return 4; 11973 return 0; /* invalid */ 11974 } 11975 11976 /** 11977 * hfi1_validate_rcvhdrcnt - validate hdrcnt 11978 * @dd: the device data 11979 * @thecnt: the header count 11980 */ 11981 int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt) 11982 { 11983 if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { 11984 dd_dev_err(dd, "Receive header queue count too small\n"); 11985 return -EINVAL; 11986 } 11987 11988 if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) { 11989 dd_dev_err(dd, 11990 "Receive header queue count cannot be greater than %u\n", 11991 HFI1_MAX_HDRQ_EGRBUF_CNT); 11992 return -EINVAL; 11993 } 11994 11995 if (thecnt % HDRQ_INCREMENT) { 11996 dd_dev_err(dd, "Receive header queue count %d must be divisible by %lu\n", 11997 thecnt, HDRQ_INCREMENT); 11998 return -EINVAL; 11999 } 12000 12001 return 0; 12002 } 12003 12004 /** 12005 * set_hdrq_regs - set header queue registers for context 12006 * @dd: the device data 12007 * @ctxt: the context 12008 * @entsize: the dword entry size 12009 * @hdrcnt: the number of header entries 12010 */ 12011 void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt) 12012 { 12013 u64 reg; 12014 12015 reg = (((u64)hdrcnt >> HDRQ_SIZE_SHIFT) & RCV_HDR_CNT_CNT_MASK) << 12016 RCV_HDR_CNT_CNT_SHIFT; 12017 write_kctxt_csr(dd, ctxt, RCV_HDR_CNT, reg); 12018 reg = ((u64)encode_rcv_header_entry_size(entsize) & 12019 RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) << 12020 RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT; 12021 write_kctxt_csr(dd, ctxt, RCV_HDR_ENT_SIZE, reg); 12022 reg = ((u64)DEFAULT_RCVHDRSIZE & RCV_HDR_SIZE_HDR_SIZE_MASK) << 12023 RCV_HDR_SIZE_HDR_SIZE_SHIFT; 12024 write_kctxt_csr(dd, ctxt, RCV_HDR_SIZE, reg); 12025 12026 /* 12027 * Program dummy tail address for every receive context 12028 * before enabling any receive context 12029 */ 12030 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12031 dd->rcvhdrtail_dummy_dma); 12032 } 12033 12034 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, 12035 struct hfi1_ctxtdata *rcd) 12036 { 12037 u64 rcvctrl, reg; 12038 int did_enable = 0; 12039 u16 ctxt; 12040 12041 if (!rcd) 12042 return; 12043 12044 ctxt = rcd->ctxt; 12045 12046 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op); 12047 12048 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL); 12049 /* if the context already enabled, don't do the extra steps */ 12050 if ((op & HFI1_RCVCTRL_CTXT_ENB) && 12051 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) { 12052 /* reset the tail and hdr addresses, and sequence count */ 12053 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR, 12054 rcd->rcvhdrq_dma); 12055 if (hfi1_rcvhdrtail_kvaddr(rcd)) 12056 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12057 rcd->rcvhdrqtailaddr_dma); 12058 hfi1_set_seq_cnt(rcd, 1); 12059 12060 /* reset the cached receive header queue head value */ 12061 hfi1_set_rcd_head(rcd, 0); 12062 12063 /* 12064 * Zero the receive header queue so we don't get false 12065 * positives when checking the sequence number. The 12066 * sequence numbers could land exactly on the same spot. 12067 * E.g. a rcd restart before the receive header wrapped. 12068 */ 12069 memset(rcd->rcvhdrq, 0, rcvhdrq_size(rcd)); 12070 12071 /* starting timeout */ 12072 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr; 12073 12074 /* enable the context */ 12075 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK; 12076 12077 /* clean the egr buffer size first */ 12078 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 12079 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size) 12080 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK) 12081 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT; 12082 12083 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */ 12084 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0); 12085 did_enable = 1; 12086 12087 /* zero RcvEgrIndexHead */ 12088 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0); 12089 12090 /* set eager count and base index */ 12091 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT) 12092 & RCV_EGR_CTRL_EGR_CNT_MASK) 12093 << RCV_EGR_CTRL_EGR_CNT_SHIFT) | 12094 (((rcd->eager_base >> RCV_SHIFT) 12095 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK) 12096 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT); 12097 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg); 12098 12099 /* 12100 * Set TID (expected) count and base index. 12101 * rcd->expected_count is set to individual RcvArray entries, 12102 * not pairs, and the CSR takes a pair-count in groups of 12103 * four, so divide by 8. 12104 */ 12105 reg = (((rcd->expected_count >> RCV_SHIFT) 12106 & RCV_TID_CTRL_TID_PAIR_CNT_MASK) 12107 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) | 12108 (((rcd->expected_base >> RCV_SHIFT) 12109 & RCV_TID_CTRL_TID_BASE_INDEX_MASK) 12110 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT); 12111 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg); 12112 if (ctxt == HFI1_CTRL_CTXT) 12113 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); 12114 } 12115 if (op & HFI1_RCVCTRL_CTXT_DIS) { 12116 write_csr(dd, RCV_VL15, 0); 12117 /* 12118 * When receive context is being disabled turn on tail 12119 * update with a dummy tail address and then disable 12120 * receive context. 12121 */ 12122 if (dd->rcvhdrtail_dummy_dma) { 12123 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12124 dd->rcvhdrtail_dummy_dma); 12125 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */ 12126 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 12127 } 12128 12129 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK; 12130 } 12131 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB) { 12132 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt, 12133 IS_RCVAVAIL_START + rcd->ctxt, true); 12134 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 12135 } 12136 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS) { 12137 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt, 12138 IS_RCVAVAIL_START + rcd->ctxt, false); 12139 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 12140 } 12141 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && hfi1_rcvhdrtail_kvaddr(rcd)) 12142 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 12143 if (op & HFI1_RCVCTRL_TAILUPD_DIS) { 12144 /* See comment on RcvCtxtCtrl.TailUpd above */ 12145 if (!(op & HFI1_RCVCTRL_CTXT_DIS)) 12146 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK; 12147 } 12148 if (op & HFI1_RCVCTRL_TIDFLOW_ENB) 12149 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 12150 if (op & HFI1_RCVCTRL_TIDFLOW_DIS) 12151 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 12152 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) { 12153 /* 12154 * In one-packet-per-eager mode, the size comes from 12155 * the RcvArray entry. 12156 */ 12157 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 12158 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 12159 } 12160 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS) 12161 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 12162 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB) 12163 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 12164 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS) 12165 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 12166 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB) 12167 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 12168 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS) 12169 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 12170 if (op & HFI1_RCVCTRL_URGENT_ENB) 12171 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt, 12172 IS_RCVURGENT_START + rcd->ctxt, true); 12173 if (op & HFI1_RCVCTRL_URGENT_DIS) 12174 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt, 12175 IS_RCVURGENT_START + rcd->ctxt, false); 12176 12177 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl); 12178 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcvctrl); 12179 12180 /* work around sticky RcvCtxtStatus.BlockedRHQFull */ 12181 if (did_enable && 12182 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) { 12183 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 12184 if (reg != 0) { 12185 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n", 12186 ctxt, reg); 12187 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 12188 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10); 12189 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00); 12190 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 12191 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 12192 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n", 12193 ctxt, reg, reg == 0 ? "not" : "still"); 12194 } 12195 } 12196 12197 if (did_enable) { 12198 /* 12199 * The interrupt timeout and count must be set after 12200 * the context is enabled to take effect. 12201 */ 12202 /* set interrupt timeout */ 12203 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT, 12204 (u64)rcd->rcvavail_timeout << 12205 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 12206 12207 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */ 12208 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT; 12209 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 12210 } 12211 12212 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS)) 12213 /* 12214 * If the context has been disabled and the Tail Update has 12215 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address 12216 * so it doesn't contain an address that is invalid. 12217 */ 12218 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12219 dd->rcvhdrtail_dummy_dma); 12220 } 12221 12222 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp) 12223 { 12224 int ret; 12225 u64 val = 0; 12226 12227 if (namep) { 12228 ret = dd->cntrnameslen; 12229 *namep = dd->cntrnames; 12230 } else { 12231 const struct cntr_entry *entry; 12232 int i, j; 12233 12234 ret = (dd->ndevcntrs) * sizeof(u64); 12235 12236 /* Get the start of the block of counters */ 12237 *cntrp = dd->cntrs; 12238 12239 /* 12240 * Now go and fill in each counter in the block. 12241 */ 12242 for (i = 0; i < DEV_CNTR_LAST; i++) { 12243 entry = &dev_cntrs[i]; 12244 hfi1_cdbg(CNTR, "reading %s", entry->name); 12245 if (entry->flags & CNTR_DISABLED) { 12246 /* Nothing */ 12247 hfi1_cdbg(CNTR, "\tDisabled\n"); 12248 } else { 12249 if (entry->flags & CNTR_VL) { 12250 hfi1_cdbg(CNTR, "\tPer VL\n"); 12251 for (j = 0; j < C_VL_COUNT; j++) { 12252 val = entry->rw_cntr(entry, 12253 dd, j, 12254 CNTR_MODE_R, 12255 0); 12256 hfi1_cdbg( 12257 CNTR, 12258 "\t\tRead 0x%llx for %d\n", 12259 val, j); 12260 dd->cntrs[entry->offset + j] = 12261 val; 12262 } 12263 } else if (entry->flags & CNTR_SDMA) { 12264 hfi1_cdbg(CNTR, 12265 "\t Per SDMA Engine\n"); 12266 for (j = 0; j < chip_sdma_engines(dd); 12267 j++) { 12268 val = 12269 entry->rw_cntr(entry, dd, j, 12270 CNTR_MODE_R, 0); 12271 hfi1_cdbg(CNTR, 12272 "\t\tRead 0x%llx for %d\n", 12273 val, j); 12274 dd->cntrs[entry->offset + j] = 12275 val; 12276 } 12277 } else { 12278 val = entry->rw_cntr(entry, dd, 12279 CNTR_INVALID_VL, 12280 CNTR_MODE_R, 0); 12281 dd->cntrs[entry->offset] = val; 12282 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12283 } 12284 } 12285 } 12286 } 12287 return ret; 12288 } 12289 12290 /* 12291 * Used by sysfs to create files for hfi stats to read 12292 */ 12293 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp) 12294 { 12295 int ret; 12296 u64 val = 0; 12297 12298 if (namep) { 12299 ret = ppd->dd->portcntrnameslen; 12300 *namep = ppd->dd->portcntrnames; 12301 } else { 12302 const struct cntr_entry *entry; 12303 int i, j; 12304 12305 ret = ppd->dd->nportcntrs * sizeof(u64); 12306 *cntrp = ppd->cntrs; 12307 12308 for (i = 0; i < PORT_CNTR_LAST; i++) { 12309 entry = &port_cntrs[i]; 12310 hfi1_cdbg(CNTR, "reading %s", entry->name); 12311 if (entry->flags & CNTR_DISABLED) { 12312 /* Nothing */ 12313 hfi1_cdbg(CNTR, "\tDisabled\n"); 12314 continue; 12315 } 12316 12317 if (entry->flags & CNTR_VL) { 12318 hfi1_cdbg(CNTR, "\tPer VL"); 12319 for (j = 0; j < C_VL_COUNT; j++) { 12320 val = entry->rw_cntr(entry, ppd, j, 12321 CNTR_MODE_R, 12322 0); 12323 hfi1_cdbg( 12324 CNTR, 12325 "\t\tRead 0x%llx for %d", 12326 val, j); 12327 ppd->cntrs[entry->offset + j] = val; 12328 } 12329 } else { 12330 val = entry->rw_cntr(entry, ppd, 12331 CNTR_INVALID_VL, 12332 CNTR_MODE_R, 12333 0); 12334 ppd->cntrs[entry->offset] = val; 12335 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12336 } 12337 } 12338 } 12339 return ret; 12340 } 12341 12342 static void free_cntrs(struct hfi1_devdata *dd) 12343 { 12344 struct hfi1_pportdata *ppd; 12345 int i; 12346 12347 if (dd->synth_stats_timer.function) 12348 del_timer_sync(&dd->synth_stats_timer); 12349 ppd = (struct hfi1_pportdata *)(dd + 1); 12350 for (i = 0; i < dd->num_pports; i++, ppd++) { 12351 kfree(ppd->cntrs); 12352 kfree(ppd->scntrs); 12353 free_percpu(ppd->ibport_data.rvp.rc_acks); 12354 free_percpu(ppd->ibport_data.rvp.rc_qacks); 12355 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp); 12356 ppd->cntrs = NULL; 12357 ppd->scntrs = NULL; 12358 ppd->ibport_data.rvp.rc_acks = NULL; 12359 ppd->ibport_data.rvp.rc_qacks = NULL; 12360 ppd->ibport_data.rvp.rc_delayed_comp = NULL; 12361 } 12362 kfree(dd->portcntrnames); 12363 dd->portcntrnames = NULL; 12364 kfree(dd->cntrs); 12365 dd->cntrs = NULL; 12366 kfree(dd->scntrs); 12367 dd->scntrs = NULL; 12368 kfree(dd->cntrnames); 12369 dd->cntrnames = NULL; 12370 if (dd->update_cntr_wq) { 12371 destroy_workqueue(dd->update_cntr_wq); 12372 dd->update_cntr_wq = NULL; 12373 } 12374 } 12375 12376 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry, 12377 u64 *psval, void *context, int vl) 12378 { 12379 u64 val; 12380 u64 sval = *psval; 12381 12382 if (entry->flags & CNTR_DISABLED) { 12383 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12384 return 0; 12385 } 12386 12387 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12388 12389 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0); 12390 12391 /* If its a synthetic counter there is more work we need to do */ 12392 if (entry->flags & CNTR_SYNTH) { 12393 if (sval == CNTR_MAX) { 12394 /* No need to read already saturated */ 12395 return CNTR_MAX; 12396 } 12397 12398 if (entry->flags & CNTR_32BIT) { 12399 /* 32bit counters can wrap multiple times */ 12400 u64 upper = sval >> 32; 12401 u64 lower = (sval << 32) >> 32; 12402 12403 if (lower > val) { /* hw wrapped */ 12404 if (upper == CNTR_32BIT_MAX) 12405 val = CNTR_MAX; 12406 else 12407 upper++; 12408 } 12409 12410 if (val != CNTR_MAX) 12411 val = (upper << 32) | val; 12412 12413 } else { 12414 /* If we rolled we are saturated */ 12415 if ((val < sval) || (val > CNTR_MAX)) 12416 val = CNTR_MAX; 12417 } 12418 } 12419 12420 *psval = val; 12421 12422 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12423 12424 return val; 12425 } 12426 12427 static u64 write_dev_port_cntr(struct hfi1_devdata *dd, 12428 struct cntr_entry *entry, 12429 u64 *psval, void *context, int vl, u64 data) 12430 { 12431 u64 val; 12432 12433 if (entry->flags & CNTR_DISABLED) { 12434 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12435 return 0; 12436 } 12437 12438 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12439 12440 if (entry->flags & CNTR_SYNTH) { 12441 *psval = data; 12442 if (entry->flags & CNTR_32BIT) { 12443 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12444 (data << 32) >> 32); 12445 val = data; /* return the full 64bit value */ 12446 } else { 12447 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12448 data); 12449 } 12450 } else { 12451 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data); 12452 } 12453 12454 *psval = val; 12455 12456 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12457 12458 return val; 12459 } 12460 12461 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl) 12462 { 12463 struct cntr_entry *entry; 12464 u64 *sval; 12465 12466 entry = &dev_cntrs[index]; 12467 sval = dd->scntrs + entry->offset; 12468 12469 if (vl != CNTR_INVALID_VL) 12470 sval += vl; 12471 12472 return read_dev_port_cntr(dd, entry, sval, dd, vl); 12473 } 12474 12475 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data) 12476 { 12477 struct cntr_entry *entry; 12478 u64 *sval; 12479 12480 entry = &dev_cntrs[index]; 12481 sval = dd->scntrs + entry->offset; 12482 12483 if (vl != CNTR_INVALID_VL) 12484 sval += vl; 12485 12486 return write_dev_port_cntr(dd, entry, sval, dd, vl, data); 12487 } 12488 12489 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl) 12490 { 12491 struct cntr_entry *entry; 12492 u64 *sval; 12493 12494 entry = &port_cntrs[index]; 12495 sval = ppd->scntrs + entry->offset; 12496 12497 if (vl != CNTR_INVALID_VL) 12498 sval += vl; 12499 12500 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12501 (index <= C_RCV_HDR_OVF_LAST)) { 12502 /* We do not want to bother for disabled contexts */ 12503 return 0; 12504 } 12505 12506 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl); 12507 } 12508 12509 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data) 12510 { 12511 struct cntr_entry *entry; 12512 u64 *sval; 12513 12514 entry = &port_cntrs[index]; 12515 sval = ppd->scntrs + entry->offset; 12516 12517 if (vl != CNTR_INVALID_VL) 12518 sval += vl; 12519 12520 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12521 (index <= C_RCV_HDR_OVF_LAST)) { 12522 /* We do not want to bother for disabled contexts */ 12523 return 0; 12524 } 12525 12526 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data); 12527 } 12528 12529 static void do_update_synth_timer(struct work_struct *work) 12530 { 12531 u64 cur_tx; 12532 u64 cur_rx; 12533 u64 total_flits; 12534 u8 update = 0; 12535 int i, j, vl; 12536 struct hfi1_pportdata *ppd; 12537 struct cntr_entry *entry; 12538 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata, 12539 update_cntr_work); 12540 12541 /* 12542 * Rather than keep beating on the CSRs pick a minimal set that we can 12543 * check to watch for potential roll over. We can do this by looking at 12544 * the number of flits sent/recv. If the total flits exceeds 32bits then 12545 * we have to iterate all the counters and update. 12546 */ 12547 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12548 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12549 12550 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12551 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12552 12553 hfi1_cdbg( 12554 CNTR, 12555 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n", 12556 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx); 12557 12558 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) { 12559 /* 12560 * May not be strictly necessary to update but it won't hurt and 12561 * simplifies the logic here. 12562 */ 12563 update = 1; 12564 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating", 12565 dd->unit); 12566 } else { 12567 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx); 12568 hfi1_cdbg(CNTR, 12569 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit, 12570 total_flits, (u64)CNTR_32BIT_MAX); 12571 if (total_flits >= CNTR_32BIT_MAX) { 12572 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating", 12573 dd->unit); 12574 update = 1; 12575 } 12576 } 12577 12578 if (update) { 12579 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit); 12580 for (i = 0; i < DEV_CNTR_LAST; i++) { 12581 entry = &dev_cntrs[i]; 12582 if (entry->flags & CNTR_VL) { 12583 for (vl = 0; vl < C_VL_COUNT; vl++) 12584 read_dev_cntr(dd, i, vl); 12585 } else { 12586 read_dev_cntr(dd, i, CNTR_INVALID_VL); 12587 } 12588 } 12589 ppd = (struct hfi1_pportdata *)(dd + 1); 12590 for (i = 0; i < dd->num_pports; i++, ppd++) { 12591 for (j = 0; j < PORT_CNTR_LAST; j++) { 12592 entry = &port_cntrs[j]; 12593 if (entry->flags & CNTR_VL) { 12594 for (vl = 0; vl < C_VL_COUNT; vl++) 12595 read_port_cntr(ppd, j, vl); 12596 } else { 12597 read_port_cntr(ppd, j, CNTR_INVALID_VL); 12598 } 12599 } 12600 } 12601 12602 /* 12603 * We want the value in the register. The goal is to keep track 12604 * of the number of "ticks" not the counter value. In other 12605 * words if the register rolls we want to notice it and go ahead 12606 * and force an update. 12607 */ 12608 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12609 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12610 CNTR_MODE_R, 0); 12611 12612 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12613 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12614 CNTR_MODE_R, 0); 12615 12616 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx", 12617 dd->unit, dd->last_tx, dd->last_rx); 12618 12619 } else { 12620 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit); 12621 } 12622 } 12623 12624 static void update_synth_timer(struct timer_list *t) 12625 { 12626 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer); 12627 12628 queue_work(dd->update_cntr_wq, &dd->update_cntr_work); 12629 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12630 } 12631 12632 #define C_MAX_NAME 16 /* 15 chars + one for /0 */ 12633 static int init_cntrs(struct hfi1_devdata *dd) 12634 { 12635 int i, rcv_ctxts, j; 12636 size_t sz; 12637 char *p; 12638 char name[C_MAX_NAME]; 12639 struct hfi1_pportdata *ppd; 12640 const char *bit_type_32 = ",32"; 12641 const int bit_type_32_sz = strlen(bit_type_32); 12642 u32 sdma_engines = chip_sdma_engines(dd); 12643 12644 /* set up the stats timer; the add_timer is done at the end */ 12645 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0); 12646 12647 /***********************/ 12648 /* per device counters */ 12649 /***********************/ 12650 12651 /* size names and determine how many we have*/ 12652 dd->ndevcntrs = 0; 12653 sz = 0; 12654 12655 for (i = 0; i < DEV_CNTR_LAST; i++) { 12656 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12657 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name); 12658 continue; 12659 } 12660 12661 if (dev_cntrs[i].flags & CNTR_VL) { 12662 dev_cntrs[i].offset = dd->ndevcntrs; 12663 for (j = 0; j < C_VL_COUNT; j++) { 12664 snprintf(name, C_MAX_NAME, "%s%d", 12665 dev_cntrs[i].name, vl_from_idx(j)); 12666 sz += strlen(name); 12667 /* Add ",32" for 32-bit counters */ 12668 if (dev_cntrs[i].flags & CNTR_32BIT) 12669 sz += bit_type_32_sz; 12670 sz++; 12671 dd->ndevcntrs++; 12672 } 12673 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12674 dev_cntrs[i].offset = dd->ndevcntrs; 12675 for (j = 0; j < sdma_engines; j++) { 12676 snprintf(name, C_MAX_NAME, "%s%d", 12677 dev_cntrs[i].name, j); 12678 sz += strlen(name); 12679 /* Add ",32" for 32-bit counters */ 12680 if (dev_cntrs[i].flags & CNTR_32BIT) 12681 sz += bit_type_32_sz; 12682 sz++; 12683 dd->ndevcntrs++; 12684 } 12685 } else { 12686 /* +1 for newline. */ 12687 sz += strlen(dev_cntrs[i].name) + 1; 12688 /* Add ",32" for 32-bit counters */ 12689 if (dev_cntrs[i].flags & CNTR_32BIT) 12690 sz += bit_type_32_sz; 12691 dev_cntrs[i].offset = dd->ndevcntrs; 12692 dd->ndevcntrs++; 12693 } 12694 } 12695 12696 /* allocate space for the counter values */ 12697 dd->cntrs = kcalloc(dd->ndevcntrs + num_driver_cntrs, sizeof(u64), 12698 GFP_KERNEL); 12699 if (!dd->cntrs) 12700 goto bail; 12701 12702 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12703 if (!dd->scntrs) 12704 goto bail; 12705 12706 /* allocate space for the counter names */ 12707 dd->cntrnameslen = sz; 12708 dd->cntrnames = kmalloc(sz, GFP_KERNEL); 12709 if (!dd->cntrnames) 12710 goto bail; 12711 12712 /* fill in the names */ 12713 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) { 12714 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12715 /* Nothing */ 12716 } else if (dev_cntrs[i].flags & CNTR_VL) { 12717 for (j = 0; j < C_VL_COUNT; j++) { 12718 snprintf(name, C_MAX_NAME, "%s%d", 12719 dev_cntrs[i].name, 12720 vl_from_idx(j)); 12721 memcpy(p, name, strlen(name)); 12722 p += strlen(name); 12723 12724 /* Counter is 32 bits */ 12725 if (dev_cntrs[i].flags & CNTR_32BIT) { 12726 memcpy(p, bit_type_32, bit_type_32_sz); 12727 p += bit_type_32_sz; 12728 } 12729 12730 *p++ = '\n'; 12731 } 12732 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12733 for (j = 0; j < sdma_engines; j++) { 12734 snprintf(name, C_MAX_NAME, "%s%d", 12735 dev_cntrs[i].name, j); 12736 memcpy(p, name, strlen(name)); 12737 p += strlen(name); 12738 12739 /* Counter is 32 bits */ 12740 if (dev_cntrs[i].flags & CNTR_32BIT) { 12741 memcpy(p, bit_type_32, bit_type_32_sz); 12742 p += bit_type_32_sz; 12743 } 12744 12745 *p++ = '\n'; 12746 } 12747 } else { 12748 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name)); 12749 p += strlen(dev_cntrs[i].name); 12750 12751 /* Counter is 32 bits */ 12752 if (dev_cntrs[i].flags & CNTR_32BIT) { 12753 memcpy(p, bit_type_32, bit_type_32_sz); 12754 p += bit_type_32_sz; 12755 } 12756 12757 *p++ = '\n'; 12758 } 12759 } 12760 12761 /*********************/ 12762 /* per port counters */ 12763 /*********************/ 12764 12765 /* 12766 * Go through the counters for the overflows and disable the ones we 12767 * don't need. This varies based on platform so we need to do it 12768 * dynamically here. 12769 */ 12770 rcv_ctxts = dd->num_rcv_contexts; 12771 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts; 12772 i <= C_RCV_HDR_OVF_LAST; i++) { 12773 port_cntrs[i].flags |= CNTR_DISABLED; 12774 } 12775 12776 /* size port counter names and determine how many we have*/ 12777 sz = 0; 12778 dd->nportcntrs = 0; 12779 for (i = 0; i < PORT_CNTR_LAST; i++) { 12780 if (port_cntrs[i].flags & CNTR_DISABLED) { 12781 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name); 12782 continue; 12783 } 12784 12785 if (port_cntrs[i].flags & CNTR_VL) { 12786 port_cntrs[i].offset = dd->nportcntrs; 12787 for (j = 0; j < C_VL_COUNT; j++) { 12788 snprintf(name, C_MAX_NAME, "%s%d", 12789 port_cntrs[i].name, vl_from_idx(j)); 12790 sz += strlen(name); 12791 /* Add ",32" for 32-bit counters */ 12792 if (port_cntrs[i].flags & CNTR_32BIT) 12793 sz += bit_type_32_sz; 12794 sz++; 12795 dd->nportcntrs++; 12796 } 12797 } else { 12798 /* +1 for newline */ 12799 sz += strlen(port_cntrs[i].name) + 1; 12800 /* Add ",32" for 32-bit counters */ 12801 if (port_cntrs[i].flags & CNTR_32BIT) 12802 sz += bit_type_32_sz; 12803 port_cntrs[i].offset = dd->nportcntrs; 12804 dd->nportcntrs++; 12805 } 12806 } 12807 12808 /* allocate space for the counter names */ 12809 dd->portcntrnameslen = sz; 12810 dd->portcntrnames = kmalloc(sz, GFP_KERNEL); 12811 if (!dd->portcntrnames) 12812 goto bail; 12813 12814 /* fill in port cntr names */ 12815 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) { 12816 if (port_cntrs[i].flags & CNTR_DISABLED) 12817 continue; 12818 12819 if (port_cntrs[i].flags & CNTR_VL) { 12820 for (j = 0; j < C_VL_COUNT; j++) { 12821 snprintf(name, C_MAX_NAME, "%s%d", 12822 port_cntrs[i].name, vl_from_idx(j)); 12823 memcpy(p, name, strlen(name)); 12824 p += strlen(name); 12825 12826 /* Counter is 32 bits */ 12827 if (port_cntrs[i].flags & CNTR_32BIT) { 12828 memcpy(p, bit_type_32, bit_type_32_sz); 12829 p += bit_type_32_sz; 12830 } 12831 12832 *p++ = '\n'; 12833 } 12834 } else { 12835 memcpy(p, port_cntrs[i].name, 12836 strlen(port_cntrs[i].name)); 12837 p += strlen(port_cntrs[i].name); 12838 12839 /* Counter is 32 bits */ 12840 if (port_cntrs[i].flags & CNTR_32BIT) { 12841 memcpy(p, bit_type_32, bit_type_32_sz); 12842 p += bit_type_32_sz; 12843 } 12844 12845 *p++ = '\n'; 12846 } 12847 } 12848 12849 /* allocate per port storage for counter values */ 12850 ppd = (struct hfi1_pportdata *)(dd + 1); 12851 for (i = 0; i < dd->num_pports; i++, ppd++) { 12852 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12853 if (!ppd->cntrs) 12854 goto bail; 12855 12856 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12857 if (!ppd->scntrs) 12858 goto bail; 12859 } 12860 12861 /* CPU counters need to be allocated and zeroed */ 12862 if (init_cpu_counters(dd)) 12863 goto bail; 12864 12865 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d", 12866 WQ_MEM_RECLAIM, dd->unit); 12867 if (!dd->update_cntr_wq) 12868 goto bail; 12869 12870 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer); 12871 12872 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12873 return 0; 12874 bail: 12875 free_cntrs(dd); 12876 return -ENOMEM; 12877 } 12878 12879 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate) 12880 { 12881 switch (chip_lstate) { 12882 case LSTATE_DOWN: 12883 return IB_PORT_DOWN; 12884 case LSTATE_INIT: 12885 return IB_PORT_INIT; 12886 case LSTATE_ARMED: 12887 return IB_PORT_ARMED; 12888 case LSTATE_ACTIVE: 12889 return IB_PORT_ACTIVE; 12890 default: 12891 dd_dev_err(dd, 12892 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n", 12893 chip_lstate); 12894 return IB_PORT_DOWN; 12895 } 12896 } 12897 12898 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate) 12899 { 12900 /* look at the HFI meta-states only */ 12901 switch (chip_pstate & 0xf0) { 12902 case PLS_DISABLED: 12903 return IB_PORTPHYSSTATE_DISABLED; 12904 case PLS_OFFLINE: 12905 return OPA_PORTPHYSSTATE_OFFLINE; 12906 case PLS_POLLING: 12907 return IB_PORTPHYSSTATE_POLLING; 12908 case PLS_CONFIGPHY: 12909 return IB_PORTPHYSSTATE_TRAINING; 12910 case PLS_LINKUP: 12911 return IB_PORTPHYSSTATE_LINKUP; 12912 case PLS_PHYTEST: 12913 return IB_PORTPHYSSTATE_PHY_TEST; 12914 default: 12915 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n", 12916 chip_pstate); 12917 return IB_PORTPHYSSTATE_DISABLED; 12918 } 12919 } 12920 12921 /* return the OPA port logical state name */ 12922 const char *opa_lstate_name(u32 lstate) 12923 { 12924 static const char * const port_logical_names[] = { 12925 "PORT_NOP", 12926 "PORT_DOWN", 12927 "PORT_INIT", 12928 "PORT_ARMED", 12929 "PORT_ACTIVE", 12930 "PORT_ACTIVE_DEFER", 12931 }; 12932 if (lstate < ARRAY_SIZE(port_logical_names)) 12933 return port_logical_names[lstate]; 12934 return "unknown"; 12935 } 12936 12937 /* return the OPA port physical state name */ 12938 const char *opa_pstate_name(u32 pstate) 12939 { 12940 static const char * const port_physical_names[] = { 12941 "PHYS_NOP", 12942 "reserved1", 12943 "PHYS_POLL", 12944 "PHYS_DISABLED", 12945 "PHYS_TRAINING", 12946 "PHYS_LINKUP", 12947 "PHYS_LINK_ERR_RECOVER", 12948 "PHYS_PHY_TEST", 12949 "reserved8", 12950 "PHYS_OFFLINE", 12951 "PHYS_GANGED", 12952 "PHYS_TEST", 12953 }; 12954 if (pstate < ARRAY_SIZE(port_physical_names)) 12955 return port_physical_names[pstate]; 12956 return "unknown"; 12957 } 12958 12959 /** 12960 * update_statusp - Update userspace status flag 12961 * @ppd: Port data structure 12962 * @state: port state information 12963 * 12964 * Actual port status is determined by the host_link_state value 12965 * in the ppd. 12966 * 12967 * host_link_state MUST be updated before updating the user space 12968 * statusp. 12969 */ 12970 static void update_statusp(struct hfi1_pportdata *ppd, u32 state) 12971 { 12972 /* 12973 * Set port status flags in the page mapped into userspace 12974 * memory. Do it here to ensure a reliable state - this is 12975 * the only function called by all state handling code. 12976 * Always set the flags due to the fact that the cache value 12977 * might have been changed explicitly outside of this 12978 * function. 12979 */ 12980 if (ppd->statusp) { 12981 switch (state) { 12982 case IB_PORT_DOWN: 12983 case IB_PORT_INIT: 12984 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 12985 HFI1_STATUS_IB_READY); 12986 break; 12987 case IB_PORT_ARMED: 12988 *ppd->statusp |= HFI1_STATUS_IB_CONF; 12989 break; 12990 case IB_PORT_ACTIVE: 12991 *ppd->statusp |= HFI1_STATUS_IB_READY; 12992 break; 12993 } 12994 } 12995 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n", 12996 opa_lstate_name(state), state); 12997 } 12998 12999 /** 13000 * wait_logical_linkstate - wait for an IB link state change to occur 13001 * @ppd: port device 13002 * @state: the state to wait for 13003 * @msecs: the number of milliseconds to wait 13004 * 13005 * Wait up to msecs milliseconds for IB link state change to occur. 13006 * For now, take the easy polling route. 13007 * Returns 0 if state reached, otherwise -ETIMEDOUT. 13008 */ 13009 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 13010 int msecs) 13011 { 13012 unsigned long timeout; 13013 u32 new_state; 13014 13015 timeout = jiffies + msecs_to_jiffies(msecs); 13016 while (1) { 13017 new_state = chip_to_opa_lstate(ppd->dd, 13018 read_logical_state(ppd->dd)); 13019 if (new_state == state) 13020 break; 13021 if (time_after(jiffies, timeout)) { 13022 dd_dev_err(ppd->dd, 13023 "timeout waiting for link state 0x%x\n", 13024 state); 13025 return -ETIMEDOUT; 13026 } 13027 msleep(20); 13028 } 13029 13030 return 0; 13031 } 13032 13033 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state) 13034 { 13035 u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state); 13036 13037 dd_dev_info(ppd->dd, 13038 "physical state changed to %s (0x%x), phy 0x%x\n", 13039 opa_pstate_name(ib_pstate), ib_pstate, state); 13040 } 13041 13042 /* 13043 * Read the physical hardware link state and check if it matches host 13044 * drivers anticipated state. 13045 */ 13046 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state) 13047 { 13048 u32 read_state = read_physical_state(ppd->dd); 13049 13050 if (read_state == state) { 13051 log_state_transition(ppd, state); 13052 } else { 13053 dd_dev_err(ppd->dd, 13054 "anticipated phy link state 0x%x, read 0x%x\n", 13055 state, read_state); 13056 } 13057 } 13058 13059 /* 13060 * wait_physical_linkstate - wait for an physical link state change to occur 13061 * @ppd: port device 13062 * @state: the state to wait for 13063 * @msecs: the number of milliseconds to wait 13064 * 13065 * Wait up to msecs milliseconds for physical link state change to occur. 13066 * Returns 0 if state reached, otherwise -ETIMEDOUT. 13067 */ 13068 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 13069 int msecs) 13070 { 13071 u32 read_state; 13072 unsigned long timeout; 13073 13074 timeout = jiffies + msecs_to_jiffies(msecs); 13075 while (1) { 13076 read_state = read_physical_state(ppd->dd); 13077 if (read_state == state) 13078 break; 13079 if (time_after(jiffies, timeout)) { 13080 dd_dev_err(ppd->dd, 13081 "timeout waiting for phy link state 0x%x\n", 13082 state); 13083 return -ETIMEDOUT; 13084 } 13085 usleep_range(1950, 2050); /* sleep 2ms-ish */ 13086 } 13087 13088 log_state_transition(ppd, state); 13089 return 0; 13090 } 13091 13092 /* 13093 * wait_phys_link_offline_quiet_substates - wait for any offline substate 13094 * @ppd: port device 13095 * @msecs: the number of milliseconds to wait 13096 * 13097 * Wait up to msecs milliseconds for any offline physical link 13098 * state change to occur. 13099 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 13100 */ 13101 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 13102 int msecs) 13103 { 13104 u32 read_state; 13105 unsigned long timeout; 13106 13107 timeout = jiffies + msecs_to_jiffies(msecs); 13108 while (1) { 13109 read_state = read_physical_state(ppd->dd); 13110 if ((read_state & 0xF0) == PLS_OFFLINE) 13111 break; 13112 if (time_after(jiffies, timeout)) { 13113 dd_dev_err(ppd->dd, 13114 "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n", 13115 read_state, msecs); 13116 return -ETIMEDOUT; 13117 } 13118 usleep_range(1950, 2050); /* sleep 2ms-ish */ 13119 } 13120 13121 log_state_transition(ppd, read_state); 13122 return read_state; 13123 } 13124 13125 /* 13126 * wait_phys_link_out_of_offline - wait for any out of offline state 13127 * @ppd: port device 13128 * @msecs: the number of milliseconds to wait 13129 * 13130 * Wait up to msecs milliseconds for any out of offline physical link 13131 * state change to occur. 13132 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 13133 */ 13134 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd, 13135 int msecs) 13136 { 13137 u32 read_state; 13138 unsigned long timeout; 13139 13140 timeout = jiffies + msecs_to_jiffies(msecs); 13141 while (1) { 13142 read_state = read_physical_state(ppd->dd); 13143 if ((read_state & 0xF0) != PLS_OFFLINE) 13144 break; 13145 if (time_after(jiffies, timeout)) { 13146 dd_dev_err(ppd->dd, 13147 "timeout waiting for phy link out of offline. Read state 0x%x, %dms\n", 13148 read_state, msecs); 13149 return -ETIMEDOUT; 13150 } 13151 usleep_range(1950, 2050); /* sleep 2ms-ish */ 13152 } 13153 13154 log_state_transition(ppd, read_state); 13155 return read_state; 13156 } 13157 13158 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ 13159 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 13160 13161 #define SET_STATIC_RATE_CONTROL_SMASK(r) \ 13162 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 13163 13164 void hfi1_init_ctxt(struct send_context *sc) 13165 { 13166 if (sc) { 13167 struct hfi1_devdata *dd = sc->dd; 13168 u64 reg; 13169 u8 set = (sc->type == SC_USER ? 13170 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) : 13171 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)); 13172 reg = read_kctxt_csr(dd, sc->hw_context, 13173 SEND_CTXT_CHECK_ENABLE); 13174 if (set) 13175 CLEAR_STATIC_RATE_CONTROL_SMASK(reg); 13176 else 13177 SET_STATIC_RATE_CONTROL_SMASK(reg); 13178 write_kctxt_csr(dd, sc->hw_context, 13179 SEND_CTXT_CHECK_ENABLE, reg); 13180 } 13181 } 13182 13183 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp) 13184 { 13185 int ret = 0; 13186 u64 reg; 13187 13188 if (dd->icode != ICODE_RTL_SILICON) { 13189 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 13190 dd_dev_info(dd, "%s: tempsense not supported by HW\n", 13191 __func__); 13192 return -EINVAL; 13193 } 13194 reg = read_csr(dd, ASIC_STS_THERM); 13195 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) & 13196 ASIC_STS_THERM_CURR_TEMP_MASK); 13197 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) & 13198 ASIC_STS_THERM_LO_TEMP_MASK); 13199 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) & 13200 ASIC_STS_THERM_HI_TEMP_MASK); 13201 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) & 13202 ASIC_STS_THERM_CRIT_TEMP_MASK); 13203 /* triggers is a 3-bit value - 1 bit per trigger. */ 13204 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7); 13205 13206 return ret; 13207 } 13208 13209 /* ========================================================================= */ 13210 13211 /** 13212 * read_mod_write() - Calculate the IRQ register index and set/clear the bits 13213 * @dd: valid devdata 13214 * @src: IRQ source to determine register index from 13215 * @bits: the bits to set or clear 13216 * @set: true == set the bits, false == clear the bits 13217 * 13218 */ 13219 static void read_mod_write(struct hfi1_devdata *dd, u16 src, u64 bits, 13220 bool set) 13221 { 13222 u64 reg; 13223 u16 idx = src / BITS_PER_REGISTER; 13224 13225 spin_lock(&dd->irq_src_lock); 13226 reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); 13227 if (set) 13228 reg |= bits; 13229 else 13230 reg &= ~bits; 13231 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); 13232 spin_unlock(&dd->irq_src_lock); 13233 } 13234 13235 /** 13236 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources 13237 * @dd: valid devdata 13238 * @first: first IRQ source to set/clear 13239 * @last: last IRQ source (inclusive) to set/clear 13240 * @set: true == set the bits, false == clear the bits 13241 * 13242 * If first == last, set the exact source. 13243 */ 13244 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set) 13245 { 13246 u64 bits = 0; 13247 u64 bit; 13248 u16 src; 13249 13250 if (first > NUM_INTERRUPT_SOURCES || last > NUM_INTERRUPT_SOURCES) 13251 return -EINVAL; 13252 13253 if (last < first) 13254 return -ERANGE; 13255 13256 for (src = first; src <= last; src++) { 13257 bit = src % BITS_PER_REGISTER; 13258 /* wrapped to next register? */ 13259 if (!bit && bits) { 13260 read_mod_write(dd, src - 1, bits, set); 13261 bits = 0; 13262 } 13263 bits |= BIT_ULL(bit); 13264 } 13265 read_mod_write(dd, last, bits, set); 13266 13267 return 0; 13268 } 13269 13270 /* 13271 * Clear all interrupt sources on the chip. 13272 */ 13273 void clear_all_interrupts(struct hfi1_devdata *dd) 13274 { 13275 int i; 13276 13277 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13278 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); 13279 13280 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); 13281 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); 13282 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); 13283 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); 13284 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); 13285 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); 13286 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); 13287 for (i = 0; i < chip_send_contexts(dd); i++) 13288 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0); 13289 for (i = 0; i < chip_sdma_engines(dd); i++) 13290 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0); 13291 13292 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); 13293 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); 13294 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); 13295 } 13296 13297 /* 13298 * Remap the interrupt source from the general handler to the given MSI-X 13299 * interrupt. 13300 */ 13301 void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr) 13302 { 13303 u64 reg; 13304 int m, n; 13305 13306 /* clear from the handled mask of the general interrupt */ 13307 m = isrc / 64; 13308 n = isrc % 64; 13309 if (likely(m < CCE_NUM_INT_CSRS)) { 13310 dd->gi_mask[m] &= ~((u64)1 << n); 13311 } else { 13312 dd_dev_err(dd, "remap interrupt err\n"); 13313 return; 13314 } 13315 13316 /* direct the chip source to the given MSI-X interrupt */ 13317 m = isrc / 8; 13318 n = isrc % 8; 13319 reg = read_csr(dd, CCE_INT_MAP + (8 * m)); 13320 reg &= ~((u64)0xff << (8 * n)); 13321 reg |= ((u64)msix_intr & 0xff) << (8 * n); 13322 write_csr(dd, CCE_INT_MAP + (8 * m), reg); 13323 } 13324 13325 void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr) 13326 { 13327 /* 13328 * SDMA engine interrupt sources grouped by type, rather than 13329 * engine. Per-engine interrupts are as follows: 13330 * SDMA 13331 * SDMAProgress 13332 * SDMAIdle 13333 */ 13334 remap_intr(dd, IS_SDMA_START + engine, msix_intr); 13335 remap_intr(dd, IS_SDMA_PROGRESS_START + engine, msix_intr); 13336 remap_intr(dd, IS_SDMA_IDLE_START + engine, msix_intr); 13337 } 13338 13339 /* 13340 * Set the general handler to accept all interrupts, remap all 13341 * chip interrupts back to MSI-X 0. 13342 */ 13343 void reset_interrupts(struct hfi1_devdata *dd) 13344 { 13345 int i; 13346 13347 /* all interrupts handled by the general handler */ 13348 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13349 dd->gi_mask[i] = ~(u64)0; 13350 13351 /* all chip interrupts map to MSI-X 0 */ 13352 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13353 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13354 } 13355 13356 /** 13357 * set_up_interrupts() - Initialize the IRQ resources and state 13358 * @dd: valid devdata 13359 * 13360 */ 13361 static int set_up_interrupts(struct hfi1_devdata *dd) 13362 { 13363 int ret; 13364 13365 /* mask all interrupts */ 13366 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false); 13367 13368 /* clear all pending interrupts */ 13369 clear_all_interrupts(dd); 13370 13371 /* reset general handler mask, chip MSI-X mappings */ 13372 reset_interrupts(dd); 13373 13374 /* ask for MSI-X interrupts */ 13375 ret = msix_initialize(dd); 13376 if (ret) 13377 return ret; 13378 13379 ret = msix_request_irqs(dd); 13380 if (ret) 13381 msix_clean_up_interrupts(dd); 13382 13383 return ret; 13384 } 13385 13386 /* 13387 * Set up context values in dd. Sets: 13388 * 13389 * num_rcv_contexts - number of contexts being used 13390 * n_krcv_queues - number of kernel contexts 13391 * first_dyn_alloc_ctxt - first dynamically allocated context 13392 * in array of contexts 13393 * freectxts - number of free user contexts 13394 * num_send_contexts - number of PIO send contexts being used 13395 * num_netdev_contexts - number of contexts reserved for netdev 13396 */ 13397 static int set_up_context_variables(struct hfi1_devdata *dd) 13398 { 13399 unsigned long num_kernel_contexts; 13400 u16 num_netdev_contexts; 13401 int ret; 13402 unsigned ngroups; 13403 int rmt_count; 13404 int user_rmt_reduced; 13405 u32 n_usr_ctxts; 13406 u32 send_contexts = chip_send_contexts(dd); 13407 u32 rcv_contexts = chip_rcv_contexts(dd); 13408 13409 /* 13410 * Kernel receive contexts: 13411 * - Context 0 - control context (VL15/multicast/error) 13412 * - Context 1 - first kernel context 13413 * - Context 2 - second kernel context 13414 * ... 13415 */ 13416 if (n_krcvqs) 13417 /* 13418 * n_krcvqs is the sum of module parameter kernel receive 13419 * contexts, krcvqs[]. It does not include the control 13420 * context, so add that. 13421 */ 13422 num_kernel_contexts = n_krcvqs + 1; 13423 else 13424 num_kernel_contexts = DEFAULT_KRCVQS + 1; 13425 /* 13426 * Every kernel receive context needs an ACK send context. 13427 * one send context is allocated for each VL{0-7} and VL15 13428 */ 13429 if (num_kernel_contexts > (send_contexts - num_vls - 1)) { 13430 dd_dev_err(dd, 13431 "Reducing # kernel rcv contexts to: %d, from %lu\n", 13432 send_contexts - num_vls - 1, 13433 num_kernel_contexts); 13434 num_kernel_contexts = send_contexts - num_vls - 1; 13435 } 13436 13437 /* 13438 * User contexts: 13439 * - default to 1 user context per real (non-HT) CPU core if 13440 * num_user_contexts is negative 13441 */ 13442 if (num_user_contexts < 0) 13443 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask); 13444 else 13445 n_usr_ctxts = num_user_contexts; 13446 /* 13447 * Adjust the counts given a global max. 13448 */ 13449 if (num_kernel_contexts + n_usr_ctxts > rcv_contexts) { 13450 dd_dev_err(dd, 13451 "Reducing # user receive contexts to: %u, from %u\n", 13452 (u32)(rcv_contexts - num_kernel_contexts), 13453 n_usr_ctxts); 13454 /* recalculate */ 13455 n_usr_ctxts = rcv_contexts - num_kernel_contexts; 13456 } 13457 13458 num_netdev_contexts = 13459 hfi1_num_netdev_contexts(dd, rcv_contexts - 13460 (num_kernel_contexts + n_usr_ctxts), 13461 &node_affinity.real_cpu_mask); 13462 /* 13463 * The RMT entries are currently allocated as shown below: 13464 * 1. QOS (0 to 128 entries); 13465 * 2. FECN (num_kernel_context - 1 + num_user_contexts + 13466 * num_netdev_contexts); 13467 * 3. netdev (num_netdev_contexts). 13468 * It should be noted that FECN oversubscribe num_netdev_contexts 13469 * entries of RMT because both netdev and PSM could allocate any receive 13470 * context between dd->first_dyn_alloc_text and dd->num_rcv_contexts, 13471 * and PSM FECN must reserve an RMT entry for each possible PSM receive 13472 * context. 13473 */ 13474 rmt_count = qos_rmt_entries(dd, NULL, NULL) + (num_netdev_contexts * 2); 13475 if (HFI1_CAP_IS_KSET(TID_RDMA)) 13476 rmt_count += num_kernel_contexts - 1; 13477 if (rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) { 13478 user_rmt_reduced = NUM_MAP_ENTRIES - rmt_count; 13479 dd_dev_err(dd, 13480 "RMT size is reducing the number of user receive contexts from %u to %d\n", 13481 n_usr_ctxts, 13482 user_rmt_reduced); 13483 /* recalculate */ 13484 n_usr_ctxts = user_rmt_reduced; 13485 } 13486 13487 /* the first N are kernel contexts, the rest are user/netdev contexts */ 13488 dd->num_rcv_contexts = 13489 num_kernel_contexts + n_usr_ctxts + num_netdev_contexts; 13490 dd->n_krcv_queues = num_kernel_contexts; 13491 dd->first_dyn_alloc_ctxt = num_kernel_contexts; 13492 dd->num_netdev_contexts = num_netdev_contexts; 13493 dd->num_user_contexts = n_usr_ctxts; 13494 dd->freectxts = n_usr_ctxts; 13495 dd_dev_info(dd, 13496 "rcv contexts: chip %d, used %d (kernel %d, netdev %u, user %u)\n", 13497 rcv_contexts, 13498 (int)dd->num_rcv_contexts, 13499 (int)dd->n_krcv_queues, 13500 dd->num_netdev_contexts, 13501 dd->num_user_contexts); 13502 13503 /* 13504 * Receive array allocation: 13505 * All RcvArray entries are divided into groups of 8. This 13506 * is required by the hardware and will speed up writes to 13507 * consecutive entries by using write-combining of the entire 13508 * cacheline. 13509 * 13510 * The number of groups are evenly divided among all contexts. 13511 * any left over groups will be given to the first N user 13512 * contexts. 13513 */ 13514 dd->rcv_entries.group_size = RCV_INCREMENT; 13515 ngroups = chip_rcv_array_count(dd) / dd->rcv_entries.group_size; 13516 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts; 13517 dd->rcv_entries.nctxt_extra = ngroups - 13518 (dd->num_rcv_contexts * dd->rcv_entries.ngroups); 13519 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n", 13520 dd->rcv_entries.ngroups, 13521 dd->rcv_entries.nctxt_extra); 13522 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size > 13523 MAX_EAGER_ENTRIES * 2) { 13524 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) / 13525 dd->rcv_entries.group_size; 13526 dd_dev_info(dd, 13527 "RcvArray group count too high, change to %u\n", 13528 dd->rcv_entries.ngroups); 13529 dd->rcv_entries.nctxt_extra = 0; 13530 } 13531 /* 13532 * PIO send contexts 13533 */ 13534 ret = init_sc_pools_and_sizes(dd); 13535 if (ret >= 0) { /* success */ 13536 dd->num_send_contexts = ret; 13537 dd_dev_info( 13538 dd, 13539 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n", 13540 send_contexts, 13541 dd->num_send_contexts, 13542 dd->sc_sizes[SC_KERNEL].count, 13543 dd->sc_sizes[SC_ACK].count, 13544 dd->sc_sizes[SC_USER].count, 13545 dd->sc_sizes[SC_VL15].count); 13546 ret = 0; /* success */ 13547 } 13548 13549 return ret; 13550 } 13551 13552 /* 13553 * Set the device/port partition key table. The MAD code 13554 * will ensure that, at least, the partial management 13555 * partition key is present in the table. 13556 */ 13557 static void set_partition_keys(struct hfi1_pportdata *ppd) 13558 { 13559 struct hfi1_devdata *dd = ppd->dd; 13560 u64 reg = 0; 13561 int i; 13562 13563 dd_dev_info(dd, "Setting partition keys\n"); 13564 for (i = 0; i < hfi1_get_npkeys(dd); i++) { 13565 reg |= (ppd->pkeys[i] & 13566 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) << 13567 ((i % 4) * 13568 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT); 13569 /* Each register holds 4 PKey values. */ 13570 if ((i % 4) == 3) { 13571 write_csr(dd, RCV_PARTITION_KEY + 13572 ((i - 3) * 2), reg); 13573 reg = 0; 13574 } 13575 } 13576 13577 /* Always enable HW pkeys check when pkeys table is set */ 13578 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK); 13579 } 13580 13581 /* 13582 * These CSRs and memories are uninitialized on reset and must be 13583 * written before reading to set the ECC/parity bits. 13584 * 13585 * NOTE: All user context CSRs that are not mmaped write-only 13586 * (e.g. the TID flows) must be initialized even if the driver never 13587 * reads them. 13588 */ 13589 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd) 13590 { 13591 int i, j; 13592 13593 /* CceIntMap */ 13594 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13595 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13596 13597 /* SendCtxtCreditReturnAddr */ 13598 for (i = 0; i < chip_send_contexts(dd); i++) 13599 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13600 13601 /* PIO Send buffers */ 13602 /* SDMA Send buffers */ 13603 /* 13604 * These are not normally read, and (presently) have no method 13605 * to be read, so are not pre-initialized 13606 */ 13607 13608 /* RcvHdrAddr */ 13609 /* RcvHdrTailAddr */ 13610 /* RcvTidFlowTable */ 13611 for (i = 0; i < chip_rcv_contexts(dd); i++) { 13612 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13613 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13614 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) 13615 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0); 13616 } 13617 13618 /* RcvArray */ 13619 for (i = 0; i < chip_rcv_array_count(dd); i++) 13620 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0); 13621 13622 /* RcvQPMapTable */ 13623 for (i = 0; i < 32; i++) 13624 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13625 } 13626 13627 /* 13628 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus. 13629 */ 13630 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits, 13631 u64 ctrl_bits) 13632 { 13633 unsigned long timeout; 13634 u64 reg; 13635 13636 /* is the condition present? */ 13637 reg = read_csr(dd, CCE_STATUS); 13638 if ((reg & status_bits) == 0) 13639 return; 13640 13641 /* clear the condition */ 13642 write_csr(dd, CCE_CTRL, ctrl_bits); 13643 13644 /* wait for the condition to clear */ 13645 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT); 13646 while (1) { 13647 reg = read_csr(dd, CCE_STATUS); 13648 if ((reg & status_bits) == 0) 13649 return; 13650 if (time_after(jiffies, timeout)) { 13651 dd_dev_err(dd, 13652 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n", 13653 status_bits, reg & status_bits); 13654 return; 13655 } 13656 udelay(1); 13657 } 13658 } 13659 13660 /* set CCE CSRs to chip reset defaults */ 13661 static void reset_cce_csrs(struct hfi1_devdata *dd) 13662 { 13663 int i; 13664 13665 /* CCE_REVISION read-only */ 13666 /* CCE_REVISION2 read-only */ 13667 /* CCE_CTRL - bits clear automatically */ 13668 /* CCE_STATUS read-only, use CceCtrl to clear */ 13669 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK); 13670 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK); 13671 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK); 13672 for (i = 0; i < CCE_NUM_SCRATCH; i++) 13673 write_csr(dd, CCE_SCRATCH + (8 * i), 0); 13674 /* CCE_ERR_STATUS read-only */ 13675 write_csr(dd, CCE_ERR_MASK, 0); 13676 write_csr(dd, CCE_ERR_CLEAR, ~0ull); 13677 /* CCE_ERR_FORCE leave alone */ 13678 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++) 13679 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); 13680 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); 13681 /* CCE_PCIE_CTRL leave alone */ 13682 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) { 13683 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); 13684 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), 13685 CCE_MSIX_TABLE_UPPER_RESETCSR); 13686 } 13687 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) { 13688 /* CCE_MSIX_PBA read-only */ 13689 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); 13690 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); 13691 } 13692 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13693 write_csr(dd, CCE_INT_MAP, 0); 13694 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 13695 /* CCE_INT_STATUS read-only */ 13696 write_csr(dd, CCE_INT_MASK + (8 * i), 0); 13697 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); 13698 /* CCE_INT_FORCE leave alone */ 13699 /* CCE_INT_BLOCKED read-only */ 13700 } 13701 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++) 13702 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); 13703 } 13704 13705 /* set MISC CSRs to chip reset defaults */ 13706 static void reset_misc_csrs(struct hfi1_devdata *dd) 13707 { 13708 int i; 13709 13710 for (i = 0; i < 32; i++) { 13711 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); 13712 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); 13713 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); 13714 } 13715 /* 13716 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can 13717 * only be written 128-byte chunks 13718 */ 13719 /* init RSA engine to clear lingering errors */ 13720 write_csr(dd, MISC_CFG_RSA_CMD, 1); 13721 write_csr(dd, MISC_CFG_RSA_MU, 0); 13722 write_csr(dd, MISC_CFG_FW_CTRL, 0); 13723 /* MISC_STS_8051_DIGEST read-only */ 13724 /* MISC_STS_SBM_DIGEST read-only */ 13725 /* MISC_STS_PCIE_DIGEST read-only */ 13726 /* MISC_STS_FAB_DIGEST read-only */ 13727 /* MISC_ERR_STATUS read-only */ 13728 write_csr(dd, MISC_ERR_MASK, 0); 13729 write_csr(dd, MISC_ERR_CLEAR, ~0ull); 13730 /* MISC_ERR_FORCE leave alone */ 13731 } 13732 13733 /* set TXE CSRs to chip reset defaults */ 13734 static void reset_txe_csrs(struct hfi1_devdata *dd) 13735 { 13736 int i; 13737 13738 /* 13739 * TXE Kernel CSRs 13740 */ 13741 write_csr(dd, SEND_CTRL, 0); 13742 __cm_reset(dd, 0); /* reset CM internal state */ 13743 /* SEND_CONTEXTS read-only */ 13744 /* SEND_DMA_ENGINES read-only */ 13745 /* SEND_PIO_MEM_SIZE read-only */ 13746 /* SEND_DMA_MEM_SIZE read-only */ 13747 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); 13748 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */ 13749 /* SEND_PIO_ERR_STATUS read-only */ 13750 write_csr(dd, SEND_PIO_ERR_MASK, 0); 13751 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); 13752 /* SEND_PIO_ERR_FORCE leave alone */ 13753 /* SEND_DMA_ERR_STATUS read-only */ 13754 write_csr(dd, SEND_DMA_ERR_MASK, 0); 13755 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); 13756 /* SEND_DMA_ERR_FORCE leave alone */ 13757 /* SEND_EGRESS_ERR_STATUS read-only */ 13758 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); 13759 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); 13760 /* SEND_EGRESS_ERR_FORCE leave alone */ 13761 write_csr(dd, SEND_BTH_QP, 0); 13762 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); 13763 write_csr(dd, SEND_SC2VLT0, 0); 13764 write_csr(dd, SEND_SC2VLT1, 0); 13765 write_csr(dd, SEND_SC2VLT2, 0); 13766 write_csr(dd, SEND_SC2VLT3, 0); 13767 write_csr(dd, SEND_LEN_CHECK0, 0); 13768 write_csr(dd, SEND_LEN_CHECK1, 0); 13769 /* SEND_ERR_STATUS read-only */ 13770 write_csr(dd, SEND_ERR_MASK, 0); 13771 write_csr(dd, SEND_ERR_CLEAR, ~0ull); 13772 /* SEND_ERR_FORCE read-only */ 13773 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++) 13774 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); 13775 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++) 13776 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); 13777 for (i = 0; i < chip_send_contexts(dd) / NUM_CONTEXTS_PER_SET; i++) 13778 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); 13779 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++) 13780 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); 13781 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++) 13782 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); 13783 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); 13784 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); 13785 /* SEND_CM_CREDIT_USED_STATUS read-only */ 13786 write_csr(dd, SEND_CM_TIMER_CTRL, 0); 13787 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); 13788 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); 13789 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); 13790 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); 13791 for (i = 0; i < TXE_NUM_DATA_VL; i++) 13792 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 13793 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 13794 /* SEND_CM_CREDIT_USED_VL read-only */ 13795 /* SEND_CM_CREDIT_USED_VL15 read-only */ 13796 /* SEND_EGRESS_CTXT_STATUS read-only */ 13797 /* SEND_EGRESS_SEND_DMA_STATUS read-only */ 13798 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); 13799 /* SEND_EGRESS_ERR_INFO read-only */ 13800 /* SEND_EGRESS_ERR_SOURCE read-only */ 13801 13802 /* 13803 * TXE Per-Context CSRs 13804 */ 13805 for (i = 0; i < chip_send_contexts(dd); i++) { 13806 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 13807 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0); 13808 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13809 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0); 13810 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0); 13811 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull); 13812 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0); 13813 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0); 13814 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0); 13815 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0); 13816 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0); 13817 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0); 13818 } 13819 13820 /* 13821 * TXE Per-SDMA CSRs 13822 */ 13823 for (i = 0; i < chip_sdma_engines(dd); i++) { 13824 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 13825 /* SEND_DMA_STATUS read-only */ 13826 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0); 13827 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0); 13828 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0); 13829 /* SEND_DMA_HEAD read-only */ 13830 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0); 13831 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0); 13832 /* SEND_DMA_IDLE_CNT read-only */ 13833 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0); 13834 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0); 13835 /* SEND_DMA_DESC_FETCHED_CNT read-only */ 13836 /* SEND_DMA_ENG_ERR_STATUS read-only */ 13837 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0); 13838 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull); 13839 /* SEND_DMA_ENG_ERR_FORCE leave alone */ 13840 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0); 13841 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0); 13842 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0); 13843 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0); 13844 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0); 13845 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0); 13846 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0); 13847 } 13848 } 13849 13850 /* 13851 * Expect on entry: 13852 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0 13853 */ 13854 static void init_rbufs(struct hfi1_devdata *dd) 13855 { 13856 u64 reg; 13857 int count; 13858 13859 /* 13860 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are 13861 * clear. 13862 */ 13863 count = 0; 13864 while (1) { 13865 reg = read_csr(dd, RCV_STATUS); 13866 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 13867 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0) 13868 break; 13869 /* 13870 * Give up after 1ms - maximum wait time. 13871 * 13872 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at 13873 * 250MB/s bandwidth. Lower rate to 66% for overhead to get: 13874 * 136 KB / (66% * 250MB/s) = 844us 13875 */ 13876 if (count++ > 500) { 13877 dd_dev_err(dd, 13878 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n", 13879 __func__, reg); 13880 break; 13881 } 13882 udelay(2); /* do not busy-wait the CSR */ 13883 } 13884 13885 /* start the init - expect RcvCtrl to be 0 */ 13886 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); 13887 13888 /* 13889 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief 13890 * period after the write before RcvStatus.RxRbufInitDone is valid. 13891 * The delay in the first run through the loop below is sufficient and 13892 * required before the first read of RcvStatus.RxRbufInintDone. 13893 */ 13894 read_csr(dd, RCV_CTRL); 13895 13896 /* wait for the init to finish */ 13897 count = 0; 13898 while (1) { 13899 /* delay is required first time through - see above */ 13900 udelay(2); /* do not busy-wait the CSR */ 13901 reg = read_csr(dd, RCV_STATUS); 13902 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK)) 13903 break; 13904 13905 /* give up after 100us - slowest possible at 33MHz is 73us */ 13906 if (count++ > 50) { 13907 dd_dev_err(dd, 13908 "%s: RcvStatus.RxRbufInit not set, continuing\n", 13909 __func__); 13910 break; 13911 } 13912 } 13913 } 13914 13915 /* set RXE CSRs to chip reset defaults */ 13916 static void reset_rxe_csrs(struct hfi1_devdata *dd) 13917 { 13918 int i, j; 13919 13920 /* 13921 * RXE Kernel CSRs 13922 */ 13923 write_csr(dd, RCV_CTRL, 0); 13924 init_rbufs(dd); 13925 /* RCV_STATUS read-only */ 13926 /* RCV_CONTEXTS read-only */ 13927 /* RCV_ARRAY_CNT read-only */ 13928 /* RCV_BUF_SIZE read-only */ 13929 write_csr(dd, RCV_BTH_QP, 0); 13930 write_csr(dd, RCV_MULTICAST, 0); 13931 write_csr(dd, RCV_BYPASS, 0); 13932 write_csr(dd, RCV_VL15, 0); 13933 /* this is a clear-down */ 13934 write_csr(dd, RCV_ERR_INFO, 13935 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK); 13936 /* RCV_ERR_STATUS read-only */ 13937 write_csr(dd, RCV_ERR_MASK, 0); 13938 write_csr(dd, RCV_ERR_CLEAR, ~0ull); 13939 /* RCV_ERR_FORCE leave alone */ 13940 for (i = 0; i < 32; i++) 13941 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13942 for (i = 0; i < 4; i++) 13943 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); 13944 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++) 13945 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); 13946 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++) 13947 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); 13948 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) 13949 clear_rsm_rule(dd, i); 13950 for (i = 0; i < 32; i++) 13951 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); 13952 13953 /* 13954 * RXE Kernel and User Per-Context CSRs 13955 */ 13956 for (i = 0; i < chip_rcv_contexts(dd); i++) { 13957 /* kernel */ 13958 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0); 13959 /* RCV_CTXT_STATUS read-only */ 13960 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0); 13961 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0); 13962 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0); 13963 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13964 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0); 13965 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0); 13966 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0); 13967 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13968 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0); 13969 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0); 13970 13971 /* user */ 13972 /* RCV_HDR_TAIL read-only */ 13973 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0); 13974 /* RCV_EGR_INDEX_TAIL read-only */ 13975 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0); 13976 /* RCV_EGR_OFFSET_TAIL read-only */ 13977 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) { 13978 write_uctxt_csr(dd, i, 13979 RCV_TID_FLOW_TABLE + (8 * j), 0); 13980 } 13981 } 13982 } 13983 13984 /* 13985 * Set sc2vl tables. 13986 * 13987 * They power on to zeros, so to avoid send context errors 13988 * they need to be set: 13989 * 13990 * SC 0-7 -> VL 0-7 (respectively) 13991 * SC 15 -> VL 15 13992 * otherwise 13993 * -> VL 0 13994 */ 13995 static void init_sc2vl_tables(struct hfi1_devdata *dd) 13996 { 13997 int i; 13998 /* init per architecture spec, constrained by hardware capability */ 13999 14000 /* HFI maps sent packets */ 14001 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( 14002 0, 14003 0, 0, 1, 1, 14004 2, 2, 3, 3, 14005 4, 4, 5, 5, 14006 6, 6, 7, 7)); 14007 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( 14008 1, 14009 8, 0, 9, 0, 14010 10, 0, 11, 0, 14011 12, 0, 13, 0, 14012 14, 0, 15, 15)); 14013 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( 14014 2, 14015 16, 0, 17, 0, 14016 18, 0, 19, 0, 14017 20, 0, 21, 0, 14018 22, 0, 23, 0)); 14019 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( 14020 3, 14021 24, 0, 25, 0, 14022 26, 0, 27, 0, 14023 28, 0, 29, 0, 14024 30, 0, 31, 0)); 14025 14026 /* DC maps received packets */ 14027 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( 14028 15_0, 14029 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 14030 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15)); 14031 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( 14032 31_16, 14033 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0, 14034 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0)); 14035 14036 /* initialize the cached sc2vl values consistently with h/w */ 14037 for (i = 0; i < 32; i++) { 14038 if (i < 8 || i == 15) 14039 *((u8 *)(dd->sc2vl) + i) = (u8)i; 14040 else 14041 *((u8 *)(dd->sc2vl) + i) = 0; 14042 } 14043 } 14044 14045 /* 14046 * Read chip sizes and then reset parts to sane, disabled, values. We cannot 14047 * depend on the chip going through a power-on reset - a driver may be loaded 14048 * and unloaded many times. 14049 * 14050 * Do not write any CSR values to the chip in this routine - there may be 14051 * a reset following the (possible) FLR in this routine. 14052 * 14053 */ 14054 static int init_chip(struct hfi1_devdata *dd) 14055 { 14056 int i; 14057 int ret = 0; 14058 14059 /* 14060 * Put the HFI CSRs in a known state. 14061 * Combine this with a DC reset. 14062 * 14063 * Stop the device from doing anything while we do a 14064 * reset. We know there are no other active users of 14065 * the device since we are now in charge. Turn off 14066 * off all outbound and inbound traffic and make sure 14067 * the device does not generate any interrupts. 14068 */ 14069 14070 /* disable send contexts and SDMA engines */ 14071 write_csr(dd, SEND_CTRL, 0); 14072 for (i = 0; i < chip_send_contexts(dd); i++) 14073 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 14074 for (i = 0; i < chip_sdma_engines(dd); i++) 14075 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 14076 /* disable port (turn off RXE inbound traffic) and contexts */ 14077 write_csr(dd, RCV_CTRL, 0); 14078 for (i = 0; i < chip_rcv_contexts(dd); i++) 14079 write_csr(dd, RCV_CTXT_CTRL, 0); 14080 /* mask all interrupt sources */ 14081 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 14082 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 14083 14084 /* 14085 * DC Reset: do a full DC reset before the register clear. 14086 * A recommended length of time to hold is one CSR read, 14087 * so reread the CceDcCtrl. Then, hold the DC in reset 14088 * across the clear. 14089 */ 14090 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 14091 (void)read_csr(dd, CCE_DC_CTRL); 14092 14093 if (use_flr) { 14094 /* 14095 * A FLR will reset the SPC core and part of the PCIe. 14096 * The parts that need to be restored have already been 14097 * saved. 14098 */ 14099 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14100 14101 /* do the FLR, the DC reset will remain */ 14102 pcie_flr(dd->pcidev); 14103 14104 /* restore command and BARs */ 14105 ret = restore_pci_variables(dd); 14106 if (ret) { 14107 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14108 __func__); 14109 return ret; 14110 } 14111 14112 if (is_ax(dd)) { 14113 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 14114 pcie_flr(dd->pcidev); 14115 ret = restore_pci_variables(dd); 14116 if (ret) { 14117 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 14118 __func__); 14119 return ret; 14120 } 14121 } 14122 } else { 14123 dd_dev_info(dd, "Resetting CSRs with writes\n"); 14124 reset_cce_csrs(dd); 14125 reset_txe_csrs(dd); 14126 reset_rxe_csrs(dd); 14127 reset_misc_csrs(dd); 14128 } 14129 /* clear the DC reset */ 14130 write_csr(dd, CCE_DC_CTRL, 0); 14131 14132 /* Set the LED off */ 14133 setextled(dd, 0); 14134 14135 /* 14136 * Clear the QSFP reset. 14137 * An FLR enforces a 0 on all out pins. The driver does not touch 14138 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and 14139 * anything plugged constantly in reset, if it pays attention 14140 * to RESET_N. 14141 * Prime examples of this are optical cables. Set all pins high. 14142 * I2CCLK and I2CDAT will change per direction, and INT_N and 14143 * MODPRS_N are input only and their value is ignored. 14144 */ 14145 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); 14146 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); 14147 init_chip_resources(dd); 14148 return ret; 14149 } 14150 14151 static void init_early_variables(struct hfi1_devdata *dd) 14152 { 14153 int i; 14154 14155 /* assign link credit variables */ 14156 dd->vau = CM_VAU; 14157 dd->link_credits = CM_GLOBAL_CREDITS; 14158 if (is_ax(dd)) 14159 dd->link_credits--; 14160 dd->vcu = cu_to_vcu(hfi1_cu); 14161 /* enough room for 8 MAD packets plus header - 17K */ 14162 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau); 14163 if (dd->vl15_init > dd->link_credits) 14164 dd->vl15_init = dd->link_credits; 14165 14166 write_uninitialized_csrs_and_memories(dd); 14167 14168 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 14169 for (i = 0; i < dd->num_pports; i++) { 14170 struct hfi1_pportdata *ppd = &dd->pport[i]; 14171 14172 set_partition_keys(ppd); 14173 } 14174 init_sc2vl_tables(dd); 14175 } 14176 14177 static void init_kdeth_qp(struct hfi1_devdata *dd) 14178 { 14179 write_csr(dd, SEND_BTH_QP, 14180 (RVT_KDETH_QP_PREFIX & SEND_BTH_QP_KDETH_QP_MASK) << 14181 SEND_BTH_QP_KDETH_QP_SHIFT); 14182 14183 write_csr(dd, RCV_BTH_QP, 14184 (RVT_KDETH_QP_PREFIX & RCV_BTH_QP_KDETH_QP_MASK) << 14185 RCV_BTH_QP_KDETH_QP_SHIFT); 14186 } 14187 14188 /** 14189 * hfi1_get_qp_map 14190 * @dd: device data 14191 * @idx: index to read 14192 */ 14193 u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx) 14194 { 14195 u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8); 14196 14197 reg >>= (idx % 8) * 8; 14198 return reg; 14199 } 14200 14201 /** 14202 * init_qpmap_table 14203 * @dd - device data 14204 * @first_ctxt - first context 14205 * @last_ctxt - first context 14206 * 14207 * This return sets the qpn mapping table that 14208 * is indexed by qpn[8:1]. 14209 * 14210 * The routine will round robin the 256 settings 14211 * from first_ctxt to last_ctxt. 14212 * 14213 * The first/last looks ahead to having specialized 14214 * receive contexts for mgmt and bypass. Normal 14215 * verbs traffic will assumed to be on a range 14216 * of receive contexts. 14217 */ 14218 static void init_qpmap_table(struct hfi1_devdata *dd, 14219 u32 first_ctxt, 14220 u32 last_ctxt) 14221 { 14222 u64 reg = 0; 14223 u64 regno = RCV_QP_MAP_TABLE; 14224 int i; 14225 u64 ctxt = first_ctxt; 14226 14227 for (i = 0; i < 256; i++) { 14228 reg |= ctxt << (8 * (i % 8)); 14229 ctxt++; 14230 if (ctxt > last_ctxt) 14231 ctxt = first_ctxt; 14232 if (i % 8 == 7) { 14233 write_csr(dd, regno, reg); 14234 reg = 0; 14235 regno += 8; 14236 } 14237 } 14238 14239 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 14240 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK); 14241 } 14242 14243 struct rsm_map_table { 14244 u64 map[NUM_MAP_REGS]; 14245 unsigned int used; 14246 }; 14247 14248 struct rsm_rule_data { 14249 u8 offset; 14250 u8 pkt_type; 14251 u32 field1_off; 14252 u32 field2_off; 14253 u32 index1_off; 14254 u32 index1_width; 14255 u32 index2_off; 14256 u32 index2_width; 14257 u32 mask1; 14258 u32 value1; 14259 u32 mask2; 14260 u32 value2; 14261 }; 14262 14263 /* 14264 * Return an initialized RMT map table for users to fill in. OK if it 14265 * returns NULL, indicating no table. 14266 */ 14267 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd) 14268 { 14269 struct rsm_map_table *rmt; 14270 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */ 14271 14272 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL); 14273 if (rmt) { 14274 memset(rmt->map, rxcontext, sizeof(rmt->map)); 14275 rmt->used = 0; 14276 } 14277 14278 return rmt; 14279 } 14280 14281 /* 14282 * Write the final RMT map table to the chip and free the table. OK if 14283 * table is NULL. 14284 */ 14285 static void complete_rsm_map_table(struct hfi1_devdata *dd, 14286 struct rsm_map_table *rmt) 14287 { 14288 int i; 14289 14290 if (rmt) { 14291 /* write table to chip */ 14292 for (i = 0; i < NUM_MAP_REGS; i++) 14293 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); 14294 14295 /* enable RSM */ 14296 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14297 } 14298 } 14299 14300 /* Is a receive side mapping rule */ 14301 static bool has_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14302 { 14303 return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0; 14304 } 14305 14306 /* 14307 * Add a receive side mapping rule. 14308 */ 14309 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index, 14310 struct rsm_rule_data *rrd) 14311 { 14312 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 14313 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT | 14314 1ull << rule_index | /* enable bit */ 14315 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT); 14316 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 14317 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT | 14318 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT | 14319 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT | 14320 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT | 14321 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT | 14322 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT); 14323 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 14324 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT | 14325 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT | 14326 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT | 14327 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT); 14328 } 14329 14330 /* 14331 * Clear a receive side mapping rule. 14332 */ 14333 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14334 { 14335 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); 14336 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); 14337 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); 14338 } 14339 14340 /* return the number of RSM map table entries that will be used for QOS */ 14341 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 14342 unsigned int *np) 14343 { 14344 int i; 14345 unsigned int m, n; 14346 u8 max_by_vl = 0; 14347 14348 /* is QOS active at all? */ 14349 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS || 14350 num_vls == 1 || 14351 krcvqsset <= 1) 14352 goto no_qos; 14353 14354 /* determine bits for qpn */ 14355 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++) 14356 if (krcvqs[i] > max_by_vl) 14357 max_by_vl = krcvqs[i]; 14358 if (max_by_vl > 32) 14359 goto no_qos; 14360 m = ilog2(__roundup_pow_of_two(max_by_vl)); 14361 14362 /* determine bits for vl */ 14363 n = ilog2(__roundup_pow_of_two(num_vls)); 14364 14365 /* reject if too much is used */ 14366 if ((m + n) > 7) 14367 goto no_qos; 14368 14369 if (mp) 14370 *mp = m; 14371 if (np) 14372 *np = n; 14373 14374 return 1 << (m + n); 14375 14376 no_qos: 14377 if (mp) 14378 *mp = 0; 14379 if (np) 14380 *np = 0; 14381 return 0; 14382 } 14383 14384 /** 14385 * init_qos - init RX qos 14386 * @dd - device data 14387 * @rmt - RSM map table 14388 * 14389 * This routine initializes Rule 0 and the RSM map table to implement 14390 * quality of service (qos). 14391 * 14392 * If all of the limit tests succeed, qos is applied based on the array 14393 * interpretation of krcvqs where entry 0 is VL0. 14394 * 14395 * The number of vl bits (n) and the number of qpn bits (m) are computed to 14396 * feed both the RSM map table and the single rule. 14397 */ 14398 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt) 14399 { 14400 struct rsm_rule_data rrd; 14401 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m; 14402 unsigned int rmt_entries; 14403 u64 reg; 14404 14405 if (!rmt) 14406 goto bail; 14407 rmt_entries = qos_rmt_entries(dd, &m, &n); 14408 if (rmt_entries == 0) 14409 goto bail; 14410 qpns_per_vl = 1 << m; 14411 14412 /* enough room in the map table? */ 14413 rmt_entries = 1 << (m + n); 14414 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES) 14415 goto bail; 14416 14417 /* add qos entries to the the RSM map table */ 14418 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) { 14419 unsigned tctxt; 14420 14421 for (qpn = 0, tctxt = ctxt; 14422 krcvqs[i] && qpn < qpns_per_vl; qpn++) { 14423 unsigned idx, regoff, regidx; 14424 14425 /* generate the index the hardware will produce */ 14426 idx = rmt->used + ((qpn << n) ^ i); 14427 regoff = (idx % 8) * 8; 14428 regidx = idx / 8; 14429 /* replace default with context number */ 14430 reg = rmt->map[regidx]; 14431 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 14432 << regoff); 14433 reg |= (u64)(tctxt++) << regoff; 14434 rmt->map[regidx] = reg; 14435 if (tctxt == ctxt + krcvqs[i]) 14436 tctxt = ctxt; 14437 } 14438 ctxt += krcvqs[i]; 14439 } 14440 14441 rrd.offset = rmt->used; 14442 rrd.pkt_type = 2; 14443 rrd.field1_off = LRH_BTH_MATCH_OFFSET; 14444 rrd.field2_off = LRH_SC_MATCH_OFFSET; 14445 rrd.index1_off = LRH_SC_SELECT_OFFSET; 14446 rrd.index1_width = n; 14447 rrd.index2_off = QPN_SELECT_OFFSET; 14448 rrd.index2_width = m + n; 14449 rrd.mask1 = LRH_BTH_MASK; 14450 rrd.value1 = LRH_BTH_VALUE; 14451 rrd.mask2 = LRH_SC_MASK; 14452 rrd.value2 = LRH_SC_VALUE; 14453 14454 /* add rule 0 */ 14455 add_rsm_rule(dd, RSM_INS_VERBS, &rrd); 14456 14457 /* mark RSM map entries as used */ 14458 rmt->used += rmt_entries; 14459 /* map everything else to the mcast/err/vl15 context */ 14460 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT); 14461 dd->qos_shift = n + 1; 14462 return; 14463 bail: 14464 dd->qos_shift = 1; 14465 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1); 14466 } 14467 14468 static void init_fecn_handling(struct hfi1_devdata *dd, 14469 struct rsm_map_table *rmt) 14470 { 14471 struct rsm_rule_data rrd; 14472 u64 reg; 14473 int i, idx, regoff, regidx, start; 14474 u8 offset; 14475 u32 total_cnt; 14476 14477 if (HFI1_CAP_IS_KSET(TID_RDMA)) 14478 /* Exclude context 0 */ 14479 start = 1; 14480 else 14481 start = dd->first_dyn_alloc_ctxt; 14482 14483 total_cnt = dd->num_rcv_contexts - start; 14484 14485 /* there needs to be enough room in the map table */ 14486 if (rmt->used + total_cnt >= NUM_MAP_ENTRIES) { 14487 dd_dev_err(dd, "FECN handling disabled - too many contexts allocated\n"); 14488 return; 14489 } 14490 14491 /* 14492 * RSM will extract the destination context as an index into the 14493 * map table. The destination contexts are a sequential block 14494 * in the range start...num_rcv_contexts-1 (inclusive). 14495 * Map entries are accessed as offset + extracted value. Adjust 14496 * the added offset so this sequence can be placed anywhere in 14497 * the table - as long as the entries themselves do not wrap. 14498 * There are only enough bits in offset for the table size, so 14499 * start with that to allow for a "negative" offset. 14500 */ 14501 offset = (u8)(NUM_MAP_ENTRIES + rmt->used - start); 14502 14503 for (i = start, idx = rmt->used; i < dd->num_rcv_contexts; 14504 i++, idx++) { 14505 /* replace with identity mapping */ 14506 regoff = (idx % 8) * 8; 14507 regidx = idx / 8; 14508 reg = rmt->map[regidx]; 14509 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff); 14510 reg |= (u64)i << regoff; 14511 rmt->map[regidx] = reg; 14512 } 14513 14514 /* 14515 * For RSM intercept of Expected FECN packets: 14516 * o packet type 0 - expected 14517 * o match on F (bit 95), using select/match 1, and 14518 * o match on SH (bit 133), using select/match 2. 14519 * 14520 * Use index 1 to extract the 8-bit receive context from DestQP 14521 * (start at bit 64). Use that as the RSM map table index. 14522 */ 14523 rrd.offset = offset; 14524 rrd.pkt_type = 0; 14525 rrd.field1_off = 95; 14526 rrd.field2_off = 133; 14527 rrd.index1_off = 64; 14528 rrd.index1_width = 8; 14529 rrd.index2_off = 0; 14530 rrd.index2_width = 0; 14531 rrd.mask1 = 1; 14532 rrd.value1 = 1; 14533 rrd.mask2 = 1; 14534 rrd.value2 = 1; 14535 14536 /* add rule 1 */ 14537 add_rsm_rule(dd, RSM_INS_FECN, &rrd); 14538 14539 rmt->used += total_cnt; 14540 } 14541 14542 static inline bool hfi1_is_rmt_full(int start, int spare) 14543 { 14544 return (start + spare) > NUM_MAP_ENTRIES; 14545 } 14546 14547 static bool hfi1_netdev_update_rmt(struct hfi1_devdata *dd) 14548 { 14549 u8 i, j; 14550 u8 ctx_id = 0; 14551 u64 reg; 14552 u32 regoff; 14553 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd); 14554 int ctxt_count = hfi1_netdev_ctxt_count(dd); 14555 14556 /* We already have contexts mapped in RMT */ 14557 if (has_rsm_rule(dd, RSM_INS_VNIC) || has_rsm_rule(dd, RSM_INS_AIP)) { 14558 dd_dev_info(dd, "Contexts are already mapped in RMT\n"); 14559 return true; 14560 } 14561 14562 if (hfi1_is_rmt_full(rmt_start, NUM_NETDEV_MAP_ENTRIES)) { 14563 dd_dev_err(dd, "Not enough RMT entries used = %d\n", 14564 rmt_start); 14565 return false; 14566 } 14567 14568 dev_dbg(&(dd)->pcidev->dev, "RMT start = %d, end %d\n", 14569 rmt_start, 14570 rmt_start + NUM_NETDEV_MAP_ENTRIES); 14571 14572 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */ 14573 regoff = RCV_RSM_MAP_TABLE + (rmt_start / 8) * 8; 14574 reg = read_csr(dd, regoff); 14575 for (i = 0; i < NUM_NETDEV_MAP_ENTRIES; i++) { 14576 /* Update map register with netdev context */ 14577 j = (rmt_start + i) % 8; 14578 reg &= ~(0xffllu << (j * 8)); 14579 reg |= (u64)hfi1_netdev_get_ctxt(dd, ctx_id++)->ctxt << (j * 8); 14580 /* Wrap up netdev ctx index */ 14581 ctx_id %= ctxt_count; 14582 /* Write back map register */ 14583 if (j == 7 || ((i + 1) == NUM_NETDEV_MAP_ENTRIES)) { 14584 dev_dbg(&(dd)->pcidev->dev, 14585 "RMT[%d] =0x%llx\n", 14586 regoff - RCV_RSM_MAP_TABLE, reg); 14587 14588 write_csr(dd, regoff, reg); 14589 regoff += 8; 14590 if (i < (NUM_NETDEV_MAP_ENTRIES - 1)) 14591 reg = read_csr(dd, regoff); 14592 } 14593 } 14594 14595 return true; 14596 } 14597 14598 static void hfi1_enable_rsm_rule(struct hfi1_devdata *dd, 14599 int rule, struct rsm_rule_data *rrd) 14600 { 14601 if (!hfi1_netdev_update_rmt(dd)) { 14602 dd_dev_err(dd, "Failed to update RMT for RSM%d rule\n", rule); 14603 return; 14604 } 14605 14606 add_rsm_rule(dd, rule, rrd); 14607 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14608 } 14609 14610 void hfi1_init_aip_rsm(struct hfi1_devdata *dd) 14611 { 14612 /* 14613 * go through with the initialisation only if this rule actually doesn't 14614 * exist yet 14615 */ 14616 if (atomic_fetch_inc(&dd->ipoib_rsm_usr_num) == 0) { 14617 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd); 14618 struct rsm_rule_data rrd = { 14619 .offset = rmt_start, 14620 .pkt_type = IB_PACKET_TYPE, 14621 .field1_off = LRH_BTH_MATCH_OFFSET, 14622 .mask1 = LRH_BTH_MASK, 14623 .value1 = LRH_BTH_VALUE, 14624 .field2_off = BTH_DESTQP_MATCH_OFFSET, 14625 .mask2 = BTH_DESTQP_MASK, 14626 .value2 = BTH_DESTQP_VALUE, 14627 .index1_off = DETH_AIP_SQPN_SELECT_OFFSET + 14628 ilog2(NUM_NETDEV_MAP_ENTRIES), 14629 .index1_width = ilog2(NUM_NETDEV_MAP_ENTRIES), 14630 .index2_off = DETH_AIP_SQPN_SELECT_OFFSET, 14631 .index2_width = ilog2(NUM_NETDEV_MAP_ENTRIES) 14632 }; 14633 14634 hfi1_enable_rsm_rule(dd, RSM_INS_AIP, &rrd); 14635 } 14636 } 14637 14638 /* Initialize RSM for VNIC */ 14639 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd) 14640 { 14641 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd); 14642 struct rsm_rule_data rrd = { 14643 /* Add rule for vnic */ 14644 .offset = rmt_start, 14645 .pkt_type = 4, 14646 /* Match 16B packets */ 14647 .field1_off = L2_TYPE_MATCH_OFFSET, 14648 .mask1 = L2_TYPE_MASK, 14649 .value1 = L2_16B_VALUE, 14650 /* Match ETH L4 packets */ 14651 .field2_off = L4_TYPE_MATCH_OFFSET, 14652 .mask2 = L4_16B_TYPE_MASK, 14653 .value2 = L4_16B_ETH_VALUE, 14654 /* Calc context from veswid and entropy */ 14655 .index1_off = L4_16B_HDR_VESWID_OFFSET, 14656 .index1_width = ilog2(NUM_NETDEV_MAP_ENTRIES), 14657 .index2_off = L2_16B_ENTROPY_OFFSET, 14658 .index2_width = ilog2(NUM_NETDEV_MAP_ENTRIES) 14659 }; 14660 14661 hfi1_enable_rsm_rule(dd, RSM_INS_VNIC, &rrd); 14662 } 14663 14664 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd) 14665 { 14666 clear_rsm_rule(dd, RSM_INS_VNIC); 14667 } 14668 14669 void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd) 14670 { 14671 /* only actually clear the rule if it's the last user asking to do so */ 14672 if (atomic_fetch_add_unless(&dd->ipoib_rsm_usr_num, -1, 0) == 1) 14673 clear_rsm_rule(dd, RSM_INS_AIP); 14674 } 14675 14676 static int init_rxe(struct hfi1_devdata *dd) 14677 { 14678 struct rsm_map_table *rmt; 14679 u64 val; 14680 14681 /* enable all receive errors */ 14682 write_csr(dd, RCV_ERR_MASK, ~0ull); 14683 14684 rmt = alloc_rsm_map_table(dd); 14685 if (!rmt) 14686 return -ENOMEM; 14687 14688 /* set up QOS, including the QPN map table */ 14689 init_qos(dd, rmt); 14690 init_fecn_handling(dd, rmt); 14691 complete_rsm_map_table(dd, rmt); 14692 /* record number of used rsm map entries for netdev */ 14693 hfi1_netdev_set_free_rmt_idx(dd, rmt->used); 14694 kfree(rmt); 14695 14696 /* 14697 * make sure RcvCtrl.RcvWcb <= PCIe Device Control 14698 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config 14699 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one 14700 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and 14701 * Max_PayLoad_Size set to its minimum of 128. 14702 * 14703 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0 14704 * (64 bytes). Max_Payload_Size is possibly modified upward in 14705 * tune_pcie_caps() which is called after this routine. 14706 */ 14707 14708 /* Have 16 bytes (4DW) of bypass header available in header queue */ 14709 val = read_csr(dd, RCV_BYPASS); 14710 val &= ~RCV_BYPASS_HDR_SIZE_SMASK; 14711 val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) << 14712 RCV_BYPASS_HDR_SIZE_SHIFT); 14713 write_csr(dd, RCV_BYPASS, val); 14714 return 0; 14715 } 14716 14717 static void init_other(struct hfi1_devdata *dd) 14718 { 14719 /* enable all CCE errors */ 14720 write_csr(dd, CCE_ERR_MASK, ~0ull); 14721 /* enable *some* Misc errors */ 14722 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); 14723 /* enable all DC errors, except LCB */ 14724 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); 14725 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); 14726 } 14727 14728 /* 14729 * Fill out the given AU table using the given CU. A CU is defined in terms 14730 * AUs. The table is a an encoding: given the index, how many AUs does that 14731 * represent? 14732 * 14733 * NOTE: Assumes that the register layout is the same for the 14734 * local and remote tables. 14735 */ 14736 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu, 14737 u32 csr0to3, u32 csr4to7) 14738 { 14739 write_csr(dd, csr0to3, 14740 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT | 14741 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT | 14742 2ull * cu << 14743 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT | 14744 4ull * cu << 14745 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT); 14746 write_csr(dd, csr4to7, 14747 8ull * cu << 14748 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT | 14749 16ull * cu << 14750 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT | 14751 32ull * cu << 14752 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT | 14753 64ull * cu << 14754 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT); 14755 } 14756 14757 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14758 { 14759 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3, 14760 SEND_CM_LOCAL_AU_TABLE4_TO7); 14761 } 14762 14763 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14764 { 14765 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3, 14766 SEND_CM_REMOTE_AU_TABLE4_TO7); 14767 } 14768 14769 static void init_txe(struct hfi1_devdata *dd) 14770 { 14771 int i; 14772 14773 /* enable all PIO, SDMA, general, and Egress errors */ 14774 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); 14775 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); 14776 write_csr(dd, SEND_ERR_MASK, ~0ull); 14777 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); 14778 14779 /* enable all per-context and per-SDMA engine errors */ 14780 for (i = 0; i < chip_send_contexts(dd); i++) 14781 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull); 14782 for (i = 0; i < chip_sdma_engines(dd); i++) 14783 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull); 14784 14785 /* set the local CU to AU mapping */ 14786 assign_local_cm_au_table(dd, dd->vcu); 14787 14788 /* 14789 * Set reasonable default for Credit Return Timer 14790 * Don't set on Simulator - causes it to choke. 14791 */ 14792 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 14793 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); 14794 } 14795 14796 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14797 u16 jkey) 14798 { 14799 u8 hw_ctxt; 14800 u64 reg; 14801 14802 if (!rcd || !rcd->sc) 14803 return -EINVAL; 14804 14805 hw_ctxt = rcd->sc->hw_context; 14806 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */ 14807 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) << 14808 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT); 14809 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */ 14810 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY)) 14811 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK; 14812 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg); 14813 /* 14814 * Enable send-side J_KEY integrity check, unless this is A0 h/w 14815 */ 14816 if (!is_ax(dd)) { 14817 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14818 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14819 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14820 } 14821 14822 /* Enable J_KEY check on receive context. */ 14823 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK | 14824 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) << 14825 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT); 14826 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg); 14827 14828 return 0; 14829 } 14830 14831 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 14832 { 14833 u8 hw_ctxt; 14834 u64 reg; 14835 14836 if (!rcd || !rcd->sc) 14837 return -EINVAL; 14838 14839 hw_ctxt = rcd->sc->hw_context; 14840 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0); 14841 /* 14842 * Disable send-side J_KEY integrity check, unless this is A0 h/w. 14843 * This check would not have been enabled for A0 h/w, see 14844 * set_ctxt_jkey(). 14845 */ 14846 if (!is_ax(dd)) { 14847 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14848 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14849 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14850 } 14851 /* Turn off the J_KEY on the receive side */ 14852 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0); 14853 14854 return 0; 14855 } 14856 14857 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14858 u16 pkey) 14859 { 14860 u8 hw_ctxt; 14861 u64 reg; 14862 14863 if (!rcd || !rcd->sc) 14864 return -EINVAL; 14865 14866 hw_ctxt = rcd->sc->hw_context; 14867 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) << 14868 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT; 14869 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg); 14870 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14871 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14872 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK; 14873 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14874 14875 return 0; 14876 } 14877 14878 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt) 14879 { 14880 u8 hw_ctxt; 14881 u64 reg; 14882 14883 if (!ctxt || !ctxt->sc) 14884 return -EINVAL; 14885 14886 hw_ctxt = ctxt->sc->hw_context; 14887 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14888 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14889 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14890 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0); 14891 14892 return 0; 14893 } 14894 14895 /* 14896 * Start doing the clean up the the chip. Our clean up happens in multiple 14897 * stages and this is just the first. 14898 */ 14899 void hfi1_start_cleanup(struct hfi1_devdata *dd) 14900 { 14901 aspm_exit(dd); 14902 free_cntrs(dd); 14903 free_rcverr(dd); 14904 finish_chip_resources(dd); 14905 } 14906 14907 #define HFI_BASE_GUID(dev) \ 14908 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT)) 14909 14910 /* 14911 * Information can be shared between the two HFIs on the same ASIC 14912 * in the same OS. This function finds the peer device and sets 14913 * up a shared structure. 14914 */ 14915 static int init_asic_data(struct hfi1_devdata *dd) 14916 { 14917 unsigned long index; 14918 struct hfi1_devdata *peer; 14919 struct hfi1_asic_data *asic_data; 14920 int ret = 0; 14921 14922 /* pre-allocate the asic structure in case we are the first device */ 14923 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL); 14924 if (!asic_data) 14925 return -ENOMEM; 14926 14927 xa_lock_irq(&hfi1_dev_table); 14928 /* Find our peer device */ 14929 xa_for_each(&hfi1_dev_table, index, peer) { 14930 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(peer)) && 14931 dd->unit != peer->unit) 14932 break; 14933 } 14934 14935 if (peer) { 14936 /* use already allocated structure */ 14937 dd->asic_data = peer->asic_data; 14938 kfree(asic_data); 14939 } else { 14940 dd->asic_data = asic_data; 14941 mutex_init(&dd->asic_data->asic_resource_mutex); 14942 } 14943 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */ 14944 xa_unlock_irq(&hfi1_dev_table); 14945 14946 /* first one through - set up i2c devices */ 14947 if (!peer) 14948 ret = set_up_i2c(dd, dd->asic_data); 14949 14950 return ret; 14951 } 14952 14953 /* 14954 * Set dd->boardname. Use a generic name if a name is not returned from 14955 * EFI variable space. 14956 * 14957 * Return 0 on success, -ENOMEM if space could not be allocated. 14958 */ 14959 static int obtain_boardname(struct hfi1_devdata *dd) 14960 { 14961 /* generic board description */ 14962 const char generic[] = 14963 "Intel Omni-Path Host Fabric Interface Adapter 100 Series"; 14964 unsigned long size; 14965 int ret; 14966 14967 ret = read_hfi1_efi_var(dd, "description", &size, 14968 (void **)&dd->boardname); 14969 if (ret) { 14970 dd_dev_info(dd, "Board description not found\n"); 14971 /* use generic description */ 14972 dd->boardname = kstrdup(generic, GFP_KERNEL); 14973 if (!dd->boardname) 14974 return -ENOMEM; 14975 } 14976 return 0; 14977 } 14978 14979 /* 14980 * Check the interrupt registers to make sure that they are mapped correctly. 14981 * It is intended to help user identify any mismapping by VMM when the driver 14982 * is running in a VM. This function should only be called before interrupt 14983 * is set up properly. 14984 * 14985 * Return 0 on success, -EINVAL on failure. 14986 */ 14987 static int check_int_registers(struct hfi1_devdata *dd) 14988 { 14989 u64 reg; 14990 u64 all_bits = ~(u64)0; 14991 u64 mask; 14992 14993 /* Clear CceIntMask[0] to avoid raising any interrupts */ 14994 mask = read_csr(dd, CCE_INT_MASK); 14995 write_csr(dd, CCE_INT_MASK, 0ull); 14996 reg = read_csr(dd, CCE_INT_MASK); 14997 if (reg) 14998 goto err_exit; 14999 15000 /* Clear all interrupt status bits */ 15001 write_csr(dd, CCE_INT_CLEAR, all_bits); 15002 reg = read_csr(dd, CCE_INT_STATUS); 15003 if (reg) 15004 goto err_exit; 15005 15006 /* Set all interrupt status bits */ 15007 write_csr(dd, CCE_INT_FORCE, all_bits); 15008 reg = read_csr(dd, CCE_INT_STATUS); 15009 if (reg != all_bits) 15010 goto err_exit; 15011 15012 /* Restore the interrupt mask */ 15013 write_csr(dd, CCE_INT_CLEAR, all_bits); 15014 write_csr(dd, CCE_INT_MASK, mask); 15015 15016 return 0; 15017 err_exit: 15018 write_csr(dd, CCE_INT_MASK, mask); 15019 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n"); 15020 return -EINVAL; 15021 } 15022 15023 /** 15024 * hfi1_init_dd() - Initialize most of the dd structure. 15025 * @dev: the pci_dev for hfi1_ib device 15026 * @ent: pci_device_id struct for this dev 15027 * 15028 * This is global, and is called directly at init to set up the 15029 * chip-specific function pointers for later use. 15030 */ 15031 int hfi1_init_dd(struct hfi1_devdata *dd) 15032 { 15033 struct pci_dev *pdev = dd->pcidev; 15034 struct hfi1_pportdata *ppd; 15035 u64 reg; 15036 int i, ret; 15037 static const char * const inames[] = { /* implementation names */ 15038 "RTL silicon", 15039 "RTL VCS simulation", 15040 "RTL FPGA emulation", 15041 "Functional simulator" 15042 }; 15043 struct pci_dev *parent = pdev->bus->self; 15044 u32 sdma_engines = chip_sdma_engines(dd); 15045 15046 ppd = dd->pport; 15047 for (i = 0; i < dd->num_pports; i++, ppd++) { 15048 int vl; 15049 /* init common fields */ 15050 hfi1_init_pportdata(pdev, ppd, dd, 0, 1); 15051 /* DC supports 4 link widths */ 15052 ppd->link_width_supported = 15053 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X | 15054 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X; 15055 ppd->link_width_downgrade_supported = 15056 ppd->link_width_supported; 15057 /* start out enabling only 4X */ 15058 ppd->link_width_enabled = OPA_LINK_WIDTH_4X; 15059 ppd->link_width_downgrade_enabled = 15060 ppd->link_width_downgrade_supported; 15061 /* link width active is 0 when link is down */ 15062 /* link width downgrade active is 0 when link is down */ 15063 15064 if (num_vls < HFI1_MIN_VLS_SUPPORTED || 15065 num_vls > HFI1_MAX_VLS_SUPPORTED) { 15066 dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n", 15067 num_vls, HFI1_MAX_VLS_SUPPORTED); 15068 num_vls = HFI1_MAX_VLS_SUPPORTED; 15069 } 15070 ppd->vls_supported = num_vls; 15071 ppd->vls_operational = ppd->vls_supported; 15072 /* Set the default MTU. */ 15073 for (vl = 0; vl < num_vls; vl++) 15074 dd->vld[vl].mtu = hfi1_max_mtu; 15075 dd->vld[15].mtu = MAX_MAD_PACKET; 15076 /* 15077 * Set the initial values to reasonable default, will be set 15078 * for real when link is up. 15079 */ 15080 ppd->overrun_threshold = 0x4; 15081 ppd->phy_error_threshold = 0xf; 15082 ppd->port_crc_mode_enabled = link_crc_mask; 15083 /* initialize supported LTP CRC mode */ 15084 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 15085 /* initialize enabled LTP CRC mode */ 15086 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4; 15087 /* start in offline */ 15088 ppd->host_link_state = HLS_DN_OFFLINE; 15089 init_vl_arb_caches(ppd); 15090 } 15091 15092 /* 15093 * Do remaining PCIe setup and save PCIe values in dd. 15094 * Any error printing is already done by the init code. 15095 * On return, we have the chip mapped. 15096 */ 15097 ret = hfi1_pcie_ddinit(dd, pdev); 15098 if (ret < 0) 15099 goto bail_free; 15100 15101 /* Save PCI space registers to rewrite after device reset */ 15102 ret = save_pci_variables(dd); 15103 if (ret < 0) 15104 goto bail_cleanup; 15105 15106 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT) 15107 & CCE_REVISION_CHIP_REV_MAJOR_MASK; 15108 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT) 15109 & CCE_REVISION_CHIP_REV_MINOR_MASK; 15110 15111 /* 15112 * Check interrupt registers mapping if the driver has no access to 15113 * the upstream component. In this case, it is likely that the driver 15114 * is running in a VM. 15115 */ 15116 if (!parent) { 15117 ret = check_int_registers(dd); 15118 if (ret) 15119 goto bail_cleanup; 15120 } 15121 15122 /* 15123 * obtain the hardware ID - NOT related to unit, which is a 15124 * software enumeration 15125 */ 15126 reg = read_csr(dd, CCE_REVISION2); 15127 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT) 15128 & CCE_REVISION2_HFI_ID_MASK; 15129 /* the variable size will remove unwanted bits */ 15130 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT; 15131 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT; 15132 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n", 15133 dd->icode < ARRAY_SIZE(inames) ? 15134 inames[dd->icode] : "unknown", (int)dd->irev); 15135 15136 /* speeds the hardware can support */ 15137 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G; 15138 /* speeds allowed to run at */ 15139 dd->pport->link_speed_enabled = dd->pport->link_speed_supported; 15140 /* give a reasonable active value, will be set on link up */ 15141 dd->pport->link_speed_active = OPA_LINK_SPEED_25G; 15142 15143 /* fix up link widths for emulation _p */ 15144 ppd = dd->pport; 15145 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) { 15146 ppd->link_width_supported = 15147 ppd->link_width_enabled = 15148 ppd->link_width_downgrade_supported = 15149 ppd->link_width_downgrade_enabled = 15150 OPA_LINK_WIDTH_1X; 15151 } 15152 /* insure num_vls isn't larger than number of sdma engines */ 15153 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > sdma_engines) { 15154 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n", 15155 num_vls, sdma_engines); 15156 num_vls = sdma_engines; 15157 ppd->vls_supported = sdma_engines; 15158 ppd->vls_operational = ppd->vls_supported; 15159 } 15160 15161 /* 15162 * Convert the ns parameter to the 64 * cclocks used in the CSR. 15163 * Limit the max if larger than the field holds. If timeout is 15164 * non-zero, then the calculated field will be at least 1. 15165 * 15166 * Must be after icode is set up - the cclock rate depends 15167 * on knowing the hardware being used. 15168 */ 15169 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64; 15170 if (dd->rcv_intr_timeout_csr > 15171 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK) 15172 dd->rcv_intr_timeout_csr = 15173 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK; 15174 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout) 15175 dd->rcv_intr_timeout_csr = 1; 15176 15177 /* needs to be done before we look for the peer device */ 15178 read_guid(dd); 15179 15180 /* set up shared ASIC data with peer device */ 15181 ret = init_asic_data(dd); 15182 if (ret) 15183 goto bail_cleanup; 15184 15185 /* obtain chip sizes, reset chip CSRs */ 15186 ret = init_chip(dd); 15187 if (ret) 15188 goto bail_cleanup; 15189 15190 /* read in the PCIe link speed information */ 15191 ret = pcie_speeds(dd); 15192 if (ret) 15193 goto bail_cleanup; 15194 15195 /* call before get_platform_config(), after init_chip_resources() */ 15196 ret = eprom_init(dd); 15197 if (ret) 15198 goto bail_free_rcverr; 15199 15200 /* Needs to be called before hfi1_firmware_init */ 15201 get_platform_config(dd); 15202 15203 /* read in firmware */ 15204 ret = hfi1_firmware_init(dd); 15205 if (ret) 15206 goto bail_cleanup; 15207 15208 /* 15209 * In general, the PCIe Gen3 transition must occur after the 15210 * chip has been idled (so it won't initiate any PCIe transactions 15211 * e.g. an interrupt) and before the driver changes any registers 15212 * (the transition will reset the registers). 15213 * 15214 * In particular, place this call after: 15215 * - init_chip() - the chip will not initiate any PCIe transactions 15216 * - pcie_speeds() - reads the current link speed 15217 * - hfi1_firmware_init() - the needed firmware is ready to be 15218 * downloaded 15219 */ 15220 ret = do_pcie_gen3_transition(dd); 15221 if (ret) 15222 goto bail_cleanup; 15223 15224 /* 15225 * This should probably occur in hfi1_pcie_init(), but historically 15226 * occurs after the do_pcie_gen3_transition() code. 15227 */ 15228 tune_pcie_caps(dd); 15229 15230 /* start setting dd values and adjusting CSRs */ 15231 init_early_variables(dd); 15232 15233 parse_platform_config(dd); 15234 15235 ret = obtain_boardname(dd); 15236 if (ret) 15237 goto bail_cleanup; 15238 15239 snprintf(dd->boardversion, BOARD_VERS_MAX, 15240 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n", 15241 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN, 15242 (u32)dd->majrev, 15243 (u32)dd->minrev, 15244 (dd->revision >> CCE_REVISION_SW_SHIFT) 15245 & CCE_REVISION_SW_MASK); 15246 15247 /* alloc netdev data */ 15248 if (hfi1_netdev_alloc(dd)) 15249 goto bail_cleanup; 15250 15251 ret = set_up_context_variables(dd); 15252 if (ret) 15253 goto bail_cleanup; 15254 15255 /* set initial RXE CSRs */ 15256 ret = init_rxe(dd); 15257 if (ret) 15258 goto bail_cleanup; 15259 15260 /* set initial TXE CSRs */ 15261 init_txe(dd); 15262 /* set initial non-RXE, non-TXE CSRs */ 15263 init_other(dd); 15264 /* set up KDETH QP prefix in both RX and TX CSRs */ 15265 init_kdeth_qp(dd); 15266 15267 ret = hfi1_dev_affinity_init(dd); 15268 if (ret) 15269 goto bail_cleanup; 15270 15271 /* send contexts must be set up before receive contexts */ 15272 ret = init_send_contexts(dd); 15273 if (ret) 15274 goto bail_cleanup; 15275 15276 ret = hfi1_create_kctxts(dd); 15277 if (ret) 15278 goto bail_cleanup; 15279 15280 /* 15281 * Initialize aspm, to be done after gen3 transition and setting up 15282 * contexts and before enabling interrupts 15283 */ 15284 aspm_init(dd); 15285 15286 ret = init_pervl_scs(dd); 15287 if (ret) 15288 goto bail_cleanup; 15289 15290 /* sdma init */ 15291 for (i = 0; i < dd->num_pports; ++i) { 15292 ret = sdma_init(dd, i); 15293 if (ret) 15294 goto bail_cleanup; 15295 } 15296 15297 /* use contexts created by hfi1_create_kctxts */ 15298 ret = set_up_interrupts(dd); 15299 if (ret) 15300 goto bail_cleanup; 15301 15302 ret = hfi1_comp_vectors_set_up(dd); 15303 if (ret) 15304 goto bail_clear_intr; 15305 15306 /* set up LCB access - must be after set_up_interrupts() */ 15307 init_lcb_access(dd); 15308 15309 /* 15310 * Serial number is created from the base guid: 15311 * [27:24] = base guid [38:35] 15312 * [23: 0] = base guid [23: 0] 15313 */ 15314 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n", 15315 (dd->base_guid & 0xFFFFFF) | 15316 ((dd->base_guid >> 11) & 0xF000000)); 15317 15318 dd->oui1 = dd->base_guid >> 56 & 0xFF; 15319 dd->oui2 = dd->base_guid >> 48 & 0xFF; 15320 dd->oui3 = dd->base_guid >> 40 & 0xFF; 15321 15322 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */ 15323 if (ret) 15324 goto bail_clear_intr; 15325 15326 thermal_init(dd); 15327 15328 ret = init_cntrs(dd); 15329 if (ret) 15330 goto bail_clear_intr; 15331 15332 ret = init_rcverr(dd); 15333 if (ret) 15334 goto bail_free_cntrs; 15335 15336 init_completion(&dd->user_comp); 15337 15338 /* The user refcount starts with one to inidicate an active device */ 15339 atomic_set(&dd->user_refcount, 1); 15340 15341 goto bail; 15342 15343 bail_free_rcverr: 15344 free_rcverr(dd); 15345 bail_free_cntrs: 15346 free_cntrs(dd); 15347 bail_clear_intr: 15348 hfi1_comp_vectors_clean_up(dd); 15349 msix_clean_up_interrupts(dd); 15350 bail_cleanup: 15351 hfi1_netdev_free(dd); 15352 hfi1_pcie_ddcleanup(dd); 15353 bail_free: 15354 hfi1_free_devdata(dd); 15355 bail: 15356 return ret; 15357 } 15358 15359 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate, 15360 u32 dw_len) 15361 { 15362 u32 delta_cycles; 15363 u32 current_egress_rate = ppd->current_egress_rate; 15364 /* rates here are in units of 10^6 bits/sec */ 15365 15366 if (desired_egress_rate == -1) 15367 return 0; /* shouldn't happen */ 15368 15369 if (desired_egress_rate >= current_egress_rate) 15370 return 0; /* we can't help go faster, only slower */ 15371 15372 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) - 15373 egress_cycles(dw_len * 4, current_egress_rate); 15374 15375 return (u16)delta_cycles; 15376 } 15377 15378 /** 15379 * create_pbc - build a pbc for transmission 15380 * @flags: special case flags or-ed in built pbc 15381 * @srate: static rate 15382 * @vl: vl 15383 * @dwlen: dword length (header words + data words + pbc words) 15384 * 15385 * Create a PBC with the given flags, rate, VL, and length. 15386 * 15387 * NOTE: The PBC created will not insert any HCRC - all callers but one are 15388 * for verbs, which does not use this PSM feature. The lone other caller 15389 * is for the diagnostic interface which calls this if the user does not 15390 * supply their own PBC. 15391 */ 15392 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, 15393 u32 dw_len) 15394 { 15395 u64 pbc, delay = 0; 15396 15397 if (unlikely(srate_mbs)) 15398 delay = delay_cycles(ppd, srate_mbs, dw_len); 15399 15400 pbc = flags 15401 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT) 15402 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT) 15403 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT 15404 | (dw_len & PBC_LENGTH_DWS_MASK) 15405 << PBC_LENGTH_DWS_SHIFT; 15406 15407 return pbc; 15408 } 15409 15410 #define SBUS_THERMAL 0x4f 15411 #define SBUS_THERM_MONITOR_MODE 0x1 15412 15413 #define THERM_FAILURE(dev, ret, reason) \ 15414 dd_dev_err((dd), \ 15415 "Thermal sensor initialization failed: %s (%d)\n", \ 15416 (reason), (ret)) 15417 15418 /* 15419 * Initialize the thermal sensor. 15420 * 15421 * After initialization, enable polling of thermal sensor through 15422 * SBus interface. In order for this to work, the SBus Master 15423 * firmware has to be loaded due to the fact that the HW polling 15424 * logic uses SBus interrupts, which are not supported with 15425 * default firmware. Otherwise, no data will be returned through 15426 * the ASIC_STS_THERM CSR. 15427 */ 15428 static int thermal_init(struct hfi1_devdata *dd) 15429 { 15430 int ret = 0; 15431 15432 if (dd->icode != ICODE_RTL_SILICON || 15433 check_chip_resource(dd, CR_THERM_INIT, NULL)) 15434 return ret; 15435 15436 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 15437 if (ret) { 15438 THERM_FAILURE(dd, ret, "Acquire SBus"); 15439 return ret; 15440 } 15441 15442 dd_dev_info(dd, "Initializing thermal sensor\n"); 15443 /* Disable polling of thermal readings */ 15444 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 15445 msleep(100); 15446 /* Thermal Sensor Initialization */ 15447 /* Step 1: Reset the Thermal SBus Receiver */ 15448 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15449 RESET_SBUS_RECEIVER, 0); 15450 if (ret) { 15451 THERM_FAILURE(dd, ret, "Bus Reset"); 15452 goto done; 15453 } 15454 /* Step 2: Set Reset bit in Thermal block */ 15455 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15456 WRITE_SBUS_RECEIVER, 0x1); 15457 if (ret) { 15458 THERM_FAILURE(dd, ret, "Therm Block Reset"); 15459 goto done; 15460 } 15461 /* Step 3: Write clock divider value (100MHz -> 2MHz) */ 15462 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1, 15463 WRITE_SBUS_RECEIVER, 0x32); 15464 if (ret) { 15465 THERM_FAILURE(dd, ret, "Write Clock Div"); 15466 goto done; 15467 } 15468 /* Step 4: Select temperature mode */ 15469 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3, 15470 WRITE_SBUS_RECEIVER, 15471 SBUS_THERM_MONITOR_MODE); 15472 if (ret) { 15473 THERM_FAILURE(dd, ret, "Write Mode Sel"); 15474 goto done; 15475 } 15476 /* Step 5: De-assert block reset and start conversion */ 15477 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15478 WRITE_SBUS_RECEIVER, 0x2); 15479 if (ret) { 15480 THERM_FAILURE(dd, ret, "Write Reset Deassert"); 15481 goto done; 15482 } 15483 /* Step 5.1: Wait for first conversion (21.5ms per spec) */ 15484 msleep(22); 15485 15486 /* Enable polling of thermal readings */ 15487 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 15488 15489 /* Set initialized flag */ 15490 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0); 15491 if (ret) 15492 THERM_FAILURE(dd, ret, "Unable to set thermal init flag"); 15493 15494 done: 15495 release_chip_resource(dd, CR_SBUS); 15496 return ret; 15497 } 15498 15499 static void handle_temp_err(struct hfi1_devdata *dd) 15500 { 15501 struct hfi1_pportdata *ppd = &dd->pport[0]; 15502 /* 15503 * Thermal Critical Interrupt 15504 * Put the device into forced freeze mode, take link down to 15505 * offline, and put DC into reset. 15506 */ 15507 dd_dev_emerg(dd, 15508 "Critical temperature reached! Forcing device into freeze mode!\n"); 15509 dd->flags |= HFI1_FORCED_FREEZE; 15510 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT); 15511 /* 15512 * Shut DC down as much and as quickly as possible. 15513 * 15514 * Step 1: Take the link down to OFFLINE. This will cause the 15515 * 8051 to put the Serdes in reset. However, we don't want to 15516 * go through the entire link state machine since we want to 15517 * shutdown ASAP. Furthermore, this is not a graceful shutdown 15518 * but rather an attempt to save the chip. 15519 * Code below is almost the same as quiet_serdes() but avoids 15520 * all the extra work and the sleeps. 15521 */ 15522 ppd->driver_link_ready = 0; 15523 ppd->link_enabled = 0; 15524 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) | 15525 PLS_OFFLINE); 15526 /* 15527 * Step 2: Shutdown LCB and 8051 15528 * After shutdown, do not restore DC_CFG_RESET value. 15529 */ 15530 dc_shutdown(dd); 15531 } 15532