1 /* 2 * Copyright(c) 2015 - 2018 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 /* 49 * This file contains all of the code that is specific to the HFI chip 50 */ 51 52 #include <linux/pci.h> 53 #include <linux/delay.h> 54 #include <linux/interrupt.h> 55 #include <linux/module.h> 56 57 #include "hfi.h" 58 #include "trace.h" 59 #include "mad.h" 60 #include "pio.h" 61 #include "sdma.h" 62 #include "eprom.h" 63 #include "efivar.h" 64 #include "platform.h" 65 #include "aspm.h" 66 #include "affinity.h" 67 #include "debugfs.h" 68 #include "fault.h" 69 70 uint kdeth_qp; 71 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO); 72 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix"); 73 74 uint num_vls = HFI1_MAX_VLS_SUPPORTED; 75 module_param(num_vls, uint, S_IRUGO); 76 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 77 78 /* 79 * Default time to aggregate two 10K packets from the idle state 80 * (timer not running). The timer starts at the end of the first packet, 81 * so only the time for one 10K packet and header plus a bit extra is needed. 82 * 10 * 1024 + 64 header byte = 10304 byte 83 * 10304 byte / 12.5 GB/s = 824.32ns 84 */ 85 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */ 86 module_param(rcv_intr_timeout, uint, S_IRUGO); 87 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns"); 88 89 uint rcv_intr_count = 16; /* same as qib */ 90 module_param(rcv_intr_count, uint, S_IRUGO); 91 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count"); 92 93 ushort link_crc_mask = SUPPORTED_CRCS; 94 module_param(link_crc_mask, ushort, S_IRUGO); 95 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link"); 96 97 uint loopback; 98 module_param_named(loopback, loopback, uint, S_IRUGO); 99 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable"); 100 101 /* Other driver tunables */ 102 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/ 103 static ushort crc_14b_sideband = 1; 104 static uint use_flr = 1; 105 uint quick_linkup; /* skip LNI */ 106 107 struct flag_table { 108 u64 flag; /* the flag */ 109 char *str; /* description string */ 110 u16 extra; /* extra information */ 111 u16 unused0; 112 u32 unused1; 113 }; 114 115 /* str must be a string constant */ 116 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra} 117 #define FLAG_ENTRY0(str, flag) {flag, str, 0} 118 119 /* Send Error Consequences */ 120 #define SEC_WRITE_DROPPED 0x1 121 #define SEC_PACKET_DROPPED 0x2 122 #define SEC_SC_HALTED 0x4 /* per-context only */ 123 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */ 124 125 #define DEFAULT_KRCVQS 2 126 #define MIN_KERNEL_KCTXTS 2 127 #define FIRST_KERNEL_KCTXT 1 128 129 /* 130 * RSM instance allocation 131 * 0 - Verbs 132 * 1 - User Fecn Handling 133 * 2 - Vnic 134 */ 135 #define RSM_INS_VERBS 0 136 #define RSM_INS_FECN 1 137 #define RSM_INS_VNIC 2 138 139 /* Bit offset into the GUID which carries HFI id information */ 140 #define GUID_HFI_INDEX_SHIFT 39 141 142 /* extract the emulation revision */ 143 #define emulator_rev(dd) ((dd)->irev >> 8) 144 /* parallel and serial emulation versions are 3 and 4 respectively */ 145 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3) 146 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4) 147 148 /* RSM fields for Verbs */ 149 /* packet type */ 150 #define IB_PACKET_TYPE 2ull 151 #define QW_SHIFT 6ull 152 /* QPN[7..1] */ 153 #define QPN_WIDTH 7ull 154 155 /* LRH.BTH: QW 0, OFFSET 48 - for match */ 156 #define LRH_BTH_QW 0ull 157 #define LRH_BTH_BIT_OFFSET 48ull 158 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off)) 159 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET) 160 #define LRH_BTH_SELECT 161 #define LRH_BTH_MASK 3ull 162 #define LRH_BTH_VALUE 2ull 163 164 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */ 165 #define LRH_SC_QW 0ull 166 #define LRH_SC_BIT_OFFSET 56ull 167 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off)) 168 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET) 169 #define LRH_SC_MASK 128ull 170 #define LRH_SC_VALUE 0ull 171 172 /* SC[n..0] QW 0, OFFSET 60 - for select */ 173 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull)) 174 175 /* QPN[m+n:1] QW 1, OFFSET 1 */ 176 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull)) 177 178 /* RSM fields for Vnic */ 179 /* L2_TYPE: QW 0, OFFSET 61 - for match */ 180 #define L2_TYPE_QW 0ull 181 #define L2_TYPE_BIT_OFFSET 61ull 182 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off)) 183 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET) 184 #define L2_TYPE_MASK 3ull 185 #define L2_16B_VALUE 2ull 186 187 /* L4_TYPE QW 1, OFFSET 0 - for match */ 188 #define L4_TYPE_QW 1ull 189 #define L4_TYPE_BIT_OFFSET 0ull 190 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off)) 191 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET) 192 #define L4_16B_TYPE_MASK 0xFFull 193 #define L4_16B_ETH_VALUE 0x78ull 194 195 /* 16B VESWID - for select */ 196 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull)) 197 /* 16B ENTROPY - for select */ 198 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull)) 199 200 /* defines to build power on SC2VL table */ 201 #define SC2VL_VAL( \ 202 num, \ 203 sc0, sc0val, \ 204 sc1, sc1val, \ 205 sc2, sc2val, \ 206 sc3, sc3val, \ 207 sc4, sc4val, \ 208 sc5, sc5val, \ 209 sc6, sc6val, \ 210 sc7, sc7val) \ 211 ( \ 212 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \ 213 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \ 214 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \ 215 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \ 216 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \ 217 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \ 218 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \ 219 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \ 220 ) 221 222 #define DC_SC_VL_VAL( \ 223 range, \ 224 e0, e0val, \ 225 e1, e1val, \ 226 e2, e2val, \ 227 e3, e3val, \ 228 e4, e4val, \ 229 e5, e5val, \ 230 e6, e6val, \ 231 e7, e7val, \ 232 e8, e8val, \ 233 e9, e9val, \ 234 e10, e10val, \ 235 e11, e11val, \ 236 e12, e12val, \ 237 e13, e13val, \ 238 e14, e14val, \ 239 e15, e15val) \ 240 ( \ 241 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \ 242 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \ 243 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \ 244 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \ 245 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \ 246 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \ 247 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \ 248 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \ 249 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \ 250 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \ 251 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \ 252 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \ 253 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \ 254 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \ 255 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \ 256 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \ 257 ) 258 259 /* all CceStatus sub-block freeze bits */ 260 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \ 261 | CCE_STATUS_RXE_FROZE_SMASK \ 262 | CCE_STATUS_TXE_FROZE_SMASK \ 263 | CCE_STATUS_TXE_PIO_FROZE_SMASK) 264 /* all CceStatus sub-block TXE pause bits */ 265 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \ 266 | CCE_STATUS_TXE_PAUSED_SMASK \ 267 | CCE_STATUS_SDMA_PAUSED_SMASK) 268 /* all CceStatus sub-block RXE pause bits */ 269 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK 270 271 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL 272 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF 273 274 /* 275 * CCE Error flags. 276 */ 277 static struct flag_table cce_err_status_flags[] = { 278 /* 0*/ FLAG_ENTRY0("CceCsrParityErr", 279 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK), 280 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr", 281 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK), 282 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr", 283 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK), 284 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr", 285 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK), 286 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr", 287 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK), 288 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr", 289 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK), 290 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr", 291 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK), 292 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr", 293 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK), 294 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr", 295 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK), 296 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 297 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK), 298 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr", 299 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK), 300 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError", 301 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK), 302 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError", 303 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK), 304 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr", 305 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK), 306 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr", 307 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK), 308 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr", 309 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK), 310 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr", 311 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK), 312 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr", 313 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK), 314 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr", 315 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK), 316 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr", 317 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK), 318 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr", 319 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK), 320 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr", 321 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK), 322 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr", 323 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK), 324 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr", 325 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK), 326 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr", 327 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK), 328 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr", 329 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK), 330 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr", 331 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK), 332 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr", 333 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK), 334 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr", 335 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK), 336 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr", 337 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK), 338 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr", 339 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK), 340 /*31*/ FLAG_ENTRY0("LATriggered", 341 CCE_ERR_STATUS_LA_TRIGGERED_SMASK), 342 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr", 343 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK), 344 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr", 345 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK), 346 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr", 347 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK), 348 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr", 349 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK), 350 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr", 351 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK), 352 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr", 353 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK), 354 /*38*/ FLAG_ENTRY0("CceIntMapCorErr", 355 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK), 356 /*39*/ FLAG_ENTRY0("CceIntMapUncErr", 357 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK), 358 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr", 359 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK), 360 /*41-63 reserved*/ 361 }; 362 363 /* 364 * Misc Error flags 365 */ 366 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK 367 static struct flag_table misc_err_status_flags[] = { 368 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)), 369 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)), 370 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)), 371 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)), 372 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)), 373 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)), 374 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)), 375 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)), 376 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)), 377 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)), 378 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)), 379 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)), 380 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL)) 381 }; 382 383 /* 384 * TXE PIO Error flags and consequences 385 */ 386 static struct flag_table pio_err_status_flags[] = { 387 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt", 388 SEC_WRITE_DROPPED, 389 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK), 390 /* 1*/ FLAG_ENTRY("PioWriteAddrParity", 391 SEC_SPC_FREEZE, 392 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK), 393 /* 2*/ FLAG_ENTRY("PioCsrParity", 394 SEC_SPC_FREEZE, 395 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK), 396 /* 3*/ FLAG_ENTRY("PioSbMemFifo0", 397 SEC_SPC_FREEZE, 398 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK), 399 /* 4*/ FLAG_ENTRY("PioSbMemFifo1", 400 SEC_SPC_FREEZE, 401 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK), 402 /* 5*/ FLAG_ENTRY("PioPccFifoParity", 403 SEC_SPC_FREEZE, 404 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK), 405 /* 6*/ FLAG_ENTRY("PioPecFifoParity", 406 SEC_SPC_FREEZE, 407 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK), 408 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity", 409 SEC_SPC_FREEZE, 410 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK), 411 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity", 412 SEC_SPC_FREEZE, 413 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK), 414 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr", 415 SEC_SPC_FREEZE, 416 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK), 417 /*10*/ FLAG_ENTRY("PioSmPktResetParity", 418 SEC_SPC_FREEZE, 419 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK), 420 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc", 421 SEC_SPC_FREEZE, 422 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK), 423 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc", 424 SEC_SPC_FREEZE, 425 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK), 426 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor", 427 0, 428 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK), 429 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor", 430 0, 431 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK), 432 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity", 433 SEC_SPC_FREEZE, 434 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK), 435 /*16*/ FLAG_ENTRY("PioPpmcPblFifo", 436 SEC_SPC_FREEZE, 437 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK), 438 /*17*/ FLAG_ENTRY("PioInitSmIn", 439 0, 440 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK), 441 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm", 442 SEC_SPC_FREEZE, 443 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK), 444 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc", 445 SEC_SPC_FREEZE, 446 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK), 447 /*20*/ FLAG_ENTRY("PioHostAddrMemCor", 448 0, 449 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK), 450 /*21*/ FLAG_ENTRY("PioWriteDataParity", 451 SEC_SPC_FREEZE, 452 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK), 453 /*22*/ FLAG_ENTRY("PioStateMachine", 454 SEC_SPC_FREEZE, 455 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK), 456 /*23*/ FLAG_ENTRY("PioWriteQwValidParity", 457 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 458 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK), 459 /*24*/ FLAG_ENTRY("PioBlockQwCountParity", 460 SEC_WRITE_DROPPED | SEC_SPC_FREEZE, 461 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK), 462 /*25*/ FLAG_ENTRY("PioVlfVlLenParity", 463 SEC_SPC_FREEZE, 464 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK), 465 /*26*/ FLAG_ENTRY("PioVlfSopParity", 466 SEC_SPC_FREEZE, 467 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK), 468 /*27*/ FLAG_ENTRY("PioVlFifoParity", 469 SEC_SPC_FREEZE, 470 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK), 471 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity", 472 SEC_SPC_FREEZE, 473 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK), 474 /*29*/ FLAG_ENTRY("PioPpmcSopLen", 475 SEC_SPC_FREEZE, 476 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK), 477 /*30-31 reserved*/ 478 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity", 479 SEC_SPC_FREEZE, 480 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK), 481 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity", 482 SEC_SPC_FREEZE, 483 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK), 484 /*34*/ FLAG_ENTRY("PioPccSopHeadParity", 485 SEC_SPC_FREEZE, 486 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK), 487 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr", 488 SEC_SPC_FREEZE, 489 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK), 490 /*36-63 reserved*/ 491 }; 492 493 /* TXE PIO errors that cause an SPC freeze */ 494 #define ALL_PIO_FREEZE_ERR \ 495 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \ 496 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \ 497 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \ 498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \ 499 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \ 500 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \ 501 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \ 502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 503 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \ 504 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \ 505 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \ 506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \ 507 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \ 508 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \ 509 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \ 510 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \ 511 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \ 512 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \ 513 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \ 514 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 515 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \ 516 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \ 517 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \ 518 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \ 519 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \ 520 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 521 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 522 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 523 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK) 524 525 /* 526 * TXE SDMA Error flags 527 */ 528 static struct flag_table sdma_err_status_flags[] = { 529 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr", 530 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK), 531 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr", 532 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK), 533 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr", 534 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK), 535 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr", 536 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK), 537 /*04-63 reserved*/ 538 }; 539 540 /* TXE SDMA errors that cause an SPC freeze */ 541 #define ALL_SDMA_FREEZE_ERR \ 542 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \ 543 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \ 544 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK) 545 546 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */ 547 #define PORT_DISCARD_EGRESS_ERRS \ 548 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \ 549 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \ 550 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK) 551 552 /* 553 * TXE Egress Error flags 554 */ 555 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK 556 static struct flag_table egress_err_status_flags[] = { 557 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)), 558 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)), 559 /* 2 reserved */ 560 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr", 561 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)), 562 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)), 563 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)), 564 /* 6 reserved */ 565 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr", 566 SEES(TX_PIO_LAUNCH_INTF_PARITY)), 567 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr", 568 SEES(TX_SDMA_LAUNCH_INTF_PARITY)), 569 /* 9-10 reserved */ 570 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr", 571 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)), 572 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)), 573 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)), 574 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)), 575 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)), 576 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr", 577 SEES(TX_SDMA0_DISALLOWED_PACKET)), 578 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr", 579 SEES(TX_SDMA1_DISALLOWED_PACKET)), 580 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr", 581 SEES(TX_SDMA2_DISALLOWED_PACKET)), 582 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr", 583 SEES(TX_SDMA3_DISALLOWED_PACKET)), 584 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr", 585 SEES(TX_SDMA4_DISALLOWED_PACKET)), 586 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr", 587 SEES(TX_SDMA5_DISALLOWED_PACKET)), 588 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr", 589 SEES(TX_SDMA6_DISALLOWED_PACKET)), 590 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr", 591 SEES(TX_SDMA7_DISALLOWED_PACKET)), 592 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr", 593 SEES(TX_SDMA8_DISALLOWED_PACKET)), 594 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr", 595 SEES(TX_SDMA9_DISALLOWED_PACKET)), 596 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr", 597 SEES(TX_SDMA10_DISALLOWED_PACKET)), 598 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr", 599 SEES(TX_SDMA11_DISALLOWED_PACKET)), 600 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr", 601 SEES(TX_SDMA12_DISALLOWED_PACKET)), 602 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr", 603 SEES(TX_SDMA13_DISALLOWED_PACKET)), 604 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr", 605 SEES(TX_SDMA14_DISALLOWED_PACKET)), 606 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr", 607 SEES(TX_SDMA15_DISALLOWED_PACKET)), 608 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr", 609 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)), 610 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr", 611 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)), 612 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr", 613 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)), 614 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr", 615 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)), 616 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr", 617 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)), 618 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr", 619 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)), 620 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr", 621 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)), 622 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr", 623 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)), 624 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr", 625 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)), 626 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)), 627 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)), 628 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)), 629 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)), 630 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)), 631 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)), 632 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)), 633 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)), 634 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)), 635 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)), 636 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)), 637 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)), 638 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)), 639 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)), 640 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)), 641 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)), 642 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)), 643 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)), 644 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)), 645 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)), 646 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)), 647 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr", 648 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)), 649 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr", 650 SEES(TX_READ_PIO_MEMORY_CSR_UNC)), 651 }; 652 653 /* 654 * TXE Egress Error Info flags 655 */ 656 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK 657 static struct flag_table egress_err_info_flags[] = { 658 /* 0*/ FLAG_ENTRY0("Reserved", 0ull), 659 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)), 660 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 661 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)), 662 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)), 663 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)), 664 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)), 665 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)), 666 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)), 667 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)), 668 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)), 669 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)), 670 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)), 671 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)), 672 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)), 673 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)), 674 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)), 675 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)), 676 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)), 677 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)), 678 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)), 679 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)), 680 }; 681 682 /* TXE Egress errors that cause an SPC freeze */ 683 #define ALL_TXE_EGRESS_FREEZE_ERR \ 684 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \ 685 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \ 686 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \ 687 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \ 688 | SEES(TX_LAUNCH_CSR_PARITY) \ 689 | SEES(TX_SBRD_CTL_CSR_PARITY) \ 690 | SEES(TX_CONFIG_PARITY) \ 691 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \ 692 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \ 693 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \ 694 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \ 695 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \ 696 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \ 697 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \ 698 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \ 699 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \ 700 | SEES(TX_CREDIT_RETURN_PARITY)) 701 702 /* 703 * TXE Send error flags 704 */ 705 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK 706 static struct flag_table send_err_status_flags[] = { 707 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)), 708 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)), 709 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR)) 710 }; 711 712 /* 713 * TXE Send Context Error flags and consequences 714 */ 715 static struct flag_table sc_err_status_flags[] = { 716 /* 0*/ FLAG_ENTRY("InconsistentSop", 717 SEC_PACKET_DROPPED | SEC_SC_HALTED, 718 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK), 719 /* 1*/ FLAG_ENTRY("DisallowedPacket", 720 SEC_PACKET_DROPPED | SEC_SC_HALTED, 721 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK), 722 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary", 723 SEC_WRITE_DROPPED | SEC_SC_HALTED, 724 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK), 725 /* 3*/ FLAG_ENTRY("WriteOverflow", 726 SEC_WRITE_DROPPED | SEC_SC_HALTED, 727 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK), 728 /* 4*/ FLAG_ENTRY("WriteOutOfBounds", 729 SEC_WRITE_DROPPED | SEC_SC_HALTED, 730 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK), 731 /* 5-63 reserved*/ 732 }; 733 734 /* 735 * RXE Receive Error flags 736 */ 737 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK 738 static struct flag_table rxe_err_status_flags[] = { 739 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)), 740 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)), 741 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)), 742 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)), 743 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)), 744 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)), 745 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)), 746 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)), 747 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)), 748 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)), 749 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)), 750 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)), 751 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)), 752 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)), 753 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)), 754 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)), 755 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr", 756 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)), 757 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)), 758 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)), 759 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr", 760 RXES(RBUF_BLOCK_LIST_READ_UNC)), 761 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr", 762 RXES(RBUF_BLOCK_LIST_READ_COR)), 763 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr", 764 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)), 765 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr", 766 RXES(RBUF_CSR_QENT_CNT_PARITY)), 767 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr", 768 RXES(RBUF_CSR_QNEXT_BUF_PARITY)), 769 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr", 770 RXES(RBUF_CSR_QVLD_BIT_PARITY)), 771 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)), 772 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)), 773 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr", 774 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)), 775 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)), 776 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)), 777 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)), 778 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)), 779 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)), 780 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)), 781 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)), 782 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr", 783 RXES(RBUF_FL_INITDONE_PARITY)), 784 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr", 785 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)), 786 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)), 787 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)), 788 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)), 789 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr", 790 RXES(LOOKUP_DES_PART1_UNC_COR)), 791 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr", 792 RXES(LOOKUP_DES_PART2_PARITY)), 793 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)), 794 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)), 795 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)), 796 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)), 797 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)), 798 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)), 799 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)), 800 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)), 801 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)), 802 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)), 803 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)), 804 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)), 805 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)), 806 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)), 807 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)), 808 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)), 809 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)), 810 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)), 811 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)), 812 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)), 813 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)), 814 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY)) 815 }; 816 817 /* RXE errors that will trigger an SPC freeze */ 818 #define ALL_RXE_FREEZE_ERR \ 819 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \ 820 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \ 821 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \ 822 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \ 823 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \ 824 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \ 825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \ 826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \ 827 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \ 828 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 829 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \ 830 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \ 831 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \ 832 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \ 833 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \ 834 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 835 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \ 836 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \ 837 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \ 838 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \ 839 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \ 840 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \ 841 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \ 842 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \ 843 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 844 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \ 845 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \ 846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 848 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \ 849 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \ 850 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \ 851 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \ 852 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \ 853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \ 854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \ 855 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \ 856 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 857 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \ 858 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \ 859 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 860 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 861 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \ 862 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK) 863 864 #define RXE_FREEZE_ABORT_MASK \ 865 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \ 866 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \ 867 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK) 868 869 /* 870 * DCC Error Flags 871 */ 872 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK 873 static struct flag_table dcc_err_flags[] = { 874 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)), 875 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)), 876 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)), 877 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)), 878 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)), 879 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)), 880 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)), 881 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)), 882 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)), 883 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)), 884 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)), 885 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)), 886 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)), 887 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)), 888 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)), 889 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)), 890 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)), 891 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)), 892 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)), 893 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)), 894 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)), 895 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)), 896 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)), 897 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)), 898 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)), 899 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)), 900 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)), 901 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)), 902 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)), 903 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)), 904 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)), 905 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)), 906 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)), 907 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)), 908 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)), 909 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)), 910 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)), 911 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)), 912 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)), 913 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)), 914 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)), 915 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)), 916 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)), 917 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)), 918 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)), 919 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)), 920 }; 921 922 /* 923 * LCB error flags 924 */ 925 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK 926 static struct flag_table lcb_err_flags[] = { 927 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)), 928 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)), 929 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)), 930 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST", 931 LCBE(ALL_LNS_FAILED_REINIT_TEST)), 932 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)), 933 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)), 934 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)), 935 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)), 936 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)), 937 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)), 938 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)), 939 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)), 940 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)), 941 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER", 942 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)), 943 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)), 944 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)), 945 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)), 946 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)), 947 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)), 948 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE", 949 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)), 950 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)), 951 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)), 952 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)), 953 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)), 954 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)), 955 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)), 956 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP", 957 LCBE(RST_FOR_INCOMPLT_RND_TRIP)), 958 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)), 959 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE", 960 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)), 961 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR", 962 LCBE(REDUNDANT_FLIT_PARITY_ERR)) 963 }; 964 965 /* 966 * DC8051 Error Flags 967 */ 968 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK 969 static struct flag_table dc8051_err_flags[] = { 970 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)), 971 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)), 972 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)), 973 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)), 974 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)), 975 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)), 976 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)), 977 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)), 978 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES", 979 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)), 980 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)), 981 }; 982 983 /* 984 * DC8051 Information Error flags 985 * 986 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field. 987 */ 988 static struct flag_table dc8051_info_err_flags[] = { 989 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED), 990 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME), 991 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET), 992 FLAG_ENTRY0("Serdes internal loopback failure", 993 FAILED_SERDES_INTERNAL_LOOPBACK), 994 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT), 995 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING), 996 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE), 997 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM), 998 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ), 999 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1), 1000 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2), 1001 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT), 1002 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT), 1003 FLAG_ENTRY0("External Device Request Timeout", 1004 EXTERNAL_DEVICE_REQ_TIMEOUT), 1005 }; 1006 1007 /* 1008 * DC8051 Information Host Information flags 1009 * 1010 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field. 1011 */ 1012 static struct flag_table dc8051_info_host_msg_flags[] = { 1013 FLAG_ENTRY0("Host request done", 0x0001), 1014 FLAG_ENTRY0("BC PWR_MGM message", 0x0002), 1015 FLAG_ENTRY0("BC SMA message", 0x0004), 1016 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008), 1017 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010), 1018 FLAG_ENTRY0("External device config request", 0x0020), 1019 FLAG_ENTRY0("VerifyCap all frames received", 0x0040), 1020 FLAG_ENTRY0("LinkUp achieved", 0x0080), 1021 FLAG_ENTRY0("Link going down", 0x0100), 1022 FLAG_ENTRY0("Link width downgraded", 0x0200), 1023 }; 1024 1025 static u32 encoded_size(u32 size); 1026 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate); 1027 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state); 1028 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 1029 u8 *continuous); 1030 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 1031 u8 *vcu, u16 *vl15buf, u8 *crc_sizes); 1032 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 1033 u8 *remote_tx_rate, u16 *link_widths); 1034 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 1035 u8 *flag_bits, u16 *link_widths); 1036 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 1037 u8 *device_rev); 1038 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx); 1039 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx, 1040 u8 *tx_polarity_inversion, 1041 u8 *rx_polarity_inversion, u8 *max_rate); 1042 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 1043 unsigned int context, u64 err_status); 1044 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg); 1045 static void handle_dcc_err(struct hfi1_devdata *dd, 1046 unsigned int context, u64 err_status); 1047 static void handle_lcb_err(struct hfi1_devdata *dd, 1048 unsigned int context, u64 err_status); 1049 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg); 1050 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1051 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1052 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1053 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1054 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1055 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1056 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); 1057 static void set_partition_keys(struct hfi1_pportdata *ppd); 1058 static const char *link_state_name(u32 state); 1059 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, 1060 u32 state); 1061 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 1062 u64 *out_data); 1063 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data); 1064 static int thermal_init(struct hfi1_devdata *dd); 1065 1066 static void update_statusp(struct hfi1_pportdata *ppd, u32 state); 1067 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 1068 int msecs); 1069 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1070 int msecs); 1071 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state); 1072 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state); 1073 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 1074 int msecs); 1075 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd, 1076 int msecs); 1077 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc); 1078 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr); 1079 static void handle_temp_err(struct hfi1_devdata *dd); 1080 static void dc_shutdown(struct hfi1_devdata *dd); 1081 static void dc_start(struct hfi1_devdata *dd); 1082 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 1083 unsigned int *np); 1084 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd); 1085 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms); 1086 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index); 1087 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width); 1088 1089 /* 1090 * Error interrupt table entry. This is used as input to the interrupt 1091 * "clear down" routine used for all second tier error interrupt register. 1092 * Second tier interrupt registers have a single bit representing them 1093 * in the top-level CceIntStatus. 1094 */ 1095 struct err_reg_info { 1096 u32 status; /* status CSR offset */ 1097 u32 clear; /* clear CSR offset */ 1098 u32 mask; /* mask CSR offset */ 1099 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg); 1100 const char *desc; 1101 }; 1102 1103 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START) 1104 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START) 1105 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START) 1106 1107 /* 1108 * Helpers for building HFI and DC error interrupt table entries. Different 1109 * helpers are needed because of inconsistent register names. 1110 */ 1111 #define EE(reg, handler, desc) \ 1112 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ 1113 handler, desc } 1114 #define DC_EE1(reg, handler, desc) \ 1115 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc } 1116 #define DC_EE2(reg, handler, desc) \ 1117 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc } 1118 1119 /* 1120 * Table of the "misc" grouping of error interrupts. Each entry refers to 1121 * another register containing more information. 1122 */ 1123 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = { 1124 /* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"), 1125 /* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"), 1126 /* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"), 1127 /* 3*/ { 0, 0, 0, NULL }, /* reserved */ 1128 /* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"), 1129 /* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"), 1130 /* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"), 1131 /* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr") 1132 /* the rest are reserved */ 1133 }; 1134 1135 /* 1136 * Index into the Various section of the interrupt sources 1137 * corresponding to the Critical Temperature interrupt. 1138 */ 1139 #define TCRIT_INT_SOURCE 4 1140 1141 /* 1142 * SDMA error interrupt entry - refers to another register containing more 1143 * information. 1144 */ 1145 static const struct err_reg_info sdma_eng_err = 1146 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr"); 1147 1148 static const struct err_reg_info various_err[NUM_VARIOUS] = { 1149 /* 0*/ { 0, 0, 0, NULL }, /* PbcInt */ 1150 /* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */ 1151 /* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"), 1152 /* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"), 1153 /* 4*/ { 0, 0, 0, NULL }, /* TCritInt */ 1154 /* rest are reserved */ 1155 }; 1156 1157 /* 1158 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG 1159 * register can not be derived from the MTU value because 10K is not 1160 * a power of 2. Therefore, we need a constant. Everything else can 1161 * be calculated. 1162 */ 1163 #define DCC_CFG_PORT_MTU_CAP_10240 7 1164 1165 /* 1166 * Table of the DC grouping of error interrupts. Each entry refers to 1167 * another register containing more information. 1168 */ 1169 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = { 1170 /* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"), 1171 /* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"), 1172 /* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"), 1173 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */ 1174 /* the rest are reserved */ 1175 }; 1176 1177 struct cntr_entry { 1178 /* 1179 * counter name 1180 */ 1181 char *name; 1182 1183 /* 1184 * csr to read for name (if applicable) 1185 */ 1186 u64 csr; 1187 1188 /* 1189 * offset into dd or ppd to store the counter's value 1190 */ 1191 int offset; 1192 1193 /* 1194 * flags 1195 */ 1196 u8 flags; 1197 1198 /* 1199 * accessor for stat element, context either dd or ppd 1200 */ 1201 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl, 1202 int mode, u64 data); 1203 }; 1204 1205 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0 1206 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159 1207 1208 #define CNTR_ELEM(name, csr, offset, flags, accessor) \ 1209 { \ 1210 name, \ 1211 csr, \ 1212 offset, \ 1213 flags, \ 1214 accessor \ 1215 } 1216 1217 /* 32bit RXE */ 1218 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1219 CNTR_ELEM(#name, \ 1220 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1221 0, flags | CNTR_32BIT, \ 1222 port_access_u32_csr) 1223 1224 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \ 1225 CNTR_ELEM(#name, \ 1226 (counter * 8 + RCV_COUNTER_ARRAY32), \ 1227 0, flags | CNTR_32BIT, \ 1228 dev_access_u32_csr) 1229 1230 /* 64bit RXE */ 1231 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1232 CNTR_ELEM(#name, \ 1233 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1234 0, flags, \ 1235 port_access_u64_csr) 1236 1237 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \ 1238 CNTR_ELEM(#name, \ 1239 (counter * 8 + RCV_COUNTER_ARRAY64), \ 1240 0, flags, \ 1241 dev_access_u64_csr) 1242 1243 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx 1244 #define OVR_ELM(ctx) \ 1245 CNTR_ELEM("RcvHdrOvr" #ctx, \ 1246 (RCV_HDR_OVFL_CNT + ctx * 0x100), \ 1247 0, CNTR_NORMAL, port_access_u64_csr) 1248 1249 /* 32bit TXE */ 1250 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \ 1251 CNTR_ELEM(#name, \ 1252 (counter * 8 + SEND_COUNTER_ARRAY32), \ 1253 0, flags | CNTR_32BIT, \ 1254 port_access_u32_csr) 1255 1256 /* 64bit TXE */ 1257 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \ 1258 CNTR_ELEM(#name, \ 1259 (counter * 8 + SEND_COUNTER_ARRAY64), \ 1260 0, flags, \ 1261 port_access_u64_csr) 1262 1263 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \ 1264 CNTR_ELEM(#name,\ 1265 counter * 8 + SEND_COUNTER_ARRAY64, \ 1266 0, \ 1267 flags, \ 1268 dev_access_u64_csr) 1269 1270 /* CCE */ 1271 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \ 1272 CNTR_ELEM(#name, \ 1273 (counter * 8 + CCE_COUNTER_ARRAY32), \ 1274 0, flags | CNTR_32BIT, \ 1275 dev_access_u32_csr) 1276 1277 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \ 1278 CNTR_ELEM(#name, \ 1279 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \ 1280 0, flags | CNTR_32BIT, \ 1281 dev_access_u32_csr) 1282 1283 /* DC */ 1284 #define DC_PERF_CNTR(name, counter, flags) \ 1285 CNTR_ELEM(#name, \ 1286 counter, \ 1287 0, \ 1288 flags, \ 1289 dev_access_u64_csr) 1290 1291 #define DC_PERF_CNTR_LCB(name, counter, flags) \ 1292 CNTR_ELEM(#name, \ 1293 counter, \ 1294 0, \ 1295 flags, \ 1296 dc_access_lcb_cntr) 1297 1298 /* ibp counters */ 1299 #define SW_IBP_CNTR(name, cntr) \ 1300 CNTR_ELEM(#name, \ 1301 0, \ 1302 0, \ 1303 CNTR_SYNTH, \ 1304 access_ibp_##cntr) 1305 1306 /** 1307 * hfi_addr_from_offset - return addr for readq/writeq 1308 * @dd - the dd device 1309 * @offset - the offset of the CSR within bar0 1310 * 1311 * This routine selects the appropriate base address 1312 * based on the indicated offset. 1313 */ 1314 static inline void __iomem *hfi1_addr_from_offset( 1315 const struct hfi1_devdata *dd, 1316 u32 offset) 1317 { 1318 if (offset >= dd->base2_start) 1319 return dd->kregbase2 + (offset - dd->base2_start); 1320 return dd->kregbase1 + offset; 1321 } 1322 1323 /** 1324 * read_csr - read CSR at the indicated offset 1325 * @dd - the dd device 1326 * @offset - the offset of the CSR within bar0 1327 * 1328 * Return: the value read or all FF's if there 1329 * is no mapping 1330 */ 1331 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) 1332 { 1333 if (dd->flags & HFI1_PRESENT) 1334 return readq(hfi1_addr_from_offset(dd, offset)); 1335 return -1; 1336 } 1337 1338 /** 1339 * write_csr - write CSR at the indicated offset 1340 * @dd - the dd device 1341 * @offset - the offset of the CSR within bar0 1342 * @value - value to write 1343 */ 1344 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) 1345 { 1346 if (dd->flags & HFI1_PRESENT) { 1347 void __iomem *base = hfi1_addr_from_offset(dd, offset); 1348 1349 /* avoid write to RcvArray */ 1350 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start)) 1351 return; 1352 writeq(value, base); 1353 } 1354 } 1355 1356 /** 1357 * get_csr_addr - return te iomem address for offset 1358 * @dd - the dd device 1359 * @offset - the offset of the CSR within bar0 1360 * 1361 * Return: The iomem address to use in subsequent 1362 * writeq/readq operations. 1363 */ 1364 void __iomem *get_csr_addr( 1365 const struct hfi1_devdata *dd, 1366 u32 offset) 1367 { 1368 if (dd->flags & HFI1_PRESENT) 1369 return hfi1_addr_from_offset(dd, offset); 1370 return NULL; 1371 } 1372 1373 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr, 1374 int mode, u64 value) 1375 { 1376 u64 ret; 1377 1378 if (mode == CNTR_MODE_R) { 1379 ret = read_csr(dd, csr); 1380 } else if (mode == CNTR_MODE_W) { 1381 write_csr(dd, csr, value); 1382 ret = value; 1383 } else { 1384 dd_dev_err(dd, "Invalid cntr register access mode"); 1385 return 0; 1386 } 1387 1388 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode); 1389 return ret; 1390 } 1391 1392 /* Dev Access */ 1393 static u64 dev_access_u32_csr(const struct cntr_entry *entry, 1394 void *context, int vl, int mode, u64 data) 1395 { 1396 struct hfi1_devdata *dd = context; 1397 u64 csr = entry->csr; 1398 1399 if (entry->flags & CNTR_SDMA) { 1400 if (vl == CNTR_INVALID_VL) 1401 return 0; 1402 csr += 0x100 * vl; 1403 } else { 1404 if (vl != CNTR_INVALID_VL) 1405 return 0; 1406 } 1407 return read_write_csr(dd, csr, mode, data); 1408 } 1409 1410 static u64 access_sde_err_cnt(const struct cntr_entry *entry, 1411 void *context, int idx, int mode, u64 data) 1412 { 1413 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1414 1415 if (dd->per_sdma && idx < dd->num_sdma) 1416 return dd->per_sdma[idx].err_cnt; 1417 return 0; 1418 } 1419 1420 static u64 access_sde_int_cnt(const struct cntr_entry *entry, 1421 void *context, int idx, int mode, u64 data) 1422 { 1423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1424 1425 if (dd->per_sdma && idx < dd->num_sdma) 1426 return dd->per_sdma[idx].sdma_int_cnt; 1427 return 0; 1428 } 1429 1430 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry, 1431 void *context, int idx, int mode, u64 data) 1432 { 1433 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1434 1435 if (dd->per_sdma && idx < dd->num_sdma) 1436 return dd->per_sdma[idx].idle_int_cnt; 1437 return 0; 1438 } 1439 1440 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry, 1441 void *context, int idx, int mode, 1442 u64 data) 1443 { 1444 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1445 1446 if (dd->per_sdma && idx < dd->num_sdma) 1447 return dd->per_sdma[idx].progress_int_cnt; 1448 return 0; 1449 } 1450 1451 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context, 1452 int vl, int mode, u64 data) 1453 { 1454 struct hfi1_devdata *dd = context; 1455 1456 u64 val = 0; 1457 u64 csr = entry->csr; 1458 1459 if (entry->flags & CNTR_VL) { 1460 if (vl == CNTR_INVALID_VL) 1461 return 0; 1462 csr += 8 * vl; 1463 } else { 1464 if (vl != CNTR_INVALID_VL) 1465 return 0; 1466 } 1467 1468 val = read_write_csr(dd, csr, mode, data); 1469 return val; 1470 } 1471 1472 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context, 1473 int vl, int mode, u64 data) 1474 { 1475 struct hfi1_devdata *dd = context; 1476 u32 csr = entry->csr; 1477 int ret = 0; 1478 1479 if (vl != CNTR_INVALID_VL) 1480 return 0; 1481 if (mode == CNTR_MODE_R) 1482 ret = read_lcb_csr(dd, csr, &data); 1483 else if (mode == CNTR_MODE_W) 1484 ret = write_lcb_csr(dd, csr, data); 1485 1486 if (ret) { 1487 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr); 1488 return 0; 1489 } 1490 1491 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode); 1492 return data; 1493 } 1494 1495 /* Port Access */ 1496 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context, 1497 int vl, int mode, u64 data) 1498 { 1499 struct hfi1_pportdata *ppd = context; 1500 1501 if (vl != CNTR_INVALID_VL) 1502 return 0; 1503 return read_write_csr(ppd->dd, entry->csr, mode, data); 1504 } 1505 1506 static u64 port_access_u64_csr(const struct cntr_entry *entry, 1507 void *context, int vl, int mode, u64 data) 1508 { 1509 struct hfi1_pportdata *ppd = context; 1510 u64 val; 1511 u64 csr = entry->csr; 1512 1513 if (entry->flags & CNTR_VL) { 1514 if (vl == CNTR_INVALID_VL) 1515 return 0; 1516 csr += 8 * vl; 1517 } else { 1518 if (vl != CNTR_INVALID_VL) 1519 return 0; 1520 } 1521 val = read_write_csr(ppd->dd, csr, mode, data); 1522 return val; 1523 } 1524 1525 /* Software defined */ 1526 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode, 1527 u64 data) 1528 { 1529 u64 ret; 1530 1531 if (mode == CNTR_MODE_R) { 1532 ret = *cntr; 1533 } else if (mode == CNTR_MODE_W) { 1534 *cntr = data; 1535 ret = data; 1536 } else { 1537 dd_dev_err(dd, "Invalid cntr sw access mode"); 1538 return 0; 1539 } 1540 1541 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode); 1542 1543 return ret; 1544 } 1545 1546 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context, 1547 int vl, int mode, u64 data) 1548 { 1549 struct hfi1_pportdata *ppd = context; 1550 1551 if (vl != CNTR_INVALID_VL) 1552 return 0; 1553 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data); 1554 } 1555 1556 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context, 1557 int vl, int mode, u64 data) 1558 { 1559 struct hfi1_pportdata *ppd = context; 1560 1561 if (vl != CNTR_INVALID_VL) 1562 return 0; 1563 return read_write_sw(ppd->dd, &ppd->link_up, mode, data); 1564 } 1565 1566 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry, 1567 void *context, int vl, int mode, 1568 u64 data) 1569 { 1570 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1571 1572 if (vl != CNTR_INVALID_VL) 1573 return 0; 1574 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data); 1575 } 1576 1577 static u64 access_sw_xmit_discards(const struct cntr_entry *entry, 1578 void *context, int vl, int mode, u64 data) 1579 { 1580 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; 1581 u64 zero = 0; 1582 u64 *counter; 1583 1584 if (vl == CNTR_INVALID_VL) 1585 counter = &ppd->port_xmit_discards; 1586 else if (vl >= 0 && vl < C_VL_COUNT) 1587 counter = &ppd->port_xmit_discards_vl[vl]; 1588 else 1589 counter = &zero; 1590 1591 return read_write_sw(ppd->dd, counter, mode, data); 1592 } 1593 1594 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry, 1595 void *context, int vl, int mode, 1596 u64 data) 1597 { 1598 struct hfi1_pportdata *ppd = context; 1599 1600 if (vl != CNTR_INVALID_VL) 1601 return 0; 1602 1603 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors, 1604 mode, data); 1605 } 1606 1607 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry, 1608 void *context, int vl, int mode, u64 data) 1609 { 1610 struct hfi1_pportdata *ppd = context; 1611 1612 if (vl != CNTR_INVALID_VL) 1613 return 0; 1614 1615 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors, 1616 mode, data); 1617 } 1618 1619 u64 get_all_cpu_total(u64 __percpu *cntr) 1620 { 1621 int cpu; 1622 u64 counter = 0; 1623 1624 for_each_possible_cpu(cpu) 1625 counter += *per_cpu_ptr(cntr, cpu); 1626 return counter; 1627 } 1628 1629 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val, 1630 u64 __percpu *cntr, 1631 int vl, int mode, u64 data) 1632 { 1633 u64 ret = 0; 1634 1635 if (vl != CNTR_INVALID_VL) 1636 return 0; 1637 1638 if (mode == CNTR_MODE_R) { 1639 ret = get_all_cpu_total(cntr) - *z_val; 1640 } else if (mode == CNTR_MODE_W) { 1641 /* A write can only zero the counter */ 1642 if (data == 0) 1643 *z_val = get_all_cpu_total(cntr); 1644 else 1645 dd_dev_err(dd, "Per CPU cntrs can only be zeroed"); 1646 } else { 1647 dd_dev_err(dd, "Invalid cntr sw cpu access mode"); 1648 return 0; 1649 } 1650 1651 return ret; 1652 } 1653 1654 static u64 access_sw_cpu_intr(const struct cntr_entry *entry, 1655 void *context, int vl, int mode, u64 data) 1656 { 1657 struct hfi1_devdata *dd = context; 1658 1659 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl, 1660 mode, data); 1661 } 1662 1663 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry, 1664 void *context, int vl, int mode, u64 data) 1665 { 1666 struct hfi1_devdata *dd = context; 1667 1668 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl, 1669 mode, data); 1670 } 1671 1672 static u64 access_sw_pio_wait(const struct cntr_entry *entry, 1673 void *context, int vl, int mode, u64 data) 1674 { 1675 struct hfi1_devdata *dd = context; 1676 1677 return dd->verbs_dev.n_piowait; 1678 } 1679 1680 static u64 access_sw_pio_drain(const struct cntr_entry *entry, 1681 void *context, int vl, int mode, u64 data) 1682 { 1683 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1684 1685 return dd->verbs_dev.n_piodrain; 1686 } 1687 1688 static u64 access_sw_vtx_wait(const struct cntr_entry *entry, 1689 void *context, int vl, int mode, u64 data) 1690 { 1691 struct hfi1_devdata *dd = context; 1692 1693 return dd->verbs_dev.n_txwait; 1694 } 1695 1696 static u64 access_sw_kmem_wait(const struct cntr_entry *entry, 1697 void *context, int vl, int mode, u64 data) 1698 { 1699 struct hfi1_devdata *dd = context; 1700 1701 return dd->verbs_dev.n_kmem_wait; 1702 } 1703 1704 static u64 access_sw_send_schedule(const struct cntr_entry *entry, 1705 void *context, int vl, int mode, u64 data) 1706 { 1707 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1708 1709 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl, 1710 mode, data); 1711 } 1712 1713 /* Software counters for the error status bits within MISC_ERR_STATUS */ 1714 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry, 1715 void *context, int vl, int mode, 1716 u64 data) 1717 { 1718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1719 1720 return dd->misc_err_status_cnt[12]; 1721 } 1722 1723 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry, 1724 void *context, int vl, int mode, 1725 u64 data) 1726 { 1727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1728 1729 return dd->misc_err_status_cnt[11]; 1730 } 1731 1732 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry, 1733 void *context, int vl, int mode, 1734 u64 data) 1735 { 1736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1737 1738 return dd->misc_err_status_cnt[10]; 1739 } 1740 1741 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry, 1742 void *context, int vl, 1743 int mode, u64 data) 1744 { 1745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1746 1747 return dd->misc_err_status_cnt[9]; 1748 } 1749 1750 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry, 1751 void *context, int vl, int mode, 1752 u64 data) 1753 { 1754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1755 1756 return dd->misc_err_status_cnt[8]; 1757 } 1758 1759 static u64 access_misc_efuse_read_bad_addr_err_cnt( 1760 const struct cntr_entry *entry, 1761 void *context, int vl, int mode, u64 data) 1762 { 1763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1764 1765 return dd->misc_err_status_cnt[7]; 1766 } 1767 1768 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry, 1769 void *context, int vl, 1770 int mode, u64 data) 1771 { 1772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1773 1774 return dd->misc_err_status_cnt[6]; 1775 } 1776 1777 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry, 1778 void *context, int vl, int mode, 1779 u64 data) 1780 { 1781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1782 1783 return dd->misc_err_status_cnt[5]; 1784 } 1785 1786 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry, 1787 void *context, int vl, int mode, 1788 u64 data) 1789 { 1790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1791 1792 return dd->misc_err_status_cnt[4]; 1793 } 1794 1795 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry, 1796 void *context, int vl, 1797 int mode, u64 data) 1798 { 1799 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1800 1801 return dd->misc_err_status_cnt[3]; 1802 } 1803 1804 static u64 access_misc_csr_write_bad_addr_err_cnt( 1805 const struct cntr_entry *entry, 1806 void *context, int vl, int mode, u64 data) 1807 { 1808 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1809 1810 return dd->misc_err_status_cnt[2]; 1811 } 1812 1813 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1814 void *context, int vl, 1815 int mode, u64 data) 1816 { 1817 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1818 1819 return dd->misc_err_status_cnt[1]; 1820 } 1821 1822 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry, 1823 void *context, int vl, int mode, 1824 u64 data) 1825 { 1826 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1827 1828 return dd->misc_err_status_cnt[0]; 1829 } 1830 1831 /* 1832 * Software counter for the aggregate of 1833 * individual CceErrStatus counters 1834 */ 1835 static u64 access_sw_cce_err_status_aggregated_cnt( 1836 const struct cntr_entry *entry, 1837 void *context, int vl, int mode, u64 data) 1838 { 1839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1840 1841 return dd->sw_cce_err_status_aggregate; 1842 } 1843 1844 /* 1845 * Software counters corresponding to each of the 1846 * error status bits within CceErrStatus 1847 */ 1848 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry, 1849 void *context, int vl, int mode, 1850 u64 data) 1851 { 1852 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1853 1854 return dd->cce_err_status_cnt[40]; 1855 } 1856 1857 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry, 1858 void *context, int vl, int mode, 1859 u64 data) 1860 { 1861 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1862 1863 return dd->cce_err_status_cnt[39]; 1864 } 1865 1866 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry, 1867 void *context, int vl, int mode, 1868 u64 data) 1869 { 1870 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1871 1872 return dd->cce_err_status_cnt[38]; 1873 } 1874 1875 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry, 1876 void *context, int vl, int mode, 1877 u64 data) 1878 { 1879 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1880 1881 return dd->cce_err_status_cnt[37]; 1882 } 1883 1884 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry, 1885 void *context, int vl, int mode, 1886 u64 data) 1887 { 1888 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1889 1890 return dd->cce_err_status_cnt[36]; 1891 } 1892 1893 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt( 1894 const struct cntr_entry *entry, 1895 void *context, int vl, int mode, u64 data) 1896 { 1897 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1898 1899 return dd->cce_err_status_cnt[35]; 1900 } 1901 1902 static u64 access_cce_rcpl_async_fifo_parity_err_cnt( 1903 const struct cntr_entry *entry, 1904 void *context, int vl, int mode, u64 data) 1905 { 1906 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1907 1908 return dd->cce_err_status_cnt[34]; 1909 } 1910 1911 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry, 1912 void *context, int vl, 1913 int mode, u64 data) 1914 { 1915 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1916 1917 return dd->cce_err_status_cnt[33]; 1918 } 1919 1920 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry, 1921 void *context, int vl, int mode, 1922 u64 data) 1923 { 1924 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1925 1926 return dd->cce_err_status_cnt[32]; 1927 } 1928 1929 static u64 access_la_triggered_cnt(const struct cntr_entry *entry, 1930 void *context, int vl, int mode, u64 data) 1931 { 1932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1933 1934 return dd->cce_err_status_cnt[31]; 1935 } 1936 1937 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry, 1938 void *context, int vl, int mode, 1939 u64 data) 1940 { 1941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1942 1943 return dd->cce_err_status_cnt[30]; 1944 } 1945 1946 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry, 1947 void *context, int vl, int mode, 1948 u64 data) 1949 { 1950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1951 1952 return dd->cce_err_status_cnt[29]; 1953 } 1954 1955 static u64 access_pcic_transmit_back_parity_err_cnt( 1956 const struct cntr_entry *entry, 1957 void *context, int vl, int mode, u64 data) 1958 { 1959 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1960 1961 return dd->cce_err_status_cnt[28]; 1962 } 1963 1964 static u64 access_pcic_transmit_front_parity_err_cnt( 1965 const struct cntr_entry *entry, 1966 void *context, int vl, int mode, u64 data) 1967 { 1968 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1969 1970 return dd->cce_err_status_cnt[27]; 1971 } 1972 1973 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry, 1974 void *context, int vl, int mode, 1975 u64 data) 1976 { 1977 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1978 1979 return dd->cce_err_status_cnt[26]; 1980 } 1981 1982 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry, 1983 void *context, int vl, int mode, 1984 u64 data) 1985 { 1986 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1987 1988 return dd->cce_err_status_cnt[25]; 1989 } 1990 1991 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry, 1992 void *context, int vl, int mode, 1993 u64 data) 1994 { 1995 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 1996 1997 return dd->cce_err_status_cnt[24]; 1998 } 1999 2000 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry, 2001 void *context, int vl, int mode, 2002 u64 data) 2003 { 2004 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2005 2006 return dd->cce_err_status_cnt[23]; 2007 } 2008 2009 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry, 2010 void *context, int vl, 2011 int mode, u64 data) 2012 { 2013 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2014 2015 return dd->cce_err_status_cnt[22]; 2016 } 2017 2018 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry, 2019 void *context, int vl, int mode, 2020 u64 data) 2021 { 2022 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2023 2024 return dd->cce_err_status_cnt[21]; 2025 } 2026 2027 static u64 access_pcic_n_post_dat_q_parity_err_cnt( 2028 const struct cntr_entry *entry, 2029 void *context, int vl, int mode, u64 data) 2030 { 2031 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2032 2033 return dd->cce_err_status_cnt[20]; 2034 } 2035 2036 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry, 2037 void *context, int vl, 2038 int mode, u64 data) 2039 { 2040 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2041 2042 return dd->cce_err_status_cnt[19]; 2043 } 2044 2045 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2046 void *context, int vl, int mode, 2047 u64 data) 2048 { 2049 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2050 2051 return dd->cce_err_status_cnt[18]; 2052 } 2053 2054 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2055 void *context, int vl, int mode, 2056 u64 data) 2057 { 2058 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2059 2060 return dd->cce_err_status_cnt[17]; 2061 } 2062 2063 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry, 2064 void *context, int vl, int mode, 2065 u64 data) 2066 { 2067 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2068 2069 return dd->cce_err_status_cnt[16]; 2070 } 2071 2072 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry, 2073 void *context, int vl, int mode, 2074 u64 data) 2075 { 2076 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2077 2078 return dd->cce_err_status_cnt[15]; 2079 } 2080 2081 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry, 2082 void *context, int vl, 2083 int mode, u64 data) 2084 { 2085 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2086 2087 return dd->cce_err_status_cnt[14]; 2088 } 2089 2090 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry, 2091 void *context, int vl, int mode, 2092 u64 data) 2093 { 2094 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2095 2096 return dd->cce_err_status_cnt[13]; 2097 } 2098 2099 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt( 2100 const struct cntr_entry *entry, 2101 void *context, int vl, int mode, u64 data) 2102 { 2103 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2104 2105 return dd->cce_err_status_cnt[12]; 2106 } 2107 2108 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt( 2109 const struct cntr_entry *entry, 2110 void *context, int vl, int mode, u64 data) 2111 { 2112 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2113 2114 return dd->cce_err_status_cnt[11]; 2115 } 2116 2117 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt( 2118 const struct cntr_entry *entry, 2119 void *context, int vl, int mode, u64 data) 2120 { 2121 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2122 2123 return dd->cce_err_status_cnt[10]; 2124 } 2125 2126 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt( 2127 const struct cntr_entry *entry, 2128 void *context, int vl, int mode, u64 data) 2129 { 2130 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2131 2132 return dd->cce_err_status_cnt[9]; 2133 } 2134 2135 static u64 access_cce_cli2_async_fifo_parity_err_cnt( 2136 const struct cntr_entry *entry, 2137 void *context, int vl, int mode, u64 data) 2138 { 2139 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2140 2141 return dd->cce_err_status_cnt[8]; 2142 } 2143 2144 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry, 2145 void *context, int vl, 2146 int mode, u64 data) 2147 { 2148 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2149 2150 return dd->cce_err_status_cnt[7]; 2151 } 2152 2153 static u64 access_cce_cli0_async_fifo_parity_err_cnt( 2154 const struct cntr_entry *entry, 2155 void *context, int vl, int mode, u64 data) 2156 { 2157 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2158 2159 return dd->cce_err_status_cnt[6]; 2160 } 2161 2162 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry, 2163 void *context, int vl, int mode, 2164 u64 data) 2165 { 2166 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2167 2168 return dd->cce_err_status_cnt[5]; 2169 } 2170 2171 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry, 2172 void *context, int vl, int mode, 2173 u64 data) 2174 { 2175 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2176 2177 return dd->cce_err_status_cnt[4]; 2178 } 2179 2180 static u64 access_cce_trgt_async_fifo_parity_err_cnt( 2181 const struct cntr_entry *entry, 2182 void *context, int vl, int mode, u64 data) 2183 { 2184 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2185 2186 return dd->cce_err_status_cnt[3]; 2187 } 2188 2189 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2190 void *context, int vl, 2191 int mode, u64 data) 2192 { 2193 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2194 2195 return dd->cce_err_status_cnt[2]; 2196 } 2197 2198 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2199 void *context, int vl, 2200 int mode, u64 data) 2201 { 2202 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2203 2204 return dd->cce_err_status_cnt[1]; 2205 } 2206 2207 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry, 2208 void *context, int vl, int mode, 2209 u64 data) 2210 { 2211 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2212 2213 return dd->cce_err_status_cnt[0]; 2214 } 2215 2216 /* 2217 * Software counters corresponding to each of the 2218 * error status bits within RcvErrStatus 2219 */ 2220 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry, 2221 void *context, int vl, int mode, 2222 u64 data) 2223 { 2224 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2225 2226 return dd->rcv_err_status_cnt[63]; 2227 } 2228 2229 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry, 2230 void *context, int vl, 2231 int mode, u64 data) 2232 { 2233 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2234 2235 return dd->rcv_err_status_cnt[62]; 2236 } 2237 2238 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 2239 void *context, int vl, int mode, 2240 u64 data) 2241 { 2242 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2243 2244 return dd->rcv_err_status_cnt[61]; 2245 } 2246 2247 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry, 2248 void *context, int vl, int mode, 2249 u64 data) 2250 { 2251 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2252 2253 return dd->rcv_err_status_cnt[60]; 2254 } 2255 2256 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2257 void *context, int vl, 2258 int mode, u64 data) 2259 { 2260 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2261 2262 return dd->rcv_err_status_cnt[59]; 2263 } 2264 2265 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2266 void *context, int vl, 2267 int mode, u64 data) 2268 { 2269 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2270 2271 return dd->rcv_err_status_cnt[58]; 2272 } 2273 2274 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry, 2275 void *context, int vl, int mode, 2276 u64 data) 2277 { 2278 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2279 2280 return dd->rcv_err_status_cnt[57]; 2281 } 2282 2283 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry, 2284 void *context, int vl, int mode, 2285 u64 data) 2286 { 2287 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2288 2289 return dd->rcv_err_status_cnt[56]; 2290 } 2291 2292 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry, 2293 void *context, int vl, int mode, 2294 u64 data) 2295 { 2296 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2297 2298 return dd->rcv_err_status_cnt[55]; 2299 } 2300 2301 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt( 2302 const struct cntr_entry *entry, 2303 void *context, int vl, int mode, u64 data) 2304 { 2305 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2306 2307 return dd->rcv_err_status_cnt[54]; 2308 } 2309 2310 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt( 2311 const struct cntr_entry *entry, 2312 void *context, int vl, int mode, u64 data) 2313 { 2314 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2315 2316 return dd->rcv_err_status_cnt[53]; 2317 } 2318 2319 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry, 2320 void *context, int vl, 2321 int mode, u64 data) 2322 { 2323 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2324 2325 return dd->rcv_err_status_cnt[52]; 2326 } 2327 2328 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry, 2329 void *context, int vl, 2330 int mode, u64 data) 2331 { 2332 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2333 2334 return dd->rcv_err_status_cnt[51]; 2335 } 2336 2337 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry, 2338 void *context, int vl, 2339 int mode, u64 data) 2340 { 2341 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2342 2343 return dd->rcv_err_status_cnt[50]; 2344 } 2345 2346 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry, 2347 void *context, int vl, 2348 int mode, u64 data) 2349 { 2350 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2351 2352 return dd->rcv_err_status_cnt[49]; 2353 } 2354 2355 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry, 2356 void *context, int vl, 2357 int mode, u64 data) 2358 { 2359 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2360 2361 return dd->rcv_err_status_cnt[48]; 2362 } 2363 2364 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry, 2365 void *context, int vl, 2366 int mode, u64 data) 2367 { 2368 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2369 2370 return dd->rcv_err_status_cnt[47]; 2371 } 2372 2373 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry, 2374 void *context, int vl, int mode, 2375 u64 data) 2376 { 2377 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2378 2379 return dd->rcv_err_status_cnt[46]; 2380 } 2381 2382 static u64 access_rx_hq_intr_csr_parity_err_cnt( 2383 const struct cntr_entry *entry, 2384 void *context, int vl, int mode, u64 data) 2385 { 2386 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2387 2388 return dd->rcv_err_status_cnt[45]; 2389 } 2390 2391 static u64 access_rx_lookup_csr_parity_err_cnt( 2392 const struct cntr_entry *entry, 2393 void *context, int vl, int mode, u64 data) 2394 { 2395 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2396 2397 return dd->rcv_err_status_cnt[44]; 2398 } 2399 2400 static u64 access_rx_lookup_rcv_array_cor_err_cnt( 2401 const struct cntr_entry *entry, 2402 void *context, int vl, int mode, u64 data) 2403 { 2404 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2405 2406 return dd->rcv_err_status_cnt[43]; 2407 } 2408 2409 static u64 access_rx_lookup_rcv_array_unc_err_cnt( 2410 const struct cntr_entry *entry, 2411 void *context, int vl, int mode, u64 data) 2412 { 2413 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2414 2415 return dd->rcv_err_status_cnt[42]; 2416 } 2417 2418 static u64 access_rx_lookup_des_part2_parity_err_cnt( 2419 const struct cntr_entry *entry, 2420 void *context, int vl, int mode, u64 data) 2421 { 2422 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2423 2424 return dd->rcv_err_status_cnt[41]; 2425 } 2426 2427 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt( 2428 const struct cntr_entry *entry, 2429 void *context, int vl, int mode, u64 data) 2430 { 2431 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2432 2433 return dd->rcv_err_status_cnt[40]; 2434 } 2435 2436 static u64 access_rx_lookup_des_part1_unc_err_cnt( 2437 const struct cntr_entry *entry, 2438 void *context, int vl, int mode, u64 data) 2439 { 2440 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2441 2442 return dd->rcv_err_status_cnt[39]; 2443 } 2444 2445 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt( 2446 const struct cntr_entry *entry, 2447 void *context, int vl, int mode, u64 data) 2448 { 2449 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2450 2451 return dd->rcv_err_status_cnt[38]; 2452 } 2453 2454 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt( 2455 const struct cntr_entry *entry, 2456 void *context, int vl, int mode, u64 data) 2457 { 2458 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2459 2460 return dd->rcv_err_status_cnt[37]; 2461 } 2462 2463 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt( 2464 const struct cntr_entry *entry, 2465 void *context, int vl, int mode, u64 data) 2466 { 2467 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2468 2469 return dd->rcv_err_status_cnt[36]; 2470 } 2471 2472 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt( 2473 const struct cntr_entry *entry, 2474 void *context, int vl, int mode, u64 data) 2475 { 2476 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2477 2478 return dd->rcv_err_status_cnt[35]; 2479 } 2480 2481 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt( 2482 const struct cntr_entry *entry, 2483 void *context, int vl, int mode, u64 data) 2484 { 2485 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2486 2487 return dd->rcv_err_status_cnt[34]; 2488 } 2489 2490 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt( 2491 const struct cntr_entry *entry, 2492 void *context, int vl, int mode, u64 data) 2493 { 2494 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2495 2496 return dd->rcv_err_status_cnt[33]; 2497 } 2498 2499 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry, 2500 void *context, int vl, int mode, 2501 u64 data) 2502 { 2503 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2504 2505 return dd->rcv_err_status_cnt[32]; 2506 } 2507 2508 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry, 2509 void *context, int vl, int mode, 2510 u64 data) 2511 { 2512 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2513 2514 return dd->rcv_err_status_cnt[31]; 2515 } 2516 2517 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry, 2518 void *context, int vl, int mode, 2519 u64 data) 2520 { 2521 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2522 2523 return dd->rcv_err_status_cnt[30]; 2524 } 2525 2526 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry, 2527 void *context, int vl, int mode, 2528 u64 data) 2529 { 2530 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2531 2532 return dd->rcv_err_status_cnt[29]; 2533 } 2534 2535 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry, 2536 void *context, int vl, 2537 int mode, u64 data) 2538 { 2539 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2540 2541 return dd->rcv_err_status_cnt[28]; 2542 } 2543 2544 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt( 2545 const struct cntr_entry *entry, 2546 void *context, int vl, int mode, u64 data) 2547 { 2548 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2549 2550 return dd->rcv_err_status_cnt[27]; 2551 } 2552 2553 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt( 2554 const struct cntr_entry *entry, 2555 void *context, int vl, int mode, u64 data) 2556 { 2557 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2558 2559 return dd->rcv_err_status_cnt[26]; 2560 } 2561 2562 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt( 2563 const struct cntr_entry *entry, 2564 void *context, int vl, int mode, u64 data) 2565 { 2566 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2567 2568 return dd->rcv_err_status_cnt[25]; 2569 } 2570 2571 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt( 2572 const struct cntr_entry *entry, 2573 void *context, int vl, int mode, u64 data) 2574 { 2575 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2576 2577 return dd->rcv_err_status_cnt[24]; 2578 } 2579 2580 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt( 2581 const struct cntr_entry *entry, 2582 void *context, int vl, int mode, u64 data) 2583 { 2584 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2585 2586 return dd->rcv_err_status_cnt[23]; 2587 } 2588 2589 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt( 2590 const struct cntr_entry *entry, 2591 void *context, int vl, int mode, u64 data) 2592 { 2593 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2594 2595 return dd->rcv_err_status_cnt[22]; 2596 } 2597 2598 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt( 2599 const struct cntr_entry *entry, 2600 void *context, int vl, int mode, u64 data) 2601 { 2602 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2603 2604 return dd->rcv_err_status_cnt[21]; 2605 } 2606 2607 static u64 access_rx_rbuf_block_list_read_cor_err_cnt( 2608 const struct cntr_entry *entry, 2609 void *context, int vl, int mode, u64 data) 2610 { 2611 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2612 2613 return dd->rcv_err_status_cnt[20]; 2614 } 2615 2616 static u64 access_rx_rbuf_block_list_read_unc_err_cnt( 2617 const struct cntr_entry *entry, 2618 void *context, int vl, int mode, u64 data) 2619 { 2620 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2621 2622 return dd->rcv_err_status_cnt[19]; 2623 } 2624 2625 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry, 2626 void *context, int vl, 2627 int mode, u64 data) 2628 { 2629 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2630 2631 return dd->rcv_err_status_cnt[18]; 2632 } 2633 2634 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry, 2635 void *context, int vl, 2636 int mode, u64 data) 2637 { 2638 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2639 2640 return dd->rcv_err_status_cnt[17]; 2641 } 2642 2643 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt( 2644 const struct cntr_entry *entry, 2645 void *context, int vl, int mode, u64 data) 2646 { 2647 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2648 2649 return dd->rcv_err_status_cnt[16]; 2650 } 2651 2652 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt( 2653 const struct cntr_entry *entry, 2654 void *context, int vl, int mode, u64 data) 2655 { 2656 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2657 2658 return dd->rcv_err_status_cnt[15]; 2659 } 2660 2661 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry, 2662 void *context, int vl, 2663 int mode, u64 data) 2664 { 2665 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2666 2667 return dd->rcv_err_status_cnt[14]; 2668 } 2669 2670 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry, 2671 void *context, int vl, 2672 int mode, u64 data) 2673 { 2674 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2675 2676 return dd->rcv_err_status_cnt[13]; 2677 } 2678 2679 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry, 2680 void *context, int vl, int mode, 2681 u64 data) 2682 { 2683 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2684 2685 return dd->rcv_err_status_cnt[12]; 2686 } 2687 2688 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry, 2689 void *context, int vl, int mode, 2690 u64 data) 2691 { 2692 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2693 2694 return dd->rcv_err_status_cnt[11]; 2695 } 2696 2697 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry, 2698 void *context, int vl, int mode, 2699 u64 data) 2700 { 2701 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2702 2703 return dd->rcv_err_status_cnt[10]; 2704 } 2705 2706 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry, 2707 void *context, int vl, int mode, 2708 u64 data) 2709 { 2710 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2711 2712 return dd->rcv_err_status_cnt[9]; 2713 } 2714 2715 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry, 2716 void *context, int vl, int mode, 2717 u64 data) 2718 { 2719 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2720 2721 return dd->rcv_err_status_cnt[8]; 2722 } 2723 2724 static u64 access_rx_rcv_qp_map_table_cor_err_cnt( 2725 const struct cntr_entry *entry, 2726 void *context, int vl, int mode, u64 data) 2727 { 2728 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2729 2730 return dd->rcv_err_status_cnt[7]; 2731 } 2732 2733 static u64 access_rx_rcv_qp_map_table_unc_err_cnt( 2734 const struct cntr_entry *entry, 2735 void *context, int vl, int mode, u64 data) 2736 { 2737 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2738 2739 return dd->rcv_err_status_cnt[6]; 2740 } 2741 2742 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry, 2743 void *context, int vl, int mode, 2744 u64 data) 2745 { 2746 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2747 2748 return dd->rcv_err_status_cnt[5]; 2749 } 2750 2751 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry, 2752 void *context, int vl, int mode, 2753 u64 data) 2754 { 2755 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2756 2757 return dd->rcv_err_status_cnt[4]; 2758 } 2759 2760 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry, 2761 void *context, int vl, int mode, 2762 u64 data) 2763 { 2764 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2765 2766 return dd->rcv_err_status_cnt[3]; 2767 } 2768 2769 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry, 2770 void *context, int vl, int mode, 2771 u64 data) 2772 { 2773 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2774 2775 return dd->rcv_err_status_cnt[2]; 2776 } 2777 2778 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry, 2779 void *context, int vl, int mode, 2780 u64 data) 2781 { 2782 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2783 2784 return dd->rcv_err_status_cnt[1]; 2785 } 2786 2787 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry, 2788 void *context, int vl, int mode, 2789 u64 data) 2790 { 2791 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2792 2793 return dd->rcv_err_status_cnt[0]; 2794 } 2795 2796 /* 2797 * Software counters corresponding to each of the 2798 * error status bits within SendPioErrStatus 2799 */ 2800 static u64 access_pio_pec_sop_head_parity_err_cnt( 2801 const struct cntr_entry *entry, 2802 void *context, int vl, int mode, u64 data) 2803 { 2804 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2805 2806 return dd->send_pio_err_status_cnt[35]; 2807 } 2808 2809 static u64 access_pio_pcc_sop_head_parity_err_cnt( 2810 const struct cntr_entry *entry, 2811 void *context, int vl, int mode, u64 data) 2812 { 2813 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2814 2815 return dd->send_pio_err_status_cnt[34]; 2816 } 2817 2818 static u64 access_pio_last_returned_cnt_parity_err_cnt( 2819 const struct cntr_entry *entry, 2820 void *context, int vl, int mode, u64 data) 2821 { 2822 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2823 2824 return dd->send_pio_err_status_cnt[33]; 2825 } 2826 2827 static u64 access_pio_current_free_cnt_parity_err_cnt( 2828 const struct cntr_entry *entry, 2829 void *context, int vl, int mode, u64 data) 2830 { 2831 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2832 2833 return dd->send_pio_err_status_cnt[32]; 2834 } 2835 2836 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry, 2837 void *context, int vl, int mode, 2838 u64 data) 2839 { 2840 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2841 2842 return dd->send_pio_err_status_cnt[31]; 2843 } 2844 2845 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry, 2846 void *context, int vl, int mode, 2847 u64 data) 2848 { 2849 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2850 2851 return dd->send_pio_err_status_cnt[30]; 2852 } 2853 2854 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry, 2855 void *context, int vl, int mode, 2856 u64 data) 2857 { 2858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2859 2860 return dd->send_pio_err_status_cnt[29]; 2861 } 2862 2863 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt( 2864 const struct cntr_entry *entry, 2865 void *context, int vl, int mode, u64 data) 2866 { 2867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2868 2869 return dd->send_pio_err_status_cnt[28]; 2870 } 2871 2872 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry, 2873 void *context, int vl, int mode, 2874 u64 data) 2875 { 2876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2877 2878 return dd->send_pio_err_status_cnt[27]; 2879 } 2880 2881 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry, 2882 void *context, int vl, int mode, 2883 u64 data) 2884 { 2885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2886 2887 return dd->send_pio_err_status_cnt[26]; 2888 } 2889 2890 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry, 2891 void *context, int vl, 2892 int mode, u64 data) 2893 { 2894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2895 2896 return dd->send_pio_err_status_cnt[25]; 2897 } 2898 2899 static u64 access_pio_block_qw_count_parity_err_cnt( 2900 const struct cntr_entry *entry, 2901 void *context, int vl, int mode, u64 data) 2902 { 2903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2904 2905 return dd->send_pio_err_status_cnt[24]; 2906 } 2907 2908 static u64 access_pio_write_qw_valid_parity_err_cnt( 2909 const struct cntr_entry *entry, 2910 void *context, int vl, int mode, u64 data) 2911 { 2912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2913 2914 return dd->send_pio_err_status_cnt[23]; 2915 } 2916 2917 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry, 2918 void *context, int vl, int mode, 2919 u64 data) 2920 { 2921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2922 2923 return dd->send_pio_err_status_cnt[22]; 2924 } 2925 2926 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry, 2927 void *context, int vl, 2928 int mode, u64 data) 2929 { 2930 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2931 2932 return dd->send_pio_err_status_cnt[21]; 2933 } 2934 2935 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry, 2936 void *context, int vl, 2937 int mode, u64 data) 2938 { 2939 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2940 2941 return dd->send_pio_err_status_cnt[20]; 2942 } 2943 2944 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry, 2945 void *context, int vl, 2946 int mode, u64 data) 2947 { 2948 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2949 2950 return dd->send_pio_err_status_cnt[19]; 2951 } 2952 2953 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt( 2954 const struct cntr_entry *entry, 2955 void *context, int vl, int mode, u64 data) 2956 { 2957 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2958 2959 return dd->send_pio_err_status_cnt[18]; 2960 } 2961 2962 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry, 2963 void *context, int vl, int mode, 2964 u64 data) 2965 { 2966 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2967 2968 return dd->send_pio_err_status_cnt[17]; 2969 } 2970 2971 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry, 2972 void *context, int vl, int mode, 2973 u64 data) 2974 { 2975 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2976 2977 return dd->send_pio_err_status_cnt[16]; 2978 } 2979 2980 static u64 access_pio_credit_ret_fifo_parity_err_cnt( 2981 const struct cntr_entry *entry, 2982 void *context, int vl, int mode, u64 data) 2983 { 2984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2985 2986 return dd->send_pio_err_status_cnt[15]; 2987 } 2988 2989 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt( 2990 const struct cntr_entry *entry, 2991 void *context, int vl, int mode, u64 data) 2992 { 2993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 2994 2995 return dd->send_pio_err_status_cnt[14]; 2996 } 2997 2998 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt( 2999 const struct cntr_entry *entry, 3000 void *context, int vl, int mode, u64 data) 3001 { 3002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3003 3004 return dd->send_pio_err_status_cnt[13]; 3005 } 3006 3007 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt( 3008 const struct cntr_entry *entry, 3009 void *context, int vl, int mode, u64 data) 3010 { 3011 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3012 3013 return dd->send_pio_err_status_cnt[12]; 3014 } 3015 3016 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt( 3017 const struct cntr_entry *entry, 3018 void *context, int vl, int mode, u64 data) 3019 { 3020 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3021 3022 return dd->send_pio_err_status_cnt[11]; 3023 } 3024 3025 static u64 access_pio_sm_pkt_reset_parity_err_cnt( 3026 const struct cntr_entry *entry, 3027 void *context, int vl, int mode, u64 data) 3028 { 3029 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3030 3031 return dd->send_pio_err_status_cnt[10]; 3032 } 3033 3034 static u64 access_pio_pkt_evict_fifo_parity_err_cnt( 3035 const struct cntr_entry *entry, 3036 void *context, int vl, int mode, u64 data) 3037 { 3038 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3039 3040 return dd->send_pio_err_status_cnt[9]; 3041 } 3042 3043 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt( 3044 const struct cntr_entry *entry, 3045 void *context, int vl, int mode, u64 data) 3046 { 3047 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3048 3049 return dd->send_pio_err_status_cnt[8]; 3050 } 3051 3052 static u64 access_pio_sbrdctl_crrel_parity_err_cnt( 3053 const struct cntr_entry *entry, 3054 void *context, int vl, int mode, u64 data) 3055 { 3056 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3057 3058 return dd->send_pio_err_status_cnt[7]; 3059 } 3060 3061 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry, 3062 void *context, int vl, int mode, 3063 u64 data) 3064 { 3065 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3066 3067 return dd->send_pio_err_status_cnt[6]; 3068 } 3069 3070 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry, 3071 void *context, int vl, int mode, 3072 u64 data) 3073 { 3074 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3075 3076 return dd->send_pio_err_status_cnt[5]; 3077 } 3078 3079 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry, 3080 void *context, int vl, int mode, 3081 u64 data) 3082 { 3083 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3084 3085 return dd->send_pio_err_status_cnt[4]; 3086 } 3087 3088 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry, 3089 void *context, int vl, int mode, 3090 u64 data) 3091 { 3092 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3093 3094 return dd->send_pio_err_status_cnt[3]; 3095 } 3096 3097 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry, 3098 void *context, int vl, int mode, 3099 u64 data) 3100 { 3101 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3102 3103 return dd->send_pio_err_status_cnt[2]; 3104 } 3105 3106 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry, 3107 void *context, int vl, 3108 int mode, u64 data) 3109 { 3110 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3111 3112 return dd->send_pio_err_status_cnt[1]; 3113 } 3114 3115 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry, 3116 void *context, int vl, int mode, 3117 u64 data) 3118 { 3119 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3120 3121 return dd->send_pio_err_status_cnt[0]; 3122 } 3123 3124 /* 3125 * Software counters corresponding to each of the 3126 * error status bits within SendDmaErrStatus 3127 */ 3128 static u64 access_sdma_pcie_req_tracking_cor_err_cnt( 3129 const struct cntr_entry *entry, 3130 void *context, int vl, int mode, u64 data) 3131 { 3132 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3133 3134 return dd->send_dma_err_status_cnt[3]; 3135 } 3136 3137 static u64 access_sdma_pcie_req_tracking_unc_err_cnt( 3138 const struct cntr_entry *entry, 3139 void *context, int vl, int mode, u64 data) 3140 { 3141 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3142 3143 return dd->send_dma_err_status_cnt[2]; 3144 } 3145 3146 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry, 3147 void *context, int vl, int mode, 3148 u64 data) 3149 { 3150 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3151 3152 return dd->send_dma_err_status_cnt[1]; 3153 } 3154 3155 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry, 3156 void *context, int vl, int mode, 3157 u64 data) 3158 { 3159 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3160 3161 return dd->send_dma_err_status_cnt[0]; 3162 } 3163 3164 /* 3165 * Software counters corresponding to each of the 3166 * error status bits within SendEgressErrStatus 3167 */ 3168 static u64 access_tx_read_pio_memory_csr_unc_err_cnt( 3169 const struct cntr_entry *entry, 3170 void *context, int vl, int mode, u64 data) 3171 { 3172 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3173 3174 return dd->send_egress_err_status_cnt[63]; 3175 } 3176 3177 static u64 access_tx_read_sdma_memory_csr_err_cnt( 3178 const struct cntr_entry *entry, 3179 void *context, int vl, int mode, u64 data) 3180 { 3181 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3182 3183 return dd->send_egress_err_status_cnt[62]; 3184 } 3185 3186 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry, 3187 void *context, int vl, int mode, 3188 u64 data) 3189 { 3190 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3191 3192 return dd->send_egress_err_status_cnt[61]; 3193 } 3194 3195 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry, 3196 void *context, int vl, 3197 int mode, u64 data) 3198 { 3199 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3200 3201 return dd->send_egress_err_status_cnt[60]; 3202 } 3203 3204 static u64 access_tx_read_sdma_memory_cor_err_cnt( 3205 const struct cntr_entry *entry, 3206 void *context, int vl, int mode, u64 data) 3207 { 3208 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3209 3210 return dd->send_egress_err_status_cnt[59]; 3211 } 3212 3213 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry, 3214 void *context, int vl, int mode, 3215 u64 data) 3216 { 3217 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3218 3219 return dd->send_egress_err_status_cnt[58]; 3220 } 3221 3222 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry, 3223 void *context, int vl, int mode, 3224 u64 data) 3225 { 3226 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3227 3228 return dd->send_egress_err_status_cnt[57]; 3229 } 3230 3231 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry, 3232 void *context, int vl, int mode, 3233 u64 data) 3234 { 3235 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3236 3237 return dd->send_egress_err_status_cnt[56]; 3238 } 3239 3240 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry, 3241 void *context, int vl, int mode, 3242 u64 data) 3243 { 3244 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3245 3246 return dd->send_egress_err_status_cnt[55]; 3247 } 3248 3249 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry, 3250 void *context, int vl, int mode, 3251 u64 data) 3252 { 3253 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3254 3255 return dd->send_egress_err_status_cnt[54]; 3256 } 3257 3258 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry, 3259 void *context, int vl, int mode, 3260 u64 data) 3261 { 3262 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3263 3264 return dd->send_egress_err_status_cnt[53]; 3265 } 3266 3267 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry, 3268 void *context, int vl, int mode, 3269 u64 data) 3270 { 3271 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3272 3273 return dd->send_egress_err_status_cnt[52]; 3274 } 3275 3276 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry, 3277 void *context, int vl, int mode, 3278 u64 data) 3279 { 3280 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3281 3282 return dd->send_egress_err_status_cnt[51]; 3283 } 3284 3285 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry, 3286 void *context, int vl, int mode, 3287 u64 data) 3288 { 3289 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3290 3291 return dd->send_egress_err_status_cnt[50]; 3292 } 3293 3294 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry, 3295 void *context, int vl, int mode, 3296 u64 data) 3297 { 3298 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3299 3300 return dd->send_egress_err_status_cnt[49]; 3301 } 3302 3303 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry, 3304 void *context, int vl, int mode, 3305 u64 data) 3306 { 3307 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3308 3309 return dd->send_egress_err_status_cnt[48]; 3310 } 3311 3312 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry, 3313 void *context, int vl, int mode, 3314 u64 data) 3315 { 3316 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3317 3318 return dd->send_egress_err_status_cnt[47]; 3319 } 3320 3321 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry, 3322 void *context, int vl, int mode, 3323 u64 data) 3324 { 3325 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3326 3327 return dd->send_egress_err_status_cnt[46]; 3328 } 3329 3330 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry, 3331 void *context, int vl, int mode, 3332 u64 data) 3333 { 3334 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3335 3336 return dd->send_egress_err_status_cnt[45]; 3337 } 3338 3339 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry, 3340 void *context, int vl, 3341 int mode, u64 data) 3342 { 3343 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3344 3345 return dd->send_egress_err_status_cnt[44]; 3346 } 3347 3348 static u64 access_tx_read_sdma_memory_unc_err_cnt( 3349 const struct cntr_entry *entry, 3350 void *context, int vl, int mode, u64 data) 3351 { 3352 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3353 3354 return dd->send_egress_err_status_cnt[43]; 3355 } 3356 3357 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry, 3358 void *context, int vl, int mode, 3359 u64 data) 3360 { 3361 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3362 3363 return dd->send_egress_err_status_cnt[42]; 3364 } 3365 3366 static u64 access_tx_credit_return_partiy_err_cnt( 3367 const struct cntr_entry *entry, 3368 void *context, int vl, int mode, u64 data) 3369 { 3370 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3371 3372 return dd->send_egress_err_status_cnt[41]; 3373 } 3374 3375 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt( 3376 const struct cntr_entry *entry, 3377 void *context, int vl, int mode, u64 data) 3378 { 3379 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3380 3381 return dd->send_egress_err_status_cnt[40]; 3382 } 3383 3384 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt( 3385 const struct cntr_entry *entry, 3386 void *context, int vl, int mode, u64 data) 3387 { 3388 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3389 3390 return dd->send_egress_err_status_cnt[39]; 3391 } 3392 3393 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt( 3394 const struct cntr_entry *entry, 3395 void *context, int vl, int mode, u64 data) 3396 { 3397 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3398 3399 return dd->send_egress_err_status_cnt[38]; 3400 } 3401 3402 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt( 3403 const struct cntr_entry *entry, 3404 void *context, int vl, int mode, u64 data) 3405 { 3406 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3407 3408 return dd->send_egress_err_status_cnt[37]; 3409 } 3410 3411 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt( 3412 const struct cntr_entry *entry, 3413 void *context, int vl, int mode, u64 data) 3414 { 3415 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3416 3417 return dd->send_egress_err_status_cnt[36]; 3418 } 3419 3420 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt( 3421 const struct cntr_entry *entry, 3422 void *context, int vl, int mode, u64 data) 3423 { 3424 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3425 3426 return dd->send_egress_err_status_cnt[35]; 3427 } 3428 3429 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt( 3430 const struct cntr_entry *entry, 3431 void *context, int vl, int mode, u64 data) 3432 { 3433 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3434 3435 return dd->send_egress_err_status_cnt[34]; 3436 } 3437 3438 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt( 3439 const struct cntr_entry *entry, 3440 void *context, int vl, int mode, u64 data) 3441 { 3442 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3443 3444 return dd->send_egress_err_status_cnt[33]; 3445 } 3446 3447 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt( 3448 const struct cntr_entry *entry, 3449 void *context, int vl, int mode, u64 data) 3450 { 3451 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3452 3453 return dd->send_egress_err_status_cnt[32]; 3454 } 3455 3456 static u64 access_tx_sdma15_disallowed_packet_err_cnt( 3457 const struct cntr_entry *entry, 3458 void *context, int vl, int mode, u64 data) 3459 { 3460 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3461 3462 return dd->send_egress_err_status_cnt[31]; 3463 } 3464 3465 static u64 access_tx_sdma14_disallowed_packet_err_cnt( 3466 const struct cntr_entry *entry, 3467 void *context, int vl, int mode, u64 data) 3468 { 3469 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3470 3471 return dd->send_egress_err_status_cnt[30]; 3472 } 3473 3474 static u64 access_tx_sdma13_disallowed_packet_err_cnt( 3475 const struct cntr_entry *entry, 3476 void *context, int vl, int mode, u64 data) 3477 { 3478 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3479 3480 return dd->send_egress_err_status_cnt[29]; 3481 } 3482 3483 static u64 access_tx_sdma12_disallowed_packet_err_cnt( 3484 const struct cntr_entry *entry, 3485 void *context, int vl, int mode, u64 data) 3486 { 3487 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3488 3489 return dd->send_egress_err_status_cnt[28]; 3490 } 3491 3492 static u64 access_tx_sdma11_disallowed_packet_err_cnt( 3493 const struct cntr_entry *entry, 3494 void *context, int vl, int mode, u64 data) 3495 { 3496 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3497 3498 return dd->send_egress_err_status_cnt[27]; 3499 } 3500 3501 static u64 access_tx_sdma10_disallowed_packet_err_cnt( 3502 const struct cntr_entry *entry, 3503 void *context, int vl, int mode, u64 data) 3504 { 3505 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3506 3507 return dd->send_egress_err_status_cnt[26]; 3508 } 3509 3510 static u64 access_tx_sdma9_disallowed_packet_err_cnt( 3511 const struct cntr_entry *entry, 3512 void *context, int vl, int mode, u64 data) 3513 { 3514 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3515 3516 return dd->send_egress_err_status_cnt[25]; 3517 } 3518 3519 static u64 access_tx_sdma8_disallowed_packet_err_cnt( 3520 const struct cntr_entry *entry, 3521 void *context, int vl, int mode, u64 data) 3522 { 3523 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3524 3525 return dd->send_egress_err_status_cnt[24]; 3526 } 3527 3528 static u64 access_tx_sdma7_disallowed_packet_err_cnt( 3529 const struct cntr_entry *entry, 3530 void *context, int vl, int mode, u64 data) 3531 { 3532 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3533 3534 return dd->send_egress_err_status_cnt[23]; 3535 } 3536 3537 static u64 access_tx_sdma6_disallowed_packet_err_cnt( 3538 const struct cntr_entry *entry, 3539 void *context, int vl, int mode, u64 data) 3540 { 3541 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3542 3543 return dd->send_egress_err_status_cnt[22]; 3544 } 3545 3546 static u64 access_tx_sdma5_disallowed_packet_err_cnt( 3547 const struct cntr_entry *entry, 3548 void *context, int vl, int mode, u64 data) 3549 { 3550 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3551 3552 return dd->send_egress_err_status_cnt[21]; 3553 } 3554 3555 static u64 access_tx_sdma4_disallowed_packet_err_cnt( 3556 const struct cntr_entry *entry, 3557 void *context, int vl, int mode, u64 data) 3558 { 3559 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3560 3561 return dd->send_egress_err_status_cnt[20]; 3562 } 3563 3564 static u64 access_tx_sdma3_disallowed_packet_err_cnt( 3565 const struct cntr_entry *entry, 3566 void *context, int vl, int mode, u64 data) 3567 { 3568 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3569 3570 return dd->send_egress_err_status_cnt[19]; 3571 } 3572 3573 static u64 access_tx_sdma2_disallowed_packet_err_cnt( 3574 const struct cntr_entry *entry, 3575 void *context, int vl, int mode, u64 data) 3576 { 3577 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3578 3579 return dd->send_egress_err_status_cnt[18]; 3580 } 3581 3582 static u64 access_tx_sdma1_disallowed_packet_err_cnt( 3583 const struct cntr_entry *entry, 3584 void *context, int vl, int mode, u64 data) 3585 { 3586 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3587 3588 return dd->send_egress_err_status_cnt[17]; 3589 } 3590 3591 static u64 access_tx_sdma0_disallowed_packet_err_cnt( 3592 const struct cntr_entry *entry, 3593 void *context, int vl, int mode, u64 data) 3594 { 3595 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3596 3597 return dd->send_egress_err_status_cnt[16]; 3598 } 3599 3600 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry, 3601 void *context, int vl, int mode, 3602 u64 data) 3603 { 3604 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3605 3606 return dd->send_egress_err_status_cnt[15]; 3607 } 3608 3609 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry, 3610 void *context, int vl, 3611 int mode, u64 data) 3612 { 3613 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3614 3615 return dd->send_egress_err_status_cnt[14]; 3616 } 3617 3618 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry, 3619 void *context, int vl, int mode, 3620 u64 data) 3621 { 3622 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3623 3624 return dd->send_egress_err_status_cnt[13]; 3625 } 3626 3627 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry, 3628 void *context, int vl, int mode, 3629 u64 data) 3630 { 3631 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3632 3633 return dd->send_egress_err_status_cnt[12]; 3634 } 3635 3636 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt( 3637 const struct cntr_entry *entry, 3638 void *context, int vl, int mode, u64 data) 3639 { 3640 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3641 3642 return dd->send_egress_err_status_cnt[11]; 3643 } 3644 3645 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry, 3646 void *context, int vl, int mode, 3647 u64 data) 3648 { 3649 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3650 3651 return dd->send_egress_err_status_cnt[10]; 3652 } 3653 3654 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry, 3655 void *context, int vl, int mode, 3656 u64 data) 3657 { 3658 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3659 3660 return dd->send_egress_err_status_cnt[9]; 3661 } 3662 3663 static u64 access_tx_sdma_launch_intf_parity_err_cnt( 3664 const struct cntr_entry *entry, 3665 void *context, int vl, int mode, u64 data) 3666 { 3667 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3668 3669 return dd->send_egress_err_status_cnt[8]; 3670 } 3671 3672 static u64 access_tx_pio_launch_intf_parity_err_cnt( 3673 const struct cntr_entry *entry, 3674 void *context, int vl, int mode, u64 data) 3675 { 3676 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3677 3678 return dd->send_egress_err_status_cnt[7]; 3679 } 3680 3681 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry, 3682 void *context, int vl, int mode, 3683 u64 data) 3684 { 3685 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3686 3687 return dd->send_egress_err_status_cnt[6]; 3688 } 3689 3690 static u64 access_tx_incorrect_link_state_err_cnt( 3691 const struct cntr_entry *entry, 3692 void *context, int vl, int mode, u64 data) 3693 { 3694 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3695 3696 return dd->send_egress_err_status_cnt[5]; 3697 } 3698 3699 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry, 3700 void *context, int vl, int mode, 3701 u64 data) 3702 { 3703 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3704 3705 return dd->send_egress_err_status_cnt[4]; 3706 } 3707 3708 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt( 3709 const struct cntr_entry *entry, 3710 void *context, int vl, int mode, u64 data) 3711 { 3712 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3713 3714 return dd->send_egress_err_status_cnt[3]; 3715 } 3716 3717 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry, 3718 void *context, int vl, int mode, 3719 u64 data) 3720 { 3721 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3722 3723 return dd->send_egress_err_status_cnt[2]; 3724 } 3725 3726 static u64 access_tx_pkt_integrity_mem_unc_err_cnt( 3727 const struct cntr_entry *entry, 3728 void *context, int vl, int mode, u64 data) 3729 { 3730 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3731 3732 return dd->send_egress_err_status_cnt[1]; 3733 } 3734 3735 static u64 access_tx_pkt_integrity_mem_cor_err_cnt( 3736 const struct cntr_entry *entry, 3737 void *context, int vl, int mode, u64 data) 3738 { 3739 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3740 3741 return dd->send_egress_err_status_cnt[0]; 3742 } 3743 3744 /* 3745 * Software counters corresponding to each of the 3746 * error status bits within SendErrStatus 3747 */ 3748 static u64 access_send_csr_write_bad_addr_err_cnt( 3749 const struct cntr_entry *entry, 3750 void *context, int vl, int mode, u64 data) 3751 { 3752 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3753 3754 return dd->send_err_status_cnt[2]; 3755 } 3756 3757 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry, 3758 void *context, int vl, 3759 int mode, u64 data) 3760 { 3761 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3762 3763 return dd->send_err_status_cnt[1]; 3764 } 3765 3766 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry, 3767 void *context, int vl, int mode, 3768 u64 data) 3769 { 3770 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3771 3772 return dd->send_err_status_cnt[0]; 3773 } 3774 3775 /* 3776 * Software counters corresponding to each of the 3777 * error status bits within SendCtxtErrStatus 3778 */ 3779 static u64 access_pio_write_out_of_bounds_err_cnt( 3780 const struct cntr_entry *entry, 3781 void *context, int vl, int mode, u64 data) 3782 { 3783 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3784 3785 return dd->sw_ctxt_err_status_cnt[4]; 3786 } 3787 3788 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry, 3789 void *context, int vl, int mode, 3790 u64 data) 3791 { 3792 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3793 3794 return dd->sw_ctxt_err_status_cnt[3]; 3795 } 3796 3797 static u64 access_pio_write_crosses_boundary_err_cnt( 3798 const struct cntr_entry *entry, 3799 void *context, int vl, int mode, u64 data) 3800 { 3801 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3802 3803 return dd->sw_ctxt_err_status_cnt[2]; 3804 } 3805 3806 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry, 3807 void *context, int vl, 3808 int mode, u64 data) 3809 { 3810 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3811 3812 return dd->sw_ctxt_err_status_cnt[1]; 3813 } 3814 3815 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry, 3816 void *context, int vl, int mode, 3817 u64 data) 3818 { 3819 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3820 3821 return dd->sw_ctxt_err_status_cnt[0]; 3822 } 3823 3824 /* 3825 * Software counters corresponding to each of the 3826 * error status bits within SendDmaEngErrStatus 3827 */ 3828 static u64 access_sdma_header_request_fifo_cor_err_cnt( 3829 const struct cntr_entry *entry, 3830 void *context, int vl, int mode, u64 data) 3831 { 3832 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3833 3834 return dd->sw_send_dma_eng_err_status_cnt[23]; 3835 } 3836 3837 static u64 access_sdma_header_storage_cor_err_cnt( 3838 const struct cntr_entry *entry, 3839 void *context, int vl, int mode, u64 data) 3840 { 3841 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3842 3843 return dd->sw_send_dma_eng_err_status_cnt[22]; 3844 } 3845 3846 static u64 access_sdma_packet_tracking_cor_err_cnt( 3847 const struct cntr_entry *entry, 3848 void *context, int vl, int mode, u64 data) 3849 { 3850 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3851 3852 return dd->sw_send_dma_eng_err_status_cnt[21]; 3853 } 3854 3855 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry, 3856 void *context, int vl, int mode, 3857 u64 data) 3858 { 3859 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3860 3861 return dd->sw_send_dma_eng_err_status_cnt[20]; 3862 } 3863 3864 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry, 3865 void *context, int vl, int mode, 3866 u64 data) 3867 { 3868 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3869 3870 return dd->sw_send_dma_eng_err_status_cnt[19]; 3871 } 3872 3873 static u64 access_sdma_header_request_fifo_unc_err_cnt( 3874 const struct cntr_entry *entry, 3875 void *context, int vl, int mode, u64 data) 3876 { 3877 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3878 3879 return dd->sw_send_dma_eng_err_status_cnt[18]; 3880 } 3881 3882 static u64 access_sdma_header_storage_unc_err_cnt( 3883 const struct cntr_entry *entry, 3884 void *context, int vl, int mode, u64 data) 3885 { 3886 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3887 3888 return dd->sw_send_dma_eng_err_status_cnt[17]; 3889 } 3890 3891 static u64 access_sdma_packet_tracking_unc_err_cnt( 3892 const struct cntr_entry *entry, 3893 void *context, int vl, int mode, u64 data) 3894 { 3895 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3896 3897 return dd->sw_send_dma_eng_err_status_cnt[16]; 3898 } 3899 3900 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry, 3901 void *context, int vl, int mode, 3902 u64 data) 3903 { 3904 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3905 3906 return dd->sw_send_dma_eng_err_status_cnt[15]; 3907 } 3908 3909 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry, 3910 void *context, int vl, int mode, 3911 u64 data) 3912 { 3913 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3914 3915 return dd->sw_send_dma_eng_err_status_cnt[14]; 3916 } 3917 3918 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry, 3919 void *context, int vl, int mode, 3920 u64 data) 3921 { 3922 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3923 3924 return dd->sw_send_dma_eng_err_status_cnt[13]; 3925 } 3926 3927 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry, 3928 void *context, int vl, int mode, 3929 u64 data) 3930 { 3931 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3932 3933 return dd->sw_send_dma_eng_err_status_cnt[12]; 3934 } 3935 3936 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry, 3937 void *context, int vl, int mode, 3938 u64 data) 3939 { 3940 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3941 3942 return dd->sw_send_dma_eng_err_status_cnt[11]; 3943 } 3944 3945 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry, 3946 void *context, int vl, int mode, 3947 u64 data) 3948 { 3949 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3950 3951 return dd->sw_send_dma_eng_err_status_cnt[10]; 3952 } 3953 3954 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry, 3955 void *context, int vl, int mode, 3956 u64 data) 3957 { 3958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3959 3960 return dd->sw_send_dma_eng_err_status_cnt[9]; 3961 } 3962 3963 static u64 access_sdma_packet_desc_overflow_err_cnt( 3964 const struct cntr_entry *entry, 3965 void *context, int vl, int mode, u64 data) 3966 { 3967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3968 3969 return dd->sw_send_dma_eng_err_status_cnt[8]; 3970 } 3971 3972 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry, 3973 void *context, int vl, 3974 int mode, u64 data) 3975 { 3976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3977 3978 return dd->sw_send_dma_eng_err_status_cnt[7]; 3979 } 3980 3981 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry, 3982 void *context, int vl, int mode, u64 data) 3983 { 3984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3985 3986 return dd->sw_send_dma_eng_err_status_cnt[6]; 3987 } 3988 3989 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry, 3990 void *context, int vl, int mode, 3991 u64 data) 3992 { 3993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 3994 3995 return dd->sw_send_dma_eng_err_status_cnt[5]; 3996 } 3997 3998 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry, 3999 void *context, int vl, int mode, 4000 u64 data) 4001 { 4002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4003 4004 return dd->sw_send_dma_eng_err_status_cnt[4]; 4005 } 4006 4007 static u64 access_sdma_tail_out_of_bounds_err_cnt( 4008 const struct cntr_entry *entry, 4009 void *context, int vl, int mode, u64 data) 4010 { 4011 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4012 4013 return dd->sw_send_dma_eng_err_status_cnt[3]; 4014 } 4015 4016 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry, 4017 void *context, int vl, int mode, 4018 u64 data) 4019 { 4020 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4021 4022 return dd->sw_send_dma_eng_err_status_cnt[2]; 4023 } 4024 4025 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry, 4026 void *context, int vl, int mode, 4027 u64 data) 4028 { 4029 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4030 4031 return dd->sw_send_dma_eng_err_status_cnt[1]; 4032 } 4033 4034 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry, 4035 void *context, int vl, int mode, 4036 u64 data) 4037 { 4038 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4039 4040 return dd->sw_send_dma_eng_err_status_cnt[0]; 4041 } 4042 4043 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry, 4044 void *context, int vl, int mode, 4045 u64 data) 4046 { 4047 struct hfi1_devdata *dd = (struct hfi1_devdata *)context; 4048 4049 u64 val = 0; 4050 u64 csr = entry->csr; 4051 4052 val = read_write_csr(dd, csr, mode, data); 4053 if (mode == CNTR_MODE_R) { 4054 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ? 4055 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors; 4056 } else if (mode == CNTR_MODE_W) { 4057 dd->sw_rcv_bypass_packet_errors = 0; 4058 } else { 4059 dd_dev_err(dd, "Invalid cntr register access mode"); 4060 return 0; 4061 } 4062 return val; 4063 } 4064 4065 #define def_access_sw_cpu(cntr) \ 4066 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \ 4067 void *context, int vl, int mode, u64 data) \ 4068 { \ 4069 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4070 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \ 4071 ppd->ibport_data.rvp.cntr, vl, \ 4072 mode, data); \ 4073 } 4074 4075 def_access_sw_cpu(rc_acks); 4076 def_access_sw_cpu(rc_qacks); 4077 def_access_sw_cpu(rc_delayed_comp); 4078 4079 #define def_access_ibp_counter(cntr) \ 4080 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \ 4081 void *context, int vl, int mode, u64 data) \ 4082 { \ 4083 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \ 4084 \ 4085 if (vl != CNTR_INVALID_VL) \ 4086 return 0; \ 4087 \ 4088 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \ 4089 mode, data); \ 4090 } 4091 4092 def_access_ibp_counter(loop_pkts); 4093 def_access_ibp_counter(rc_resends); 4094 def_access_ibp_counter(rnr_naks); 4095 def_access_ibp_counter(other_naks); 4096 def_access_ibp_counter(rc_timeouts); 4097 def_access_ibp_counter(pkt_drops); 4098 def_access_ibp_counter(dmawait); 4099 def_access_ibp_counter(rc_seqnak); 4100 def_access_ibp_counter(rc_dupreq); 4101 def_access_ibp_counter(rdma_seq); 4102 def_access_ibp_counter(unaligned); 4103 def_access_ibp_counter(seq_naks); 4104 4105 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = { 4106 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH), 4107 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT, 4108 CNTR_NORMAL), 4109 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT, 4110 CNTR_NORMAL), 4111 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs, 4112 RCV_TID_FLOW_GEN_MISMATCH_CNT, 4113 CNTR_NORMAL), 4114 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL, 4115 CNTR_NORMAL), 4116 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs, 4117 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL), 4118 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt, 4119 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL), 4120 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT, 4121 CNTR_NORMAL), 4122 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT, 4123 CNTR_NORMAL), 4124 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT, 4125 CNTR_NORMAL), 4126 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT, 4127 CNTR_NORMAL), 4128 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT, 4129 CNTR_NORMAL), 4130 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT, 4131 CNTR_NORMAL), 4132 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt, 4133 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL), 4134 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt, 4135 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL), 4136 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT, 4137 CNTR_SYNTH), 4138 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH, 4139 access_dc_rcv_err_cnt), 4140 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT, 4141 CNTR_SYNTH), 4142 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT, 4143 CNTR_SYNTH), 4144 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT, 4145 CNTR_SYNTH), 4146 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts, 4147 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH), 4148 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts, 4149 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT, 4150 CNTR_SYNTH), 4151 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr, 4152 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH), 4153 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT, 4154 CNTR_SYNTH), 4155 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT, 4156 CNTR_SYNTH), 4157 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT, 4158 CNTR_SYNTH), 4159 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT, 4160 CNTR_SYNTH), 4161 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT, 4162 CNTR_SYNTH), 4163 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT, 4164 CNTR_SYNTH), 4165 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT, 4166 CNTR_SYNTH), 4167 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT, 4168 CNTR_SYNTH | CNTR_VL), 4169 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT, 4170 CNTR_SYNTH | CNTR_VL), 4171 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH), 4172 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT, 4173 CNTR_SYNTH | CNTR_VL), 4174 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH), 4175 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT, 4176 CNTR_SYNTH | CNTR_VL), 4177 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT, 4178 CNTR_SYNTH), 4179 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT, 4180 CNTR_SYNTH | CNTR_VL), 4181 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT, 4182 CNTR_SYNTH), 4183 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT, 4184 CNTR_SYNTH | CNTR_VL), 4185 [C_DC_TOTAL_CRC] = 4186 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR, 4187 CNTR_SYNTH), 4188 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0, 4189 CNTR_SYNTH), 4190 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1, 4191 CNTR_SYNTH), 4192 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2, 4193 CNTR_SYNTH), 4194 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3, 4195 CNTR_SYNTH), 4196 [C_DC_CRC_MULT_LN] = 4197 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN, 4198 CNTR_SYNTH), 4199 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT, 4200 CNTR_SYNTH), 4201 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT, 4202 CNTR_SYNTH), 4203 [C_DC_SEQ_CRC_CNT] = 4204 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT, 4205 CNTR_SYNTH), 4206 [C_DC_ESC0_ONLY_CNT] = 4207 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT, 4208 CNTR_SYNTH), 4209 [C_DC_ESC0_PLUS1_CNT] = 4210 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT, 4211 CNTR_SYNTH), 4212 [C_DC_ESC0_PLUS2_CNT] = 4213 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT, 4214 CNTR_SYNTH), 4215 [C_DC_REINIT_FROM_PEER_CNT] = 4216 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 4217 CNTR_SYNTH), 4218 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT, 4219 CNTR_SYNTH), 4220 [C_DC_MISC_FLG_CNT] = 4221 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT, 4222 CNTR_SYNTH), 4223 [C_DC_PRF_GOOD_LTP_CNT] = 4224 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH), 4225 [C_DC_PRF_ACCEPTED_LTP_CNT] = 4226 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT, 4227 CNTR_SYNTH), 4228 [C_DC_PRF_RX_FLIT_CNT] = 4229 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH), 4230 [C_DC_PRF_TX_FLIT_CNT] = 4231 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH), 4232 [C_DC_PRF_CLK_CNTR] = 4233 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH), 4234 [C_DC_PG_DBG_FLIT_CRDTS_CNT] = 4235 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH), 4236 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] = 4237 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT, 4238 CNTR_SYNTH), 4239 [C_DC_PG_STS_TX_SBE_CNT] = 4240 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH), 4241 [C_DC_PG_STS_TX_MBE_CNT] = 4242 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT, 4243 CNTR_SYNTH), 4244 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL, 4245 access_sw_cpu_intr), 4246 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL, 4247 access_sw_cpu_rcv_limit), 4248 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL, 4249 access_sw_vtx_wait), 4250 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL, 4251 access_sw_pio_wait), 4252 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL, 4253 access_sw_pio_drain), 4254 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL, 4255 access_sw_kmem_wait), 4256 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL, 4257 access_sw_send_schedule), 4258 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn", 4259 SEND_DMA_DESC_FETCHED_CNT, 0, 4260 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4261 dev_access_u32_csr), 4262 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0, 4263 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4264 access_sde_int_cnt), 4265 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0, 4266 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4267 access_sde_err_cnt), 4268 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0, 4269 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4270 access_sde_idle_int_cnt), 4271 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0, 4272 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA, 4273 access_sde_progress_int_cnt), 4274 /* MISC_ERR_STATUS */ 4275 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0, 4276 CNTR_NORMAL, 4277 access_misc_pll_lock_fail_err_cnt), 4278 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0, 4279 CNTR_NORMAL, 4280 access_misc_mbist_fail_err_cnt), 4281 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0, 4282 CNTR_NORMAL, 4283 access_misc_invalid_eep_cmd_err_cnt), 4284 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0, 4285 CNTR_NORMAL, 4286 access_misc_efuse_done_parity_err_cnt), 4287 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0, 4288 CNTR_NORMAL, 4289 access_misc_efuse_write_err_cnt), 4290 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0, 4291 0, CNTR_NORMAL, 4292 access_misc_efuse_read_bad_addr_err_cnt), 4293 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0, 4294 CNTR_NORMAL, 4295 access_misc_efuse_csr_parity_err_cnt), 4296 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0, 4297 CNTR_NORMAL, 4298 access_misc_fw_auth_failed_err_cnt), 4299 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0, 4300 CNTR_NORMAL, 4301 access_misc_key_mismatch_err_cnt), 4302 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0, 4303 CNTR_NORMAL, 4304 access_misc_sbus_write_failed_err_cnt), 4305 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0, 4306 CNTR_NORMAL, 4307 access_misc_csr_write_bad_addr_err_cnt), 4308 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0, 4309 CNTR_NORMAL, 4310 access_misc_csr_read_bad_addr_err_cnt), 4311 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0, 4312 CNTR_NORMAL, 4313 access_misc_csr_parity_err_cnt), 4314 /* CceErrStatus */ 4315 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0, 4316 CNTR_NORMAL, 4317 access_sw_cce_err_status_aggregated_cnt), 4318 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0, 4319 CNTR_NORMAL, 4320 access_cce_msix_csr_parity_err_cnt), 4321 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0, 4322 CNTR_NORMAL, 4323 access_cce_int_map_unc_err_cnt), 4324 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0, 4325 CNTR_NORMAL, 4326 access_cce_int_map_cor_err_cnt), 4327 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0, 4328 CNTR_NORMAL, 4329 access_cce_msix_table_unc_err_cnt), 4330 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0, 4331 CNTR_NORMAL, 4332 access_cce_msix_table_cor_err_cnt), 4333 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0, 4334 0, CNTR_NORMAL, 4335 access_cce_rxdma_conv_fifo_parity_err_cnt), 4336 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0, 4337 0, CNTR_NORMAL, 4338 access_cce_rcpl_async_fifo_parity_err_cnt), 4339 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0, 4340 CNTR_NORMAL, 4341 access_cce_seg_write_bad_addr_err_cnt), 4342 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0, 4343 CNTR_NORMAL, 4344 access_cce_seg_read_bad_addr_err_cnt), 4345 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0, 4346 CNTR_NORMAL, 4347 access_la_triggered_cnt), 4348 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0, 4349 CNTR_NORMAL, 4350 access_cce_trgt_cpl_timeout_err_cnt), 4351 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0, 4352 CNTR_NORMAL, 4353 access_pcic_receive_parity_err_cnt), 4354 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0, 4355 CNTR_NORMAL, 4356 access_pcic_transmit_back_parity_err_cnt), 4357 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0, 4358 0, CNTR_NORMAL, 4359 access_pcic_transmit_front_parity_err_cnt), 4360 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0, 4361 CNTR_NORMAL, 4362 access_pcic_cpl_dat_q_unc_err_cnt), 4363 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0, 4364 CNTR_NORMAL, 4365 access_pcic_cpl_hd_q_unc_err_cnt), 4366 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0, 4367 CNTR_NORMAL, 4368 access_pcic_post_dat_q_unc_err_cnt), 4369 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0, 4370 CNTR_NORMAL, 4371 access_pcic_post_hd_q_unc_err_cnt), 4372 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0, 4373 CNTR_NORMAL, 4374 access_pcic_retry_sot_mem_unc_err_cnt), 4375 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0, 4376 CNTR_NORMAL, 4377 access_pcic_retry_mem_unc_err), 4378 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0, 4379 CNTR_NORMAL, 4380 access_pcic_n_post_dat_q_parity_err_cnt), 4381 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0, 4382 CNTR_NORMAL, 4383 access_pcic_n_post_h_q_parity_err_cnt), 4384 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0, 4385 CNTR_NORMAL, 4386 access_pcic_cpl_dat_q_cor_err_cnt), 4387 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0, 4388 CNTR_NORMAL, 4389 access_pcic_cpl_hd_q_cor_err_cnt), 4390 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0, 4391 CNTR_NORMAL, 4392 access_pcic_post_dat_q_cor_err_cnt), 4393 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0, 4394 CNTR_NORMAL, 4395 access_pcic_post_hd_q_cor_err_cnt), 4396 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0, 4397 CNTR_NORMAL, 4398 access_pcic_retry_sot_mem_cor_err_cnt), 4399 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0, 4400 CNTR_NORMAL, 4401 access_pcic_retry_mem_cor_err_cnt), 4402 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM( 4403 "CceCli1AsyncFifoDbgParityError", 0, 0, 4404 CNTR_NORMAL, 4405 access_cce_cli1_async_fifo_dbg_parity_err_cnt), 4406 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM( 4407 "CceCli1AsyncFifoRxdmaParityError", 0, 0, 4408 CNTR_NORMAL, 4409 access_cce_cli1_async_fifo_rxdma_parity_err_cnt 4410 ), 4411 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM( 4412 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0, 4413 CNTR_NORMAL, 4414 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt), 4415 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM( 4416 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0, 4417 CNTR_NORMAL, 4418 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt), 4419 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0, 4420 0, CNTR_NORMAL, 4421 access_cce_cli2_async_fifo_parity_err_cnt), 4422 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0, 4423 CNTR_NORMAL, 4424 access_cce_csr_cfg_bus_parity_err_cnt), 4425 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0, 4426 0, CNTR_NORMAL, 4427 access_cce_cli0_async_fifo_parity_err_cnt), 4428 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0, 4429 CNTR_NORMAL, 4430 access_cce_rspd_data_parity_err_cnt), 4431 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0, 4432 CNTR_NORMAL, 4433 access_cce_trgt_access_err_cnt), 4434 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0, 4435 0, CNTR_NORMAL, 4436 access_cce_trgt_async_fifo_parity_err_cnt), 4437 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0, 4438 CNTR_NORMAL, 4439 access_cce_csr_write_bad_addr_err_cnt), 4440 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0, 4441 CNTR_NORMAL, 4442 access_cce_csr_read_bad_addr_err_cnt), 4443 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0, 4444 CNTR_NORMAL, 4445 access_ccs_csr_parity_err_cnt), 4446 4447 /* RcvErrStatus */ 4448 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0, 4449 CNTR_NORMAL, 4450 access_rx_csr_parity_err_cnt), 4451 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0, 4452 CNTR_NORMAL, 4453 access_rx_csr_write_bad_addr_err_cnt), 4454 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0, 4455 CNTR_NORMAL, 4456 access_rx_csr_read_bad_addr_err_cnt), 4457 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0, 4458 CNTR_NORMAL, 4459 access_rx_dma_csr_unc_err_cnt), 4460 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0, 4461 CNTR_NORMAL, 4462 access_rx_dma_dq_fsm_encoding_err_cnt), 4463 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0, 4464 CNTR_NORMAL, 4465 access_rx_dma_eq_fsm_encoding_err_cnt), 4466 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0, 4467 CNTR_NORMAL, 4468 access_rx_dma_csr_parity_err_cnt), 4469 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0, 4470 CNTR_NORMAL, 4471 access_rx_rbuf_data_cor_err_cnt), 4472 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0, 4473 CNTR_NORMAL, 4474 access_rx_rbuf_data_unc_err_cnt), 4475 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0, 4476 CNTR_NORMAL, 4477 access_rx_dma_data_fifo_rd_cor_err_cnt), 4478 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0, 4479 CNTR_NORMAL, 4480 access_rx_dma_data_fifo_rd_unc_err_cnt), 4481 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0, 4482 CNTR_NORMAL, 4483 access_rx_dma_hdr_fifo_rd_cor_err_cnt), 4484 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0, 4485 CNTR_NORMAL, 4486 access_rx_dma_hdr_fifo_rd_unc_err_cnt), 4487 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0, 4488 CNTR_NORMAL, 4489 access_rx_rbuf_desc_part2_cor_err_cnt), 4490 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0, 4491 CNTR_NORMAL, 4492 access_rx_rbuf_desc_part2_unc_err_cnt), 4493 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0, 4494 CNTR_NORMAL, 4495 access_rx_rbuf_desc_part1_cor_err_cnt), 4496 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0, 4497 CNTR_NORMAL, 4498 access_rx_rbuf_desc_part1_unc_err_cnt), 4499 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0, 4500 CNTR_NORMAL, 4501 access_rx_hq_intr_fsm_err_cnt), 4502 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0, 4503 CNTR_NORMAL, 4504 access_rx_hq_intr_csr_parity_err_cnt), 4505 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0, 4506 CNTR_NORMAL, 4507 access_rx_lookup_csr_parity_err_cnt), 4508 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0, 4509 CNTR_NORMAL, 4510 access_rx_lookup_rcv_array_cor_err_cnt), 4511 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0, 4512 CNTR_NORMAL, 4513 access_rx_lookup_rcv_array_unc_err_cnt), 4514 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0, 4515 0, CNTR_NORMAL, 4516 access_rx_lookup_des_part2_parity_err_cnt), 4517 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0, 4518 0, CNTR_NORMAL, 4519 access_rx_lookup_des_part1_unc_cor_err_cnt), 4520 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0, 4521 CNTR_NORMAL, 4522 access_rx_lookup_des_part1_unc_err_cnt), 4523 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0, 4524 CNTR_NORMAL, 4525 access_rx_rbuf_next_free_buf_cor_err_cnt), 4526 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0, 4527 CNTR_NORMAL, 4528 access_rx_rbuf_next_free_buf_unc_err_cnt), 4529 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM( 4530 "RxRbufFlInitWrAddrParityErr", 0, 0, 4531 CNTR_NORMAL, 4532 access_rbuf_fl_init_wr_addr_parity_err_cnt), 4533 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0, 4534 0, CNTR_NORMAL, 4535 access_rx_rbuf_fl_initdone_parity_err_cnt), 4536 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0, 4537 0, CNTR_NORMAL, 4538 access_rx_rbuf_fl_write_addr_parity_err_cnt), 4539 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0, 4540 CNTR_NORMAL, 4541 access_rx_rbuf_fl_rd_addr_parity_err_cnt), 4542 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0, 4543 CNTR_NORMAL, 4544 access_rx_rbuf_empty_err_cnt), 4545 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0, 4546 CNTR_NORMAL, 4547 access_rx_rbuf_full_err_cnt), 4548 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0, 4549 CNTR_NORMAL, 4550 access_rbuf_bad_lookup_err_cnt), 4551 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0, 4552 CNTR_NORMAL, 4553 access_rbuf_ctx_id_parity_err_cnt), 4554 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0, 4555 CNTR_NORMAL, 4556 access_rbuf_csr_qeopdw_parity_err_cnt), 4557 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM( 4558 "RxRbufCsrQNumOfPktParityErr", 0, 0, 4559 CNTR_NORMAL, 4560 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt), 4561 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM( 4562 "RxRbufCsrQTlPtrParityErr", 0, 0, 4563 CNTR_NORMAL, 4564 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt), 4565 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0, 4566 0, CNTR_NORMAL, 4567 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt), 4568 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0, 4569 0, CNTR_NORMAL, 4570 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt), 4571 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr", 4572 0, 0, CNTR_NORMAL, 4573 access_rx_rbuf_csr_q_next_buf_parity_err_cnt), 4574 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0, 4575 0, CNTR_NORMAL, 4576 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt), 4577 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM( 4578 "RxRbufCsrQHeadBufNumParityErr", 0, 0, 4579 CNTR_NORMAL, 4580 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt), 4581 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0, 4582 0, CNTR_NORMAL, 4583 access_rx_rbuf_block_list_read_cor_err_cnt), 4584 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0, 4585 0, CNTR_NORMAL, 4586 access_rx_rbuf_block_list_read_unc_err_cnt), 4587 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0, 4588 CNTR_NORMAL, 4589 access_rx_rbuf_lookup_des_cor_err_cnt), 4590 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0, 4591 CNTR_NORMAL, 4592 access_rx_rbuf_lookup_des_unc_err_cnt), 4593 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM( 4594 "RxRbufLookupDesRegUncCorErr", 0, 0, 4595 CNTR_NORMAL, 4596 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt), 4597 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0, 4598 CNTR_NORMAL, 4599 access_rx_rbuf_lookup_des_reg_unc_err_cnt), 4600 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0, 4601 CNTR_NORMAL, 4602 access_rx_rbuf_free_list_cor_err_cnt), 4603 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0, 4604 CNTR_NORMAL, 4605 access_rx_rbuf_free_list_unc_err_cnt), 4606 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0, 4607 CNTR_NORMAL, 4608 access_rx_rcv_fsm_encoding_err_cnt), 4609 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0, 4610 CNTR_NORMAL, 4611 access_rx_dma_flag_cor_err_cnt), 4612 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0, 4613 CNTR_NORMAL, 4614 access_rx_dma_flag_unc_err_cnt), 4615 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0, 4616 CNTR_NORMAL, 4617 access_rx_dc_sop_eop_parity_err_cnt), 4618 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0, 4619 CNTR_NORMAL, 4620 access_rx_rcv_csr_parity_err_cnt), 4621 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0, 4622 CNTR_NORMAL, 4623 access_rx_rcv_qp_map_table_cor_err_cnt), 4624 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0, 4625 CNTR_NORMAL, 4626 access_rx_rcv_qp_map_table_unc_err_cnt), 4627 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0, 4628 CNTR_NORMAL, 4629 access_rx_rcv_data_cor_err_cnt), 4630 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0, 4631 CNTR_NORMAL, 4632 access_rx_rcv_data_unc_err_cnt), 4633 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0, 4634 CNTR_NORMAL, 4635 access_rx_rcv_hdr_cor_err_cnt), 4636 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0, 4637 CNTR_NORMAL, 4638 access_rx_rcv_hdr_unc_err_cnt), 4639 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0, 4640 CNTR_NORMAL, 4641 access_rx_dc_intf_parity_err_cnt), 4642 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0, 4643 CNTR_NORMAL, 4644 access_rx_dma_csr_cor_err_cnt), 4645 /* SendPioErrStatus */ 4646 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0, 4647 CNTR_NORMAL, 4648 access_pio_pec_sop_head_parity_err_cnt), 4649 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0, 4650 CNTR_NORMAL, 4651 access_pio_pcc_sop_head_parity_err_cnt), 4652 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr", 4653 0, 0, CNTR_NORMAL, 4654 access_pio_last_returned_cnt_parity_err_cnt), 4655 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0, 4656 0, CNTR_NORMAL, 4657 access_pio_current_free_cnt_parity_err_cnt), 4658 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0, 4659 CNTR_NORMAL, 4660 access_pio_reserved_31_err_cnt), 4661 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0, 4662 CNTR_NORMAL, 4663 access_pio_reserved_30_err_cnt), 4664 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0, 4665 CNTR_NORMAL, 4666 access_pio_ppmc_sop_len_err_cnt), 4667 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0, 4668 CNTR_NORMAL, 4669 access_pio_ppmc_bqc_mem_parity_err_cnt), 4670 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0, 4671 CNTR_NORMAL, 4672 access_pio_vl_fifo_parity_err_cnt), 4673 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0, 4674 CNTR_NORMAL, 4675 access_pio_vlf_sop_parity_err_cnt), 4676 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0, 4677 CNTR_NORMAL, 4678 access_pio_vlf_v1_len_parity_err_cnt), 4679 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0, 4680 CNTR_NORMAL, 4681 access_pio_block_qw_count_parity_err_cnt), 4682 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0, 4683 CNTR_NORMAL, 4684 access_pio_write_qw_valid_parity_err_cnt), 4685 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0, 4686 CNTR_NORMAL, 4687 access_pio_state_machine_err_cnt), 4688 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0, 4689 CNTR_NORMAL, 4690 access_pio_write_data_parity_err_cnt), 4691 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0, 4692 CNTR_NORMAL, 4693 access_pio_host_addr_mem_cor_err_cnt), 4694 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0, 4695 CNTR_NORMAL, 4696 access_pio_host_addr_mem_unc_err_cnt), 4697 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0, 4698 CNTR_NORMAL, 4699 access_pio_pkt_evict_sm_or_arb_sm_err_cnt), 4700 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0, 4701 CNTR_NORMAL, 4702 access_pio_init_sm_in_err_cnt), 4703 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0, 4704 CNTR_NORMAL, 4705 access_pio_ppmc_pbl_fifo_err_cnt), 4706 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0, 4707 0, CNTR_NORMAL, 4708 access_pio_credit_ret_fifo_parity_err_cnt), 4709 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0, 4710 CNTR_NORMAL, 4711 access_pio_v1_len_mem_bank1_cor_err_cnt), 4712 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0, 4713 CNTR_NORMAL, 4714 access_pio_v1_len_mem_bank0_cor_err_cnt), 4715 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0, 4716 CNTR_NORMAL, 4717 access_pio_v1_len_mem_bank1_unc_err_cnt), 4718 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0, 4719 CNTR_NORMAL, 4720 access_pio_v1_len_mem_bank0_unc_err_cnt), 4721 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0, 4722 CNTR_NORMAL, 4723 access_pio_sm_pkt_reset_parity_err_cnt), 4724 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0, 4725 CNTR_NORMAL, 4726 access_pio_pkt_evict_fifo_parity_err_cnt), 4727 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM( 4728 "PioSbrdctrlCrrelFifoParityErr", 0, 0, 4729 CNTR_NORMAL, 4730 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt), 4731 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0, 4732 CNTR_NORMAL, 4733 access_pio_sbrdctl_crrel_parity_err_cnt), 4734 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0, 4735 CNTR_NORMAL, 4736 access_pio_pec_fifo_parity_err_cnt), 4737 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0, 4738 CNTR_NORMAL, 4739 access_pio_pcc_fifo_parity_err_cnt), 4740 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0, 4741 CNTR_NORMAL, 4742 access_pio_sb_mem_fifo1_err_cnt), 4743 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0, 4744 CNTR_NORMAL, 4745 access_pio_sb_mem_fifo0_err_cnt), 4746 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0, 4747 CNTR_NORMAL, 4748 access_pio_csr_parity_err_cnt), 4749 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0, 4750 CNTR_NORMAL, 4751 access_pio_write_addr_parity_err_cnt), 4752 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0, 4753 CNTR_NORMAL, 4754 access_pio_write_bad_ctxt_err_cnt), 4755 /* SendDmaErrStatus */ 4756 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0, 4757 0, CNTR_NORMAL, 4758 access_sdma_pcie_req_tracking_cor_err_cnt), 4759 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0, 4760 0, CNTR_NORMAL, 4761 access_sdma_pcie_req_tracking_unc_err_cnt), 4762 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0, 4763 CNTR_NORMAL, 4764 access_sdma_csr_parity_err_cnt), 4765 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0, 4766 CNTR_NORMAL, 4767 access_sdma_rpy_tag_err_cnt), 4768 /* SendEgressErrStatus */ 4769 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0, 4770 CNTR_NORMAL, 4771 access_tx_read_pio_memory_csr_unc_err_cnt), 4772 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0, 4773 0, CNTR_NORMAL, 4774 access_tx_read_sdma_memory_csr_err_cnt), 4775 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0, 4776 CNTR_NORMAL, 4777 access_tx_egress_fifo_cor_err_cnt), 4778 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0, 4779 CNTR_NORMAL, 4780 access_tx_read_pio_memory_cor_err_cnt), 4781 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0, 4782 CNTR_NORMAL, 4783 access_tx_read_sdma_memory_cor_err_cnt), 4784 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0, 4785 CNTR_NORMAL, 4786 access_tx_sb_hdr_cor_err_cnt), 4787 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0, 4788 CNTR_NORMAL, 4789 access_tx_credit_overrun_err_cnt), 4790 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0, 4791 CNTR_NORMAL, 4792 access_tx_launch_fifo8_cor_err_cnt), 4793 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0, 4794 CNTR_NORMAL, 4795 access_tx_launch_fifo7_cor_err_cnt), 4796 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0, 4797 CNTR_NORMAL, 4798 access_tx_launch_fifo6_cor_err_cnt), 4799 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0, 4800 CNTR_NORMAL, 4801 access_tx_launch_fifo5_cor_err_cnt), 4802 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0, 4803 CNTR_NORMAL, 4804 access_tx_launch_fifo4_cor_err_cnt), 4805 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0, 4806 CNTR_NORMAL, 4807 access_tx_launch_fifo3_cor_err_cnt), 4808 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0, 4809 CNTR_NORMAL, 4810 access_tx_launch_fifo2_cor_err_cnt), 4811 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0, 4812 CNTR_NORMAL, 4813 access_tx_launch_fifo1_cor_err_cnt), 4814 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0, 4815 CNTR_NORMAL, 4816 access_tx_launch_fifo0_cor_err_cnt), 4817 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0, 4818 CNTR_NORMAL, 4819 access_tx_credit_return_vl_err_cnt), 4820 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0, 4821 CNTR_NORMAL, 4822 access_tx_hcrc_insertion_err_cnt), 4823 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0, 4824 CNTR_NORMAL, 4825 access_tx_egress_fifo_unc_err_cnt), 4826 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0, 4827 CNTR_NORMAL, 4828 access_tx_read_pio_memory_unc_err_cnt), 4829 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0, 4830 CNTR_NORMAL, 4831 access_tx_read_sdma_memory_unc_err_cnt), 4832 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0, 4833 CNTR_NORMAL, 4834 access_tx_sb_hdr_unc_err_cnt), 4835 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0, 4836 CNTR_NORMAL, 4837 access_tx_credit_return_partiy_err_cnt), 4838 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr", 4839 0, 0, CNTR_NORMAL, 4840 access_tx_launch_fifo8_unc_or_parity_err_cnt), 4841 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr", 4842 0, 0, CNTR_NORMAL, 4843 access_tx_launch_fifo7_unc_or_parity_err_cnt), 4844 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr", 4845 0, 0, CNTR_NORMAL, 4846 access_tx_launch_fifo6_unc_or_parity_err_cnt), 4847 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr", 4848 0, 0, CNTR_NORMAL, 4849 access_tx_launch_fifo5_unc_or_parity_err_cnt), 4850 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr", 4851 0, 0, CNTR_NORMAL, 4852 access_tx_launch_fifo4_unc_or_parity_err_cnt), 4853 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr", 4854 0, 0, CNTR_NORMAL, 4855 access_tx_launch_fifo3_unc_or_parity_err_cnt), 4856 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr", 4857 0, 0, CNTR_NORMAL, 4858 access_tx_launch_fifo2_unc_or_parity_err_cnt), 4859 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr", 4860 0, 0, CNTR_NORMAL, 4861 access_tx_launch_fifo1_unc_or_parity_err_cnt), 4862 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr", 4863 0, 0, CNTR_NORMAL, 4864 access_tx_launch_fifo0_unc_or_parity_err_cnt), 4865 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr", 4866 0, 0, CNTR_NORMAL, 4867 access_tx_sdma15_disallowed_packet_err_cnt), 4868 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr", 4869 0, 0, CNTR_NORMAL, 4870 access_tx_sdma14_disallowed_packet_err_cnt), 4871 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr", 4872 0, 0, CNTR_NORMAL, 4873 access_tx_sdma13_disallowed_packet_err_cnt), 4874 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr", 4875 0, 0, CNTR_NORMAL, 4876 access_tx_sdma12_disallowed_packet_err_cnt), 4877 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr", 4878 0, 0, CNTR_NORMAL, 4879 access_tx_sdma11_disallowed_packet_err_cnt), 4880 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr", 4881 0, 0, CNTR_NORMAL, 4882 access_tx_sdma10_disallowed_packet_err_cnt), 4883 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr", 4884 0, 0, CNTR_NORMAL, 4885 access_tx_sdma9_disallowed_packet_err_cnt), 4886 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr", 4887 0, 0, CNTR_NORMAL, 4888 access_tx_sdma8_disallowed_packet_err_cnt), 4889 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr", 4890 0, 0, CNTR_NORMAL, 4891 access_tx_sdma7_disallowed_packet_err_cnt), 4892 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr", 4893 0, 0, CNTR_NORMAL, 4894 access_tx_sdma6_disallowed_packet_err_cnt), 4895 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr", 4896 0, 0, CNTR_NORMAL, 4897 access_tx_sdma5_disallowed_packet_err_cnt), 4898 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr", 4899 0, 0, CNTR_NORMAL, 4900 access_tx_sdma4_disallowed_packet_err_cnt), 4901 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr", 4902 0, 0, CNTR_NORMAL, 4903 access_tx_sdma3_disallowed_packet_err_cnt), 4904 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr", 4905 0, 0, CNTR_NORMAL, 4906 access_tx_sdma2_disallowed_packet_err_cnt), 4907 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr", 4908 0, 0, CNTR_NORMAL, 4909 access_tx_sdma1_disallowed_packet_err_cnt), 4910 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr", 4911 0, 0, CNTR_NORMAL, 4912 access_tx_sdma0_disallowed_packet_err_cnt), 4913 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0, 4914 CNTR_NORMAL, 4915 access_tx_config_parity_err_cnt), 4916 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0, 4917 CNTR_NORMAL, 4918 access_tx_sbrd_ctl_csr_parity_err_cnt), 4919 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0, 4920 CNTR_NORMAL, 4921 access_tx_launch_csr_parity_err_cnt), 4922 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0, 4923 CNTR_NORMAL, 4924 access_tx_illegal_vl_err_cnt), 4925 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM( 4926 "TxSbrdCtlStateMachineParityErr", 0, 0, 4927 CNTR_NORMAL, 4928 access_tx_sbrd_ctl_state_machine_parity_err_cnt), 4929 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0, 4930 CNTR_NORMAL, 4931 access_egress_reserved_10_err_cnt), 4932 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0, 4933 CNTR_NORMAL, 4934 access_egress_reserved_9_err_cnt), 4935 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr", 4936 0, 0, CNTR_NORMAL, 4937 access_tx_sdma_launch_intf_parity_err_cnt), 4938 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0, 4939 CNTR_NORMAL, 4940 access_tx_pio_launch_intf_parity_err_cnt), 4941 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0, 4942 CNTR_NORMAL, 4943 access_egress_reserved_6_err_cnt), 4944 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0, 4945 CNTR_NORMAL, 4946 access_tx_incorrect_link_state_err_cnt), 4947 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0, 4948 CNTR_NORMAL, 4949 access_tx_linkdown_err_cnt), 4950 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM( 4951 "EgressFifoUnderrunOrParityErr", 0, 0, 4952 CNTR_NORMAL, 4953 access_tx_egress_fifi_underrun_or_parity_err_cnt), 4954 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0, 4955 CNTR_NORMAL, 4956 access_egress_reserved_2_err_cnt), 4957 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0, 4958 CNTR_NORMAL, 4959 access_tx_pkt_integrity_mem_unc_err_cnt), 4960 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0, 4961 CNTR_NORMAL, 4962 access_tx_pkt_integrity_mem_cor_err_cnt), 4963 /* SendErrStatus */ 4964 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0, 4965 CNTR_NORMAL, 4966 access_send_csr_write_bad_addr_err_cnt), 4967 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0, 4968 CNTR_NORMAL, 4969 access_send_csr_read_bad_addr_err_cnt), 4970 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0, 4971 CNTR_NORMAL, 4972 access_send_csr_parity_cnt), 4973 /* SendCtxtErrStatus */ 4974 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0, 4975 CNTR_NORMAL, 4976 access_pio_write_out_of_bounds_err_cnt), 4977 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0, 4978 CNTR_NORMAL, 4979 access_pio_write_overflow_err_cnt), 4980 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr", 4981 0, 0, CNTR_NORMAL, 4982 access_pio_write_crosses_boundary_err_cnt), 4983 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0, 4984 CNTR_NORMAL, 4985 access_pio_disallowed_packet_err_cnt), 4986 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0, 4987 CNTR_NORMAL, 4988 access_pio_inconsistent_sop_err_cnt), 4989 /* SendDmaEngErrStatus */ 4990 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr", 4991 0, 0, CNTR_NORMAL, 4992 access_sdma_header_request_fifo_cor_err_cnt), 4993 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0, 4994 CNTR_NORMAL, 4995 access_sdma_header_storage_cor_err_cnt), 4996 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0, 4997 CNTR_NORMAL, 4998 access_sdma_packet_tracking_cor_err_cnt), 4999 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0, 5000 CNTR_NORMAL, 5001 access_sdma_assembly_cor_err_cnt), 5002 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0, 5003 CNTR_NORMAL, 5004 access_sdma_desc_table_cor_err_cnt), 5005 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr", 5006 0, 0, CNTR_NORMAL, 5007 access_sdma_header_request_fifo_unc_err_cnt), 5008 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0, 5009 CNTR_NORMAL, 5010 access_sdma_header_storage_unc_err_cnt), 5011 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0, 5012 CNTR_NORMAL, 5013 access_sdma_packet_tracking_unc_err_cnt), 5014 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0, 5015 CNTR_NORMAL, 5016 access_sdma_assembly_unc_err_cnt), 5017 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0, 5018 CNTR_NORMAL, 5019 access_sdma_desc_table_unc_err_cnt), 5020 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0, 5021 CNTR_NORMAL, 5022 access_sdma_timeout_err_cnt), 5023 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0, 5024 CNTR_NORMAL, 5025 access_sdma_header_length_err_cnt), 5026 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0, 5027 CNTR_NORMAL, 5028 access_sdma_header_address_err_cnt), 5029 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0, 5030 CNTR_NORMAL, 5031 access_sdma_header_select_err_cnt), 5032 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0, 5033 CNTR_NORMAL, 5034 access_sdma_reserved_9_err_cnt), 5035 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0, 5036 CNTR_NORMAL, 5037 access_sdma_packet_desc_overflow_err_cnt), 5038 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0, 5039 CNTR_NORMAL, 5040 access_sdma_length_mismatch_err_cnt), 5041 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0, 5042 CNTR_NORMAL, 5043 access_sdma_halt_err_cnt), 5044 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0, 5045 CNTR_NORMAL, 5046 access_sdma_mem_read_err_cnt), 5047 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0, 5048 CNTR_NORMAL, 5049 access_sdma_first_desc_err_cnt), 5050 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0, 5051 CNTR_NORMAL, 5052 access_sdma_tail_out_of_bounds_err_cnt), 5053 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0, 5054 CNTR_NORMAL, 5055 access_sdma_too_long_err_cnt), 5056 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0, 5057 CNTR_NORMAL, 5058 access_sdma_gen_mismatch_err_cnt), 5059 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0, 5060 CNTR_NORMAL, 5061 access_sdma_wrong_dw_err_cnt), 5062 }; 5063 5064 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = { 5065 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT, 5066 CNTR_NORMAL), 5067 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT, 5068 CNTR_NORMAL), 5069 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT, 5070 CNTR_NORMAL), 5071 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT, 5072 CNTR_NORMAL), 5073 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT, 5074 CNTR_NORMAL), 5075 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT, 5076 CNTR_NORMAL), 5077 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT, 5078 CNTR_NORMAL), 5079 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL), 5080 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL), 5081 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH), 5082 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT, 5083 CNTR_SYNTH | CNTR_VL), 5084 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT, 5085 CNTR_SYNTH | CNTR_VL), 5086 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT, 5087 CNTR_SYNTH | CNTR_VL), 5088 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL), 5089 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL), 5090 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5091 access_sw_link_dn_cnt), 5092 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5093 access_sw_link_up_cnt), 5094 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL, 5095 access_sw_unknown_frame_cnt), 5096 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT, 5097 access_sw_xmit_discards), 5098 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0, 5099 CNTR_SYNTH | CNTR_32BIT | CNTR_VL, 5100 access_sw_xmit_discards), 5101 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH, 5102 access_xmit_constraint_errs), 5103 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH, 5104 access_rcv_constraint_errs), 5105 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts), 5106 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends), 5107 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks), 5108 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks), 5109 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts), 5110 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops), 5111 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait), 5112 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak), 5113 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq), 5114 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq), 5115 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned), 5116 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks), 5117 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL, 5118 access_sw_cpu_rc_acks), 5119 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL, 5120 access_sw_cpu_rc_qacks), 5121 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL, 5122 access_sw_cpu_rc_delayed_comp), 5123 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1), 5124 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3), 5125 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5), 5126 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7), 5127 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9), 5128 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11), 5129 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13), 5130 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15), 5131 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17), 5132 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19), 5133 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21), 5134 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23), 5135 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25), 5136 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27), 5137 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29), 5138 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31), 5139 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33), 5140 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35), 5141 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37), 5142 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39), 5143 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41), 5144 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43), 5145 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45), 5146 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47), 5147 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49), 5148 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51), 5149 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53), 5150 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55), 5151 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57), 5152 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59), 5153 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61), 5154 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63), 5155 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65), 5156 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67), 5157 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69), 5158 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71), 5159 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73), 5160 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75), 5161 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77), 5162 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79), 5163 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81), 5164 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83), 5165 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85), 5166 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87), 5167 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89), 5168 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91), 5169 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93), 5170 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95), 5171 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97), 5172 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99), 5173 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101), 5174 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103), 5175 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105), 5176 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107), 5177 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109), 5178 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111), 5179 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113), 5180 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115), 5181 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117), 5182 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119), 5183 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121), 5184 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123), 5185 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125), 5186 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127), 5187 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129), 5188 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131), 5189 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133), 5190 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135), 5191 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137), 5192 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139), 5193 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141), 5194 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143), 5195 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145), 5196 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147), 5197 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149), 5198 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151), 5199 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153), 5200 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155), 5201 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157), 5202 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159), 5203 }; 5204 5205 /* ======================================================================== */ 5206 5207 /* return true if this is chip revision revision a */ 5208 int is_ax(struct hfi1_devdata *dd) 5209 { 5210 u8 chip_rev_minor = 5211 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5212 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5213 return (chip_rev_minor & 0xf0) == 0; 5214 } 5215 5216 /* return true if this is chip revision revision b */ 5217 int is_bx(struct hfi1_devdata *dd) 5218 { 5219 u8 chip_rev_minor = 5220 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT 5221 & CCE_REVISION_CHIP_REV_MINOR_MASK; 5222 return (chip_rev_minor & 0xF0) == 0x10; 5223 } 5224 5225 /* 5226 * Append string s to buffer buf. Arguments curp and len are the current 5227 * position and remaining length, respectively. 5228 * 5229 * return 0 on success, 1 on out of room 5230 */ 5231 static int append_str(char *buf, char **curp, int *lenp, const char *s) 5232 { 5233 char *p = *curp; 5234 int len = *lenp; 5235 int result = 0; /* success */ 5236 char c; 5237 5238 /* add a comma, if first in the buffer */ 5239 if (p != buf) { 5240 if (len == 0) { 5241 result = 1; /* out of room */ 5242 goto done; 5243 } 5244 *p++ = ','; 5245 len--; 5246 } 5247 5248 /* copy the string */ 5249 while ((c = *s++) != 0) { 5250 if (len == 0) { 5251 result = 1; /* out of room */ 5252 goto done; 5253 } 5254 *p++ = c; 5255 len--; 5256 } 5257 5258 done: 5259 /* write return values */ 5260 *curp = p; 5261 *lenp = len; 5262 5263 return result; 5264 } 5265 5266 /* 5267 * Using the given flag table, print a comma separated string into 5268 * the buffer. End in '*' if the buffer is too short. 5269 */ 5270 static char *flag_string(char *buf, int buf_len, u64 flags, 5271 struct flag_table *table, int table_size) 5272 { 5273 char extra[32]; 5274 char *p = buf; 5275 int len = buf_len; 5276 int no_room = 0; 5277 int i; 5278 5279 /* make sure there is at least 2 so we can form "*" */ 5280 if (len < 2) 5281 return ""; 5282 5283 len--; /* leave room for a nul */ 5284 for (i = 0; i < table_size; i++) { 5285 if (flags & table[i].flag) { 5286 no_room = append_str(buf, &p, &len, table[i].str); 5287 if (no_room) 5288 break; 5289 flags &= ~table[i].flag; 5290 } 5291 } 5292 5293 /* any undocumented bits left? */ 5294 if (!no_room && flags) { 5295 snprintf(extra, sizeof(extra), "bits 0x%llx", flags); 5296 no_room = append_str(buf, &p, &len, extra); 5297 } 5298 5299 /* add * if ran out of room */ 5300 if (no_room) { 5301 /* may need to back up to add space for a '*' */ 5302 if (len == 0) 5303 --p; 5304 *p++ = '*'; 5305 } 5306 5307 /* add final nul - space already allocated above */ 5308 *p = 0; 5309 return buf; 5310 } 5311 5312 /* first 8 CCE error interrupt source names */ 5313 static const char * const cce_misc_names[] = { 5314 "CceErrInt", /* 0 */ 5315 "RxeErrInt", /* 1 */ 5316 "MiscErrInt", /* 2 */ 5317 "Reserved3", /* 3 */ 5318 "PioErrInt", /* 4 */ 5319 "SDmaErrInt", /* 5 */ 5320 "EgressErrInt", /* 6 */ 5321 "TxeErrInt" /* 7 */ 5322 }; 5323 5324 /* 5325 * Return the miscellaneous error interrupt name. 5326 */ 5327 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source) 5328 { 5329 if (source < ARRAY_SIZE(cce_misc_names)) 5330 strncpy(buf, cce_misc_names[source], bsize); 5331 else 5332 snprintf(buf, bsize, "Reserved%u", 5333 source + IS_GENERAL_ERR_START); 5334 5335 return buf; 5336 } 5337 5338 /* 5339 * Return the SDMA engine error interrupt name. 5340 */ 5341 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source) 5342 { 5343 snprintf(buf, bsize, "SDmaEngErrInt%u", source); 5344 return buf; 5345 } 5346 5347 /* 5348 * Return the send context error interrupt name. 5349 */ 5350 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source) 5351 { 5352 snprintf(buf, bsize, "SendCtxtErrInt%u", source); 5353 return buf; 5354 } 5355 5356 static const char * const various_names[] = { 5357 "PbcInt", 5358 "GpioAssertInt", 5359 "Qsfp1Int", 5360 "Qsfp2Int", 5361 "TCritInt" 5362 }; 5363 5364 /* 5365 * Return the various interrupt name. 5366 */ 5367 static char *is_various_name(char *buf, size_t bsize, unsigned int source) 5368 { 5369 if (source < ARRAY_SIZE(various_names)) 5370 strncpy(buf, various_names[source], bsize); 5371 else 5372 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START); 5373 return buf; 5374 } 5375 5376 /* 5377 * Return the DC interrupt name. 5378 */ 5379 static char *is_dc_name(char *buf, size_t bsize, unsigned int source) 5380 { 5381 static const char * const dc_int_names[] = { 5382 "common", 5383 "lcb", 5384 "8051", 5385 "lbm" /* local block merge */ 5386 }; 5387 5388 if (source < ARRAY_SIZE(dc_int_names)) 5389 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]); 5390 else 5391 snprintf(buf, bsize, "DCInt%u", source); 5392 return buf; 5393 } 5394 5395 static const char * const sdma_int_names[] = { 5396 "SDmaInt", 5397 "SdmaIdleInt", 5398 "SdmaProgressInt", 5399 }; 5400 5401 /* 5402 * Return the SDMA engine interrupt name. 5403 */ 5404 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source) 5405 { 5406 /* what interrupt */ 5407 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 5408 /* which engine */ 5409 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 5410 5411 if (likely(what < 3)) 5412 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which); 5413 else 5414 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source); 5415 return buf; 5416 } 5417 5418 /* 5419 * Return the receive available interrupt name. 5420 */ 5421 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source) 5422 { 5423 snprintf(buf, bsize, "RcvAvailInt%u", source); 5424 return buf; 5425 } 5426 5427 /* 5428 * Return the receive urgent interrupt name. 5429 */ 5430 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source) 5431 { 5432 snprintf(buf, bsize, "RcvUrgentInt%u", source); 5433 return buf; 5434 } 5435 5436 /* 5437 * Return the send credit interrupt name. 5438 */ 5439 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source) 5440 { 5441 snprintf(buf, bsize, "SendCreditInt%u", source); 5442 return buf; 5443 } 5444 5445 /* 5446 * Return the reserved interrupt name. 5447 */ 5448 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source) 5449 { 5450 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START); 5451 return buf; 5452 } 5453 5454 static char *cce_err_status_string(char *buf, int buf_len, u64 flags) 5455 { 5456 return flag_string(buf, buf_len, flags, 5457 cce_err_status_flags, 5458 ARRAY_SIZE(cce_err_status_flags)); 5459 } 5460 5461 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags) 5462 { 5463 return flag_string(buf, buf_len, flags, 5464 rxe_err_status_flags, 5465 ARRAY_SIZE(rxe_err_status_flags)); 5466 } 5467 5468 static char *misc_err_status_string(char *buf, int buf_len, u64 flags) 5469 { 5470 return flag_string(buf, buf_len, flags, misc_err_status_flags, 5471 ARRAY_SIZE(misc_err_status_flags)); 5472 } 5473 5474 static char *pio_err_status_string(char *buf, int buf_len, u64 flags) 5475 { 5476 return flag_string(buf, buf_len, flags, 5477 pio_err_status_flags, 5478 ARRAY_SIZE(pio_err_status_flags)); 5479 } 5480 5481 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags) 5482 { 5483 return flag_string(buf, buf_len, flags, 5484 sdma_err_status_flags, 5485 ARRAY_SIZE(sdma_err_status_flags)); 5486 } 5487 5488 static char *egress_err_status_string(char *buf, int buf_len, u64 flags) 5489 { 5490 return flag_string(buf, buf_len, flags, 5491 egress_err_status_flags, 5492 ARRAY_SIZE(egress_err_status_flags)); 5493 } 5494 5495 static char *egress_err_info_string(char *buf, int buf_len, u64 flags) 5496 { 5497 return flag_string(buf, buf_len, flags, 5498 egress_err_info_flags, 5499 ARRAY_SIZE(egress_err_info_flags)); 5500 } 5501 5502 static char *send_err_status_string(char *buf, int buf_len, u64 flags) 5503 { 5504 return flag_string(buf, buf_len, flags, 5505 send_err_status_flags, 5506 ARRAY_SIZE(send_err_status_flags)); 5507 } 5508 5509 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5510 { 5511 char buf[96]; 5512 int i = 0; 5513 5514 /* 5515 * For most these errors, there is nothing that can be done except 5516 * report or record it. 5517 */ 5518 dd_dev_info(dd, "CCE Error: %s\n", 5519 cce_err_status_string(buf, sizeof(buf), reg)); 5520 5521 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) && 5522 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) { 5523 /* this error requires a manual drop into SPC freeze mode */ 5524 /* then a fix up */ 5525 start_freeze_handling(dd->pport, FREEZE_SELF); 5526 } 5527 5528 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) { 5529 if (reg & (1ull << i)) { 5530 incr_cntr64(&dd->cce_err_status_cnt[i]); 5531 /* maintain a counter over all cce_err_status errors */ 5532 incr_cntr64(&dd->sw_cce_err_status_aggregate); 5533 } 5534 } 5535 } 5536 5537 /* 5538 * Check counters for receive errors that do not have an interrupt 5539 * associated with them. 5540 */ 5541 #define RCVERR_CHECK_TIME 10 5542 static void update_rcverr_timer(struct timer_list *t) 5543 { 5544 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer); 5545 struct hfi1_pportdata *ppd = dd->pport; 5546 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL); 5547 5548 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt && 5549 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) { 5550 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__); 5551 set_link_down_reason( 5552 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0, 5553 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN); 5554 queue_work(ppd->link_wq, &ppd->link_bounce_work); 5555 } 5556 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt; 5557 5558 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5559 } 5560 5561 static int init_rcverr(struct hfi1_devdata *dd) 5562 { 5563 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0); 5564 /* Assume the hardware counter has been reset */ 5565 dd->rcv_ovfl_cnt = 0; 5566 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5567 } 5568 5569 static void free_rcverr(struct hfi1_devdata *dd) 5570 { 5571 if (dd->rcverr_timer.function) 5572 del_timer_sync(&dd->rcverr_timer); 5573 } 5574 5575 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5576 { 5577 char buf[96]; 5578 int i = 0; 5579 5580 dd_dev_info(dd, "Receive Error: %s\n", 5581 rxe_err_status_string(buf, sizeof(buf), reg)); 5582 5583 if (reg & ALL_RXE_FREEZE_ERR) { 5584 int flags = 0; 5585 5586 /* 5587 * Freeze mode recovery is disabled for the errors 5588 * in RXE_FREEZE_ABORT_MASK 5589 */ 5590 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK)) 5591 flags = FREEZE_ABORT; 5592 5593 start_freeze_handling(dd->pport, flags); 5594 } 5595 5596 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) { 5597 if (reg & (1ull << i)) 5598 incr_cntr64(&dd->rcv_err_status_cnt[i]); 5599 } 5600 } 5601 5602 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5603 { 5604 char buf[96]; 5605 int i = 0; 5606 5607 dd_dev_info(dd, "Misc Error: %s", 5608 misc_err_status_string(buf, sizeof(buf), reg)); 5609 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) { 5610 if (reg & (1ull << i)) 5611 incr_cntr64(&dd->misc_err_status_cnt[i]); 5612 } 5613 } 5614 5615 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5616 { 5617 char buf[96]; 5618 int i = 0; 5619 5620 dd_dev_info(dd, "PIO Error: %s\n", 5621 pio_err_status_string(buf, sizeof(buf), reg)); 5622 5623 if (reg & ALL_PIO_FREEZE_ERR) 5624 start_freeze_handling(dd->pport, 0); 5625 5626 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) { 5627 if (reg & (1ull << i)) 5628 incr_cntr64(&dd->send_pio_err_status_cnt[i]); 5629 } 5630 } 5631 5632 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5633 { 5634 char buf[96]; 5635 int i = 0; 5636 5637 dd_dev_info(dd, "SDMA Error: %s\n", 5638 sdma_err_status_string(buf, sizeof(buf), reg)); 5639 5640 if (reg & ALL_SDMA_FREEZE_ERR) 5641 start_freeze_handling(dd->pport, 0); 5642 5643 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) { 5644 if (reg & (1ull << i)) 5645 incr_cntr64(&dd->send_dma_err_status_cnt[i]); 5646 } 5647 } 5648 5649 static inline void __count_port_discards(struct hfi1_pportdata *ppd) 5650 { 5651 incr_cntr64(&ppd->port_xmit_discards); 5652 } 5653 5654 static void count_port_inactive(struct hfi1_devdata *dd) 5655 { 5656 __count_port_discards(dd->pport); 5657 } 5658 5659 /* 5660 * We have had a "disallowed packet" error during egress. Determine the 5661 * integrity check which failed, and update relevant error counter, etc. 5662 * 5663 * Note that the SEND_EGRESS_ERR_INFO register has only a single 5664 * bit of state per integrity check, and so we can miss the reason for an 5665 * egress error if more than one packet fails the same integrity check 5666 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO. 5667 */ 5668 static void handle_send_egress_err_info(struct hfi1_devdata *dd, 5669 int vl) 5670 { 5671 struct hfi1_pportdata *ppd = dd->pport; 5672 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ 5673 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); 5674 char buf[96]; 5675 5676 /* clear down all observed info as quickly as possible after read */ 5677 write_csr(dd, SEND_EGRESS_ERR_INFO, info); 5678 5679 dd_dev_info(dd, 5680 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n", 5681 info, egress_err_info_string(buf, sizeof(buf), info), src); 5682 5683 /* Eventually add other counters for each bit */ 5684 if (info & PORT_DISCARD_EGRESS_ERRS) { 5685 int weight, i; 5686 5687 /* 5688 * Count all applicable bits as individual errors and 5689 * attribute them to the packet that triggered this handler. 5690 * This may not be completely accurate due to limitations 5691 * on the available hardware error information. There is 5692 * a single information register and any number of error 5693 * packets may have occurred and contributed to it before 5694 * this routine is called. This means that: 5695 * a) If multiple packets with the same error occur before 5696 * this routine is called, earlier packets are missed. 5697 * There is only a single bit for each error type. 5698 * b) Errors may not be attributed to the correct VL. 5699 * The driver is attributing all bits in the info register 5700 * to the packet that triggered this call, but bits 5701 * could be an accumulation of different packets with 5702 * different VLs. 5703 * c) A single error packet may have multiple counts attached 5704 * to it. There is no way for the driver to know if 5705 * multiple bits set in the info register are due to a 5706 * single packet or multiple packets. The driver assumes 5707 * multiple packets. 5708 */ 5709 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS); 5710 for (i = 0; i < weight; i++) { 5711 __count_port_discards(ppd); 5712 if (vl >= 0 && vl < TXE_NUM_DATA_VL) 5713 incr_cntr64(&ppd->port_xmit_discards_vl[vl]); 5714 else if (vl == 15) 5715 incr_cntr64(&ppd->port_xmit_discards_vl 5716 [C_VL_15]); 5717 } 5718 } 5719 } 5720 5721 /* 5722 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5723 * register. Does it represent a 'port inactive' error? 5724 */ 5725 static inline int port_inactive_err(u64 posn) 5726 { 5727 return (posn >= SEES(TX_LINKDOWN) && 5728 posn <= SEES(TX_INCORRECT_LINK_STATE)); 5729 } 5730 5731 /* 5732 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS 5733 * register. Does it represent a 'disallowed packet' error? 5734 */ 5735 static inline int disallowed_pkt_err(int posn) 5736 { 5737 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) && 5738 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET)); 5739 } 5740 5741 /* 5742 * Input value is a bit position of one of the SDMA engine disallowed 5743 * packet errors. Return which engine. Use of this must be guarded by 5744 * disallowed_pkt_err(). 5745 */ 5746 static inline int disallowed_pkt_engine(int posn) 5747 { 5748 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET); 5749 } 5750 5751 /* 5752 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot 5753 * be done. 5754 */ 5755 static int engine_to_vl(struct hfi1_devdata *dd, int engine) 5756 { 5757 struct sdma_vl_map *m; 5758 int vl; 5759 5760 /* range check */ 5761 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES) 5762 return -1; 5763 5764 rcu_read_lock(); 5765 m = rcu_dereference(dd->sdma_map); 5766 vl = m->engine_to_vl[engine]; 5767 rcu_read_unlock(); 5768 5769 return vl; 5770 } 5771 5772 /* 5773 * Translate the send context (sofware index) into a VL. Return -1 if the 5774 * translation cannot be done. 5775 */ 5776 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index) 5777 { 5778 struct send_context_info *sci; 5779 struct send_context *sc; 5780 int i; 5781 5782 sci = &dd->send_contexts[sw_index]; 5783 5784 /* there is no information for user (PSM) and ack contexts */ 5785 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15)) 5786 return -1; 5787 5788 sc = sci->sc; 5789 if (!sc) 5790 return -1; 5791 if (dd->vld[15].sc == sc) 5792 return 15; 5793 for (i = 0; i < num_vls; i++) 5794 if (dd->vld[i].sc == sc) 5795 return i; 5796 5797 return -1; 5798 } 5799 5800 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5801 { 5802 u64 reg_copy = reg, handled = 0; 5803 char buf[96]; 5804 int i = 0; 5805 5806 if (reg & ALL_TXE_EGRESS_FREEZE_ERR) 5807 start_freeze_handling(dd->pport, 0); 5808 else if (is_ax(dd) && 5809 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) && 5810 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) 5811 start_freeze_handling(dd->pport, 0); 5812 5813 while (reg_copy) { 5814 int posn = fls64(reg_copy); 5815 /* fls64() returns a 1-based offset, we want it zero based */ 5816 int shift = posn - 1; 5817 u64 mask = 1ULL << shift; 5818 5819 if (port_inactive_err(shift)) { 5820 count_port_inactive(dd); 5821 handled |= mask; 5822 } else if (disallowed_pkt_err(shift)) { 5823 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift)); 5824 5825 handle_send_egress_err_info(dd, vl); 5826 handled |= mask; 5827 } 5828 reg_copy &= ~mask; 5829 } 5830 5831 reg &= ~handled; 5832 5833 if (reg) 5834 dd_dev_info(dd, "Egress Error: %s\n", 5835 egress_err_status_string(buf, sizeof(buf), reg)); 5836 5837 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) { 5838 if (reg & (1ull << i)) 5839 incr_cntr64(&dd->send_egress_err_status_cnt[i]); 5840 } 5841 } 5842 5843 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5844 { 5845 char buf[96]; 5846 int i = 0; 5847 5848 dd_dev_info(dd, "Send Error: %s\n", 5849 send_err_status_string(buf, sizeof(buf), reg)); 5850 5851 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) { 5852 if (reg & (1ull << i)) 5853 incr_cntr64(&dd->send_err_status_cnt[i]); 5854 } 5855 } 5856 5857 /* 5858 * The maximum number of times the error clear down will loop before 5859 * blocking a repeating error. This value is arbitrary. 5860 */ 5861 #define MAX_CLEAR_COUNT 20 5862 5863 /* 5864 * Clear and handle an error register. All error interrupts are funneled 5865 * through here to have a central location to correctly handle single- 5866 * or multi-shot errors. 5867 * 5868 * For non per-context registers, call this routine with a context value 5869 * of 0 so the per-context offset is zero. 5870 * 5871 * If the handler loops too many times, assume that something is wrong 5872 * and can't be fixed, so mask the error bits. 5873 */ 5874 static void interrupt_clear_down(struct hfi1_devdata *dd, 5875 u32 context, 5876 const struct err_reg_info *eri) 5877 { 5878 u64 reg; 5879 u32 count; 5880 5881 /* read in a loop until no more errors are seen */ 5882 count = 0; 5883 while (1) { 5884 reg = read_kctxt_csr(dd, context, eri->status); 5885 if (reg == 0) 5886 break; 5887 write_kctxt_csr(dd, context, eri->clear, reg); 5888 if (likely(eri->handler)) 5889 eri->handler(dd, context, reg); 5890 count++; 5891 if (count > MAX_CLEAR_COUNT) { 5892 u64 mask; 5893 5894 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n", 5895 eri->desc, reg); 5896 /* 5897 * Read-modify-write so any other masked bits 5898 * remain masked. 5899 */ 5900 mask = read_kctxt_csr(dd, context, eri->mask); 5901 mask &= ~reg; 5902 write_kctxt_csr(dd, context, eri->mask, mask); 5903 break; 5904 } 5905 } 5906 } 5907 5908 /* 5909 * CCE block "misc" interrupt. Source is < 16. 5910 */ 5911 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source) 5912 { 5913 const struct err_reg_info *eri = &misc_errs[source]; 5914 5915 if (eri->handler) { 5916 interrupt_clear_down(dd, 0, eri); 5917 } else { 5918 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n", 5919 source); 5920 } 5921 } 5922 5923 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags) 5924 { 5925 return flag_string(buf, buf_len, flags, 5926 sc_err_status_flags, 5927 ARRAY_SIZE(sc_err_status_flags)); 5928 } 5929 5930 /* 5931 * Send context error interrupt. Source (hw_context) is < 160. 5932 * 5933 * All send context errors cause the send context to halt. The normal 5934 * clear-down mechanism cannot be used because we cannot clear the 5935 * error bits until several other long-running items are done first. 5936 * This is OK because with the context halted, nothing else is going 5937 * to happen on it anyway. 5938 */ 5939 static void is_sendctxt_err_int(struct hfi1_devdata *dd, 5940 unsigned int hw_context) 5941 { 5942 struct send_context_info *sci; 5943 struct send_context *sc; 5944 char flags[96]; 5945 u64 status; 5946 u32 sw_index; 5947 int i = 0; 5948 unsigned long irq_flags; 5949 5950 sw_index = dd->hw_to_sw[hw_context]; 5951 if (sw_index >= dd->num_send_contexts) { 5952 dd_dev_err(dd, 5953 "out of range sw index %u for send context %u\n", 5954 sw_index, hw_context); 5955 return; 5956 } 5957 sci = &dd->send_contexts[sw_index]; 5958 spin_lock_irqsave(&dd->sc_lock, irq_flags); 5959 sc = sci->sc; 5960 if (!sc) { 5961 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__, 5962 sw_index, hw_context); 5963 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 5964 return; 5965 } 5966 5967 /* tell the software that a halt has begun */ 5968 sc_stop(sc, SCF_HALTED); 5969 5970 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS); 5971 5972 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context, 5973 send_context_err_status_string(flags, sizeof(flags), 5974 status)); 5975 5976 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK) 5977 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index)); 5978 5979 /* 5980 * Automatically restart halted kernel contexts out of interrupt 5981 * context. User contexts must ask the driver to restart the context. 5982 */ 5983 if (sc->type != SC_USER) 5984 queue_work(dd->pport->hfi1_wq, &sc->halt_work); 5985 spin_unlock_irqrestore(&dd->sc_lock, irq_flags); 5986 5987 /* 5988 * Update the counters for the corresponding status bits. 5989 * Note that these particular counters are aggregated over all 5990 * 160 contexts. 5991 */ 5992 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) { 5993 if (status & (1ull << i)) 5994 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]); 5995 } 5996 } 5997 5998 static void handle_sdma_eng_err(struct hfi1_devdata *dd, 5999 unsigned int source, u64 status) 6000 { 6001 struct sdma_engine *sde; 6002 int i = 0; 6003 6004 sde = &dd->per_sdma[source]; 6005 #ifdef CONFIG_SDMA_VERBOSITY 6006 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6007 slashstrip(__FILE__), __LINE__, __func__); 6008 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n", 6009 sde->this_idx, source, (unsigned long long)status); 6010 #endif 6011 sde->err_cnt++; 6012 sdma_engine_error(sde, status); 6013 6014 /* 6015 * Update the counters for the corresponding status bits. 6016 * Note that these particular counters are aggregated over 6017 * all 16 DMA engines. 6018 */ 6019 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) { 6020 if (status & (1ull << i)) 6021 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]); 6022 } 6023 } 6024 6025 /* 6026 * CCE block SDMA error interrupt. Source is < 16. 6027 */ 6028 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source) 6029 { 6030 #ifdef CONFIG_SDMA_VERBOSITY 6031 struct sdma_engine *sde = &dd->per_sdma[source]; 6032 6033 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 6034 slashstrip(__FILE__), __LINE__, __func__); 6035 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx, 6036 source); 6037 sdma_dumpstate(sde); 6038 #endif 6039 interrupt_clear_down(dd, source, &sdma_eng_err); 6040 } 6041 6042 /* 6043 * CCE block "various" interrupt. Source is < 8. 6044 */ 6045 static void is_various_int(struct hfi1_devdata *dd, unsigned int source) 6046 { 6047 const struct err_reg_info *eri = &various_err[source]; 6048 6049 /* 6050 * TCritInt cannot go through interrupt_clear_down() 6051 * because it is not a second tier interrupt. The handler 6052 * should be called directly. 6053 */ 6054 if (source == TCRIT_INT_SOURCE) 6055 handle_temp_err(dd); 6056 else if (eri->handler) 6057 interrupt_clear_down(dd, 0, eri); 6058 else 6059 dd_dev_info(dd, 6060 "%s: Unimplemented/reserved interrupt %d\n", 6061 __func__, source); 6062 } 6063 6064 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg) 6065 { 6066 /* src_ctx is always zero */ 6067 struct hfi1_pportdata *ppd = dd->pport; 6068 unsigned long flags; 6069 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 6070 6071 if (reg & QSFP_HFI0_MODPRST_N) { 6072 if (!qsfp_mod_present(ppd)) { 6073 dd_dev_info(dd, "%s: QSFP module removed\n", 6074 __func__); 6075 6076 ppd->driver_link_ready = 0; 6077 /* 6078 * Cable removed, reset all our information about the 6079 * cache and cable capabilities 6080 */ 6081 6082 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6083 /* 6084 * We don't set cache_refresh_required here as we expect 6085 * an interrupt when a cable is inserted 6086 */ 6087 ppd->qsfp_info.cache_valid = 0; 6088 ppd->qsfp_info.reset_needed = 0; 6089 ppd->qsfp_info.limiting_active = 0; 6090 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6091 flags); 6092 /* Invert the ModPresent pin now to detect plug-in */ 6093 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6094 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6095 6096 if ((ppd->offline_disabled_reason > 6097 HFI1_ODR_MASK( 6098 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) || 6099 (ppd->offline_disabled_reason == 6100 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))) 6101 ppd->offline_disabled_reason = 6102 HFI1_ODR_MASK( 6103 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED); 6104 6105 if (ppd->host_link_state == HLS_DN_POLL) { 6106 /* 6107 * The link is still in POLL. This means 6108 * that the normal link down processing 6109 * will not happen. We have to do it here 6110 * before turning the DC off. 6111 */ 6112 queue_work(ppd->link_wq, &ppd->link_down_work); 6113 } 6114 } else { 6115 dd_dev_info(dd, "%s: QSFP module inserted\n", 6116 __func__); 6117 6118 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6119 ppd->qsfp_info.cache_valid = 0; 6120 ppd->qsfp_info.cache_refresh_required = 1; 6121 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 6122 flags); 6123 6124 /* 6125 * Stop inversion of ModPresent pin to detect 6126 * removal of the cable 6127 */ 6128 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N; 6129 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : 6130 ASIC_QSFP1_INVERT, qsfp_int_mgmt); 6131 6132 ppd->offline_disabled_reason = 6133 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 6134 } 6135 } 6136 6137 if (reg & QSFP_HFI0_INT_N) { 6138 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n", 6139 __func__); 6140 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 6141 ppd->qsfp_info.check_interrupt_flags = 1; 6142 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags); 6143 } 6144 6145 /* Schedule the QSFP work only if there is a cable attached. */ 6146 if (qsfp_mod_present(ppd)) 6147 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work); 6148 } 6149 6150 static int request_host_lcb_access(struct hfi1_devdata *dd) 6151 { 6152 int ret; 6153 6154 ret = do_8051_command(dd, HCMD_MISC, 6155 (u64)HCMD_MISC_REQUEST_LCB_ACCESS << 6156 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6157 if (ret != HCMD_SUCCESS) { 6158 dd_dev_err(dd, "%s: command failed with error %d\n", 6159 __func__, ret); 6160 } 6161 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6162 } 6163 6164 static int request_8051_lcb_access(struct hfi1_devdata *dd) 6165 { 6166 int ret; 6167 6168 ret = do_8051_command(dd, HCMD_MISC, 6169 (u64)HCMD_MISC_GRANT_LCB_ACCESS << 6170 LOAD_DATA_FIELD_ID_SHIFT, NULL); 6171 if (ret != HCMD_SUCCESS) { 6172 dd_dev_err(dd, "%s: command failed with error %d\n", 6173 __func__, ret); 6174 } 6175 return ret == HCMD_SUCCESS ? 0 : -EBUSY; 6176 } 6177 6178 /* 6179 * Set the LCB selector - allow host access. The DCC selector always 6180 * points to the host. 6181 */ 6182 static inline void set_host_lcb_access(struct hfi1_devdata *dd) 6183 { 6184 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6185 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK | 6186 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK); 6187 } 6188 6189 /* 6190 * Clear the LCB selector - allow 8051 access. The DCC selector always 6191 * points to the host. 6192 */ 6193 static inline void set_8051_lcb_access(struct hfi1_devdata *dd) 6194 { 6195 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, 6196 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK); 6197 } 6198 6199 /* 6200 * Acquire LCB access from the 8051. If the host already has access, 6201 * just increment a counter. Otherwise, inform the 8051 that the 6202 * host is taking access. 6203 * 6204 * Returns: 6205 * 0 on success 6206 * -EBUSY if the 8051 has control and cannot be disturbed 6207 * -errno if unable to acquire access from the 8051 6208 */ 6209 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6210 { 6211 struct hfi1_pportdata *ppd = dd->pport; 6212 int ret = 0; 6213 6214 /* 6215 * Use the host link state lock so the operation of this routine 6216 * { link state check, selector change, count increment } can occur 6217 * as a unit against a link state change. Otherwise there is a 6218 * race between the state change and the count increment. 6219 */ 6220 if (sleep_ok) { 6221 mutex_lock(&ppd->hls_lock); 6222 } else { 6223 while (!mutex_trylock(&ppd->hls_lock)) 6224 udelay(1); 6225 } 6226 6227 /* this access is valid only when the link is up */ 6228 if (ppd->host_link_state & HLS_DOWN) { 6229 dd_dev_info(dd, "%s: link state %s not up\n", 6230 __func__, link_state_name(ppd->host_link_state)); 6231 ret = -EBUSY; 6232 goto done; 6233 } 6234 6235 if (dd->lcb_access_count == 0) { 6236 ret = request_host_lcb_access(dd); 6237 if (ret) { 6238 dd_dev_err(dd, 6239 "%s: unable to acquire LCB access, err %d\n", 6240 __func__, ret); 6241 goto done; 6242 } 6243 set_host_lcb_access(dd); 6244 } 6245 dd->lcb_access_count++; 6246 done: 6247 mutex_unlock(&ppd->hls_lock); 6248 return ret; 6249 } 6250 6251 /* 6252 * Release LCB access by decrementing the use count. If the count is moving 6253 * from 1 to 0, inform 8051 that it has control back. 6254 * 6255 * Returns: 6256 * 0 on success 6257 * -errno if unable to release access to the 8051 6258 */ 6259 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok) 6260 { 6261 int ret = 0; 6262 6263 /* 6264 * Use the host link state lock because the acquire needed it. 6265 * Here, we only need to keep { selector change, count decrement } 6266 * as a unit. 6267 */ 6268 if (sleep_ok) { 6269 mutex_lock(&dd->pport->hls_lock); 6270 } else { 6271 while (!mutex_trylock(&dd->pport->hls_lock)) 6272 udelay(1); 6273 } 6274 6275 if (dd->lcb_access_count == 0) { 6276 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n", 6277 __func__); 6278 goto done; 6279 } 6280 6281 if (dd->lcb_access_count == 1) { 6282 set_8051_lcb_access(dd); 6283 ret = request_8051_lcb_access(dd); 6284 if (ret) { 6285 dd_dev_err(dd, 6286 "%s: unable to release LCB access, err %d\n", 6287 __func__, ret); 6288 /* restore host access if the grant didn't work */ 6289 set_host_lcb_access(dd); 6290 goto done; 6291 } 6292 } 6293 dd->lcb_access_count--; 6294 done: 6295 mutex_unlock(&dd->pport->hls_lock); 6296 return ret; 6297 } 6298 6299 /* 6300 * Initialize LCB access variables and state. Called during driver load, 6301 * after most of the initialization is finished. 6302 * 6303 * The DC default is LCB access on for the host. The driver defaults to 6304 * leaving access to the 8051. Assign access now - this constrains the call 6305 * to this routine to be after all LCB set-up is done. In particular, after 6306 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts() 6307 */ 6308 static void init_lcb_access(struct hfi1_devdata *dd) 6309 { 6310 dd->lcb_access_count = 0; 6311 } 6312 6313 /* 6314 * Write a response back to a 8051 request. 6315 */ 6316 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data) 6317 { 6318 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 6319 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK | 6320 (u64)return_code << 6321 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT | 6322 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 6323 } 6324 6325 /* 6326 * Handle host requests from the 8051. 6327 */ 6328 static void handle_8051_request(struct hfi1_pportdata *ppd) 6329 { 6330 struct hfi1_devdata *dd = ppd->dd; 6331 u64 reg; 6332 u16 data = 0; 6333 u8 type; 6334 6335 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); 6336 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0) 6337 return; /* no request */ 6338 6339 /* zero out COMPLETED so the response is seen */ 6340 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); 6341 6342 /* extract request details */ 6343 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT) 6344 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK; 6345 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT) 6346 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK; 6347 6348 switch (type) { 6349 case HREQ_LOAD_CONFIG: 6350 case HREQ_SAVE_CONFIG: 6351 case HREQ_READ_CONFIG: 6352 case HREQ_SET_TX_EQ_ABS: 6353 case HREQ_SET_TX_EQ_REL: 6354 case HREQ_ENABLE: 6355 dd_dev_info(dd, "8051 request: request 0x%x not supported\n", 6356 type); 6357 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6358 break; 6359 case HREQ_LCB_RESET: 6360 /* Put the LCB, RX FPE and TX FPE into reset */ 6361 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); 6362 /* Make sure the write completed */ 6363 (void)read_csr(dd, DCC_CFG_RESET); 6364 /* Hold the reset long enough to take effect */ 6365 udelay(1); 6366 /* Take the LCB, RX FPE and TX FPE out of reset */ 6367 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6368 hreq_response(dd, HREQ_SUCCESS, 0); 6369 6370 break; 6371 case HREQ_CONFIG_DONE: 6372 hreq_response(dd, HREQ_SUCCESS, 0); 6373 break; 6374 6375 case HREQ_INTERFACE_TEST: 6376 hreq_response(dd, HREQ_SUCCESS, data); 6377 break; 6378 default: 6379 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type); 6380 hreq_response(dd, HREQ_NOT_SUPPORTED, 0); 6381 break; 6382 } 6383 } 6384 6385 /* 6386 * Set up allocation unit vaulue. 6387 */ 6388 void set_up_vau(struct hfi1_devdata *dd, u8 vau) 6389 { 6390 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6391 6392 /* do not modify other values in the register */ 6393 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK; 6394 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT; 6395 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6396 } 6397 6398 /* 6399 * Set up initial VL15 credits of the remote. Assumes the rest of 6400 * the CM credit registers are zero from a previous global or credit reset. 6401 * Shared limit for VL15 will always be 0. 6402 */ 6403 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf) 6404 { 6405 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 6406 6407 /* set initial values for total and shared credit limit */ 6408 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK | 6409 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK); 6410 6411 /* 6412 * Set total limit to be equal to VL15 credits. 6413 * Leave shared limit at 0. 6414 */ 6415 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 6416 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 6417 6418 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf 6419 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); 6420 } 6421 6422 /* 6423 * Zero all credit details from the previous connection and 6424 * reset the CM manager's internal counters. 6425 */ 6426 void reset_link_credits(struct hfi1_devdata *dd) 6427 { 6428 int i; 6429 6430 /* remove all previous VL credit limits */ 6431 for (i = 0; i < TXE_NUM_DATA_VL; i++) 6432 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 6433 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 6434 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); 6435 /* reset the CM block */ 6436 pio_send_control(dd, PSC_CM_RESET); 6437 /* reset cached value */ 6438 dd->vl15buf_cached = 0; 6439 } 6440 6441 /* convert a vCU to a CU */ 6442 static u32 vcu_to_cu(u8 vcu) 6443 { 6444 return 1 << vcu; 6445 } 6446 6447 /* convert a CU to a vCU */ 6448 static u8 cu_to_vcu(u32 cu) 6449 { 6450 return ilog2(cu); 6451 } 6452 6453 /* convert a vAU to an AU */ 6454 static u32 vau_to_au(u8 vau) 6455 { 6456 return 8 * (1 << vau); 6457 } 6458 6459 static void set_linkup_defaults(struct hfi1_pportdata *ppd) 6460 { 6461 ppd->sm_trap_qp = 0x0; 6462 ppd->sa_qp = 0x1; 6463 } 6464 6465 /* 6466 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset. 6467 */ 6468 static void lcb_shutdown(struct hfi1_devdata *dd, int abort) 6469 { 6470 u64 reg; 6471 6472 /* clear lcb run: LCB_CFG_RUN.EN = 0 */ 6473 write_csr(dd, DC_LCB_CFG_RUN, 0); 6474 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */ 6475 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 6476 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT); 6477 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */ 6478 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); 6479 reg = read_csr(dd, DCC_CFG_RESET); 6480 write_csr(dd, DCC_CFG_RESET, reg | 6481 DCC_CFG_RESET_RESET_LCB | DCC_CFG_RESET_RESET_RX_FPE); 6482 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ 6483 if (!abort) { 6484 udelay(1); /* must hold for the longer of 16cclks or 20ns */ 6485 write_csr(dd, DCC_CFG_RESET, reg); 6486 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6487 } 6488 } 6489 6490 /* 6491 * This routine should be called after the link has been transitioned to 6492 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into 6493 * reset). 6494 * 6495 * The expectation is that the caller of this routine would have taken 6496 * care of properly transitioning the link into the correct state. 6497 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6498 * before calling this function. 6499 */ 6500 static void _dc_shutdown(struct hfi1_devdata *dd) 6501 { 6502 lockdep_assert_held(&dd->dc8051_lock); 6503 6504 if (dd->dc_shutdown) 6505 return; 6506 6507 dd->dc_shutdown = 1; 6508 /* Shutdown the LCB */ 6509 lcb_shutdown(dd, 1); 6510 /* 6511 * Going to OFFLINE would have causes the 8051 to put the 6512 * SerDes into reset already. Just need to shut down the 8051, 6513 * itself. 6514 */ 6515 write_csr(dd, DC_DC8051_CFG_RST, 0x1); 6516 } 6517 6518 static void dc_shutdown(struct hfi1_devdata *dd) 6519 { 6520 mutex_lock(&dd->dc8051_lock); 6521 _dc_shutdown(dd); 6522 mutex_unlock(&dd->dc8051_lock); 6523 } 6524 6525 /* 6526 * Calling this after the DC has been brought out of reset should not 6527 * do any damage. 6528 * NOTE: the caller needs to acquire the dd->dc8051_lock lock 6529 * before calling this function. 6530 */ 6531 static void _dc_start(struct hfi1_devdata *dd) 6532 { 6533 lockdep_assert_held(&dd->dc8051_lock); 6534 6535 if (!dd->dc_shutdown) 6536 return; 6537 6538 /* Take the 8051 out of reset */ 6539 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 6540 /* Wait until 8051 is ready */ 6541 if (wait_fm_ready(dd, TIMEOUT_8051_START)) 6542 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n", 6543 __func__); 6544 6545 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */ 6546 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); 6547 /* lcb_shutdown() with abort=1 does not restore these */ 6548 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); 6549 dd->dc_shutdown = 0; 6550 } 6551 6552 static void dc_start(struct hfi1_devdata *dd) 6553 { 6554 mutex_lock(&dd->dc8051_lock); 6555 _dc_start(dd); 6556 mutex_unlock(&dd->dc8051_lock); 6557 } 6558 6559 /* 6560 * These LCB adjustments are for the Aurora SerDes core in the FPGA. 6561 */ 6562 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd) 6563 { 6564 u64 rx_radr, tx_radr; 6565 u32 version; 6566 6567 if (dd->icode != ICODE_FPGA_EMULATION) 6568 return; 6569 6570 /* 6571 * These LCB defaults on emulator _s are good, nothing to do here: 6572 * LCB_CFG_TX_FIFOS_RADR 6573 * LCB_CFG_RX_FIFOS_RADR 6574 * LCB_CFG_LN_DCLK 6575 * LCB_CFG_IGNORE_LOST_RCLK 6576 */ 6577 if (is_emulator_s(dd)) 6578 return; 6579 /* else this is _p */ 6580 6581 version = emulator_rev(dd); 6582 if (!is_ax(dd)) 6583 version = 0x2d; /* all B0 use 0x2d or higher settings */ 6584 6585 if (version <= 0x12) { 6586 /* release 0x12 and below */ 6587 6588 /* 6589 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9 6590 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9 6591 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa 6592 */ 6593 rx_radr = 6594 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6595 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6596 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6597 /* 6598 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default) 6599 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6 6600 */ 6601 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6602 } else if (version <= 0x18) { 6603 /* release 0x13 up to 0x18 */ 6604 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6605 rx_radr = 6606 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6607 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6608 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6609 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6610 } else if (version == 0x19) { 6611 /* release 0x19 */ 6612 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */ 6613 rx_radr = 6614 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6615 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6616 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6617 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6618 } else if (version == 0x1a) { 6619 /* release 0x1a */ 6620 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */ 6621 rx_radr = 6622 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6623 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6624 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6625 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6626 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); 6627 } else { 6628 /* release 0x1b and higher */ 6629 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */ 6630 rx_radr = 6631 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 6632 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 6633 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT; 6634 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT; 6635 } 6636 6637 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); 6638 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */ 6639 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 6640 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 6641 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); 6642 } 6643 6644 /* 6645 * Handle a SMA idle message 6646 * 6647 * This is a work-queue function outside of the interrupt. 6648 */ 6649 void handle_sma_message(struct work_struct *work) 6650 { 6651 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6652 sma_message_work); 6653 struct hfi1_devdata *dd = ppd->dd; 6654 u64 msg; 6655 int ret; 6656 6657 /* 6658 * msg is bytes 1-4 of the 40-bit idle message - the command code 6659 * is stripped off 6660 */ 6661 ret = read_idle_sma(dd, &msg); 6662 if (ret) 6663 return; 6664 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg); 6665 /* 6666 * React to the SMA message. Byte[1] (0 for us) is the command. 6667 */ 6668 switch (msg & 0xff) { 6669 case SMA_IDLE_ARM: 6670 /* 6671 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6672 * State Transitions 6673 * 6674 * Only expected in INIT or ARMED, discard otherwise. 6675 */ 6676 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED)) 6677 ppd->neighbor_normal = 1; 6678 break; 6679 case SMA_IDLE_ACTIVE: 6680 /* 6681 * See OPAv1 table 9-14 - HFI and External Switch Ports Key 6682 * State Transitions 6683 * 6684 * Can activate the node. Discard otherwise. 6685 */ 6686 if (ppd->host_link_state == HLS_UP_ARMED && 6687 ppd->is_active_optimize_enabled) { 6688 ppd->neighbor_normal = 1; 6689 ret = set_link_state(ppd, HLS_UP_ACTIVE); 6690 if (ret) 6691 dd_dev_err( 6692 dd, 6693 "%s: received Active SMA idle message, couldn't set link to Active\n", 6694 __func__); 6695 } 6696 break; 6697 default: 6698 dd_dev_err(dd, 6699 "%s: received unexpected SMA idle message 0x%llx\n", 6700 __func__, msg); 6701 break; 6702 } 6703 } 6704 6705 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear) 6706 { 6707 u64 rcvctrl; 6708 unsigned long flags; 6709 6710 spin_lock_irqsave(&dd->rcvctrl_lock, flags); 6711 rcvctrl = read_csr(dd, RCV_CTRL); 6712 rcvctrl |= add; 6713 rcvctrl &= ~clear; 6714 write_csr(dd, RCV_CTRL, rcvctrl); 6715 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags); 6716 } 6717 6718 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add) 6719 { 6720 adjust_rcvctrl(dd, add, 0); 6721 } 6722 6723 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear) 6724 { 6725 adjust_rcvctrl(dd, 0, clear); 6726 } 6727 6728 /* 6729 * Called from all interrupt handlers to start handling an SPC freeze. 6730 */ 6731 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags) 6732 { 6733 struct hfi1_devdata *dd = ppd->dd; 6734 struct send_context *sc; 6735 int i; 6736 int sc_flags; 6737 6738 if (flags & FREEZE_SELF) 6739 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6740 6741 /* enter frozen mode */ 6742 dd->flags |= HFI1_FROZEN; 6743 6744 /* notify all SDMA engines that they are going into a freeze */ 6745 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN)); 6746 6747 sc_flags = SCF_FROZEN | SCF_HALTED | (flags & FREEZE_LINK_DOWN ? 6748 SCF_LINK_DOWN : 0); 6749 /* do halt pre-handling on all enabled send contexts */ 6750 for (i = 0; i < dd->num_send_contexts; i++) { 6751 sc = dd->send_contexts[i].sc; 6752 if (sc && (sc->flags & SCF_ENABLED)) 6753 sc_stop(sc, sc_flags); 6754 } 6755 6756 /* Send context are frozen. Notify user space */ 6757 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT); 6758 6759 if (flags & FREEZE_ABORT) { 6760 dd_dev_err(dd, 6761 "Aborted freeze recovery. Please REBOOT system\n"); 6762 return; 6763 } 6764 /* queue non-interrupt handler */ 6765 queue_work(ppd->hfi1_wq, &ppd->freeze_work); 6766 } 6767 6768 /* 6769 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen, 6770 * depending on the "freeze" parameter. 6771 * 6772 * No need to return an error if it times out, our only option 6773 * is to proceed anyway. 6774 */ 6775 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze) 6776 { 6777 unsigned long timeout; 6778 u64 reg; 6779 6780 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT); 6781 while (1) { 6782 reg = read_csr(dd, CCE_STATUS); 6783 if (freeze) { 6784 /* waiting until all indicators are set */ 6785 if ((reg & ALL_FROZE) == ALL_FROZE) 6786 return; /* all done */ 6787 } else { 6788 /* waiting until all indicators are clear */ 6789 if ((reg & ALL_FROZE) == 0) 6790 return; /* all done */ 6791 } 6792 6793 if (time_after(jiffies, timeout)) { 6794 dd_dev_err(dd, 6795 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing", 6796 freeze ? "" : "un", reg & ALL_FROZE, 6797 freeze ? ALL_FROZE : 0ull); 6798 return; 6799 } 6800 usleep_range(80, 120); 6801 } 6802 } 6803 6804 /* 6805 * Do all freeze handling for the RXE block. 6806 */ 6807 static void rxe_freeze(struct hfi1_devdata *dd) 6808 { 6809 int i; 6810 struct hfi1_ctxtdata *rcd; 6811 6812 /* disable port */ 6813 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6814 6815 /* disable all receive contexts */ 6816 for (i = 0; i < dd->num_rcv_contexts; i++) { 6817 rcd = hfi1_rcd_get_by_index(dd, i); 6818 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd); 6819 hfi1_rcd_put(rcd); 6820 } 6821 } 6822 6823 /* 6824 * Unfreeze handling for the RXE block - kernel contexts only. 6825 * This will also enable the port. User contexts will do unfreeze 6826 * handling on a per-context basis as they call into the driver. 6827 * 6828 */ 6829 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd) 6830 { 6831 u32 rcvmask; 6832 u16 i; 6833 struct hfi1_ctxtdata *rcd; 6834 6835 /* enable all kernel contexts */ 6836 for (i = 0; i < dd->num_rcv_contexts; i++) { 6837 rcd = hfi1_rcd_get_by_index(dd, i); 6838 6839 /* Ensure all non-user contexts(including vnic) are enabled */ 6840 if (!rcd || 6841 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) { 6842 hfi1_rcd_put(rcd); 6843 continue; 6844 } 6845 rcvmask = HFI1_RCVCTRL_CTXT_ENB; 6846 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */ 6847 rcvmask |= rcd->rcvhdrtail_kvaddr ? 6848 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; 6849 hfi1_rcvctrl(dd, rcvmask, rcd); 6850 hfi1_rcd_put(rcd); 6851 } 6852 6853 /* enable port */ 6854 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 6855 } 6856 6857 /* 6858 * Non-interrupt SPC freeze handling. 6859 * 6860 * This is a work-queue function outside of the triggering interrupt. 6861 */ 6862 void handle_freeze(struct work_struct *work) 6863 { 6864 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6865 freeze_work); 6866 struct hfi1_devdata *dd = ppd->dd; 6867 6868 /* wait for freeze indicators on all affected blocks */ 6869 wait_for_freeze_status(dd, 1); 6870 6871 /* SPC is now frozen */ 6872 6873 /* do send PIO freeze steps */ 6874 pio_freeze(dd); 6875 6876 /* do send DMA freeze steps */ 6877 sdma_freeze(dd); 6878 6879 /* do send egress freeze steps - nothing to do */ 6880 6881 /* do receive freeze steps */ 6882 rxe_freeze(dd); 6883 6884 /* 6885 * Unfreeze the hardware - clear the freeze, wait for each 6886 * block's frozen bit to clear, then clear the frozen flag. 6887 */ 6888 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6889 wait_for_freeze_status(dd, 0); 6890 6891 if (is_ax(dd)) { 6892 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); 6893 wait_for_freeze_status(dd, 1); 6894 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); 6895 wait_for_freeze_status(dd, 0); 6896 } 6897 6898 /* do send PIO unfreeze steps for kernel contexts */ 6899 pio_kernel_unfreeze(dd); 6900 6901 /* do send DMA unfreeze steps */ 6902 sdma_unfreeze(dd); 6903 6904 /* do send egress unfreeze steps - nothing to do */ 6905 6906 /* do receive unfreeze steps for kernel contexts */ 6907 rxe_kernel_unfreeze(dd); 6908 6909 /* 6910 * The unfreeze procedure touches global device registers when 6911 * it disables and re-enables RXE. Mark the device unfrozen 6912 * after all that is done so other parts of the driver waiting 6913 * for the device to unfreeze don't do things out of order. 6914 * 6915 * The above implies that the meaning of HFI1_FROZEN flag is 6916 * "Device has gone into freeze mode and freeze mode handling 6917 * is still in progress." 6918 * 6919 * The flag will be removed when freeze mode processing has 6920 * completed. 6921 */ 6922 dd->flags &= ~HFI1_FROZEN; 6923 wake_up(&dd->event_queue); 6924 6925 /* no longer frozen */ 6926 } 6927 6928 /** 6929 * update_xmit_counters - update PortXmitWait/PortVlXmitWait 6930 * counters. 6931 * @ppd: info of physical Hfi port 6932 * @link_width: new link width after link up or downgrade 6933 * 6934 * Update the PortXmitWait and PortVlXmitWait counters after 6935 * a link up or downgrade event to reflect a link width change. 6936 */ 6937 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width) 6938 { 6939 int i; 6940 u16 tx_width; 6941 u16 link_speed; 6942 6943 tx_width = tx_link_width(link_width); 6944 link_speed = get_link_speed(ppd->link_speed_active); 6945 6946 /* 6947 * There are C_VL_COUNT number of PortVLXmitWait counters. 6948 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter. 6949 */ 6950 for (i = 0; i < C_VL_COUNT + 1; i++) 6951 get_xmit_wait_counters(ppd, tx_width, link_speed, i); 6952 } 6953 6954 /* 6955 * Handle a link up interrupt from the 8051. 6956 * 6957 * This is a work-queue function outside of the interrupt. 6958 */ 6959 void handle_link_up(struct work_struct *work) 6960 { 6961 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 6962 link_up_work); 6963 struct hfi1_devdata *dd = ppd->dd; 6964 6965 set_link_state(ppd, HLS_UP_INIT); 6966 6967 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */ 6968 read_ltp_rtt(dd); 6969 /* 6970 * OPA specifies that certain counters are cleared on a transition 6971 * to link up, so do that. 6972 */ 6973 clear_linkup_counters(dd); 6974 /* 6975 * And (re)set link up default values. 6976 */ 6977 set_linkup_defaults(ppd); 6978 6979 /* 6980 * Set VL15 credits. Use cached value from verify cap interrupt. 6981 * In case of quick linkup or simulator, vl15 value will be set by 6982 * handle_linkup_change. VerifyCap interrupt handler will not be 6983 * called in those scenarios. 6984 */ 6985 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) 6986 set_up_vl15(dd, dd->vl15buf_cached); 6987 6988 /* enforce link speed enabled */ 6989 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) { 6990 /* oops - current speed is not enabled, bounce */ 6991 dd_dev_err(dd, 6992 "Link speed active 0x%x is outside enabled 0x%x, downing link\n", 6993 ppd->link_speed_active, ppd->link_speed_enabled); 6994 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0, 6995 OPA_LINKDOWN_REASON_SPEED_POLICY); 6996 set_link_state(ppd, HLS_DN_OFFLINE); 6997 start_link(ppd); 6998 } 6999 } 7000 7001 /* 7002 * Several pieces of LNI information were cached for SMA in ppd. 7003 * Reset these on link down 7004 */ 7005 static void reset_neighbor_info(struct hfi1_pportdata *ppd) 7006 { 7007 ppd->neighbor_guid = 0; 7008 ppd->neighbor_port_number = 0; 7009 ppd->neighbor_type = 0; 7010 ppd->neighbor_fm_security = 0; 7011 } 7012 7013 static const char * const link_down_reason_strs[] = { 7014 [OPA_LINKDOWN_REASON_NONE] = "None", 7015 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0", 7016 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length", 7017 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long", 7018 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short", 7019 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID", 7020 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID", 7021 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2", 7022 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC", 7023 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8", 7024 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail", 7025 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10", 7026 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error", 7027 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15", 7028 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker", 7029 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14", 7030 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15", 7031 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance", 7032 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance", 7033 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance", 7034 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack", 7035 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker", 7036 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt", 7037 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit", 7038 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit", 7039 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24", 7040 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25", 7041 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26", 7042 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27", 7043 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28", 7044 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29", 7045 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30", 7046 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] = 7047 "Excessive buffer overrun", 7048 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown", 7049 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot", 7050 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown", 7051 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce", 7052 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy", 7053 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy", 7054 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected", 7055 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] = 7056 "Local media not installed", 7057 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed", 7058 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config", 7059 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] = 7060 "End to end not installed", 7061 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy", 7062 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy", 7063 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy", 7064 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management", 7065 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled", 7066 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient" 7067 }; 7068 7069 /* return the neighbor link down reason string */ 7070 static const char *link_down_reason_str(u8 reason) 7071 { 7072 const char *str = NULL; 7073 7074 if (reason < ARRAY_SIZE(link_down_reason_strs)) 7075 str = link_down_reason_strs[reason]; 7076 if (!str) 7077 str = "(invalid)"; 7078 7079 return str; 7080 } 7081 7082 /* 7083 * Handle a link down interrupt from the 8051. 7084 * 7085 * This is a work-queue function outside of the interrupt. 7086 */ 7087 void handle_link_down(struct work_struct *work) 7088 { 7089 u8 lcl_reason, neigh_reason = 0; 7090 u8 link_down_reason; 7091 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7092 link_down_work); 7093 int was_up; 7094 static const char ldr_str[] = "Link down reason: "; 7095 7096 if ((ppd->host_link_state & 7097 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) && 7098 ppd->port_type == PORT_TYPE_FIXED) 7099 ppd->offline_disabled_reason = 7100 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED); 7101 7102 /* Go offline first, then deal with reading/writing through 8051 */ 7103 was_up = !!(ppd->host_link_state & HLS_UP); 7104 set_link_state(ppd, HLS_DN_OFFLINE); 7105 xchg(&ppd->is_link_down_queued, 0); 7106 7107 if (was_up) { 7108 lcl_reason = 0; 7109 /* link down reason is only valid if the link was up */ 7110 read_link_down_reason(ppd->dd, &link_down_reason); 7111 switch (link_down_reason) { 7112 case LDR_LINK_TRANSFER_ACTIVE_LOW: 7113 /* the link went down, no idle message reason */ 7114 dd_dev_info(ppd->dd, "%sUnexpected link down\n", 7115 ldr_str); 7116 break; 7117 case LDR_RECEIVED_LINKDOWN_IDLE_MSG: 7118 /* 7119 * The neighbor reason is only valid if an idle message 7120 * was received for it. 7121 */ 7122 read_planned_down_reason_code(ppd->dd, &neigh_reason); 7123 dd_dev_info(ppd->dd, 7124 "%sNeighbor link down message %d, %s\n", 7125 ldr_str, neigh_reason, 7126 link_down_reason_str(neigh_reason)); 7127 break; 7128 case LDR_RECEIVED_HOST_OFFLINE_REQ: 7129 dd_dev_info(ppd->dd, 7130 "%sHost requested link to go offline\n", 7131 ldr_str); 7132 break; 7133 default: 7134 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n", 7135 ldr_str, link_down_reason); 7136 break; 7137 } 7138 7139 /* 7140 * If no reason, assume peer-initiated but missed 7141 * LinkGoingDown idle flits. 7142 */ 7143 if (neigh_reason == 0) 7144 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN; 7145 } else { 7146 /* went down while polling or going up */ 7147 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT; 7148 } 7149 7150 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0); 7151 7152 /* inform the SMA when the link transitions from up to down */ 7153 if (was_up && ppd->local_link_down_reason.sma == 0 && 7154 ppd->neigh_link_down_reason.sma == 0) { 7155 ppd->local_link_down_reason.sma = 7156 ppd->local_link_down_reason.latest; 7157 ppd->neigh_link_down_reason.sma = 7158 ppd->neigh_link_down_reason.latest; 7159 } 7160 7161 reset_neighbor_info(ppd); 7162 7163 /* disable the port */ 7164 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 7165 7166 /* 7167 * If there is no cable attached, turn the DC off. Otherwise, 7168 * start the link bring up. 7169 */ 7170 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) 7171 dc_shutdown(ppd->dd); 7172 else 7173 start_link(ppd); 7174 } 7175 7176 void handle_link_bounce(struct work_struct *work) 7177 { 7178 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7179 link_bounce_work); 7180 7181 /* 7182 * Only do something if the link is currently up. 7183 */ 7184 if (ppd->host_link_state & HLS_UP) { 7185 set_link_state(ppd, HLS_DN_OFFLINE); 7186 start_link(ppd); 7187 } else { 7188 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n", 7189 __func__, link_state_name(ppd->host_link_state)); 7190 } 7191 } 7192 7193 /* 7194 * Mask conversion: Capability exchange to Port LTP. The capability 7195 * exchange has an implicit 16b CRC that is mandatory. 7196 */ 7197 static int cap_to_port_ltp(int cap) 7198 { 7199 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */ 7200 7201 if (cap & CAP_CRC_14B) 7202 port_ltp |= PORT_LTP_CRC_MODE_14; 7203 if (cap & CAP_CRC_48B) 7204 port_ltp |= PORT_LTP_CRC_MODE_48; 7205 if (cap & CAP_CRC_12B_16B_PER_LANE) 7206 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE; 7207 7208 return port_ltp; 7209 } 7210 7211 /* 7212 * Convert an OPA Port LTP mask to capability mask 7213 */ 7214 int port_ltp_to_cap(int port_ltp) 7215 { 7216 int cap_mask = 0; 7217 7218 if (port_ltp & PORT_LTP_CRC_MODE_14) 7219 cap_mask |= CAP_CRC_14B; 7220 if (port_ltp & PORT_LTP_CRC_MODE_48) 7221 cap_mask |= CAP_CRC_48B; 7222 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE) 7223 cap_mask |= CAP_CRC_12B_16B_PER_LANE; 7224 7225 return cap_mask; 7226 } 7227 7228 /* 7229 * Convert a single DC LCB CRC mode to an OPA Port LTP mask. 7230 */ 7231 static int lcb_to_port_ltp(int lcb_crc) 7232 { 7233 int port_ltp = 0; 7234 7235 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE) 7236 port_ltp = PORT_LTP_CRC_MODE_PER_LANE; 7237 else if (lcb_crc == LCB_CRC_48B) 7238 port_ltp = PORT_LTP_CRC_MODE_48; 7239 else if (lcb_crc == LCB_CRC_14B) 7240 port_ltp = PORT_LTP_CRC_MODE_14; 7241 else 7242 port_ltp = PORT_LTP_CRC_MODE_16; 7243 7244 return port_ltp; 7245 } 7246 7247 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd) 7248 { 7249 if (ppd->pkeys[2] != 0) { 7250 ppd->pkeys[2] = 0; 7251 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0); 7252 hfi1_event_pkey_change(ppd->dd, ppd->port); 7253 } 7254 } 7255 7256 /* 7257 * Convert the given link width to the OPA link width bitmask. 7258 */ 7259 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width) 7260 { 7261 switch (width) { 7262 case 0: 7263 /* 7264 * Simulator and quick linkup do not set the width. 7265 * Just set it to 4x without complaint. 7266 */ 7267 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup) 7268 return OPA_LINK_WIDTH_4X; 7269 return 0; /* no lanes up */ 7270 case 1: return OPA_LINK_WIDTH_1X; 7271 case 2: return OPA_LINK_WIDTH_2X; 7272 case 3: return OPA_LINK_WIDTH_3X; 7273 default: 7274 dd_dev_info(dd, "%s: invalid width %d, using 4\n", 7275 __func__, width); 7276 /* fall through */ 7277 case 4: return OPA_LINK_WIDTH_4X; 7278 } 7279 } 7280 7281 /* 7282 * Do a population count on the bottom nibble. 7283 */ 7284 static const u8 bit_counts[16] = { 7285 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 7286 }; 7287 7288 static inline u8 nibble_to_count(u8 nibble) 7289 { 7290 return bit_counts[nibble & 0xf]; 7291 } 7292 7293 /* 7294 * Read the active lane information from the 8051 registers and return 7295 * their widths. 7296 * 7297 * Active lane information is found in these 8051 registers: 7298 * enable_lane_tx 7299 * enable_lane_rx 7300 */ 7301 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width, 7302 u16 *rx_width) 7303 { 7304 u16 tx, rx; 7305 u8 enable_lane_rx; 7306 u8 enable_lane_tx; 7307 u8 tx_polarity_inversion; 7308 u8 rx_polarity_inversion; 7309 u8 max_rate; 7310 7311 /* read the active lanes */ 7312 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 7313 &rx_polarity_inversion, &max_rate); 7314 read_local_lni(dd, &enable_lane_rx); 7315 7316 /* convert to counts */ 7317 tx = nibble_to_count(enable_lane_tx); 7318 rx = nibble_to_count(enable_lane_rx); 7319 7320 /* 7321 * Set link_speed_active here, overriding what was set in 7322 * handle_verify_cap(). The ASIC 8051 firmware does not correctly 7323 * set the max_rate field in handle_verify_cap until v0.19. 7324 */ 7325 if ((dd->icode == ICODE_RTL_SILICON) && 7326 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) { 7327 /* max_rate: 0 = 12.5G, 1 = 25G */ 7328 switch (max_rate) { 7329 case 0: 7330 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G; 7331 break; 7332 default: 7333 dd_dev_err(dd, 7334 "%s: unexpected max rate %d, using 25Gb\n", 7335 __func__, (int)max_rate); 7336 /* fall through */ 7337 case 1: 7338 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G; 7339 break; 7340 } 7341 } 7342 7343 dd_dev_info(dd, 7344 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n", 7345 enable_lane_tx, tx, enable_lane_rx, rx); 7346 *tx_width = link_width_to_bits(dd, tx); 7347 *rx_width = link_width_to_bits(dd, rx); 7348 } 7349 7350 /* 7351 * Read verify_cap_local_fm_link_width[1] to obtain the link widths. 7352 * Valid after the end of VerifyCap and during LinkUp. Does not change 7353 * after link up. I.e. look elsewhere for downgrade information. 7354 * 7355 * Bits are: 7356 * + bits [7:4] contain the number of active transmitters 7357 * + bits [3:0] contain the number of active receivers 7358 * These are numbers 1 through 4 and can be different values if the 7359 * link is asymmetric. 7360 * 7361 * verify_cap_local_fm_link_width[0] retains its original value. 7362 */ 7363 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width, 7364 u16 *rx_width) 7365 { 7366 u16 widths, tx, rx; 7367 u8 misc_bits, local_flags; 7368 u16 active_tx, active_rx; 7369 7370 read_vc_local_link_mode(dd, &misc_bits, &local_flags, &widths); 7371 tx = widths >> 12; 7372 rx = (widths >> 8) & 0xf; 7373 7374 *tx_width = link_width_to_bits(dd, tx); 7375 *rx_width = link_width_to_bits(dd, rx); 7376 7377 /* print the active widths */ 7378 get_link_widths(dd, &active_tx, &active_rx); 7379 } 7380 7381 /* 7382 * Set ppd->link_width_active and ppd->link_width_downgrade_active using 7383 * hardware information when the link first comes up. 7384 * 7385 * The link width is not available until after VerifyCap.AllFramesReceived 7386 * (the trigger for handle_verify_cap), so this is outside that routine 7387 * and should be called when the 8051 signals linkup. 7388 */ 7389 void get_linkup_link_widths(struct hfi1_pportdata *ppd) 7390 { 7391 u16 tx_width, rx_width; 7392 7393 /* get end-of-LNI link widths */ 7394 get_linkup_widths(ppd->dd, &tx_width, &rx_width); 7395 7396 /* use tx_width as the link is supposed to be symmetric on link up */ 7397 ppd->link_width_active = tx_width; 7398 /* link width downgrade active (LWD.A) starts out matching LW.A */ 7399 ppd->link_width_downgrade_tx_active = ppd->link_width_active; 7400 ppd->link_width_downgrade_rx_active = ppd->link_width_active; 7401 /* per OPA spec, on link up LWD.E resets to LWD.S */ 7402 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported; 7403 /* cache the active egress rate (units {10^6 bits/sec]) */ 7404 ppd->current_egress_rate = active_egress_rate(ppd); 7405 } 7406 7407 /* 7408 * Handle a verify capabilities interrupt from the 8051. 7409 * 7410 * This is a work-queue function outside of the interrupt. 7411 */ 7412 void handle_verify_cap(struct work_struct *work) 7413 { 7414 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7415 link_vc_work); 7416 struct hfi1_devdata *dd = ppd->dd; 7417 u64 reg; 7418 u8 power_management; 7419 u8 continuous; 7420 u8 vcu; 7421 u8 vau; 7422 u8 z; 7423 u16 vl15buf; 7424 u16 link_widths; 7425 u16 crc_mask; 7426 u16 crc_val; 7427 u16 device_id; 7428 u16 active_tx, active_rx; 7429 u8 partner_supported_crc; 7430 u8 remote_tx_rate; 7431 u8 device_rev; 7432 7433 set_link_state(ppd, HLS_VERIFY_CAP); 7434 7435 lcb_shutdown(dd, 0); 7436 adjust_lcb_for_fpga_serdes(dd); 7437 7438 read_vc_remote_phy(dd, &power_management, &continuous); 7439 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf, 7440 &partner_supported_crc); 7441 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths); 7442 read_remote_device_id(dd, &device_id, &device_rev); 7443 7444 /* print the active widths */ 7445 get_link_widths(dd, &active_tx, &active_rx); 7446 dd_dev_info(dd, 7447 "Peer PHY: power management 0x%x, continuous updates 0x%x\n", 7448 (int)power_management, (int)continuous); 7449 dd_dev_info(dd, 7450 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n", 7451 (int)vau, (int)z, (int)vcu, (int)vl15buf, 7452 (int)partner_supported_crc); 7453 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n", 7454 (u32)remote_tx_rate, (u32)link_widths); 7455 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n", 7456 (u32)device_id, (u32)device_rev); 7457 /* 7458 * The peer vAU value just read is the peer receiver value. HFI does 7459 * not support a transmit vAU of 0 (AU == 8). We advertised that 7460 * with Z=1 in the fabric capabilities sent to the peer. The peer 7461 * will see our Z=1, and, if it advertised a vAU of 0, will move its 7462 * receive to vAU of 1 (AU == 16). Do the same here. We do not care 7463 * about the peer Z value - our sent vAU is 3 (hardwired) and is not 7464 * subject to the Z value exception. 7465 */ 7466 if (vau == 0) 7467 vau = 1; 7468 set_up_vau(dd, vau); 7469 7470 /* 7471 * Set VL15 credits to 0 in global credit register. Cache remote VL15 7472 * credits value and wait for link-up interrupt ot set it. 7473 */ 7474 set_up_vl15(dd, 0); 7475 dd->vl15buf_cached = vl15buf; 7476 7477 /* set up the LCB CRC mode */ 7478 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc; 7479 7480 /* order is important: use the lowest bit in common */ 7481 if (crc_mask & CAP_CRC_14B) 7482 crc_val = LCB_CRC_14B; 7483 else if (crc_mask & CAP_CRC_48B) 7484 crc_val = LCB_CRC_48B; 7485 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE) 7486 crc_val = LCB_CRC_12B_16B_PER_LANE; 7487 else 7488 crc_val = LCB_CRC_16B; 7489 7490 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val); 7491 write_csr(dd, DC_LCB_CFG_CRC_MODE, 7492 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT); 7493 7494 /* set (14b only) or clear sideband credit */ 7495 reg = read_csr(dd, SEND_CM_CTRL); 7496 if (crc_val == LCB_CRC_14B && crc_14b_sideband) { 7497 write_csr(dd, SEND_CM_CTRL, 7498 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7499 } else { 7500 write_csr(dd, SEND_CM_CTRL, 7501 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); 7502 } 7503 7504 ppd->link_speed_active = 0; /* invalid value */ 7505 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 7506 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */ 7507 switch (remote_tx_rate) { 7508 case 0: 7509 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7510 break; 7511 case 1: 7512 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7513 break; 7514 } 7515 } else { 7516 /* actual rate is highest bit of the ANDed rates */ 7517 u8 rate = remote_tx_rate & ppd->local_tx_rate; 7518 7519 if (rate & 2) 7520 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7521 else if (rate & 1) 7522 ppd->link_speed_active = OPA_LINK_SPEED_12_5G; 7523 } 7524 if (ppd->link_speed_active == 0) { 7525 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n", 7526 __func__, (int)remote_tx_rate); 7527 ppd->link_speed_active = OPA_LINK_SPEED_25G; 7528 } 7529 7530 /* 7531 * Cache the values of the supported, enabled, and active 7532 * LTP CRC modes to return in 'portinfo' queries. But the bit 7533 * flags that are returned in the portinfo query differ from 7534 * what's in the link_crc_mask, crc_sizes, and crc_val 7535 * variables. Convert these here. 7536 */ 7537 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 7538 /* supported crc modes */ 7539 ppd->port_ltp_crc_mode |= 7540 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4; 7541 /* enabled crc modes */ 7542 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val); 7543 /* active crc mode */ 7544 7545 /* set up the remote credit return table */ 7546 assign_remote_cm_au_table(dd, vcu); 7547 7548 /* 7549 * The LCB is reset on entry to handle_verify_cap(), so this must 7550 * be applied on every link up. 7551 * 7552 * Adjust LCB error kill enable to kill the link if 7553 * these RBUF errors are seen: 7554 * REPLAY_BUF_MBE_SMASK 7555 * FLIT_INPUT_BUF_MBE_SMASK 7556 */ 7557 if (is_ax(dd)) { /* fixed in B0 */ 7558 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); 7559 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 7560 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK; 7561 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); 7562 } 7563 7564 /* pull LCB fifos out of reset - all fifo clocks must be stable */ 7565 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 7566 7567 /* give 8051 access to the LCB CSRs */ 7568 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 7569 set_8051_lcb_access(dd); 7570 7571 /* tell the 8051 to go to LinkUp */ 7572 set_link_state(ppd, HLS_GOING_UP); 7573 } 7574 7575 /** 7576 * apply_link_downgrade_policy - Apply the link width downgrade enabled 7577 * policy against the current active link widths. 7578 * @ppd: info of physical Hfi port 7579 * @refresh_widths: True indicates link downgrade event 7580 * @return: True indicates a successful link downgrade. False indicates 7581 * link downgrade event failed and the link will bounce back to 7582 * default link width. 7583 * 7584 * Called when the enabled policy changes or the active link widths 7585 * change. 7586 * Refresh_widths indicates that a link downgrade occurred. The 7587 * link_downgraded variable is set by refresh_widths and 7588 * determines the success/failure of the policy application. 7589 */ 7590 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, 7591 bool refresh_widths) 7592 { 7593 int do_bounce = 0; 7594 int tries; 7595 u16 lwde; 7596 u16 tx, rx; 7597 bool link_downgraded = refresh_widths; 7598 7599 /* use the hls lock to avoid a race with actual link up */ 7600 tries = 0; 7601 retry: 7602 mutex_lock(&ppd->hls_lock); 7603 /* only apply if the link is up */ 7604 if (ppd->host_link_state & HLS_DOWN) { 7605 /* still going up..wait and retry */ 7606 if (ppd->host_link_state & HLS_GOING_UP) { 7607 if (++tries < 1000) { 7608 mutex_unlock(&ppd->hls_lock); 7609 usleep_range(100, 120); /* arbitrary */ 7610 goto retry; 7611 } 7612 dd_dev_err(ppd->dd, 7613 "%s: giving up waiting for link state change\n", 7614 __func__); 7615 } 7616 goto done; 7617 } 7618 7619 lwde = ppd->link_width_downgrade_enabled; 7620 7621 if (refresh_widths) { 7622 get_link_widths(ppd->dd, &tx, &rx); 7623 ppd->link_width_downgrade_tx_active = tx; 7624 ppd->link_width_downgrade_rx_active = rx; 7625 } 7626 7627 if (ppd->link_width_downgrade_tx_active == 0 || 7628 ppd->link_width_downgrade_rx_active == 0) { 7629 /* the 8051 reported a dead link as a downgrade */ 7630 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n"); 7631 link_downgraded = false; 7632 } else if (lwde == 0) { 7633 /* downgrade is disabled */ 7634 7635 /* bounce if not at starting active width */ 7636 if ((ppd->link_width_active != 7637 ppd->link_width_downgrade_tx_active) || 7638 (ppd->link_width_active != 7639 ppd->link_width_downgrade_rx_active)) { 7640 dd_dev_err(ppd->dd, 7641 "Link downgrade is disabled and link has downgraded, downing link\n"); 7642 dd_dev_err(ppd->dd, 7643 " original 0x%x, tx active 0x%x, rx active 0x%x\n", 7644 ppd->link_width_active, 7645 ppd->link_width_downgrade_tx_active, 7646 ppd->link_width_downgrade_rx_active); 7647 do_bounce = 1; 7648 link_downgraded = false; 7649 } 7650 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 || 7651 (lwde & ppd->link_width_downgrade_rx_active) == 0) { 7652 /* Tx or Rx is outside the enabled policy */ 7653 dd_dev_err(ppd->dd, 7654 "Link is outside of downgrade allowed, downing link\n"); 7655 dd_dev_err(ppd->dd, 7656 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n", 7657 lwde, ppd->link_width_downgrade_tx_active, 7658 ppd->link_width_downgrade_rx_active); 7659 do_bounce = 1; 7660 link_downgraded = false; 7661 } 7662 7663 done: 7664 mutex_unlock(&ppd->hls_lock); 7665 7666 if (do_bounce) { 7667 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0, 7668 OPA_LINKDOWN_REASON_WIDTH_POLICY); 7669 set_link_state(ppd, HLS_DN_OFFLINE); 7670 start_link(ppd); 7671 } 7672 7673 return link_downgraded; 7674 } 7675 7676 /* 7677 * Handle a link downgrade interrupt from the 8051. 7678 * 7679 * This is a work-queue function outside of the interrupt. 7680 */ 7681 void handle_link_downgrade(struct work_struct *work) 7682 { 7683 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 7684 link_downgrade_work); 7685 7686 dd_dev_info(ppd->dd, "8051: Link width downgrade\n"); 7687 if (apply_link_downgrade_policy(ppd, true)) 7688 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active); 7689 } 7690 7691 static char *dcc_err_string(char *buf, int buf_len, u64 flags) 7692 { 7693 return flag_string(buf, buf_len, flags, dcc_err_flags, 7694 ARRAY_SIZE(dcc_err_flags)); 7695 } 7696 7697 static char *lcb_err_string(char *buf, int buf_len, u64 flags) 7698 { 7699 return flag_string(buf, buf_len, flags, lcb_err_flags, 7700 ARRAY_SIZE(lcb_err_flags)); 7701 } 7702 7703 static char *dc8051_err_string(char *buf, int buf_len, u64 flags) 7704 { 7705 return flag_string(buf, buf_len, flags, dc8051_err_flags, 7706 ARRAY_SIZE(dc8051_err_flags)); 7707 } 7708 7709 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags) 7710 { 7711 return flag_string(buf, buf_len, flags, dc8051_info_err_flags, 7712 ARRAY_SIZE(dc8051_info_err_flags)); 7713 } 7714 7715 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags) 7716 { 7717 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags, 7718 ARRAY_SIZE(dc8051_info_host_msg_flags)); 7719 } 7720 7721 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg) 7722 { 7723 struct hfi1_pportdata *ppd = dd->pport; 7724 u64 info, err, host_msg; 7725 int queue_link_down = 0; 7726 char buf[96]; 7727 7728 /* look at the flags */ 7729 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) { 7730 /* 8051 information set by firmware */ 7731 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */ 7732 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); 7733 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT) 7734 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK; 7735 host_msg = (info >> 7736 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT) 7737 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK; 7738 7739 /* 7740 * Handle error flags. 7741 */ 7742 if (err & FAILED_LNI) { 7743 /* 7744 * LNI error indications are cleared by the 8051 7745 * only when starting polling. Only pay attention 7746 * to them when in the states that occur during 7747 * LNI. 7748 */ 7749 if (ppd->host_link_state 7750 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 7751 queue_link_down = 1; 7752 dd_dev_info(dd, "Link error: %s\n", 7753 dc8051_info_err_string(buf, 7754 sizeof(buf), 7755 err & 7756 FAILED_LNI)); 7757 } 7758 err &= ~(u64)FAILED_LNI; 7759 } 7760 /* unknown frames can happen durning LNI, just count */ 7761 if (err & UNKNOWN_FRAME) { 7762 ppd->unknown_frame_count++; 7763 err &= ~(u64)UNKNOWN_FRAME; 7764 } 7765 if (err) { 7766 /* report remaining errors, but do not do anything */ 7767 dd_dev_err(dd, "8051 info error: %s\n", 7768 dc8051_info_err_string(buf, sizeof(buf), 7769 err)); 7770 } 7771 7772 /* 7773 * Handle host message flags. 7774 */ 7775 if (host_msg & HOST_REQ_DONE) { 7776 /* 7777 * Presently, the driver does a busy wait for 7778 * host requests to complete. This is only an 7779 * informational message. 7780 * NOTE: The 8051 clears the host message 7781 * information *on the next 8051 command*. 7782 * Therefore, when linkup is achieved, 7783 * this flag will still be set. 7784 */ 7785 host_msg &= ~(u64)HOST_REQ_DONE; 7786 } 7787 if (host_msg & BC_SMA_MSG) { 7788 queue_work(ppd->link_wq, &ppd->sma_message_work); 7789 host_msg &= ~(u64)BC_SMA_MSG; 7790 } 7791 if (host_msg & LINKUP_ACHIEVED) { 7792 dd_dev_info(dd, "8051: Link up\n"); 7793 queue_work(ppd->link_wq, &ppd->link_up_work); 7794 host_msg &= ~(u64)LINKUP_ACHIEVED; 7795 } 7796 if (host_msg & EXT_DEVICE_CFG_REQ) { 7797 handle_8051_request(ppd); 7798 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ; 7799 } 7800 if (host_msg & VERIFY_CAP_FRAME) { 7801 queue_work(ppd->link_wq, &ppd->link_vc_work); 7802 host_msg &= ~(u64)VERIFY_CAP_FRAME; 7803 } 7804 if (host_msg & LINK_GOING_DOWN) { 7805 const char *extra = ""; 7806 /* no downgrade action needed if going down */ 7807 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7808 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7809 extra = " (ignoring downgrade)"; 7810 } 7811 dd_dev_info(dd, "8051: Link down%s\n", extra); 7812 queue_link_down = 1; 7813 host_msg &= ~(u64)LINK_GOING_DOWN; 7814 } 7815 if (host_msg & LINK_WIDTH_DOWNGRADED) { 7816 queue_work(ppd->link_wq, &ppd->link_downgrade_work); 7817 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED; 7818 } 7819 if (host_msg) { 7820 /* report remaining messages, but do not do anything */ 7821 dd_dev_info(dd, "8051 info host message: %s\n", 7822 dc8051_info_host_msg_string(buf, 7823 sizeof(buf), 7824 host_msg)); 7825 } 7826 7827 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK; 7828 } 7829 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) { 7830 /* 7831 * Lost the 8051 heartbeat. If this happens, we 7832 * receive constant interrupts about it. Disable 7833 * the interrupt after the first. 7834 */ 7835 dd_dev_err(dd, "Lost 8051 heartbeat\n"); 7836 write_csr(dd, DC_DC8051_ERR_EN, 7837 read_csr(dd, DC_DC8051_ERR_EN) & 7838 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK); 7839 7840 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK; 7841 } 7842 if (reg) { 7843 /* report the error, but do not do anything */ 7844 dd_dev_err(dd, "8051 error: %s\n", 7845 dc8051_err_string(buf, sizeof(buf), reg)); 7846 } 7847 7848 if (queue_link_down) { 7849 /* 7850 * if the link is already going down or disabled, do not 7851 * queue another. If there's a link down entry already 7852 * queued, don't queue another one. 7853 */ 7854 if ((ppd->host_link_state & 7855 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) || 7856 ppd->link_enabled == 0) { 7857 dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n", 7858 __func__, ppd->host_link_state, 7859 ppd->link_enabled); 7860 } else { 7861 if (xchg(&ppd->is_link_down_queued, 1) == 1) 7862 dd_dev_info(dd, 7863 "%s: link down request already queued\n", 7864 __func__); 7865 else 7866 queue_work(ppd->link_wq, &ppd->link_down_work); 7867 } 7868 } 7869 } 7870 7871 static const char * const fm_config_txt[] = { 7872 [0] = 7873 "BadHeadDist: Distance violation between two head flits", 7874 [1] = 7875 "BadTailDist: Distance violation between two tail flits", 7876 [2] = 7877 "BadCtrlDist: Distance violation between two credit control flits", 7878 [3] = 7879 "BadCrdAck: Credits return for unsupported VL", 7880 [4] = 7881 "UnsupportedVLMarker: Received VL Marker", 7882 [5] = 7883 "BadPreempt: Exceeded the preemption nesting level", 7884 [6] = 7885 "BadControlFlit: Received unsupported control flit", 7886 /* no 7 */ 7887 [8] = 7888 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL", 7889 }; 7890 7891 static const char * const port_rcv_txt[] = { 7892 [1] = 7893 "BadPktLen: Illegal PktLen", 7894 [2] = 7895 "PktLenTooLong: Packet longer than PktLen", 7896 [3] = 7897 "PktLenTooShort: Packet shorter than PktLen", 7898 [4] = 7899 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)", 7900 [5] = 7901 "BadDLID: Illegal DLID (0, doesn't match HFI)", 7902 [6] = 7903 "BadL2: Illegal L2 opcode", 7904 [7] = 7905 "BadSC: Unsupported SC", 7906 [9] = 7907 "BadRC: Illegal RC", 7908 [11] = 7909 "PreemptError: Preempting with same VL", 7910 [12] = 7911 "PreemptVL15: Preempting a VL15 packet", 7912 }; 7913 7914 #define OPA_LDR_FMCONFIG_OFFSET 16 7915 #define OPA_LDR_PORTRCV_OFFSET 0 7916 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 7917 { 7918 u64 info, hdr0, hdr1; 7919 const char *extra; 7920 char buf[96]; 7921 struct hfi1_pportdata *ppd = dd->pport; 7922 u8 lcl_reason = 0; 7923 int do_bounce = 0; 7924 7925 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) { 7926 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) { 7927 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); 7928 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK; 7929 /* set status bit */ 7930 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK; 7931 } 7932 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK; 7933 } 7934 7935 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) { 7936 struct hfi1_pportdata *ppd = dd->pport; 7937 /* this counter saturates at (2^32) - 1 */ 7938 if (ppd->link_downed < (u32)UINT_MAX) 7939 ppd->link_downed++; 7940 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK; 7941 } 7942 7943 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) { 7944 u8 reason_valid = 1; 7945 7946 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); 7947 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) { 7948 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK; 7949 /* set status bit */ 7950 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK; 7951 } 7952 switch (info) { 7953 case 0: 7954 case 1: 7955 case 2: 7956 case 3: 7957 case 4: 7958 case 5: 7959 case 6: 7960 extra = fm_config_txt[info]; 7961 break; 7962 case 8: 7963 extra = fm_config_txt[info]; 7964 if (ppd->port_error_action & 7965 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) { 7966 do_bounce = 1; 7967 /* 7968 * lcl_reason cannot be derived from info 7969 * for this error 7970 */ 7971 lcl_reason = 7972 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER; 7973 } 7974 break; 7975 default: 7976 reason_valid = 0; 7977 snprintf(buf, sizeof(buf), "reserved%lld", info); 7978 extra = buf; 7979 break; 7980 } 7981 7982 if (reason_valid && !do_bounce) { 7983 do_bounce = ppd->port_error_action & 7984 (1 << (OPA_LDR_FMCONFIG_OFFSET + info)); 7985 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST; 7986 } 7987 7988 /* just report this */ 7989 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n", 7990 extra); 7991 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK; 7992 } 7993 7994 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) { 7995 u8 reason_valid = 1; 7996 7997 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); 7998 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); 7999 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); 8000 if (!(dd->err_info_rcvport.status_and_code & 8001 OPA_EI_STATUS_SMASK)) { 8002 dd->err_info_rcvport.status_and_code = 8003 info & OPA_EI_CODE_SMASK; 8004 /* set status bit */ 8005 dd->err_info_rcvport.status_and_code |= 8006 OPA_EI_STATUS_SMASK; 8007 /* 8008 * save first 2 flits in the packet that caused 8009 * the error 8010 */ 8011 dd->err_info_rcvport.packet_flit1 = hdr0; 8012 dd->err_info_rcvport.packet_flit2 = hdr1; 8013 } 8014 switch (info) { 8015 case 1: 8016 case 2: 8017 case 3: 8018 case 4: 8019 case 5: 8020 case 6: 8021 case 7: 8022 case 9: 8023 case 11: 8024 case 12: 8025 extra = port_rcv_txt[info]; 8026 break; 8027 default: 8028 reason_valid = 0; 8029 snprintf(buf, sizeof(buf), "reserved%lld", info); 8030 extra = buf; 8031 break; 8032 } 8033 8034 if (reason_valid && !do_bounce) { 8035 do_bounce = ppd->port_error_action & 8036 (1 << (OPA_LDR_PORTRCV_OFFSET + info)); 8037 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0; 8038 } 8039 8040 /* just report this */ 8041 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n" 8042 " hdr0 0x%llx, hdr1 0x%llx\n", 8043 extra, hdr0, hdr1); 8044 8045 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK; 8046 } 8047 8048 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) { 8049 /* informative only */ 8050 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n"); 8051 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK; 8052 } 8053 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) { 8054 /* informative only */ 8055 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n"); 8056 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK; 8057 } 8058 8059 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev))) 8060 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK; 8061 8062 /* report any remaining errors */ 8063 if (reg) 8064 dd_dev_info_ratelimited(dd, "DCC Error: %s\n", 8065 dcc_err_string(buf, sizeof(buf), reg)); 8066 8067 if (lcl_reason == 0) 8068 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN; 8069 8070 if (do_bounce) { 8071 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n", 8072 __func__); 8073 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason); 8074 queue_work(ppd->link_wq, &ppd->link_bounce_work); 8075 } 8076 } 8077 8078 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 8079 { 8080 char buf[96]; 8081 8082 dd_dev_info(dd, "LCB Error: %s\n", 8083 lcb_err_string(buf, sizeof(buf), reg)); 8084 } 8085 8086 /* 8087 * CCE block DC interrupt. Source is < 8. 8088 */ 8089 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source) 8090 { 8091 const struct err_reg_info *eri = &dc_errs[source]; 8092 8093 if (eri->handler) { 8094 interrupt_clear_down(dd, 0, eri); 8095 } else if (source == 3 /* dc_lbm_int */) { 8096 /* 8097 * This indicates that a parity error has occurred on the 8098 * address/control lines presented to the LBM. The error 8099 * is a single pulse, there is no associated error flag, 8100 * and it is non-maskable. This is because if a parity 8101 * error occurs on the request the request is dropped. 8102 * This should never occur, but it is nice to know if it 8103 * ever does. 8104 */ 8105 dd_dev_err(dd, "Parity error in DC LBM block\n"); 8106 } else { 8107 dd_dev_err(dd, "Invalid DC interrupt %u\n", source); 8108 } 8109 } 8110 8111 /* 8112 * TX block send credit interrupt. Source is < 160. 8113 */ 8114 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source) 8115 { 8116 sc_group_release_update(dd, source); 8117 } 8118 8119 /* 8120 * TX block SDMA interrupt. Source is < 48. 8121 * 8122 * SDMA interrupts are grouped by type: 8123 * 8124 * 0 - N-1 = SDma 8125 * N - 2N-1 = SDmaProgress 8126 * 2N - 3N-1 = SDmaIdle 8127 */ 8128 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source) 8129 { 8130 /* what interrupt */ 8131 unsigned int what = source / TXE_NUM_SDMA_ENGINES; 8132 /* which engine */ 8133 unsigned int which = source % TXE_NUM_SDMA_ENGINES; 8134 8135 #ifdef CONFIG_SDMA_VERBOSITY 8136 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which, 8137 slashstrip(__FILE__), __LINE__, __func__); 8138 sdma_dumpstate(&dd->per_sdma[which]); 8139 #endif 8140 8141 if (likely(what < 3 && which < dd->num_sdma)) { 8142 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source); 8143 } else { 8144 /* should not happen */ 8145 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source); 8146 } 8147 } 8148 8149 /** 8150 * is_rcv_avail_int() - User receive context available IRQ handler 8151 * @dd: valid dd 8152 * @source: logical IRQ source (offset from IS_RCVAVAIL_START) 8153 * 8154 * RX block receive available interrupt. Source is < 160. 8155 * 8156 * This is the general interrupt handler for user (PSM) receive contexts, 8157 * and can only be used for non-threaded IRQs. 8158 */ 8159 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source) 8160 { 8161 struct hfi1_ctxtdata *rcd; 8162 char *err_detail; 8163 8164 if (likely(source < dd->num_rcv_contexts)) { 8165 rcd = hfi1_rcd_get_by_index(dd, source); 8166 if (rcd) { 8167 handle_user_interrupt(rcd); 8168 hfi1_rcd_put(rcd); 8169 return; /* OK */ 8170 } 8171 /* received an interrupt, but no rcd */ 8172 err_detail = "dataless"; 8173 } else { 8174 /* received an interrupt, but are not using that context */ 8175 err_detail = "out of range"; 8176 } 8177 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n", 8178 err_detail, source); 8179 } 8180 8181 /** 8182 * is_rcv_urgent_int() - User receive context urgent IRQ handler 8183 * @dd: valid dd 8184 * @source: logical IRQ source (offset from IS_RCVURGENT_START) 8185 * 8186 * RX block receive urgent interrupt. Source is < 160. 8187 * 8188 * NOTE: kernel receive contexts specifically do NOT enable this IRQ. 8189 */ 8190 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source) 8191 { 8192 struct hfi1_ctxtdata *rcd; 8193 char *err_detail; 8194 8195 if (likely(source < dd->num_rcv_contexts)) { 8196 rcd = hfi1_rcd_get_by_index(dd, source); 8197 if (rcd) { 8198 handle_user_interrupt(rcd); 8199 hfi1_rcd_put(rcd); 8200 return; /* OK */ 8201 } 8202 /* received an interrupt, but no rcd */ 8203 err_detail = "dataless"; 8204 } else { 8205 /* received an interrupt, but are not using that context */ 8206 err_detail = "out of range"; 8207 } 8208 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n", 8209 err_detail, source); 8210 } 8211 8212 /* 8213 * Reserved range interrupt. Should not be called in normal operation. 8214 */ 8215 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source) 8216 { 8217 char name[64]; 8218 8219 dd_dev_err(dd, "unexpected %s interrupt\n", 8220 is_reserved_name(name, sizeof(name), source)); 8221 } 8222 8223 static const struct is_table is_table[] = { 8224 /* 8225 * start end 8226 * name func interrupt func 8227 */ 8228 { IS_GENERAL_ERR_START, IS_GENERAL_ERR_END, 8229 is_misc_err_name, is_misc_err_int }, 8230 { IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END, 8231 is_sdma_eng_err_name, is_sdma_eng_err_int }, 8232 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, 8233 is_sendctxt_err_name, is_sendctxt_err_int }, 8234 { IS_SDMA_START, IS_SDMA_IDLE_END, 8235 is_sdma_eng_name, is_sdma_eng_int }, 8236 { IS_VARIOUS_START, IS_VARIOUS_END, 8237 is_various_name, is_various_int }, 8238 { IS_DC_START, IS_DC_END, 8239 is_dc_name, is_dc_int }, 8240 { IS_RCVAVAIL_START, IS_RCVAVAIL_END, 8241 is_rcv_avail_name, is_rcv_avail_int }, 8242 { IS_RCVURGENT_START, IS_RCVURGENT_END, 8243 is_rcv_urgent_name, is_rcv_urgent_int }, 8244 { IS_SENDCREDIT_START, IS_SENDCREDIT_END, 8245 is_send_credit_name, is_send_credit_int}, 8246 { IS_RESERVED_START, IS_RESERVED_END, 8247 is_reserved_name, is_reserved_int}, 8248 }; 8249 8250 /* 8251 * Interrupt source interrupt - called when the given source has an interrupt. 8252 * Source is a bit index into an array of 64-bit integers. 8253 */ 8254 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source) 8255 { 8256 const struct is_table *entry; 8257 8258 /* avoids a double compare by walking the table in-order */ 8259 for (entry = &is_table[0]; entry->is_name; entry++) { 8260 if (source <= entry->end) { 8261 trace_hfi1_interrupt(dd, entry, source); 8262 entry->is_int(dd, source - entry->start); 8263 return; 8264 } 8265 } 8266 /* fell off the end */ 8267 dd_dev_err(dd, "invalid interrupt source %u\n", source); 8268 } 8269 8270 /** 8271 * gerneral_interrupt() - General interrupt handler 8272 * @irq: MSIx IRQ vector 8273 * @data: hfi1 devdata 8274 * 8275 * This is able to correctly handle all non-threaded interrupts. Receive 8276 * context DATA IRQs are threaded and are not supported by this handler. 8277 * 8278 */ 8279 irqreturn_t general_interrupt(int irq, void *data) 8280 { 8281 struct hfi1_devdata *dd = data; 8282 u64 regs[CCE_NUM_INT_CSRS]; 8283 u32 bit; 8284 int i; 8285 irqreturn_t handled = IRQ_NONE; 8286 8287 this_cpu_inc(*dd->int_counter); 8288 8289 /* phase 1: scan and clear all handled interrupts */ 8290 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 8291 if (dd->gi_mask[i] == 0) { 8292 regs[i] = 0; /* used later */ 8293 continue; 8294 } 8295 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & 8296 dd->gi_mask[i]; 8297 /* only clear if anything is set */ 8298 if (regs[i]) 8299 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); 8300 } 8301 8302 /* phase 2: call the appropriate handler */ 8303 for_each_set_bit(bit, (unsigned long *)®s[0], 8304 CCE_NUM_INT_CSRS * 64) { 8305 is_interrupt(dd, bit); 8306 handled = IRQ_HANDLED; 8307 } 8308 8309 return handled; 8310 } 8311 8312 irqreturn_t sdma_interrupt(int irq, void *data) 8313 { 8314 struct sdma_engine *sde = data; 8315 struct hfi1_devdata *dd = sde->dd; 8316 u64 status; 8317 8318 #ifdef CONFIG_SDMA_VERBOSITY 8319 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 8320 slashstrip(__FILE__), __LINE__, __func__); 8321 sdma_dumpstate(sde); 8322 #endif 8323 8324 this_cpu_inc(*dd->int_counter); 8325 8326 /* This read_csr is really bad in the hot path */ 8327 status = read_csr(dd, 8328 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64))) 8329 & sde->imask; 8330 if (likely(status)) { 8331 /* clear the interrupt(s) */ 8332 write_csr(dd, 8333 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)), 8334 status); 8335 8336 /* handle the interrupt(s) */ 8337 sdma_engine_interrupt(sde, status); 8338 } else { 8339 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n", 8340 sde->this_idx); 8341 } 8342 return IRQ_HANDLED; 8343 } 8344 8345 /* 8346 * Clear the receive interrupt. Use a read of the interrupt clear CSR 8347 * to insure that the write completed. This does NOT guarantee that 8348 * queued DMA writes to memory from the chip are pushed. 8349 */ 8350 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd) 8351 { 8352 struct hfi1_devdata *dd = rcd->dd; 8353 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg); 8354 8355 mmiowb(); /* make sure everything before is written */ 8356 write_csr(dd, addr, rcd->imask); 8357 /* force the above write on the chip and get a value back */ 8358 (void)read_csr(dd, addr); 8359 } 8360 8361 /* force the receive interrupt */ 8362 void force_recv_intr(struct hfi1_ctxtdata *rcd) 8363 { 8364 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); 8365 } 8366 8367 /* 8368 * Return non-zero if a packet is present. 8369 * 8370 * This routine is called when rechecking for packets after the RcvAvail 8371 * interrupt has been cleared down. First, do a quick check of memory for 8372 * a packet present. If not found, use an expensive CSR read of the context 8373 * tail to determine the actual tail. The CSR read is necessary because there 8374 * is no method to push pending DMAs to memory other than an interrupt and we 8375 * are trying to determine if we need to force an interrupt. 8376 */ 8377 static inline int check_packet_present(struct hfi1_ctxtdata *rcd) 8378 { 8379 u32 tail; 8380 int present; 8381 8382 if (!rcd->rcvhdrtail_kvaddr) 8383 present = (rcd->seq_cnt == 8384 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd)))); 8385 else /* is RDMA rtail */ 8386 present = (rcd->head != get_rcvhdrtail(rcd)); 8387 8388 if (present) 8389 return 1; 8390 8391 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */ 8392 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 8393 return rcd->head != tail; 8394 } 8395 8396 /* 8397 * Receive packet IRQ handler. This routine expects to be on its own IRQ. 8398 * This routine will try to handle packets immediately (latency), but if 8399 * it finds too many, it will invoke the thread handler (bandwitdh). The 8400 * chip receive interrupt is *not* cleared down until this or the thread (if 8401 * invoked) is finished. The intent is to avoid extra interrupts while we 8402 * are processing packets anyway. 8403 */ 8404 irqreturn_t receive_context_interrupt(int irq, void *data) 8405 { 8406 struct hfi1_ctxtdata *rcd = data; 8407 struct hfi1_devdata *dd = rcd->dd; 8408 int disposition; 8409 int present; 8410 8411 trace_hfi1_receive_interrupt(dd, rcd); 8412 this_cpu_inc(*dd->int_counter); 8413 aspm_ctx_disable(rcd); 8414 8415 /* receive interrupt remains blocked while processing packets */ 8416 disposition = rcd->do_interrupt(rcd, 0); 8417 8418 /* 8419 * Too many packets were seen while processing packets in this 8420 * IRQ handler. Invoke the handler thread. The receive interrupt 8421 * remains blocked. 8422 */ 8423 if (disposition == RCV_PKT_LIMIT) 8424 return IRQ_WAKE_THREAD; 8425 8426 /* 8427 * The packet processor detected no more packets. Clear the receive 8428 * interrupt and recheck for a packet packet that may have arrived 8429 * after the previous check and interrupt clear. If a packet arrived, 8430 * force another interrupt. 8431 */ 8432 clear_recv_intr(rcd); 8433 present = check_packet_present(rcd); 8434 if (present) 8435 force_recv_intr(rcd); 8436 8437 return IRQ_HANDLED; 8438 } 8439 8440 /* 8441 * Receive packet thread handler. This expects to be invoked with the 8442 * receive interrupt still blocked. 8443 */ 8444 irqreturn_t receive_context_thread(int irq, void *data) 8445 { 8446 struct hfi1_ctxtdata *rcd = data; 8447 int present; 8448 8449 /* receive interrupt is still blocked from the IRQ handler */ 8450 (void)rcd->do_interrupt(rcd, 1); 8451 8452 /* 8453 * The packet processor will only return if it detected no more 8454 * packets. Hold IRQs here so we can safely clear the interrupt and 8455 * recheck for a packet that may have arrived after the previous 8456 * check and the interrupt clear. If a packet arrived, force another 8457 * interrupt. 8458 */ 8459 local_irq_disable(); 8460 clear_recv_intr(rcd); 8461 present = check_packet_present(rcd); 8462 if (present) 8463 force_recv_intr(rcd); 8464 local_irq_enable(); 8465 8466 return IRQ_HANDLED; 8467 } 8468 8469 /* ========================================================================= */ 8470 8471 u32 read_physical_state(struct hfi1_devdata *dd) 8472 { 8473 u64 reg; 8474 8475 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 8476 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT) 8477 & DC_DC8051_STS_CUR_STATE_PORT_MASK; 8478 } 8479 8480 u32 read_logical_state(struct hfi1_devdata *dd) 8481 { 8482 u64 reg; 8483 8484 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8485 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT) 8486 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK; 8487 } 8488 8489 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate) 8490 { 8491 u64 reg; 8492 8493 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); 8494 /* clear current state, set new state */ 8495 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK; 8496 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT; 8497 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); 8498 } 8499 8500 /* 8501 * Use the 8051 to read a LCB CSR. 8502 */ 8503 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data) 8504 { 8505 u32 regno; 8506 int ret; 8507 8508 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 8509 if (acquire_lcb_access(dd, 0) == 0) { 8510 *data = read_csr(dd, addr); 8511 release_lcb_access(dd, 0); 8512 return 0; 8513 } 8514 return -EBUSY; 8515 } 8516 8517 /* register is an index of LCB registers: (offset - base) / 8 */ 8518 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8519 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data); 8520 if (ret != HCMD_SUCCESS) 8521 return -EBUSY; 8522 return 0; 8523 } 8524 8525 /* 8526 * Provide a cache for some of the LCB registers in case the LCB is 8527 * unavailable. 8528 * (The LCB is unavailable in certain link states, for example.) 8529 */ 8530 struct lcb_datum { 8531 u32 off; 8532 u64 val; 8533 }; 8534 8535 static struct lcb_datum lcb_cache[] = { 8536 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0}, 8537 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 }, 8538 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 }, 8539 }; 8540 8541 static void update_lcb_cache(struct hfi1_devdata *dd) 8542 { 8543 int i; 8544 int ret; 8545 u64 val; 8546 8547 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8548 ret = read_lcb_csr(dd, lcb_cache[i].off, &val); 8549 8550 /* Update if we get good data */ 8551 if (likely(ret != -EBUSY)) 8552 lcb_cache[i].val = val; 8553 } 8554 } 8555 8556 static int read_lcb_cache(u32 off, u64 *val) 8557 { 8558 int i; 8559 8560 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) { 8561 if (lcb_cache[i].off == off) { 8562 *val = lcb_cache[i].val; 8563 return 0; 8564 } 8565 } 8566 8567 pr_warn("%s bad offset 0x%x\n", __func__, off); 8568 return -1; 8569 } 8570 8571 /* 8572 * Read an LCB CSR. Access may not be in host control, so check. 8573 * Return 0 on success, -EBUSY on failure. 8574 */ 8575 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data) 8576 { 8577 struct hfi1_pportdata *ppd = dd->pport; 8578 8579 /* if up, go through the 8051 for the value */ 8580 if (ppd->host_link_state & HLS_UP) 8581 return read_lcb_via_8051(dd, addr, data); 8582 /* if going up or down, check the cache, otherwise, no access */ 8583 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) { 8584 if (read_lcb_cache(addr, data)) 8585 return -EBUSY; 8586 return 0; 8587 } 8588 8589 /* otherwise, host has access */ 8590 *data = read_csr(dd, addr); 8591 return 0; 8592 } 8593 8594 /* 8595 * Use the 8051 to write a LCB CSR. 8596 */ 8597 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data) 8598 { 8599 u32 regno; 8600 int ret; 8601 8602 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || 8603 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) { 8604 if (acquire_lcb_access(dd, 0) == 0) { 8605 write_csr(dd, addr, data); 8606 release_lcb_access(dd, 0); 8607 return 0; 8608 } 8609 return -EBUSY; 8610 } 8611 8612 /* register is an index of LCB registers: (offset - base) / 8 */ 8613 regno = (addr - DC_LCB_CFG_RUN) >> 3; 8614 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data); 8615 if (ret != HCMD_SUCCESS) 8616 return -EBUSY; 8617 return 0; 8618 } 8619 8620 /* 8621 * Write an LCB CSR. Access may not be in host control, so check. 8622 * Return 0 on success, -EBUSY on failure. 8623 */ 8624 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data) 8625 { 8626 struct hfi1_pportdata *ppd = dd->pport; 8627 8628 /* if up, go through the 8051 for the value */ 8629 if (ppd->host_link_state & HLS_UP) 8630 return write_lcb_via_8051(dd, addr, data); 8631 /* if going up or down, no access */ 8632 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) 8633 return -EBUSY; 8634 /* otherwise, host has access */ 8635 write_csr(dd, addr, data); 8636 return 0; 8637 } 8638 8639 /* 8640 * Returns: 8641 * < 0 = Linux error, not able to get access 8642 * > 0 = 8051 command RETURN_CODE 8643 */ 8644 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data, 8645 u64 *out_data) 8646 { 8647 u64 reg, completed; 8648 int return_code; 8649 unsigned long timeout; 8650 8651 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data); 8652 8653 mutex_lock(&dd->dc8051_lock); 8654 8655 /* We can't send any commands to the 8051 if it's in reset */ 8656 if (dd->dc_shutdown) { 8657 return_code = -ENODEV; 8658 goto fail; 8659 } 8660 8661 /* 8662 * If an 8051 host command timed out previously, then the 8051 is 8663 * stuck. 8664 * 8665 * On first timeout, attempt to reset and restart the entire DC 8666 * block (including 8051). (Is this too big of a hammer?) 8667 * 8668 * If the 8051 times out a second time, the reset did not bring it 8669 * back to healthy life. In that case, fail any subsequent commands. 8670 */ 8671 if (dd->dc8051_timed_out) { 8672 if (dd->dc8051_timed_out > 1) { 8673 dd_dev_err(dd, 8674 "Previous 8051 host command timed out, skipping command %u\n", 8675 type); 8676 return_code = -ENXIO; 8677 goto fail; 8678 } 8679 _dc_shutdown(dd); 8680 _dc_start(dd); 8681 } 8682 8683 /* 8684 * If there is no timeout, then the 8051 command interface is 8685 * waiting for a command. 8686 */ 8687 8688 /* 8689 * When writing a LCB CSR, out_data contains the full value to 8690 * to be written, while in_data contains the relative LCB 8691 * address in 7:0. Do the work here, rather than the caller, 8692 * of distrubting the write data to where it needs to go: 8693 * 8694 * Write data 8695 * 39:00 -> in_data[47:8] 8696 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE 8697 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA 8698 */ 8699 if (type == HCMD_WRITE_LCB_CSR) { 8700 in_data |= ((*out_data) & 0xffffffffffull) << 8; 8701 /* must preserve COMPLETED - it is tied to hardware */ 8702 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); 8703 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK; 8704 reg |= ((((*out_data) >> 40) & 0xff) << 8705 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT) 8706 | ((((*out_data) >> 48) & 0xffff) << 8707 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 8708 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); 8709 } 8710 8711 /* 8712 * Do two writes: the first to stabilize the type and req_data, the 8713 * second to activate. 8714 */ 8715 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK) 8716 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8717 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK) 8718 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT; 8719 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8720 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK; 8721 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); 8722 8723 /* wait for completion, alternate: interrupt */ 8724 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT); 8725 while (1) { 8726 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); 8727 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK; 8728 if (completed) 8729 break; 8730 if (time_after(jiffies, timeout)) { 8731 dd->dc8051_timed_out++; 8732 dd_dev_err(dd, "8051 host command %u timeout\n", type); 8733 if (out_data) 8734 *out_data = 0; 8735 return_code = -ETIMEDOUT; 8736 goto fail; 8737 } 8738 udelay(2); 8739 } 8740 8741 if (out_data) { 8742 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT) 8743 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK; 8744 if (type == HCMD_READ_LCB_CSR) { 8745 /* top 16 bits are in a different register */ 8746 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) 8747 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK) 8748 << (48 8749 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT); 8750 } 8751 } 8752 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT) 8753 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK; 8754 dd->dc8051_timed_out = 0; 8755 /* 8756 * Clear command for next user. 8757 */ 8758 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); 8759 8760 fail: 8761 mutex_unlock(&dd->dc8051_lock); 8762 return return_code; 8763 } 8764 8765 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state) 8766 { 8767 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL); 8768 } 8769 8770 int load_8051_config(struct hfi1_devdata *dd, u8 field_id, 8771 u8 lane_id, u32 config_data) 8772 { 8773 u64 data; 8774 int ret; 8775 8776 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT 8777 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT 8778 | (u64)config_data << LOAD_DATA_DATA_SHIFT; 8779 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL); 8780 if (ret != HCMD_SUCCESS) { 8781 dd_dev_err(dd, 8782 "load 8051 config: field id %d, lane %d, err %d\n", 8783 (int)field_id, (int)lane_id, ret); 8784 } 8785 return ret; 8786 } 8787 8788 /* 8789 * Read the 8051 firmware "registers". Use the RAM directly. Always 8790 * set the result, even on error. 8791 * Return 0 on success, -errno on failure 8792 */ 8793 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id, 8794 u32 *result) 8795 { 8796 u64 big_data; 8797 u32 addr; 8798 int ret; 8799 8800 /* address start depends on the lane_id */ 8801 if (lane_id < 4) 8802 addr = (4 * NUM_GENERAL_FIELDS) 8803 + (lane_id * 4 * NUM_LANE_FIELDS); 8804 else 8805 addr = 0; 8806 addr += field_id * 4; 8807 8808 /* read is in 8-byte chunks, hardware will truncate the address down */ 8809 ret = read_8051_data(dd, addr, 8, &big_data); 8810 8811 if (ret == 0) { 8812 /* extract the 4 bytes we want */ 8813 if (addr & 0x4) 8814 *result = (u32)(big_data >> 32); 8815 else 8816 *result = (u32)big_data; 8817 } else { 8818 *result = 0; 8819 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n", 8820 __func__, lane_id, field_id); 8821 } 8822 8823 return ret; 8824 } 8825 8826 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management, 8827 u8 continuous) 8828 { 8829 u32 frame; 8830 8831 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 8832 | power_management << POWER_MANAGEMENT_SHIFT; 8833 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY, 8834 GENERAL_CONFIG, frame); 8835 } 8836 8837 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu, 8838 u16 vl15buf, u8 crc_sizes) 8839 { 8840 u32 frame; 8841 8842 frame = (u32)vau << VAU_SHIFT 8843 | (u32)z << Z_SHIFT 8844 | (u32)vcu << VCU_SHIFT 8845 | (u32)vl15buf << VL15BUF_SHIFT 8846 | (u32)crc_sizes << CRC_SIZES_SHIFT; 8847 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC, 8848 GENERAL_CONFIG, frame); 8849 } 8850 8851 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits, 8852 u8 *flag_bits, u16 *link_widths) 8853 { 8854 u32 frame; 8855 8856 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8857 &frame); 8858 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK; 8859 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK; 8860 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8861 } 8862 8863 static int write_vc_local_link_mode(struct hfi1_devdata *dd, 8864 u8 misc_bits, 8865 u8 flag_bits, 8866 u16 link_widths) 8867 { 8868 u32 frame; 8869 8870 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT 8871 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT 8872 | (u32)link_widths << LINK_WIDTH_SHIFT; 8873 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG, 8874 frame); 8875 } 8876 8877 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id, 8878 u8 device_rev) 8879 { 8880 u32 frame; 8881 8882 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT) 8883 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT); 8884 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame); 8885 } 8886 8887 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 8888 u8 *device_rev) 8889 { 8890 u32 frame; 8891 8892 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame); 8893 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK; 8894 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT) 8895 & REMOTE_DEVICE_REV_MASK; 8896 } 8897 8898 int write_host_interface_version(struct hfi1_devdata *dd, u8 version) 8899 { 8900 u32 frame; 8901 u32 mask; 8902 8903 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); 8904 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame); 8905 /* Clear, then set field */ 8906 frame &= ~mask; 8907 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT); 8908 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, 8909 frame); 8910 } 8911 8912 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 8913 u8 *ver_patch) 8914 { 8915 u32 frame; 8916 8917 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame); 8918 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) & 8919 STS_FM_VERSION_MAJOR_MASK; 8920 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) & 8921 STS_FM_VERSION_MINOR_MASK; 8922 8923 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame); 8924 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) & 8925 STS_FM_VERSION_PATCH_MASK; 8926 } 8927 8928 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management, 8929 u8 *continuous) 8930 { 8931 u32 frame; 8932 8933 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame); 8934 *power_management = (frame >> POWER_MANAGEMENT_SHIFT) 8935 & POWER_MANAGEMENT_MASK; 8936 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT) 8937 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK; 8938 } 8939 8940 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z, 8941 u8 *vcu, u16 *vl15buf, u8 *crc_sizes) 8942 { 8943 u32 frame; 8944 8945 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame); 8946 *vau = (frame >> VAU_SHIFT) & VAU_MASK; 8947 *z = (frame >> Z_SHIFT) & Z_MASK; 8948 *vcu = (frame >> VCU_SHIFT) & VCU_MASK; 8949 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK; 8950 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK; 8951 } 8952 8953 static void read_vc_remote_link_width(struct hfi1_devdata *dd, 8954 u8 *remote_tx_rate, 8955 u16 *link_widths) 8956 { 8957 u32 frame; 8958 8959 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG, 8960 &frame); 8961 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT) 8962 & REMOTE_TX_RATE_MASK; 8963 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK; 8964 } 8965 8966 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx) 8967 { 8968 u32 frame; 8969 8970 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame); 8971 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK; 8972 } 8973 8974 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls) 8975 { 8976 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls); 8977 } 8978 8979 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs) 8980 { 8981 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs); 8982 } 8983 8984 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality) 8985 { 8986 u32 frame; 8987 int ret; 8988 8989 *link_quality = 0; 8990 if (dd->pport->host_link_state & HLS_UP) { 8991 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, 8992 &frame); 8993 if (ret == 0) 8994 *link_quality = (frame >> LINK_QUALITY_SHIFT) 8995 & LINK_QUALITY_MASK; 8996 } 8997 } 8998 8999 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc) 9000 { 9001 u32 frame; 9002 9003 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame); 9004 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK; 9005 } 9006 9007 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr) 9008 { 9009 u32 frame; 9010 9011 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame); 9012 *ldr = (frame & 0xff); 9013 } 9014 9015 static int read_tx_settings(struct hfi1_devdata *dd, 9016 u8 *enable_lane_tx, 9017 u8 *tx_polarity_inversion, 9018 u8 *rx_polarity_inversion, 9019 u8 *max_rate) 9020 { 9021 u32 frame; 9022 int ret; 9023 9024 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame); 9025 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT) 9026 & ENABLE_LANE_TX_MASK; 9027 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT) 9028 & TX_POLARITY_INVERSION_MASK; 9029 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT) 9030 & RX_POLARITY_INVERSION_MASK; 9031 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK; 9032 return ret; 9033 } 9034 9035 static int write_tx_settings(struct hfi1_devdata *dd, 9036 u8 enable_lane_tx, 9037 u8 tx_polarity_inversion, 9038 u8 rx_polarity_inversion, 9039 u8 max_rate) 9040 { 9041 u32 frame; 9042 9043 /* no need to mask, all variable sizes match field widths */ 9044 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT 9045 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT 9046 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT 9047 | max_rate << MAX_RATE_SHIFT; 9048 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame); 9049 } 9050 9051 /* 9052 * Read an idle LCB message. 9053 * 9054 * Returns 0 on success, -EINVAL on error 9055 */ 9056 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out) 9057 { 9058 int ret; 9059 9060 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out); 9061 if (ret != HCMD_SUCCESS) { 9062 dd_dev_err(dd, "read idle message: type %d, err %d\n", 9063 (u32)type, ret); 9064 return -EINVAL; 9065 } 9066 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out); 9067 /* return only the payload as we already know the type */ 9068 *data_out >>= IDLE_PAYLOAD_SHIFT; 9069 return 0; 9070 } 9071 9072 /* 9073 * Read an idle SMA message. To be done in response to a notification from 9074 * the 8051. 9075 * 9076 * Returns 0 on success, -EINVAL on error 9077 */ 9078 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data) 9079 { 9080 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT, 9081 data); 9082 } 9083 9084 /* 9085 * Send an idle LCB message. 9086 * 9087 * Returns 0 on success, -EINVAL on error 9088 */ 9089 static int send_idle_message(struct hfi1_devdata *dd, u64 data) 9090 { 9091 int ret; 9092 9093 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data); 9094 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL); 9095 if (ret != HCMD_SUCCESS) { 9096 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n", 9097 data, ret); 9098 return -EINVAL; 9099 } 9100 return 0; 9101 } 9102 9103 /* 9104 * Send an idle SMA message. 9105 * 9106 * Returns 0 on success, -EINVAL on error 9107 */ 9108 int send_idle_sma(struct hfi1_devdata *dd, u64 message) 9109 { 9110 u64 data; 9111 9112 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) | 9113 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT); 9114 return send_idle_message(dd, data); 9115 } 9116 9117 /* 9118 * Initialize the LCB then do a quick link up. This may or may not be 9119 * in loopback. 9120 * 9121 * return 0 on success, -errno on error 9122 */ 9123 static int do_quick_linkup(struct hfi1_devdata *dd) 9124 { 9125 int ret; 9126 9127 lcb_shutdown(dd, 0); 9128 9129 if (loopback) { 9130 /* LCB_CFG_LOOPBACK.VAL = 2 */ 9131 /* LCB_CFG_LANE_WIDTH.VAL = 0 */ 9132 write_csr(dd, DC_LCB_CFG_LOOPBACK, 9133 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT); 9134 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 9135 } 9136 9137 /* start the LCBs */ 9138 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */ 9139 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 9140 9141 /* simulator only loopback steps */ 9142 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 9143 /* LCB_CFG_RUN.EN = 1 */ 9144 write_csr(dd, DC_LCB_CFG_RUN, 9145 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 9146 9147 ret = wait_link_transfer_active(dd, 10); 9148 if (ret) 9149 return ret; 9150 9151 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 9152 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT); 9153 } 9154 9155 if (!loopback) { 9156 /* 9157 * When doing quick linkup and not in loopback, both 9158 * sides must be done with LCB set-up before either 9159 * starts the quick linkup. Put a delay here so that 9160 * both sides can be started and have a chance to be 9161 * done with LCB set up before resuming. 9162 */ 9163 dd_dev_err(dd, 9164 "Pausing for peer to be finished with LCB set up\n"); 9165 msleep(5000); 9166 dd_dev_err(dd, "Continuing with quick linkup\n"); 9167 } 9168 9169 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 9170 set_8051_lcb_access(dd); 9171 9172 /* 9173 * State "quick" LinkUp request sets the physical link state to 9174 * LinkUp without a verify capability sequence. 9175 * This state is in simulator v37 and later. 9176 */ 9177 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP); 9178 if (ret != HCMD_SUCCESS) { 9179 dd_dev_err(dd, 9180 "%s: set physical link state to quick LinkUp failed with return %d\n", 9181 __func__, ret); 9182 9183 set_host_lcb_access(dd); 9184 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 9185 9186 if (ret >= 0) 9187 ret = -EINVAL; 9188 return ret; 9189 } 9190 9191 return 0; /* success */ 9192 } 9193 9194 /* 9195 * Do all special steps to set up loopback. 9196 */ 9197 static int init_loopback(struct hfi1_devdata *dd) 9198 { 9199 dd_dev_info(dd, "Entering loopback mode\n"); 9200 9201 /* all loopbacks should disable self GUID check */ 9202 write_csr(dd, DC_DC8051_CFG_MODE, 9203 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); 9204 9205 /* 9206 * The simulator has only one loopback option - LCB. Switch 9207 * to that option, which includes quick link up. 9208 * 9209 * Accept all valid loopback values. 9210 */ 9211 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) && 9212 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB || 9213 loopback == LOOPBACK_CABLE)) { 9214 loopback = LOOPBACK_LCB; 9215 quick_linkup = 1; 9216 return 0; 9217 } 9218 9219 /* 9220 * SerDes loopback init sequence is handled in set_local_link_attributes 9221 */ 9222 if (loopback == LOOPBACK_SERDES) 9223 return 0; 9224 9225 /* LCB loopback - handled at poll time */ 9226 if (loopback == LOOPBACK_LCB) { 9227 quick_linkup = 1; /* LCB is always quick linkup */ 9228 9229 /* not supported in emulation due to emulation RTL changes */ 9230 if (dd->icode == ICODE_FPGA_EMULATION) { 9231 dd_dev_err(dd, 9232 "LCB loopback not supported in emulation\n"); 9233 return -EINVAL; 9234 } 9235 return 0; 9236 } 9237 9238 /* external cable loopback requires no extra steps */ 9239 if (loopback == LOOPBACK_CABLE) 9240 return 0; 9241 9242 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback); 9243 return -EINVAL; 9244 } 9245 9246 /* 9247 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits 9248 * used in the Verify Capability link width attribute. 9249 */ 9250 static u16 opa_to_vc_link_widths(u16 opa_widths) 9251 { 9252 int i; 9253 u16 result = 0; 9254 9255 static const struct link_bits { 9256 u16 from; 9257 u16 to; 9258 } opa_link_xlate[] = { 9259 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) }, 9260 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) }, 9261 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) }, 9262 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) }, 9263 }; 9264 9265 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) { 9266 if (opa_widths & opa_link_xlate[i].from) 9267 result |= opa_link_xlate[i].to; 9268 } 9269 return result; 9270 } 9271 9272 /* 9273 * Set link attributes before moving to polling. 9274 */ 9275 static int set_local_link_attributes(struct hfi1_pportdata *ppd) 9276 { 9277 struct hfi1_devdata *dd = ppd->dd; 9278 u8 enable_lane_tx; 9279 u8 tx_polarity_inversion; 9280 u8 rx_polarity_inversion; 9281 int ret; 9282 u32 misc_bits = 0; 9283 /* reset our fabric serdes to clear any lingering problems */ 9284 fabric_serdes_reset(dd); 9285 9286 /* set the local tx rate - need to read-modify-write */ 9287 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion, 9288 &rx_polarity_inversion, &ppd->local_tx_rate); 9289 if (ret) 9290 goto set_local_link_attributes_fail; 9291 9292 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) { 9293 /* set the tx rate to the fastest enabled */ 9294 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9295 ppd->local_tx_rate = 1; 9296 else 9297 ppd->local_tx_rate = 0; 9298 } else { 9299 /* set the tx rate to all enabled */ 9300 ppd->local_tx_rate = 0; 9301 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G) 9302 ppd->local_tx_rate |= 2; 9303 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G) 9304 ppd->local_tx_rate |= 1; 9305 } 9306 9307 enable_lane_tx = 0xF; /* enable all four lanes */ 9308 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion, 9309 rx_polarity_inversion, ppd->local_tx_rate); 9310 if (ret != HCMD_SUCCESS) 9311 goto set_local_link_attributes_fail; 9312 9313 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION); 9314 if (ret != HCMD_SUCCESS) { 9315 dd_dev_err(dd, 9316 "Failed to set host interface version, return 0x%x\n", 9317 ret); 9318 goto set_local_link_attributes_fail; 9319 } 9320 9321 /* 9322 * DC supports continuous updates. 9323 */ 9324 ret = write_vc_local_phy(dd, 9325 0 /* no power management */, 9326 1 /* continuous updates */); 9327 if (ret != HCMD_SUCCESS) 9328 goto set_local_link_attributes_fail; 9329 9330 /* z=1 in the next call: AU of 0 is not supported by the hardware */ 9331 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init, 9332 ppd->port_crc_mode_enabled); 9333 if (ret != HCMD_SUCCESS) 9334 goto set_local_link_attributes_fail; 9335 9336 /* 9337 * SerDes loopback init sequence requires 9338 * setting bit 0 of MISC_CONFIG_BITS 9339 */ 9340 if (loopback == LOOPBACK_SERDES) 9341 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT; 9342 9343 /* 9344 * An external device configuration request is used to reset the LCB 9345 * to retry to obtain operational lanes when the first attempt is 9346 * unsuccesful. 9347 */ 9348 if (dd->dc8051_ver >= dc8051_ver(1, 25, 0)) 9349 misc_bits |= 1 << EXT_CFG_LCB_RESET_SUPPORTED_SHIFT; 9350 9351 ret = write_vc_local_link_mode(dd, misc_bits, 0, 9352 opa_to_vc_link_widths( 9353 ppd->link_width_enabled)); 9354 if (ret != HCMD_SUCCESS) 9355 goto set_local_link_attributes_fail; 9356 9357 /* let peer know who we are */ 9358 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev); 9359 if (ret == HCMD_SUCCESS) 9360 return 0; 9361 9362 set_local_link_attributes_fail: 9363 dd_dev_err(dd, 9364 "Failed to set local link attributes, return 0x%x\n", 9365 ret); 9366 return ret; 9367 } 9368 9369 /* 9370 * Call this to start the link. 9371 * Do not do anything if the link is disabled. 9372 * Returns 0 if link is disabled, moved to polling, or the driver is not ready. 9373 */ 9374 int start_link(struct hfi1_pportdata *ppd) 9375 { 9376 /* 9377 * Tune the SerDes to a ballpark setting for optimal signal and bit 9378 * error rate. Needs to be done before starting the link. 9379 */ 9380 tune_serdes(ppd); 9381 9382 if (!ppd->driver_link_ready) { 9383 dd_dev_info(ppd->dd, 9384 "%s: stopping link start because driver is not ready\n", 9385 __func__); 9386 return 0; 9387 } 9388 9389 /* 9390 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the 9391 * pkey table can be configured properly if the HFI unit is connected 9392 * to switch port with MgmtAllowed=NO 9393 */ 9394 clear_full_mgmt_pkey(ppd); 9395 9396 return set_link_state(ppd, HLS_DN_POLL); 9397 } 9398 9399 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd) 9400 { 9401 struct hfi1_devdata *dd = ppd->dd; 9402 u64 mask; 9403 unsigned long timeout; 9404 9405 /* 9406 * Some QSFP cables have a quirk that asserts the IntN line as a side 9407 * effect of power up on plug-in. We ignore this false positive 9408 * interrupt until the module has finished powering up by waiting for 9409 * a minimum timeout of the module inrush initialization time of 9410 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the 9411 * module have stabilized. 9412 */ 9413 msleep(500); 9414 9415 /* 9416 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1) 9417 */ 9418 timeout = jiffies + msecs_to_jiffies(2000); 9419 while (1) { 9420 mask = read_csr(dd, dd->hfi1_id ? 9421 ASIC_QSFP2_IN : ASIC_QSFP1_IN); 9422 if (!(mask & QSFP_HFI0_INT_N)) 9423 break; 9424 if (time_after(jiffies, timeout)) { 9425 dd_dev_info(dd, "%s: No IntN detected, reset complete\n", 9426 __func__); 9427 break; 9428 } 9429 udelay(2); 9430 } 9431 } 9432 9433 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable) 9434 { 9435 struct hfi1_devdata *dd = ppd->dd; 9436 u64 mask; 9437 9438 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); 9439 if (enable) { 9440 /* 9441 * Clear the status register to avoid an immediate interrupt 9442 * when we re-enable the IntN pin 9443 */ 9444 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9445 QSFP_HFI0_INT_N); 9446 mask |= (u64)QSFP_HFI0_INT_N; 9447 } else { 9448 mask &= ~(u64)QSFP_HFI0_INT_N; 9449 } 9450 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); 9451 } 9452 9453 int reset_qsfp(struct hfi1_pportdata *ppd) 9454 { 9455 struct hfi1_devdata *dd = ppd->dd; 9456 u64 mask, qsfp_mask; 9457 9458 /* Disable INT_N from triggering QSFP interrupts */ 9459 set_qsfp_int_n(ppd, 0); 9460 9461 /* Reset the QSFP */ 9462 mask = (u64)QSFP_HFI0_RESET_N; 9463 9464 qsfp_mask = read_csr(dd, 9465 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT); 9466 qsfp_mask &= ~mask; 9467 write_csr(dd, 9468 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9469 9470 udelay(10); 9471 9472 qsfp_mask |= mask; 9473 write_csr(dd, 9474 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask); 9475 9476 wait_for_qsfp_init(ppd); 9477 9478 /* 9479 * Allow INT_N to trigger the QSFP interrupt to watch 9480 * for alarms and warnings 9481 */ 9482 set_qsfp_int_n(ppd, 1); 9483 9484 /* 9485 * After the reset, AOC transmitters are enabled by default. They need 9486 * to be turned off to complete the QSFP setup before they can be 9487 * enabled again. 9488 */ 9489 return set_qsfp_tx(ppd, 0); 9490 } 9491 9492 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd, 9493 u8 *qsfp_interrupt_status) 9494 { 9495 struct hfi1_devdata *dd = ppd->dd; 9496 9497 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) || 9498 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING)) 9499 dd_dev_err(dd, "%s: QSFP cable temperature too high\n", 9500 __func__); 9501 9502 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) || 9503 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING)) 9504 dd_dev_err(dd, "%s: QSFP cable temperature too low\n", 9505 __func__); 9506 9507 /* 9508 * The remaining alarms/warnings don't matter if the link is down. 9509 */ 9510 if (ppd->host_link_state & HLS_DOWN) 9511 return 0; 9512 9513 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) || 9514 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING)) 9515 dd_dev_err(dd, "%s: QSFP supply voltage too high\n", 9516 __func__); 9517 9518 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) || 9519 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING)) 9520 dd_dev_err(dd, "%s: QSFP supply voltage too low\n", 9521 __func__); 9522 9523 /* Byte 2 is vendor specific */ 9524 9525 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) || 9526 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING)) 9527 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n", 9528 __func__); 9529 9530 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) || 9531 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING)) 9532 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n", 9533 __func__); 9534 9535 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) || 9536 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING)) 9537 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n", 9538 __func__); 9539 9540 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) || 9541 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING)) 9542 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n", 9543 __func__); 9544 9545 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) || 9546 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING)) 9547 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n", 9548 __func__); 9549 9550 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) || 9551 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING)) 9552 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n", 9553 __func__); 9554 9555 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) || 9556 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING)) 9557 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n", 9558 __func__); 9559 9560 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) || 9561 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING)) 9562 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n", 9563 __func__); 9564 9565 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) || 9566 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING)) 9567 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n", 9568 __func__); 9569 9570 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) || 9571 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING)) 9572 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n", 9573 __func__); 9574 9575 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) || 9576 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING)) 9577 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n", 9578 __func__); 9579 9580 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) || 9581 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING)) 9582 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n", 9583 __func__); 9584 9585 /* Bytes 9-10 and 11-12 are reserved */ 9586 /* Bytes 13-15 are vendor specific */ 9587 9588 return 0; 9589 } 9590 9591 /* This routine will only be scheduled if the QSFP module present is asserted */ 9592 void qsfp_event(struct work_struct *work) 9593 { 9594 struct qsfp_data *qd; 9595 struct hfi1_pportdata *ppd; 9596 struct hfi1_devdata *dd; 9597 9598 qd = container_of(work, struct qsfp_data, qsfp_work); 9599 ppd = qd->ppd; 9600 dd = ppd->dd; 9601 9602 /* Sanity check */ 9603 if (!qsfp_mod_present(ppd)) 9604 return; 9605 9606 if (ppd->host_link_state == HLS_DN_DISABLE) { 9607 dd_dev_info(ppd->dd, 9608 "%s: stopping link start because link is disabled\n", 9609 __func__); 9610 return; 9611 } 9612 9613 /* 9614 * Turn DC back on after cable has been re-inserted. Up until 9615 * now, the DC has been in reset to save power. 9616 */ 9617 dc_start(dd); 9618 9619 if (qd->cache_refresh_required) { 9620 set_qsfp_int_n(ppd, 0); 9621 9622 wait_for_qsfp_init(ppd); 9623 9624 /* 9625 * Allow INT_N to trigger the QSFP interrupt to watch 9626 * for alarms and warnings 9627 */ 9628 set_qsfp_int_n(ppd, 1); 9629 9630 start_link(ppd); 9631 } 9632 9633 if (qd->check_interrupt_flags) { 9634 u8 qsfp_interrupt_status[16] = {0,}; 9635 9636 if (one_qsfp_read(ppd, dd->hfi1_id, 6, 9637 &qsfp_interrupt_status[0], 16) != 16) { 9638 dd_dev_info(dd, 9639 "%s: Failed to read status of QSFP module\n", 9640 __func__); 9641 } else { 9642 unsigned long flags; 9643 9644 handle_qsfp_error_conditions( 9645 ppd, qsfp_interrupt_status); 9646 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags); 9647 ppd->qsfp_info.check_interrupt_flags = 0; 9648 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, 9649 flags); 9650 } 9651 } 9652 } 9653 9654 void init_qsfp_int(struct hfi1_devdata *dd) 9655 { 9656 struct hfi1_pportdata *ppd = dd->pport; 9657 u64 qsfp_mask; 9658 9659 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N); 9660 /* Clear current status to avoid spurious interrupts */ 9661 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, 9662 qsfp_mask); 9663 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, 9664 qsfp_mask); 9665 9666 set_qsfp_int_n(ppd, 0); 9667 9668 /* Handle active low nature of INT_N and MODPRST_N pins */ 9669 if (qsfp_mod_present(ppd)) 9670 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N; 9671 write_csr(dd, 9672 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT, 9673 qsfp_mask); 9674 9675 /* Enable the appropriate QSFP IRQ source */ 9676 if (!dd->hfi1_id) 9677 set_intr_bits(dd, QSFP1_INT, QSFP1_INT, true); 9678 else 9679 set_intr_bits(dd, QSFP2_INT, QSFP2_INT, true); 9680 } 9681 9682 /* 9683 * Do a one-time initialize of the LCB block. 9684 */ 9685 static void init_lcb(struct hfi1_devdata *dd) 9686 { 9687 /* simulator does not correctly handle LCB cclk loopback, skip */ 9688 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 9689 return; 9690 9691 /* the DC has been reset earlier in the driver load */ 9692 9693 /* set LCB for cclk loopback on the port */ 9694 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); 9695 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); 9696 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); 9697 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 9698 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); 9699 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); 9700 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); 9701 } 9702 9703 /* 9704 * Perform a test read on the QSFP. Return 0 on success, -ERRNO 9705 * on error. 9706 */ 9707 static int test_qsfp_read(struct hfi1_pportdata *ppd) 9708 { 9709 int ret; 9710 u8 status; 9711 9712 /* 9713 * Report success if not a QSFP or, if it is a QSFP, but the cable is 9714 * not present 9715 */ 9716 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd)) 9717 return 0; 9718 9719 /* read byte 2, the status byte */ 9720 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1); 9721 if (ret < 0) 9722 return ret; 9723 if (ret != 1) 9724 return -EIO; 9725 9726 return 0; /* success */ 9727 } 9728 9729 /* 9730 * Values for QSFP retry. 9731 * 9732 * Give up after 10s (20 x 500ms). The overall timeout was empirically 9733 * arrived at from experience on a large cluster. 9734 */ 9735 #define MAX_QSFP_RETRIES 20 9736 #define QSFP_RETRY_WAIT 500 /* msec */ 9737 9738 /* 9739 * Try a QSFP read. If it fails, schedule a retry for later. 9740 * Called on first link activation after driver load. 9741 */ 9742 static void try_start_link(struct hfi1_pportdata *ppd) 9743 { 9744 if (test_qsfp_read(ppd)) { 9745 /* read failed */ 9746 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) { 9747 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n"); 9748 return; 9749 } 9750 dd_dev_info(ppd->dd, 9751 "QSFP not responding, waiting and retrying %d\n", 9752 (int)ppd->qsfp_retry_count); 9753 ppd->qsfp_retry_count++; 9754 queue_delayed_work(ppd->link_wq, &ppd->start_link_work, 9755 msecs_to_jiffies(QSFP_RETRY_WAIT)); 9756 return; 9757 } 9758 ppd->qsfp_retry_count = 0; 9759 9760 start_link(ppd); 9761 } 9762 9763 /* 9764 * Workqueue function to start the link after a delay. 9765 */ 9766 void handle_start_link(struct work_struct *work) 9767 { 9768 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata, 9769 start_link_work.work); 9770 try_start_link(ppd); 9771 } 9772 9773 int bringup_serdes(struct hfi1_pportdata *ppd) 9774 { 9775 struct hfi1_devdata *dd = ppd->dd; 9776 u64 guid; 9777 int ret; 9778 9779 if (HFI1_CAP_IS_KSET(EXTENDED_PSN)) 9780 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK); 9781 9782 guid = ppd->guids[HFI1_PORT_GUID_INDEX]; 9783 if (!guid) { 9784 if (dd->base_guid) 9785 guid = dd->base_guid + ppd->port - 1; 9786 ppd->guids[HFI1_PORT_GUID_INDEX] = guid; 9787 } 9788 9789 /* Set linkinit_reason on power up per OPA spec */ 9790 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP; 9791 9792 /* one-time init of the LCB */ 9793 init_lcb(dd); 9794 9795 if (loopback) { 9796 ret = init_loopback(dd); 9797 if (ret < 0) 9798 return ret; 9799 } 9800 9801 get_port_type(ppd); 9802 if (ppd->port_type == PORT_TYPE_QSFP) { 9803 set_qsfp_int_n(ppd, 0); 9804 wait_for_qsfp_init(ppd); 9805 set_qsfp_int_n(ppd, 1); 9806 } 9807 9808 try_start_link(ppd); 9809 return 0; 9810 } 9811 9812 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd) 9813 { 9814 struct hfi1_devdata *dd = ppd->dd; 9815 9816 /* 9817 * Shut down the link and keep it down. First turn off that the 9818 * driver wants to allow the link to be up (driver_link_ready). 9819 * Then make sure the link is not automatically restarted 9820 * (link_enabled). Cancel any pending restart. And finally 9821 * go offline. 9822 */ 9823 ppd->driver_link_ready = 0; 9824 ppd->link_enabled = 0; 9825 9826 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */ 9827 flush_delayed_work(&ppd->start_link_work); 9828 cancel_delayed_work_sync(&ppd->start_link_work); 9829 9830 ppd->offline_disabled_reason = 9831 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT); 9832 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0, 9833 OPA_LINKDOWN_REASON_REBOOT); 9834 set_link_state(ppd, HLS_DN_OFFLINE); 9835 9836 /* disable the port */ 9837 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 9838 } 9839 9840 static inline int init_cpu_counters(struct hfi1_devdata *dd) 9841 { 9842 struct hfi1_pportdata *ppd; 9843 int i; 9844 9845 ppd = (struct hfi1_pportdata *)(dd + 1); 9846 for (i = 0; i < dd->num_pports; i++, ppd++) { 9847 ppd->ibport_data.rvp.rc_acks = NULL; 9848 ppd->ibport_data.rvp.rc_qacks = NULL; 9849 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64); 9850 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64); 9851 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64); 9852 if (!ppd->ibport_data.rvp.rc_acks || 9853 !ppd->ibport_data.rvp.rc_delayed_comp || 9854 !ppd->ibport_data.rvp.rc_qacks) 9855 return -ENOMEM; 9856 } 9857 9858 return 0; 9859 } 9860 9861 /* 9862 * index is the index into the receive array 9863 */ 9864 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, 9865 u32 type, unsigned long pa, u16 order) 9866 { 9867 u64 reg; 9868 9869 if (!(dd->flags & HFI1_PRESENT)) 9870 goto done; 9871 9872 if (type == PT_INVALID || type == PT_INVALID_FLUSH) { 9873 pa = 0; 9874 order = 0; 9875 } else if (type > PT_INVALID) { 9876 dd_dev_err(dd, 9877 "unexpected receive array type %u for index %u, not handled\n", 9878 type, index); 9879 goto done; 9880 } 9881 trace_hfi1_put_tid(dd, index, type, pa, order); 9882 9883 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */ 9884 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK 9885 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT 9886 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK) 9887 << RCV_ARRAY_RT_ADDR_SHIFT; 9888 trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg); 9889 writeq(reg, dd->rcvarray_wc + (index * 8)); 9890 9891 if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3) 9892 /* 9893 * Eager entries are written and flushed 9894 * 9895 * Expected entries are flushed every 4 writes 9896 */ 9897 flush_wc(); 9898 done: 9899 return; 9900 } 9901 9902 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd) 9903 { 9904 struct hfi1_devdata *dd = rcd->dd; 9905 u32 i; 9906 9907 /* this could be optimized */ 9908 for (i = rcd->eager_base; i < rcd->eager_base + 9909 rcd->egrbufs.alloced; i++) 9910 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 9911 9912 for (i = rcd->expected_base; 9913 i < rcd->expected_base + rcd->expected_count; i++) 9914 hfi1_put_tid(dd, i, PT_INVALID, 0, 0); 9915 } 9916 9917 static const char * const ib_cfg_name_strings[] = { 9918 "HFI1_IB_CFG_LIDLMC", 9919 "HFI1_IB_CFG_LWID_DG_ENB", 9920 "HFI1_IB_CFG_LWID_ENB", 9921 "HFI1_IB_CFG_LWID", 9922 "HFI1_IB_CFG_SPD_ENB", 9923 "HFI1_IB_CFG_SPD", 9924 "HFI1_IB_CFG_RXPOL_ENB", 9925 "HFI1_IB_CFG_LREV_ENB", 9926 "HFI1_IB_CFG_LINKLATENCY", 9927 "HFI1_IB_CFG_HRTBT", 9928 "HFI1_IB_CFG_OP_VLS", 9929 "HFI1_IB_CFG_VL_HIGH_CAP", 9930 "HFI1_IB_CFG_VL_LOW_CAP", 9931 "HFI1_IB_CFG_OVERRUN_THRESH", 9932 "HFI1_IB_CFG_PHYERR_THRESH", 9933 "HFI1_IB_CFG_LINKDEFAULT", 9934 "HFI1_IB_CFG_PKEYS", 9935 "HFI1_IB_CFG_MTU", 9936 "HFI1_IB_CFG_LSTATE", 9937 "HFI1_IB_CFG_VL_HIGH_LIMIT", 9938 "HFI1_IB_CFG_PMA_TICKS", 9939 "HFI1_IB_CFG_PORT" 9940 }; 9941 9942 static const char *ib_cfg_name(int which) 9943 { 9944 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings)) 9945 return "invalid"; 9946 return ib_cfg_name_strings[which]; 9947 } 9948 9949 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which) 9950 { 9951 struct hfi1_devdata *dd = ppd->dd; 9952 int val = 0; 9953 9954 switch (which) { 9955 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */ 9956 val = ppd->link_width_enabled; 9957 break; 9958 case HFI1_IB_CFG_LWID: /* currently active Link-width */ 9959 val = ppd->link_width_active; 9960 break; 9961 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 9962 val = ppd->link_speed_enabled; 9963 break; 9964 case HFI1_IB_CFG_SPD: /* current Link speed */ 9965 val = ppd->link_speed_active; 9966 break; 9967 9968 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */ 9969 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */ 9970 case HFI1_IB_CFG_LINKLATENCY: 9971 goto unimplemented; 9972 9973 case HFI1_IB_CFG_OP_VLS: 9974 val = ppd->actual_vls_operational; 9975 break; 9976 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */ 9977 val = VL_ARB_HIGH_PRIO_TABLE_SIZE; 9978 break; 9979 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */ 9980 val = VL_ARB_LOW_PRIO_TABLE_SIZE; 9981 break; 9982 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 9983 val = ppd->overrun_threshold; 9984 break; 9985 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 9986 val = ppd->phy_error_threshold; 9987 break; 9988 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 9989 val = HLS_DEFAULT; 9990 break; 9991 9992 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */ 9993 case HFI1_IB_CFG_PMA_TICKS: 9994 default: 9995 unimplemented: 9996 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 9997 dd_dev_info( 9998 dd, 9999 "%s: which %s: not implemented\n", 10000 __func__, 10001 ib_cfg_name(which)); 10002 break; 10003 } 10004 10005 return val; 10006 } 10007 10008 /* 10009 * The largest MAD packet size. 10010 */ 10011 #define MAX_MAD_PACKET 2048 10012 10013 /* 10014 * Return the maximum header bytes that can go on the _wire_ 10015 * for this device. This count includes the ICRC which is 10016 * not part of the packet held in memory but it is appended 10017 * by the HW. 10018 * This is dependent on the device's receive header entry size. 10019 * HFI allows this to be set per-receive context, but the 10020 * driver presently enforces a global value. 10021 */ 10022 u32 lrh_max_header_bytes(struct hfi1_devdata *dd) 10023 { 10024 /* 10025 * The maximum non-payload (MTU) bytes in LRH.PktLen are 10026 * the Receive Header Entry Size minus the PBC (or RHF) size 10027 * plus one DW for the ICRC appended by HW. 10028 * 10029 * dd->rcd[0].rcvhdrqentsize is in DW. 10030 * We use rcd[0] as all context will have the same value. Also, 10031 * the first kernel context would have been allocated by now so 10032 * we are guaranteed a valid value. 10033 */ 10034 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2; 10035 } 10036 10037 /* 10038 * Set Send Length 10039 * @ppd - per port data 10040 * 10041 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck* 10042 * registers compare against LRH.PktLen, so use the max bytes included 10043 * in the LRH. 10044 * 10045 * This routine changes all VL values except VL15, which it maintains at 10046 * the same value. 10047 */ 10048 static void set_send_length(struct hfi1_pportdata *ppd) 10049 { 10050 struct hfi1_devdata *dd = ppd->dd; 10051 u32 max_hb = lrh_max_header_bytes(dd), dcmtu; 10052 u32 maxvlmtu = dd->vld[15].mtu; 10053 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2) 10054 & SEND_LEN_CHECK1_LEN_VL15_MASK) << 10055 SEND_LEN_CHECK1_LEN_VL15_SHIFT; 10056 int i, j; 10057 u32 thres; 10058 10059 for (i = 0; i < ppd->vls_supported; i++) { 10060 if (dd->vld[i].mtu > maxvlmtu) 10061 maxvlmtu = dd->vld[i].mtu; 10062 if (i <= 3) 10063 len1 |= (((dd->vld[i].mtu + max_hb) >> 2) 10064 & SEND_LEN_CHECK0_LEN_VL0_MASK) << 10065 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT); 10066 else 10067 len2 |= (((dd->vld[i].mtu + max_hb) >> 2) 10068 & SEND_LEN_CHECK1_LEN_VL4_MASK) << 10069 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT); 10070 } 10071 write_csr(dd, SEND_LEN_CHECK0, len1); 10072 write_csr(dd, SEND_LEN_CHECK1, len2); 10073 /* adjust kernel credit return thresholds based on new MTUs */ 10074 /* all kernel receive contexts have the same hdrqentsize */ 10075 for (i = 0; i < ppd->vls_supported; i++) { 10076 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50), 10077 sc_mtu_to_threshold(dd->vld[i].sc, 10078 dd->vld[i].mtu, 10079 dd->rcd[0]->rcvhdrqentsize)); 10080 for (j = 0; j < INIT_SC_PER_VL; j++) 10081 sc_set_cr_threshold( 10082 pio_select_send_context_vl(dd, j, i), 10083 thres); 10084 } 10085 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50), 10086 sc_mtu_to_threshold(dd->vld[15].sc, 10087 dd->vld[15].mtu, 10088 dd->rcd[0]->rcvhdrqentsize)); 10089 sc_set_cr_threshold(dd->vld[15].sc, thres); 10090 10091 /* Adjust maximum MTU for the port in DC */ 10092 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 : 10093 (ilog2(maxvlmtu >> 8) + 1); 10094 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); 10095 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK; 10096 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) << 10097 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT; 10098 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); 10099 } 10100 10101 static void set_lidlmc(struct hfi1_pportdata *ppd) 10102 { 10103 int i; 10104 u64 sreg = 0; 10105 struct hfi1_devdata *dd = ppd->dd; 10106 u32 mask = ~((1U << ppd->lmc) - 1); 10107 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); 10108 u32 lid; 10109 10110 /* 10111 * Program 0 in CSR if port lid is extended. This prevents 10112 * 9B packets being sent out for large lids. 10113 */ 10114 lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid; 10115 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 10116 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK); 10117 c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK) 10118 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) | 10119 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK) 10120 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT); 10121 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); 10122 10123 /* 10124 * Iterate over all the send contexts and set their SLID check 10125 */ 10126 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) << 10127 SEND_CTXT_CHECK_SLID_MASK_SHIFT) | 10128 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) << 10129 SEND_CTXT_CHECK_SLID_VALUE_SHIFT); 10130 10131 for (i = 0; i < chip_send_contexts(dd); i++) { 10132 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x", 10133 i, (u32)sreg); 10134 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg); 10135 } 10136 10137 /* Now we have to do the same thing for the sdma engines */ 10138 sdma_update_lmc(dd, mask, lid); 10139 } 10140 10141 static const char *state_completed_string(u32 completed) 10142 { 10143 static const char * const state_completed[] = { 10144 "EstablishComm", 10145 "OptimizeEQ", 10146 "VerifyCap" 10147 }; 10148 10149 if (completed < ARRAY_SIZE(state_completed)) 10150 return state_completed[completed]; 10151 10152 return "unknown"; 10153 } 10154 10155 static const char all_lanes_dead_timeout_expired[] = 10156 "All lanes were inactive – was the interconnect media removed?"; 10157 static const char tx_out_of_policy[] = 10158 "Passing lanes on local port do not meet the local link width policy"; 10159 static const char no_state_complete[] = 10160 "State timeout occurred before link partner completed the state"; 10161 static const char * const state_complete_reasons[] = { 10162 [0x00] = "Reason unknown", 10163 [0x01] = "Link was halted by driver, refer to LinkDownReason", 10164 [0x02] = "Link partner reported failure", 10165 [0x10] = "Unable to achieve frame sync on any lane", 10166 [0x11] = 10167 "Unable to find a common bit rate with the link partner", 10168 [0x12] = 10169 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy", 10170 [0x13] = 10171 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy", 10172 [0x14] = no_state_complete, 10173 [0x15] = 10174 "State timeout occurred before link partner identified equalization presets", 10175 [0x16] = 10176 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy", 10177 [0x17] = tx_out_of_policy, 10178 [0x20] = all_lanes_dead_timeout_expired, 10179 [0x21] = 10180 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy", 10181 [0x22] = no_state_complete, 10182 [0x23] = 10183 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy", 10184 [0x24] = tx_out_of_policy, 10185 [0x30] = all_lanes_dead_timeout_expired, 10186 [0x31] = 10187 "State timeout occurred waiting for host to process received frames", 10188 [0x32] = no_state_complete, 10189 [0x33] = 10190 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy", 10191 [0x34] = tx_out_of_policy, 10192 [0x35] = "Negotiated link width is mutually exclusive", 10193 [0x36] = 10194 "Timed out before receiving verifycap frames in VerifyCap.Exchange", 10195 [0x37] = "Unable to resolve secure data exchange", 10196 }; 10197 10198 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd, 10199 u32 code) 10200 { 10201 const char *str = NULL; 10202 10203 if (code < ARRAY_SIZE(state_complete_reasons)) 10204 str = state_complete_reasons[code]; 10205 10206 if (str) 10207 return str; 10208 return "Reserved"; 10209 } 10210 10211 /* describe the given last state complete frame */ 10212 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame, 10213 const char *prefix) 10214 { 10215 struct hfi1_devdata *dd = ppd->dd; 10216 u32 success; 10217 u32 state; 10218 u32 reason; 10219 u32 lanes; 10220 10221 /* 10222 * Decode frame: 10223 * [ 0: 0] - success 10224 * [ 3: 1] - state 10225 * [ 7: 4] - next state timeout 10226 * [15: 8] - reason code 10227 * [31:16] - lanes 10228 */ 10229 success = frame & 0x1; 10230 state = (frame >> 1) & 0x7; 10231 reason = (frame >> 8) & 0xff; 10232 lanes = (frame >> 16) & 0xffff; 10233 10234 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n", 10235 prefix, frame); 10236 dd_dev_err(dd, " last reported state state: %s (0x%x)\n", 10237 state_completed_string(state), state); 10238 dd_dev_err(dd, " state successfully completed: %s\n", 10239 success ? "yes" : "no"); 10240 dd_dev_err(dd, " fail reason 0x%x: %s\n", 10241 reason, state_complete_reason_code_string(ppd, reason)); 10242 dd_dev_err(dd, " passing lane mask: 0x%x", lanes); 10243 } 10244 10245 /* 10246 * Read the last state complete frames and explain them. This routine 10247 * expects to be called if the link went down during link negotiation 10248 * and initialization (LNI). That is, anywhere between polling and link up. 10249 */ 10250 static void check_lni_states(struct hfi1_pportdata *ppd) 10251 { 10252 u32 last_local_state; 10253 u32 last_remote_state; 10254 10255 read_last_local_state(ppd->dd, &last_local_state); 10256 read_last_remote_state(ppd->dd, &last_remote_state); 10257 10258 /* 10259 * Don't report anything if there is nothing to report. A value of 10260 * 0 means the link was taken down while polling and there was no 10261 * training in-process. 10262 */ 10263 if (last_local_state == 0 && last_remote_state == 0) 10264 return; 10265 10266 decode_state_complete(ppd, last_local_state, "transmitted"); 10267 decode_state_complete(ppd, last_remote_state, "received"); 10268 } 10269 10270 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */ 10271 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms) 10272 { 10273 u64 reg; 10274 unsigned long timeout; 10275 10276 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */ 10277 timeout = jiffies + msecs_to_jiffies(wait_ms); 10278 while (1) { 10279 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); 10280 if (reg) 10281 break; 10282 if (time_after(jiffies, timeout)) { 10283 dd_dev_err(dd, 10284 "timeout waiting for LINK_TRANSFER_ACTIVE\n"); 10285 return -ETIMEDOUT; 10286 } 10287 udelay(2); 10288 } 10289 return 0; 10290 } 10291 10292 /* called when the logical link state is not down as it should be */ 10293 static void force_logical_link_state_down(struct hfi1_pportdata *ppd) 10294 { 10295 struct hfi1_devdata *dd = ppd->dd; 10296 10297 /* 10298 * Bring link up in LCB loopback 10299 */ 10300 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10301 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 10302 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK); 10303 10304 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); 10305 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); 10306 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); 10307 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); 10308 10309 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); 10310 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); 10311 udelay(3); 10312 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); 10313 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); 10314 10315 wait_link_transfer_active(dd, 100); 10316 10317 /* 10318 * Bring the link down again. 10319 */ 10320 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); 10321 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); 10322 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); 10323 10324 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n"); 10325 } 10326 10327 /* 10328 * Helper for set_link_state(). Do not call except from that routine. 10329 * Expects ppd->hls_mutex to be held. 10330 * 10331 * @rem_reason value to be sent to the neighbor 10332 * 10333 * LinkDownReasons only set if transition succeeds. 10334 */ 10335 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason) 10336 { 10337 struct hfi1_devdata *dd = ppd->dd; 10338 u32 previous_state; 10339 int offline_state_ret; 10340 int ret; 10341 10342 update_lcb_cache(dd); 10343 10344 previous_state = ppd->host_link_state; 10345 ppd->host_link_state = HLS_GOING_OFFLINE; 10346 10347 /* start offline transition */ 10348 ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE); 10349 10350 if (ret != HCMD_SUCCESS) { 10351 dd_dev_err(dd, 10352 "Failed to transition to Offline link state, return %d\n", 10353 ret); 10354 return -EINVAL; 10355 } 10356 if (ppd->offline_disabled_reason == 10357 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)) 10358 ppd->offline_disabled_reason = 10359 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT); 10360 10361 offline_state_ret = wait_phys_link_offline_substates(ppd, 10000); 10362 if (offline_state_ret < 0) 10363 return offline_state_ret; 10364 10365 /* Disabling AOC transmitters */ 10366 if (ppd->port_type == PORT_TYPE_QSFP && 10367 ppd->qsfp_info.limiting_active && 10368 qsfp_mod_present(ppd)) { 10369 int ret; 10370 10371 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT); 10372 if (ret == 0) { 10373 set_qsfp_tx(ppd, 0); 10374 release_chip_resource(dd, qsfp_resource(dd)); 10375 } else { 10376 /* not fatal, but should warn */ 10377 dd_dev_err(dd, 10378 "Unable to acquire lock to turn off QSFP TX\n"); 10379 } 10380 } 10381 10382 /* 10383 * Wait for the offline.Quiet transition if it hasn't happened yet. It 10384 * can take a while for the link to go down. 10385 */ 10386 if (offline_state_ret != PLS_OFFLINE_QUIET) { 10387 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000); 10388 if (ret < 0) 10389 return ret; 10390 } 10391 10392 /* 10393 * Now in charge of LCB - must be after the physical state is 10394 * offline.quiet and before host_link_state is changed. 10395 */ 10396 set_host_lcb_access(dd); 10397 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ 10398 10399 /* make sure the logical state is also down */ 10400 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000); 10401 if (ret) 10402 force_logical_link_state_down(ppd); 10403 10404 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */ 10405 update_statusp(ppd, IB_PORT_DOWN); 10406 10407 /* 10408 * The LNI has a mandatory wait time after the physical state 10409 * moves to Offline.Quiet. The wait time may be different 10410 * depending on how the link went down. The 8051 firmware 10411 * will observe the needed wait time and only move to ready 10412 * when that is completed. The largest of the quiet timeouts 10413 * is 6s, so wait that long and then at least 0.5s more for 10414 * other transitions, and another 0.5s for a buffer. 10415 */ 10416 ret = wait_fm_ready(dd, 7000); 10417 if (ret) { 10418 dd_dev_err(dd, 10419 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n"); 10420 /* state is really offline, so make it so */ 10421 ppd->host_link_state = HLS_DN_OFFLINE; 10422 return ret; 10423 } 10424 10425 /* 10426 * The state is now offline and the 8051 is ready to accept host 10427 * requests. 10428 * - change our state 10429 * - notify others if we were previously in a linkup state 10430 */ 10431 ppd->host_link_state = HLS_DN_OFFLINE; 10432 if (previous_state & HLS_UP) { 10433 /* went down while link was up */ 10434 handle_linkup_change(dd, 0); 10435 } else if (previous_state 10436 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) { 10437 /* went down while attempting link up */ 10438 check_lni_states(ppd); 10439 10440 /* The QSFP doesn't need to be reset on LNI failure */ 10441 ppd->qsfp_info.reset_needed = 0; 10442 } 10443 10444 /* the active link width (downgrade) is 0 on link down */ 10445 ppd->link_width_active = 0; 10446 ppd->link_width_downgrade_tx_active = 0; 10447 ppd->link_width_downgrade_rx_active = 0; 10448 ppd->current_egress_rate = 0; 10449 return 0; 10450 } 10451 10452 /* return the link state name */ 10453 static const char *link_state_name(u32 state) 10454 { 10455 const char *name; 10456 int n = ilog2(state); 10457 static const char * const names[] = { 10458 [__HLS_UP_INIT_BP] = "INIT", 10459 [__HLS_UP_ARMED_BP] = "ARMED", 10460 [__HLS_UP_ACTIVE_BP] = "ACTIVE", 10461 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF", 10462 [__HLS_DN_POLL_BP] = "POLL", 10463 [__HLS_DN_DISABLE_BP] = "DISABLE", 10464 [__HLS_DN_OFFLINE_BP] = "OFFLINE", 10465 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP", 10466 [__HLS_GOING_UP_BP] = "GOING_UP", 10467 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE", 10468 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN" 10469 }; 10470 10471 name = n < ARRAY_SIZE(names) ? names[n] : NULL; 10472 return name ? name : "unknown"; 10473 } 10474 10475 /* return the link state reason name */ 10476 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state) 10477 { 10478 if (state == HLS_UP_INIT) { 10479 switch (ppd->linkinit_reason) { 10480 case OPA_LINKINIT_REASON_LINKUP: 10481 return "(LINKUP)"; 10482 case OPA_LINKINIT_REASON_FLAPPING: 10483 return "(FLAPPING)"; 10484 case OPA_LINKINIT_OUTSIDE_POLICY: 10485 return "(OUTSIDE_POLICY)"; 10486 case OPA_LINKINIT_QUARANTINED: 10487 return "(QUARANTINED)"; 10488 case OPA_LINKINIT_INSUFIC_CAPABILITY: 10489 return "(INSUFIC_CAPABILITY)"; 10490 default: 10491 break; 10492 } 10493 } 10494 return ""; 10495 } 10496 10497 /* 10498 * driver_pstate - convert the driver's notion of a port's 10499 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*). 10500 * Return -1 (converted to a u32) to indicate error. 10501 */ 10502 u32 driver_pstate(struct hfi1_pportdata *ppd) 10503 { 10504 switch (ppd->host_link_state) { 10505 case HLS_UP_INIT: 10506 case HLS_UP_ARMED: 10507 case HLS_UP_ACTIVE: 10508 return IB_PORTPHYSSTATE_LINKUP; 10509 case HLS_DN_POLL: 10510 return IB_PORTPHYSSTATE_POLLING; 10511 case HLS_DN_DISABLE: 10512 return IB_PORTPHYSSTATE_DISABLED; 10513 case HLS_DN_OFFLINE: 10514 return OPA_PORTPHYSSTATE_OFFLINE; 10515 case HLS_VERIFY_CAP: 10516 return IB_PORTPHYSSTATE_TRAINING; 10517 case HLS_GOING_UP: 10518 return IB_PORTPHYSSTATE_TRAINING; 10519 case HLS_GOING_OFFLINE: 10520 return OPA_PORTPHYSSTATE_OFFLINE; 10521 case HLS_LINK_COOLDOWN: 10522 return OPA_PORTPHYSSTATE_OFFLINE; 10523 case HLS_DN_DOWNDEF: 10524 default: 10525 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10526 ppd->host_link_state); 10527 return -1; 10528 } 10529 } 10530 10531 /* 10532 * driver_lstate - convert the driver's notion of a port's 10533 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1 10534 * (converted to a u32) to indicate error. 10535 */ 10536 u32 driver_lstate(struct hfi1_pportdata *ppd) 10537 { 10538 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN)) 10539 return IB_PORT_DOWN; 10540 10541 switch (ppd->host_link_state & HLS_UP) { 10542 case HLS_UP_INIT: 10543 return IB_PORT_INIT; 10544 case HLS_UP_ARMED: 10545 return IB_PORT_ARMED; 10546 case HLS_UP_ACTIVE: 10547 return IB_PORT_ACTIVE; 10548 default: 10549 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n", 10550 ppd->host_link_state); 10551 return -1; 10552 } 10553 } 10554 10555 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 10556 u8 neigh_reason, u8 rem_reason) 10557 { 10558 if (ppd->local_link_down_reason.latest == 0 && 10559 ppd->neigh_link_down_reason.latest == 0) { 10560 ppd->local_link_down_reason.latest = lcl_reason; 10561 ppd->neigh_link_down_reason.latest = neigh_reason; 10562 ppd->remote_link_down_reason = rem_reason; 10563 } 10564 } 10565 10566 /** 10567 * data_vls_operational() - Verify if data VL BCT credits and MTU 10568 * are both set. 10569 * @ppd: pointer to hfi1_pportdata structure 10570 * 10571 * Return: true - Ok, false -otherwise. 10572 */ 10573 static inline bool data_vls_operational(struct hfi1_pportdata *ppd) 10574 { 10575 int i; 10576 u64 reg; 10577 10578 if (!ppd->actual_vls_operational) 10579 return false; 10580 10581 for (i = 0; i < ppd->vls_supported; i++) { 10582 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i)); 10583 if ((reg && !ppd->dd->vld[i].mtu) || 10584 (!reg && ppd->dd->vld[i].mtu)) 10585 return false; 10586 } 10587 10588 return true; 10589 } 10590 10591 /* 10592 * Change the physical and/or logical link state. 10593 * 10594 * Do not call this routine while inside an interrupt. It contains 10595 * calls to routines that can take multiple seconds to finish. 10596 * 10597 * Returns 0 on success, -errno on failure. 10598 */ 10599 int set_link_state(struct hfi1_pportdata *ppd, u32 state) 10600 { 10601 struct hfi1_devdata *dd = ppd->dd; 10602 struct ib_event event = {.device = NULL}; 10603 int ret1, ret = 0; 10604 int orig_new_state, poll_bounce; 10605 10606 mutex_lock(&ppd->hls_lock); 10607 10608 orig_new_state = state; 10609 if (state == HLS_DN_DOWNDEF) 10610 state = HLS_DEFAULT; 10611 10612 /* interpret poll -> poll as a link bounce */ 10613 poll_bounce = ppd->host_link_state == HLS_DN_POLL && 10614 state == HLS_DN_POLL; 10615 10616 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__, 10617 link_state_name(ppd->host_link_state), 10618 link_state_name(orig_new_state), 10619 poll_bounce ? "(bounce) " : "", 10620 link_state_reason_name(ppd, state)); 10621 10622 /* 10623 * If we're going to a (HLS_*) link state that implies the logical 10624 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then 10625 * reset is_sm_config_started to 0. 10626 */ 10627 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE))) 10628 ppd->is_sm_config_started = 0; 10629 10630 /* 10631 * Do nothing if the states match. Let a poll to poll link bounce 10632 * go through. 10633 */ 10634 if (ppd->host_link_state == state && !poll_bounce) 10635 goto done; 10636 10637 switch (state) { 10638 case HLS_UP_INIT: 10639 if (ppd->host_link_state == HLS_DN_POLL && 10640 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) { 10641 /* 10642 * Quick link up jumps from polling to here. 10643 * 10644 * Whether in normal or loopback mode, the 10645 * simulator jumps from polling to link up. 10646 * Accept that here. 10647 */ 10648 /* OK */ 10649 } else if (ppd->host_link_state != HLS_GOING_UP) { 10650 goto unexpected; 10651 } 10652 10653 /* 10654 * Wait for Link_Up physical state. 10655 * Physical and Logical states should already be 10656 * be transitioned to LinkUp and LinkInit respectively. 10657 */ 10658 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000); 10659 if (ret) { 10660 dd_dev_err(dd, 10661 "%s: physical state did not change to LINK-UP\n", 10662 __func__); 10663 break; 10664 } 10665 10666 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000); 10667 if (ret) { 10668 dd_dev_err(dd, 10669 "%s: logical state did not change to INIT\n", 10670 __func__); 10671 break; 10672 } 10673 10674 /* clear old transient LINKINIT_REASON code */ 10675 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR) 10676 ppd->linkinit_reason = 10677 OPA_LINKINIT_REASON_LINKUP; 10678 10679 /* enable the port */ 10680 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK); 10681 10682 handle_linkup_change(dd, 1); 10683 pio_kernel_linkup(dd); 10684 10685 /* 10686 * After link up, a new link width will have been set. 10687 * Update the xmit counters with regards to the new 10688 * link width. 10689 */ 10690 update_xmit_counters(ppd, ppd->link_width_active); 10691 10692 ppd->host_link_state = HLS_UP_INIT; 10693 update_statusp(ppd, IB_PORT_INIT); 10694 break; 10695 case HLS_UP_ARMED: 10696 if (ppd->host_link_state != HLS_UP_INIT) 10697 goto unexpected; 10698 10699 if (!data_vls_operational(ppd)) { 10700 dd_dev_err(dd, 10701 "%s: Invalid data VL credits or mtu\n", 10702 __func__); 10703 ret = -EINVAL; 10704 break; 10705 } 10706 10707 set_logical_state(dd, LSTATE_ARMED); 10708 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000); 10709 if (ret) { 10710 dd_dev_err(dd, 10711 "%s: logical state did not change to ARMED\n", 10712 __func__); 10713 break; 10714 } 10715 ppd->host_link_state = HLS_UP_ARMED; 10716 update_statusp(ppd, IB_PORT_ARMED); 10717 /* 10718 * The simulator does not currently implement SMA messages, 10719 * so neighbor_normal is not set. Set it here when we first 10720 * move to Armed. 10721 */ 10722 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 10723 ppd->neighbor_normal = 1; 10724 break; 10725 case HLS_UP_ACTIVE: 10726 if (ppd->host_link_state != HLS_UP_ARMED) 10727 goto unexpected; 10728 10729 set_logical_state(dd, LSTATE_ACTIVE); 10730 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000); 10731 if (ret) { 10732 dd_dev_err(dd, 10733 "%s: logical state did not change to ACTIVE\n", 10734 __func__); 10735 } else { 10736 /* tell all engines to go running */ 10737 sdma_all_running(dd); 10738 ppd->host_link_state = HLS_UP_ACTIVE; 10739 update_statusp(ppd, IB_PORT_ACTIVE); 10740 10741 /* Signal the IB layer that the port has went active */ 10742 event.device = &dd->verbs_dev.rdi.ibdev; 10743 event.element.port_num = ppd->port; 10744 event.event = IB_EVENT_PORT_ACTIVE; 10745 } 10746 break; 10747 case HLS_DN_POLL: 10748 if ((ppd->host_link_state == HLS_DN_DISABLE || 10749 ppd->host_link_state == HLS_DN_OFFLINE) && 10750 dd->dc_shutdown) 10751 dc_start(dd); 10752 /* Hand LED control to the DC */ 10753 write_csr(dd, DCC_CFG_LED_CNTRL, 0); 10754 10755 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10756 u8 tmp = ppd->link_enabled; 10757 10758 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10759 if (ret) { 10760 ppd->link_enabled = tmp; 10761 break; 10762 } 10763 ppd->remote_link_down_reason = 0; 10764 10765 if (ppd->driver_link_ready) 10766 ppd->link_enabled = 1; 10767 } 10768 10769 set_all_slowpath(ppd->dd); 10770 ret = set_local_link_attributes(ppd); 10771 if (ret) 10772 break; 10773 10774 ppd->port_error_action = 0; 10775 10776 if (quick_linkup) { 10777 /* quick linkup does not go into polling */ 10778 ret = do_quick_linkup(dd); 10779 } else { 10780 ret1 = set_physical_link_state(dd, PLS_POLLING); 10781 if (!ret1) 10782 ret1 = wait_phys_link_out_of_offline(ppd, 10783 3000); 10784 if (ret1 != HCMD_SUCCESS) { 10785 dd_dev_err(dd, 10786 "Failed to transition to Polling link state, return 0x%x\n", 10787 ret1); 10788 ret = -EINVAL; 10789 } 10790 } 10791 10792 /* 10793 * Change the host link state after requesting DC8051 to 10794 * change its physical state so that we can ignore any 10795 * interrupt with stale LNI(XX) error, which will not be 10796 * cleared until DC8051 transitions to Polling state. 10797 */ 10798 ppd->host_link_state = HLS_DN_POLL; 10799 ppd->offline_disabled_reason = 10800 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE); 10801 /* 10802 * If an error occurred above, go back to offline. The 10803 * caller may reschedule another attempt. 10804 */ 10805 if (ret) 10806 goto_offline(ppd, 0); 10807 else 10808 log_physical_state(ppd, PLS_POLLING); 10809 break; 10810 case HLS_DN_DISABLE: 10811 /* link is disabled */ 10812 ppd->link_enabled = 0; 10813 10814 /* allow any state to transition to disabled */ 10815 10816 /* must transition to offline first */ 10817 if (ppd->host_link_state != HLS_DN_OFFLINE) { 10818 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10819 if (ret) 10820 break; 10821 ppd->remote_link_down_reason = 0; 10822 } 10823 10824 if (!dd->dc_shutdown) { 10825 ret1 = set_physical_link_state(dd, PLS_DISABLED); 10826 if (ret1 != HCMD_SUCCESS) { 10827 dd_dev_err(dd, 10828 "Failed to transition to Disabled link state, return 0x%x\n", 10829 ret1); 10830 ret = -EINVAL; 10831 break; 10832 } 10833 ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000); 10834 if (ret) { 10835 dd_dev_err(dd, 10836 "%s: physical state did not change to DISABLED\n", 10837 __func__); 10838 break; 10839 } 10840 dc_shutdown(dd); 10841 } 10842 ppd->host_link_state = HLS_DN_DISABLE; 10843 break; 10844 case HLS_DN_OFFLINE: 10845 if (ppd->host_link_state == HLS_DN_DISABLE) 10846 dc_start(dd); 10847 10848 /* allow any state to transition to offline */ 10849 ret = goto_offline(ppd, ppd->remote_link_down_reason); 10850 if (!ret) 10851 ppd->remote_link_down_reason = 0; 10852 break; 10853 case HLS_VERIFY_CAP: 10854 if (ppd->host_link_state != HLS_DN_POLL) 10855 goto unexpected; 10856 ppd->host_link_state = HLS_VERIFY_CAP; 10857 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP); 10858 break; 10859 case HLS_GOING_UP: 10860 if (ppd->host_link_state != HLS_VERIFY_CAP) 10861 goto unexpected; 10862 10863 ret1 = set_physical_link_state(dd, PLS_LINKUP); 10864 if (ret1 != HCMD_SUCCESS) { 10865 dd_dev_err(dd, 10866 "Failed to transition to link up state, return 0x%x\n", 10867 ret1); 10868 ret = -EINVAL; 10869 break; 10870 } 10871 ppd->host_link_state = HLS_GOING_UP; 10872 break; 10873 10874 case HLS_GOING_OFFLINE: /* transient within goto_offline() */ 10875 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */ 10876 default: 10877 dd_dev_info(dd, "%s: state 0x%x: not supported\n", 10878 __func__, state); 10879 ret = -EINVAL; 10880 break; 10881 } 10882 10883 goto done; 10884 10885 unexpected: 10886 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n", 10887 __func__, link_state_name(ppd->host_link_state), 10888 link_state_name(state)); 10889 ret = -EINVAL; 10890 10891 done: 10892 mutex_unlock(&ppd->hls_lock); 10893 10894 if (event.device) 10895 ib_dispatch_event(&event); 10896 10897 return ret; 10898 } 10899 10900 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val) 10901 { 10902 u64 reg; 10903 int ret = 0; 10904 10905 switch (which) { 10906 case HFI1_IB_CFG_LIDLMC: 10907 set_lidlmc(ppd); 10908 break; 10909 case HFI1_IB_CFG_VL_HIGH_LIMIT: 10910 /* 10911 * The VL Arbitrator high limit is sent in units of 4k 10912 * bytes, while HFI stores it in units of 64 bytes. 10913 */ 10914 val *= 4096 / 64; 10915 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) 10916 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT; 10917 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); 10918 break; 10919 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 10920 /* HFI only supports POLL as the default link down state */ 10921 if (val != HLS_DN_POLL) 10922 ret = -EINVAL; 10923 break; 10924 case HFI1_IB_CFG_OP_VLS: 10925 if (ppd->vls_operational != val) { 10926 ppd->vls_operational = val; 10927 if (!ppd->port) 10928 ret = -EINVAL; 10929 } 10930 break; 10931 /* 10932 * For link width, link width downgrade, and speed enable, always AND 10933 * the setting with what is actually supported. This has two benefits. 10934 * First, enabled can't have unsupported values, no matter what the 10935 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean 10936 * "fill in with your supported value" have all the bits in the 10937 * field set, so simply ANDing with supported has the desired result. 10938 */ 10939 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */ 10940 ppd->link_width_enabled = val & ppd->link_width_supported; 10941 break; 10942 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */ 10943 ppd->link_width_downgrade_enabled = 10944 val & ppd->link_width_downgrade_supported; 10945 break; 10946 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */ 10947 ppd->link_speed_enabled = val & ppd->link_speed_supported; 10948 break; 10949 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 10950 /* 10951 * HFI does not follow IB specs, save this value 10952 * so we can report it, if asked. 10953 */ 10954 ppd->overrun_threshold = val; 10955 break; 10956 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 10957 /* 10958 * HFI does not follow IB specs, save this value 10959 * so we can report it, if asked. 10960 */ 10961 ppd->phy_error_threshold = val; 10962 break; 10963 10964 case HFI1_IB_CFG_MTU: 10965 set_send_length(ppd); 10966 break; 10967 10968 case HFI1_IB_CFG_PKEYS: 10969 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 10970 set_partition_keys(ppd); 10971 break; 10972 10973 default: 10974 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 10975 dd_dev_info(ppd->dd, 10976 "%s: which %s, val 0x%x: not implemented\n", 10977 __func__, ib_cfg_name(which), val); 10978 break; 10979 } 10980 return ret; 10981 } 10982 10983 /* begin functions related to vl arbitration table caching */ 10984 static void init_vl_arb_caches(struct hfi1_pportdata *ppd) 10985 { 10986 int i; 10987 10988 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 10989 VL_ARB_LOW_PRIO_TABLE_SIZE); 10990 BUILD_BUG_ON(VL_ARB_TABLE_SIZE != 10991 VL_ARB_HIGH_PRIO_TABLE_SIZE); 10992 10993 /* 10994 * Note that we always return values directly from the 10995 * 'vl_arb_cache' (and do no CSR reads) in response to a 10996 * 'Get(VLArbTable)'. This is obviously correct after a 10997 * 'Set(VLArbTable)', since the cache will then be up to 10998 * date. But it's also correct prior to any 'Set(VLArbTable)' 10999 * since then both the cache, and the relevant h/w registers 11000 * will be zeroed. 11001 */ 11002 11003 for (i = 0; i < MAX_PRIO_TABLE; i++) 11004 spin_lock_init(&ppd->vl_arb_cache[i].lock); 11005 } 11006 11007 /* 11008 * vl_arb_lock_cache 11009 * 11010 * All other vl_arb_* functions should be called only after locking 11011 * the cache. 11012 */ 11013 static inline struct vl_arb_cache * 11014 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx) 11015 { 11016 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE) 11017 return NULL; 11018 spin_lock(&ppd->vl_arb_cache[idx].lock); 11019 return &ppd->vl_arb_cache[idx]; 11020 } 11021 11022 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx) 11023 { 11024 spin_unlock(&ppd->vl_arb_cache[idx].lock); 11025 } 11026 11027 static void vl_arb_get_cache(struct vl_arb_cache *cache, 11028 struct ib_vl_weight_elem *vl) 11029 { 11030 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11031 } 11032 11033 static void vl_arb_set_cache(struct vl_arb_cache *cache, 11034 struct ib_vl_weight_elem *vl) 11035 { 11036 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11037 } 11038 11039 static int vl_arb_match_cache(struct vl_arb_cache *cache, 11040 struct ib_vl_weight_elem *vl) 11041 { 11042 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl)); 11043 } 11044 11045 /* end functions related to vl arbitration table caching */ 11046 11047 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target, 11048 u32 size, struct ib_vl_weight_elem *vl) 11049 { 11050 struct hfi1_devdata *dd = ppd->dd; 11051 u64 reg; 11052 unsigned int i, is_up = 0; 11053 int drain, ret = 0; 11054 11055 mutex_lock(&ppd->hls_lock); 11056 11057 if (ppd->host_link_state & HLS_UP) 11058 is_up = 1; 11059 11060 drain = !is_ax(dd) && is_up; 11061 11062 if (drain) 11063 /* 11064 * Before adjusting VL arbitration weights, empty per-VL 11065 * FIFOs, otherwise a packet whose VL weight is being 11066 * set to 0 could get stuck in a FIFO with no chance to 11067 * egress. 11068 */ 11069 ret = stop_drain_data_vls(dd); 11070 11071 if (ret) { 11072 dd_dev_err( 11073 dd, 11074 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n", 11075 __func__); 11076 goto err; 11077 } 11078 11079 for (i = 0; i < size; i++, vl++) { 11080 /* 11081 * NOTE: The low priority shift and mask are used here, but 11082 * they are the same for both the low and high registers. 11083 */ 11084 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK) 11085 << SEND_LOW_PRIORITY_LIST_VL_SHIFT) 11086 | (((u64)vl->weight 11087 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK) 11088 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT); 11089 write_csr(dd, target + (i * 8), reg); 11090 } 11091 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE); 11092 11093 if (drain) 11094 open_fill_data_vls(dd); /* reopen all VLs */ 11095 11096 err: 11097 mutex_unlock(&ppd->hls_lock); 11098 11099 return ret; 11100 } 11101 11102 /* 11103 * Read one credit merge VL register. 11104 */ 11105 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr, 11106 struct vl_limit *vll) 11107 { 11108 u64 reg = read_csr(dd, csr); 11109 11110 vll->dedicated = cpu_to_be16( 11111 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT) 11112 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK); 11113 vll->shared = cpu_to_be16( 11114 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT) 11115 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK); 11116 } 11117 11118 /* 11119 * Read the current credit merge limits. 11120 */ 11121 static int get_buffer_control(struct hfi1_devdata *dd, 11122 struct buffer_control *bc, u16 *overall_limit) 11123 { 11124 u64 reg; 11125 int i; 11126 11127 /* not all entries are filled in */ 11128 memset(bc, 0, sizeof(*bc)); 11129 11130 /* OPA and HFI have a 1-1 mapping */ 11131 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11132 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]); 11133 11134 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */ 11135 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]); 11136 11137 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11138 bc->overall_shared_limit = cpu_to_be16( 11139 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) 11140 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK); 11141 if (overall_limit) 11142 *overall_limit = (reg 11143 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) 11144 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK; 11145 return sizeof(struct buffer_control); 11146 } 11147 11148 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11149 { 11150 u64 reg; 11151 int i; 11152 11153 /* each register contains 16 SC->VLnt mappings, 4 bits each */ 11154 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); 11155 for (i = 0; i < sizeof(u64); i++) { 11156 u8 byte = *(((u8 *)®) + i); 11157 11158 dp->vlnt[2 * i] = byte & 0xf; 11159 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4; 11160 } 11161 11162 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); 11163 for (i = 0; i < sizeof(u64); i++) { 11164 u8 byte = *(((u8 *)®) + i); 11165 11166 dp->vlnt[16 + (2 * i)] = byte & 0xf; 11167 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4; 11168 } 11169 return sizeof(struct sc2vlnt); 11170 } 11171 11172 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems, 11173 struct ib_vl_weight_elem *vl) 11174 { 11175 unsigned int i; 11176 11177 for (i = 0; i < nelems; i++, vl++) { 11178 vl->vl = 0xf; 11179 vl->weight = 0; 11180 } 11181 } 11182 11183 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp) 11184 { 11185 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, 11186 DC_SC_VL_VAL(15_0, 11187 0, dp->vlnt[0] & 0xf, 11188 1, dp->vlnt[1] & 0xf, 11189 2, dp->vlnt[2] & 0xf, 11190 3, dp->vlnt[3] & 0xf, 11191 4, dp->vlnt[4] & 0xf, 11192 5, dp->vlnt[5] & 0xf, 11193 6, dp->vlnt[6] & 0xf, 11194 7, dp->vlnt[7] & 0xf, 11195 8, dp->vlnt[8] & 0xf, 11196 9, dp->vlnt[9] & 0xf, 11197 10, dp->vlnt[10] & 0xf, 11198 11, dp->vlnt[11] & 0xf, 11199 12, dp->vlnt[12] & 0xf, 11200 13, dp->vlnt[13] & 0xf, 11201 14, dp->vlnt[14] & 0xf, 11202 15, dp->vlnt[15] & 0xf)); 11203 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, 11204 DC_SC_VL_VAL(31_16, 11205 16, dp->vlnt[16] & 0xf, 11206 17, dp->vlnt[17] & 0xf, 11207 18, dp->vlnt[18] & 0xf, 11208 19, dp->vlnt[19] & 0xf, 11209 20, dp->vlnt[20] & 0xf, 11210 21, dp->vlnt[21] & 0xf, 11211 22, dp->vlnt[22] & 0xf, 11212 23, dp->vlnt[23] & 0xf, 11213 24, dp->vlnt[24] & 0xf, 11214 25, dp->vlnt[25] & 0xf, 11215 26, dp->vlnt[26] & 0xf, 11216 27, dp->vlnt[27] & 0xf, 11217 28, dp->vlnt[28] & 0xf, 11218 29, dp->vlnt[29] & 0xf, 11219 30, dp->vlnt[30] & 0xf, 11220 31, dp->vlnt[31] & 0xf)); 11221 } 11222 11223 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what, 11224 u16 limit) 11225 { 11226 if (limit != 0) 11227 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n", 11228 what, (int)limit, idx); 11229 } 11230 11231 /* change only the shared limit portion of SendCmGLobalCredit */ 11232 static void set_global_shared(struct hfi1_devdata *dd, u16 limit) 11233 { 11234 u64 reg; 11235 11236 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11237 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK; 11238 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT; 11239 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11240 } 11241 11242 /* change only the total credit limit portion of SendCmGLobalCredit */ 11243 static void set_global_limit(struct hfi1_devdata *dd, u16 limit) 11244 { 11245 u64 reg; 11246 11247 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); 11248 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK; 11249 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; 11250 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); 11251 } 11252 11253 /* set the given per-VL shared limit */ 11254 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit) 11255 { 11256 u64 reg; 11257 u32 addr; 11258 11259 if (vl < TXE_NUM_DATA_VL) 11260 addr = SEND_CM_CREDIT_VL + (8 * vl); 11261 else 11262 addr = SEND_CM_CREDIT_VL15; 11263 11264 reg = read_csr(dd, addr); 11265 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK; 11266 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT; 11267 write_csr(dd, addr, reg); 11268 } 11269 11270 /* set the given per-VL dedicated limit */ 11271 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit) 11272 { 11273 u64 reg; 11274 u32 addr; 11275 11276 if (vl < TXE_NUM_DATA_VL) 11277 addr = SEND_CM_CREDIT_VL + (8 * vl); 11278 else 11279 addr = SEND_CM_CREDIT_VL15; 11280 11281 reg = read_csr(dd, addr); 11282 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK; 11283 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT; 11284 write_csr(dd, addr, reg); 11285 } 11286 11287 /* spin until the given per-VL status mask bits clear */ 11288 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask, 11289 const char *which) 11290 { 11291 unsigned long timeout; 11292 u64 reg; 11293 11294 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT); 11295 while (1) { 11296 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; 11297 11298 if (reg == 0) 11299 return; /* success */ 11300 if (time_after(jiffies, timeout)) 11301 break; /* timed out */ 11302 udelay(1); 11303 } 11304 11305 dd_dev_err(dd, 11306 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n", 11307 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); 11308 /* 11309 * If this occurs, it is likely there was a credit loss on the link. 11310 * The only recovery from that is a link bounce. 11311 */ 11312 dd_dev_err(dd, 11313 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n"); 11314 } 11315 11316 /* 11317 * The number of credits on the VLs may be changed while everything 11318 * is "live", but the following algorithm must be followed due to 11319 * how the hardware is actually implemented. In particular, 11320 * Return_Credit_Status[] is the only correct status check. 11321 * 11322 * if (reducing Global_Shared_Credit_Limit or any shared limit changing) 11323 * set Global_Shared_Credit_Limit = 0 11324 * use_all_vl = 1 11325 * mask0 = all VLs that are changing either dedicated or shared limits 11326 * set Shared_Limit[mask0] = 0 11327 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0 11328 * if (changing any dedicated limit) 11329 * mask1 = all VLs that are lowering dedicated limits 11330 * lower Dedicated_Limit[mask1] 11331 * spin until Return_Credit_Status[mask1] == 0 11332 * raise Dedicated_Limits 11333 * raise Shared_Limits 11334 * raise Global_Shared_Credit_Limit 11335 * 11336 * lower = if the new limit is lower, set the limit to the new value 11337 * raise = if the new limit is higher than the current value (may be changed 11338 * earlier in the algorithm), set the new limit to the new value 11339 */ 11340 int set_buffer_control(struct hfi1_pportdata *ppd, 11341 struct buffer_control *new_bc) 11342 { 11343 struct hfi1_devdata *dd = ppd->dd; 11344 u64 changing_mask, ld_mask, stat_mask; 11345 int change_count; 11346 int i, use_all_mask; 11347 int this_shared_changing; 11348 int vl_count = 0, ret; 11349 /* 11350 * A0: add the variable any_shared_limit_changing below and in the 11351 * algorithm above. If removing A0 support, it can be removed. 11352 */ 11353 int any_shared_limit_changing; 11354 struct buffer_control cur_bc; 11355 u8 changing[OPA_MAX_VLS]; 11356 u8 lowering_dedicated[OPA_MAX_VLS]; 11357 u16 cur_total; 11358 u32 new_total = 0; 11359 const u64 all_mask = 11360 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK 11361 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK 11362 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK 11363 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK 11364 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK 11365 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK 11366 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK 11367 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK 11368 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK; 11369 11370 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15) 11371 #define NUM_USABLE_VLS 16 /* look at VL15 and less */ 11372 11373 /* find the new total credits, do sanity check on unused VLs */ 11374 for (i = 0; i < OPA_MAX_VLS; i++) { 11375 if (valid_vl(i)) { 11376 new_total += be16_to_cpu(new_bc->vl[i].dedicated); 11377 continue; 11378 } 11379 nonzero_msg(dd, i, "dedicated", 11380 be16_to_cpu(new_bc->vl[i].dedicated)); 11381 nonzero_msg(dd, i, "shared", 11382 be16_to_cpu(new_bc->vl[i].shared)); 11383 new_bc->vl[i].dedicated = 0; 11384 new_bc->vl[i].shared = 0; 11385 } 11386 new_total += be16_to_cpu(new_bc->overall_shared_limit); 11387 11388 /* fetch the current values */ 11389 get_buffer_control(dd, &cur_bc, &cur_total); 11390 11391 /* 11392 * Create the masks we will use. 11393 */ 11394 memset(changing, 0, sizeof(changing)); 11395 memset(lowering_dedicated, 0, sizeof(lowering_dedicated)); 11396 /* 11397 * NOTE: Assumes that the individual VL bits are adjacent and in 11398 * increasing order 11399 */ 11400 stat_mask = 11401 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK; 11402 changing_mask = 0; 11403 ld_mask = 0; 11404 change_count = 0; 11405 any_shared_limit_changing = 0; 11406 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) { 11407 if (!valid_vl(i)) 11408 continue; 11409 this_shared_changing = new_bc->vl[i].shared 11410 != cur_bc.vl[i].shared; 11411 if (this_shared_changing) 11412 any_shared_limit_changing = 1; 11413 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated || 11414 this_shared_changing) { 11415 changing[i] = 1; 11416 changing_mask |= stat_mask; 11417 change_count++; 11418 } 11419 if (be16_to_cpu(new_bc->vl[i].dedicated) < 11420 be16_to_cpu(cur_bc.vl[i].dedicated)) { 11421 lowering_dedicated[i] = 1; 11422 ld_mask |= stat_mask; 11423 } 11424 } 11425 11426 /* bracket the credit change with a total adjustment */ 11427 if (new_total > cur_total) 11428 set_global_limit(dd, new_total); 11429 11430 /* 11431 * Start the credit change algorithm. 11432 */ 11433 use_all_mask = 0; 11434 if ((be16_to_cpu(new_bc->overall_shared_limit) < 11435 be16_to_cpu(cur_bc.overall_shared_limit)) || 11436 (is_ax(dd) && any_shared_limit_changing)) { 11437 set_global_shared(dd, 0); 11438 cur_bc.overall_shared_limit = 0; 11439 use_all_mask = 1; 11440 } 11441 11442 for (i = 0; i < NUM_USABLE_VLS; i++) { 11443 if (!valid_vl(i)) 11444 continue; 11445 11446 if (changing[i]) { 11447 set_vl_shared(dd, i, 0); 11448 cur_bc.vl[i].shared = 0; 11449 } 11450 } 11451 11452 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask, 11453 "shared"); 11454 11455 if (change_count > 0) { 11456 for (i = 0; i < NUM_USABLE_VLS; i++) { 11457 if (!valid_vl(i)) 11458 continue; 11459 11460 if (lowering_dedicated[i]) { 11461 set_vl_dedicated(dd, i, 11462 be16_to_cpu(new_bc-> 11463 vl[i].dedicated)); 11464 cur_bc.vl[i].dedicated = 11465 new_bc->vl[i].dedicated; 11466 } 11467 } 11468 11469 wait_for_vl_status_clear(dd, ld_mask, "dedicated"); 11470 11471 /* now raise all dedicated that are going up */ 11472 for (i = 0; i < NUM_USABLE_VLS; i++) { 11473 if (!valid_vl(i)) 11474 continue; 11475 11476 if (be16_to_cpu(new_bc->vl[i].dedicated) > 11477 be16_to_cpu(cur_bc.vl[i].dedicated)) 11478 set_vl_dedicated(dd, i, 11479 be16_to_cpu(new_bc-> 11480 vl[i].dedicated)); 11481 } 11482 } 11483 11484 /* next raise all shared that are going up */ 11485 for (i = 0; i < NUM_USABLE_VLS; i++) { 11486 if (!valid_vl(i)) 11487 continue; 11488 11489 if (be16_to_cpu(new_bc->vl[i].shared) > 11490 be16_to_cpu(cur_bc.vl[i].shared)) 11491 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared)); 11492 } 11493 11494 /* finally raise the global shared */ 11495 if (be16_to_cpu(new_bc->overall_shared_limit) > 11496 be16_to_cpu(cur_bc.overall_shared_limit)) 11497 set_global_shared(dd, 11498 be16_to_cpu(new_bc->overall_shared_limit)); 11499 11500 /* bracket the credit change with a total adjustment */ 11501 if (new_total < cur_total) 11502 set_global_limit(dd, new_total); 11503 11504 /* 11505 * Determine the actual number of operational VLS using the number of 11506 * dedicated and shared credits for each VL. 11507 */ 11508 if (change_count > 0) { 11509 for (i = 0; i < TXE_NUM_DATA_VL; i++) 11510 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 || 11511 be16_to_cpu(new_bc->vl[i].shared) > 0) 11512 vl_count++; 11513 ppd->actual_vls_operational = vl_count; 11514 ret = sdma_map_init(dd, ppd->port - 1, vl_count ? 11515 ppd->actual_vls_operational : 11516 ppd->vls_operational, 11517 NULL); 11518 if (ret == 0) 11519 ret = pio_map_init(dd, ppd->port - 1, vl_count ? 11520 ppd->actual_vls_operational : 11521 ppd->vls_operational, NULL); 11522 if (ret) 11523 return ret; 11524 } 11525 return 0; 11526 } 11527 11528 /* 11529 * Read the given fabric manager table. Return the size of the 11530 * table (in bytes) on success, and a negative error code on 11531 * failure. 11532 */ 11533 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t) 11534 11535 { 11536 int size; 11537 struct vl_arb_cache *vlc; 11538 11539 switch (which) { 11540 case FM_TBL_VL_HIGH_ARB: 11541 size = 256; 11542 /* 11543 * OPA specifies 128 elements (of 2 bytes each), though 11544 * HFI supports only 16 elements in h/w. 11545 */ 11546 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11547 vl_arb_get_cache(vlc, t); 11548 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11549 break; 11550 case FM_TBL_VL_LOW_ARB: 11551 size = 256; 11552 /* 11553 * OPA specifies 128 elements (of 2 bytes each), though 11554 * HFI supports only 16 elements in h/w. 11555 */ 11556 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11557 vl_arb_get_cache(vlc, t); 11558 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11559 break; 11560 case FM_TBL_BUFFER_CONTROL: 11561 size = get_buffer_control(ppd->dd, t, NULL); 11562 break; 11563 case FM_TBL_SC2VLNT: 11564 size = get_sc2vlnt(ppd->dd, t); 11565 break; 11566 case FM_TBL_VL_PREEMPT_ELEMS: 11567 size = 256; 11568 /* OPA specifies 128 elements, of 2 bytes each */ 11569 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t); 11570 break; 11571 case FM_TBL_VL_PREEMPT_MATRIX: 11572 size = 256; 11573 /* 11574 * OPA specifies that this is the same size as the VL 11575 * arbitration tables (i.e., 256 bytes). 11576 */ 11577 break; 11578 default: 11579 return -EINVAL; 11580 } 11581 return size; 11582 } 11583 11584 /* 11585 * Write the given fabric manager table. 11586 */ 11587 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t) 11588 { 11589 int ret = 0; 11590 struct vl_arb_cache *vlc; 11591 11592 switch (which) { 11593 case FM_TBL_VL_HIGH_ARB: 11594 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE); 11595 if (vl_arb_match_cache(vlc, t)) { 11596 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11597 break; 11598 } 11599 vl_arb_set_cache(vlc, t); 11600 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE); 11601 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST, 11602 VL_ARB_HIGH_PRIO_TABLE_SIZE, t); 11603 break; 11604 case FM_TBL_VL_LOW_ARB: 11605 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE); 11606 if (vl_arb_match_cache(vlc, t)) { 11607 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11608 break; 11609 } 11610 vl_arb_set_cache(vlc, t); 11611 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE); 11612 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST, 11613 VL_ARB_LOW_PRIO_TABLE_SIZE, t); 11614 break; 11615 case FM_TBL_BUFFER_CONTROL: 11616 ret = set_buffer_control(ppd, t); 11617 break; 11618 case FM_TBL_SC2VLNT: 11619 set_sc2vlnt(ppd->dd, t); 11620 break; 11621 default: 11622 ret = -EINVAL; 11623 } 11624 return ret; 11625 } 11626 11627 /* 11628 * Disable all data VLs. 11629 * 11630 * Return 0 if disabled, non-zero if the VLs cannot be disabled. 11631 */ 11632 static int disable_data_vls(struct hfi1_devdata *dd) 11633 { 11634 if (is_ax(dd)) 11635 return 1; 11636 11637 pio_send_control(dd, PSC_DATA_VL_DISABLE); 11638 11639 return 0; 11640 } 11641 11642 /* 11643 * open_fill_data_vls() - the counterpart to stop_drain_data_vls(). 11644 * Just re-enables all data VLs (the "fill" part happens 11645 * automatically - the name was chosen for symmetry with 11646 * stop_drain_data_vls()). 11647 * 11648 * Return 0 if successful, non-zero if the VLs cannot be enabled. 11649 */ 11650 int open_fill_data_vls(struct hfi1_devdata *dd) 11651 { 11652 if (is_ax(dd)) 11653 return 1; 11654 11655 pio_send_control(dd, PSC_DATA_VL_ENABLE); 11656 11657 return 0; 11658 } 11659 11660 /* 11661 * drain_data_vls() - assumes that disable_data_vls() has been called, 11662 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA 11663 * engines to drop to 0. 11664 */ 11665 static void drain_data_vls(struct hfi1_devdata *dd) 11666 { 11667 sc_wait(dd); 11668 sdma_wait(dd); 11669 pause_for_credit_return(dd); 11670 } 11671 11672 /* 11673 * stop_drain_data_vls() - disable, then drain all per-VL fifos. 11674 * 11675 * Use open_fill_data_vls() to resume using data VLs. This pair is 11676 * meant to be used like this: 11677 * 11678 * stop_drain_data_vls(dd); 11679 * // do things with per-VL resources 11680 * open_fill_data_vls(dd); 11681 */ 11682 int stop_drain_data_vls(struct hfi1_devdata *dd) 11683 { 11684 int ret; 11685 11686 ret = disable_data_vls(dd); 11687 if (ret == 0) 11688 drain_data_vls(dd); 11689 11690 return ret; 11691 } 11692 11693 /* 11694 * Convert a nanosecond time to a cclock count. No matter how slow 11695 * the cclock, a non-zero ns will always have a non-zero result. 11696 */ 11697 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns) 11698 { 11699 u32 cclocks; 11700 11701 if (dd->icode == ICODE_FPGA_EMULATION) 11702 cclocks = (ns * 1000) / FPGA_CCLOCK_PS; 11703 else /* simulation pretends to be ASIC */ 11704 cclocks = (ns * 1000) / ASIC_CCLOCK_PS; 11705 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */ 11706 cclocks = 1; 11707 return cclocks; 11708 } 11709 11710 /* 11711 * Convert a cclock count to nanoseconds. Not matter how slow 11712 * the cclock, a non-zero cclocks will always have a non-zero result. 11713 */ 11714 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks) 11715 { 11716 u32 ns; 11717 11718 if (dd->icode == ICODE_FPGA_EMULATION) 11719 ns = (cclocks * FPGA_CCLOCK_PS) / 1000; 11720 else /* simulation pretends to be ASIC */ 11721 ns = (cclocks * ASIC_CCLOCK_PS) / 1000; 11722 if (cclocks && !ns) 11723 ns = 1; 11724 return ns; 11725 } 11726 11727 /* 11728 * Dynamically adjust the receive interrupt timeout for a context based on 11729 * incoming packet rate. 11730 * 11731 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero. 11732 */ 11733 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts) 11734 { 11735 struct hfi1_devdata *dd = rcd->dd; 11736 u32 timeout = rcd->rcvavail_timeout; 11737 11738 /* 11739 * This algorithm doubles or halves the timeout depending on whether 11740 * the number of packets received in this interrupt were less than or 11741 * greater equal the interrupt count. 11742 * 11743 * The calculations below do not allow a steady state to be achieved. 11744 * Only at the endpoints it is possible to have an unchanging 11745 * timeout. 11746 */ 11747 if (npkts < rcv_intr_count) { 11748 /* 11749 * Not enough packets arrived before the timeout, adjust 11750 * timeout downward. 11751 */ 11752 if (timeout < 2) /* already at minimum? */ 11753 return; 11754 timeout >>= 1; 11755 } else { 11756 /* 11757 * More than enough packets arrived before the timeout, adjust 11758 * timeout upward. 11759 */ 11760 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */ 11761 return; 11762 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr); 11763 } 11764 11765 rcd->rcvavail_timeout = timeout; 11766 /* 11767 * timeout cannot be larger than rcv_intr_timeout_csr which has already 11768 * been verified to be in range 11769 */ 11770 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT, 11771 (u64)timeout << 11772 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 11773 } 11774 11775 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, 11776 u32 intr_adjust, u32 npkts) 11777 { 11778 struct hfi1_devdata *dd = rcd->dd; 11779 u64 reg; 11780 u32 ctxt = rcd->ctxt; 11781 11782 /* 11783 * Need to write timeout register before updating RcvHdrHead to ensure 11784 * that a new value is used when the HW decides to restart counting. 11785 */ 11786 if (intr_adjust) 11787 adjust_rcv_timeout(rcd, npkts); 11788 if (updegr) { 11789 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK) 11790 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT; 11791 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg); 11792 } 11793 mmiowb(); 11794 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) | 11795 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK) 11796 << RCV_HDR_HEAD_HEAD_SHIFT); 11797 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 11798 mmiowb(); 11799 } 11800 11801 u32 hdrqempty(struct hfi1_ctxtdata *rcd) 11802 { 11803 u32 head, tail; 11804 11805 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD) 11806 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT; 11807 11808 if (rcd->rcvhdrtail_kvaddr) 11809 tail = get_rcvhdrtail(rcd); 11810 else 11811 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL); 11812 11813 return head == tail; 11814 } 11815 11816 /* 11817 * Context Control and Receive Array encoding for buffer size: 11818 * 0x0 invalid 11819 * 0x1 4 KB 11820 * 0x2 8 KB 11821 * 0x3 16 KB 11822 * 0x4 32 KB 11823 * 0x5 64 KB 11824 * 0x6 128 KB 11825 * 0x7 256 KB 11826 * 0x8 512 KB (Receive Array only) 11827 * 0x9 1 MB (Receive Array only) 11828 * 0xa 2 MB (Receive Array only) 11829 * 11830 * 0xB-0xF - reserved (Receive Array only) 11831 * 11832 * 11833 * This routine assumes that the value has already been sanity checked. 11834 */ 11835 static u32 encoded_size(u32 size) 11836 { 11837 switch (size) { 11838 case 4 * 1024: return 0x1; 11839 case 8 * 1024: return 0x2; 11840 case 16 * 1024: return 0x3; 11841 case 32 * 1024: return 0x4; 11842 case 64 * 1024: return 0x5; 11843 case 128 * 1024: return 0x6; 11844 case 256 * 1024: return 0x7; 11845 case 512 * 1024: return 0x8; 11846 case 1 * 1024 * 1024: return 0x9; 11847 case 2 * 1024 * 1024: return 0xa; 11848 } 11849 return 0x1; /* if invalid, go with the minimum size */ 11850 } 11851 11852 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, 11853 struct hfi1_ctxtdata *rcd) 11854 { 11855 u64 rcvctrl, reg; 11856 int did_enable = 0; 11857 u16 ctxt; 11858 11859 if (!rcd) 11860 return; 11861 11862 ctxt = rcd->ctxt; 11863 11864 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op); 11865 11866 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL); 11867 /* if the context already enabled, don't do the extra steps */ 11868 if ((op & HFI1_RCVCTRL_CTXT_ENB) && 11869 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) { 11870 /* reset the tail and hdr addresses, and sequence count */ 11871 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR, 11872 rcd->rcvhdrq_dma); 11873 if (rcd->rcvhdrtail_kvaddr) 11874 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11875 rcd->rcvhdrqtailaddr_dma); 11876 rcd->seq_cnt = 1; 11877 11878 /* reset the cached receive header queue head value */ 11879 rcd->head = 0; 11880 11881 /* 11882 * Zero the receive header queue so we don't get false 11883 * positives when checking the sequence number. The 11884 * sequence numbers could land exactly on the same spot. 11885 * E.g. a rcd restart before the receive header wrapped. 11886 */ 11887 memset(rcd->rcvhdrq, 0, rcvhdrq_size(rcd)); 11888 11889 /* starting timeout */ 11890 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr; 11891 11892 /* enable the context */ 11893 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK; 11894 11895 /* clean the egr buffer size first */ 11896 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 11897 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size) 11898 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK) 11899 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT; 11900 11901 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */ 11902 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0); 11903 did_enable = 1; 11904 11905 /* zero RcvEgrIndexHead */ 11906 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0); 11907 11908 /* set eager count and base index */ 11909 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT) 11910 & RCV_EGR_CTRL_EGR_CNT_MASK) 11911 << RCV_EGR_CTRL_EGR_CNT_SHIFT) | 11912 (((rcd->eager_base >> RCV_SHIFT) 11913 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK) 11914 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT); 11915 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg); 11916 11917 /* 11918 * Set TID (expected) count and base index. 11919 * rcd->expected_count is set to individual RcvArray entries, 11920 * not pairs, and the CSR takes a pair-count in groups of 11921 * four, so divide by 8. 11922 */ 11923 reg = (((rcd->expected_count >> RCV_SHIFT) 11924 & RCV_TID_CTRL_TID_PAIR_CNT_MASK) 11925 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) | 11926 (((rcd->expected_base >> RCV_SHIFT) 11927 & RCV_TID_CTRL_TID_BASE_INDEX_MASK) 11928 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT); 11929 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg); 11930 if (ctxt == HFI1_CTRL_CTXT) 11931 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); 11932 } 11933 if (op & HFI1_RCVCTRL_CTXT_DIS) { 11934 write_csr(dd, RCV_VL15, 0); 11935 /* 11936 * When receive context is being disabled turn on tail 11937 * update with a dummy tail address and then disable 11938 * receive context. 11939 */ 11940 if (dd->rcvhdrtail_dummy_dma) { 11941 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 11942 dd->rcvhdrtail_dummy_dma); 11943 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */ 11944 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11945 } 11946 11947 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK; 11948 } 11949 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB) { 11950 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt, 11951 IS_RCVAVAIL_START + rcd->ctxt, true); 11952 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 11953 } 11954 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS) { 11955 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt, 11956 IS_RCVAVAIL_START + rcd->ctxt, false); 11957 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK; 11958 } 11959 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && rcd->rcvhdrtail_kvaddr) 11960 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11961 if (op & HFI1_RCVCTRL_TAILUPD_DIS) { 11962 /* See comment on RcvCtxtCtrl.TailUpd above */ 11963 if (!(op & HFI1_RCVCTRL_CTXT_DIS)) 11964 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK; 11965 } 11966 if (op & HFI1_RCVCTRL_TIDFLOW_ENB) 11967 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 11968 if (op & HFI1_RCVCTRL_TIDFLOW_DIS) 11969 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK; 11970 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) { 11971 /* 11972 * In one-packet-per-eager mode, the size comes from 11973 * the RcvArray entry. 11974 */ 11975 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK; 11976 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 11977 } 11978 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS) 11979 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK; 11980 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB) 11981 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 11982 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS) 11983 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK; 11984 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB) 11985 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 11986 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS) 11987 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK; 11988 if (op & HFI1_RCVCTRL_URGENT_ENB) 11989 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt, 11990 IS_RCVURGENT_START + rcd->ctxt, true); 11991 if (op & HFI1_RCVCTRL_URGENT_DIS) 11992 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt, 11993 IS_RCVURGENT_START + rcd->ctxt, false); 11994 11995 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl); 11996 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcvctrl); 11997 11998 /* work around sticky RcvCtxtStatus.BlockedRHQFull */ 11999 if (did_enable && 12000 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) { 12001 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 12002 if (reg != 0) { 12003 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n", 12004 ctxt, reg); 12005 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 12006 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10); 12007 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00); 12008 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD); 12009 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); 12010 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n", 12011 ctxt, reg, reg == 0 ? "not" : "still"); 12012 } 12013 } 12014 12015 if (did_enable) { 12016 /* 12017 * The interrupt timeout and count must be set after 12018 * the context is enabled to take effect. 12019 */ 12020 /* set interrupt timeout */ 12021 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT, 12022 (u64)rcd->rcvavail_timeout << 12023 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT); 12024 12025 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */ 12026 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT; 12027 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); 12028 } 12029 12030 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS)) 12031 /* 12032 * If the context has been disabled and the Tail Update has 12033 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address 12034 * so it doesn't contain an address that is invalid. 12035 */ 12036 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR, 12037 dd->rcvhdrtail_dummy_dma); 12038 } 12039 12040 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp) 12041 { 12042 int ret; 12043 u64 val = 0; 12044 12045 if (namep) { 12046 ret = dd->cntrnameslen; 12047 *namep = dd->cntrnames; 12048 } else { 12049 const struct cntr_entry *entry; 12050 int i, j; 12051 12052 ret = (dd->ndevcntrs) * sizeof(u64); 12053 12054 /* Get the start of the block of counters */ 12055 *cntrp = dd->cntrs; 12056 12057 /* 12058 * Now go and fill in each counter in the block. 12059 */ 12060 for (i = 0; i < DEV_CNTR_LAST; i++) { 12061 entry = &dev_cntrs[i]; 12062 hfi1_cdbg(CNTR, "reading %s", entry->name); 12063 if (entry->flags & CNTR_DISABLED) { 12064 /* Nothing */ 12065 hfi1_cdbg(CNTR, "\tDisabled\n"); 12066 } else { 12067 if (entry->flags & CNTR_VL) { 12068 hfi1_cdbg(CNTR, "\tPer VL\n"); 12069 for (j = 0; j < C_VL_COUNT; j++) { 12070 val = entry->rw_cntr(entry, 12071 dd, j, 12072 CNTR_MODE_R, 12073 0); 12074 hfi1_cdbg( 12075 CNTR, 12076 "\t\tRead 0x%llx for %d\n", 12077 val, j); 12078 dd->cntrs[entry->offset + j] = 12079 val; 12080 } 12081 } else if (entry->flags & CNTR_SDMA) { 12082 hfi1_cdbg(CNTR, 12083 "\t Per SDMA Engine\n"); 12084 for (j = 0; j < chip_sdma_engines(dd); 12085 j++) { 12086 val = 12087 entry->rw_cntr(entry, dd, j, 12088 CNTR_MODE_R, 0); 12089 hfi1_cdbg(CNTR, 12090 "\t\tRead 0x%llx for %d\n", 12091 val, j); 12092 dd->cntrs[entry->offset + j] = 12093 val; 12094 } 12095 } else { 12096 val = entry->rw_cntr(entry, dd, 12097 CNTR_INVALID_VL, 12098 CNTR_MODE_R, 0); 12099 dd->cntrs[entry->offset] = val; 12100 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12101 } 12102 } 12103 } 12104 } 12105 return ret; 12106 } 12107 12108 /* 12109 * Used by sysfs to create files for hfi stats to read 12110 */ 12111 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp) 12112 { 12113 int ret; 12114 u64 val = 0; 12115 12116 if (namep) { 12117 ret = ppd->dd->portcntrnameslen; 12118 *namep = ppd->dd->portcntrnames; 12119 } else { 12120 const struct cntr_entry *entry; 12121 int i, j; 12122 12123 ret = ppd->dd->nportcntrs * sizeof(u64); 12124 *cntrp = ppd->cntrs; 12125 12126 for (i = 0; i < PORT_CNTR_LAST; i++) { 12127 entry = &port_cntrs[i]; 12128 hfi1_cdbg(CNTR, "reading %s", entry->name); 12129 if (entry->flags & CNTR_DISABLED) { 12130 /* Nothing */ 12131 hfi1_cdbg(CNTR, "\tDisabled\n"); 12132 continue; 12133 } 12134 12135 if (entry->flags & CNTR_VL) { 12136 hfi1_cdbg(CNTR, "\tPer VL"); 12137 for (j = 0; j < C_VL_COUNT; j++) { 12138 val = entry->rw_cntr(entry, ppd, j, 12139 CNTR_MODE_R, 12140 0); 12141 hfi1_cdbg( 12142 CNTR, 12143 "\t\tRead 0x%llx for %d", 12144 val, j); 12145 ppd->cntrs[entry->offset + j] = val; 12146 } 12147 } else { 12148 val = entry->rw_cntr(entry, ppd, 12149 CNTR_INVALID_VL, 12150 CNTR_MODE_R, 12151 0); 12152 ppd->cntrs[entry->offset] = val; 12153 hfi1_cdbg(CNTR, "\tRead 0x%llx", val); 12154 } 12155 } 12156 } 12157 return ret; 12158 } 12159 12160 static void free_cntrs(struct hfi1_devdata *dd) 12161 { 12162 struct hfi1_pportdata *ppd; 12163 int i; 12164 12165 if (dd->synth_stats_timer.function) 12166 del_timer_sync(&dd->synth_stats_timer); 12167 ppd = (struct hfi1_pportdata *)(dd + 1); 12168 for (i = 0; i < dd->num_pports; i++, ppd++) { 12169 kfree(ppd->cntrs); 12170 kfree(ppd->scntrs); 12171 free_percpu(ppd->ibport_data.rvp.rc_acks); 12172 free_percpu(ppd->ibport_data.rvp.rc_qacks); 12173 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp); 12174 ppd->cntrs = NULL; 12175 ppd->scntrs = NULL; 12176 ppd->ibport_data.rvp.rc_acks = NULL; 12177 ppd->ibport_data.rvp.rc_qacks = NULL; 12178 ppd->ibport_data.rvp.rc_delayed_comp = NULL; 12179 } 12180 kfree(dd->portcntrnames); 12181 dd->portcntrnames = NULL; 12182 kfree(dd->cntrs); 12183 dd->cntrs = NULL; 12184 kfree(dd->scntrs); 12185 dd->scntrs = NULL; 12186 kfree(dd->cntrnames); 12187 dd->cntrnames = NULL; 12188 if (dd->update_cntr_wq) { 12189 destroy_workqueue(dd->update_cntr_wq); 12190 dd->update_cntr_wq = NULL; 12191 } 12192 } 12193 12194 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry, 12195 u64 *psval, void *context, int vl) 12196 { 12197 u64 val; 12198 u64 sval = *psval; 12199 12200 if (entry->flags & CNTR_DISABLED) { 12201 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12202 return 0; 12203 } 12204 12205 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12206 12207 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0); 12208 12209 /* If its a synthetic counter there is more work we need to do */ 12210 if (entry->flags & CNTR_SYNTH) { 12211 if (sval == CNTR_MAX) { 12212 /* No need to read already saturated */ 12213 return CNTR_MAX; 12214 } 12215 12216 if (entry->flags & CNTR_32BIT) { 12217 /* 32bit counters can wrap multiple times */ 12218 u64 upper = sval >> 32; 12219 u64 lower = (sval << 32) >> 32; 12220 12221 if (lower > val) { /* hw wrapped */ 12222 if (upper == CNTR_32BIT_MAX) 12223 val = CNTR_MAX; 12224 else 12225 upper++; 12226 } 12227 12228 if (val != CNTR_MAX) 12229 val = (upper << 32) | val; 12230 12231 } else { 12232 /* If we rolled we are saturated */ 12233 if ((val < sval) || (val > CNTR_MAX)) 12234 val = CNTR_MAX; 12235 } 12236 } 12237 12238 *psval = val; 12239 12240 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12241 12242 return val; 12243 } 12244 12245 static u64 write_dev_port_cntr(struct hfi1_devdata *dd, 12246 struct cntr_entry *entry, 12247 u64 *psval, void *context, int vl, u64 data) 12248 { 12249 u64 val; 12250 12251 if (entry->flags & CNTR_DISABLED) { 12252 dd_dev_err(dd, "Counter %s not enabled", entry->name); 12253 return 0; 12254 } 12255 12256 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval); 12257 12258 if (entry->flags & CNTR_SYNTH) { 12259 *psval = data; 12260 if (entry->flags & CNTR_32BIT) { 12261 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12262 (data << 32) >> 32); 12263 val = data; /* return the full 64bit value */ 12264 } else { 12265 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, 12266 data); 12267 } 12268 } else { 12269 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data); 12270 } 12271 12272 *psval = val; 12273 12274 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val); 12275 12276 return val; 12277 } 12278 12279 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl) 12280 { 12281 struct cntr_entry *entry; 12282 u64 *sval; 12283 12284 entry = &dev_cntrs[index]; 12285 sval = dd->scntrs + entry->offset; 12286 12287 if (vl != CNTR_INVALID_VL) 12288 sval += vl; 12289 12290 return read_dev_port_cntr(dd, entry, sval, dd, vl); 12291 } 12292 12293 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data) 12294 { 12295 struct cntr_entry *entry; 12296 u64 *sval; 12297 12298 entry = &dev_cntrs[index]; 12299 sval = dd->scntrs + entry->offset; 12300 12301 if (vl != CNTR_INVALID_VL) 12302 sval += vl; 12303 12304 return write_dev_port_cntr(dd, entry, sval, dd, vl, data); 12305 } 12306 12307 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl) 12308 { 12309 struct cntr_entry *entry; 12310 u64 *sval; 12311 12312 entry = &port_cntrs[index]; 12313 sval = ppd->scntrs + entry->offset; 12314 12315 if (vl != CNTR_INVALID_VL) 12316 sval += vl; 12317 12318 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12319 (index <= C_RCV_HDR_OVF_LAST)) { 12320 /* We do not want to bother for disabled contexts */ 12321 return 0; 12322 } 12323 12324 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl); 12325 } 12326 12327 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data) 12328 { 12329 struct cntr_entry *entry; 12330 u64 *sval; 12331 12332 entry = &port_cntrs[index]; 12333 sval = ppd->scntrs + entry->offset; 12334 12335 if (vl != CNTR_INVALID_VL) 12336 sval += vl; 12337 12338 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) && 12339 (index <= C_RCV_HDR_OVF_LAST)) { 12340 /* We do not want to bother for disabled contexts */ 12341 return 0; 12342 } 12343 12344 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data); 12345 } 12346 12347 static void do_update_synth_timer(struct work_struct *work) 12348 { 12349 u64 cur_tx; 12350 u64 cur_rx; 12351 u64 total_flits; 12352 u8 update = 0; 12353 int i, j, vl; 12354 struct hfi1_pportdata *ppd; 12355 struct cntr_entry *entry; 12356 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata, 12357 update_cntr_work); 12358 12359 /* 12360 * Rather than keep beating on the CSRs pick a minimal set that we can 12361 * check to watch for potential roll over. We can do this by looking at 12362 * the number of flits sent/recv. If the total flits exceeds 32bits then 12363 * we have to iterate all the counters and update. 12364 */ 12365 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12366 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12367 12368 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12369 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0); 12370 12371 hfi1_cdbg( 12372 CNTR, 12373 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n", 12374 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx); 12375 12376 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) { 12377 /* 12378 * May not be strictly necessary to update but it won't hurt and 12379 * simplifies the logic here. 12380 */ 12381 update = 1; 12382 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating", 12383 dd->unit); 12384 } else { 12385 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx); 12386 hfi1_cdbg(CNTR, 12387 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit, 12388 total_flits, (u64)CNTR_32BIT_MAX); 12389 if (total_flits >= CNTR_32BIT_MAX) { 12390 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating", 12391 dd->unit); 12392 update = 1; 12393 } 12394 } 12395 12396 if (update) { 12397 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit); 12398 for (i = 0; i < DEV_CNTR_LAST; i++) { 12399 entry = &dev_cntrs[i]; 12400 if (entry->flags & CNTR_VL) { 12401 for (vl = 0; vl < C_VL_COUNT; vl++) 12402 read_dev_cntr(dd, i, vl); 12403 } else { 12404 read_dev_cntr(dd, i, CNTR_INVALID_VL); 12405 } 12406 } 12407 ppd = (struct hfi1_pportdata *)(dd + 1); 12408 for (i = 0; i < dd->num_pports; i++, ppd++) { 12409 for (j = 0; j < PORT_CNTR_LAST; j++) { 12410 entry = &port_cntrs[j]; 12411 if (entry->flags & CNTR_VL) { 12412 for (vl = 0; vl < C_VL_COUNT; vl++) 12413 read_port_cntr(ppd, j, vl); 12414 } else { 12415 read_port_cntr(ppd, j, CNTR_INVALID_VL); 12416 } 12417 } 12418 } 12419 12420 /* 12421 * We want the value in the register. The goal is to keep track 12422 * of the number of "ticks" not the counter value. In other 12423 * words if the register rolls we want to notice it and go ahead 12424 * and force an update. 12425 */ 12426 entry = &dev_cntrs[C_DC_XMIT_FLITS]; 12427 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12428 CNTR_MODE_R, 0); 12429 12430 entry = &dev_cntrs[C_DC_RCV_FLITS]; 12431 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, 12432 CNTR_MODE_R, 0); 12433 12434 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx", 12435 dd->unit, dd->last_tx, dd->last_rx); 12436 12437 } else { 12438 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit); 12439 } 12440 } 12441 12442 static void update_synth_timer(struct timer_list *t) 12443 { 12444 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer); 12445 12446 queue_work(dd->update_cntr_wq, &dd->update_cntr_work); 12447 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12448 } 12449 12450 #define C_MAX_NAME 16 /* 15 chars + one for /0 */ 12451 static int init_cntrs(struct hfi1_devdata *dd) 12452 { 12453 int i, rcv_ctxts, j; 12454 size_t sz; 12455 char *p; 12456 char name[C_MAX_NAME]; 12457 struct hfi1_pportdata *ppd; 12458 const char *bit_type_32 = ",32"; 12459 const int bit_type_32_sz = strlen(bit_type_32); 12460 u32 sdma_engines = chip_sdma_engines(dd); 12461 12462 /* set up the stats timer; the add_timer is done at the end */ 12463 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0); 12464 12465 /***********************/ 12466 /* per device counters */ 12467 /***********************/ 12468 12469 /* size names and determine how many we have*/ 12470 dd->ndevcntrs = 0; 12471 sz = 0; 12472 12473 for (i = 0; i < DEV_CNTR_LAST; i++) { 12474 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12475 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name); 12476 continue; 12477 } 12478 12479 if (dev_cntrs[i].flags & CNTR_VL) { 12480 dev_cntrs[i].offset = dd->ndevcntrs; 12481 for (j = 0; j < C_VL_COUNT; j++) { 12482 snprintf(name, C_MAX_NAME, "%s%d", 12483 dev_cntrs[i].name, vl_from_idx(j)); 12484 sz += strlen(name); 12485 /* Add ",32" for 32-bit counters */ 12486 if (dev_cntrs[i].flags & CNTR_32BIT) 12487 sz += bit_type_32_sz; 12488 sz++; 12489 dd->ndevcntrs++; 12490 } 12491 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12492 dev_cntrs[i].offset = dd->ndevcntrs; 12493 for (j = 0; j < sdma_engines; j++) { 12494 snprintf(name, C_MAX_NAME, "%s%d", 12495 dev_cntrs[i].name, j); 12496 sz += strlen(name); 12497 /* Add ",32" for 32-bit counters */ 12498 if (dev_cntrs[i].flags & CNTR_32BIT) 12499 sz += bit_type_32_sz; 12500 sz++; 12501 dd->ndevcntrs++; 12502 } 12503 } else { 12504 /* +1 for newline. */ 12505 sz += strlen(dev_cntrs[i].name) + 1; 12506 /* Add ",32" for 32-bit counters */ 12507 if (dev_cntrs[i].flags & CNTR_32BIT) 12508 sz += bit_type_32_sz; 12509 dev_cntrs[i].offset = dd->ndevcntrs; 12510 dd->ndevcntrs++; 12511 } 12512 } 12513 12514 /* allocate space for the counter values */ 12515 dd->cntrs = kcalloc(dd->ndevcntrs + num_driver_cntrs, sizeof(u64), 12516 GFP_KERNEL); 12517 if (!dd->cntrs) 12518 goto bail; 12519 12520 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); 12521 if (!dd->scntrs) 12522 goto bail; 12523 12524 /* allocate space for the counter names */ 12525 dd->cntrnameslen = sz; 12526 dd->cntrnames = kmalloc(sz, GFP_KERNEL); 12527 if (!dd->cntrnames) 12528 goto bail; 12529 12530 /* fill in the names */ 12531 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) { 12532 if (dev_cntrs[i].flags & CNTR_DISABLED) { 12533 /* Nothing */ 12534 } else if (dev_cntrs[i].flags & CNTR_VL) { 12535 for (j = 0; j < C_VL_COUNT; j++) { 12536 snprintf(name, C_MAX_NAME, "%s%d", 12537 dev_cntrs[i].name, 12538 vl_from_idx(j)); 12539 memcpy(p, name, strlen(name)); 12540 p += strlen(name); 12541 12542 /* Counter is 32 bits */ 12543 if (dev_cntrs[i].flags & CNTR_32BIT) { 12544 memcpy(p, bit_type_32, bit_type_32_sz); 12545 p += bit_type_32_sz; 12546 } 12547 12548 *p++ = '\n'; 12549 } 12550 } else if (dev_cntrs[i].flags & CNTR_SDMA) { 12551 for (j = 0; j < sdma_engines; j++) { 12552 snprintf(name, C_MAX_NAME, "%s%d", 12553 dev_cntrs[i].name, j); 12554 memcpy(p, name, strlen(name)); 12555 p += strlen(name); 12556 12557 /* Counter is 32 bits */ 12558 if (dev_cntrs[i].flags & CNTR_32BIT) { 12559 memcpy(p, bit_type_32, bit_type_32_sz); 12560 p += bit_type_32_sz; 12561 } 12562 12563 *p++ = '\n'; 12564 } 12565 } else { 12566 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name)); 12567 p += strlen(dev_cntrs[i].name); 12568 12569 /* Counter is 32 bits */ 12570 if (dev_cntrs[i].flags & CNTR_32BIT) { 12571 memcpy(p, bit_type_32, bit_type_32_sz); 12572 p += bit_type_32_sz; 12573 } 12574 12575 *p++ = '\n'; 12576 } 12577 } 12578 12579 /*********************/ 12580 /* per port counters */ 12581 /*********************/ 12582 12583 /* 12584 * Go through the counters for the overflows and disable the ones we 12585 * don't need. This varies based on platform so we need to do it 12586 * dynamically here. 12587 */ 12588 rcv_ctxts = dd->num_rcv_contexts; 12589 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts; 12590 i <= C_RCV_HDR_OVF_LAST; i++) { 12591 port_cntrs[i].flags |= CNTR_DISABLED; 12592 } 12593 12594 /* size port counter names and determine how many we have*/ 12595 sz = 0; 12596 dd->nportcntrs = 0; 12597 for (i = 0; i < PORT_CNTR_LAST; i++) { 12598 if (port_cntrs[i].flags & CNTR_DISABLED) { 12599 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name); 12600 continue; 12601 } 12602 12603 if (port_cntrs[i].flags & CNTR_VL) { 12604 port_cntrs[i].offset = dd->nportcntrs; 12605 for (j = 0; j < C_VL_COUNT; j++) { 12606 snprintf(name, C_MAX_NAME, "%s%d", 12607 port_cntrs[i].name, vl_from_idx(j)); 12608 sz += strlen(name); 12609 /* Add ",32" for 32-bit counters */ 12610 if (port_cntrs[i].flags & CNTR_32BIT) 12611 sz += bit_type_32_sz; 12612 sz++; 12613 dd->nportcntrs++; 12614 } 12615 } else { 12616 /* +1 for newline */ 12617 sz += strlen(port_cntrs[i].name) + 1; 12618 /* Add ",32" for 32-bit counters */ 12619 if (port_cntrs[i].flags & CNTR_32BIT) 12620 sz += bit_type_32_sz; 12621 port_cntrs[i].offset = dd->nportcntrs; 12622 dd->nportcntrs++; 12623 } 12624 } 12625 12626 /* allocate space for the counter names */ 12627 dd->portcntrnameslen = sz; 12628 dd->portcntrnames = kmalloc(sz, GFP_KERNEL); 12629 if (!dd->portcntrnames) 12630 goto bail; 12631 12632 /* fill in port cntr names */ 12633 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) { 12634 if (port_cntrs[i].flags & CNTR_DISABLED) 12635 continue; 12636 12637 if (port_cntrs[i].flags & CNTR_VL) { 12638 for (j = 0; j < C_VL_COUNT; j++) { 12639 snprintf(name, C_MAX_NAME, "%s%d", 12640 port_cntrs[i].name, vl_from_idx(j)); 12641 memcpy(p, name, strlen(name)); 12642 p += strlen(name); 12643 12644 /* Counter is 32 bits */ 12645 if (port_cntrs[i].flags & CNTR_32BIT) { 12646 memcpy(p, bit_type_32, bit_type_32_sz); 12647 p += bit_type_32_sz; 12648 } 12649 12650 *p++ = '\n'; 12651 } 12652 } else { 12653 memcpy(p, port_cntrs[i].name, 12654 strlen(port_cntrs[i].name)); 12655 p += strlen(port_cntrs[i].name); 12656 12657 /* Counter is 32 bits */ 12658 if (port_cntrs[i].flags & CNTR_32BIT) { 12659 memcpy(p, bit_type_32, bit_type_32_sz); 12660 p += bit_type_32_sz; 12661 } 12662 12663 *p++ = '\n'; 12664 } 12665 } 12666 12667 /* allocate per port storage for counter values */ 12668 ppd = (struct hfi1_pportdata *)(dd + 1); 12669 for (i = 0; i < dd->num_pports; i++, ppd++) { 12670 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12671 if (!ppd->cntrs) 12672 goto bail; 12673 12674 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL); 12675 if (!ppd->scntrs) 12676 goto bail; 12677 } 12678 12679 /* CPU counters need to be allocated and zeroed */ 12680 if (init_cpu_counters(dd)) 12681 goto bail; 12682 12683 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d", 12684 WQ_MEM_RECLAIM, dd->unit); 12685 if (!dd->update_cntr_wq) 12686 goto bail; 12687 12688 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer); 12689 12690 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12691 return 0; 12692 bail: 12693 free_cntrs(dd); 12694 return -ENOMEM; 12695 } 12696 12697 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate) 12698 { 12699 switch (chip_lstate) { 12700 default: 12701 dd_dev_err(dd, 12702 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n", 12703 chip_lstate); 12704 /* fall through */ 12705 case LSTATE_DOWN: 12706 return IB_PORT_DOWN; 12707 case LSTATE_INIT: 12708 return IB_PORT_INIT; 12709 case LSTATE_ARMED: 12710 return IB_PORT_ARMED; 12711 case LSTATE_ACTIVE: 12712 return IB_PORT_ACTIVE; 12713 } 12714 } 12715 12716 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate) 12717 { 12718 /* look at the HFI meta-states only */ 12719 switch (chip_pstate & 0xf0) { 12720 default: 12721 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n", 12722 chip_pstate); 12723 /* fall through */ 12724 case PLS_DISABLED: 12725 return IB_PORTPHYSSTATE_DISABLED; 12726 case PLS_OFFLINE: 12727 return OPA_PORTPHYSSTATE_OFFLINE; 12728 case PLS_POLLING: 12729 return IB_PORTPHYSSTATE_POLLING; 12730 case PLS_CONFIGPHY: 12731 return IB_PORTPHYSSTATE_TRAINING; 12732 case PLS_LINKUP: 12733 return IB_PORTPHYSSTATE_LINKUP; 12734 case PLS_PHYTEST: 12735 return IB_PORTPHYSSTATE_PHY_TEST; 12736 } 12737 } 12738 12739 /* return the OPA port logical state name */ 12740 const char *opa_lstate_name(u32 lstate) 12741 { 12742 static const char * const port_logical_names[] = { 12743 "PORT_NOP", 12744 "PORT_DOWN", 12745 "PORT_INIT", 12746 "PORT_ARMED", 12747 "PORT_ACTIVE", 12748 "PORT_ACTIVE_DEFER", 12749 }; 12750 if (lstate < ARRAY_SIZE(port_logical_names)) 12751 return port_logical_names[lstate]; 12752 return "unknown"; 12753 } 12754 12755 /* return the OPA port physical state name */ 12756 const char *opa_pstate_name(u32 pstate) 12757 { 12758 static const char * const port_physical_names[] = { 12759 "PHYS_NOP", 12760 "reserved1", 12761 "PHYS_POLL", 12762 "PHYS_DISABLED", 12763 "PHYS_TRAINING", 12764 "PHYS_LINKUP", 12765 "PHYS_LINK_ERR_RECOVER", 12766 "PHYS_PHY_TEST", 12767 "reserved8", 12768 "PHYS_OFFLINE", 12769 "PHYS_GANGED", 12770 "PHYS_TEST", 12771 }; 12772 if (pstate < ARRAY_SIZE(port_physical_names)) 12773 return port_physical_names[pstate]; 12774 return "unknown"; 12775 } 12776 12777 /** 12778 * update_statusp - Update userspace status flag 12779 * @ppd: Port data structure 12780 * @state: port state information 12781 * 12782 * Actual port status is determined by the host_link_state value 12783 * in the ppd. 12784 * 12785 * host_link_state MUST be updated before updating the user space 12786 * statusp. 12787 */ 12788 static void update_statusp(struct hfi1_pportdata *ppd, u32 state) 12789 { 12790 /* 12791 * Set port status flags in the page mapped into userspace 12792 * memory. Do it here to ensure a reliable state - this is 12793 * the only function called by all state handling code. 12794 * Always set the flags due to the fact that the cache value 12795 * might have been changed explicitly outside of this 12796 * function. 12797 */ 12798 if (ppd->statusp) { 12799 switch (state) { 12800 case IB_PORT_DOWN: 12801 case IB_PORT_INIT: 12802 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | 12803 HFI1_STATUS_IB_READY); 12804 break; 12805 case IB_PORT_ARMED: 12806 *ppd->statusp |= HFI1_STATUS_IB_CONF; 12807 break; 12808 case IB_PORT_ACTIVE: 12809 *ppd->statusp |= HFI1_STATUS_IB_READY; 12810 break; 12811 } 12812 } 12813 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n", 12814 opa_lstate_name(state), state); 12815 } 12816 12817 /** 12818 * wait_logical_linkstate - wait for an IB link state change to occur 12819 * @ppd: port device 12820 * @state: the state to wait for 12821 * @msecs: the number of milliseconds to wait 12822 * 12823 * Wait up to msecs milliseconds for IB link state change to occur. 12824 * For now, take the easy polling route. 12825 * Returns 0 if state reached, otherwise -ETIMEDOUT. 12826 */ 12827 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state, 12828 int msecs) 12829 { 12830 unsigned long timeout; 12831 u32 new_state; 12832 12833 timeout = jiffies + msecs_to_jiffies(msecs); 12834 while (1) { 12835 new_state = chip_to_opa_lstate(ppd->dd, 12836 read_logical_state(ppd->dd)); 12837 if (new_state == state) 12838 break; 12839 if (time_after(jiffies, timeout)) { 12840 dd_dev_err(ppd->dd, 12841 "timeout waiting for link state 0x%x\n", 12842 state); 12843 return -ETIMEDOUT; 12844 } 12845 msleep(20); 12846 } 12847 12848 return 0; 12849 } 12850 12851 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state) 12852 { 12853 u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state); 12854 12855 dd_dev_info(ppd->dd, 12856 "physical state changed to %s (0x%x), phy 0x%x\n", 12857 opa_pstate_name(ib_pstate), ib_pstate, state); 12858 } 12859 12860 /* 12861 * Read the physical hardware link state and check if it matches host 12862 * drivers anticipated state. 12863 */ 12864 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state) 12865 { 12866 u32 read_state = read_physical_state(ppd->dd); 12867 12868 if (read_state == state) { 12869 log_state_transition(ppd, state); 12870 } else { 12871 dd_dev_err(ppd->dd, 12872 "anticipated phy link state 0x%x, read 0x%x\n", 12873 state, read_state); 12874 } 12875 } 12876 12877 /* 12878 * wait_physical_linkstate - wait for an physical link state change to occur 12879 * @ppd: port device 12880 * @state: the state to wait for 12881 * @msecs: the number of milliseconds to wait 12882 * 12883 * Wait up to msecs milliseconds for physical link state change to occur. 12884 * Returns 0 if state reached, otherwise -ETIMEDOUT. 12885 */ 12886 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state, 12887 int msecs) 12888 { 12889 u32 read_state; 12890 unsigned long timeout; 12891 12892 timeout = jiffies + msecs_to_jiffies(msecs); 12893 while (1) { 12894 read_state = read_physical_state(ppd->dd); 12895 if (read_state == state) 12896 break; 12897 if (time_after(jiffies, timeout)) { 12898 dd_dev_err(ppd->dd, 12899 "timeout waiting for phy link state 0x%x\n", 12900 state); 12901 return -ETIMEDOUT; 12902 } 12903 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12904 } 12905 12906 log_state_transition(ppd, state); 12907 return 0; 12908 } 12909 12910 /* 12911 * wait_phys_link_offline_quiet_substates - wait for any offline substate 12912 * @ppd: port device 12913 * @msecs: the number of milliseconds to wait 12914 * 12915 * Wait up to msecs milliseconds for any offline physical link 12916 * state change to occur. 12917 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 12918 */ 12919 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd, 12920 int msecs) 12921 { 12922 u32 read_state; 12923 unsigned long timeout; 12924 12925 timeout = jiffies + msecs_to_jiffies(msecs); 12926 while (1) { 12927 read_state = read_physical_state(ppd->dd); 12928 if ((read_state & 0xF0) == PLS_OFFLINE) 12929 break; 12930 if (time_after(jiffies, timeout)) { 12931 dd_dev_err(ppd->dd, 12932 "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n", 12933 read_state, msecs); 12934 return -ETIMEDOUT; 12935 } 12936 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12937 } 12938 12939 log_state_transition(ppd, read_state); 12940 return read_state; 12941 } 12942 12943 /* 12944 * wait_phys_link_out_of_offline - wait for any out of offline state 12945 * @ppd: port device 12946 * @msecs: the number of milliseconds to wait 12947 * 12948 * Wait up to msecs milliseconds for any out of offline physical link 12949 * state change to occur. 12950 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT. 12951 */ 12952 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd, 12953 int msecs) 12954 { 12955 u32 read_state; 12956 unsigned long timeout; 12957 12958 timeout = jiffies + msecs_to_jiffies(msecs); 12959 while (1) { 12960 read_state = read_physical_state(ppd->dd); 12961 if ((read_state & 0xF0) != PLS_OFFLINE) 12962 break; 12963 if (time_after(jiffies, timeout)) { 12964 dd_dev_err(ppd->dd, 12965 "timeout waiting for phy link out of offline. Read state 0x%x, %dms\n", 12966 read_state, msecs); 12967 return -ETIMEDOUT; 12968 } 12969 usleep_range(1950, 2050); /* sleep 2ms-ish */ 12970 } 12971 12972 log_state_transition(ppd, read_state); 12973 return read_state; 12974 } 12975 12976 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ 12977 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 12978 12979 #define SET_STATIC_RATE_CONTROL_SMASK(r) \ 12980 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) 12981 12982 void hfi1_init_ctxt(struct send_context *sc) 12983 { 12984 if (sc) { 12985 struct hfi1_devdata *dd = sc->dd; 12986 u64 reg; 12987 u8 set = (sc->type == SC_USER ? 12988 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) : 12989 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)); 12990 reg = read_kctxt_csr(dd, sc->hw_context, 12991 SEND_CTXT_CHECK_ENABLE); 12992 if (set) 12993 CLEAR_STATIC_RATE_CONTROL_SMASK(reg); 12994 else 12995 SET_STATIC_RATE_CONTROL_SMASK(reg); 12996 write_kctxt_csr(dd, sc->hw_context, 12997 SEND_CTXT_CHECK_ENABLE, reg); 12998 } 12999 } 13000 13001 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp) 13002 { 13003 int ret = 0; 13004 u64 reg; 13005 13006 if (dd->icode != ICODE_RTL_SILICON) { 13007 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL)) 13008 dd_dev_info(dd, "%s: tempsense not supported by HW\n", 13009 __func__); 13010 return -EINVAL; 13011 } 13012 reg = read_csr(dd, ASIC_STS_THERM); 13013 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) & 13014 ASIC_STS_THERM_CURR_TEMP_MASK); 13015 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) & 13016 ASIC_STS_THERM_LO_TEMP_MASK); 13017 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) & 13018 ASIC_STS_THERM_HI_TEMP_MASK); 13019 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) & 13020 ASIC_STS_THERM_CRIT_TEMP_MASK); 13021 /* triggers is a 3-bit value - 1 bit per trigger. */ 13022 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7); 13023 13024 return ret; 13025 } 13026 13027 /* ========================================================================= */ 13028 13029 /** 13030 * read_mod_write() - Calculate the IRQ register index and set/clear the bits 13031 * @dd: valid devdata 13032 * @src: IRQ source to determine register index from 13033 * @bits: the bits to set or clear 13034 * @set: true == set the bits, false == clear the bits 13035 * 13036 */ 13037 static void read_mod_write(struct hfi1_devdata *dd, u16 src, u64 bits, 13038 bool set) 13039 { 13040 u64 reg; 13041 u16 idx = src / BITS_PER_REGISTER; 13042 13043 spin_lock(&dd->irq_src_lock); 13044 reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); 13045 if (set) 13046 reg |= bits; 13047 else 13048 reg &= ~bits; 13049 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); 13050 spin_unlock(&dd->irq_src_lock); 13051 } 13052 13053 /** 13054 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources 13055 * @dd: valid devdata 13056 * @first: first IRQ source to set/clear 13057 * @last: last IRQ source (inclusive) to set/clear 13058 * @set: true == set the bits, false == clear the bits 13059 * 13060 * If first == last, set the exact source. 13061 */ 13062 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set) 13063 { 13064 u64 bits = 0; 13065 u64 bit; 13066 u16 src; 13067 13068 if (first > NUM_INTERRUPT_SOURCES || last > NUM_INTERRUPT_SOURCES) 13069 return -EINVAL; 13070 13071 if (last < first) 13072 return -ERANGE; 13073 13074 for (src = first; src <= last; src++) { 13075 bit = src % BITS_PER_REGISTER; 13076 /* wrapped to next register? */ 13077 if (!bit && bits) { 13078 read_mod_write(dd, src - 1, bits, set); 13079 bits = 0; 13080 } 13081 bits |= BIT_ULL(bit); 13082 } 13083 read_mod_write(dd, last, bits, set); 13084 13085 return 0; 13086 } 13087 13088 /* 13089 * Clear all interrupt sources on the chip. 13090 */ 13091 void clear_all_interrupts(struct hfi1_devdata *dd) 13092 { 13093 int i; 13094 13095 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13096 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); 13097 13098 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); 13099 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); 13100 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); 13101 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); 13102 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); 13103 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); 13104 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); 13105 for (i = 0; i < chip_send_contexts(dd); i++) 13106 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0); 13107 for (i = 0; i < chip_sdma_engines(dd); i++) 13108 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0); 13109 13110 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); 13111 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); 13112 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); 13113 } 13114 13115 /* 13116 * Remap the interrupt source from the general handler to the given MSI-X 13117 * interrupt. 13118 */ 13119 void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr) 13120 { 13121 u64 reg; 13122 int m, n; 13123 13124 /* clear from the handled mask of the general interrupt */ 13125 m = isrc / 64; 13126 n = isrc % 64; 13127 if (likely(m < CCE_NUM_INT_CSRS)) { 13128 dd->gi_mask[m] &= ~((u64)1 << n); 13129 } else { 13130 dd_dev_err(dd, "remap interrupt err\n"); 13131 return; 13132 } 13133 13134 /* direct the chip source to the given MSI-X interrupt */ 13135 m = isrc / 8; 13136 n = isrc % 8; 13137 reg = read_csr(dd, CCE_INT_MAP + (8 * m)); 13138 reg &= ~((u64)0xff << (8 * n)); 13139 reg |= ((u64)msix_intr & 0xff) << (8 * n); 13140 write_csr(dd, CCE_INT_MAP + (8 * m), reg); 13141 } 13142 13143 void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr) 13144 { 13145 /* 13146 * SDMA engine interrupt sources grouped by type, rather than 13147 * engine. Per-engine interrupts are as follows: 13148 * SDMA 13149 * SDMAProgress 13150 * SDMAIdle 13151 */ 13152 remap_intr(dd, IS_SDMA_START + engine, msix_intr); 13153 remap_intr(dd, IS_SDMA_PROGRESS_START + engine, msix_intr); 13154 remap_intr(dd, IS_SDMA_IDLE_START + engine, msix_intr); 13155 } 13156 13157 /* 13158 * Set the general handler to accept all interrupts, remap all 13159 * chip interrupts back to MSI-X 0. 13160 */ 13161 void reset_interrupts(struct hfi1_devdata *dd) 13162 { 13163 int i; 13164 13165 /* all interrupts handled by the general handler */ 13166 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13167 dd->gi_mask[i] = ~(u64)0; 13168 13169 /* all chip interrupts map to MSI-X 0 */ 13170 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13171 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13172 } 13173 13174 /** 13175 * set_up_interrupts() - Initialize the IRQ resources and state 13176 * @dd: valid devdata 13177 * 13178 */ 13179 static int set_up_interrupts(struct hfi1_devdata *dd) 13180 { 13181 int ret; 13182 13183 /* mask all interrupts */ 13184 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false); 13185 13186 /* clear all pending interrupts */ 13187 clear_all_interrupts(dd); 13188 13189 /* reset general handler mask, chip MSI-X mappings */ 13190 reset_interrupts(dd); 13191 13192 /* ask for MSI-X interrupts */ 13193 ret = msix_initialize(dd); 13194 if (ret) 13195 return ret; 13196 13197 ret = msix_request_irqs(dd); 13198 if (ret) 13199 msix_clean_up_interrupts(dd); 13200 13201 return ret; 13202 } 13203 13204 /* 13205 * Set up context values in dd. Sets: 13206 * 13207 * num_rcv_contexts - number of contexts being used 13208 * n_krcv_queues - number of kernel contexts 13209 * first_dyn_alloc_ctxt - first dynamically allocated context 13210 * in array of contexts 13211 * freectxts - number of free user contexts 13212 * num_send_contexts - number of PIO send contexts being used 13213 * num_vnic_contexts - number of contexts reserved for VNIC 13214 */ 13215 static int set_up_context_variables(struct hfi1_devdata *dd) 13216 { 13217 unsigned long num_kernel_contexts; 13218 u16 num_vnic_contexts = HFI1_NUM_VNIC_CTXT; 13219 int total_contexts; 13220 int ret; 13221 unsigned ngroups; 13222 int qos_rmt_count; 13223 int user_rmt_reduced; 13224 u32 n_usr_ctxts; 13225 u32 send_contexts = chip_send_contexts(dd); 13226 u32 rcv_contexts = chip_rcv_contexts(dd); 13227 13228 /* 13229 * Kernel receive contexts: 13230 * - Context 0 - control context (VL15/multicast/error) 13231 * - Context 1 - first kernel context 13232 * - Context 2 - second kernel context 13233 * ... 13234 */ 13235 if (n_krcvqs) 13236 /* 13237 * n_krcvqs is the sum of module parameter kernel receive 13238 * contexts, krcvqs[]. It does not include the control 13239 * context, so add that. 13240 */ 13241 num_kernel_contexts = n_krcvqs + 1; 13242 else 13243 num_kernel_contexts = DEFAULT_KRCVQS + 1; 13244 /* 13245 * Every kernel receive context needs an ACK send context. 13246 * one send context is allocated for each VL{0-7} and VL15 13247 */ 13248 if (num_kernel_contexts > (send_contexts - num_vls - 1)) { 13249 dd_dev_err(dd, 13250 "Reducing # kernel rcv contexts to: %d, from %lu\n", 13251 send_contexts - num_vls - 1, 13252 num_kernel_contexts); 13253 num_kernel_contexts = send_contexts - num_vls - 1; 13254 } 13255 13256 /* Accommodate VNIC contexts if possible */ 13257 if ((num_kernel_contexts + num_vnic_contexts) > rcv_contexts) { 13258 dd_dev_err(dd, "No receive contexts available for VNIC\n"); 13259 num_vnic_contexts = 0; 13260 } 13261 total_contexts = num_kernel_contexts + num_vnic_contexts; 13262 13263 /* 13264 * User contexts: 13265 * - default to 1 user context per real (non-HT) CPU core if 13266 * num_user_contexts is negative 13267 */ 13268 if (num_user_contexts < 0) 13269 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask); 13270 else 13271 n_usr_ctxts = num_user_contexts; 13272 /* 13273 * Adjust the counts given a global max. 13274 */ 13275 if (total_contexts + n_usr_ctxts > rcv_contexts) { 13276 dd_dev_err(dd, 13277 "Reducing # user receive contexts to: %d, from %u\n", 13278 rcv_contexts - total_contexts, 13279 n_usr_ctxts); 13280 /* recalculate */ 13281 n_usr_ctxts = rcv_contexts - total_contexts; 13282 } 13283 13284 /* each user context requires an entry in the RMT */ 13285 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL); 13286 if (qos_rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) { 13287 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count; 13288 dd_dev_err(dd, 13289 "RMT size is reducing the number of user receive contexts from %u to %d\n", 13290 n_usr_ctxts, 13291 user_rmt_reduced); 13292 /* recalculate */ 13293 n_usr_ctxts = user_rmt_reduced; 13294 } 13295 13296 total_contexts += n_usr_ctxts; 13297 13298 /* the first N are kernel contexts, the rest are user/vnic contexts */ 13299 dd->num_rcv_contexts = total_contexts; 13300 dd->n_krcv_queues = num_kernel_contexts; 13301 dd->first_dyn_alloc_ctxt = num_kernel_contexts; 13302 dd->num_vnic_contexts = num_vnic_contexts; 13303 dd->num_user_contexts = n_usr_ctxts; 13304 dd->freectxts = n_usr_ctxts; 13305 dd_dev_info(dd, 13306 "rcv contexts: chip %d, used %d (kernel %d, vnic %u, user %u)\n", 13307 rcv_contexts, 13308 (int)dd->num_rcv_contexts, 13309 (int)dd->n_krcv_queues, 13310 dd->num_vnic_contexts, 13311 dd->num_user_contexts); 13312 13313 /* 13314 * Receive array allocation: 13315 * All RcvArray entries are divided into groups of 8. This 13316 * is required by the hardware and will speed up writes to 13317 * consecutive entries by using write-combining of the entire 13318 * cacheline. 13319 * 13320 * The number of groups are evenly divided among all contexts. 13321 * any left over groups will be given to the first N user 13322 * contexts. 13323 */ 13324 dd->rcv_entries.group_size = RCV_INCREMENT; 13325 ngroups = chip_rcv_array_count(dd) / dd->rcv_entries.group_size; 13326 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts; 13327 dd->rcv_entries.nctxt_extra = ngroups - 13328 (dd->num_rcv_contexts * dd->rcv_entries.ngroups); 13329 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n", 13330 dd->rcv_entries.ngroups, 13331 dd->rcv_entries.nctxt_extra); 13332 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size > 13333 MAX_EAGER_ENTRIES * 2) { 13334 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) / 13335 dd->rcv_entries.group_size; 13336 dd_dev_info(dd, 13337 "RcvArray group count too high, change to %u\n", 13338 dd->rcv_entries.ngroups); 13339 dd->rcv_entries.nctxt_extra = 0; 13340 } 13341 /* 13342 * PIO send contexts 13343 */ 13344 ret = init_sc_pools_and_sizes(dd); 13345 if (ret >= 0) { /* success */ 13346 dd->num_send_contexts = ret; 13347 dd_dev_info( 13348 dd, 13349 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n", 13350 send_contexts, 13351 dd->num_send_contexts, 13352 dd->sc_sizes[SC_KERNEL].count, 13353 dd->sc_sizes[SC_ACK].count, 13354 dd->sc_sizes[SC_USER].count, 13355 dd->sc_sizes[SC_VL15].count); 13356 ret = 0; /* success */ 13357 } 13358 13359 return ret; 13360 } 13361 13362 /* 13363 * Set the device/port partition key table. The MAD code 13364 * will ensure that, at least, the partial management 13365 * partition key is present in the table. 13366 */ 13367 static void set_partition_keys(struct hfi1_pportdata *ppd) 13368 { 13369 struct hfi1_devdata *dd = ppd->dd; 13370 u64 reg = 0; 13371 int i; 13372 13373 dd_dev_info(dd, "Setting partition keys\n"); 13374 for (i = 0; i < hfi1_get_npkeys(dd); i++) { 13375 reg |= (ppd->pkeys[i] & 13376 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) << 13377 ((i % 4) * 13378 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT); 13379 /* Each register holds 4 PKey values. */ 13380 if ((i % 4) == 3) { 13381 write_csr(dd, RCV_PARTITION_KEY + 13382 ((i - 3) * 2), reg); 13383 reg = 0; 13384 } 13385 } 13386 13387 /* Always enable HW pkeys check when pkeys table is set */ 13388 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK); 13389 } 13390 13391 /* 13392 * These CSRs and memories are uninitialized on reset and must be 13393 * written before reading to set the ECC/parity bits. 13394 * 13395 * NOTE: All user context CSRs that are not mmaped write-only 13396 * (e.g. the TID flows) must be initialized even if the driver never 13397 * reads them. 13398 */ 13399 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd) 13400 { 13401 int i, j; 13402 13403 /* CceIntMap */ 13404 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13405 write_csr(dd, CCE_INT_MAP + (8 * i), 0); 13406 13407 /* SendCtxtCreditReturnAddr */ 13408 for (i = 0; i < chip_send_contexts(dd); i++) 13409 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13410 13411 /* PIO Send buffers */ 13412 /* SDMA Send buffers */ 13413 /* 13414 * These are not normally read, and (presently) have no method 13415 * to be read, so are not pre-initialized 13416 */ 13417 13418 /* RcvHdrAddr */ 13419 /* RcvHdrTailAddr */ 13420 /* RcvTidFlowTable */ 13421 for (i = 0; i < chip_rcv_contexts(dd); i++) { 13422 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13423 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13424 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) 13425 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0); 13426 } 13427 13428 /* RcvArray */ 13429 for (i = 0; i < chip_rcv_array_count(dd); i++) 13430 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0); 13431 13432 /* RcvQPMapTable */ 13433 for (i = 0; i < 32; i++) 13434 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13435 } 13436 13437 /* 13438 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus. 13439 */ 13440 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits, 13441 u64 ctrl_bits) 13442 { 13443 unsigned long timeout; 13444 u64 reg; 13445 13446 /* is the condition present? */ 13447 reg = read_csr(dd, CCE_STATUS); 13448 if ((reg & status_bits) == 0) 13449 return; 13450 13451 /* clear the condition */ 13452 write_csr(dd, CCE_CTRL, ctrl_bits); 13453 13454 /* wait for the condition to clear */ 13455 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT); 13456 while (1) { 13457 reg = read_csr(dd, CCE_STATUS); 13458 if ((reg & status_bits) == 0) 13459 return; 13460 if (time_after(jiffies, timeout)) { 13461 dd_dev_err(dd, 13462 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n", 13463 status_bits, reg & status_bits); 13464 return; 13465 } 13466 udelay(1); 13467 } 13468 } 13469 13470 /* set CCE CSRs to chip reset defaults */ 13471 static void reset_cce_csrs(struct hfi1_devdata *dd) 13472 { 13473 int i; 13474 13475 /* CCE_REVISION read-only */ 13476 /* CCE_REVISION2 read-only */ 13477 /* CCE_CTRL - bits clear automatically */ 13478 /* CCE_STATUS read-only, use CceCtrl to clear */ 13479 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK); 13480 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK); 13481 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK); 13482 for (i = 0; i < CCE_NUM_SCRATCH; i++) 13483 write_csr(dd, CCE_SCRATCH + (8 * i), 0); 13484 /* CCE_ERR_STATUS read-only */ 13485 write_csr(dd, CCE_ERR_MASK, 0); 13486 write_csr(dd, CCE_ERR_CLEAR, ~0ull); 13487 /* CCE_ERR_FORCE leave alone */ 13488 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++) 13489 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); 13490 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); 13491 /* CCE_PCIE_CTRL leave alone */ 13492 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) { 13493 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); 13494 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), 13495 CCE_MSIX_TABLE_UPPER_RESETCSR); 13496 } 13497 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) { 13498 /* CCE_MSIX_PBA read-only */ 13499 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); 13500 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); 13501 } 13502 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++) 13503 write_csr(dd, CCE_INT_MAP, 0); 13504 for (i = 0; i < CCE_NUM_INT_CSRS; i++) { 13505 /* CCE_INT_STATUS read-only */ 13506 write_csr(dd, CCE_INT_MASK + (8 * i), 0); 13507 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); 13508 /* CCE_INT_FORCE leave alone */ 13509 /* CCE_INT_BLOCKED read-only */ 13510 } 13511 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++) 13512 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); 13513 } 13514 13515 /* set MISC CSRs to chip reset defaults */ 13516 static void reset_misc_csrs(struct hfi1_devdata *dd) 13517 { 13518 int i; 13519 13520 for (i = 0; i < 32; i++) { 13521 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); 13522 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); 13523 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); 13524 } 13525 /* 13526 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can 13527 * only be written 128-byte chunks 13528 */ 13529 /* init RSA engine to clear lingering errors */ 13530 write_csr(dd, MISC_CFG_RSA_CMD, 1); 13531 write_csr(dd, MISC_CFG_RSA_MU, 0); 13532 write_csr(dd, MISC_CFG_FW_CTRL, 0); 13533 /* MISC_STS_8051_DIGEST read-only */ 13534 /* MISC_STS_SBM_DIGEST read-only */ 13535 /* MISC_STS_PCIE_DIGEST read-only */ 13536 /* MISC_STS_FAB_DIGEST read-only */ 13537 /* MISC_ERR_STATUS read-only */ 13538 write_csr(dd, MISC_ERR_MASK, 0); 13539 write_csr(dd, MISC_ERR_CLEAR, ~0ull); 13540 /* MISC_ERR_FORCE leave alone */ 13541 } 13542 13543 /* set TXE CSRs to chip reset defaults */ 13544 static void reset_txe_csrs(struct hfi1_devdata *dd) 13545 { 13546 int i; 13547 13548 /* 13549 * TXE Kernel CSRs 13550 */ 13551 write_csr(dd, SEND_CTRL, 0); 13552 __cm_reset(dd, 0); /* reset CM internal state */ 13553 /* SEND_CONTEXTS read-only */ 13554 /* SEND_DMA_ENGINES read-only */ 13555 /* SEND_PIO_MEM_SIZE read-only */ 13556 /* SEND_DMA_MEM_SIZE read-only */ 13557 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); 13558 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */ 13559 /* SEND_PIO_ERR_STATUS read-only */ 13560 write_csr(dd, SEND_PIO_ERR_MASK, 0); 13561 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); 13562 /* SEND_PIO_ERR_FORCE leave alone */ 13563 /* SEND_DMA_ERR_STATUS read-only */ 13564 write_csr(dd, SEND_DMA_ERR_MASK, 0); 13565 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); 13566 /* SEND_DMA_ERR_FORCE leave alone */ 13567 /* SEND_EGRESS_ERR_STATUS read-only */ 13568 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); 13569 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); 13570 /* SEND_EGRESS_ERR_FORCE leave alone */ 13571 write_csr(dd, SEND_BTH_QP, 0); 13572 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); 13573 write_csr(dd, SEND_SC2VLT0, 0); 13574 write_csr(dd, SEND_SC2VLT1, 0); 13575 write_csr(dd, SEND_SC2VLT2, 0); 13576 write_csr(dd, SEND_SC2VLT3, 0); 13577 write_csr(dd, SEND_LEN_CHECK0, 0); 13578 write_csr(dd, SEND_LEN_CHECK1, 0); 13579 /* SEND_ERR_STATUS read-only */ 13580 write_csr(dd, SEND_ERR_MASK, 0); 13581 write_csr(dd, SEND_ERR_CLEAR, ~0ull); 13582 /* SEND_ERR_FORCE read-only */ 13583 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++) 13584 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); 13585 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++) 13586 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); 13587 for (i = 0; i < chip_send_contexts(dd) / NUM_CONTEXTS_PER_SET; i++) 13588 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); 13589 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++) 13590 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); 13591 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++) 13592 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); 13593 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); 13594 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); 13595 /* SEND_CM_CREDIT_USED_STATUS read-only */ 13596 write_csr(dd, SEND_CM_TIMER_CTRL, 0); 13597 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); 13598 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); 13599 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); 13600 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); 13601 for (i = 0; i < TXE_NUM_DATA_VL; i++) 13602 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); 13603 write_csr(dd, SEND_CM_CREDIT_VL15, 0); 13604 /* SEND_CM_CREDIT_USED_VL read-only */ 13605 /* SEND_CM_CREDIT_USED_VL15 read-only */ 13606 /* SEND_EGRESS_CTXT_STATUS read-only */ 13607 /* SEND_EGRESS_SEND_DMA_STATUS read-only */ 13608 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); 13609 /* SEND_EGRESS_ERR_INFO read-only */ 13610 /* SEND_EGRESS_ERR_SOURCE read-only */ 13611 13612 /* 13613 * TXE Per-Context CSRs 13614 */ 13615 for (i = 0; i < chip_send_contexts(dd); i++) { 13616 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 13617 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0); 13618 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0); 13619 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0); 13620 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0); 13621 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull); 13622 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0); 13623 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0); 13624 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0); 13625 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0); 13626 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0); 13627 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0); 13628 } 13629 13630 /* 13631 * TXE Per-SDMA CSRs 13632 */ 13633 for (i = 0; i < chip_sdma_engines(dd); i++) { 13634 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 13635 /* SEND_DMA_STATUS read-only */ 13636 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0); 13637 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0); 13638 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0); 13639 /* SEND_DMA_HEAD read-only */ 13640 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0); 13641 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0); 13642 /* SEND_DMA_IDLE_CNT read-only */ 13643 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0); 13644 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0); 13645 /* SEND_DMA_DESC_FETCHED_CNT read-only */ 13646 /* SEND_DMA_ENG_ERR_STATUS read-only */ 13647 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0); 13648 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull); 13649 /* SEND_DMA_ENG_ERR_FORCE leave alone */ 13650 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0); 13651 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0); 13652 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0); 13653 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0); 13654 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0); 13655 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0); 13656 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0); 13657 } 13658 } 13659 13660 /* 13661 * Expect on entry: 13662 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0 13663 */ 13664 static void init_rbufs(struct hfi1_devdata *dd) 13665 { 13666 u64 reg; 13667 int count; 13668 13669 /* 13670 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are 13671 * clear. 13672 */ 13673 count = 0; 13674 while (1) { 13675 reg = read_csr(dd, RCV_STATUS); 13676 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 13677 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0) 13678 break; 13679 /* 13680 * Give up after 1ms - maximum wait time. 13681 * 13682 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at 13683 * 250MB/s bandwidth. Lower rate to 66% for overhead to get: 13684 * 136 KB / (66% * 250MB/s) = 844us 13685 */ 13686 if (count++ > 500) { 13687 dd_dev_err(dd, 13688 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n", 13689 __func__, reg); 13690 break; 13691 } 13692 udelay(2); /* do not busy-wait the CSR */ 13693 } 13694 13695 /* start the init - expect RcvCtrl to be 0 */ 13696 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); 13697 13698 /* 13699 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief 13700 * period after the write before RcvStatus.RxRbufInitDone is valid. 13701 * The delay in the first run through the loop below is sufficient and 13702 * required before the first read of RcvStatus.RxRbufInintDone. 13703 */ 13704 read_csr(dd, RCV_CTRL); 13705 13706 /* wait for the init to finish */ 13707 count = 0; 13708 while (1) { 13709 /* delay is required first time through - see above */ 13710 udelay(2); /* do not busy-wait the CSR */ 13711 reg = read_csr(dd, RCV_STATUS); 13712 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK)) 13713 break; 13714 13715 /* give up after 100us - slowest possible at 33MHz is 73us */ 13716 if (count++ > 50) { 13717 dd_dev_err(dd, 13718 "%s: RcvStatus.RxRbufInit not set, continuing\n", 13719 __func__); 13720 break; 13721 } 13722 } 13723 } 13724 13725 /* set RXE CSRs to chip reset defaults */ 13726 static void reset_rxe_csrs(struct hfi1_devdata *dd) 13727 { 13728 int i, j; 13729 13730 /* 13731 * RXE Kernel CSRs 13732 */ 13733 write_csr(dd, RCV_CTRL, 0); 13734 init_rbufs(dd); 13735 /* RCV_STATUS read-only */ 13736 /* RCV_CONTEXTS read-only */ 13737 /* RCV_ARRAY_CNT read-only */ 13738 /* RCV_BUF_SIZE read-only */ 13739 write_csr(dd, RCV_BTH_QP, 0); 13740 write_csr(dd, RCV_MULTICAST, 0); 13741 write_csr(dd, RCV_BYPASS, 0); 13742 write_csr(dd, RCV_VL15, 0); 13743 /* this is a clear-down */ 13744 write_csr(dd, RCV_ERR_INFO, 13745 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK); 13746 /* RCV_ERR_STATUS read-only */ 13747 write_csr(dd, RCV_ERR_MASK, 0); 13748 write_csr(dd, RCV_ERR_CLEAR, ~0ull); 13749 /* RCV_ERR_FORCE leave alone */ 13750 for (i = 0; i < 32; i++) 13751 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); 13752 for (i = 0; i < 4; i++) 13753 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); 13754 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++) 13755 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); 13756 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++) 13757 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); 13758 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) 13759 clear_rsm_rule(dd, i); 13760 for (i = 0; i < 32; i++) 13761 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); 13762 13763 /* 13764 * RXE Kernel and User Per-Context CSRs 13765 */ 13766 for (i = 0; i < chip_rcv_contexts(dd); i++) { 13767 /* kernel */ 13768 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0); 13769 /* RCV_CTXT_STATUS read-only */ 13770 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0); 13771 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0); 13772 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0); 13773 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0); 13774 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0); 13775 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0); 13776 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0); 13777 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0); 13778 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0); 13779 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0); 13780 13781 /* user */ 13782 /* RCV_HDR_TAIL read-only */ 13783 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0); 13784 /* RCV_EGR_INDEX_TAIL read-only */ 13785 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0); 13786 /* RCV_EGR_OFFSET_TAIL read-only */ 13787 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) { 13788 write_uctxt_csr(dd, i, 13789 RCV_TID_FLOW_TABLE + (8 * j), 0); 13790 } 13791 } 13792 } 13793 13794 /* 13795 * Set sc2vl tables. 13796 * 13797 * They power on to zeros, so to avoid send context errors 13798 * they need to be set: 13799 * 13800 * SC 0-7 -> VL 0-7 (respectively) 13801 * SC 15 -> VL 15 13802 * otherwise 13803 * -> VL 0 13804 */ 13805 static void init_sc2vl_tables(struct hfi1_devdata *dd) 13806 { 13807 int i; 13808 /* init per architecture spec, constrained by hardware capability */ 13809 13810 /* HFI maps sent packets */ 13811 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( 13812 0, 13813 0, 0, 1, 1, 13814 2, 2, 3, 3, 13815 4, 4, 5, 5, 13816 6, 6, 7, 7)); 13817 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( 13818 1, 13819 8, 0, 9, 0, 13820 10, 0, 11, 0, 13821 12, 0, 13, 0, 13822 14, 0, 15, 15)); 13823 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( 13824 2, 13825 16, 0, 17, 0, 13826 18, 0, 19, 0, 13827 20, 0, 21, 0, 13828 22, 0, 23, 0)); 13829 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( 13830 3, 13831 24, 0, 25, 0, 13832 26, 0, 27, 0, 13833 28, 0, 29, 0, 13834 30, 0, 31, 0)); 13835 13836 /* DC maps received packets */ 13837 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( 13838 15_0, 13839 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 13840 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15)); 13841 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( 13842 31_16, 13843 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0, 13844 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0)); 13845 13846 /* initialize the cached sc2vl values consistently with h/w */ 13847 for (i = 0; i < 32; i++) { 13848 if (i < 8 || i == 15) 13849 *((u8 *)(dd->sc2vl) + i) = (u8)i; 13850 else 13851 *((u8 *)(dd->sc2vl) + i) = 0; 13852 } 13853 } 13854 13855 /* 13856 * Read chip sizes and then reset parts to sane, disabled, values. We cannot 13857 * depend on the chip going through a power-on reset - a driver may be loaded 13858 * and unloaded many times. 13859 * 13860 * Do not write any CSR values to the chip in this routine - there may be 13861 * a reset following the (possible) FLR in this routine. 13862 * 13863 */ 13864 static int init_chip(struct hfi1_devdata *dd) 13865 { 13866 int i; 13867 int ret = 0; 13868 13869 /* 13870 * Put the HFI CSRs in a known state. 13871 * Combine this with a DC reset. 13872 * 13873 * Stop the device from doing anything while we do a 13874 * reset. We know there are no other active users of 13875 * the device since we are now in charge. Turn off 13876 * off all outbound and inbound traffic and make sure 13877 * the device does not generate any interrupts. 13878 */ 13879 13880 /* disable send contexts and SDMA engines */ 13881 write_csr(dd, SEND_CTRL, 0); 13882 for (i = 0; i < chip_send_contexts(dd); i++) 13883 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0); 13884 for (i = 0; i < chip_sdma_engines(dd); i++) 13885 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0); 13886 /* disable port (turn off RXE inbound traffic) and contexts */ 13887 write_csr(dd, RCV_CTRL, 0); 13888 for (i = 0; i < chip_rcv_contexts(dd); i++) 13889 write_csr(dd, RCV_CTXT_CTRL, 0); 13890 /* mask all interrupt sources */ 13891 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 13892 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); 13893 13894 /* 13895 * DC Reset: do a full DC reset before the register clear. 13896 * A recommended length of time to hold is one CSR read, 13897 * so reread the CceDcCtrl. Then, hold the DC in reset 13898 * across the clear. 13899 */ 13900 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 13901 (void)read_csr(dd, CCE_DC_CTRL); 13902 13903 if (use_flr) { 13904 /* 13905 * A FLR will reset the SPC core and part of the PCIe. 13906 * The parts that need to be restored have already been 13907 * saved. 13908 */ 13909 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 13910 13911 /* do the FLR, the DC reset will remain */ 13912 pcie_flr(dd->pcidev); 13913 13914 /* restore command and BARs */ 13915 ret = restore_pci_variables(dd); 13916 if (ret) { 13917 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 13918 __func__); 13919 return ret; 13920 } 13921 13922 if (is_ax(dd)) { 13923 dd_dev_info(dd, "Resetting CSRs with FLR\n"); 13924 pcie_flr(dd->pcidev); 13925 ret = restore_pci_variables(dd); 13926 if (ret) { 13927 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 13928 __func__); 13929 return ret; 13930 } 13931 } 13932 } else { 13933 dd_dev_info(dd, "Resetting CSRs with writes\n"); 13934 reset_cce_csrs(dd); 13935 reset_txe_csrs(dd); 13936 reset_rxe_csrs(dd); 13937 reset_misc_csrs(dd); 13938 } 13939 /* clear the DC reset */ 13940 write_csr(dd, CCE_DC_CTRL, 0); 13941 13942 /* Set the LED off */ 13943 setextled(dd, 0); 13944 13945 /* 13946 * Clear the QSFP reset. 13947 * An FLR enforces a 0 on all out pins. The driver does not touch 13948 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and 13949 * anything plugged constantly in reset, if it pays attention 13950 * to RESET_N. 13951 * Prime examples of this are optical cables. Set all pins high. 13952 * I2CCLK and I2CDAT will change per direction, and INT_N and 13953 * MODPRS_N are input only and their value is ignored. 13954 */ 13955 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); 13956 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); 13957 init_chip_resources(dd); 13958 return ret; 13959 } 13960 13961 static void init_early_variables(struct hfi1_devdata *dd) 13962 { 13963 int i; 13964 13965 /* assign link credit variables */ 13966 dd->vau = CM_VAU; 13967 dd->link_credits = CM_GLOBAL_CREDITS; 13968 if (is_ax(dd)) 13969 dd->link_credits--; 13970 dd->vcu = cu_to_vcu(hfi1_cu); 13971 /* enough room for 8 MAD packets plus header - 17K */ 13972 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau); 13973 if (dd->vl15_init > dd->link_credits) 13974 dd->vl15_init = dd->link_credits; 13975 13976 write_uninitialized_csrs_and_memories(dd); 13977 13978 if (HFI1_CAP_IS_KSET(PKEY_CHECK)) 13979 for (i = 0; i < dd->num_pports; i++) { 13980 struct hfi1_pportdata *ppd = &dd->pport[i]; 13981 13982 set_partition_keys(ppd); 13983 } 13984 init_sc2vl_tables(dd); 13985 } 13986 13987 static void init_kdeth_qp(struct hfi1_devdata *dd) 13988 { 13989 /* user changed the KDETH_QP */ 13990 if (kdeth_qp != 0 && kdeth_qp >= 0xff) { 13991 /* out of range or illegal value */ 13992 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring"); 13993 kdeth_qp = 0; 13994 } 13995 if (kdeth_qp == 0) /* not set, or failed range check */ 13996 kdeth_qp = DEFAULT_KDETH_QP; 13997 13998 write_csr(dd, SEND_BTH_QP, 13999 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) << 14000 SEND_BTH_QP_KDETH_QP_SHIFT); 14001 14002 write_csr(dd, RCV_BTH_QP, 14003 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) << 14004 RCV_BTH_QP_KDETH_QP_SHIFT); 14005 } 14006 14007 /** 14008 * init_qpmap_table 14009 * @dd - device data 14010 * @first_ctxt - first context 14011 * @last_ctxt - first context 14012 * 14013 * This return sets the qpn mapping table that 14014 * is indexed by qpn[8:1]. 14015 * 14016 * The routine will round robin the 256 settings 14017 * from first_ctxt to last_ctxt. 14018 * 14019 * The first/last looks ahead to having specialized 14020 * receive contexts for mgmt and bypass. Normal 14021 * verbs traffic will assumed to be on a range 14022 * of receive contexts. 14023 */ 14024 static void init_qpmap_table(struct hfi1_devdata *dd, 14025 u32 first_ctxt, 14026 u32 last_ctxt) 14027 { 14028 u64 reg = 0; 14029 u64 regno = RCV_QP_MAP_TABLE; 14030 int i; 14031 u64 ctxt = first_ctxt; 14032 14033 for (i = 0; i < 256; i++) { 14034 reg |= ctxt << (8 * (i % 8)); 14035 ctxt++; 14036 if (ctxt > last_ctxt) 14037 ctxt = first_ctxt; 14038 if (i % 8 == 7) { 14039 write_csr(dd, regno, reg); 14040 reg = 0; 14041 regno += 8; 14042 } 14043 } 14044 14045 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 14046 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK); 14047 } 14048 14049 struct rsm_map_table { 14050 u64 map[NUM_MAP_REGS]; 14051 unsigned int used; 14052 }; 14053 14054 struct rsm_rule_data { 14055 u8 offset; 14056 u8 pkt_type; 14057 u32 field1_off; 14058 u32 field2_off; 14059 u32 index1_off; 14060 u32 index1_width; 14061 u32 index2_off; 14062 u32 index2_width; 14063 u32 mask1; 14064 u32 value1; 14065 u32 mask2; 14066 u32 value2; 14067 }; 14068 14069 /* 14070 * Return an initialized RMT map table for users to fill in. OK if it 14071 * returns NULL, indicating no table. 14072 */ 14073 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd) 14074 { 14075 struct rsm_map_table *rmt; 14076 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */ 14077 14078 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL); 14079 if (rmt) { 14080 memset(rmt->map, rxcontext, sizeof(rmt->map)); 14081 rmt->used = 0; 14082 } 14083 14084 return rmt; 14085 } 14086 14087 /* 14088 * Write the final RMT map table to the chip and free the table. OK if 14089 * table is NULL. 14090 */ 14091 static void complete_rsm_map_table(struct hfi1_devdata *dd, 14092 struct rsm_map_table *rmt) 14093 { 14094 int i; 14095 14096 if (rmt) { 14097 /* write table to chip */ 14098 for (i = 0; i < NUM_MAP_REGS; i++) 14099 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); 14100 14101 /* enable RSM */ 14102 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14103 } 14104 } 14105 14106 /* 14107 * Add a receive side mapping rule. 14108 */ 14109 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index, 14110 struct rsm_rule_data *rrd) 14111 { 14112 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 14113 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT | 14114 1ull << rule_index | /* enable bit */ 14115 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT); 14116 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 14117 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT | 14118 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT | 14119 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT | 14120 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT | 14121 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT | 14122 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT); 14123 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 14124 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT | 14125 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT | 14126 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT | 14127 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT); 14128 } 14129 14130 /* 14131 * Clear a receive side mapping rule. 14132 */ 14133 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index) 14134 { 14135 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); 14136 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); 14137 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); 14138 } 14139 14140 /* return the number of RSM map table entries that will be used for QOS */ 14141 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp, 14142 unsigned int *np) 14143 { 14144 int i; 14145 unsigned int m, n; 14146 u8 max_by_vl = 0; 14147 14148 /* is QOS active at all? */ 14149 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS || 14150 num_vls == 1 || 14151 krcvqsset <= 1) 14152 goto no_qos; 14153 14154 /* determine bits for qpn */ 14155 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++) 14156 if (krcvqs[i] > max_by_vl) 14157 max_by_vl = krcvqs[i]; 14158 if (max_by_vl > 32) 14159 goto no_qos; 14160 m = ilog2(__roundup_pow_of_two(max_by_vl)); 14161 14162 /* determine bits for vl */ 14163 n = ilog2(__roundup_pow_of_two(num_vls)); 14164 14165 /* reject if too much is used */ 14166 if ((m + n) > 7) 14167 goto no_qos; 14168 14169 if (mp) 14170 *mp = m; 14171 if (np) 14172 *np = n; 14173 14174 return 1 << (m + n); 14175 14176 no_qos: 14177 if (mp) 14178 *mp = 0; 14179 if (np) 14180 *np = 0; 14181 return 0; 14182 } 14183 14184 /** 14185 * init_qos - init RX qos 14186 * @dd - device data 14187 * @rmt - RSM map table 14188 * 14189 * This routine initializes Rule 0 and the RSM map table to implement 14190 * quality of service (qos). 14191 * 14192 * If all of the limit tests succeed, qos is applied based on the array 14193 * interpretation of krcvqs where entry 0 is VL0. 14194 * 14195 * The number of vl bits (n) and the number of qpn bits (m) are computed to 14196 * feed both the RSM map table and the single rule. 14197 */ 14198 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt) 14199 { 14200 struct rsm_rule_data rrd; 14201 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m; 14202 unsigned int rmt_entries; 14203 u64 reg; 14204 14205 if (!rmt) 14206 goto bail; 14207 rmt_entries = qos_rmt_entries(dd, &m, &n); 14208 if (rmt_entries == 0) 14209 goto bail; 14210 qpns_per_vl = 1 << m; 14211 14212 /* enough room in the map table? */ 14213 rmt_entries = 1 << (m + n); 14214 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES) 14215 goto bail; 14216 14217 /* add qos entries to the the RSM map table */ 14218 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) { 14219 unsigned tctxt; 14220 14221 for (qpn = 0, tctxt = ctxt; 14222 krcvqs[i] && qpn < qpns_per_vl; qpn++) { 14223 unsigned idx, regoff, regidx; 14224 14225 /* generate the index the hardware will produce */ 14226 idx = rmt->used + ((qpn << n) ^ i); 14227 regoff = (idx % 8) * 8; 14228 regidx = idx / 8; 14229 /* replace default with context number */ 14230 reg = rmt->map[regidx]; 14231 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 14232 << regoff); 14233 reg |= (u64)(tctxt++) << regoff; 14234 rmt->map[regidx] = reg; 14235 if (tctxt == ctxt + krcvqs[i]) 14236 tctxt = ctxt; 14237 } 14238 ctxt += krcvqs[i]; 14239 } 14240 14241 rrd.offset = rmt->used; 14242 rrd.pkt_type = 2; 14243 rrd.field1_off = LRH_BTH_MATCH_OFFSET; 14244 rrd.field2_off = LRH_SC_MATCH_OFFSET; 14245 rrd.index1_off = LRH_SC_SELECT_OFFSET; 14246 rrd.index1_width = n; 14247 rrd.index2_off = QPN_SELECT_OFFSET; 14248 rrd.index2_width = m + n; 14249 rrd.mask1 = LRH_BTH_MASK; 14250 rrd.value1 = LRH_BTH_VALUE; 14251 rrd.mask2 = LRH_SC_MASK; 14252 rrd.value2 = LRH_SC_VALUE; 14253 14254 /* add rule 0 */ 14255 add_rsm_rule(dd, RSM_INS_VERBS, &rrd); 14256 14257 /* mark RSM map entries as used */ 14258 rmt->used += rmt_entries; 14259 /* map everything else to the mcast/err/vl15 context */ 14260 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT); 14261 dd->qos_shift = n + 1; 14262 return; 14263 bail: 14264 dd->qos_shift = 1; 14265 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1); 14266 } 14267 14268 static void init_user_fecn_handling(struct hfi1_devdata *dd, 14269 struct rsm_map_table *rmt) 14270 { 14271 struct rsm_rule_data rrd; 14272 u64 reg; 14273 int i, idx, regoff, regidx; 14274 u8 offset; 14275 14276 /* there needs to be enough room in the map table */ 14277 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) { 14278 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n"); 14279 return; 14280 } 14281 14282 /* 14283 * RSM will extract the destination context as an index into the 14284 * map table. The destination contexts are a sequential block 14285 * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive). 14286 * Map entries are accessed as offset + extracted value. Adjust 14287 * the added offset so this sequence can be placed anywhere in 14288 * the table - as long as the entries themselves do not wrap. 14289 * There are only enough bits in offset for the table size, so 14290 * start with that to allow for a "negative" offset. 14291 */ 14292 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used - 14293 (int)dd->first_dyn_alloc_ctxt); 14294 14295 for (i = dd->first_dyn_alloc_ctxt, idx = rmt->used; 14296 i < dd->num_rcv_contexts; i++, idx++) { 14297 /* replace with identity mapping */ 14298 regoff = (idx % 8) * 8; 14299 regidx = idx / 8; 14300 reg = rmt->map[regidx]; 14301 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff); 14302 reg |= (u64)i << regoff; 14303 rmt->map[regidx] = reg; 14304 } 14305 14306 /* 14307 * For RSM intercept of Expected FECN packets: 14308 * o packet type 0 - expected 14309 * o match on F (bit 95), using select/match 1, and 14310 * o match on SH (bit 133), using select/match 2. 14311 * 14312 * Use index 1 to extract the 8-bit receive context from DestQP 14313 * (start at bit 64). Use that as the RSM map table index. 14314 */ 14315 rrd.offset = offset; 14316 rrd.pkt_type = 0; 14317 rrd.field1_off = 95; 14318 rrd.field2_off = 133; 14319 rrd.index1_off = 64; 14320 rrd.index1_width = 8; 14321 rrd.index2_off = 0; 14322 rrd.index2_width = 0; 14323 rrd.mask1 = 1; 14324 rrd.value1 = 1; 14325 rrd.mask2 = 1; 14326 rrd.value2 = 1; 14327 14328 /* add rule 1 */ 14329 add_rsm_rule(dd, RSM_INS_FECN, &rrd); 14330 14331 rmt->used += dd->num_user_contexts; 14332 } 14333 14334 /* Initialize RSM for VNIC */ 14335 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd) 14336 { 14337 u8 i, j; 14338 u8 ctx_id = 0; 14339 u64 reg; 14340 u32 regoff; 14341 struct rsm_rule_data rrd; 14342 14343 if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) { 14344 dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n", 14345 dd->vnic.rmt_start); 14346 return; 14347 } 14348 14349 dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n", 14350 dd->vnic.rmt_start, 14351 dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES); 14352 14353 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */ 14354 regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8; 14355 reg = read_csr(dd, regoff); 14356 for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) { 14357 /* Update map register with vnic context */ 14358 j = (dd->vnic.rmt_start + i) % 8; 14359 reg &= ~(0xffllu << (j * 8)); 14360 reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8); 14361 /* Wrap up vnic ctx index */ 14362 ctx_id %= dd->vnic.num_ctxt; 14363 /* Write back map register */ 14364 if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) { 14365 dev_dbg(&(dd)->pcidev->dev, 14366 "Vnic rsm map reg[%d] =0x%llx\n", 14367 regoff - RCV_RSM_MAP_TABLE, reg); 14368 14369 write_csr(dd, regoff, reg); 14370 regoff += 8; 14371 if (i < (NUM_VNIC_MAP_ENTRIES - 1)) 14372 reg = read_csr(dd, regoff); 14373 } 14374 } 14375 14376 /* Add rule for vnic */ 14377 rrd.offset = dd->vnic.rmt_start; 14378 rrd.pkt_type = 4; 14379 /* Match 16B packets */ 14380 rrd.field1_off = L2_TYPE_MATCH_OFFSET; 14381 rrd.mask1 = L2_TYPE_MASK; 14382 rrd.value1 = L2_16B_VALUE; 14383 /* Match ETH L4 packets */ 14384 rrd.field2_off = L4_TYPE_MATCH_OFFSET; 14385 rrd.mask2 = L4_16B_TYPE_MASK; 14386 rrd.value2 = L4_16B_ETH_VALUE; 14387 /* Calc context from veswid and entropy */ 14388 rrd.index1_off = L4_16B_HDR_VESWID_OFFSET; 14389 rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES); 14390 rrd.index2_off = L2_16B_ENTROPY_OFFSET; 14391 rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES); 14392 add_rsm_rule(dd, RSM_INS_VNIC, &rrd); 14393 14394 /* Enable RSM if not already enabled */ 14395 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14396 } 14397 14398 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd) 14399 { 14400 clear_rsm_rule(dd, RSM_INS_VNIC); 14401 14402 /* Disable RSM if used only by vnic */ 14403 if (dd->vnic.rmt_start == 0) 14404 clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK); 14405 } 14406 14407 static void init_rxe(struct hfi1_devdata *dd) 14408 { 14409 struct rsm_map_table *rmt; 14410 u64 val; 14411 14412 /* enable all receive errors */ 14413 write_csr(dd, RCV_ERR_MASK, ~0ull); 14414 14415 rmt = alloc_rsm_map_table(dd); 14416 /* set up QOS, including the QPN map table */ 14417 init_qos(dd, rmt); 14418 init_user_fecn_handling(dd, rmt); 14419 complete_rsm_map_table(dd, rmt); 14420 /* record number of used rsm map entries for vnic */ 14421 dd->vnic.rmt_start = rmt->used; 14422 kfree(rmt); 14423 14424 /* 14425 * make sure RcvCtrl.RcvWcb <= PCIe Device Control 14426 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config 14427 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one 14428 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and 14429 * Max_PayLoad_Size set to its minimum of 128. 14430 * 14431 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0 14432 * (64 bytes). Max_Payload_Size is possibly modified upward in 14433 * tune_pcie_caps() which is called after this routine. 14434 */ 14435 14436 /* Have 16 bytes (4DW) of bypass header available in header queue */ 14437 val = read_csr(dd, RCV_BYPASS); 14438 val &= ~RCV_BYPASS_HDR_SIZE_SMASK; 14439 val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) << 14440 RCV_BYPASS_HDR_SIZE_SHIFT); 14441 write_csr(dd, RCV_BYPASS, val); 14442 } 14443 14444 static void init_other(struct hfi1_devdata *dd) 14445 { 14446 /* enable all CCE errors */ 14447 write_csr(dd, CCE_ERR_MASK, ~0ull); 14448 /* enable *some* Misc errors */ 14449 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); 14450 /* enable all DC errors, except LCB */ 14451 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); 14452 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); 14453 } 14454 14455 /* 14456 * Fill out the given AU table using the given CU. A CU is defined in terms 14457 * AUs. The table is a an encoding: given the index, how many AUs does that 14458 * represent? 14459 * 14460 * NOTE: Assumes that the register layout is the same for the 14461 * local and remote tables. 14462 */ 14463 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu, 14464 u32 csr0to3, u32 csr4to7) 14465 { 14466 write_csr(dd, csr0to3, 14467 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT | 14468 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT | 14469 2ull * cu << 14470 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT | 14471 4ull * cu << 14472 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT); 14473 write_csr(dd, csr4to7, 14474 8ull * cu << 14475 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT | 14476 16ull * cu << 14477 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT | 14478 32ull * cu << 14479 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT | 14480 64ull * cu << 14481 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT); 14482 } 14483 14484 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14485 { 14486 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3, 14487 SEND_CM_LOCAL_AU_TABLE4_TO7); 14488 } 14489 14490 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu) 14491 { 14492 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3, 14493 SEND_CM_REMOTE_AU_TABLE4_TO7); 14494 } 14495 14496 static void init_txe(struct hfi1_devdata *dd) 14497 { 14498 int i; 14499 14500 /* enable all PIO, SDMA, general, and Egress errors */ 14501 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); 14502 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); 14503 write_csr(dd, SEND_ERR_MASK, ~0ull); 14504 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); 14505 14506 /* enable all per-context and per-SDMA engine errors */ 14507 for (i = 0; i < chip_send_contexts(dd); i++) 14508 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull); 14509 for (i = 0; i < chip_sdma_engines(dd); i++) 14510 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull); 14511 14512 /* set the local CU to AU mapping */ 14513 assign_local_cm_au_table(dd, dd->vcu); 14514 14515 /* 14516 * Set reasonable default for Credit Return Timer 14517 * Don't set on Simulator - causes it to choke. 14518 */ 14519 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 14520 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); 14521 } 14522 14523 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14524 u16 jkey) 14525 { 14526 u8 hw_ctxt; 14527 u64 reg; 14528 14529 if (!rcd || !rcd->sc) 14530 return -EINVAL; 14531 14532 hw_ctxt = rcd->sc->hw_context; 14533 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */ 14534 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) << 14535 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT); 14536 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */ 14537 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY)) 14538 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK; 14539 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg); 14540 /* 14541 * Enable send-side J_KEY integrity check, unless this is A0 h/w 14542 */ 14543 if (!is_ax(dd)) { 14544 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14545 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14546 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14547 } 14548 14549 /* Enable J_KEY check on receive context. */ 14550 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK | 14551 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) << 14552 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT); 14553 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg); 14554 14555 return 0; 14556 } 14557 14558 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 14559 { 14560 u8 hw_ctxt; 14561 u64 reg; 14562 14563 if (!rcd || !rcd->sc) 14564 return -EINVAL; 14565 14566 hw_ctxt = rcd->sc->hw_context; 14567 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0); 14568 /* 14569 * Disable send-side J_KEY integrity check, unless this is A0 h/w. 14570 * This check would not have been enabled for A0 h/w, see 14571 * set_ctxt_jkey(). 14572 */ 14573 if (!is_ax(dd)) { 14574 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14575 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 14576 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14577 } 14578 /* Turn off the J_KEY on the receive side */ 14579 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0); 14580 14581 return 0; 14582 } 14583 14584 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, 14585 u16 pkey) 14586 { 14587 u8 hw_ctxt; 14588 u64 reg; 14589 14590 if (!rcd || !rcd->sc) 14591 return -EINVAL; 14592 14593 hw_ctxt = rcd->sc->hw_context; 14594 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) << 14595 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT; 14596 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg); 14597 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14598 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14599 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK; 14600 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14601 14602 return 0; 14603 } 14604 14605 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt) 14606 { 14607 u8 hw_ctxt; 14608 u64 reg; 14609 14610 if (!ctxt || !ctxt->sc) 14611 return -EINVAL; 14612 14613 hw_ctxt = ctxt->sc->hw_context; 14614 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); 14615 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; 14616 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); 14617 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0); 14618 14619 return 0; 14620 } 14621 14622 /* 14623 * Start doing the clean up the the chip. Our clean up happens in multiple 14624 * stages and this is just the first. 14625 */ 14626 void hfi1_start_cleanup(struct hfi1_devdata *dd) 14627 { 14628 aspm_exit(dd); 14629 free_cntrs(dd); 14630 free_rcverr(dd); 14631 finish_chip_resources(dd); 14632 } 14633 14634 #define HFI_BASE_GUID(dev) \ 14635 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT)) 14636 14637 /* 14638 * Information can be shared between the two HFIs on the same ASIC 14639 * in the same OS. This function finds the peer device and sets 14640 * up a shared structure. 14641 */ 14642 static int init_asic_data(struct hfi1_devdata *dd) 14643 { 14644 unsigned long flags; 14645 struct hfi1_devdata *tmp, *peer = NULL; 14646 struct hfi1_asic_data *asic_data; 14647 int ret = 0; 14648 14649 /* pre-allocate the asic structure in case we are the first device */ 14650 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL); 14651 if (!asic_data) 14652 return -ENOMEM; 14653 14654 spin_lock_irqsave(&hfi1_devs_lock, flags); 14655 /* Find our peer device */ 14656 list_for_each_entry(tmp, &hfi1_dev_list, list) { 14657 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) && 14658 dd->unit != tmp->unit) { 14659 peer = tmp; 14660 break; 14661 } 14662 } 14663 14664 if (peer) { 14665 /* use already allocated structure */ 14666 dd->asic_data = peer->asic_data; 14667 kfree(asic_data); 14668 } else { 14669 dd->asic_data = asic_data; 14670 mutex_init(&dd->asic_data->asic_resource_mutex); 14671 } 14672 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */ 14673 spin_unlock_irqrestore(&hfi1_devs_lock, flags); 14674 14675 /* first one through - set up i2c devices */ 14676 if (!peer) 14677 ret = set_up_i2c(dd, dd->asic_data); 14678 14679 return ret; 14680 } 14681 14682 /* 14683 * Set dd->boardname. Use a generic name if a name is not returned from 14684 * EFI variable space. 14685 * 14686 * Return 0 on success, -ENOMEM if space could not be allocated. 14687 */ 14688 static int obtain_boardname(struct hfi1_devdata *dd) 14689 { 14690 /* generic board description */ 14691 const char generic[] = 14692 "Intel Omni-Path Host Fabric Interface Adapter 100 Series"; 14693 unsigned long size; 14694 int ret; 14695 14696 ret = read_hfi1_efi_var(dd, "description", &size, 14697 (void **)&dd->boardname); 14698 if (ret) { 14699 dd_dev_info(dd, "Board description not found\n"); 14700 /* use generic description */ 14701 dd->boardname = kstrdup(generic, GFP_KERNEL); 14702 if (!dd->boardname) 14703 return -ENOMEM; 14704 } 14705 return 0; 14706 } 14707 14708 /* 14709 * Check the interrupt registers to make sure that they are mapped correctly. 14710 * It is intended to help user identify any mismapping by VMM when the driver 14711 * is running in a VM. This function should only be called before interrupt 14712 * is set up properly. 14713 * 14714 * Return 0 on success, -EINVAL on failure. 14715 */ 14716 static int check_int_registers(struct hfi1_devdata *dd) 14717 { 14718 u64 reg; 14719 u64 all_bits = ~(u64)0; 14720 u64 mask; 14721 14722 /* Clear CceIntMask[0] to avoid raising any interrupts */ 14723 mask = read_csr(dd, CCE_INT_MASK); 14724 write_csr(dd, CCE_INT_MASK, 0ull); 14725 reg = read_csr(dd, CCE_INT_MASK); 14726 if (reg) 14727 goto err_exit; 14728 14729 /* Clear all interrupt status bits */ 14730 write_csr(dd, CCE_INT_CLEAR, all_bits); 14731 reg = read_csr(dd, CCE_INT_STATUS); 14732 if (reg) 14733 goto err_exit; 14734 14735 /* Set all interrupt status bits */ 14736 write_csr(dd, CCE_INT_FORCE, all_bits); 14737 reg = read_csr(dd, CCE_INT_STATUS); 14738 if (reg != all_bits) 14739 goto err_exit; 14740 14741 /* Restore the interrupt mask */ 14742 write_csr(dd, CCE_INT_CLEAR, all_bits); 14743 write_csr(dd, CCE_INT_MASK, mask); 14744 14745 return 0; 14746 err_exit: 14747 write_csr(dd, CCE_INT_MASK, mask); 14748 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n"); 14749 return -EINVAL; 14750 } 14751 14752 /** 14753 * hfi1_init_dd() - Initialize most of the dd structure. 14754 * @dev: the pci_dev for hfi1_ib device 14755 * @ent: pci_device_id struct for this dev 14756 * 14757 * This is global, and is called directly at init to set up the 14758 * chip-specific function pointers for later use. 14759 */ 14760 int hfi1_init_dd(struct hfi1_devdata *dd) 14761 { 14762 struct pci_dev *pdev = dd->pcidev; 14763 struct hfi1_pportdata *ppd; 14764 u64 reg; 14765 int i, ret; 14766 static const char * const inames[] = { /* implementation names */ 14767 "RTL silicon", 14768 "RTL VCS simulation", 14769 "RTL FPGA emulation", 14770 "Functional simulator" 14771 }; 14772 struct pci_dev *parent = pdev->bus->self; 14773 u32 sdma_engines = chip_sdma_engines(dd); 14774 14775 ppd = dd->pport; 14776 for (i = 0; i < dd->num_pports; i++, ppd++) { 14777 int vl; 14778 /* init common fields */ 14779 hfi1_init_pportdata(pdev, ppd, dd, 0, 1); 14780 /* DC supports 4 link widths */ 14781 ppd->link_width_supported = 14782 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X | 14783 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X; 14784 ppd->link_width_downgrade_supported = 14785 ppd->link_width_supported; 14786 /* start out enabling only 4X */ 14787 ppd->link_width_enabled = OPA_LINK_WIDTH_4X; 14788 ppd->link_width_downgrade_enabled = 14789 ppd->link_width_downgrade_supported; 14790 /* link width active is 0 when link is down */ 14791 /* link width downgrade active is 0 when link is down */ 14792 14793 if (num_vls < HFI1_MIN_VLS_SUPPORTED || 14794 num_vls > HFI1_MAX_VLS_SUPPORTED) { 14795 dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n", 14796 num_vls, HFI1_MAX_VLS_SUPPORTED); 14797 num_vls = HFI1_MAX_VLS_SUPPORTED; 14798 } 14799 ppd->vls_supported = num_vls; 14800 ppd->vls_operational = ppd->vls_supported; 14801 /* Set the default MTU. */ 14802 for (vl = 0; vl < num_vls; vl++) 14803 dd->vld[vl].mtu = hfi1_max_mtu; 14804 dd->vld[15].mtu = MAX_MAD_PACKET; 14805 /* 14806 * Set the initial values to reasonable default, will be set 14807 * for real when link is up. 14808 */ 14809 ppd->overrun_threshold = 0x4; 14810 ppd->phy_error_threshold = 0xf; 14811 ppd->port_crc_mode_enabled = link_crc_mask; 14812 /* initialize supported LTP CRC mode */ 14813 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8; 14814 /* initialize enabled LTP CRC mode */ 14815 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4; 14816 /* start in offline */ 14817 ppd->host_link_state = HLS_DN_OFFLINE; 14818 init_vl_arb_caches(ppd); 14819 } 14820 14821 /* 14822 * Do remaining PCIe setup and save PCIe values in dd. 14823 * Any error printing is already done by the init code. 14824 * On return, we have the chip mapped. 14825 */ 14826 ret = hfi1_pcie_ddinit(dd, pdev); 14827 if (ret < 0) 14828 goto bail_free; 14829 14830 /* Save PCI space registers to rewrite after device reset */ 14831 ret = save_pci_variables(dd); 14832 if (ret < 0) 14833 goto bail_cleanup; 14834 14835 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT) 14836 & CCE_REVISION_CHIP_REV_MAJOR_MASK; 14837 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT) 14838 & CCE_REVISION_CHIP_REV_MINOR_MASK; 14839 14840 /* 14841 * Check interrupt registers mapping if the driver has no access to 14842 * the upstream component. In this case, it is likely that the driver 14843 * is running in a VM. 14844 */ 14845 if (!parent) { 14846 ret = check_int_registers(dd); 14847 if (ret) 14848 goto bail_cleanup; 14849 } 14850 14851 /* 14852 * obtain the hardware ID - NOT related to unit, which is a 14853 * software enumeration 14854 */ 14855 reg = read_csr(dd, CCE_REVISION2); 14856 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT) 14857 & CCE_REVISION2_HFI_ID_MASK; 14858 /* the variable size will remove unwanted bits */ 14859 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT; 14860 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT; 14861 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n", 14862 dd->icode < ARRAY_SIZE(inames) ? 14863 inames[dd->icode] : "unknown", (int)dd->irev); 14864 14865 /* speeds the hardware can support */ 14866 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G; 14867 /* speeds allowed to run at */ 14868 dd->pport->link_speed_enabled = dd->pport->link_speed_supported; 14869 /* give a reasonable active value, will be set on link up */ 14870 dd->pport->link_speed_active = OPA_LINK_SPEED_25G; 14871 14872 /* fix up link widths for emulation _p */ 14873 ppd = dd->pport; 14874 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) { 14875 ppd->link_width_supported = 14876 ppd->link_width_enabled = 14877 ppd->link_width_downgrade_supported = 14878 ppd->link_width_downgrade_enabled = 14879 OPA_LINK_WIDTH_1X; 14880 } 14881 /* insure num_vls isn't larger than number of sdma engines */ 14882 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > sdma_engines) { 14883 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n", 14884 num_vls, sdma_engines); 14885 num_vls = sdma_engines; 14886 ppd->vls_supported = sdma_engines; 14887 ppd->vls_operational = ppd->vls_supported; 14888 } 14889 14890 /* 14891 * Convert the ns parameter to the 64 * cclocks used in the CSR. 14892 * Limit the max if larger than the field holds. If timeout is 14893 * non-zero, then the calculated field will be at least 1. 14894 * 14895 * Must be after icode is set up - the cclock rate depends 14896 * on knowing the hardware being used. 14897 */ 14898 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64; 14899 if (dd->rcv_intr_timeout_csr > 14900 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK) 14901 dd->rcv_intr_timeout_csr = 14902 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK; 14903 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout) 14904 dd->rcv_intr_timeout_csr = 1; 14905 14906 /* needs to be done before we look for the peer device */ 14907 read_guid(dd); 14908 14909 /* set up shared ASIC data with peer device */ 14910 ret = init_asic_data(dd); 14911 if (ret) 14912 goto bail_cleanup; 14913 14914 /* obtain chip sizes, reset chip CSRs */ 14915 ret = init_chip(dd); 14916 if (ret) 14917 goto bail_cleanup; 14918 14919 /* read in the PCIe link speed information */ 14920 ret = pcie_speeds(dd); 14921 if (ret) 14922 goto bail_cleanup; 14923 14924 /* call before get_platform_config(), after init_chip_resources() */ 14925 ret = eprom_init(dd); 14926 if (ret) 14927 goto bail_free_rcverr; 14928 14929 /* Needs to be called before hfi1_firmware_init */ 14930 get_platform_config(dd); 14931 14932 /* read in firmware */ 14933 ret = hfi1_firmware_init(dd); 14934 if (ret) 14935 goto bail_cleanup; 14936 14937 /* 14938 * In general, the PCIe Gen3 transition must occur after the 14939 * chip has been idled (so it won't initiate any PCIe transactions 14940 * e.g. an interrupt) and before the driver changes any registers 14941 * (the transition will reset the registers). 14942 * 14943 * In particular, place this call after: 14944 * - init_chip() - the chip will not initiate any PCIe transactions 14945 * - pcie_speeds() - reads the current link speed 14946 * - hfi1_firmware_init() - the needed firmware is ready to be 14947 * downloaded 14948 */ 14949 ret = do_pcie_gen3_transition(dd); 14950 if (ret) 14951 goto bail_cleanup; 14952 14953 /* 14954 * This should probably occur in hfi1_pcie_init(), but historically 14955 * occurs after the do_pcie_gen3_transition() code. 14956 */ 14957 tune_pcie_caps(dd); 14958 14959 /* start setting dd values and adjusting CSRs */ 14960 init_early_variables(dd); 14961 14962 parse_platform_config(dd); 14963 14964 ret = obtain_boardname(dd); 14965 if (ret) 14966 goto bail_cleanup; 14967 14968 snprintf(dd->boardversion, BOARD_VERS_MAX, 14969 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n", 14970 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN, 14971 (u32)dd->majrev, 14972 (u32)dd->minrev, 14973 (dd->revision >> CCE_REVISION_SW_SHIFT) 14974 & CCE_REVISION_SW_MASK); 14975 14976 ret = set_up_context_variables(dd); 14977 if (ret) 14978 goto bail_cleanup; 14979 14980 /* set initial RXE CSRs */ 14981 init_rxe(dd); 14982 /* set initial TXE CSRs */ 14983 init_txe(dd); 14984 /* set initial non-RXE, non-TXE CSRs */ 14985 init_other(dd); 14986 /* set up KDETH QP prefix in both RX and TX CSRs */ 14987 init_kdeth_qp(dd); 14988 14989 ret = hfi1_dev_affinity_init(dd); 14990 if (ret) 14991 goto bail_cleanup; 14992 14993 /* send contexts must be set up before receive contexts */ 14994 ret = init_send_contexts(dd); 14995 if (ret) 14996 goto bail_cleanup; 14997 14998 ret = hfi1_create_kctxts(dd); 14999 if (ret) 15000 goto bail_cleanup; 15001 15002 /* 15003 * Initialize aspm, to be done after gen3 transition and setting up 15004 * contexts and before enabling interrupts 15005 */ 15006 aspm_init(dd); 15007 15008 ret = init_pervl_scs(dd); 15009 if (ret) 15010 goto bail_cleanup; 15011 15012 /* sdma init */ 15013 for (i = 0; i < dd->num_pports; ++i) { 15014 ret = sdma_init(dd, i); 15015 if (ret) 15016 goto bail_cleanup; 15017 } 15018 15019 /* use contexts created by hfi1_create_kctxts */ 15020 ret = set_up_interrupts(dd); 15021 if (ret) 15022 goto bail_cleanup; 15023 15024 ret = hfi1_comp_vectors_set_up(dd); 15025 if (ret) 15026 goto bail_clear_intr; 15027 15028 /* set up LCB access - must be after set_up_interrupts() */ 15029 init_lcb_access(dd); 15030 15031 /* 15032 * Serial number is created from the base guid: 15033 * [27:24] = base guid [38:35] 15034 * [23: 0] = base guid [23: 0] 15035 */ 15036 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n", 15037 (dd->base_guid & 0xFFFFFF) | 15038 ((dd->base_guid >> 11) & 0xF000000)); 15039 15040 dd->oui1 = dd->base_guid >> 56 & 0xFF; 15041 dd->oui2 = dd->base_guid >> 48 & 0xFF; 15042 dd->oui3 = dd->base_guid >> 40 & 0xFF; 15043 15044 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */ 15045 if (ret) 15046 goto bail_clear_intr; 15047 15048 thermal_init(dd); 15049 15050 ret = init_cntrs(dd); 15051 if (ret) 15052 goto bail_clear_intr; 15053 15054 ret = init_rcverr(dd); 15055 if (ret) 15056 goto bail_free_cntrs; 15057 15058 init_completion(&dd->user_comp); 15059 15060 /* The user refcount starts with one to inidicate an active device */ 15061 atomic_set(&dd->user_refcount, 1); 15062 15063 goto bail; 15064 15065 bail_free_rcverr: 15066 free_rcverr(dd); 15067 bail_free_cntrs: 15068 free_cntrs(dd); 15069 bail_clear_intr: 15070 hfi1_comp_vectors_clean_up(dd); 15071 msix_clean_up_interrupts(dd); 15072 bail_cleanup: 15073 hfi1_pcie_ddcleanup(dd); 15074 bail_free: 15075 hfi1_free_devdata(dd); 15076 bail: 15077 return ret; 15078 } 15079 15080 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate, 15081 u32 dw_len) 15082 { 15083 u32 delta_cycles; 15084 u32 current_egress_rate = ppd->current_egress_rate; 15085 /* rates here are in units of 10^6 bits/sec */ 15086 15087 if (desired_egress_rate == -1) 15088 return 0; /* shouldn't happen */ 15089 15090 if (desired_egress_rate >= current_egress_rate) 15091 return 0; /* we can't help go faster, only slower */ 15092 15093 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) - 15094 egress_cycles(dw_len * 4, current_egress_rate); 15095 15096 return (u16)delta_cycles; 15097 } 15098 15099 /** 15100 * create_pbc - build a pbc for transmission 15101 * @flags: special case flags or-ed in built pbc 15102 * @srate: static rate 15103 * @vl: vl 15104 * @dwlen: dword length (header words + data words + pbc words) 15105 * 15106 * Create a PBC with the given flags, rate, VL, and length. 15107 * 15108 * NOTE: The PBC created will not insert any HCRC - all callers but one are 15109 * for verbs, which does not use this PSM feature. The lone other caller 15110 * is for the diagnostic interface which calls this if the user does not 15111 * supply their own PBC. 15112 */ 15113 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, 15114 u32 dw_len) 15115 { 15116 u64 pbc, delay = 0; 15117 15118 if (unlikely(srate_mbs)) 15119 delay = delay_cycles(ppd, srate_mbs, dw_len); 15120 15121 pbc = flags 15122 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT) 15123 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT) 15124 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT 15125 | (dw_len & PBC_LENGTH_DWS_MASK) 15126 << PBC_LENGTH_DWS_SHIFT; 15127 15128 return pbc; 15129 } 15130 15131 #define SBUS_THERMAL 0x4f 15132 #define SBUS_THERM_MONITOR_MODE 0x1 15133 15134 #define THERM_FAILURE(dev, ret, reason) \ 15135 dd_dev_err((dd), \ 15136 "Thermal sensor initialization failed: %s (%d)\n", \ 15137 (reason), (ret)) 15138 15139 /* 15140 * Initialize the thermal sensor. 15141 * 15142 * After initialization, enable polling of thermal sensor through 15143 * SBus interface. In order for this to work, the SBus Master 15144 * firmware has to be loaded due to the fact that the HW polling 15145 * logic uses SBus interrupts, which are not supported with 15146 * default firmware. Otherwise, no data will be returned through 15147 * the ASIC_STS_THERM CSR. 15148 */ 15149 static int thermal_init(struct hfi1_devdata *dd) 15150 { 15151 int ret = 0; 15152 15153 if (dd->icode != ICODE_RTL_SILICON || 15154 check_chip_resource(dd, CR_THERM_INIT, NULL)) 15155 return ret; 15156 15157 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 15158 if (ret) { 15159 THERM_FAILURE(dd, ret, "Acquire SBus"); 15160 return ret; 15161 } 15162 15163 dd_dev_info(dd, "Initializing thermal sensor\n"); 15164 /* Disable polling of thermal readings */ 15165 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 15166 msleep(100); 15167 /* Thermal Sensor Initialization */ 15168 /* Step 1: Reset the Thermal SBus Receiver */ 15169 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15170 RESET_SBUS_RECEIVER, 0); 15171 if (ret) { 15172 THERM_FAILURE(dd, ret, "Bus Reset"); 15173 goto done; 15174 } 15175 /* Step 2: Set Reset bit in Thermal block */ 15176 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15177 WRITE_SBUS_RECEIVER, 0x1); 15178 if (ret) { 15179 THERM_FAILURE(dd, ret, "Therm Block Reset"); 15180 goto done; 15181 } 15182 /* Step 3: Write clock divider value (100MHz -> 2MHz) */ 15183 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1, 15184 WRITE_SBUS_RECEIVER, 0x32); 15185 if (ret) { 15186 THERM_FAILURE(dd, ret, "Write Clock Div"); 15187 goto done; 15188 } 15189 /* Step 4: Select temperature mode */ 15190 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3, 15191 WRITE_SBUS_RECEIVER, 15192 SBUS_THERM_MONITOR_MODE); 15193 if (ret) { 15194 THERM_FAILURE(dd, ret, "Write Mode Sel"); 15195 goto done; 15196 } 15197 /* Step 5: De-assert block reset and start conversion */ 15198 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, 15199 WRITE_SBUS_RECEIVER, 0x2); 15200 if (ret) { 15201 THERM_FAILURE(dd, ret, "Write Reset Deassert"); 15202 goto done; 15203 } 15204 /* Step 5.1: Wait for first conversion (21.5ms per spec) */ 15205 msleep(22); 15206 15207 /* Enable polling of thermal readings */ 15208 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 15209 15210 /* Set initialized flag */ 15211 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0); 15212 if (ret) 15213 THERM_FAILURE(dd, ret, "Unable to set thermal init flag"); 15214 15215 done: 15216 release_chip_resource(dd, CR_SBUS); 15217 return ret; 15218 } 15219 15220 static void handle_temp_err(struct hfi1_devdata *dd) 15221 { 15222 struct hfi1_pportdata *ppd = &dd->pport[0]; 15223 /* 15224 * Thermal Critical Interrupt 15225 * Put the device into forced freeze mode, take link down to 15226 * offline, and put DC into reset. 15227 */ 15228 dd_dev_emerg(dd, 15229 "Critical temperature reached! Forcing device into freeze mode!\n"); 15230 dd->flags |= HFI1_FORCED_FREEZE; 15231 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT); 15232 /* 15233 * Shut DC down as much and as quickly as possible. 15234 * 15235 * Step 1: Take the link down to OFFLINE. This will cause the 15236 * 8051 to put the Serdes in reset. However, we don't want to 15237 * go through the entire link state machine since we want to 15238 * shutdown ASAP. Furthermore, this is not a graceful shutdown 15239 * but rather an attempt to save the chip. 15240 * Code below is almost the same as quiet_serdes() but avoids 15241 * all the extra work and the sleeps. 15242 */ 15243 ppd->driver_link_ready = 0; 15244 ppd->link_enabled = 0; 15245 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) | 15246 PLS_OFFLINE); 15247 /* 15248 * Step 2: Shutdown LCB and 8051 15249 * After shutdown, do not restore DC_CFG_RESET value. 15250 */ 15251 dc_shutdown(dd); 15252 } 15253