1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_REGS_H_ 7 #define _EFA_REGS_H_ 8 9 enum efa_regs_reset_reason_types { 10 EFA_REGS_RESET_NORMAL = 0, 11 /* Keep alive timeout */ 12 EFA_REGS_RESET_KEEP_ALIVE_TO = 1, 13 EFA_REGS_RESET_ADMIN_TO = 2, 14 EFA_REGS_RESET_INIT_ERR = 3, 15 EFA_REGS_RESET_DRIVER_INVALID_STATE = 4, 16 EFA_REGS_RESET_OS_TRIGGER = 5, 17 EFA_REGS_RESET_SHUTDOWN = 6, 18 EFA_REGS_RESET_USER_TRIGGER = 7, 19 EFA_REGS_RESET_GENERIC = 8, 20 }; 21 22 /* efa_registers offsets */ 23 24 /* 0 base */ 25 #define EFA_REGS_VERSION_OFF 0x0 26 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x4 27 #define EFA_REGS_CAPS_OFF 0x8 28 #define EFA_REGS_AQ_BASE_LO_OFF 0x10 29 #define EFA_REGS_AQ_BASE_HI_OFF 0x14 30 #define EFA_REGS_AQ_CAPS_OFF 0x18 31 #define EFA_REGS_ACQ_BASE_LO_OFF 0x20 32 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24 33 #define EFA_REGS_ACQ_CAPS_OFF 0x28 34 #define EFA_REGS_AQ_PROD_DB_OFF 0x2c 35 #define EFA_REGS_AENQ_CAPS_OFF 0x34 36 #define EFA_REGS_AENQ_BASE_LO_OFF 0x38 37 #define EFA_REGS_AENQ_BASE_HI_OFF 0x3c 38 #define EFA_REGS_AENQ_CONS_DB_OFF 0x40 39 #define EFA_REGS_INTR_MASK_OFF 0x4c 40 #define EFA_REGS_DEV_CTL_OFF 0x54 41 #define EFA_REGS_DEV_STS_OFF 0x58 42 #define EFA_REGS_MMIO_REG_READ_OFF 0x5c 43 #define EFA_REGS_MMIO_RESP_LO_OFF 0x60 44 #define EFA_REGS_MMIO_RESP_HI_OFF 0x64 45 #define EFA_REGS_EQ_DB_OFF 0x68 46 47 /* version register */ 48 #define EFA_REGS_VERSION_MINOR_VERSION_MASK 0xff 49 #define EFA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00 50 51 /* controller_version register */ 52 #define EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff 53 #define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00 54 #define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000 55 #define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000 56 57 /* caps register */ 58 #define EFA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 59 #define EFA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e 60 #define EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 61 #define EFA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000 62 63 /* aq_caps register */ 64 #define EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff 65 #define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000 66 67 /* acq_caps register */ 68 #define EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff 69 #define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xff0000 70 #define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK 0xff000000 71 72 /* aenq_caps register */ 73 #define EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff 74 #define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xff0000 75 #define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK 0xff000000 76 77 /* intr_mask register */ 78 #define EFA_REGS_INTR_MASK_EN_MASK 0x1 79 80 /* dev_ctl register */ 81 #define EFA_REGS_DEV_CTL_DEV_RESET_MASK 0x1 82 #define EFA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2 83 #define EFA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000 84 85 /* dev_sts register */ 86 #define EFA_REGS_DEV_STS_READY_MASK 0x1 87 #define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 88 #define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 89 #define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 90 #define EFA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10 91 #define EFA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20 92 93 /* mmio_reg_read register */ 94 #define EFA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff 95 #define EFA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000 96 97 /* eq_db register */ 98 #define EFA_REGS_EQ_DB_EQN_MASK 0xffff 99 #define EFA_REGS_EQ_DB_ARM_MASK 0x80000000 100 101 #endif /* _EFA_REGS_H_ */ 102