1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2 /*
3  * Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
4  */
5 
6 #ifndef _EFA_REGS_H_
7 #define _EFA_REGS_H_
8 
9 enum efa_regs_reset_reason_types {
10 	EFA_REGS_RESET_NORMAL                       = 0,
11 	/* Keep alive timeout */
12 	EFA_REGS_RESET_KEEP_ALIVE_TO                = 1,
13 	EFA_REGS_RESET_ADMIN_TO                     = 2,
14 	EFA_REGS_RESET_INIT_ERR                     = 3,
15 	EFA_REGS_RESET_DRIVER_INVALID_STATE         = 4,
16 	EFA_REGS_RESET_OS_TRIGGER                   = 5,
17 	EFA_REGS_RESET_SHUTDOWN                     = 6,
18 	EFA_REGS_RESET_USER_TRIGGER                 = 7,
19 	EFA_REGS_RESET_GENERIC                      = 8,
20 };
21 
22 /* efa_registers offsets */
23 
24 /* 0 base */
25 #define EFA_REGS_VERSION_OFF                                0x0
26 #define EFA_REGS_CONTROLLER_VERSION_OFF                     0x4
27 #define EFA_REGS_CAPS_OFF                                   0x8
28 #define EFA_REGS_AQ_BASE_LO_OFF                             0x10
29 #define EFA_REGS_AQ_BASE_HI_OFF                             0x14
30 #define EFA_REGS_AQ_CAPS_OFF                                0x18
31 #define EFA_REGS_ACQ_BASE_LO_OFF                            0x20
32 #define EFA_REGS_ACQ_BASE_HI_OFF                            0x24
33 #define EFA_REGS_ACQ_CAPS_OFF                               0x28
34 #define EFA_REGS_AQ_PROD_DB_OFF                             0x2c
35 #define EFA_REGS_AENQ_CAPS_OFF                              0x34
36 #define EFA_REGS_AENQ_BASE_LO_OFF                           0x38
37 #define EFA_REGS_AENQ_BASE_HI_OFF                           0x3c
38 #define EFA_REGS_AENQ_CONS_DB_OFF                           0x40
39 #define EFA_REGS_INTR_MASK_OFF                              0x4c
40 #define EFA_REGS_DEV_CTL_OFF                                0x54
41 #define EFA_REGS_DEV_STS_OFF                                0x58
42 #define EFA_REGS_MMIO_REG_READ_OFF                          0x5c
43 #define EFA_REGS_MMIO_RESP_LO_OFF                           0x60
44 #define EFA_REGS_MMIO_RESP_HI_OFF                           0x64
45 
46 /* version register */
47 #define EFA_REGS_VERSION_MINOR_VERSION_MASK                 0xff
48 #define EFA_REGS_VERSION_MAJOR_VERSION_SHIFT                8
49 #define EFA_REGS_VERSION_MAJOR_VERSION_MASK                 0xff00
50 
51 /* controller_version register */
52 #define EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK   0xff
53 #define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT     8
54 #define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK      0xff00
55 #define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT     16
56 #define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK      0xff0000
57 #define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT           24
58 #define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK            0xff000000
59 
60 /* caps register */
61 #define EFA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK        0x1
62 #define EFA_REGS_CAPS_RESET_TIMEOUT_SHIFT                   1
63 #define EFA_REGS_CAPS_RESET_TIMEOUT_MASK                    0x3e
64 #define EFA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT                  8
65 #define EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK                   0xff00
66 #define EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT                    16
67 #define EFA_REGS_CAPS_ADMIN_CMD_TO_MASK                     0xf0000
68 
69 /* aq_caps register */
70 #define EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK                      0xffff
71 #define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT                16
72 #define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK                 0xffff0000
73 
74 /* acq_caps register */
75 #define EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                    0xffff
76 #define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT              16
77 #define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK               0xff0000
78 #define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_SHIFT             24
79 #define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK              0xff000000
80 
81 /* aenq_caps register */
82 #define EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK                  0xffff
83 #define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT            16
84 #define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK             0xff0000
85 #define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_SHIFT           24
86 #define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK            0xff000000
87 
88 /* dev_ctl register */
89 #define EFA_REGS_DEV_CTL_DEV_RESET_MASK                     0x1
90 #define EFA_REGS_DEV_CTL_AQ_RESTART_SHIFT                   1
91 #define EFA_REGS_DEV_CTL_AQ_RESTART_MASK                    0x2
92 #define EFA_REGS_DEV_CTL_RESET_REASON_SHIFT                 28
93 #define EFA_REGS_DEV_CTL_RESET_REASON_MASK                  0xf0000000
94 
95 /* dev_sts register */
96 #define EFA_REGS_DEV_STS_READY_MASK                         0x1
97 #define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT       1
98 #define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK        0x2
99 #define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT          2
100 #define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK           0x4
101 #define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT            3
102 #define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK             0x8
103 #define EFA_REGS_DEV_STS_RESET_FINISHED_SHIFT               4
104 #define EFA_REGS_DEV_STS_RESET_FINISHED_MASK                0x10
105 #define EFA_REGS_DEV_STS_FATAL_ERROR_SHIFT                  5
106 #define EFA_REGS_DEV_STS_FATAL_ERROR_MASK                   0x20
107 
108 /* mmio_reg_read register */
109 #define EFA_REGS_MMIO_REG_READ_REQ_ID_MASK                  0xffff
110 #define EFA_REGS_MMIO_REG_READ_REG_OFF_SHIFT                16
111 #define EFA_REGS_MMIO_REG_READ_REG_OFF_MASK                 0xffff0000
112 
113 #endif /* _EFA_REGS_H_ */
114