1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 /*
3  * Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
4  */
5 
6 #include "efa_com.h"
7 #include "efa_regs_defs.h"
8 
9 #define ADMIN_CMD_TIMEOUT_US 30000000 /* usecs */
10 
11 #define EFA_REG_READ_TIMEOUT_US 50000 /* usecs */
12 #define EFA_MMIO_READ_INVALID 0xffffffff
13 
14 #define EFA_POLL_INTERVAL_MS 100 /* msecs */
15 
16 #define EFA_ASYNC_QUEUE_DEPTH 16
17 #define EFA_ADMIN_QUEUE_DEPTH 32
18 
19 #define MIN_EFA_VER\
20 	((EFA_ADMIN_API_VERSION_MAJOR << EFA_REGS_VERSION_MAJOR_VERSION_SHIFT) | \
21 	 (EFA_ADMIN_API_VERSION_MINOR & EFA_REGS_VERSION_MINOR_VERSION_MASK))
22 
23 #define EFA_CTRL_MAJOR          0
24 #define EFA_CTRL_MINOR          0
25 #define EFA_CTRL_SUB_MINOR      1
26 
27 #define MIN_EFA_CTRL_VER \
28 	(((EFA_CTRL_MAJOR) << \
29 	(EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
30 	((EFA_CTRL_MINOR) << \
31 	(EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
32 	(EFA_CTRL_SUB_MINOR))
33 
34 #define EFA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
35 #define EFA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
36 
37 #define EFA_REGS_ADMIN_INTR_MASK 1
38 
39 enum efa_cmd_status {
40 	EFA_CMD_SUBMITTED,
41 	EFA_CMD_COMPLETED,
42 	/* Abort - canceled by the driver */
43 	EFA_CMD_ABORTED,
44 };
45 
46 struct efa_comp_ctx {
47 	struct completion wait_event;
48 	struct efa_admin_acq_entry *user_cqe;
49 	u32 comp_size;
50 	enum efa_cmd_status status;
51 	/* status from the device */
52 	u8 comp_status;
53 	u8 cmd_opcode;
54 	u8 occupied;
55 };
56 
57 static const char *efa_com_cmd_str(u8 cmd)
58 {
59 #define EFA_CMD_STR_CASE(_cmd) case EFA_ADMIN_##_cmd: return #_cmd
60 
61 	switch (cmd) {
62 	EFA_CMD_STR_CASE(CREATE_QP);
63 	EFA_CMD_STR_CASE(MODIFY_QP);
64 	EFA_CMD_STR_CASE(QUERY_QP);
65 	EFA_CMD_STR_CASE(DESTROY_QP);
66 	EFA_CMD_STR_CASE(CREATE_AH);
67 	EFA_CMD_STR_CASE(DESTROY_AH);
68 	EFA_CMD_STR_CASE(REG_MR);
69 	EFA_CMD_STR_CASE(DEREG_MR);
70 	EFA_CMD_STR_CASE(CREATE_CQ);
71 	EFA_CMD_STR_CASE(DESTROY_CQ);
72 	EFA_CMD_STR_CASE(GET_FEATURE);
73 	EFA_CMD_STR_CASE(SET_FEATURE);
74 	EFA_CMD_STR_CASE(GET_STATS);
75 	EFA_CMD_STR_CASE(ALLOC_PD);
76 	EFA_CMD_STR_CASE(DEALLOC_PD);
77 	EFA_CMD_STR_CASE(ALLOC_UAR);
78 	EFA_CMD_STR_CASE(DEALLOC_UAR);
79 	default: return "unknown command opcode";
80 	}
81 #undef EFA_CMD_STR_CASE
82 }
83 
84 static u32 efa_com_reg_read32(struct efa_com_dev *edev, u16 offset)
85 {
86 	struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
87 	struct efa_admin_mmio_req_read_less_resp *read_resp;
88 	unsigned long exp_time;
89 	u32 mmio_read_reg;
90 	u32 err;
91 
92 	read_resp = mmio_read->read_resp;
93 
94 	spin_lock(&mmio_read->lock);
95 	mmio_read->seq_num++;
96 
97 	/* trash DMA req_id to identify when hardware is done */
98 	read_resp->req_id = mmio_read->seq_num + 0x9aL;
99 	mmio_read_reg = (offset << EFA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
100 			EFA_REGS_MMIO_REG_READ_REG_OFF_MASK;
101 	mmio_read_reg |= mmio_read->seq_num &
102 			 EFA_REGS_MMIO_REG_READ_REQ_ID_MASK;
103 
104 	writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);
105 
106 	exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout);
107 	do {
108 		if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
109 			break;
110 		udelay(1);
111 	} while (time_is_after_jiffies(exp_time));
112 
113 	if (read_resp->req_id != mmio_read->seq_num) {
114 		ibdev_err(edev->efa_dev,
115 			  "Reading register timed out. expected: req id[%u] offset[%#x] actual: req id[%u] offset[%#x]\n",
116 			  mmio_read->seq_num, offset, read_resp->req_id,
117 			  read_resp->reg_off);
118 		err = EFA_MMIO_READ_INVALID;
119 		goto out;
120 	}
121 
122 	if (read_resp->reg_off != offset) {
123 		ibdev_err(edev->efa_dev,
124 			  "Reading register failed: wrong offset provided\n");
125 		err = EFA_MMIO_READ_INVALID;
126 		goto out;
127 	}
128 
129 	err = read_resp->reg_val;
130 out:
131 	spin_unlock(&mmio_read->lock);
132 	return err;
133 }
134 
135 static int efa_com_admin_init_sq(struct efa_com_dev *edev)
136 {
137 	struct efa_com_admin_queue *aq = &edev->aq;
138 	struct efa_com_admin_sq *sq = &aq->sq;
139 	u16 size = aq->depth * sizeof(*sq->entries);
140 	u32 addr_high;
141 	u32 addr_low;
142 	u32 aq_caps;
143 
144 	sq->entries =
145 		dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL);
146 	if (!sq->entries)
147 		return -ENOMEM;
148 
149 	spin_lock_init(&sq->lock);
150 
151 	sq->cc = 0;
152 	sq->pc = 0;
153 	sq->phase = 1;
154 
155 	sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF);
156 
157 	addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(sq->dma_addr);
158 	addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(sq->dma_addr);
159 
160 	writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);
161 	writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);
162 
163 	aq_caps = aq->depth & EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
164 	aq_caps |= (sizeof(struct efa_admin_aq_entry) <<
165 			EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
166 			EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
167 
168 	writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);
169 
170 	return 0;
171 }
172 
173 static int efa_com_admin_init_cq(struct efa_com_dev *edev)
174 {
175 	struct efa_com_admin_queue *aq = &edev->aq;
176 	struct efa_com_admin_cq *cq = &aq->cq;
177 	u16 size = aq->depth * sizeof(*cq->entries);
178 	u32 addr_high;
179 	u32 addr_low;
180 	u32 acq_caps;
181 
182 	cq->entries =
183 		dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL);
184 	if (!cq->entries)
185 		return -ENOMEM;
186 
187 	spin_lock_init(&cq->lock);
188 
189 	cq->cc = 0;
190 	cq->phase = 1;
191 
192 	addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(cq->dma_addr);
193 	addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(cq->dma_addr);
194 
195 	writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);
196 	writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);
197 
198 	acq_caps = aq->depth & EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
199 	acq_caps |= (sizeof(struct efa_admin_acq_entry) <<
200 			EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
201 			EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
202 	acq_caps |= (aq->msix_vector_idx <<
203 			EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_SHIFT) &
204 			EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK;
205 
206 	writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);
207 
208 	return 0;
209 }
210 
211 static int efa_com_admin_init_aenq(struct efa_com_dev *edev,
212 				   struct efa_aenq_handlers *aenq_handlers)
213 {
214 	struct efa_com_aenq *aenq = &edev->aenq;
215 	u32 addr_low, addr_high, aenq_caps;
216 	u16 size;
217 
218 	if (!aenq_handlers) {
219 		ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n");
220 		return -EINVAL;
221 	}
222 
223 	size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries);
224 	aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr,
225 					   GFP_KERNEL);
226 	if (!aenq->entries)
227 		return -ENOMEM;
228 
229 	aenq->aenq_handlers = aenq_handlers;
230 	aenq->depth = EFA_ASYNC_QUEUE_DEPTH;
231 	aenq->cc = 0;
232 	aenq->phase = 1;
233 
234 	addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
235 	addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
236 
237 	writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);
238 	writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);
239 
240 	aenq_caps = aenq->depth & EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
241 	aenq_caps |= (sizeof(struct efa_admin_aenq_entry) <<
242 		EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
243 		EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
244 	aenq_caps |= (aenq->msix_vector_idx
245 		      << EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_SHIFT) &
246 		     EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK;
247 	writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);
248 
249 	/*
250 	 * Init cons_db to mark that all entries in the queue
251 	 * are initially available
252 	 */
253 	writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
254 
255 	return 0;
256 }
257 
258 /* ID to be used with efa_com_get_comp_ctx */
259 static u16 efa_com_alloc_ctx_id(struct efa_com_admin_queue *aq)
260 {
261 	u16 ctx_id;
262 
263 	spin_lock(&aq->comp_ctx_lock);
264 	ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next];
265 	aq->comp_ctx_pool_next++;
266 	spin_unlock(&aq->comp_ctx_lock);
267 
268 	return ctx_id;
269 }
270 
271 static void efa_com_dealloc_ctx_id(struct efa_com_admin_queue *aq,
272 				   u16 ctx_id)
273 {
274 	spin_lock(&aq->comp_ctx_lock);
275 	aq->comp_ctx_pool_next--;
276 	aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id;
277 	spin_unlock(&aq->comp_ctx_lock);
278 }
279 
280 static inline void efa_com_put_comp_ctx(struct efa_com_admin_queue *aq,
281 					struct efa_comp_ctx *comp_ctx)
282 {
283 	u16 comp_id = comp_ctx->user_cqe->acq_common_descriptor.command &
284 		      EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
285 
286 	ibdev_dbg(aq->efa_dev, "Putting completion command_id %d\n", comp_id);
287 	comp_ctx->occupied = 0;
288 	efa_com_dealloc_ctx_id(aq, comp_id);
289 }
290 
291 static struct efa_comp_ctx *efa_com_get_comp_ctx(struct efa_com_admin_queue *aq,
292 						 u16 command_id, bool capture)
293 {
294 	if (command_id >= aq->depth) {
295 		ibdev_err(aq->efa_dev,
296 			  "command id is larger than the queue size. cmd_id: %u queue size %d\n",
297 			  command_id, aq->depth);
298 		return NULL;
299 	}
300 
301 	if (aq->comp_ctx[command_id].occupied && capture) {
302 		ibdev_err(aq->efa_dev, "Completion context is occupied\n");
303 		return NULL;
304 	}
305 
306 	if (capture) {
307 		aq->comp_ctx[command_id].occupied = 1;
308 		ibdev_dbg(aq->efa_dev, "Taking completion ctxt command_id %d\n",
309 			  command_id);
310 	}
311 
312 	return &aq->comp_ctx[command_id];
313 }
314 
315 static struct efa_comp_ctx *__efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq,
316 						       struct efa_admin_aq_entry *cmd,
317 						       size_t cmd_size_in_bytes,
318 						       struct efa_admin_acq_entry *comp,
319 						       size_t comp_size_in_bytes)
320 {
321 	struct efa_comp_ctx *comp_ctx;
322 	u16 queue_size_mask;
323 	u16 ctx_id;
324 	u16 pi;
325 
326 	queue_size_mask = aq->depth - 1;
327 	pi = aq->sq.pc & queue_size_mask;
328 
329 	ctx_id = efa_com_alloc_ctx_id(aq);
330 
331 	cmd->aq_common_descriptor.flags |= aq->sq.phase &
332 		EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
333 
334 	cmd->aq_common_descriptor.command_id |= ctx_id &
335 		EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
336 
337 	comp_ctx = efa_com_get_comp_ctx(aq, ctx_id, true);
338 	if (!comp_ctx) {
339 		efa_com_dealloc_ctx_id(aq, ctx_id);
340 		return ERR_PTR(-EINVAL);
341 	}
342 
343 	comp_ctx->status = EFA_CMD_SUBMITTED;
344 	comp_ctx->comp_size = comp_size_in_bytes;
345 	comp_ctx->user_cqe = comp;
346 	comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
347 
348 	reinit_completion(&comp_ctx->wait_event);
349 
350 	memcpy(&aq->sq.entries[pi], cmd, cmd_size_in_bytes);
351 
352 	aq->sq.pc++;
353 	atomic64_inc(&aq->stats.submitted_cmd);
354 
355 	if ((aq->sq.pc & queue_size_mask) == 0)
356 		aq->sq.phase = !aq->sq.phase;
357 
358 	/* barrier not needed in case of writel */
359 	writel(aq->sq.pc, aq->sq.db_addr);
360 
361 	return comp_ctx;
362 }
363 
364 static inline int efa_com_init_comp_ctxt(struct efa_com_admin_queue *aq)
365 {
366 	size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool);
367 	size_t size = aq->depth * sizeof(struct efa_comp_ctx);
368 	struct efa_comp_ctx *comp_ctx;
369 	u16 i;
370 
371 	aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL);
372 	aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL);
373 	if (!aq->comp_ctx || !aq->comp_ctx_pool) {
374 		devm_kfree(aq->dmadev, aq->comp_ctx_pool);
375 		devm_kfree(aq->dmadev, aq->comp_ctx);
376 		return -ENOMEM;
377 	}
378 
379 	for (i = 0; i < aq->depth; i++) {
380 		comp_ctx = efa_com_get_comp_ctx(aq, i, false);
381 		if (comp_ctx)
382 			init_completion(&comp_ctx->wait_event);
383 
384 		aq->comp_ctx_pool[i] = i;
385 	}
386 
387 	spin_lock_init(&aq->comp_ctx_lock);
388 
389 	aq->comp_ctx_pool_next = 0;
390 
391 	return 0;
392 }
393 
394 static struct efa_comp_ctx *efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq,
395 						     struct efa_admin_aq_entry *cmd,
396 						     size_t cmd_size_in_bytes,
397 						     struct efa_admin_acq_entry *comp,
398 						     size_t comp_size_in_bytes)
399 {
400 	struct efa_comp_ctx *comp_ctx;
401 
402 	spin_lock(&aq->sq.lock);
403 	if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) {
404 		ibdev_err(aq->efa_dev, "Admin queue is closed\n");
405 		spin_unlock(&aq->sq.lock);
406 		return ERR_PTR(-ENODEV);
407 	}
408 
409 	comp_ctx = __efa_com_submit_admin_cmd(aq, cmd, cmd_size_in_bytes, comp,
410 					      comp_size_in_bytes);
411 	spin_unlock(&aq->sq.lock);
412 	if (IS_ERR(comp_ctx))
413 		clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
414 
415 	return comp_ctx;
416 }
417 
418 static void efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq,
419 						   struct efa_admin_acq_entry *cqe)
420 {
421 	struct efa_comp_ctx *comp_ctx;
422 	u16 cmd_id;
423 
424 	cmd_id = cqe->acq_common_descriptor.command &
425 		 EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
426 
427 	comp_ctx = efa_com_get_comp_ctx(aq, cmd_id, false);
428 	if (!comp_ctx) {
429 		ibdev_err(aq->efa_dev,
430 			  "comp_ctx is NULL. Changing the admin queue running state\n");
431 		clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
432 		return;
433 	}
434 
435 	comp_ctx->status = EFA_CMD_COMPLETED;
436 	comp_ctx->comp_status = cqe->acq_common_descriptor.status;
437 	if (comp_ctx->user_cqe)
438 		memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size);
439 
440 	if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
441 		complete(&comp_ctx->wait_event);
442 }
443 
444 static void efa_com_handle_admin_completion(struct efa_com_admin_queue *aq)
445 {
446 	struct efa_admin_acq_entry *cqe;
447 	u16 queue_size_mask;
448 	u16 comp_num = 0;
449 	u8 phase;
450 	u16 ci;
451 
452 	queue_size_mask = aq->depth - 1;
453 
454 	ci = aq->cq.cc & queue_size_mask;
455 	phase = aq->cq.phase;
456 
457 	cqe = &aq->cq.entries[ci];
458 
459 	/* Go over all the completions */
460 	while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
461 		EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
462 		/*
463 		 * Do not read the rest of the completion entry before the
464 		 * phase bit was validated
465 		 */
466 		dma_rmb();
467 		efa_com_handle_single_admin_completion(aq, cqe);
468 
469 		ci++;
470 		comp_num++;
471 		if (ci == aq->depth) {
472 			ci = 0;
473 			phase = !phase;
474 		}
475 
476 		cqe = &aq->cq.entries[ci];
477 	}
478 
479 	aq->cq.cc += comp_num;
480 	aq->cq.phase = phase;
481 	aq->sq.cc += comp_num;
482 	atomic64_add(comp_num, &aq->stats.completed_cmd);
483 }
484 
485 static int efa_com_comp_status_to_errno(u8 comp_status)
486 {
487 	switch (comp_status) {
488 	case EFA_ADMIN_SUCCESS:
489 		return 0;
490 	case EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
491 		return -ENOMEM;
492 	case EFA_ADMIN_UNSUPPORTED_OPCODE:
493 		return -EOPNOTSUPP;
494 	case EFA_ADMIN_BAD_OPCODE:
495 	case EFA_ADMIN_MALFORMED_REQUEST:
496 	case EFA_ADMIN_ILLEGAL_PARAMETER:
497 	case EFA_ADMIN_UNKNOWN_ERROR:
498 		return -EINVAL;
499 	default:
500 		return -EINVAL;
501 	}
502 }
503 
504 static int efa_com_wait_and_process_admin_cq_polling(struct efa_comp_ctx *comp_ctx,
505 						     struct efa_com_admin_queue *aq)
506 {
507 	unsigned long timeout;
508 	unsigned long flags;
509 	int err;
510 
511 	timeout = jiffies + usecs_to_jiffies(aq->completion_timeout);
512 
513 	while (1) {
514 		spin_lock_irqsave(&aq->cq.lock, flags);
515 		efa_com_handle_admin_completion(aq);
516 		spin_unlock_irqrestore(&aq->cq.lock, flags);
517 
518 		if (comp_ctx->status != EFA_CMD_SUBMITTED)
519 			break;
520 
521 		if (time_is_before_jiffies(timeout)) {
522 			ibdev_err(aq->efa_dev,
523 				  "Wait for completion (polling) timeout\n");
524 			/* EFA didn't have any completion */
525 			atomic64_inc(&aq->stats.no_completion);
526 
527 			clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
528 			err = -ETIME;
529 			goto out;
530 		}
531 
532 		msleep(aq->poll_interval);
533 	}
534 
535 	if (comp_ctx->status == EFA_CMD_ABORTED) {
536 		ibdev_err(aq->efa_dev, "Command was aborted\n");
537 		atomic64_inc(&aq->stats.aborted_cmd);
538 		err = -ENODEV;
539 		goto out;
540 	}
541 
542 	WARN_ONCE(comp_ctx->status != EFA_CMD_COMPLETED,
543 		  "Invalid completion status %d\n", comp_ctx->status);
544 
545 	err = efa_com_comp_status_to_errno(comp_ctx->comp_status);
546 out:
547 	efa_com_put_comp_ctx(aq, comp_ctx);
548 	return err;
549 }
550 
551 static int efa_com_wait_and_process_admin_cq_interrupts(struct efa_comp_ctx *comp_ctx,
552 							struct efa_com_admin_queue *aq)
553 {
554 	unsigned long flags;
555 	int err;
556 
557 	wait_for_completion_timeout(&comp_ctx->wait_event,
558 				    usecs_to_jiffies(aq->completion_timeout));
559 
560 	/*
561 	 * In case the command wasn't completed find out the root cause.
562 	 * There might be 2 kinds of errors
563 	 * 1) No completion (timeout reached)
564 	 * 2) There is completion but the device didn't get any msi-x interrupt.
565 	 */
566 	if (comp_ctx->status == EFA_CMD_SUBMITTED) {
567 		spin_lock_irqsave(&aq->cq.lock, flags);
568 		efa_com_handle_admin_completion(aq);
569 		spin_unlock_irqrestore(&aq->cq.lock, flags);
570 
571 		atomic64_inc(&aq->stats.no_completion);
572 
573 		if (comp_ctx->status == EFA_CMD_COMPLETED)
574 			ibdev_err(aq->efa_dev,
575 				  "The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%d) status %d (ctx: 0x%p, sq producer: %d, sq consumer: %d, cq consumer: %d)\n",
576 				  efa_com_cmd_str(comp_ctx->cmd_opcode),
577 				  comp_ctx->cmd_opcode, comp_ctx->status,
578 				  comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc);
579 		else
580 			ibdev_err(aq->efa_dev,
581 				  "The device didn't send any completion for admin cmd %s(%d) status %d (ctx 0x%p, sq producer: %d, sq consumer: %d, cq consumer: %d)\n",
582 				  efa_com_cmd_str(comp_ctx->cmd_opcode),
583 				  comp_ctx->cmd_opcode, comp_ctx->status,
584 				  comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc);
585 
586 		clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
587 		err = -ETIME;
588 		goto out;
589 	}
590 
591 	err = efa_com_comp_status_to_errno(comp_ctx->comp_status);
592 out:
593 	efa_com_put_comp_ctx(aq, comp_ctx);
594 	return err;
595 }
596 
597 /*
598  * There are two types to wait for completion.
599  * Polling mode - wait until the completion is available.
600  * Async mode - wait on wait queue until the completion is ready
601  * (or the timeout expired).
602  * It is expected that the IRQ called efa_com_handle_admin_completion
603  * to mark the completions.
604  */
605 static int efa_com_wait_and_process_admin_cq(struct efa_comp_ctx *comp_ctx,
606 					     struct efa_com_admin_queue *aq)
607 {
608 	if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
609 		return efa_com_wait_and_process_admin_cq_polling(comp_ctx, aq);
610 
611 	return efa_com_wait_and_process_admin_cq_interrupts(comp_ctx, aq);
612 }
613 
614 /**
615  * efa_com_cmd_exec - Execute admin command
616  * @aq: admin queue.
617  * @cmd: the admin command to execute.
618  * @cmd_size: the command size.
619  * @comp: command completion return entry.
620  * @comp_size: command completion size.
621  * Submit an admin command and then wait until the device will return a
622  * completion.
623  * The completion will be copied into comp.
624  *
625  * @return - 0 on success, negative value on failure.
626  */
627 int efa_com_cmd_exec(struct efa_com_admin_queue *aq,
628 		     struct efa_admin_aq_entry *cmd,
629 		     size_t cmd_size,
630 		     struct efa_admin_acq_entry *comp,
631 		     size_t comp_size)
632 {
633 	struct efa_comp_ctx *comp_ctx;
634 	int err;
635 
636 	might_sleep();
637 
638 	/* In case of queue FULL */
639 	down(&aq->avail_cmds);
640 
641 	ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n",
642 		  efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
643 		  cmd->aq_common_descriptor.opcode);
644 	comp_ctx = efa_com_submit_admin_cmd(aq, cmd, cmd_size, comp, comp_size);
645 	if (IS_ERR(comp_ctx)) {
646 		ibdev_err(aq->efa_dev,
647 			  "Failed to submit command %s (opcode %u) err %ld\n",
648 			  efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
649 			  cmd->aq_common_descriptor.opcode, PTR_ERR(comp_ctx));
650 
651 		up(&aq->avail_cmds);
652 		return PTR_ERR(comp_ctx);
653 	}
654 
655 	err = efa_com_wait_and_process_admin_cq(comp_ctx, aq);
656 	if (err)
657 		ibdev_err(aq->efa_dev,
658 			  "Failed to process command %s (opcode %u) comp_status %d err %d\n",
659 			  efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
660 			  cmd->aq_common_descriptor.opcode,
661 			  comp_ctx->comp_status, err);
662 
663 	up(&aq->avail_cmds);
664 
665 	return err;
666 }
667 
668 /**
669  * efa_com_abort_admin_commands - Abort all the outstanding admin commands.
670  * @edev: EFA communication layer struct
671  *
672  * This method aborts all the outstanding admin commands.
673  * The caller should then call efa_com_wait_for_abort_completion to make sure
674  * all the commands were completed.
675  */
676 static void efa_com_abort_admin_commands(struct efa_com_dev *edev)
677 {
678 	struct efa_com_admin_queue *aq = &edev->aq;
679 	struct efa_comp_ctx *comp_ctx;
680 	unsigned long flags;
681 	u16 i;
682 
683 	spin_lock(&aq->sq.lock);
684 	spin_lock_irqsave(&aq->cq.lock, flags);
685 	for (i = 0; i < aq->depth; i++) {
686 		comp_ctx = efa_com_get_comp_ctx(aq, i, false);
687 		if (!comp_ctx)
688 			break;
689 
690 		comp_ctx->status = EFA_CMD_ABORTED;
691 
692 		complete(&comp_ctx->wait_event);
693 	}
694 	spin_unlock_irqrestore(&aq->cq.lock, flags);
695 	spin_unlock(&aq->sq.lock);
696 }
697 
698 /**
699  * efa_com_wait_for_abort_completion - Wait for admin commands abort.
700  * @edev: EFA communication layer struct
701  *
702  * This method wait until all the outstanding admin commands will be completed.
703  */
704 static void efa_com_wait_for_abort_completion(struct efa_com_dev *edev)
705 {
706 	struct efa_com_admin_queue *aq = &edev->aq;
707 	int i;
708 
709 	/* all mine */
710 	for (i = 0; i < aq->depth; i++)
711 		down(&aq->avail_cmds);
712 
713 	/* let it go */
714 	for (i = 0; i < aq->depth; i++)
715 		up(&aq->avail_cmds);
716 }
717 
718 static void efa_com_admin_flush(struct efa_com_dev *edev)
719 {
720 	struct efa_com_admin_queue *aq = &edev->aq;
721 
722 	clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
723 
724 	efa_com_abort_admin_commands(edev);
725 	efa_com_wait_for_abort_completion(edev);
726 }
727 
728 /**
729  * efa_com_admin_destroy - Destroy the admin and the async events queues.
730  * @edev: EFA communication layer struct
731  */
732 void efa_com_admin_destroy(struct efa_com_dev *edev)
733 {
734 	struct efa_com_admin_queue *aq = &edev->aq;
735 	struct efa_com_aenq *aenq = &edev->aenq;
736 	struct efa_com_admin_cq *cq = &aq->cq;
737 	struct efa_com_admin_sq *sq = &aq->sq;
738 	u16 size;
739 
740 	efa_com_admin_flush(edev);
741 
742 	devm_kfree(edev->dmadev, aq->comp_ctx_pool);
743 	devm_kfree(edev->dmadev, aq->comp_ctx);
744 
745 	size = aq->depth * sizeof(*sq->entries);
746 	dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr);
747 
748 	size = aq->depth * sizeof(*cq->entries);
749 	dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr);
750 
751 	size = aenq->depth * sizeof(*aenq->entries);
752 	dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr);
753 }
754 
755 /**
756  * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode
757  * @edev: EFA communication layer struct
758  * @polling: Enable/Disable polling mode
759  *
760  * Set the admin completion mode.
761  */
762 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling)
763 {
764 	u32 mask_value = 0;
765 
766 	if (polling)
767 		mask_value = EFA_REGS_ADMIN_INTR_MASK;
768 
769 	writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);
770 	if (polling)
771 		set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
772 	else
773 		clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
774 }
775 
776 static void efa_com_stats_init(struct efa_com_dev *edev)
777 {
778 	atomic64_t *s = (atomic64_t *)&edev->aq.stats;
779 	int i;
780 
781 	for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++)
782 		atomic64_set(s, 0);
783 }
784 
785 /**
786  * efa_com_admin_init - Init the admin and the async queues
787  * @edev: EFA communication layer struct
788  * @aenq_handlers: Those handlers to be called upon event.
789  *
790  * Initialize the admin submission and completion queues.
791  * Initialize the asynchronous events notification queues.
792  *
793  * @return - 0 on success, negative value on failure.
794  */
795 int efa_com_admin_init(struct efa_com_dev *edev,
796 		       struct efa_aenq_handlers *aenq_handlers)
797 {
798 	struct efa_com_admin_queue *aq = &edev->aq;
799 	u32 timeout;
800 	u32 dev_sts;
801 	u32 cap;
802 	int err;
803 
804 	dev_sts = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
805 	if (!(dev_sts & EFA_REGS_DEV_STS_READY_MASK)) {
806 		ibdev_err(edev->efa_dev,
807 			  "Device isn't ready, abort com init %#x\n", dev_sts);
808 		return -ENODEV;
809 	}
810 
811 	aq->depth = EFA_ADMIN_QUEUE_DEPTH;
812 
813 	aq->dmadev = edev->dmadev;
814 	aq->efa_dev = edev->efa_dev;
815 	set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state);
816 
817 	sema_init(&aq->avail_cmds, aq->depth);
818 
819 	efa_com_stats_init(edev);
820 
821 	err = efa_com_init_comp_ctxt(aq);
822 	if (err)
823 		return err;
824 
825 	err = efa_com_admin_init_sq(edev);
826 	if (err)
827 		goto err_destroy_comp_ctxt;
828 
829 	err = efa_com_admin_init_cq(edev);
830 	if (err)
831 		goto err_destroy_sq;
832 
833 	efa_com_set_admin_polling_mode(edev, false);
834 
835 	err = efa_com_admin_init_aenq(edev, aenq_handlers);
836 	if (err)
837 		goto err_destroy_cq;
838 
839 	cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
840 	timeout = (cap & EFA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
841 		  EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
842 	if (timeout)
843 		/* the resolution of timeout reg is 100ms */
844 		aq->completion_timeout = timeout * 100000;
845 	else
846 		aq->completion_timeout = ADMIN_CMD_TIMEOUT_US;
847 
848 	aq->poll_interval = EFA_POLL_INTERVAL_MS;
849 
850 	set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
851 
852 	return 0;
853 
854 err_destroy_cq:
855 	dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries),
856 			  aq->cq.entries, aq->cq.dma_addr);
857 err_destroy_sq:
858 	dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries),
859 			  aq->sq.entries, aq->sq.dma_addr);
860 err_destroy_comp_ctxt:
861 	devm_kfree(edev->dmadev, aq->comp_ctx);
862 
863 	return err;
864 }
865 
866 /**
867  * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler
868  * @edev: EFA communication layer struct
869  *
870  * This method goes over the admin completion queue and wakes up
871  * all the pending threads that wait on the commands wait event.
872  *
873  * @note: Should be called after MSI-X interrupt.
874  */
875 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev)
876 {
877 	unsigned long flags;
878 
879 	spin_lock_irqsave(&edev->aq.cq.lock, flags);
880 	efa_com_handle_admin_completion(&edev->aq);
881 	spin_unlock_irqrestore(&edev->aq.cq.lock, flags);
882 }
883 
884 /*
885  * efa_handle_specific_aenq_event:
886  * return the handler that is relevant to the specific event group
887  */
888 static efa_aenq_handler efa_com_get_specific_aenq_cb(struct efa_com_dev *edev,
889 						     u16 group)
890 {
891 	struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers;
892 
893 	if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group])
894 		return aenq_handlers->handlers[group];
895 
896 	return aenq_handlers->unimplemented_handler;
897 }
898 
899 /**
900  * efa_com_aenq_intr_handler - AENQ interrupt handler
901  * @edev: EFA communication layer struct
902  * @data: Data of interrupt handler.
903  *
904  * Go over the async event notification queue and call the proper aenq handler.
905  */
906 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data)
907 {
908 	struct efa_admin_aenq_common_desc *aenq_common;
909 	struct efa_com_aenq *aenq = &edev->aenq;
910 	struct efa_admin_aenq_entry *aenq_e;
911 	efa_aenq_handler handler_cb;
912 	u32 processed = 0;
913 	u8 phase;
914 	u32 ci;
915 
916 	ci = aenq->cc & (aenq->depth - 1);
917 	phase = aenq->phase;
918 	aenq_e = &aenq->entries[ci]; /* Get first entry */
919 	aenq_common = &aenq_e->aenq_common_desc;
920 
921 	/* Go over all the events */
922 	while ((READ_ONCE(aenq_common->flags) &
923 		EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
924 		/*
925 		 * Do not read the rest of the completion entry before the
926 		 * phase bit was validated
927 		 */
928 		dma_rmb();
929 
930 		/* Handle specific event*/
931 		handler_cb = efa_com_get_specific_aenq_cb(edev,
932 							  aenq_common->group);
933 		handler_cb(data, aenq_e); /* call the actual event handler*/
934 
935 		/* Get next event entry */
936 		ci++;
937 		processed++;
938 
939 		if (ci == aenq->depth) {
940 			ci = 0;
941 			phase = !phase;
942 		}
943 		aenq_e = &aenq->entries[ci];
944 		aenq_common = &aenq_e->aenq_common_desc;
945 	}
946 
947 	aenq->cc += processed;
948 	aenq->phase = phase;
949 
950 	/* Don't update aenq doorbell if there weren't any processed events */
951 	if (!processed)
952 		return;
953 
954 	/* barrier not needed in case of writel */
955 	writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
956 }
957 
958 static void efa_com_mmio_reg_read_resp_addr_init(struct efa_com_dev *edev)
959 {
960 	struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
961 	u32 addr_high;
962 	u32 addr_low;
963 
964 	/* dma_addr_bits is unknown at this point */
965 	addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0);
966 	addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0);
967 
968 	writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);
969 	writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);
970 }
971 
972 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev)
973 {
974 	struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
975 
976 	spin_lock_init(&mmio_read->lock);
977 	mmio_read->read_resp =
978 		dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
979 				   &mmio_read->read_resp_dma_addr, GFP_KERNEL);
980 	if (!mmio_read->read_resp)
981 		return -ENOMEM;
982 
983 	efa_com_mmio_reg_read_resp_addr_init(edev);
984 
985 	mmio_read->read_resp->req_id = 0;
986 	mmio_read->seq_num = 0;
987 	mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US;
988 
989 	return 0;
990 }
991 
992 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev)
993 {
994 	struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
995 
996 	dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
997 			  mmio_read->read_resp, mmio_read->read_resp_dma_addr);
998 }
999 
1000 int efa_com_validate_version(struct efa_com_dev *edev)
1001 {
1002 	u32 ctrl_ver_masked;
1003 	u32 ctrl_ver;
1004 	u32 ver;
1005 
1006 	/*
1007 	 * Make sure the EFA version and the controller version are at least
1008 	 * as the driver expects
1009 	 */
1010 	ver = efa_com_reg_read32(edev, EFA_REGS_VERSION_OFF);
1011 	ctrl_ver = efa_com_reg_read32(edev,
1012 				      EFA_REGS_CONTROLLER_VERSION_OFF);
1013 
1014 	ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n",
1015 		  (ver & EFA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1016 			  EFA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1017 		  ver & EFA_REGS_VERSION_MINOR_VERSION_MASK);
1018 
1019 	if (ver < MIN_EFA_VER) {
1020 		ibdev_err(edev->efa_dev,
1021 			  "EFA version is lower than the minimal version the driver supports\n");
1022 		return -EOPNOTSUPP;
1023 	}
1024 
1025 	ibdev_dbg(edev->efa_dev,
1026 		  "efa controller version: %d.%d.%d implementation version %d\n",
1027 		  (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1028 			  EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1029 		  (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1030 			  EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1031 		  (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1032 		  (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1033 			  EFA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1034 
1035 	ctrl_ver_masked =
1036 		(ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1037 		(ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1038 		(ctrl_ver & EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1039 
1040 	/* Validate the ctrl version without the implementation ID */
1041 	if (ctrl_ver_masked < MIN_EFA_CTRL_VER) {
1042 		ibdev_err(edev->efa_dev,
1043 			  "EFA ctrl version is lower than the minimal ctrl version the driver supports\n");
1044 		return -EOPNOTSUPP;
1045 	}
1046 
1047 	return 0;
1048 }
1049 
1050 /**
1051  * efa_com_get_dma_width - Retrieve physical dma address width the device
1052  * supports.
1053  * @edev: EFA communication layer struct
1054  *
1055  * Retrieve the maximum physical address bits the device can handle.
1056  *
1057  * @return: > 0 on Success and negative value otherwise.
1058  */
1059 int efa_com_get_dma_width(struct efa_com_dev *edev)
1060 {
1061 	u32 caps = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1062 	int width;
1063 
1064 	width = (caps & EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1065 		EFA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1066 
1067 	ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width);
1068 
1069 	if (width < 32 || width > 64) {
1070 		ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width);
1071 		return -EINVAL;
1072 	}
1073 
1074 	edev->dma_addr_bits = width;
1075 
1076 	return width;
1077 }
1078 
1079 static int wait_for_reset_state(struct efa_com_dev *edev, u32 timeout,
1080 				u16 exp_state)
1081 {
1082 	u32 val, i;
1083 
1084 	for (i = 0; i < timeout; i++) {
1085 		val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1086 
1087 		if ((val & EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
1088 		    exp_state)
1089 			return 0;
1090 
1091 		ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val);
1092 		msleep(EFA_POLL_INTERVAL_MS);
1093 	}
1094 
1095 	return -ETIME;
1096 }
1097 
1098 /**
1099  * efa_com_dev_reset - Perform device FLR to the device.
1100  * @edev: EFA communication layer struct
1101  * @reset_reason: Specify what is the trigger for the reset in case of an error.
1102  *
1103  * @return - 0 on success, negative value on failure.
1104  */
1105 int efa_com_dev_reset(struct efa_com_dev *edev,
1106 		      enum efa_regs_reset_reason_types reset_reason)
1107 {
1108 	u32 stat, timeout, cap, reset_val;
1109 	int err;
1110 
1111 	stat = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1112 	cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1113 
1114 	if (!(stat & EFA_REGS_DEV_STS_READY_MASK)) {
1115 		ibdev_err(edev->efa_dev,
1116 			  "Device isn't ready, can't reset device\n");
1117 		return -EINVAL;
1118 	}
1119 
1120 	timeout = (cap & EFA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1121 		  EFA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1122 	if (!timeout) {
1123 		ibdev_err(edev->efa_dev, "Invalid timeout value\n");
1124 		return -EINVAL;
1125 	}
1126 
1127 	/* start reset */
1128 	reset_val = EFA_REGS_DEV_CTL_DEV_RESET_MASK;
1129 	reset_val |= (reset_reason << EFA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
1130 		     EFA_REGS_DEV_CTL_RESET_REASON_MASK;
1131 	writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1132 
1133 	/* reset clears the mmio readless address, restore it */
1134 	efa_com_mmio_reg_read_resp_addr_init(edev);
1135 
1136 	err = wait_for_reset_state(edev, timeout,
1137 				   EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1138 	if (err) {
1139 		ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n");
1140 		return err;
1141 	}
1142 
1143 	/* reset done */
1144 	writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1145 	err = wait_for_reset_state(edev, timeout, 0);
1146 	if (err) {
1147 		ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n");
1148 		return err;
1149 	}
1150 
1151 	timeout = (cap & EFA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
1152 		  EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
1153 	if (timeout)
1154 		/* the resolution of timeout reg is 100ms */
1155 		edev->aq.completion_timeout = timeout * 100000;
1156 	else
1157 		edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US;
1158 
1159 	return 0;
1160 }
1161