1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_CMDS_H_ 7 #define _EFA_ADMIN_CMDS_H_ 8 9 #define EFA_ADMIN_API_VERSION_MAJOR 0 10 #define EFA_ADMIN_API_VERSION_MINOR 1 11 12 /* EFA admin queue opcodes */ 13 enum efa_admin_aq_opcode { 14 EFA_ADMIN_CREATE_QP = 1, 15 EFA_ADMIN_MODIFY_QP = 2, 16 EFA_ADMIN_QUERY_QP = 3, 17 EFA_ADMIN_DESTROY_QP = 4, 18 EFA_ADMIN_CREATE_AH = 5, 19 EFA_ADMIN_DESTROY_AH = 6, 20 EFA_ADMIN_REG_MR = 7, 21 EFA_ADMIN_DEREG_MR = 8, 22 EFA_ADMIN_CREATE_CQ = 9, 23 EFA_ADMIN_DESTROY_CQ = 10, 24 EFA_ADMIN_GET_FEATURE = 11, 25 EFA_ADMIN_SET_FEATURE = 12, 26 EFA_ADMIN_GET_STATS = 13, 27 EFA_ADMIN_ALLOC_PD = 14, 28 EFA_ADMIN_DEALLOC_PD = 15, 29 EFA_ADMIN_ALLOC_UAR = 16, 30 EFA_ADMIN_DEALLOC_UAR = 17, 31 EFA_ADMIN_MAX_OPCODE = 17, 32 }; 33 34 enum efa_admin_aq_feature_id { 35 EFA_ADMIN_DEVICE_ATTR = 1, 36 EFA_ADMIN_AENQ_CONFIG = 2, 37 EFA_ADMIN_NETWORK_ATTR = 3, 38 EFA_ADMIN_QUEUE_ATTR = 4, 39 EFA_ADMIN_HW_HINTS = 5, 40 EFA_ADMIN_HOST_INFO = 6, 41 }; 42 43 /* QP transport type */ 44 enum efa_admin_qp_type { 45 /* Unreliable Datagram */ 46 EFA_ADMIN_QP_TYPE_UD = 1, 47 /* Scalable Reliable Datagram */ 48 EFA_ADMIN_QP_TYPE_SRD = 2, 49 }; 50 51 /* QP state */ 52 enum efa_admin_qp_state { 53 EFA_ADMIN_QP_STATE_RESET = 0, 54 EFA_ADMIN_QP_STATE_INIT = 1, 55 EFA_ADMIN_QP_STATE_RTR = 2, 56 EFA_ADMIN_QP_STATE_RTS = 3, 57 EFA_ADMIN_QP_STATE_SQD = 4, 58 EFA_ADMIN_QP_STATE_SQE = 5, 59 EFA_ADMIN_QP_STATE_ERR = 6, 60 }; 61 62 enum efa_admin_get_stats_type { 63 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0, 64 EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1, 65 EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2, 66 }; 67 68 enum efa_admin_get_stats_scope { 69 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0, 70 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1, 71 }; 72 73 /* 74 * QP allocation sizes, converted by fabric QueuePair (QP) create command 75 * from QP capabilities. 76 */ 77 struct efa_admin_qp_alloc_size { 78 /* Send descriptor ring size in bytes */ 79 u32 send_queue_ring_size; 80 81 /* Max number of WQEs that can be outstanding on send queue. */ 82 u32 send_queue_depth; 83 84 /* 85 * Recv descriptor ring size in bytes, sufficient for user-provided 86 * number of WQEs 87 */ 88 u32 recv_queue_ring_size; 89 90 /* Max number of WQEs that can be outstanding on recv queue */ 91 u32 recv_queue_depth; 92 }; 93 94 struct efa_admin_create_qp_cmd { 95 /* Common Admin Queue descriptor */ 96 struct efa_admin_aq_common_desc aq_common_desc; 97 98 /* Protection Domain associated with this QP */ 99 u16 pd; 100 101 /* QP type */ 102 u8 qp_type; 103 104 /* 105 * 0 : sq_virt - If set, SQ ring base address is 106 * virtual (IOVA returned by MR registration) 107 * 1 : rq_virt - If set, RQ ring base address is 108 * virtual (IOVA returned by MR registration) 109 * 7:2 : reserved - MBZ 110 */ 111 u8 flags; 112 113 /* 114 * Send queue (SQ) ring base physical address. This field is not 115 * used if this is a Low Latency Queue(LLQ). 116 */ 117 u64 sq_base_addr; 118 119 /* Receive queue (RQ) ring base address. */ 120 u64 rq_base_addr; 121 122 /* Index of CQ to be associated with Send Queue completions */ 123 u32 send_cq_idx; 124 125 /* Index of CQ to be associated with Recv Queue completions */ 126 u32 recv_cq_idx; 127 128 /* 129 * Memory registration key for the SQ ring, used only when not in 130 * LLQ mode and base address is virtual 131 */ 132 u32 sq_l_key; 133 134 /* 135 * Memory registration key for the RQ ring, used only when base 136 * address is virtual 137 */ 138 u32 rq_l_key; 139 140 /* Requested QP allocation sizes */ 141 struct efa_admin_qp_alloc_size qp_alloc_size; 142 143 /* UAR number */ 144 u16 uar; 145 146 /* MBZ */ 147 u16 reserved; 148 149 /* MBZ */ 150 u32 reserved2; 151 }; 152 153 struct efa_admin_create_qp_resp { 154 /* Common Admin Queue completion descriptor */ 155 struct efa_admin_acq_common_desc acq_common_desc; 156 157 /* 158 * Opaque handle to be used for consequent admin operations on the 159 * QP 160 */ 161 u32 qp_handle; 162 163 /* 164 * QP number in the given EFA virtual device. Least-significant bits (as 165 * needed according to max_qp) carry unique QP ID 166 */ 167 u16 qp_num; 168 169 /* MBZ */ 170 u16 reserved; 171 172 /* Index of sub-CQ for Send Queue completions */ 173 u16 send_sub_cq_idx; 174 175 /* Index of sub-CQ for Receive Queue completions */ 176 u16 recv_sub_cq_idx; 177 178 /* SQ doorbell address, as offset to PCIe DB BAR */ 179 u32 sq_db_offset; 180 181 /* RQ doorbell address, as offset to PCIe DB BAR */ 182 u32 rq_db_offset; 183 184 /* 185 * low latency send queue ring base address as an offset to PCIe 186 * MMIO LLQ_MEM BAR 187 */ 188 u32 llq_descriptors_offset; 189 }; 190 191 struct efa_admin_modify_qp_cmd { 192 /* Common Admin Queue descriptor */ 193 struct efa_admin_aq_common_desc aq_common_desc; 194 195 /* 196 * Mask indicating which fields should be updated 197 * 0 : qp_state 198 * 1 : cur_qp_state 199 * 2 : qkey 200 * 3 : sq_psn 201 * 4 : sq_drained_async_notify 202 * 5 : rnr_retry 203 * 31:6 : reserved 204 */ 205 u32 modify_mask; 206 207 /* QP handle returned by create_qp command */ 208 u32 qp_handle; 209 210 /* QP state */ 211 u32 qp_state; 212 213 /* Override current QP state (before applying the transition) */ 214 u32 cur_qp_state; 215 216 /* QKey */ 217 u32 qkey; 218 219 /* SQ PSN */ 220 u32 sq_psn; 221 222 /* Enable async notification when SQ is drained */ 223 u8 sq_drained_async_notify; 224 225 /* Number of RNR retries (valid only for SRD QPs) */ 226 u8 rnr_retry; 227 228 /* MBZ */ 229 u16 reserved2; 230 }; 231 232 struct efa_admin_modify_qp_resp { 233 /* Common Admin Queue completion descriptor */ 234 struct efa_admin_acq_common_desc acq_common_desc; 235 }; 236 237 struct efa_admin_query_qp_cmd { 238 /* Common Admin Queue descriptor */ 239 struct efa_admin_aq_common_desc aq_common_desc; 240 241 /* QP handle returned by create_qp command */ 242 u32 qp_handle; 243 }; 244 245 struct efa_admin_query_qp_resp { 246 /* Common Admin Queue completion descriptor */ 247 struct efa_admin_acq_common_desc acq_common_desc; 248 249 /* QP state */ 250 u32 qp_state; 251 252 /* QKey */ 253 u32 qkey; 254 255 /* SQ PSN */ 256 u32 sq_psn; 257 258 /* Indicates that draining is in progress */ 259 u8 sq_draining; 260 261 /* Number of RNR retries (valid only for SRD QPs) */ 262 u8 rnr_retry; 263 264 /* MBZ */ 265 u16 reserved2; 266 }; 267 268 struct efa_admin_destroy_qp_cmd { 269 /* Common Admin Queue descriptor */ 270 struct efa_admin_aq_common_desc aq_common_desc; 271 272 /* QP handle returned by create_qp command */ 273 u32 qp_handle; 274 }; 275 276 struct efa_admin_destroy_qp_resp { 277 /* Common Admin Queue completion descriptor */ 278 struct efa_admin_acq_common_desc acq_common_desc; 279 }; 280 281 /* 282 * Create Address Handle command parameters. Must not be called more than 283 * once for the same destination 284 */ 285 struct efa_admin_create_ah_cmd { 286 /* Common Admin Queue descriptor */ 287 struct efa_admin_aq_common_desc aq_common_desc; 288 289 /* Destination address in network byte order */ 290 u8 dest_addr[16]; 291 292 /* PD number */ 293 u16 pd; 294 295 /* MBZ */ 296 u16 reserved; 297 }; 298 299 struct efa_admin_create_ah_resp { 300 /* Common Admin Queue completion descriptor */ 301 struct efa_admin_acq_common_desc acq_common_desc; 302 303 /* Target interface address handle (opaque) */ 304 u16 ah; 305 306 /* MBZ */ 307 u16 reserved; 308 }; 309 310 struct efa_admin_destroy_ah_cmd { 311 /* Common Admin Queue descriptor */ 312 struct efa_admin_aq_common_desc aq_common_desc; 313 314 /* Target interface address handle (opaque) */ 315 u16 ah; 316 317 /* PD number */ 318 u16 pd; 319 }; 320 321 struct efa_admin_destroy_ah_resp { 322 /* Common Admin Queue completion descriptor */ 323 struct efa_admin_acq_common_desc acq_common_desc; 324 }; 325 326 /* 327 * Registration of MemoryRegion, required for QP working with Virtual 328 * Addresses. In standard verbs semantics, region length is limited to 2GB 329 * space, but EFA offers larger MR support for large memory space, to ease 330 * on users working with very large datasets (i.e. full GPU memory mapping). 331 */ 332 struct efa_admin_reg_mr_cmd { 333 /* Common Admin Queue descriptor */ 334 struct efa_admin_aq_common_desc aq_common_desc; 335 336 /* Protection Domain */ 337 u16 pd; 338 339 /* MBZ */ 340 u16 reserved16_w1; 341 342 /* Physical Buffer List, each element is page-aligned. */ 343 union { 344 /* 345 * Inline array of guest-physical page addresses of user 346 * memory pages (optimization for short region 347 * registrations) 348 */ 349 u64 inline_pbl_array[4]; 350 351 /* points to PBL (direct or indirect, chained if needed) */ 352 struct efa_admin_ctrl_buff_info pbl; 353 } pbl; 354 355 /* Memory region length, in bytes. */ 356 u64 mr_length; 357 358 /* 359 * flags and page size 360 * 4:0 : phys_page_size_shift - page size is (1 << 361 * phys_page_size_shift). Page size is used for 362 * building the Virtual to Physical address mapping 363 * 6:5 : reserved - MBZ 364 * 7 : mem_addr_phy_mode_en - Enable bit for physical 365 * memory registration (no translation), can be used 366 * only by privileged clients. If set, PBL must 367 * contain a single entry. 368 */ 369 u8 flags; 370 371 /* 372 * permissions 373 * 0 : local_write_enable - Local write permissions: 374 * must be set for RQ buffers and buffers posted for 375 * RDMA Read requests 376 * 1 : reserved1 - MBZ 377 * 2 : remote_read_enable - Remote read permissions: 378 * must be set to enable RDMA read from the region 379 * 7:3 : reserved2 - MBZ 380 */ 381 u8 permissions; 382 383 /* MBZ */ 384 u16 reserved16_w5; 385 386 /* number of pages in PBL (redundant, could be calculated) */ 387 u32 page_num; 388 389 /* 390 * IO Virtual Address associated with this MR. If 391 * mem_addr_phy_mode_en is set, contains the physical address of 392 * the region. 393 */ 394 u64 iova; 395 }; 396 397 struct efa_admin_reg_mr_resp { 398 /* Common Admin Queue completion descriptor */ 399 struct efa_admin_acq_common_desc acq_common_desc; 400 401 /* 402 * L_Key, to be used in conjunction with local buffer references in 403 * SQ and RQ WQE, or with virtual RQ/CQ rings 404 */ 405 u32 l_key; 406 407 /* 408 * R_Key, to be used in RDMA messages to refer to remotely accessed 409 * memory region 410 */ 411 u32 r_key; 412 }; 413 414 struct efa_admin_dereg_mr_cmd { 415 /* Common Admin Queue descriptor */ 416 struct efa_admin_aq_common_desc aq_common_desc; 417 418 /* L_Key, memory region's l_key */ 419 u32 l_key; 420 }; 421 422 struct efa_admin_dereg_mr_resp { 423 /* Common Admin Queue completion descriptor */ 424 struct efa_admin_acq_common_desc acq_common_desc; 425 }; 426 427 struct efa_admin_create_cq_cmd { 428 struct efa_admin_aq_common_desc aq_common_desc; 429 430 /* 431 * 4:0 : reserved5 - MBZ 432 * 5 : interrupt_mode_enabled - if set, cq operates 433 * in interrupt mode (i.e. CQ events and MSI-X are 434 * generated), otherwise - polling 435 * 6 : virt - If set, ring base address is virtual 436 * (IOVA returned by MR registration) 437 * 7 : reserved6 - MBZ 438 */ 439 u8 cq_caps_1; 440 441 /* 442 * 4:0 : cq_entry_size_words - size of CQ entry in 443 * 32-bit words, valid values: 4, 8. 444 * 7:5 : reserved7 - MBZ 445 */ 446 u8 cq_caps_2; 447 448 /* completion queue depth in # of entries. must be power of 2 */ 449 u16 cq_depth; 450 451 /* msix vector assigned to this cq */ 452 u32 msix_vector_idx; 453 454 /* 455 * CQ ring base address, virtual or physical depending on 'virt' 456 * flag 457 */ 458 struct efa_common_mem_addr cq_ba; 459 460 /* 461 * Memory registration key for the ring, used only when base 462 * address is virtual 463 */ 464 u32 l_key; 465 466 /* 467 * number of sub cqs - must be equal to sub_cqs_per_cq of queue 468 * attributes. 469 */ 470 u16 num_sub_cqs; 471 472 /* UAR number */ 473 u16 uar; 474 }; 475 476 struct efa_admin_create_cq_resp { 477 struct efa_admin_acq_common_desc acq_common_desc; 478 479 u16 cq_idx; 480 481 /* actual cq depth in number of entries */ 482 u16 cq_actual_depth; 483 }; 484 485 struct efa_admin_destroy_cq_cmd { 486 struct efa_admin_aq_common_desc aq_common_desc; 487 488 u16 cq_idx; 489 490 /* MBZ */ 491 u16 reserved1; 492 }; 493 494 struct efa_admin_destroy_cq_resp { 495 struct efa_admin_acq_common_desc acq_common_desc; 496 }; 497 498 /* 499 * EFA AQ Get Statistics command. Extended statistics are placed in control 500 * buffer pointed by AQ entry 501 */ 502 struct efa_admin_aq_get_stats_cmd { 503 struct efa_admin_aq_common_desc aq_common_descriptor; 504 505 union { 506 /* command specific inline data */ 507 u32 inline_data_w1[3]; 508 509 struct efa_admin_ctrl_buff_info control_buffer; 510 } u; 511 512 /* stats type as defined in enum efa_admin_get_stats_type */ 513 u8 type; 514 515 /* stats scope defined in enum efa_admin_get_stats_scope */ 516 u8 scope; 517 518 u16 scope_modifier; 519 }; 520 521 struct efa_admin_basic_stats { 522 u64 tx_bytes; 523 524 u64 tx_pkts; 525 526 u64 rx_bytes; 527 528 u64 rx_pkts; 529 530 u64 rx_drops; 531 }; 532 533 struct efa_admin_messages_stats { 534 u64 send_bytes; 535 536 u64 send_wrs; 537 538 u64 recv_bytes; 539 540 u64 recv_wrs; 541 }; 542 543 struct efa_admin_rdma_read_stats { 544 u64 read_wrs; 545 546 u64 read_bytes; 547 548 u64 read_wr_err; 549 550 u64 read_resp_bytes; 551 }; 552 553 struct efa_admin_acq_get_stats_resp { 554 struct efa_admin_acq_common_desc acq_common_desc; 555 556 union { 557 struct efa_admin_basic_stats basic_stats; 558 559 struct efa_admin_messages_stats messages_stats; 560 561 struct efa_admin_rdma_read_stats rdma_read_stats; 562 } u; 563 }; 564 565 struct efa_admin_get_set_feature_common_desc { 566 /* MBZ */ 567 u8 reserved0; 568 569 /* as appears in efa_admin_aq_feature_id */ 570 u8 feature_id; 571 572 /* MBZ */ 573 u16 reserved16; 574 }; 575 576 struct efa_admin_feature_device_attr_desc { 577 /* Bitmap of efa_admin_aq_feature_id */ 578 u64 supported_features; 579 580 /* Bitmap of supported page sizes in MR registrations */ 581 u64 page_size_cap; 582 583 u32 fw_version; 584 585 u32 admin_api_version; 586 587 u32 device_version; 588 589 /* Bar used for SQ and RQ doorbells */ 590 u16 db_bar; 591 592 /* Indicates how many bits are used on physical address access */ 593 u8 phys_addr_width; 594 595 /* Indicates how many bits are used on virtual address access */ 596 u8 virt_addr_width; 597 598 /* 599 * 0 : rdma_read - If set, RDMA Read is supported on 600 * TX queues 601 * 1 : rnr_retry - If set, RNR retry is supported on 602 * modify QP command 603 * 31:2 : reserved - MBZ 604 */ 605 u32 device_caps; 606 607 /* Max RDMA transfer size in bytes */ 608 u32 max_rdma_size; 609 }; 610 611 struct efa_admin_feature_queue_attr_desc { 612 /* The maximum number of queue pairs supported */ 613 u32 max_qp; 614 615 /* Maximum number of WQEs per Send Queue */ 616 u32 max_sq_depth; 617 618 /* Maximum size of data that can be sent inline in a Send WQE */ 619 u32 inline_buf_size; 620 621 /* Maximum number of buffer descriptors per Recv Queue */ 622 u32 max_rq_depth; 623 624 /* The maximum number of completion queues supported per VF */ 625 u32 max_cq; 626 627 /* Maximum number of CQEs per Completion Queue */ 628 u32 max_cq_depth; 629 630 /* Number of sub-CQs to be created for each CQ */ 631 u16 sub_cqs_per_cq; 632 633 /* Minimum number of WQEs per SQ */ 634 u16 min_sq_depth; 635 636 /* Maximum number of SGEs (buffers) allowed for a single send WQE */ 637 u16 max_wr_send_sges; 638 639 /* Maximum number of SGEs allowed for a single recv WQE */ 640 u16 max_wr_recv_sges; 641 642 /* The maximum number of memory regions supported */ 643 u32 max_mr; 644 645 /* The maximum number of pages can be registered */ 646 u32 max_mr_pages; 647 648 /* The maximum number of protection domains supported */ 649 u32 max_pd; 650 651 /* The maximum number of address handles supported */ 652 u32 max_ah; 653 654 /* The maximum size of LLQ in bytes */ 655 u32 max_llq_size; 656 657 /* Maximum number of SGEs for a single RDMA read WQE */ 658 u16 max_wr_rdma_sges; 659 660 /* 661 * Maximum number of bytes that can be written to SQ between two 662 * consecutive doorbells (in units of 64B). Driver must ensure that only 663 * complete WQEs are written to queue before issuing a doorbell. 664 * Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can 665 * be written to SQ between two consecutive doorbells. max_tx_batch=11 666 * and WQE size = 128B, means up to 5 WQEs can be written to SQ between 667 * two consecutive doorbells. Zero means unlimited. 668 */ 669 u16 max_tx_batch; 670 }; 671 672 struct efa_admin_feature_aenq_desc { 673 /* bitmask for AENQ groups the device can report */ 674 u32 supported_groups; 675 676 /* bitmask for AENQ groups to report */ 677 u32 enabled_groups; 678 }; 679 680 struct efa_admin_feature_network_attr_desc { 681 /* Raw address data in network byte order */ 682 u8 addr[16]; 683 684 /* max packet payload size in bytes */ 685 u32 mtu; 686 }; 687 688 /* 689 * When hint value is 0, hints capabilities are not supported or driver 690 * should use its own predefined value 691 */ 692 struct efa_admin_hw_hints { 693 /* value in ms */ 694 u16 mmio_read_timeout; 695 696 /* value in ms */ 697 u16 driver_watchdog_timeout; 698 699 /* value in ms */ 700 u16 admin_completion_timeout; 701 702 /* poll interval in ms */ 703 u16 poll_interval; 704 }; 705 706 struct efa_admin_get_feature_cmd { 707 struct efa_admin_aq_common_desc aq_common_descriptor; 708 709 struct efa_admin_ctrl_buff_info control_buffer; 710 711 struct efa_admin_get_set_feature_common_desc feature_common; 712 713 u32 raw[11]; 714 }; 715 716 struct efa_admin_get_feature_resp { 717 struct efa_admin_acq_common_desc acq_common_desc; 718 719 union { 720 u32 raw[14]; 721 722 struct efa_admin_feature_device_attr_desc device_attr; 723 724 struct efa_admin_feature_aenq_desc aenq; 725 726 struct efa_admin_feature_network_attr_desc network_attr; 727 728 struct efa_admin_feature_queue_attr_desc queue_attr; 729 730 struct efa_admin_hw_hints hw_hints; 731 } u; 732 }; 733 734 struct efa_admin_set_feature_cmd { 735 struct efa_admin_aq_common_desc aq_common_descriptor; 736 737 struct efa_admin_ctrl_buff_info control_buffer; 738 739 struct efa_admin_get_set_feature_common_desc feature_common; 740 741 union { 742 u32 raw[11]; 743 744 /* AENQ configuration */ 745 struct efa_admin_feature_aenq_desc aenq; 746 } u; 747 }; 748 749 struct efa_admin_set_feature_resp { 750 struct efa_admin_acq_common_desc acq_common_desc; 751 752 union { 753 u32 raw[14]; 754 } u; 755 }; 756 757 struct efa_admin_alloc_pd_cmd { 758 struct efa_admin_aq_common_desc aq_common_descriptor; 759 }; 760 761 struct efa_admin_alloc_pd_resp { 762 struct efa_admin_acq_common_desc acq_common_desc; 763 764 /* PD number */ 765 u16 pd; 766 767 /* MBZ */ 768 u16 reserved; 769 }; 770 771 struct efa_admin_dealloc_pd_cmd { 772 struct efa_admin_aq_common_desc aq_common_descriptor; 773 774 /* PD number */ 775 u16 pd; 776 777 /* MBZ */ 778 u16 reserved; 779 }; 780 781 struct efa_admin_dealloc_pd_resp { 782 struct efa_admin_acq_common_desc acq_common_desc; 783 }; 784 785 struct efa_admin_alloc_uar_cmd { 786 struct efa_admin_aq_common_desc aq_common_descriptor; 787 }; 788 789 struct efa_admin_alloc_uar_resp { 790 struct efa_admin_acq_common_desc acq_common_desc; 791 792 /* UAR number */ 793 u16 uar; 794 795 /* MBZ */ 796 u16 reserved; 797 }; 798 799 struct efa_admin_dealloc_uar_cmd { 800 struct efa_admin_aq_common_desc aq_common_descriptor; 801 802 /* UAR number */ 803 u16 uar; 804 805 /* MBZ */ 806 u16 reserved; 807 }; 808 809 struct efa_admin_dealloc_uar_resp { 810 struct efa_admin_acq_common_desc acq_common_desc; 811 }; 812 813 /* asynchronous event notification groups */ 814 enum efa_admin_aenq_group { 815 EFA_ADMIN_FATAL_ERROR = 1, 816 EFA_ADMIN_WARNING = 2, 817 EFA_ADMIN_NOTIFICATION = 3, 818 EFA_ADMIN_KEEP_ALIVE = 4, 819 EFA_ADMIN_AENQ_GROUPS_NUM = 5, 820 }; 821 822 struct efa_admin_mmio_req_read_less_resp { 823 u16 req_id; 824 825 u16 reg_off; 826 827 /* value is valid when poll is cleared */ 828 u32 reg_val; 829 }; 830 831 enum efa_admin_os_type { 832 EFA_ADMIN_OS_LINUX = 0, 833 }; 834 835 struct efa_admin_host_info { 836 /* OS distribution string format */ 837 u8 os_dist_str[128]; 838 839 /* Defined in enum efa_admin_os_type */ 840 u32 os_type; 841 842 /* Kernel version string format */ 843 u8 kernel_ver_str[32]; 844 845 /* Kernel version numeric format */ 846 u32 kernel_ver; 847 848 /* 849 * 7:0 : driver_module_type 850 * 15:8 : driver_sub_minor 851 * 23:16 : driver_minor 852 * 31:24 : driver_major 853 */ 854 u32 driver_ver; 855 856 /* 857 * Device's Bus, Device and Function 858 * 2:0 : function 859 * 7:3 : device 860 * 15:8 : bus 861 */ 862 u16 bdf; 863 864 /* 865 * Spec version 866 * 7:0 : spec_minor 867 * 15:8 : spec_major 868 */ 869 u16 spec_ver; 870 871 /* 872 * 0 : intree - Intree driver 873 * 1 : gdr - GPUDirect RDMA supported 874 * 31:2 : reserved2 875 */ 876 u32 flags; 877 }; 878 879 /* create_qp_cmd */ 880 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0) 881 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1) 882 883 /* modify_qp_cmd */ 884 #define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0) 885 #define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1) 886 #define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2) 887 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3) 888 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4) 889 #define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5) 890 891 /* reg_mr_cmd */ 892 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0) 893 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7) 894 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0) 895 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2) 896 897 /* create_cq_cmd */ 898 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 899 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6) 900 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 901 902 /* feature_device_attr_desc */ 903 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0) 904 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1) 905 906 /* host_info */ 907 #define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0) 908 #define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8) 909 #define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16) 910 #define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24) 911 #define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 912 #define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 913 #define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 914 #define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0) 915 #define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8) 916 #define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0) 917 #define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1) 918 919 #endif /* _EFA_ADMIN_CMDS_H_ */ 920