1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_CMDS_H_ 7 #define _EFA_ADMIN_CMDS_H_ 8 9 #define EFA_ADMIN_API_VERSION_MAJOR 0 10 #define EFA_ADMIN_API_VERSION_MINOR 1 11 12 /* EFA admin queue opcodes */ 13 enum efa_admin_aq_opcode { 14 EFA_ADMIN_CREATE_QP = 1, 15 EFA_ADMIN_MODIFY_QP = 2, 16 EFA_ADMIN_QUERY_QP = 3, 17 EFA_ADMIN_DESTROY_QP = 4, 18 EFA_ADMIN_CREATE_AH = 5, 19 EFA_ADMIN_DESTROY_AH = 6, 20 EFA_ADMIN_REG_MR = 7, 21 EFA_ADMIN_DEREG_MR = 8, 22 EFA_ADMIN_CREATE_CQ = 9, 23 EFA_ADMIN_DESTROY_CQ = 10, 24 EFA_ADMIN_GET_FEATURE = 11, 25 EFA_ADMIN_SET_FEATURE = 12, 26 EFA_ADMIN_GET_STATS = 13, 27 EFA_ADMIN_ALLOC_PD = 14, 28 EFA_ADMIN_DEALLOC_PD = 15, 29 EFA_ADMIN_ALLOC_UAR = 16, 30 EFA_ADMIN_DEALLOC_UAR = 17, 31 EFA_ADMIN_MAX_OPCODE = 17, 32 }; 33 34 enum efa_admin_aq_feature_id { 35 EFA_ADMIN_DEVICE_ATTR = 1, 36 EFA_ADMIN_AENQ_CONFIG = 2, 37 EFA_ADMIN_NETWORK_ATTR = 3, 38 EFA_ADMIN_QUEUE_ATTR = 4, 39 EFA_ADMIN_HW_HINTS = 5, 40 EFA_ADMIN_FEATURES_OPCODE_NUM = 8, 41 }; 42 43 /* QP transport type */ 44 enum efa_admin_qp_type { 45 /* Unreliable Datagram */ 46 EFA_ADMIN_QP_TYPE_UD = 1, 47 /* Scalable Reliable Datagram */ 48 EFA_ADMIN_QP_TYPE_SRD = 2, 49 }; 50 51 /* QP state */ 52 enum efa_admin_qp_state { 53 EFA_ADMIN_QP_STATE_RESET = 0, 54 EFA_ADMIN_QP_STATE_INIT = 1, 55 EFA_ADMIN_QP_STATE_RTR = 2, 56 EFA_ADMIN_QP_STATE_RTS = 3, 57 EFA_ADMIN_QP_STATE_SQD = 4, 58 EFA_ADMIN_QP_STATE_SQE = 5, 59 EFA_ADMIN_QP_STATE_ERR = 6, 60 }; 61 62 enum efa_admin_get_stats_type { 63 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0, 64 }; 65 66 enum efa_admin_get_stats_scope { 67 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0, 68 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1, 69 }; 70 71 enum efa_admin_modify_qp_mask_bits { 72 EFA_ADMIN_QP_STATE_BIT = 0, 73 EFA_ADMIN_CUR_QP_STATE_BIT = 1, 74 EFA_ADMIN_QKEY_BIT = 2, 75 EFA_ADMIN_SQ_PSN_BIT = 3, 76 EFA_ADMIN_SQ_DRAINED_ASYNC_NOTIFY_BIT = 4, 77 }; 78 79 /* 80 * QP allocation sizes, converted by fabric QueuePair (QP) create command 81 * from QP capabilities. 82 */ 83 struct efa_admin_qp_alloc_size { 84 /* Send descriptor ring size in bytes */ 85 u32 send_queue_ring_size; 86 87 /* Max number of WQEs that can be outstanding on send queue. */ 88 u32 send_queue_depth; 89 90 /* 91 * Recv descriptor ring size in bytes, sufficient for user-provided 92 * number of WQEs 93 */ 94 u32 recv_queue_ring_size; 95 96 /* Max number of WQEs that can be outstanding on recv queue */ 97 u32 recv_queue_depth; 98 }; 99 100 struct efa_admin_create_qp_cmd { 101 /* Common Admin Queue descriptor */ 102 struct efa_admin_aq_common_desc aq_common_desc; 103 104 /* Protection Domain associated with this QP */ 105 u16 pd; 106 107 /* QP type */ 108 u8 qp_type; 109 110 /* 111 * 0 : sq_virt - If set, SQ ring base address is 112 * virtual (IOVA returned by MR registration) 113 * 1 : rq_virt - If set, RQ ring base address is 114 * virtual (IOVA returned by MR registration) 115 * 7:2 : reserved - MBZ 116 */ 117 u8 flags; 118 119 /* 120 * Send queue (SQ) ring base physical address. This field is not 121 * used if this is a Low Latency Queue(LLQ). 122 */ 123 u64 sq_base_addr; 124 125 /* Receive queue (RQ) ring base address. */ 126 u64 rq_base_addr; 127 128 /* Index of CQ to be associated with Send Queue completions */ 129 u32 send_cq_idx; 130 131 /* Index of CQ to be associated with Recv Queue completions */ 132 u32 recv_cq_idx; 133 134 /* 135 * Memory registration key for the SQ ring, used only when not in 136 * LLQ mode and base address is virtual 137 */ 138 u32 sq_l_key; 139 140 /* 141 * Memory registration key for the RQ ring, used only when base 142 * address is virtual 143 */ 144 u32 rq_l_key; 145 146 /* Requested QP allocation sizes */ 147 struct efa_admin_qp_alloc_size qp_alloc_size; 148 149 /* UAR number */ 150 u16 uar; 151 152 /* MBZ */ 153 u16 reserved; 154 155 /* MBZ */ 156 u32 reserved2; 157 }; 158 159 struct efa_admin_create_qp_resp { 160 /* Common Admin Queue completion descriptor */ 161 struct efa_admin_acq_common_desc acq_common_desc; 162 163 /* Opaque handle to be used for consequent operations on the QP */ 164 u32 qp_handle; 165 166 /* QP number in the given EFA virtual device */ 167 u16 qp_num; 168 169 /* MBZ */ 170 u16 reserved; 171 172 /* Index of sub-CQ for Send Queue completions */ 173 u16 send_sub_cq_idx; 174 175 /* Index of sub-CQ for Receive Queue completions */ 176 u16 recv_sub_cq_idx; 177 178 /* SQ doorbell address, as offset to PCIe DB BAR */ 179 u32 sq_db_offset; 180 181 /* RQ doorbell address, as offset to PCIe DB BAR */ 182 u32 rq_db_offset; 183 184 /* 185 * low latency send queue ring base address as an offset to PCIe 186 * MMIO LLQ_MEM BAR 187 */ 188 u32 llq_descriptors_offset; 189 }; 190 191 struct efa_admin_modify_qp_cmd { 192 /* Common Admin Queue descriptor */ 193 struct efa_admin_aq_common_desc aq_common_desc; 194 195 /* 196 * Mask indicating which fields should be updated see enum 197 * efa_admin_modify_qp_mask_bits 198 */ 199 u32 modify_mask; 200 201 /* QP handle returned by create_qp command */ 202 u32 qp_handle; 203 204 /* QP state */ 205 u32 qp_state; 206 207 /* Override current QP state (before applying the transition) */ 208 u32 cur_qp_state; 209 210 /* QKey */ 211 u32 qkey; 212 213 /* SQ PSN */ 214 u32 sq_psn; 215 216 /* Enable async notification when SQ is drained */ 217 u8 sq_drained_async_notify; 218 219 /* MBZ */ 220 u8 reserved1; 221 222 /* MBZ */ 223 u16 reserved2; 224 }; 225 226 struct efa_admin_modify_qp_resp { 227 /* Common Admin Queue completion descriptor */ 228 struct efa_admin_acq_common_desc acq_common_desc; 229 }; 230 231 struct efa_admin_query_qp_cmd { 232 /* Common Admin Queue descriptor */ 233 struct efa_admin_aq_common_desc aq_common_desc; 234 235 /* QP handle returned by create_qp command */ 236 u32 qp_handle; 237 }; 238 239 struct efa_admin_query_qp_resp { 240 /* Common Admin Queue completion descriptor */ 241 struct efa_admin_acq_common_desc acq_common_desc; 242 243 /* QP state */ 244 u32 qp_state; 245 246 /* QKey */ 247 u32 qkey; 248 249 /* SQ PSN */ 250 u32 sq_psn; 251 252 /* Indicates that draining is in progress */ 253 u8 sq_draining; 254 255 /* MBZ */ 256 u8 reserved1; 257 258 /* MBZ */ 259 u16 reserved2; 260 }; 261 262 struct efa_admin_destroy_qp_cmd { 263 /* Common Admin Queue descriptor */ 264 struct efa_admin_aq_common_desc aq_common_desc; 265 266 /* QP handle returned by create_qp command */ 267 u32 qp_handle; 268 }; 269 270 struct efa_admin_destroy_qp_resp { 271 /* Common Admin Queue completion descriptor */ 272 struct efa_admin_acq_common_desc acq_common_desc; 273 }; 274 275 /* 276 * Create Address Handle command parameters. Must not be called more than 277 * once for the same destination 278 */ 279 struct efa_admin_create_ah_cmd { 280 /* Common Admin Queue descriptor */ 281 struct efa_admin_aq_common_desc aq_common_desc; 282 283 /* Destination address in network byte order */ 284 u8 dest_addr[16]; 285 286 /* PD number */ 287 u16 pd; 288 289 u16 reserved; 290 }; 291 292 struct efa_admin_create_ah_resp { 293 /* Common Admin Queue completion descriptor */ 294 struct efa_admin_acq_common_desc acq_common_desc; 295 296 /* Target interface address handle (opaque) */ 297 u16 ah; 298 299 u16 reserved; 300 }; 301 302 struct efa_admin_destroy_ah_cmd { 303 /* Common Admin Queue descriptor */ 304 struct efa_admin_aq_common_desc aq_common_desc; 305 306 /* Target interface address handle (opaque) */ 307 u16 ah; 308 309 /* PD number */ 310 u16 pd; 311 }; 312 313 struct efa_admin_destroy_ah_resp { 314 /* Common Admin Queue completion descriptor */ 315 struct efa_admin_acq_common_desc acq_common_desc; 316 }; 317 318 /* 319 * Registration of MemoryRegion, required for QP working with Virtual 320 * Addresses. In standard verbs semantics, region length is limited to 2GB 321 * space, but EFA offers larger MR support for large memory space, to ease 322 * on users working with very large datasets (i.e. full GPU memory mapping). 323 */ 324 struct efa_admin_reg_mr_cmd { 325 /* Common Admin Queue descriptor */ 326 struct efa_admin_aq_common_desc aq_common_desc; 327 328 /* Protection Domain */ 329 u16 pd; 330 331 /* MBZ */ 332 u16 reserved16_w1; 333 334 /* Physical Buffer List, each element is page-aligned. */ 335 union { 336 /* 337 * Inline array of guest-physical page addresses of user 338 * memory pages (optimization for short region 339 * registrations) 340 */ 341 u64 inline_pbl_array[4]; 342 343 /* points to PBL (direct or indirect, chained if needed) */ 344 struct efa_admin_ctrl_buff_info pbl; 345 } pbl; 346 347 /* Memory region length, in bytes. */ 348 u64 mr_length; 349 350 /* 351 * flags and page size 352 * 4:0 : phys_page_size_shift - page size is (1 << 353 * phys_page_size_shift). Page size is used for 354 * building the Virtual to Physical address mapping 355 * 6:5 : reserved - MBZ 356 * 7 : mem_addr_phy_mode_en - Enable bit for physical 357 * memory registration (no translation), can be used 358 * only by privileged clients. If set, PBL must 359 * contain a single entry. 360 */ 361 u8 flags; 362 363 /* 364 * permissions 365 * 0 : local_write_enable - Local write permissions: 366 * must be set for RQ buffers and buffers posted for 367 * RDMA Read requests 368 * 1 : reserved1 - MBZ 369 * 2 : remote_read_enable - Remote read permissions: 370 * must be set to enable RDMA read from the region 371 * 7:3 : reserved2 - MBZ 372 */ 373 u8 permissions; 374 375 u16 reserved16_w5; 376 377 /* number of pages in PBL (redundant, could be calculated) */ 378 u32 page_num; 379 380 /* 381 * IO Virtual Address associated with this MR. If 382 * mem_addr_phy_mode_en is set, contains the physical address of 383 * the region. 384 */ 385 u64 iova; 386 }; 387 388 struct efa_admin_reg_mr_resp { 389 /* Common Admin Queue completion descriptor */ 390 struct efa_admin_acq_common_desc acq_common_desc; 391 392 /* 393 * L_Key, to be used in conjunction with local buffer references in 394 * SQ and RQ WQE, or with virtual RQ/CQ rings 395 */ 396 u32 l_key; 397 398 /* 399 * R_Key, to be used in RDMA messages to refer to remotely accessed 400 * memory region 401 */ 402 u32 r_key; 403 }; 404 405 struct efa_admin_dereg_mr_cmd { 406 /* Common Admin Queue descriptor */ 407 struct efa_admin_aq_common_desc aq_common_desc; 408 409 /* L_Key, memory region's l_key */ 410 u32 l_key; 411 }; 412 413 struct efa_admin_dereg_mr_resp { 414 /* Common Admin Queue completion descriptor */ 415 struct efa_admin_acq_common_desc acq_common_desc; 416 }; 417 418 struct efa_admin_create_cq_cmd { 419 struct efa_admin_aq_common_desc aq_common_desc; 420 421 /* 422 * 4:0 : reserved5 423 * 5 : interrupt_mode_enabled - if set, cq operates 424 * in interrupt mode (i.e. CQ events and MSI-X are 425 * generated), otherwise - polling 426 * 6 : virt - If set, ring base address is virtual 427 * (IOVA returned by MR registration) 428 * 7 : reserved6 429 */ 430 u8 cq_caps_1; 431 432 /* 433 * 4:0 : cq_entry_size_words - size of CQ entry in 434 * 32-bit words, valid values: 4, 8. 435 * 7:5 : reserved7 436 */ 437 u8 cq_caps_2; 438 439 /* completion queue depth in # of entries. must be power of 2 */ 440 u16 cq_depth; 441 442 /* msix vector assigned to this cq */ 443 u32 msix_vector_idx; 444 445 /* 446 * CQ ring base address, virtual or physical depending on 'virt' 447 * flag 448 */ 449 struct efa_common_mem_addr cq_ba; 450 451 /* 452 * Memory registration key for the ring, used only when base 453 * address is virtual 454 */ 455 u32 l_key; 456 457 /* 458 * number of sub cqs - must be equal to sub_cqs_per_cq of queue 459 * attributes. 460 */ 461 u16 num_sub_cqs; 462 463 /* UAR number */ 464 u16 uar; 465 }; 466 467 struct efa_admin_create_cq_resp { 468 struct efa_admin_acq_common_desc acq_common_desc; 469 470 u16 cq_idx; 471 472 /* actual cq depth in number of entries */ 473 u16 cq_actual_depth; 474 }; 475 476 struct efa_admin_destroy_cq_cmd { 477 struct efa_admin_aq_common_desc aq_common_desc; 478 479 u16 cq_idx; 480 481 u16 reserved1; 482 }; 483 484 struct efa_admin_destroy_cq_resp { 485 struct efa_admin_acq_common_desc acq_common_desc; 486 }; 487 488 /* 489 * EFA AQ Get Statistics command. Extended statistics are placed in control 490 * buffer pointed by AQ entry 491 */ 492 struct efa_admin_aq_get_stats_cmd { 493 struct efa_admin_aq_common_desc aq_common_descriptor; 494 495 union { 496 /* command specific inline data */ 497 u32 inline_data_w1[3]; 498 499 struct efa_admin_ctrl_buff_info control_buffer; 500 } u; 501 502 /* stats type as defined in enum efa_admin_get_stats_type */ 503 u8 type; 504 505 /* stats scope defined in enum efa_admin_get_stats_scope */ 506 u8 scope; 507 508 u16 scope_modifier; 509 }; 510 511 struct efa_admin_basic_stats { 512 u64 tx_bytes; 513 514 u64 tx_pkts; 515 516 u64 rx_bytes; 517 518 u64 rx_pkts; 519 520 u64 rx_drops; 521 }; 522 523 struct efa_admin_acq_get_stats_resp { 524 struct efa_admin_acq_common_desc acq_common_desc; 525 526 struct efa_admin_basic_stats basic_stats; 527 }; 528 529 struct efa_admin_get_set_feature_common_desc { 530 /* 531 * 1:0 : select - 0x1 - current value; 0x3 - default 532 * value 533 * 7:3 : reserved3 534 */ 535 u8 flags; 536 537 /* as appears in efa_admin_aq_feature_id */ 538 u8 feature_id; 539 540 /* MBZ */ 541 u16 reserved16; 542 }; 543 544 struct efa_admin_feature_device_attr_desc { 545 /* Bitmap of efa_admin_aq_feature_id */ 546 u64 supported_features; 547 548 /* Bitmap of supported page sizes in MR registrations */ 549 u64 page_size_cap; 550 551 u32 fw_version; 552 553 u32 admin_api_version; 554 555 u32 device_version; 556 557 /* Bar used for SQ and RQ doorbells */ 558 u16 db_bar; 559 560 /* Indicates how many bits are used physical address access */ 561 u8 phys_addr_width; 562 563 /* Indicates how many bits are used virtual address access */ 564 u8 virt_addr_width; 565 566 /* 567 * 0 : rdma_read - If set, RDMA Read is supported on 568 * TX queues 569 * 31:1 : reserved - MBZ 570 */ 571 u32 device_caps; 572 573 /* Max RDMA transfer size in bytes */ 574 u32 max_rdma_size; 575 }; 576 577 struct efa_admin_feature_queue_attr_desc { 578 /* The maximum number of queue pairs supported */ 579 u32 max_qp; 580 581 u32 max_sq_depth; 582 583 /* max send wr used in inline-buf */ 584 u32 inline_buf_size; 585 586 u32 max_rq_depth; 587 588 /* The maximum number of completion queues supported per VF */ 589 u32 max_cq; 590 591 u32 max_cq_depth; 592 593 /* Number of sub-CQs to be created for each CQ */ 594 u16 sub_cqs_per_cq; 595 596 u16 reserved; 597 598 /* 599 * Maximum number of SGEs (buffs) allowed for a single send work 600 * queue element (WQE) 601 */ 602 u16 max_wr_send_sges; 603 604 /* Maximum number of SGEs allowed for a single recv WQE */ 605 u16 max_wr_recv_sges; 606 607 /* The maximum number of memory regions supported */ 608 u32 max_mr; 609 610 /* The maximum number of pages can be registered */ 611 u32 max_mr_pages; 612 613 /* The maximum number of protection domains supported */ 614 u32 max_pd; 615 616 /* The maximum number of address handles supported */ 617 u32 max_ah; 618 619 /* The maximum size of LLQ in bytes */ 620 u32 max_llq_size; 621 622 /* Maximum number of SGEs for a single RDMA read WQE */ 623 u16 max_wr_rdma_sges; 624 }; 625 626 struct efa_admin_feature_aenq_desc { 627 /* bitmask for AENQ groups the device can report */ 628 u32 supported_groups; 629 630 /* bitmask for AENQ groups to report */ 631 u32 enabled_groups; 632 }; 633 634 struct efa_admin_feature_network_attr_desc { 635 /* Raw address data in network byte order */ 636 u8 addr[16]; 637 638 /* max packet payload size in bytes */ 639 u32 mtu; 640 }; 641 642 /* 643 * When hint value is 0, hints capabilities are not supported or driver 644 * should use its own predefined value 645 */ 646 struct efa_admin_hw_hints { 647 /* value in ms */ 648 u16 mmio_read_timeout; 649 650 /* value in ms */ 651 u16 driver_watchdog_timeout; 652 653 /* value in ms */ 654 u16 admin_completion_timeout; 655 656 /* poll interval in ms */ 657 u16 poll_interval; 658 }; 659 660 struct efa_admin_get_feature_cmd { 661 struct efa_admin_aq_common_desc aq_common_descriptor; 662 663 struct efa_admin_ctrl_buff_info control_buffer; 664 665 struct efa_admin_get_set_feature_common_desc feature_common; 666 667 u32 raw[11]; 668 }; 669 670 struct efa_admin_get_feature_resp { 671 struct efa_admin_acq_common_desc acq_common_desc; 672 673 union { 674 u32 raw[14]; 675 676 struct efa_admin_feature_device_attr_desc device_attr; 677 678 struct efa_admin_feature_aenq_desc aenq; 679 680 struct efa_admin_feature_network_attr_desc network_attr; 681 682 struct efa_admin_feature_queue_attr_desc queue_attr; 683 684 struct efa_admin_hw_hints hw_hints; 685 } u; 686 }; 687 688 struct efa_admin_set_feature_cmd { 689 struct efa_admin_aq_common_desc aq_common_descriptor; 690 691 struct efa_admin_ctrl_buff_info control_buffer; 692 693 struct efa_admin_get_set_feature_common_desc feature_common; 694 695 union { 696 u32 raw[11]; 697 698 /* AENQ configuration */ 699 struct efa_admin_feature_aenq_desc aenq; 700 } u; 701 }; 702 703 struct efa_admin_set_feature_resp { 704 struct efa_admin_acq_common_desc acq_common_desc; 705 706 union { 707 u32 raw[14]; 708 } u; 709 }; 710 711 struct efa_admin_alloc_pd_cmd { 712 struct efa_admin_aq_common_desc aq_common_descriptor; 713 }; 714 715 struct efa_admin_alloc_pd_resp { 716 struct efa_admin_acq_common_desc acq_common_desc; 717 718 /* PD number */ 719 u16 pd; 720 721 /* MBZ */ 722 u16 reserved; 723 }; 724 725 struct efa_admin_dealloc_pd_cmd { 726 struct efa_admin_aq_common_desc aq_common_descriptor; 727 728 /* PD number */ 729 u16 pd; 730 731 /* MBZ */ 732 u16 reserved; 733 }; 734 735 struct efa_admin_dealloc_pd_resp { 736 struct efa_admin_acq_common_desc acq_common_desc; 737 }; 738 739 struct efa_admin_alloc_uar_cmd { 740 struct efa_admin_aq_common_desc aq_common_descriptor; 741 }; 742 743 struct efa_admin_alloc_uar_resp { 744 struct efa_admin_acq_common_desc acq_common_desc; 745 746 /* UAR number */ 747 u16 uar; 748 749 /* MBZ */ 750 u16 reserved; 751 }; 752 753 struct efa_admin_dealloc_uar_cmd { 754 struct efa_admin_aq_common_desc aq_common_descriptor; 755 756 /* UAR number */ 757 u16 uar; 758 759 /* MBZ */ 760 u16 reserved; 761 }; 762 763 struct efa_admin_dealloc_uar_resp { 764 struct efa_admin_acq_common_desc acq_common_desc; 765 }; 766 767 /* asynchronous event notification groups */ 768 enum efa_admin_aenq_group { 769 EFA_ADMIN_FATAL_ERROR = 1, 770 EFA_ADMIN_WARNING = 2, 771 EFA_ADMIN_NOTIFICATION = 3, 772 EFA_ADMIN_KEEP_ALIVE = 4, 773 EFA_ADMIN_AENQ_GROUPS_NUM = 5, 774 }; 775 776 enum efa_admin_aenq_notification_syndrom { 777 EFA_ADMIN_SUSPEND = 0, 778 EFA_ADMIN_RESUME = 1, 779 EFA_ADMIN_UPDATE_HINTS = 2, 780 }; 781 782 struct efa_admin_mmio_req_read_less_resp { 783 u16 req_id; 784 785 u16 reg_off; 786 787 /* value is valid when poll is cleared */ 788 u32 reg_val; 789 }; 790 791 /* create_qp_cmd */ 792 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0) 793 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_SHIFT 1 794 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1) 795 796 /* reg_mr_cmd */ 797 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0) 798 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_SHIFT 7 799 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7) 800 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0) 801 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_SHIFT 2 802 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2) 803 804 /* create_cq_cmd */ 805 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 806 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 807 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_SHIFT 6 808 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6) 809 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 810 811 /* get_set_feature_common_desc */ 812 #define EFA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 813 814 /* feature_device_attr_desc */ 815 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0) 816 817 #endif /* _EFA_ADMIN_CMDS_H_ */ 818