1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_CMDS_H_ 7 #define _EFA_ADMIN_CMDS_H_ 8 9 #define EFA_ADMIN_API_VERSION_MAJOR 0 10 #define EFA_ADMIN_API_VERSION_MINOR 1 11 12 /* EFA admin queue opcodes */ 13 enum efa_admin_aq_opcode { 14 EFA_ADMIN_CREATE_QP = 1, 15 EFA_ADMIN_MODIFY_QP = 2, 16 EFA_ADMIN_QUERY_QP = 3, 17 EFA_ADMIN_DESTROY_QP = 4, 18 EFA_ADMIN_CREATE_AH = 5, 19 EFA_ADMIN_DESTROY_AH = 6, 20 EFA_ADMIN_REG_MR = 7, 21 EFA_ADMIN_DEREG_MR = 8, 22 EFA_ADMIN_CREATE_CQ = 9, 23 EFA_ADMIN_DESTROY_CQ = 10, 24 EFA_ADMIN_GET_FEATURE = 11, 25 EFA_ADMIN_SET_FEATURE = 12, 26 EFA_ADMIN_GET_STATS = 13, 27 EFA_ADMIN_ALLOC_PD = 14, 28 EFA_ADMIN_DEALLOC_PD = 15, 29 EFA_ADMIN_ALLOC_UAR = 16, 30 EFA_ADMIN_DEALLOC_UAR = 17, 31 EFA_ADMIN_CREATE_EQ = 18, 32 EFA_ADMIN_DESTROY_EQ = 19, 33 EFA_ADMIN_MAX_OPCODE = 19, 34 }; 35 36 enum efa_admin_aq_feature_id { 37 EFA_ADMIN_DEVICE_ATTR = 1, 38 EFA_ADMIN_AENQ_CONFIG = 2, 39 EFA_ADMIN_NETWORK_ATTR = 3, 40 EFA_ADMIN_QUEUE_ATTR = 4, 41 EFA_ADMIN_HW_HINTS = 5, 42 EFA_ADMIN_HOST_INFO = 6, 43 EFA_ADMIN_EVENT_QUEUE_ATTR = 7, 44 }; 45 46 /* QP transport type */ 47 enum efa_admin_qp_type { 48 /* Unreliable Datagram */ 49 EFA_ADMIN_QP_TYPE_UD = 1, 50 /* Scalable Reliable Datagram */ 51 EFA_ADMIN_QP_TYPE_SRD = 2, 52 }; 53 54 /* QP state */ 55 enum efa_admin_qp_state { 56 EFA_ADMIN_QP_STATE_RESET = 0, 57 EFA_ADMIN_QP_STATE_INIT = 1, 58 EFA_ADMIN_QP_STATE_RTR = 2, 59 EFA_ADMIN_QP_STATE_RTS = 3, 60 EFA_ADMIN_QP_STATE_SQD = 4, 61 EFA_ADMIN_QP_STATE_SQE = 5, 62 EFA_ADMIN_QP_STATE_ERR = 6, 63 }; 64 65 enum efa_admin_get_stats_type { 66 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0, 67 EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1, 68 EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2, 69 }; 70 71 enum efa_admin_get_stats_scope { 72 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0, 73 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1, 74 }; 75 76 /* 77 * QP allocation sizes, converted by fabric QueuePair (QP) create command 78 * from QP capabilities. 79 */ 80 struct efa_admin_qp_alloc_size { 81 /* Send descriptor ring size in bytes */ 82 u32 send_queue_ring_size; 83 84 /* Max number of WQEs that can be outstanding on send queue. */ 85 u32 send_queue_depth; 86 87 /* 88 * Recv descriptor ring size in bytes, sufficient for user-provided 89 * number of WQEs 90 */ 91 u32 recv_queue_ring_size; 92 93 /* Max number of WQEs that can be outstanding on recv queue */ 94 u32 recv_queue_depth; 95 }; 96 97 struct efa_admin_create_qp_cmd { 98 /* Common Admin Queue descriptor */ 99 struct efa_admin_aq_common_desc aq_common_desc; 100 101 /* Protection Domain associated with this QP */ 102 u16 pd; 103 104 /* QP type */ 105 u8 qp_type; 106 107 /* 108 * 0 : sq_virt - If set, SQ ring base address is 109 * virtual (IOVA returned by MR registration) 110 * 1 : rq_virt - If set, RQ ring base address is 111 * virtual (IOVA returned by MR registration) 112 * 7:2 : reserved - MBZ 113 */ 114 u8 flags; 115 116 /* 117 * Send queue (SQ) ring base physical address. This field is not 118 * used if this is a Low Latency Queue(LLQ). 119 */ 120 u64 sq_base_addr; 121 122 /* Receive queue (RQ) ring base address. */ 123 u64 rq_base_addr; 124 125 /* Index of CQ to be associated with Send Queue completions */ 126 u32 send_cq_idx; 127 128 /* Index of CQ to be associated with Recv Queue completions */ 129 u32 recv_cq_idx; 130 131 /* 132 * Memory registration key for the SQ ring, used only when not in 133 * LLQ mode and base address is virtual 134 */ 135 u32 sq_l_key; 136 137 /* 138 * Memory registration key for the RQ ring, used only when base 139 * address is virtual 140 */ 141 u32 rq_l_key; 142 143 /* Requested QP allocation sizes */ 144 struct efa_admin_qp_alloc_size qp_alloc_size; 145 146 /* UAR number */ 147 u16 uar; 148 149 /* MBZ */ 150 u16 reserved; 151 152 /* MBZ */ 153 u32 reserved2; 154 }; 155 156 struct efa_admin_create_qp_resp { 157 /* Common Admin Queue completion descriptor */ 158 struct efa_admin_acq_common_desc acq_common_desc; 159 160 /* 161 * Opaque handle to be used for consequent admin operations on the 162 * QP 163 */ 164 u32 qp_handle; 165 166 /* 167 * QP number in the given EFA virtual device. Least-significant bits (as 168 * needed according to max_qp) carry unique QP ID 169 */ 170 u16 qp_num; 171 172 /* MBZ */ 173 u16 reserved; 174 175 /* Index of sub-CQ for Send Queue completions */ 176 u16 send_sub_cq_idx; 177 178 /* Index of sub-CQ for Receive Queue completions */ 179 u16 recv_sub_cq_idx; 180 181 /* SQ doorbell address, as offset to PCIe DB BAR */ 182 u32 sq_db_offset; 183 184 /* RQ doorbell address, as offset to PCIe DB BAR */ 185 u32 rq_db_offset; 186 187 /* 188 * low latency send queue ring base address as an offset to PCIe 189 * MMIO LLQ_MEM BAR 190 */ 191 u32 llq_descriptors_offset; 192 }; 193 194 struct efa_admin_modify_qp_cmd { 195 /* Common Admin Queue descriptor */ 196 struct efa_admin_aq_common_desc aq_common_desc; 197 198 /* 199 * Mask indicating which fields should be updated 200 * 0 : qp_state 201 * 1 : cur_qp_state 202 * 2 : qkey 203 * 3 : sq_psn 204 * 4 : sq_drained_async_notify 205 * 5 : rnr_retry 206 * 31:6 : reserved 207 */ 208 u32 modify_mask; 209 210 /* QP handle returned by create_qp command */ 211 u32 qp_handle; 212 213 /* QP state */ 214 u32 qp_state; 215 216 /* Override current QP state (before applying the transition) */ 217 u32 cur_qp_state; 218 219 /* QKey */ 220 u32 qkey; 221 222 /* SQ PSN */ 223 u32 sq_psn; 224 225 /* Enable async notification when SQ is drained */ 226 u8 sq_drained_async_notify; 227 228 /* Number of RNR retries (valid only for SRD QPs) */ 229 u8 rnr_retry; 230 231 /* MBZ */ 232 u16 reserved2; 233 }; 234 235 struct efa_admin_modify_qp_resp { 236 /* Common Admin Queue completion descriptor */ 237 struct efa_admin_acq_common_desc acq_common_desc; 238 }; 239 240 struct efa_admin_query_qp_cmd { 241 /* Common Admin Queue descriptor */ 242 struct efa_admin_aq_common_desc aq_common_desc; 243 244 /* QP handle returned by create_qp command */ 245 u32 qp_handle; 246 }; 247 248 struct efa_admin_query_qp_resp { 249 /* Common Admin Queue completion descriptor */ 250 struct efa_admin_acq_common_desc acq_common_desc; 251 252 /* QP state */ 253 u32 qp_state; 254 255 /* QKey */ 256 u32 qkey; 257 258 /* SQ PSN */ 259 u32 sq_psn; 260 261 /* Indicates that draining is in progress */ 262 u8 sq_draining; 263 264 /* Number of RNR retries (valid only for SRD QPs) */ 265 u8 rnr_retry; 266 267 /* MBZ */ 268 u16 reserved2; 269 }; 270 271 struct efa_admin_destroy_qp_cmd { 272 /* Common Admin Queue descriptor */ 273 struct efa_admin_aq_common_desc aq_common_desc; 274 275 /* QP handle returned by create_qp command */ 276 u32 qp_handle; 277 }; 278 279 struct efa_admin_destroy_qp_resp { 280 /* Common Admin Queue completion descriptor */ 281 struct efa_admin_acq_common_desc acq_common_desc; 282 }; 283 284 /* 285 * Create Address Handle command parameters. Must not be called more than 286 * once for the same destination 287 */ 288 struct efa_admin_create_ah_cmd { 289 /* Common Admin Queue descriptor */ 290 struct efa_admin_aq_common_desc aq_common_desc; 291 292 /* Destination address in network byte order */ 293 u8 dest_addr[16]; 294 295 /* PD number */ 296 u16 pd; 297 298 /* MBZ */ 299 u16 reserved; 300 }; 301 302 struct efa_admin_create_ah_resp { 303 /* Common Admin Queue completion descriptor */ 304 struct efa_admin_acq_common_desc acq_common_desc; 305 306 /* Target interface address handle (opaque) */ 307 u16 ah; 308 309 /* MBZ */ 310 u16 reserved; 311 }; 312 313 struct efa_admin_destroy_ah_cmd { 314 /* Common Admin Queue descriptor */ 315 struct efa_admin_aq_common_desc aq_common_desc; 316 317 /* Target interface address handle (opaque) */ 318 u16 ah; 319 320 /* PD number */ 321 u16 pd; 322 }; 323 324 struct efa_admin_destroy_ah_resp { 325 /* Common Admin Queue completion descriptor */ 326 struct efa_admin_acq_common_desc acq_common_desc; 327 }; 328 329 /* 330 * Registration of MemoryRegion, required for QP working with Virtual 331 * Addresses. In standard verbs semantics, region length is limited to 2GB 332 * space, but EFA offers larger MR support for large memory space, to ease 333 * on users working with very large datasets (i.e. full GPU memory mapping). 334 */ 335 struct efa_admin_reg_mr_cmd { 336 /* Common Admin Queue descriptor */ 337 struct efa_admin_aq_common_desc aq_common_desc; 338 339 /* Protection Domain */ 340 u16 pd; 341 342 /* MBZ */ 343 u16 reserved16_w1; 344 345 /* Physical Buffer List, each element is page-aligned. */ 346 union { 347 /* 348 * Inline array of guest-physical page addresses of user 349 * memory pages (optimization for short region 350 * registrations) 351 */ 352 u64 inline_pbl_array[4]; 353 354 /* points to PBL (direct or indirect, chained if needed) */ 355 struct efa_admin_ctrl_buff_info pbl; 356 } pbl; 357 358 /* Memory region length, in bytes. */ 359 u64 mr_length; 360 361 /* 362 * flags and page size 363 * 4:0 : phys_page_size_shift - page size is (1 << 364 * phys_page_size_shift). Page size is used for 365 * building the Virtual to Physical address mapping 366 * 6:5 : reserved - MBZ 367 * 7 : mem_addr_phy_mode_en - Enable bit for physical 368 * memory registration (no translation), can be used 369 * only by privileged clients. If set, PBL must 370 * contain a single entry. 371 */ 372 u8 flags; 373 374 /* 375 * permissions 376 * 0 : local_write_enable - Local write permissions: 377 * must be set for RQ buffers and buffers posted for 378 * RDMA Read requests 379 * 1 : remote_write_enable - Remote write 380 * permissions: must be set to enable RDMA write to 381 * the region 382 * 2 : remote_read_enable - Remote read permissions: 383 * must be set to enable RDMA read from the region 384 * 7:3 : reserved2 - MBZ 385 */ 386 u8 permissions; 387 388 /* MBZ */ 389 u16 reserved16_w5; 390 391 /* number of pages in PBL (redundant, could be calculated) */ 392 u32 page_num; 393 394 /* 395 * IO Virtual Address associated with this MR. If 396 * mem_addr_phy_mode_en is set, contains the physical address of 397 * the region. 398 */ 399 u64 iova; 400 }; 401 402 struct efa_admin_reg_mr_resp { 403 /* Common Admin Queue completion descriptor */ 404 struct efa_admin_acq_common_desc acq_common_desc; 405 406 /* 407 * L_Key, to be used in conjunction with local buffer references in 408 * SQ and RQ WQE, or with virtual RQ/CQ rings 409 */ 410 u32 l_key; 411 412 /* 413 * R_Key, to be used in RDMA messages to refer to remotely accessed 414 * memory region 415 */ 416 u32 r_key; 417 }; 418 419 struct efa_admin_dereg_mr_cmd { 420 /* Common Admin Queue descriptor */ 421 struct efa_admin_aq_common_desc aq_common_desc; 422 423 /* L_Key, memory region's l_key */ 424 u32 l_key; 425 }; 426 427 struct efa_admin_dereg_mr_resp { 428 /* Common Admin Queue completion descriptor */ 429 struct efa_admin_acq_common_desc acq_common_desc; 430 }; 431 432 struct efa_admin_create_cq_cmd { 433 struct efa_admin_aq_common_desc aq_common_desc; 434 435 /* 436 * 4:0 : reserved5 - MBZ 437 * 5 : interrupt_mode_enabled - if set, cq operates 438 * in interrupt mode (i.e. CQ events and EQ elements 439 * are generated), otherwise - polling 440 * 6 : virt - If set, ring base address is virtual 441 * (IOVA returned by MR registration) 442 * 7 : reserved6 - MBZ 443 */ 444 u8 cq_caps_1; 445 446 /* 447 * 4:0 : cq_entry_size_words - size of CQ entry in 448 * 32-bit words, valid values: 4, 8. 449 * 5 : set_src_addr - If set, source address will be 450 * filled on RX completions from unknown senders. 451 * Requires 8 words CQ entry size. 452 * 7:6 : reserved7 - MBZ 453 */ 454 u8 cq_caps_2; 455 456 /* completion queue depth in # of entries. must be power of 2 */ 457 u16 cq_depth; 458 459 /* EQ number assigned to this cq */ 460 u16 eqn; 461 462 /* MBZ */ 463 u16 reserved; 464 465 /* 466 * CQ ring base address, virtual or physical depending on 'virt' 467 * flag 468 */ 469 struct efa_common_mem_addr cq_ba; 470 471 /* 472 * Memory registration key for the ring, used only when base 473 * address is virtual 474 */ 475 u32 l_key; 476 477 /* 478 * number of sub cqs - must be equal to sub_cqs_per_cq of queue 479 * attributes. 480 */ 481 u16 num_sub_cqs; 482 483 /* UAR number */ 484 u16 uar; 485 }; 486 487 struct efa_admin_create_cq_resp { 488 struct efa_admin_acq_common_desc acq_common_desc; 489 490 u16 cq_idx; 491 492 /* actual cq depth in number of entries */ 493 u16 cq_actual_depth; 494 495 /* CQ doorbell address, as offset to PCIe DB BAR */ 496 u32 db_offset; 497 498 /* 499 * 0 : db_valid - If set, doorbell offset is valid. 500 * Always set when interrupts are requested. 501 */ 502 u32 flags; 503 }; 504 505 struct efa_admin_destroy_cq_cmd { 506 struct efa_admin_aq_common_desc aq_common_desc; 507 508 u16 cq_idx; 509 510 /* MBZ */ 511 u16 reserved1; 512 }; 513 514 struct efa_admin_destroy_cq_resp { 515 struct efa_admin_acq_common_desc acq_common_desc; 516 }; 517 518 /* 519 * EFA AQ Get Statistics command. Extended statistics are placed in control 520 * buffer pointed by AQ entry 521 */ 522 struct efa_admin_aq_get_stats_cmd { 523 struct efa_admin_aq_common_desc aq_common_descriptor; 524 525 union { 526 /* command specific inline data */ 527 u32 inline_data_w1[3]; 528 529 struct efa_admin_ctrl_buff_info control_buffer; 530 } u; 531 532 /* stats type as defined in enum efa_admin_get_stats_type */ 533 u8 type; 534 535 /* stats scope defined in enum efa_admin_get_stats_scope */ 536 u8 scope; 537 538 u16 scope_modifier; 539 }; 540 541 struct efa_admin_basic_stats { 542 u64 tx_bytes; 543 544 u64 tx_pkts; 545 546 u64 rx_bytes; 547 548 u64 rx_pkts; 549 550 u64 rx_drops; 551 }; 552 553 struct efa_admin_messages_stats { 554 u64 send_bytes; 555 556 u64 send_wrs; 557 558 u64 recv_bytes; 559 560 u64 recv_wrs; 561 }; 562 563 struct efa_admin_rdma_read_stats { 564 u64 read_wrs; 565 566 u64 read_bytes; 567 568 u64 read_wr_err; 569 570 u64 read_resp_bytes; 571 }; 572 573 struct efa_admin_acq_get_stats_resp { 574 struct efa_admin_acq_common_desc acq_common_desc; 575 576 union { 577 struct efa_admin_basic_stats basic_stats; 578 579 struct efa_admin_messages_stats messages_stats; 580 581 struct efa_admin_rdma_read_stats rdma_read_stats; 582 } u; 583 }; 584 585 struct efa_admin_get_set_feature_common_desc { 586 /* MBZ */ 587 u8 reserved0; 588 589 /* as appears in efa_admin_aq_feature_id */ 590 u8 feature_id; 591 592 /* MBZ */ 593 u16 reserved16; 594 }; 595 596 struct efa_admin_feature_device_attr_desc { 597 /* Bitmap of efa_admin_aq_feature_id */ 598 u64 supported_features; 599 600 /* Bitmap of supported page sizes in MR registrations */ 601 u64 page_size_cap; 602 603 u32 fw_version; 604 605 u32 admin_api_version; 606 607 u32 device_version; 608 609 /* Bar used for SQ and RQ doorbells */ 610 u16 db_bar; 611 612 /* Indicates how many bits are used on physical address access */ 613 u8 phys_addr_width; 614 615 /* Indicates how many bits are used on virtual address access */ 616 u8 virt_addr_width; 617 618 /* 619 * 0 : rdma_read - If set, RDMA Read is supported on 620 * TX queues 621 * 1 : rnr_retry - If set, RNR retry is supported on 622 * modify QP command 623 * 2 : data_polling_128 - If set, 128 bytes data 624 * polling is supported 625 * 3 : rdma_write - If set, RDMA Write is supported 626 * on TX queues 627 * 31:4 : reserved - MBZ 628 */ 629 u32 device_caps; 630 631 /* Max RDMA transfer size in bytes */ 632 u32 max_rdma_size; 633 }; 634 635 struct efa_admin_feature_queue_attr_desc { 636 /* The maximum number of queue pairs supported */ 637 u32 max_qp; 638 639 /* Maximum number of WQEs per Send Queue */ 640 u32 max_sq_depth; 641 642 /* Maximum size of data that can be sent inline in a Send WQE */ 643 u32 inline_buf_size; 644 645 /* Maximum number of buffer descriptors per Recv Queue */ 646 u32 max_rq_depth; 647 648 /* The maximum number of completion queues supported per VF */ 649 u32 max_cq; 650 651 /* Maximum number of CQEs per Completion Queue */ 652 u32 max_cq_depth; 653 654 /* Number of sub-CQs to be created for each CQ */ 655 u16 sub_cqs_per_cq; 656 657 /* Minimum number of WQEs per SQ */ 658 u16 min_sq_depth; 659 660 /* Maximum number of SGEs (buffers) allowed for a single send WQE */ 661 u16 max_wr_send_sges; 662 663 /* Maximum number of SGEs allowed for a single recv WQE */ 664 u16 max_wr_recv_sges; 665 666 /* The maximum number of memory regions supported */ 667 u32 max_mr; 668 669 /* The maximum number of pages can be registered */ 670 u32 max_mr_pages; 671 672 /* The maximum number of protection domains supported */ 673 u32 max_pd; 674 675 /* The maximum number of address handles supported */ 676 u32 max_ah; 677 678 /* The maximum size of LLQ in bytes */ 679 u32 max_llq_size; 680 681 /* Maximum number of SGEs for a single RDMA read/write WQE */ 682 u16 max_wr_rdma_sges; 683 684 /* 685 * Maximum number of bytes that can be written to SQ between two 686 * consecutive doorbells (in units of 64B). Driver must ensure that only 687 * complete WQEs are written to queue before issuing a doorbell. 688 * Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can 689 * be written to SQ between two consecutive doorbells. max_tx_batch=11 690 * and WQE size = 128B, means up to 5 WQEs can be written to SQ between 691 * two consecutive doorbells. Zero means unlimited. 692 */ 693 u16 max_tx_batch; 694 }; 695 696 struct efa_admin_event_queue_attr_desc { 697 /* The maximum number of event queues supported */ 698 u32 max_eq; 699 700 /* Maximum number of EQEs per Event Queue */ 701 u32 max_eq_depth; 702 703 /* Supported events bitmask */ 704 u32 event_bitmask; 705 }; 706 707 struct efa_admin_feature_aenq_desc { 708 /* bitmask for AENQ groups the device can report */ 709 u32 supported_groups; 710 711 /* bitmask for AENQ groups to report */ 712 u32 enabled_groups; 713 }; 714 715 struct efa_admin_feature_network_attr_desc { 716 /* Raw address data in network byte order */ 717 u8 addr[16]; 718 719 /* max packet payload size in bytes */ 720 u32 mtu; 721 }; 722 723 /* 724 * When hint value is 0, hints capabilities are not supported or driver 725 * should use its own predefined value 726 */ 727 struct efa_admin_hw_hints { 728 /* value in ms */ 729 u16 mmio_read_timeout; 730 731 /* value in ms */ 732 u16 driver_watchdog_timeout; 733 734 /* value in ms */ 735 u16 admin_completion_timeout; 736 737 /* poll interval in ms */ 738 u16 poll_interval; 739 }; 740 741 struct efa_admin_get_feature_cmd { 742 struct efa_admin_aq_common_desc aq_common_descriptor; 743 744 struct efa_admin_ctrl_buff_info control_buffer; 745 746 struct efa_admin_get_set_feature_common_desc feature_common; 747 748 u32 raw[11]; 749 }; 750 751 struct efa_admin_get_feature_resp { 752 struct efa_admin_acq_common_desc acq_common_desc; 753 754 union { 755 u32 raw[14]; 756 757 struct efa_admin_feature_device_attr_desc device_attr; 758 759 struct efa_admin_feature_aenq_desc aenq; 760 761 struct efa_admin_feature_network_attr_desc network_attr; 762 763 struct efa_admin_feature_queue_attr_desc queue_attr; 764 765 struct efa_admin_event_queue_attr_desc event_queue_attr; 766 767 struct efa_admin_hw_hints hw_hints; 768 } u; 769 }; 770 771 struct efa_admin_set_feature_cmd { 772 struct efa_admin_aq_common_desc aq_common_descriptor; 773 774 struct efa_admin_ctrl_buff_info control_buffer; 775 776 struct efa_admin_get_set_feature_common_desc feature_common; 777 778 union { 779 u32 raw[11]; 780 781 /* AENQ configuration */ 782 struct efa_admin_feature_aenq_desc aenq; 783 } u; 784 }; 785 786 struct efa_admin_set_feature_resp { 787 struct efa_admin_acq_common_desc acq_common_desc; 788 789 union { 790 u32 raw[14]; 791 } u; 792 }; 793 794 struct efa_admin_alloc_pd_cmd { 795 struct efa_admin_aq_common_desc aq_common_descriptor; 796 }; 797 798 struct efa_admin_alloc_pd_resp { 799 struct efa_admin_acq_common_desc acq_common_desc; 800 801 /* PD number */ 802 u16 pd; 803 804 /* MBZ */ 805 u16 reserved; 806 }; 807 808 struct efa_admin_dealloc_pd_cmd { 809 struct efa_admin_aq_common_desc aq_common_descriptor; 810 811 /* PD number */ 812 u16 pd; 813 814 /* MBZ */ 815 u16 reserved; 816 }; 817 818 struct efa_admin_dealloc_pd_resp { 819 struct efa_admin_acq_common_desc acq_common_desc; 820 }; 821 822 struct efa_admin_alloc_uar_cmd { 823 struct efa_admin_aq_common_desc aq_common_descriptor; 824 }; 825 826 struct efa_admin_alloc_uar_resp { 827 struct efa_admin_acq_common_desc acq_common_desc; 828 829 /* UAR number */ 830 u16 uar; 831 832 /* MBZ */ 833 u16 reserved; 834 }; 835 836 struct efa_admin_dealloc_uar_cmd { 837 struct efa_admin_aq_common_desc aq_common_descriptor; 838 839 /* UAR number */ 840 u16 uar; 841 842 /* MBZ */ 843 u16 reserved; 844 }; 845 846 struct efa_admin_dealloc_uar_resp { 847 struct efa_admin_acq_common_desc acq_common_desc; 848 }; 849 850 struct efa_admin_create_eq_cmd { 851 struct efa_admin_aq_common_desc aq_common_descriptor; 852 853 /* Size of the EQ in entries, must be power of 2 */ 854 u16 depth; 855 856 /* MSI-X table entry index */ 857 u8 msix_vec; 858 859 /* 860 * 4:0 : entry_size_words - size of EQ entry in 861 * 32-bit words 862 * 7:5 : reserved - MBZ 863 */ 864 u8 caps; 865 866 /* EQ ring base address */ 867 struct efa_common_mem_addr ba; 868 869 /* 870 * Enabled events on this EQ 871 * 0 : completion_events - Enable completion events 872 * 31:1 : reserved - MBZ 873 */ 874 u32 event_bitmask; 875 876 /* MBZ */ 877 u32 reserved; 878 }; 879 880 struct efa_admin_create_eq_resp { 881 struct efa_admin_acq_common_desc acq_common_desc; 882 883 /* EQ number */ 884 u16 eqn; 885 886 /* MBZ */ 887 u16 reserved; 888 }; 889 890 struct efa_admin_destroy_eq_cmd { 891 struct efa_admin_aq_common_desc aq_common_descriptor; 892 893 /* EQ number */ 894 u16 eqn; 895 896 /* MBZ */ 897 u16 reserved; 898 }; 899 900 struct efa_admin_destroy_eq_resp { 901 struct efa_admin_acq_common_desc acq_common_desc; 902 }; 903 904 /* asynchronous event notification groups */ 905 enum efa_admin_aenq_group { 906 EFA_ADMIN_FATAL_ERROR = 1, 907 EFA_ADMIN_WARNING = 2, 908 EFA_ADMIN_NOTIFICATION = 3, 909 EFA_ADMIN_KEEP_ALIVE = 4, 910 EFA_ADMIN_AENQ_GROUPS_NUM = 5, 911 }; 912 913 struct efa_admin_mmio_req_read_less_resp { 914 u16 req_id; 915 916 u16 reg_off; 917 918 /* value is valid when poll is cleared */ 919 u32 reg_val; 920 }; 921 922 enum efa_admin_os_type { 923 EFA_ADMIN_OS_LINUX = 0, 924 }; 925 926 struct efa_admin_host_info { 927 /* OS distribution string format */ 928 u8 os_dist_str[128]; 929 930 /* Defined in enum efa_admin_os_type */ 931 u32 os_type; 932 933 /* Kernel version string format */ 934 u8 kernel_ver_str[32]; 935 936 /* Kernel version numeric format */ 937 u32 kernel_ver; 938 939 /* 940 * 7:0 : driver_module_type 941 * 15:8 : driver_sub_minor 942 * 23:16 : driver_minor 943 * 31:24 : driver_major 944 */ 945 u32 driver_ver; 946 947 /* 948 * Device's Bus, Device and Function 949 * 2:0 : function 950 * 7:3 : device 951 * 15:8 : bus 952 */ 953 u16 bdf; 954 955 /* 956 * Spec version 957 * 7:0 : spec_minor 958 * 15:8 : spec_major 959 */ 960 u16 spec_ver; 961 962 /* 963 * 0 : intree - Intree driver 964 * 1 : gdr - GPUDirect RDMA supported 965 * 31:2 : reserved2 966 */ 967 u32 flags; 968 }; 969 970 /* create_qp_cmd */ 971 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0) 972 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1) 973 974 /* modify_qp_cmd */ 975 #define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0) 976 #define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1) 977 #define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2) 978 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3) 979 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4) 980 #define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5) 981 982 /* reg_mr_cmd */ 983 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0) 984 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7) 985 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0) 986 #define EFA_ADMIN_REG_MR_CMD_REMOTE_WRITE_ENABLE_MASK BIT(1) 987 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2) 988 989 /* create_cq_cmd */ 990 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 991 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6) 992 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 993 #define EFA_ADMIN_CREATE_CQ_CMD_SET_SRC_ADDR_MASK BIT(5) 994 995 /* create_cq_resp */ 996 #define EFA_ADMIN_CREATE_CQ_RESP_DB_VALID_MASK BIT(0) 997 998 /* feature_device_attr_desc */ 999 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0) 1000 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1) 1001 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_DATA_POLLING_128_MASK BIT(2) 1002 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_WRITE_MASK BIT(3) 1003 1004 /* create_eq_cmd */ 1005 #define EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1006 #define EFA_ADMIN_CREATE_EQ_CMD_VIRT_MASK BIT(6) 1007 #define EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS_MASK BIT(0) 1008 1009 /* host_info */ 1010 #define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0) 1011 #define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8) 1012 #define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16) 1013 #define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24) 1014 #define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1015 #define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1016 #define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1017 #define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0) 1018 #define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8) 1019 #define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0) 1020 #define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1) 1021 1022 #endif /* _EFA_ADMIN_CMDS_H_ */ 1023