1 /*
2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *      - Redistributions in binary form must reproduce the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer in the documentation and/or other materials
20  *        provided with the distribution.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29  * SOFTWARE.
30  */
31 #ifndef _T4FW_RI_API_H_
32 #define _T4FW_RI_API_H_
33 
34 #include "t4fw_api.h"
35 
36 enum fw_ri_wr_opcode {
37 	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
38 	FW_RI_READ_REQ			= 0x1,
39 	FW_RI_READ_RESP			= 0x2,
40 	FW_RI_SEND			= 0x3,
41 	FW_RI_SEND_WITH_INV		= 0x4,
42 	FW_RI_SEND_WITH_SE		= 0x5,
43 	FW_RI_SEND_WITH_SE_INV		= 0x6,
44 	FW_RI_TERMINATE			= 0x7,
45 	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
46 	FW_RI_BIND_MW			= 0x9,
47 	FW_RI_FAST_REGISTER		= 0xa,
48 	FW_RI_LOCAL_INV			= 0xb,
49 	FW_RI_QP_MODIFY			= 0xc,
50 	FW_RI_BYPASS			= 0xd,
51 	FW_RI_RECEIVE			= 0xe,
52 
53 	FW_RI_SGE_EC_CR_RETURN		= 0xf,
54 	FW_RI_WRITE_IMMEDIATE           = FW_RI_RDMA_INIT
55 };
56 
57 enum fw_ri_wr_flags {
58 	FW_RI_COMPLETION_FLAG		= 0x01,
59 	FW_RI_NOTIFICATION_FLAG		= 0x02,
60 	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
61 	FW_RI_READ_FENCE_FLAG		= 0x08,
62 	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
63 	FW_RI_RDMA_READ_INVALIDATE	= 0x20,
64 	FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
65 };
66 
67 enum fw_ri_mpa_attrs {
68 	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
69 	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
70 	FW_RI_MPA_CRC_ENABLE		= 0x04,
71 	FW_RI_MPA_IETF_ENABLE		= 0x08
72 };
73 
74 enum fw_ri_qp_caps {
75 	FW_RI_QP_RDMA_READ_ENABLE	= 0x01,
76 	FW_RI_QP_RDMA_WRITE_ENABLE	= 0x02,
77 	FW_RI_QP_BIND_ENABLE		= 0x04,
78 	FW_RI_QP_FAST_REGISTER_ENABLE	= 0x08,
79 	FW_RI_QP_STAG0_ENABLE		= 0x10
80 };
81 
82 enum fw_ri_addr_type {
83 	FW_RI_ZERO_BASED_TO		= 0x00,
84 	FW_RI_VA_BASED_TO		= 0x01
85 };
86 
87 enum fw_ri_mem_perms {
88 	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
89 	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
90 	FW_RI_MEM_ACCESS_REM		= 0x03,
91 	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
92 	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
93 	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
94 };
95 
96 enum fw_ri_stag_type {
97 	FW_RI_STAG_NSMR			= 0x00,
98 	FW_RI_STAG_SMR			= 0x01,
99 	FW_RI_STAG_MW			= 0x02,
100 	FW_RI_STAG_MW_RELAXED		= 0x03
101 };
102 
103 enum fw_ri_data_op {
104 	FW_RI_DATA_IMMD			= 0x81,
105 	FW_RI_DATA_DSGL			= 0x82,
106 	FW_RI_DATA_ISGL			= 0x83
107 };
108 
109 enum fw_ri_sgl_depth {
110 	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
111 	FW_RI_SGL_DEPTH_MAX_RQ		= 4
112 };
113 
114 struct fw_ri_dsge_pair {
115 	__be32	len[2];
116 	__be64	addr[2];
117 };
118 
119 struct fw_ri_dsgl {
120 	__u8	op;
121 	__u8	r1;
122 	__be16	nsge;
123 	__be32	len0;
124 	__be64	addr0;
125 #ifndef C99_NOT_SUPPORTED
126 	struct fw_ri_dsge_pair sge[0];
127 #endif
128 };
129 
130 struct fw_ri_sge {
131 	__be32 stag;
132 	__be32 len;
133 	__be64 to;
134 };
135 
136 struct fw_ri_isgl {
137 	__u8	op;
138 	__u8	r1;
139 	__be16	nsge;
140 	__be32	r2;
141 #ifndef C99_NOT_SUPPORTED
142 	struct fw_ri_sge sge[0];
143 #endif
144 };
145 
146 struct fw_ri_immd {
147 	__u8	op;
148 	__u8	r1;
149 	__be16	r2;
150 	__be32	immdlen;
151 #ifndef C99_NOT_SUPPORTED
152 	__u8	data[0];
153 #endif
154 };
155 
156 struct fw_ri_tpte {
157 	__be32 valid_to_pdid;
158 	__be32 locread_to_qpid;
159 	__be32 nosnoop_pbladdr;
160 	__be32 len_lo;
161 	__be32 va_hi;
162 	__be32 va_lo_fbo;
163 	__be32 dca_mwbcnt_pstag;
164 	__be32 len_hi;
165 };
166 
167 #define FW_RI_TPTE_VALID_S		31
168 #define FW_RI_TPTE_VALID_M		0x1
169 #define FW_RI_TPTE_VALID_V(x)		((x) << FW_RI_TPTE_VALID_S)
170 #define FW_RI_TPTE_VALID_G(x)		\
171 	(((x) >> FW_RI_TPTE_VALID_S) & FW_RI_TPTE_VALID_M)
172 #define FW_RI_TPTE_VALID_F		FW_RI_TPTE_VALID_V(1U)
173 
174 #define FW_RI_TPTE_STAGKEY_S		23
175 #define FW_RI_TPTE_STAGKEY_M		0xff
176 #define FW_RI_TPTE_STAGKEY_V(x)		((x) << FW_RI_TPTE_STAGKEY_S)
177 #define FW_RI_TPTE_STAGKEY_G(x)		\
178 	(((x) >> FW_RI_TPTE_STAGKEY_S) & FW_RI_TPTE_STAGKEY_M)
179 
180 #define FW_RI_TPTE_STAGSTATE_S		22
181 #define FW_RI_TPTE_STAGSTATE_M		0x1
182 #define FW_RI_TPTE_STAGSTATE_V(x)	((x) << FW_RI_TPTE_STAGSTATE_S)
183 #define FW_RI_TPTE_STAGSTATE_G(x)	\
184 	(((x) >> FW_RI_TPTE_STAGSTATE_S) & FW_RI_TPTE_STAGSTATE_M)
185 #define FW_RI_TPTE_STAGSTATE_F		FW_RI_TPTE_STAGSTATE_V(1U)
186 
187 #define FW_RI_TPTE_STAGTYPE_S		20
188 #define FW_RI_TPTE_STAGTYPE_M		0x3
189 #define FW_RI_TPTE_STAGTYPE_V(x)	((x) << FW_RI_TPTE_STAGTYPE_S)
190 #define FW_RI_TPTE_STAGTYPE_G(x)	\
191 	(((x) >> FW_RI_TPTE_STAGTYPE_S) & FW_RI_TPTE_STAGTYPE_M)
192 
193 #define FW_RI_TPTE_PDID_S		0
194 #define FW_RI_TPTE_PDID_M		0xfffff
195 #define FW_RI_TPTE_PDID_V(x)		((x) << FW_RI_TPTE_PDID_S)
196 #define FW_RI_TPTE_PDID_G(x)		\
197 	(((x) >> FW_RI_TPTE_PDID_S) & FW_RI_TPTE_PDID_M)
198 
199 #define FW_RI_TPTE_PERM_S		28
200 #define FW_RI_TPTE_PERM_M		0xf
201 #define FW_RI_TPTE_PERM_V(x)		((x) << FW_RI_TPTE_PERM_S)
202 #define FW_RI_TPTE_PERM_G(x)		\
203 	(((x) >> FW_RI_TPTE_PERM_S) & FW_RI_TPTE_PERM_M)
204 
205 #define FW_RI_TPTE_REMINVDIS_S		27
206 #define FW_RI_TPTE_REMINVDIS_M		0x1
207 #define FW_RI_TPTE_REMINVDIS_V(x)	((x) << FW_RI_TPTE_REMINVDIS_S)
208 #define FW_RI_TPTE_REMINVDIS_G(x)	\
209 	(((x) >> FW_RI_TPTE_REMINVDIS_S) & FW_RI_TPTE_REMINVDIS_M)
210 #define FW_RI_TPTE_REMINVDIS_F		FW_RI_TPTE_REMINVDIS_V(1U)
211 
212 #define FW_RI_TPTE_ADDRTYPE_S		26
213 #define FW_RI_TPTE_ADDRTYPE_M		1
214 #define FW_RI_TPTE_ADDRTYPE_V(x)	((x) << FW_RI_TPTE_ADDRTYPE_S)
215 #define FW_RI_TPTE_ADDRTYPE_G(x)	\
216 	(((x) >> FW_RI_TPTE_ADDRTYPE_S) & FW_RI_TPTE_ADDRTYPE_M)
217 #define FW_RI_TPTE_ADDRTYPE_F		FW_RI_TPTE_ADDRTYPE_V(1U)
218 
219 #define FW_RI_TPTE_MWBINDEN_S		25
220 #define FW_RI_TPTE_MWBINDEN_M		0x1
221 #define FW_RI_TPTE_MWBINDEN_V(x)	((x) << FW_RI_TPTE_MWBINDEN_S)
222 #define FW_RI_TPTE_MWBINDEN_G(x)	\
223 	(((x) >> FW_RI_TPTE_MWBINDEN_S) & FW_RI_TPTE_MWBINDEN_M)
224 #define FW_RI_TPTE_MWBINDEN_F		FW_RI_TPTE_MWBINDEN_V(1U)
225 
226 #define FW_RI_TPTE_PS_S			20
227 #define FW_RI_TPTE_PS_M			0x1f
228 #define FW_RI_TPTE_PS_V(x)		((x) << FW_RI_TPTE_PS_S)
229 #define FW_RI_TPTE_PS_G(x)		\
230 	(((x) >> FW_RI_TPTE_PS_S) & FW_RI_TPTE_PS_M)
231 
232 #define FW_RI_TPTE_QPID_S		0
233 #define FW_RI_TPTE_QPID_M		0xfffff
234 #define FW_RI_TPTE_QPID_V(x)		((x) << FW_RI_TPTE_QPID_S)
235 #define FW_RI_TPTE_QPID_G(x)		\
236 	(((x) >> FW_RI_TPTE_QPID_S) & FW_RI_TPTE_QPID_M)
237 
238 #define FW_RI_TPTE_NOSNOOP_S		30
239 #define FW_RI_TPTE_NOSNOOP_M		0x1
240 #define FW_RI_TPTE_NOSNOOP_V(x)		((x) << FW_RI_TPTE_NOSNOOP_S)
241 #define FW_RI_TPTE_NOSNOOP_G(x)		\
242 	(((x) >> FW_RI_TPTE_NOSNOOP_S) & FW_RI_TPTE_NOSNOOP_M)
243 #define FW_RI_TPTE_NOSNOOP_F		FW_RI_TPTE_NOSNOOP_V(1U)
244 
245 #define FW_RI_TPTE_PBLADDR_S		0
246 #define FW_RI_TPTE_PBLADDR_M		0x1fffffff
247 #define FW_RI_TPTE_PBLADDR_V(x)		((x) << FW_RI_TPTE_PBLADDR_S)
248 #define FW_RI_TPTE_PBLADDR_G(x)		\
249 	(((x) >> FW_RI_TPTE_PBLADDR_S) & FW_RI_TPTE_PBLADDR_M)
250 
251 #define FW_RI_TPTE_DCA_S		24
252 #define FW_RI_TPTE_DCA_M		0x1f
253 #define FW_RI_TPTE_DCA_V(x)		((x) << FW_RI_TPTE_DCA_S)
254 #define FW_RI_TPTE_DCA_G(x)		\
255 	(((x) >> FW_RI_TPTE_DCA_S) & FW_RI_TPTE_DCA_M)
256 
257 #define FW_RI_TPTE_MWBCNT_PSTAG_S	0
258 #define FW_RI_TPTE_MWBCNT_PSTAG_M	0xffffff
259 #define FW_RI_TPTE_MWBCNT_PSTAT_V(x)	\
260 	((x) << FW_RI_TPTE_MWBCNT_PSTAG_S)
261 #define FW_RI_TPTE_MWBCNT_PSTAG_G(x)	\
262 	(((x) >> FW_RI_TPTE_MWBCNT_PSTAG_S) & FW_RI_TPTE_MWBCNT_PSTAG_M)
263 
264 enum fw_ri_res_type {
265 	FW_RI_RES_TYPE_SQ,
266 	FW_RI_RES_TYPE_RQ,
267 	FW_RI_RES_TYPE_CQ,
268 	FW_RI_RES_TYPE_SRQ,
269 };
270 
271 enum fw_ri_res_op {
272 	FW_RI_RES_OP_WRITE,
273 	FW_RI_RES_OP_RESET,
274 };
275 
276 struct fw_ri_res {
277 	union fw_ri_restype {
278 		struct fw_ri_res_sqrq {
279 			__u8   restype;
280 			__u8   op;
281 			__be16 r3;
282 			__be32 eqid;
283 			__be32 r4[2];
284 			__be32 fetchszm_to_iqid;
285 			__be32 dcaen_to_eqsize;
286 			__be64 eqaddr;
287 		} sqrq;
288 		struct fw_ri_res_cq {
289 			__u8   restype;
290 			__u8   op;
291 			__be16 r3;
292 			__be32 iqid;
293 			__be32 r4[2];
294 			__be32 iqandst_to_iqandstindex;
295 			__be16 iqdroprss_to_iqesize;
296 			__be16 iqsize;
297 			__be64 iqaddr;
298 			__be32 iqns_iqro;
299 			__be32 r6_lo;
300 			__be64 r7;
301 		} cq;
302 		struct fw_ri_res_srq {
303 			__u8   restype;
304 			__u8   op;
305 			__be16 r3;
306 			__be32 eqid;
307 			__be32 r4[2];
308 			__be32 fetchszm_to_iqid;
309 			__be32 dcaen_to_eqsize;
310 			__be64 eqaddr;
311 			__be32 srqid;
312 			__be32 pdid;
313 			__be32 hwsrqsize;
314 			__be32 hwsrqaddr;
315 		} srq;
316 	} u;
317 };
318 
319 struct fw_ri_res_wr {
320 	__be32 op_nres;
321 	__be32 len16_pkd;
322 	__u64  cookie;
323 #ifndef C99_NOT_SUPPORTED
324 	struct fw_ri_res res[0];
325 #endif
326 };
327 
328 #define FW_RI_RES_WR_NRES_S	0
329 #define FW_RI_RES_WR_NRES_M	0xff
330 #define FW_RI_RES_WR_NRES_V(x)	((x) << FW_RI_RES_WR_NRES_S)
331 #define FW_RI_RES_WR_NRES_G(x)	\
332 	(((x) >> FW_RI_RES_WR_NRES_S) & FW_RI_RES_WR_NRES_M)
333 
334 #define FW_RI_RES_WR_FETCHSZM_S		26
335 #define FW_RI_RES_WR_FETCHSZM_M		0x1
336 #define FW_RI_RES_WR_FETCHSZM_V(x)	((x) << FW_RI_RES_WR_FETCHSZM_S)
337 #define FW_RI_RES_WR_FETCHSZM_G(x)	\
338 	(((x) >> FW_RI_RES_WR_FETCHSZM_S) & FW_RI_RES_WR_FETCHSZM_M)
339 #define FW_RI_RES_WR_FETCHSZM_F	FW_RI_RES_WR_FETCHSZM_V(1U)
340 
341 #define FW_RI_RES_WR_STATUSPGNS_S	25
342 #define FW_RI_RES_WR_STATUSPGNS_M	0x1
343 #define FW_RI_RES_WR_STATUSPGNS_V(x)	((x) << FW_RI_RES_WR_STATUSPGNS_S)
344 #define FW_RI_RES_WR_STATUSPGNS_G(x)	\
345 	(((x) >> FW_RI_RES_WR_STATUSPGNS_S) & FW_RI_RES_WR_STATUSPGNS_M)
346 #define FW_RI_RES_WR_STATUSPGNS_F	FW_RI_RES_WR_STATUSPGNS_V(1U)
347 
348 #define FW_RI_RES_WR_STATUSPGRO_S	24
349 #define FW_RI_RES_WR_STATUSPGRO_M	0x1
350 #define FW_RI_RES_WR_STATUSPGRO_V(x)	((x) << FW_RI_RES_WR_STATUSPGRO_S)
351 #define FW_RI_RES_WR_STATUSPGRO_G(x)	\
352 	(((x) >> FW_RI_RES_WR_STATUSPGRO_S) & FW_RI_RES_WR_STATUSPGRO_M)
353 #define FW_RI_RES_WR_STATUSPGRO_F	FW_RI_RES_WR_STATUSPGRO_V(1U)
354 
355 #define FW_RI_RES_WR_FETCHNS_S		23
356 #define FW_RI_RES_WR_FETCHNS_M		0x1
357 #define FW_RI_RES_WR_FETCHNS_V(x)	((x) << FW_RI_RES_WR_FETCHNS_S)
358 #define FW_RI_RES_WR_FETCHNS_G(x)	\
359 	(((x) >> FW_RI_RES_WR_FETCHNS_S) & FW_RI_RES_WR_FETCHNS_M)
360 #define FW_RI_RES_WR_FETCHNS_F	FW_RI_RES_WR_FETCHNS_V(1U)
361 
362 #define FW_RI_RES_WR_FETCHRO_S		22
363 #define FW_RI_RES_WR_FETCHRO_M		0x1
364 #define FW_RI_RES_WR_FETCHRO_V(x)	((x) << FW_RI_RES_WR_FETCHRO_S)
365 #define FW_RI_RES_WR_FETCHRO_G(x)	\
366 	(((x) >> FW_RI_RES_WR_FETCHRO_S) & FW_RI_RES_WR_FETCHRO_M)
367 #define FW_RI_RES_WR_FETCHRO_F	FW_RI_RES_WR_FETCHRO_V(1U)
368 
369 #define FW_RI_RES_WR_HOSTFCMODE_S	20
370 #define FW_RI_RES_WR_HOSTFCMODE_M	0x3
371 #define FW_RI_RES_WR_HOSTFCMODE_V(x)	((x) << FW_RI_RES_WR_HOSTFCMODE_S)
372 #define FW_RI_RES_WR_HOSTFCMODE_G(x)	\
373 	(((x) >> FW_RI_RES_WR_HOSTFCMODE_S) & FW_RI_RES_WR_HOSTFCMODE_M)
374 
375 #define FW_RI_RES_WR_CPRIO_S	19
376 #define FW_RI_RES_WR_CPRIO_M	0x1
377 #define FW_RI_RES_WR_CPRIO_V(x)	((x) << FW_RI_RES_WR_CPRIO_S)
378 #define FW_RI_RES_WR_CPRIO_G(x)	\
379 	(((x) >> FW_RI_RES_WR_CPRIO_S) & FW_RI_RES_WR_CPRIO_M)
380 #define FW_RI_RES_WR_CPRIO_F	FW_RI_RES_WR_CPRIO_V(1U)
381 
382 #define FW_RI_RES_WR_ONCHIP_S		18
383 #define FW_RI_RES_WR_ONCHIP_M		0x1
384 #define FW_RI_RES_WR_ONCHIP_V(x)	((x) << FW_RI_RES_WR_ONCHIP_S)
385 #define FW_RI_RES_WR_ONCHIP_G(x)	\
386 	(((x) >> FW_RI_RES_WR_ONCHIP_S) & FW_RI_RES_WR_ONCHIP_M)
387 #define FW_RI_RES_WR_ONCHIP_F	FW_RI_RES_WR_ONCHIP_V(1U)
388 
389 #define FW_RI_RES_WR_PCIECHN_S		16
390 #define FW_RI_RES_WR_PCIECHN_M		0x3
391 #define FW_RI_RES_WR_PCIECHN_V(x)	((x) << FW_RI_RES_WR_PCIECHN_S)
392 #define FW_RI_RES_WR_PCIECHN_G(x)	\
393 	(((x) >> FW_RI_RES_WR_PCIECHN_S) & FW_RI_RES_WR_PCIECHN_M)
394 
395 #define FW_RI_RES_WR_IQID_S	0
396 #define FW_RI_RES_WR_IQID_M	0xffff
397 #define FW_RI_RES_WR_IQID_V(x)	((x) << FW_RI_RES_WR_IQID_S)
398 #define FW_RI_RES_WR_IQID_G(x)	\
399 	(((x) >> FW_RI_RES_WR_IQID_S) & FW_RI_RES_WR_IQID_M)
400 
401 #define FW_RI_RES_WR_DCAEN_S	31
402 #define FW_RI_RES_WR_DCAEN_M	0x1
403 #define FW_RI_RES_WR_DCAEN_V(x)	((x) << FW_RI_RES_WR_DCAEN_S)
404 #define FW_RI_RES_WR_DCAEN_G(x)	\
405 	(((x) >> FW_RI_RES_WR_DCAEN_S) & FW_RI_RES_WR_DCAEN_M)
406 #define FW_RI_RES_WR_DCAEN_F	FW_RI_RES_WR_DCAEN_V(1U)
407 
408 #define FW_RI_RES_WR_DCACPU_S		26
409 #define FW_RI_RES_WR_DCACPU_M		0x1f
410 #define FW_RI_RES_WR_DCACPU_V(x)	((x) << FW_RI_RES_WR_DCACPU_S)
411 #define FW_RI_RES_WR_DCACPU_G(x)	\
412 	(((x) >> FW_RI_RES_WR_DCACPU_S) & FW_RI_RES_WR_DCACPU_M)
413 
414 #define FW_RI_RES_WR_FBMIN_S	23
415 #define FW_RI_RES_WR_FBMIN_M	0x7
416 #define FW_RI_RES_WR_FBMIN_V(x)	((x) << FW_RI_RES_WR_FBMIN_S)
417 #define FW_RI_RES_WR_FBMIN_G(x)	\
418 	(((x) >> FW_RI_RES_WR_FBMIN_S) & FW_RI_RES_WR_FBMIN_M)
419 
420 #define FW_RI_RES_WR_FBMAX_S	20
421 #define FW_RI_RES_WR_FBMAX_M	0x7
422 #define FW_RI_RES_WR_FBMAX_V(x)	((x) << FW_RI_RES_WR_FBMAX_S)
423 #define FW_RI_RES_WR_FBMAX_G(x)	\
424 	(((x) >> FW_RI_RES_WR_FBMAX_S) & FW_RI_RES_WR_FBMAX_M)
425 
426 #define FW_RI_RES_WR_CIDXFTHRESHO_S	19
427 #define FW_RI_RES_WR_CIDXFTHRESHO_M	0x1
428 #define FW_RI_RES_WR_CIDXFTHRESHO_V(x)	((x) << FW_RI_RES_WR_CIDXFTHRESHO_S)
429 #define FW_RI_RES_WR_CIDXFTHRESHO_G(x)	\
430 	(((x) >> FW_RI_RES_WR_CIDXFTHRESHO_S) & FW_RI_RES_WR_CIDXFTHRESHO_M)
431 #define FW_RI_RES_WR_CIDXFTHRESHO_F	FW_RI_RES_WR_CIDXFTHRESHO_V(1U)
432 
433 #define FW_RI_RES_WR_CIDXFTHRESH_S	16
434 #define FW_RI_RES_WR_CIDXFTHRESH_M	0x7
435 #define FW_RI_RES_WR_CIDXFTHRESH_V(x)	((x) << FW_RI_RES_WR_CIDXFTHRESH_S)
436 #define FW_RI_RES_WR_CIDXFTHRESH_G(x)	\
437 	(((x) >> FW_RI_RES_WR_CIDXFTHRESH_S) & FW_RI_RES_WR_CIDXFTHRESH_M)
438 
439 #define FW_RI_RES_WR_EQSIZE_S		0
440 #define FW_RI_RES_WR_EQSIZE_M		0xffff
441 #define FW_RI_RES_WR_EQSIZE_V(x)	((x) << FW_RI_RES_WR_EQSIZE_S)
442 #define FW_RI_RES_WR_EQSIZE_G(x)	\
443 	(((x) >> FW_RI_RES_WR_EQSIZE_S) & FW_RI_RES_WR_EQSIZE_M)
444 
445 #define FW_RI_RES_WR_IQANDST_S		15
446 #define FW_RI_RES_WR_IQANDST_M		0x1
447 #define FW_RI_RES_WR_IQANDST_V(x)	((x) << FW_RI_RES_WR_IQANDST_S)
448 #define FW_RI_RES_WR_IQANDST_G(x)	\
449 	(((x) >> FW_RI_RES_WR_IQANDST_S) & FW_RI_RES_WR_IQANDST_M)
450 #define FW_RI_RES_WR_IQANDST_F	FW_RI_RES_WR_IQANDST_V(1U)
451 
452 #define FW_RI_RES_WR_IQANUS_S		14
453 #define FW_RI_RES_WR_IQANUS_M		0x1
454 #define FW_RI_RES_WR_IQANUS_V(x)	((x) << FW_RI_RES_WR_IQANUS_S)
455 #define FW_RI_RES_WR_IQANUS_G(x)	\
456 	(((x) >> FW_RI_RES_WR_IQANUS_S) & FW_RI_RES_WR_IQANUS_M)
457 #define FW_RI_RES_WR_IQANUS_F	FW_RI_RES_WR_IQANUS_V(1U)
458 
459 #define FW_RI_RES_WR_IQANUD_S		12
460 #define FW_RI_RES_WR_IQANUD_M		0x3
461 #define FW_RI_RES_WR_IQANUD_V(x)	((x) << FW_RI_RES_WR_IQANUD_S)
462 #define FW_RI_RES_WR_IQANUD_G(x)	\
463 	(((x) >> FW_RI_RES_WR_IQANUD_S) & FW_RI_RES_WR_IQANUD_M)
464 
465 #define FW_RI_RES_WR_IQANDSTINDEX_S	0
466 #define FW_RI_RES_WR_IQANDSTINDEX_M	0xfff
467 #define FW_RI_RES_WR_IQANDSTINDEX_V(x)	((x) << FW_RI_RES_WR_IQANDSTINDEX_S)
468 #define FW_RI_RES_WR_IQANDSTINDEX_G(x)	\
469 	(((x) >> FW_RI_RES_WR_IQANDSTINDEX_S) & FW_RI_RES_WR_IQANDSTINDEX_M)
470 
471 #define FW_RI_RES_WR_IQDROPRSS_S	15
472 #define FW_RI_RES_WR_IQDROPRSS_M	0x1
473 #define FW_RI_RES_WR_IQDROPRSS_V(x)	((x) << FW_RI_RES_WR_IQDROPRSS_S)
474 #define FW_RI_RES_WR_IQDROPRSS_G(x)	\
475 	(((x) >> FW_RI_RES_WR_IQDROPRSS_S) & FW_RI_RES_WR_IQDROPRSS_M)
476 #define FW_RI_RES_WR_IQDROPRSS_F	FW_RI_RES_WR_IQDROPRSS_V(1U)
477 
478 #define FW_RI_RES_WR_IQGTSMODE_S	14
479 #define FW_RI_RES_WR_IQGTSMODE_M	0x1
480 #define FW_RI_RES_WR_IQGTSMODE_V(x)	((x) << FW_RI_RES_WR_IQGTSMODE_S)
481 #define FW_RI_RES_WR_IQGTSMODE_G(x)	\
482 	(((x) >> FW_RI_RES_WR_IQGTSMODE_S) & FW_RI_RES_WR_IQGTSMODE_M)
483 #define FW_RI_RES_WR_IQGTSMODE_F	FW_RI_RES_WR_IQGTSMODE_V(1U)
484 
485 #define FW_RI_RES_WR_IQPCIECH_S		12
486 #define FW_RI_RES_WR_IQPCIECH_M		0x3
487 #define FW_RI_RES_WR_IQPCIECH_V(x)	((x) << FW_RI_RES_WR_IQPCIECH_S)
488 #define FW_RI_RES_WR_IQPCIECH_G(x)	\
489 	(((x) >> FW_RI_RES_WR_IQPCIECH_S) & FW_RI_RES_WR_IQPCIECH_M)
490 
491 #define FW_RI_RES_WR_IQDCAEN_S		11
492 #define FW_RI_RES_WR_IQDCAEN_M		0x1
493 #define FW_RI_RES_WR_IQDCAEN_V(x)	((x) << FW_RI_RES_WR_IQDCAEN_S)
494 #define FW_RI_RES_WR_IQDCAEN_G(x)	\
495 	(((x) >> FW_RI_RES_WR_IQDCAEN_S) & FW_RI_RES_WR_IQDCAEN_M)
496 #define FW_RI_RES_WR_IQDCAEN_F	FW_RI_RES_WR_IQDCAEN_V(1U)
497 
498 #define FW_RI_RES_WR_IQDCACPU_S		6
499 #define FW_RI_RES_WR_IQDCACPU_M		0x1f
500 #define FW_RI_RES_WR_IQDCACPU_V(x)	((x) << FW_RI_RES_WR_IQDCACPU_S)
501 #define FW_RI_RES_WR_IQDCACPU_G(x)	\
502 	(((x) >> FW_RI_RES_WR_IQDCACPU_S) & FW_RI_RES_WR_IQDCACPU_M)
503 
504 #define FW_RI_RES_WR_IQINTCNTTHRESH_S		4
505 #define FW_RI_RES_WR_IQINTCNTTHRESH_M		0x3
506 #define FW_RI_RES_WR_IQINTCNTTHRESH_V(x)	\
507 	((x) << FW_RI_RES_WR_IQINTCNTTHRESH_S)
508 #define FW_RI_RES_WR_IQINTCNTTHRESH_G(x)	\
509 	(((x) >> FW_RI_RES_WR_IQINTCNTTHRESH_S) & FW_RI_RES_WR_IQINTCNTTHRESH_M)
510 
511 #define FW_RI_RES_WR_IQO_S	3
512 #define FW_RI_RES_WR_IQO_M	0x1
513 #define FW_RI_RES_WR_IQO_V(x)	((x) << FW_RI_RES_WR_IQO_S)
514 #define FW_RI_RES_WR_IQO_G(x)	\
515 	(((x) >> FW_RI_RES_WR_IQO_S) & FW_RI_RES_WR_IQO_M)
516 #define FW_RI_RES_WR_IQO_F	FW_RI_RES_WR_IQO_V(1U)
517 
518 #define FW_RI_RES_WR_IQCPRIO_S		2
519 #define FW_RI_RES_WR_IQCPRIO_M		0x1
520 #define FW_RI_RES_WR_IQCPRIO_V(x)	((x) << FW_RI_RES_WR_IQCPRIO_S)
521 #define FW_RI_RES_WR_IQCPRIO_G(x)	\
522 	(((x) >> FW_RI_RES_WR_IQCPRIO_S) & FW_RI_RES_WR_IQCPRIO_M)
523 #define FW_RI_RES_WR_IQCPRIO_F	FW_RI_RES_WR_IQCPRIO_V(1U)
524 
525 #define FW_RI_RES_WR_IQESIZE_S		0
526 #define FW_RI_RES_WR_IQESIZE_M		0x3
527 #define FW_RI_RES_WR_IQESIZE_V(x)	((x) << FW_RI_RES_WR_IQESIZE_S)
528 #define FW_RI_RES_WR_IQESIZE_G(x)	\
529 	(((x) >> FW_RI_RES_WR_IQESIZE_S) & FW_RI_RES_WR_IQESIZE_M)
530 
531 #define FW_RI_RES_WR_IQNS_S	31
532 #define FW_RI_RES_WR_IQNS_M	0x1
533 #define FW_RI_RES_WR_IQNS_V(x)	((x) << FW_RI_RES_WR_IQNS_S)
534 #define FW_RI_RES_WR_IQNS_G(x)	\
535 	(((x) >> FW_RI_RES_WR_IQNS_S) & FW_RI_RES_WR_IQNS_M)
536 #define FW_RI_RES_WR_IQNS_F	FW_RI_RES_WR_IQNS_V(1U)
537 
538 #define FW_RI_RES_WR_IQRO_S	30
539 #define FW_RI_RES_WR_IQRO_M	0x1
540 #define FW_RI_RES_WR_IQRO_V(x)	((x) << FW_RI_RES_WR_IQRO_S)
541 #define FW_RI_RES_WR_IQRO_G(x)	\
542 	(((x) >> FW_RI_RES_WR_IQRO_S) & FW_RI_RES_WR_IQRO_M)
543 #define FW_RI_RES_WR_IQRO_F	FW_RI_RES_WR_IQRO_V(1U)
544 
545 struct fw_ri_rdma_write_wr {
546 	__u8   opcode;
547 	__u8   flags;
548 	__u16  wrid;
549 	__u8   r1[3];
550 	__u8   len16;
551 	/*
552 	 * Use union for immediate data to be consistent with stack's 32 bit
553 	 * data and iWARP spec's 64 bit data.
554 	 */
555 	union {
556 		struct {
557 			__be32 imm_data32;
558 			u32 reserved;
559 		} ib_imm_data;
560 		__be64 imm_data64;
561 	} iw_imm_data;
562 	__be32 plen;
563 	__be32 stag_sink;
564 	__be64 to_sink;
565 #ifndef C99_NOT_SUPPORTED
566 	union {
567 		struct fw_ri_immd immd_src[0];
568 		struct fw_ri_isgl isgl_src[0];
569 	} u;
570 #endif
571 };
572 
573 struct fw_ri_send_wr {
574 	__u8   opcode;
575 	__u8   flags;
576 	__u16  wrid;
577 	__u8   r1[3];
578 	__u8   len16;
579 	__be32 sendop_pkd;
580 	__be32 stag_inv;
581 	__be32 plen;
582 	__be32 r3;
583 	__be64 r4;
584 #ifndef C99_NOT_SUPPORTED
585 	union {
586 		struct fw_ri_immd immd_src[0];
587 		struct fw_ri_isgl isgl_src[0];
588 	} u;
589 #endif
590 };
591 
592 #define FW_RI_SEND_WR_SENDOP_S		0
593 #define FW_RI_SEND_WR_SENDOP_M		0xf
594 #define FW_RI_SEND_WR_SENDOP_V(x)	((x) << FW_RI_SEND_WR_SENDOP_S)
595 #define FW_RI_SEND_WR_SENDOP_G(x)	\
596 	(((x) >> FW_RI_SEND_WR_SENDOP_S) & FW_RI_SEND_WR_SENDOP_M)
597 
598 struct fw_ri_rdma_write_cmpl_wr {
599 	__u8   opcode;
600 	__u8   flags;
601 	__u16  wrid;
602 	__u8   r1[3];
603 	__u8   len16;
604 	__u8   r2;
605 	__u8   flags_send;
606 	__u16  wrid_send;
607 	__be32 stag_inv;
608 	__be32 plen;
609 	__be32 stag_sink;
610 	__be64 to_sink;
611 	union fw_ri_cmpl {
612 		struct fw_ri_immd_cmpl {
613 			__u8   op;
614 			__u8   r1[6];
615 			__u8   immdlen;
616 			__u8   data[16];
617 		} immd_src;
618 		struct fw_ri_isgl isgl_src;
619 	} u_cmpl;
620 	__be64 r3;
621 #ifndef C99_NOT_SUPPORTED
622 	union fw_ri_write {
623 		struct fw_ri_immd immd_src[0];
624 		struct fw_ri_isgl isgl_src[0];
625 	} u;
626 #endif
627 };
628 
629 struct fw_ri_rdma_read_wr {
630 	__u8   opcode;
631 	__u8   flags;
632 	__u16  wrid;
633 	__u8   r1[3];
634 	__u8   len16;
635 	__be64 r2;
636 	__be32 stag_sink;
637 	__be32 to_sink_hi;
638 	__be32 to_sink_lo;
639 	__be32 plen;
640 	__be32 stag_src;
641 	__be32 to_src_hi;
642 	__be32 to_src_lo;
643 	__be32 r5;
644 };
645 
646 struct fw_ri_recv_wr {
647 	__u8   opcode;
648 	__u8   r1;
649 	__u16  wrid;
650 	__u8   r2[3];
651 	__u8   len16;
652 	struct fw_ri_isgl isgl;
653 };
654 
655 struct fw_ri_bind_mw_wr {
656 	__u8   opcode;
657 	__u8   flags;
658 	__u16  wrid;
659 	__u8   r1[3];
660 	__u8   len16;
661 	__u8   qpbinde_to_dcacpu;
662 	__u8   pgsz_shift;
663 	__u8   addr_type;
664 	__u8   mem_perms;
665 	__be32 stag_mr;
666 	__be32 stag_mw;
667 	__be32 r3;
668 	__be64 len_mw;
669 	__be64 va_fbo;
670 	__be64 r4;
671 };
672 
673 #define FW_RI_BIND_MW_WR_QPBINDE_S	6
674 #define FW_RI_BIND_MW_WR_QPBINDE_M	0x1
675 #define FW_RI_BIND_MW_WR_QPBINDE_V(x)	((x) << FW_RI_BIND_MW_WR_QPBINDE_S)
676 #define FW_RI_BIND_MW_WR_QPBINDE_G(x)	\
677 	(((x) >> FW_RI_BIND_MW_WR_QPBINDE_S) & FW_RI_BIND_MW_WR_QPBINDE_M)
678 #define FW_RI_BIND_MW_WR_QPBINDE_F	FW_RI_BIND_MW_WR_QPBINDE_V(1U)
679 
680 #define FW_RI_BIND_MW_WR_NS_S		5
681 #define FW_RI_BIND_MW_WR_NS_M		0x1
682 #define FW_RI_BIND_MW_WR_NS_V(x)	((x) << FW_RI_BIND_MW_WR_NS_S)
683 #define FW_RI_BIND_MW_WR_NS_G(x)	\
684 	(((x) >> FW_RI_BIND_MW_WR_NS_S) & FW_RI_BIND_MW_WR_NS_M)
685 #define FW_RI_BIND_MW_WR_NS_F	FW_RI_BIND_MW_WR_NS_V(1U)
686 
687 #define FW_RI_BIND_MW_WR_DCACPU_S	0
688 #define FW_RI_BIND_MW_WR_DCACPU_M	0x1f
689 #define FW_RI_BIND_MW_WR_DCACPU_V(x)	((x) << FW_RI_BIND_MW_WR_DCACPU_S)
690 #define FW_RI_BIND_MW_WR_DCACPU_G(x)	\
691 	(((x) >> FW_RI_BIND_MW_WR_DCACPU_S) & FW_RI_BIND_MW_WR_DCACPU_M)
692 
693 struct fw_ri_fr_nsmr_wr {
694 	__u8   opcode;
695 	__u8   flags;
696 	__u16  wrid;
697 	__u8   r1[3];
698 	__u8   len16;
699 	__u8   qpbinde_to_dcacpu;
700 	__u8   pgsz_shift;
701 	__u8   addr_type;
702 	__u8   mem_perms;
703 	__be32 stag;
704 	__be32 len_hi;
705 	__be32 len_lo;
706 	__be32 va_hi;
707 	__be32 va_lo_fbo;
708 };
709 
710 #define FW_RI_FR_NSMR_WR_QPBINDE_S	6
711 #define FW_RI_FR_NSMR_WR_QPBINDE_M	0x1
712 #define FW_RI_FR_NSMR_WR_QPBINDE_V(x)	((x) << FW_RI_FR_NSMR_WR_QPBINDE_S)
713 #define FW_RI_FR_NSMR_WR_QPBINDE_G(x)	\
714 	(((x) >> FW_RI_FR_NSMR_WR_QPBINDE_S) & FW_RI_FR_NSMR_WR_QPBINDE_M)
715 #define FW_RI_FR_NSMR_WR_QPBINDE_F	FW_RI_FR_NSMR_WR_QPBINDE_V(1U)
716 
717 #define FW_RI_FR_NSMR_WR_NS_S		5
718 #define FW_RI_FR_NSMR_WR_NS_M		0x1
719 #define FW_RI_FR_NSMR_WR_NS_V(x)	((x) << FW_RI_FR_NSMR_WR_NS_S)
720 #define FW_RI_FR_NSMR_WR_NS_G(x)	\
721 	(((x) >> FW_RI_FR_NSMR_WR_NS_S) & FW_RI_FR_NSMR_WR_NS_M)
722 #define FW_RI_FR_NSMR_WR_NS_F	FW_RI_FR_NSMR_WR_NS_V(1U)
723 
724 #define FW_RI_FR_NSMR_WR_DCACPU_S	0
725 #define FW_RI_FR_NSMR_WR_DCACPU_M	0x1f
726 #define FW_RI_FR_NSMR_WR_DCACPU_V(x)	((x) << FW_RI_FR_NSMR_WR_DCACPU_S)
727 #define FW_RI_FR_NSMR_WR_DCACPU_G(x)	\
728 	(((x) >> FW_RI_FR_NSMR_WR_DCACPU_S) & FW_RI_FR_NSMR_WR_DCACPU_M)
729 
730 struct fw_ri_fr_nsmr_tpte_wr {
731 	__u8	opcode;
732 	__u8   flags;
733 	__u16  wrid;
734 	__u8   r1[3];
735 	__u8   len16;
736 	__be32  r2;
737 	__be32  stag;
738 	struct fw_ri_tpte tpte;
739 	__u64  pbl[2];
740 };
741 
742 struct fw_ri_inv_lstag_wr {
743 	__u8   opcode;
744 	__u8   flags;
745 	__u16  wrid;
746 	__u8   r1[3];
747 	__u8   len16;
748 	__be32 r2;
749 	__be32 stag_inv;
750 };
751 
752 enum fw_ri_type {
753 	FW_RI_TYPE_INIT,
754 	FW_RI_TYPE_FINI,
755 	FW_RI_TYPE_TERMINATE
756 };
757 
758 enum fw_ri_init_p2ptype {
759 	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
760 	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
761 	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
762 	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
763 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
764 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
765 	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
766 };
767 
768 enum fw_ri_init_rqeqid_srq {
769 	FW_RI_INIT_RQEQID_SRQ			= 1 << 31,
770 };
771 
772 struct fw_ri_wr {
773 	__be32 op_compl;
774 	__be32 flowid_len16;
775 	__u64  cookie;
776 	union fw_ri {
777 		struct fw_ri_init {
778 			__u8   type;
779 			__u8   mpareqbit_p2ptype;
780 			__u8   r4[2];
781 			__u8   mpa_attrs;
782 			__u8   qp_caps;
783 			__be16 nrqe;
784 			__be32 pdid;
785 			__be32 qpid;
786 			__be32 sq_eqid;
787 			__be32 rq_eqid;
788 			__be32 scqid;
789 			__be32 rcqid;
790 			__be32 ord_max;
791 			__be32 ird_max;
792 			__be32 iss;
793 			__be32 irs;
794 			__be32 hwrqsize;
795 			__be32 hwrqaddr;
796 			__be64 r5;
797 			union fw_ri_init_p2p {
798 				struct fw_ri_rdma_write_wr write;
799 				struct fw_ri_rdma_read_wr read;
800 				struct fw_ri_send_wr send;
801 			} u;
802 		} init;
803 		struct fw_ri_fini {
804 			__u8   type;
805 			__u8   r3[7];
806 			__be64 r4;
807 		} fini;
808 		struct fw_ri_terminate {
809 			__u8   type;
810 			__u8   r3[3];
811 			__be32 immdlen;
812 			__u8   termmsg[40];
813 		} terminate;
814 	} u;
815 };
816 
817 #define FW_RI_WR_MPAREQBIT_S	7
818 #define FW_RI_WR_MPAREQBIT_M	0x1
819 #define FW_RI_WR_MPAREQBIT_V(x)	((x) << FW_RI_WR_MPAREQBIT_S)
820 #define FW_RI_WR_MPAREQBIT_G(x)	\
821 	(((x) >> FW_RI_WR_MPAREQBIT_S) & FW_RI_WR_MPAREQBIT_M)
822 #define FW_RI_WR_MPAREQBIT_F	FW_RI_WR_MPAREQBIT_V(1U)
823 
824 #define FW_RI_WR_P2PTYPE_S	0
825 #define FW_RI_WR_P2PTYPE_M	0xf
826 #define FW_RI_WR_P2PTYPE_V(x)	((x) << FW_RI_WR_P2PTYPE_S)
827 #define FW_RI_WR_P2PTYPE_G(x)	\
828 	(((x) >> FW_RI_WR_P2PTYPE_S) & FW_RI_WR_P2PTYPE_M)
829 
830 #endif /* _T4FW_RI_API_H_ */
831