1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __T4_H__ 32 #define __T4_H__ 33 34 #include "t4_hw.h" 35 #include "t4_regs.h" 36 #include "t4_values.h" 37 #include "t4_msg.h" 38 #include "t4fw_ri_api.h" 39 40 #define T4_MAX_NUM_PD 65536 41 #define T4_MAX_MR_SIZE (~0ULL) 42 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ 43 #define T4_STAG_UNSET 0xffffffff 44 #define T4_FW_MAJ 0 45 #define PCIE_MA_SYNC_A 0x30b4 46 47 struct t4_status_page { 48 __be32 rsvd1; /* flit 0 - hw owns */ 49 __be16 rsvd2; 50 __be16 qid; 51 __be16 cidx; 52 __be16 pidx; 53 u8 qp_err; /* flit 1 - sw owns */ 54 u8 db_off; 55 u8 pad[2]; 56 u16 host_wq_pidx; 57 u16 host_cidx; 58 u16 host_pidx; 59 u16 pad2; 60 u32 srqidx; 61 }; 62 63 #define T4_RQT_ENTRY_SHIFT 6 64 #define T4_RQT_ENTRY_SIZE BIT(T4_RQT_ENTRY_SHIFT) 65 #define T4_EQ_ENTRY_SIZE 64 66 67 #define T4_SQ_NUM_SLOTS 5 68 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 69 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 70 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 71 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 72 sizeof(struct fw_ri_immd))) 73 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 74 sizeof(struct fw_ri_rdma_write_wr) - \ 75 sizeof(struct fw_ri_immd))) 76 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 77 sizeof(struct fw_ri_rdma_write_wr) - \ 78 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 79 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 80 sizeof(struct fw_ri_immd)) & ~31UL) 81 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 82 #define T4_MAX_FR_DSGL 1024 83 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) 84 85 static inline int t4_max_fr_depth(int use_dsgl) 86 { 87 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH; 88 } 89 90 #define T4_RQ_NUM_SLOTS 2 91 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 92 #define T4_MAX_RECV_SGE 4 93 94 #define T4_WRITE_CMPL_MAX_SGL 4 95 #define T4_WRITE_CMPL_MAX_CQE 16 96 97 union t4_wr { 98 struct fw_ri_res_wr res; 99 struct fw_ri_wr ri; 100 struct fw_ri_rdma_write_wr write; 101 struct fw_ri_send_wr send; 102 struct fw_ri_rdma_read_wr read; 103 struct fw_ri_bind_mw_wr bind; 104 struct fw_ri_fr_nsmr_wr fr; 105 struct fw_ri_fr_nsmr_tpte_wr fr_tpte; 106 struct fw_ri_inv_lstag_wr inv; 107 struct fw_ri_rdma_write_cmpl_wr write_cmpl; 108 struct t4_status_page status; 109 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 110 }; 111 112 union t4_recv_wr { 113 struct fw_ri_recv_wr recv; 114 struct t4_status_page status; 115 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 116 }; 117 118 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 119 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 120 { 121 wqe->send.opcode = (u8)opcode; 122 wqe->send.flags = flags; 123 wqe->send.wrid = wrid; 124 wqe->send.r1[0] = 0; 125 wqe->send.r1[1] = 0; 126 wqe->send.r1[2] = 0; 127 wqe->send.len16 = len16; 128 } 129 130 /* CQE/AE status codes */ 131 #define T4_ERR_SUCCESS 0x0 132 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 133 /* STAG is offlimt, being 0, */ 134 /* or STAG_key mismatch */ 135 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 136 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 137 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 138 #define T4_ERR_WRAP 0x5 /* Wrap error */ 139 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 140 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 141 /* shared memory region */ 142 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 143 /* shared memory region */ 144 #define T4_ERR_ECC 0x9 /* ECC error detected */ 145 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 146 /* reading PSTAG for a MW */ 147 /* Invalidate */ 148 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 149 /* software error */ 150 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 151 #define T4_ERR_CRC 0x10 /* CRC error */ 152 #define T4_ERR_MARKER 0x11 /* Marker error */ 153 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 154 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 155 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 156 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 157 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 158 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 159 #define T4_ERR_MSN 0x18 /* MSN error */ 160 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 161 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 162 /* or READ_REQ */ 163 #define T4_ERR_MSN_GAP 0x1B 164 #define T4_ERR_MSN_RANGE 0x1C 165 #define T4_ERR_IRD_OVERFLOW 0x1D 166 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 167 /* software error */ 168 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 169 /* mismatch) */ 170 /* 171 * CQE defs 172 */ 173 struct t4_cqe { 174 __be32 header; 175 __be32 len; 176 union { 177 struct { 178 __be32 stag; 179 __be32 msn; 180 } rcqe; 181 struct { 182 __be32 stag; 183 u16 nada2; 184 u16 cidx; 185 } scqe; 186 struct { 187 __be32 wrid_hi; 188 __be32 wrid_low; 189 } gen; 190 struct { 191 __be32 stag; 192 __be32 msn; 193 __be32 reserved; 194 __be32 abs_rqe_idx; 195 } srcqe; 196 struct { 197 __be32 mo; 198 __be32 msn; 199 /* 200 * Use union for immediate data to be consistent with 201 * stack's 32 bit data and iWARP spec's 64 bit data. 202 */ 203 union { 204 struct { 205 __be32 imm_data32; 206 u32 reserved; 207 } ib_imm_data; 208 __be64 imm_data64; 209 } iw_imm_data; 210 } imm_data_rcqe; 211 212 u64 drain_cookie; 213 __be64 flits[3]; 214 } u; 215 __be64 reserved[3]; 216 __be64 bits_type_ts; 217 }; 218 219 /* macros for flit 0 of the cqe */ 220 221 #define CQE_QPID_S 12 222 #define CQE_QPID_M 0xFFFFF 223 #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M) 224 #define CQE_QPID_V(x) ((x)<<CQE_QPID_S) 225 226 #define CQE_SWCQE_S 11 227 #define CQE_SWCQE_M 0x1 228 #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M) 229 #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S) 230 231 #define CQE_DRAIN_S 10 232 #define CQE_DRAIN_M 0x1 233 #define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M) 234 #define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S) 235 236 #define CQE_STATUS_S 5 237 #define CQE_STATUS_M 0x1F 238 #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M) 239 #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S) 240 241 #define CQE_TYPE_S 4 242 #define CQE_TYPE_M 0x1 243 #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M) 244 #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S) 245 246 #define CQE_OPCODE_S 0 247 #define CQE_OPCODE_M 0xF 248 #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M) 249 #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S) 250 251 #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header))) 252 #define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header))) 253 #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header))) 254 #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header))) 255 #define SQ_TYPE(x) (CQE_TYPE((x))) 256 #define RQ_TYPE(x) (!CQE_TYPE((x))) 257 #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header))) 258 #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header))) 259 260 #define CQE_SEND_OPCODE(x)( \ 261 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 262 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 263 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 264 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 265 266 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 267 268 /* used for RQ completion processing */ 269 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 270 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 271 #define CQE_ABS_RQE_IDX(x) (be32_to_cpu((x)->u.srcqe.abs_rqe_idx)) 272 #define CQE_IMM_DATA(x)( \ 273 (x)->u.imm_data_rcqe.iw_imm_data.ib_imm_data.imm_data32) 274 275 /* used for SQ completion processing */ 276 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 277 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag)) 278 279 /* generic accessor macros */ 280 #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi)) 281 #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low)) 282 #define CQE_DRAIN_COOKIE(x) ((x)->u.drain_cookie) 283 284 /* macros for flit 3 of the cqe */ 285 #define CQE_GENBIT_S 63 286 #define CQE_GENBIT_M 0x1 287 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M) 288 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S) 289 290 #define CQE_OVFBIT_S 62 291 #define CQE_OVFBIT_M 0x1 292 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M) 293 294 #define CQE_IQTYPE_S 60 295 #define CQE_IQTYPE_M 0x3 296 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M) 297 298 #define CQE_TS_M 0x0fffffffffffffffULL 299 #define CQE_TS_G(x) ((x) & CQE_TS_M) 300 301 #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts))) 302 #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts))) 303 #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts))) 304 305 struct t4_swsqe { 306 u64 wr_id; 307 struct t4_cqe cqe; 308 int read_len; 309 int opcode; 310 int complete; 311 int signaled; 312 u16 idx; 313 int flushed; 314 ktime_t host_time; 315 u64 sge_ts; 316 }; 317 318 static inline pgprot_t t4_pgprot_wc(pgprot_t prot) 319 { 320 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 321 return pgprot_writecombine(prot); 322 #else 323 return pgprot_noncached(prot); 324 #endif 325 } 326 327 enum { 328 T4_SQ_ONCHIP = (1<<0), 329 }; 330 331 struct t4_sq { 332 union t4_wr *queue; 333 dma_addr_t dma_addr; 334 DEFINE_DMA_UNMAP_ADDR(mapping); 335 unsigned long phys_addr; 336 struct t4_swsqe *sw_sq; 337 struct t4_swsqe *oldest_read; 338 void __iomem *bar2_va; 339 u64 bar2_pa; 340 size_t memsize; 341 u32 bar2_qid; 342 u32 qid; 343 u16 in_use; 344 u16 size; 345 u16 cidx; 346 u16 pidx; 347 u16 wq_pidx; 348 u16 wq_pidx_inc; 349 u16 flags; 350 short flush_cidx; 351 }; 352 353 struct t4_swrqe { 354 u64 wr_id; 355 ktime_t host_time; 356 u64 sge_ts; 357 int valid; 358 }; 359 360 struct t4_rq { 361 union t4_recv_wr *queue; 362 dma_addr_t dma_addr; 363 DEFINE_DMA_UNMAP_ADDR(mapping); 364 struct t4_swrqe *sw_rq; 365 void __iomem *bar2_va; 366 u64 bar2_pa; 367 size_t memsize; 368 u32 bar2_qid; 369 u32 qid; 370 u32 msn; 371 u32 rqt_hwaddr; 372 u16 rqt_size; 373 u16 in_use; 374 u16 size; 375 u16 cidx; 376 u16 pidx; 377 u16 wq_pidx; 378 u16 wq_pidx_inc; 379 }; 380 381 struct t4_wq { 382 struct t4_sq sq; 383 struct t4_rq rq; 384 void __iomem *db; 385 struct c4iw_rdev *rdev; 386 int flushed; 387 u8 *qp_errp; 388 u32 *srqidxp; 389 }; 390 391 struct t4_srq_pending_wr { 392 u64 wr_id; 393 union t4_recv_wr wqe; 394 u8 len16; 395 }; 396 397 struct t4_srq { 398 union t4_recv_wr *queue; 399 dma_addr_t dma_addr; 400 DECLARE_PCI_UNMAP_ADDR(mapping); 401 struct t4_swrqe *sw_rq; 402 void __iomem *bar2_va; 403 u64 bar2_pa; 404 size_t memsize; 405 u32 bar2_qid; 406 u32 qid; 407 u32 msn; 408 u32 rqt_hwaddr; 409 u32 rqt_abs_idx; 410 u16 rqt_size; 411 u16 size; 412 u16 cidx; 413 u16 pidx; 414 u16 wq_pidx; 415 u16 wq_pidx_inc; 416 u16 in_use; 417 struct t4_srq_pending_wr *pending_wrs; 418 u16 pending_cidx; 419 u16 pending_pidx; 420 u16 pending_in_use; 421 u16 ooo_count; 422 }; 423 424 static inline u32 t4_srq_avail(struct t4_srq *srq) 425 { 426 return srq->size - 1 - srq->in_use; 427 } 428 429 static inline void t4_srq_produce(struct t4_srq *srq, u8 len16) 430 { 431 srq->in_use++; 432 if (++srq->pidx == srq->size) 433 srq->pidx = 0; 434 srq->wq_pidx += DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE); 435 if (srq->wq_pidx >= srq->size * T4_RQ_NUM_SLOTS) 436 srq->wq_pidx %= srq->size * T4_RQ_NUM_SLOTS; 437 srq->queue[srq->size].status.host_pidx = srq->pidx; 438 } 439 440 static inline void t4_srq_produce_pending_wr(struct t4_srq *srq) 441 { 442 srq->pending_in_use++; 443 srq->in_use++; 444 if (++srq->pending_pidx == srq->size) 445 srq->pending_pidx = 0; 446 } 447 448 static inline void t4_srq_consume_pending_wr(struct t4_srq *srq) 449 { 450 srq->pending_in_use--; 451 srq->in_use--; 452 if (++srq->pending_cidx == srq->size) 453 srq->pending_cidx = 0; 454 } 455 456 static inline void t4_srq_produce_ooo(struct t4_srq *srq) 457 { 458 srq->in_use--; 459 srq->ooo_count++; 460 } 461 462 static inline void t4_srq_consume_ooo(struct t4_srq *srq) 463 { 464 srq->cidx++; 465 if (srq->cidx == srq->size) 466 srq->cidx = 0; 467 srq->queue[srq->size].status.host_cidx = srq->cidx; 468 srq->ooo_count--; 469 } 470 471 static inline void t4_srq_consume(struct t4_srq *srq) 472 { 473 srq->in_use--; 474 if (++srq->cidx == srq->size) 475 srq->cidx = 0; 476 srq->queue[srq->size].status.host_cidx = srq->cidx; 477 } 478 479 static inline int t4_rqes_posted(struct t4_wq *wq) 480 { 481 return wq->rq.in_use; 482 } 483 484 static inline int t4_rq_empty(struct t4_wq *wq) 485 { 486 return wq->rq.in_use == 0; 487 } 488 489 static inline int t4_rq_full(struct t4_wq *wq) 490 { 491 return wq->rq.in_use == (wq->rq.size - 1); 492 } 493 494 static inline u32 t4_rq_avail(struct t4_wq *wq) 495 { 496 return wq->rq.size - 1 - wq->rq.in_use; 497 } 498 499 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 500 { 501 wq->rq.in_use++; 502 if (++wq->rq.pidx == wq->rq.size) 503 wq->rq.pidx = 0; 504 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 505 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 506 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 507 } 508 509 static inline void t4_rq_consume(struct t4_wq *wq) 510 { 511 wq->rq.in_use--; 512 if (++wq->rq.cidx == wq->rq.size) 513 wq->rq.cidx = 0; 514 } 515 516 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 517 { 518 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 519 } 520 521 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 522 { 523 return wq->rq.size * T4_RQ_NUM_SLOTS; 524 } 525 526 static inline int t4_sq_onchip(struct t4_sq *sq) 527 { 528 return sq->flags & T4_SQ_ONCHIP; 529 } 530 531 static inline int t4_sq_empty(struct t4_wq *wq) 532 { 533 return wq->sq.in_use == 0; 534 } 535 536 static inline int t4_sq_full(struct t4_wq *wq) 537 { 538 return wq->sq.in_use == (wq->sq.size - 1); 539 } 540 541 static inline u32 t4_sq_avail(struct t4_wq *wq) 542 { 543 return wq->sq.size - 1 - wq->sq.in_use; 544 } 545 546 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 547 { 548 wq->sq.in_use++; 549 if (++wq->sq.pidx == wq->sq.size) 550 wq->sq.pidx = 0; 551 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 552 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 553 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 554 } 555 556 static inline void t4_sq_consume(struct t4_wq *wq) 557 { 558 if (wq->sq.cidx == wq->sq.flush_cidx) 559 wq->sq.flush_cidx = -1; 560 wq->sq.in_use--; 561 if (++wq->sq.cidx == wq->sq.size) 562 wq->sq.cidx = 0; 563 } 564 565 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 566 { 567 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 568 } 569 570 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 571 { 572 return wq->sq.size * T4_SQ_NUM_SLOTS; 573 } 574 575 /* This function copies 64 byte coalesced work request to memory 576 * mapped BAR2 space. For coalesced WRs, the SGE fetches data 577 * from the FIFO instead of from Host. 578 */ 579 static inline void pio_copy(u64 __iomem *dst, u64 *src) 580 { 581 int count = 8; 582 583 while (count) { 584 writeq(*src, dst); 585 src++; 586 dst++; 587 count--; 588 } 589 } 590 591 static inline void t4_ring_srq_db(struct t4_srq *srq, u16 inc, u8 len16, 592 union t4_recv_wr *wqe) 593 { 594 /* Flush host queue memory writes. */ 595 wmb(); 596 if (inc == 1 && srq->bar2_qid == 0 && wqe) { 597 pr_debug("%s : WC srq->pidx = %d; len16=%d\n", 598 __func__, srq->pidx, len16); 599 pio_copy(srq->bar2_va + SGE_UDB_WCDOORBELL, (u64 *)wqe); 600 } else { 601 pr_debug("%s: DB srq->pidx = %d; len16=%d\n", 602 __func__, srq->pidx, len16); 603 writel(PIDX_T5_V(inc) | QID_V(srq->bar2_qid), 604 srq->bar2_va + SGE_UDB_KDOORBELL); 605 } 606 /* Flush user doorbell area writes. */ 607 wmb(); 608 } 609 610 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe) 611 { 612 613 /* Flush host queue memory writes. */ 614 wmb(); 615 if (wq->sq.bar2_va) { 616 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 617 pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx); 618 pio_copy((u64 __iomem *) 619 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 620 (u64 *)wqe); 621 } else { 622 pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx); 623 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid), 624 wq->sq.bar2_va + SGE_UDB_KDOORBELL); 625 } 626 627 /* Flush user doorbell area writes. */ 628 wmb(); 629 return; 630 } 631 writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db); 632 } 633 634 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, 635 union t4_recv_wr *wqe) 636 { 637 638 /* Flush host queue memory writes. */ 639 wmb(); 640 if (wq->rq.bar2_va) { 641 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 642 pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx); 643 pio_copy((u64 __iomem *) 644 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL), 645 (void *)wqe); 646 } else { 647 pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx); 648 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid), 649 wq->rq.bar2_va + SGE_UDB_KDOORBELL); 650 } 651 652 /* Flush user doorbell area writes. */ 653 wmb(); 654 return; 655 } 656 writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db); 657 } 658 659 static inline int t4_wq_in_error(struct t4_wq *wq) 660 { 661 return *wq->qp_errp; 662 } 663 664 static inline void t4_set_wq_in_error(struct t4_wq *wq, u32 srqidx) 665 { 666 if (srqidx) 667 *wq->srqidxp = srqidx; 668 *wq->qp_errp = 1; 669 } 670 671 static inline void t4_disable_wq_db(struct t4_wq *wq) 672 { 673 wq->rq.queue[wq->rq.size].status.db_off = 1; 674 } 675 676 static inline void t4_enable_wq_db(struct t4_wq *wq) 677 { 678 wq->rq.queue[wq->rq.size].status.db_off = 0; 679 } 680 681 static inline int t4_wq_db_enabled(struct t4_wq *wq) 682 { 683 return !wq->rq.queue[wq->rq.size].status.db_off; 684 } 685 686 enum t4_cq_flags { 687 CQ_ARMED = 1, 688 }; 689 690 struct t4_cq { 691 struct t4_cqe *queue; 692 dma_addr_t dma_addr; 693 DEFINE_DMA_UNMAP_ADDR(mapping); 694 struct t4_cqe *sw_queue; 695 void __iomem *gts; 696 void __iomem *bar2_va; 697 u64 bar2_pa; 698 u32 bar2_qid; 699 struct c4iw_rdev *rdev; 700 size_t memsize; 701 __be64 bits_type_ts; 702 u32 cqid; 703 u32 qid_mask; 704 int vector; 705 u16 size; /* including status page */ 706 u16 cidx; 707 u16 sw_pidx; 708 u16 sw_cidx; 709 u16 sw_in_use; 710 u16 cidx_inc; 711 u8 gen; 712 u8 error; 713 u8 *qp_errp; 714 unsigned long flags; 715 }; 716 717 static inline void write_gts(struct t4_cq *cq, u32 val) 718 { 719 if (cq->bar2_va) 720 writel(val | INGRESSQID_V(cq->bar2_qid), 721 cq->bar2_va + SGE_UDB_GTS); 722 else 723 writel(val | INGRESSQID_V(cq->cqid), cq->gts); 724 } 725 726 static inline int t4_clear_cq_armed(struct t4_cq *cq) 727 { 728 return test_and_clear_bit(CQ_ARMED, &cq->flags); 729 } 730 731 static inline int t4_arm_cq(struct t4_cq *cq, int se) 732 { 733 u32 val; 734 735 set_bit(CQ_ARMED, &cq->flags); 736 while (cq->cidx_inc > CIDXINC_M) { 737 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7); 738 write_gts(cq, val); 739 cq->cidx_inc -= CIDXINC_M; 740 } 741 val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6); 742 write_gts(cq, val); 743 cq->cidx_inc = 0; 744 return 0; 745 } 746 747 static inline void t4_swcq_produce(struct t4_cq *cq) 748 { 749 cq->sw_in_use++; 750 if (cq->sw_in_use == cq->size) { 751 pr_warn("%s cxgb4 sw cq overflow cqid %u\n", 752 __func__, cq->cqid); 753 cq->error = 1; 754 cq->sw_in_use--; 755 return; 756 } 757 if (++cq->sw_pidx == cq->size) 758 cq->sw_pidx = 0; 759 } 760 761 static inline void t4_swcq_consume(struct t4_cq *cq) 762 { 763 cq->sw_in_use--; 764 if (++cq->sw_cidx == cq->size) 765 cq->sw_cidx = 0; 766 } 767 768 static inline void t4_hwcq_consume(struct t4_cq *cq) 769 { 770 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 771 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) { 772 u32 val; 773 774 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7); 775 write_gts(cq, val); 776 cq->cidx_inc = 0; 777 } 778 if (++cq->cidx == cq->size) { 779 cq->cidx = 0; 780 cq->gen ^= 1; 781 } 782 } 783 784 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 785 { 786 return (CQE_GENBIT(cqe) == cq->gen); 787 } 788 789 static inline int t4_cq_notempty(struct t4_cq *cq) 790 { 791 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]); 792 } 793 794 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 795 { 796 int ret; 797 u16 prev_cidx; 798 799 if (cq->cidx == 0) 800 prev_cidx = cq->size - 1; 801 else 802 prev_cidx = cq->cidx - 1; 803 804 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 805 ret = -EOVERFLOW; 806 cq->error = 1; 807 pr_err("cq overflow cqid %u\n", cq->cqid); 808 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 809 810 /* Ensure CQE is flushed to memory */ 811 rmb(); 812 *cqe = &cq->queue[cq->cidx]; 813 ret = 0; 814 } else 815 ret = -ENODATA; 816 return ret; 817 } 818 819 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 820 { 821 if (cq->sw_in_use == cq->size) { 822 pr_warn("%s cxgb4 sw cq overflow cqid %u\n", 823 __func__, cq->cqid); 824 cq->error = 1; 825 return NULL; 826 } 827 if (cq->sw_in_use) 828 return &cq->sw_queue[cq->sw_cidx]; 829 return NULL; 830 } 831 832 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 833 { 834 int ret = 0; 835 836 if (cq->error) 837 ret = -ENODATA; 838 else if (cq->sw_in_use) 839 *cqe = &cq->sw_queue[cq->sw_cidx]; 840 else 841 ret = t4_next_hw_cqe(cq, cqe); 842 return ret; 843 } 844 845 static inline int t4_cq_in_error(struct t4_cq *cq) 846 { 847 return *cq->qp_errp; 848 } 849 850 static inline void t4_set_cq_in_error(struct t4_cq *cq) 851 { 852 *cq->qp_errp = 1; 853 } 854 #endif 855 856 struct t4_dev_status_page { 857 u8 db_off; 858 u8 write_cmpl_supported; 859 u16 pad2; 860 u32 pad3; 861 u64 qp_start; 862 u64 qp_size; 863 u64 cq_start; 864 u64 cq_size; 865 }; 866