1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 35 #include "iw_cxgb4.h" 36 37 static int db_delay_usecs = 1; 38 module_param(db_delay_usecs, int, 0644); 39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain"); 40 41 static int ocqp_support = 1; 42 module_param(ocqp_support, int, 0644); 43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); 44 45 int db_fc_threshold = 1000; 46 module_param(db_fc_threshold, int, 0644); 47 MODULE_PARM_DESC(db_fc_threshold, 48 "QP count/threshold that triggers" 49 " automatic db flow control mode (default = 1000)"); 50 51 int db_coalescing_threshold; 52 module_param(db_coalescing_threshold, int, 0644); 53 MODULE_PARM_DESC(db_coalescing_threshold, 54 "QP count/threshold that triggers" 55 " disabling db coalescing (default = 0)"); 56 57 static int max_fr_immd = T4_MAX_FR_IMMD; 58 module_param(max_fr_immd, int, 0644); 59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate"); 60 61 static int alloc_ird(struct c4iw_dev *dev, u32 ird) 62 { 63 int ret = 0; 64 65 spin_lock_irq(&dev->lock); 66 if (ird <= dev->avail_ird) 67 dev->avail_ird -= ird; 68 else 69 ret = -ENOMEM; 70 spin_unlock_irq(&dev->lock); 71 72 if (ret) 73 dev_warn(&dev->rdev.lldi.pdev->dev, 74 "device IRD resources exhausted\n"); 75 76 return ret; 77 } 78 79 static void free_ird(struct c4iw_dev *dev, int ird) 80 { 81 spin_lock_irq(&dev->lock); 82 dev->avail_ird += ird; 83 spin_unlock_irq(&dev->lock); 84 } 85 86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 87 { 88 unsigned long flag; 89 spin_lock_irqsave(&qhp->lock, flag); 90 qhp->attr.state = state; 91 spin_unlock_irqrestore(&qhp->lock, flag); 92 } 93 94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 95 { 96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize); 97 } 98 99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 100 { 101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue, 102 pci_unmap_addr(sq, mapping)); 103 } 104 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 106 { 107 if (t4_sq_onchip(sq)) 108 dealloc_oc_sq(rdev, sq); 109 else 110 dealloc_host_sq(rdev, sq); 111 } 112 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 114 { 115 if (!ocqp_support || !ocqp_supported(&rdev->lldi)) 116 return -ENOSYS; 117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); 118 if (!sq->dma_addr) 119 return -ENOMEM; 120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr - 121 rdev->lldi.vr->ocq.start; 122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr - 123 rdev->lldi.vr->ocq.start); 124 sq->flags |= T4_SQ_ONCHIP; 125 return 0; 126 } 127 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 129 { 130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize, 131 &(sq->dma_addr), GFP_KERNEL); 132 if (!sq->queue) 133 return -ENOMEM; 134 sq->phys_addr = virt_to_phys(sq->queue); 135 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 136 return 0; 137 } 138 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user) 140 { 141 int ret = -ENOSYS; 142 if (user) 143 ret = alloc_oc_sq(rdev, sq); 144 if (ret) 145 ret = alloc_host_sq(rdev, sq); 146 return ret; 147 } 148 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 150 struct c4iw_dev_ucontext *uctx) 151 { 152 /* 153 * uP clears EQ contexts when the connection exits rdma mode, 154 * so no need to post a RESET WR for these EQs. 155 */ 156 dma_free_coherent(&(rdev->lldi.pdev->dev), 157 wq->rq.memsize, wq->rq.queue, 158 dma_unmap_addr(&wq->rq, mapping)); 159 dealloc_sq(rdev, &wq->sq); 160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 161 kfree(wq->rq.sw_rq); 162 kfree(wq->sq.sw_sq); 163 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 164 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 165 return 0; 166 } 167 168 /* 169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL, 170 * then this is a user mapping so compute the page-aligned physical address 171 * for mapping. 172 */ 173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 174 enum cxgb4_bar2_qtype qtype, 175 unsigned int *pbar2_qid, u64 *pbar2_pa) 176 { 177 u64 bar2_qoffset; 178 int ret; 179 180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype, 181 pbar2_pa ? 1 : 0, 182 &bar2_qoffset, pbar2_qid); 183 if (ret) 184 return NULL; 185 186 if (pbar2_pa) 187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK; 188 189 if (is_t4(rdev->lldi.adapter_type)) 190 return NULL; 191 192 return rdev->bar2_kva + bar2_qoffset; 193 } 194 195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 196 struct t4_cq *rcq, struct t4_cq *scq, 197 struct c4iw_dev_ucontext *uctx) 198 { 199 int user = (uctx != &rdev->uctx); 200 struct fw_ri_res_wr *res_wr; 201 struct fw_ri_res *res; 202 int wr_len; 203 struct c4iw_wr_wait wr_wait; 204 struct sk_buff *skb; 205 int ret = 0; 206 int eqsize; 207 208 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 209 if (!wq->sq.qid) 210 return -ENOMEM; 211 212 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 213 if (!wq->rq.qid) { 214 ret = -ENOMEM; 215 goto free_sq_qid; 216 } 217 218 if (!user) { 219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 220 GFP_KERNEL); 221 if (!wq->sq.sw_sq) { 222 ret = -ENOMEM; 223 goto free_rq_qid; 224 } 225 226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 227 GFP_KERNEL); 228 if (!wq->rq.sw_rq) { 229 ret = -ENOMEM; 230 goto free_sw_sq; 231 } 232 } 233 234 /* 235 * RQT must be a power of 2 and at least 16 deep. 236 */ 237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16)); 238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 239 if (!wq->rq.rqt_hwaddr) { 240 ret = -ENOMEM; 241 goto free_sw_rq; 242 } 243 244 ret = alloc_sq(rdev, &wq->sq, user); 245 if (ret) 246 goto free_hwaddr; 247 memset(wq->sq.queue, 0, wq->sq.memsize); 248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 249 250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), 251 wq->rq.memsize, &(wq->rq.dma_addr), 252 GFP_KERNEL); 253 if (!wq->rq.queue) { 254 ret = -ENOMEM; 255 goto free_sq; 256 } 257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", 258 __func__, wq->sq.queue, 259 (unsigned long long)virt_to_phys(wq->sq.queue), 260 wq->rq.queue, 261 (unsigned long long)virt_to_phys(wq->rq.queue)); 262 memset(wq->rq.queue, 0, wq->rq.memsize); 263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 264 265 wq->db = rdev->lldi.db_reg; 266 267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, 268 &wq->sq.bar2_qid, 269 user ? &wq->sq.bar2_pa : NULL); 270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, 271 &wq->rq.bar2_qid, 272 user ? &wq->rq.bar2_pa : NULL); 273 274 /* 275 * User mode must have bar2 access. 276 */ 277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) { 278 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n", 279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid); 280 goto free_dma; 281 } 282 283 wq->rdev = rdev; 284 wq->rq.msn = 1; 285 286 /* build fw_ri_res_wr */ 287 wr_len = sizeof *res_wr + 2 * sizeof *res; 288 289 skb = alloc_skb(wr_len, GFP_KERNEL); 290 if (!skb) { 291 ret = -ENOMEM; 292 goto free_dma; 293 } 294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 295 296 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); 297 memset(res_wr, 0, wr_len); 298 res_wr->op_nres = cpu_to_be32( 299 FW_WR_OP_V(FW_RI_RES_WR) | 300 FW_RI_RES_WR_NRES_V(2) | 301 FW_WR_COMPL_F); 302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 303 res_wr->cookie = (uintptr_t)&wr_wait; 304 res = res_wr->res; 305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 306 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 307 308 /* 309 * eqsize is the number of 64B entries plus the status page size. 310 */ 311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 312 rdev->hw_queue.t4_eq_status_entries; 313 314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) | 319 FW_RI_RES_WR_IQID_V(scq->cqid)); 320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 321 FW_RI_RES_WR_DCAEN_V(0) | 322 FW_RI_RES_WR_DCACPU_V(0) | 323 FW_RI_RES_WR_FBMIN_V(2) | 324 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) : 325 FW_RI_RES_WR_FBMAX_V(3)) | 326 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 327 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 328 FW_RI_RES_WR_EQSIZE_V(eqsize)); 329 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 330 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 331 res++; 332 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 333 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 334 335 /* 336 * eqsize is the number of 64B entries plus the status page size. 337 */ 338 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 339 rdev->hw_queue.t4_eq_status_entries; 340 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 341 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 342 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 343 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 344 FW_RI_RES_WR_IQID_V(rcq->cqid)); 345 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 346 FW_RI_RES_WR_DCAEN_V(0) | 347 FW_RI_RES_WR_DCACPU_V(0) | 348 FW_RI_RES_WR_FBMIN_V(2) | 349 FW_RI_RES_WR_FBMAX_V(3) | 350 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 351 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 352 FW_RI_RES_WR_EQSIZE_V(eqsize)); 353 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 354 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 355 356 c4iw_init_wr_wait(&wr_wait); 357 358 ret = c4iw_ofld_send(rdev, skb); 359 if (ret) 360 goto free_dma; 361 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 362 if (ret) 363 goto free_dma; 364 365 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n", 366 __func__, wq->sq.qid, wq->rq.qid, wq->db, 367 wq->sq.bar2_va, wq->rq.bar2_va); 368 369 return 0; 370 free_dma: 371 dma_free_coherent(&(rdev->lldi.pdev->dev), 372 wq->rq.memsize, wq->rq.queue, 373 dma_unmap_addr(&wq->rq, mapping)); 374 free_sq: 375 dealloc_sq(rdev, &wq->sq); 376 free_hwaddr: 377 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 378 free_sw_rq: 379 kfree(wq->rq.sw_rq); 380 free_sw_sq: 381 kfree(wq->sq.sw_sq); 382 free_rq_qid: 383 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 384 free_sq_qid: 385 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 386 return ret; 387 } 388 389 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 390 struct ib_send_wr *wr, int max, u32 *plenp) 391 { 392 u8 *dstp, *srcp; 393 u32 plen = 0; 394 int i; 395 int rem, len; 396 397 dstp = (u8 *)immdp->data; 398 for (i = 0; i < wr->num_sge; i++) { 399 if ((plen + wr->sg_list[i].length) > max) 400 return -EMSGSIZE; 401 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 402 plen += wr->sg_list[i].length; 403 rem = wr->sg_list[i].length; 404 while (rem) { 405 if (dstp == (u8 *)&sq->queue[sq->size]) 406 dstp = (u8 *)sq->queue; 407 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 408 len = rem; 409 else 410 len = (u8 *)&sq->queue[sq->size] - dstp; 411 memcpy(dstp, srcp, len); 412 dstp += len; 413 srcp += len; 414 rem -= len; 415 } 416 } 417 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 418 if (len) 419 memset(dstp, 0, len); 420 immdp->op = FW_RI_DATA_IMMD; 421 immdp->r1 = 0; 422 immdp->r2 = 0; 423 immdp->immdlen = cpu_to_be32(plen); 424 *plenp = plen; 425 return 0; 426 } 427 428 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 429 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 430 int num_sge, u32 *plenp) 431 432 { 433 int i; 434 u32 plen = 0; 435 __be64 *flitp = (__be64 *)isglp->sge; 436 437 for (i = 0; i < num_sge; i++) { 438 if ((plen + sg_list[i].length) < plen) 439 return -EMSGSIZE; 440 plen += sg_list[i].length; 441 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 442 sg_list[i].length); 443 if (++flitp == queue_end) 444 flitp = queue_start; 445 *flitp = cpu_to_be64(sg_list[i].addr); 446 if (++flitp == queue_end) 447 flitp = queue_start; 448 } 449 *flitp = (__force __be64)0; 450 isglp->op = FW_RI_DATA_ISGL; 451 isglp->r1 = 0; 452 isglp->nsge = cpu_to_be16(num_sge); 453 isglp->r2 = 0; 454 if (plenp) 455 *plenp = plen; 456 return 0; 457 } 458 459 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 460 struct ib_send_wr *wr, u8 *len16) 461 { 462 u32 plen; 463 int size; 464 int ret; 465 466 if (wr->num_sge > T4_MAX_SEND_SGE) 467 return -EINVAL; 468 switch (wr->opcode) { 469 case IB_WR_SEND: 470 if (wr->send_flags & IB_SEND_SOLICITED) 471 wqe->send.sendop_pkd = cpu_to_be32( 472 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE)); 473 else 474 wqe->send.sendop_pkd = cpu_to_be32( 475 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND)); 476 wqe->send.stag_inv = 0; 477 break; 478 case IB_WR_SEND_WITH_INV: 479 if (wr->send_flags & IB_SEND_SOLICITED) 480 wqe->send.sendop_pkd = cpu_to_be32( 481 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV)); 482 else 483 wqe->send.sendop_pkd = cpu_to_be32( 484 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV)); 485 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 486 break; 487 488 default: 489 return -EINVAL; 490 } 491 wqe->send.r3 = 0; 492 wqe->send.r4 = 0; 493 494 plen = 0; 495 if (wr->num_sge) { 496 if (wr->send_flags & IB_SEND_INLINE) { 497 ret = build_immd(sq, wqe->send.u.immd_src, wr, 498 T4_MAX_SEND_INLINE, &plen); 499 if (ret) 500 return ret; 501 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 502 plen; 503 } else { 504 ret = build_isgl((__be64 *)sq->queue, 505 (__be64 *)&sq->queue[sq->size], 506 wqe->send.u.isgl_src, 507 wr->sg_list, wr->num_sge, &plen); 508 if (ret) 509 return ret; 510 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 511 wr->num_sge * sizeof(struct fw_ri_sge); 512 } 513 } else { 514 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 515 wqe->send.u.immd_src[0].r1 = 0; 516 wqe->send.u.immd_src[0].r2 = 0; 517 wqe->send.u.immd_src[0].immdlen = 0; 518 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 519 plen = 0; 520 } 521 *len16 = DIV_ROUND_UP(size, 16); 522 wqe->send.plen = cpu_to_be32(plen); 523 return 0; 524 } 525 526 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 527 struct ib_send_wr *wr, u8 *len16) 528 { 529 u32 plen; 530 int size; 531 int ret; 532 533 if (wr->num_sge > T4_MAX_SEND_SGE) 534 return -EINVAL; 535 wqe->write.r2 = 0; 536 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey); 537 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr); 538 if (wr->num_sge) { 539 if (wr->send_flags & IB_SEND_INLINE) { 540 ret = build_immd(sq, wqe->write.u.immd_src, wr, 541 T4_MAX_WRITE_INLINE, &plen); 542 if (ret) 543 return ret; 544 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 545 plen; 546 } else { 547 ret = build_isgl((__be64 *)sq->queue, 548 (__be64 *)&sq->queue[sq->size], 549 wqe->write.u.isgl_src, 550 wr->sg_list, wr->num_sge, &plen); 551 if (ret) 552 return ret; 553 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 554 wr->num_sge * sizeof(struct fw_ri_sge); 555 } 556 } else { 557 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 558 wqe->write.u.immd_src[0].r1 = 0; 559 wqe->write.u.immd_src[0].r2 = 0; 560 wqe->write.u.immd_src[0].immdlen = 0; 561 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 562 plen = 0; 563 } 564 *len16 = DIV_ROUND_UP(size, 16); 565 wqe->write.plen = cpu_to_be32(plen); 566 return 0; 567 } 568 569 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 570 { 571 if (wr->num_sge > 1) 572 return -EINVAL; 573 if (wr->num_sge) { 574 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey); 575 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr 576 >> 32)); 577 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr); 578 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 579 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 580 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 581 >> 32)); 582 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 583 } else { 584 wqe->read.stag_src = cpu_to_be32(2); 585 wqe->read.to_src_hi = 0; 586 wqe->read.to_src_lo = 0; 587 wqe->read.stag_sink = cpu_to_be32(2); 588 wqe->read.plen = 0; 589 wqe->read.to_sink_hi = 0; 590 wqe->read.to_sink_lo = 0; 591 } 592 wqe->read.r2 = 0; 593 wqe->read.r5 = 0; 594 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 595 return 0; 596 } 597 598 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 599 struct ib_recv_wr *wr, u8 *len16) 600 { 601 int ret; 602 603 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 604 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 605 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 606 if (ret) 607 return ret; 608 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 609 wr->num_sge * sizeof(struct fw_ri_sge), 16); 610 return 0; 611 } 612 613 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr, 614 struct ib_reg_wr *wr, struct c4iw_mr *mhp, 615 u8 *len16) 616 { 617 __be64 *p = (__be64 *)fr->pbl; 618 619 fr->r2 = cpu_to_be32(0); 620 fr->stag = cpu_to_be32(mhp->ibmr.rkey); 621 622 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 623 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) | 624 FW_RI_TPTE_STAGSTATE_V(1) | 625 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) | 626 FW_RI_TPTE_PDID_V(mhp->attr.pdid)); 627 fr->tpte.locread_to_qpid = cpu_to_be32( 628 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) | 629 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) | 630 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12)); 631 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V( 632 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3)); 633 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0); 634 fr->tpte.len_hi = cpu_to_be32(0); 635 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length); 636 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 637 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 638 639 p[0] = cpu_to_be64((u64)mhp->mpl[0]); 640 p[1] = cpu_to_be64((u64)mhp->mpl[1]); 641 642 *len16 = DIV_ROUND_UP(sizeof(*fr), 16); 643 } 644 645 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, 646 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16, 647 bool dsgl_supported) 648 { 649 struct fw_ri_immd *imdp; 650 __be64 *p; 651 int i; 652 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32); 653 int rem; 654 655 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl)) 656 return -EINVAL; 657 658 wqe->fr.qpbinde_to_dcacpu = 0; 659 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12; 660 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 661 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access); 662 wqe->fr.len_hi = 0; 663 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length); 664 wqe->fr.stag = cpu_to_be32(wr->key); 665 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 666 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 667 0xffffffff); 668 669 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) { 670 struct fw_ri_dsgl *sglp; 671 672 for (i = 0; i < mhp->mpl_len; i++) 673 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]); 674 675 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 676 sglp->op = FW_RI_DATA_DSGL; 677 sglp->r1 = 0; 678 sglp->nsge = cpu_to_be16(1); 679 sglp->addr0 = cpu_to_be64(mhp->mpl_addr); 680 sglp->len0 = cpu_to_be32(pbllen); 681 682 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); 683 } else { 684 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 685 imdp->op = FW_RI_DATA_IMMD; 686 imdp->r1 = 0; 687 imdp->r2 = 0; 688 imdp->immdlen = cpu_to_be32(pbllen); 689 p = (__be64 *)(imdp + 1); 690 rem = pbllen; 691 for (i = 0; i < mhp->mpl_len; i++) { 692 *p = cpu_to_be64((u64)mhp->mpl[i]); 693 rem -= sizeof(*p); 694 if (++p == (__be64 *)&sq->queue[sq->size]) 695 p = (__be64 *)sq->queue; 696 } 697 BUG_ON(rem < 0); 698 while (rem) { 699 *p = 0; 700 rem -= sizeof(*p); 701 if (++p == (__be64 *)&sq->queue[sq->size]) 702 p = (__be64 *)sq->queue; 703 } 704 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) 705 + pbllen, 16); 706 } 707 return 0; 708 } 709 710 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 711 { 712 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 713 wqe->inv.r2 = 0; 714 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 715 return 0; 716 } 717 718 static void _free_qp(struct kref *kref) 719 { 720 struct c4iw_qp *qhp; 721 722 qhp = container_of(kref, struct c4iw_qp, kref); 723 PDBG("%s qhp %p\n", __func__, qhp); 724 kfree(qhp); 725 } 726 727 void c4iw_qp_add_ref(struct ib_qp *qp) 728 { 729 PDBG("%s ib_qp %p\n", __func__, qp); 730 kref_get(&to_c4iw_qp(qp)->kref); 731 } 732 733 void c4iw_qp_rem_ref(struct ib_qp *qp) 734 { 735 PDBG("%s ib_qp %p\n", __func__, qp); 736 kref_put(&to_c4iw_qp(qp)->kref, _free_qp); 737 } 738 739 static void add_to_fc_list(struct list_head *head, struct list_head *entry) 740 { 741 if (list_empty(entry)) 742 list_add_tail(entry, head); 743 } 744 745 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc) 746 { 747 unsigned long flags; 748 749 spin_lock_irqsave(&qhp->rhp->lock, flags); 750 spin_lock(&qhp->lock); 751 if (qhp->rhp->db_state == NORMAL) 752 t4_ring_sq_db(&qhp->wq, inc, NULL); 753 else { 754 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 755 qhp->wq.sq.wq_pidx_inc += inc; 756 } 757 spin_unlock(&qhp->lock); 758 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 759 return 0; 760 } 761 762 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc) 763 { 764 unsigned long flags; 765 766 spin_lock_irqsave(&qhp->rhp->lock, flags); 767 spin_lock(&qhp->lock); 768 if (qhp->rhp->db_state == NORMAL) 769 t4_ring_rq_db(&qhp->wq, inc, NULL); 770 else { 771 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 772 qhp->wq.rq.wq_pidx_inc += inc; 773 } 774 spin_unlock(&qhp->lock); 775 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 776 return 0; 777 } 778 779 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 780 struct ib_send_wr **bad_wr) 781 { 782 int err = 0; 783 u8 len16 = 0; 784 enum fw_wr_opcodes fw_opcode = 0; 785 enum fw_ri_wr_flags fw_flags; 786 struct c4iw_qp *qhp; 787 union t4_wr *wqe = NULL; 788 u32 num_wrs; 789 struct t4_swsqe *swsqe; 790 unsigned long flag; 791 u16 idx = 0; 792 793 qhp = to_c4iw_qp(ibqp); 794 spin_lock_irqsave(&qhp->lock, flag); 795 if (t4_wq_in_error(&qhp->wq)) { 796 spin_unlock_irqrestore(&qhp->lock, flag); 797 *bad_wr = wr; 798 return -EINVAL; 799 } 800 num_wrs = t4_sq_avail(&qhp->wq); 801 if (num_wrs == 0) { 802 spin_unlock_irqrestore(&qhp->lock, flag); 803 *bad_wr = wr; 804 return -ENOMEM; 805 } 806 while (wr) { 807 if (num_wrs == 0) { 808 err = -ENOMEM; 809 *bad_wr = wr; 810 break; 811 } 812 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 813 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 814 815 fw_flags = 0; 816 if (wr->send_flags & IB_SEND_SOLICITED) 817 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 818 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 819 fw_flags |= FW_RI_COMPLETION_FLAG; 820 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 821 switch (wr->opcode) { 822 case IB_WR_SEND_WITH_INV: 823 case IB_WR_SEND: 824 if (wr->send_flags & IB_SEND_FENCE) 825 fw_flags |= FW_RI_READ_FENCE_FLAG; 826 fw_opcode = FW_RI_SEND_WR; 827 if (wr->opcode == IB_WR_SEND) 828 swsqe->opcode = FW_RI_SEND; 829 else 830 swsqe->opcode = FW_RI_SEND_WITH_INV; 831 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 832 break; 833 case IB_WR_RDMA_WRITE: 834 fw_opcode = FW_RI_RDMA_WRITE_WR; 835 swsqe->opcode = FW_RI_RDMA_WRITE; 836 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 837 break; 838 case IB_WR_RDMA_READ: 839 case IB_WR_RDMA_READ_WITH_INV: 840 fw_opcode = FW_RI_RDMA_READ_WR; 841 swsqe->opcode = FW_RI_READ_REQ; 842 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) { 843 c4iw_invalidate_mr(qhp->rhp, 844 wr->sg_list[0].lkey); 845 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 846 } else { 847 fw_flags = 0; 848 } 849 err = build_rdma_read(wqe, wr, &len16); 850 if (err) 851 break; 852 swsqe->read_len = wr->sg_list[0].length; 853 if (!qhp->wq.sq.oldest_read) 854 qhp->wq.sq.oldest_read = swsqe; 855 break; 856 case IB_WR_REG_MR: { 857 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr); 858 859 swsqe->opcode = FW_RI_FAST_REGISTER; 860 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support && 861 !mhp->attr.state && mhp->mpl_len <= 2) { 862 fw_opcode = FW_RI_FR_NSMR_TPTE_WR; 863 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr), 864 mhp, &len16); 865 } else { 866 fw_opcode = FW_RI_FR_NSMR_WR; 867 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), 868 mhp, &len16, 869 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl); 870 if (err) 871 break; 872 } 873 mhp->attr.state = 1; 874 break; 875 } 876 case IB_WR_LOCAL_INV: 877 if (wr->send_flags & IB_SEND_FENCE) 878 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 879 fw_opcode = FW_RI_INV_LSTAG_WR; 880 swsqe->opcode = FW_RI_LOCAL_INV; 881 err = build_inv_stag(wqe, wr, &len16); 882 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); 883 break; 884 default: 885 PDBG("%s post of type=%d TBD!\n", __func__, 886 wr->opcode); 887 err = -EINVAL; 888 } 889 if (err) { 890 *bad_wr = wr; 891 break; 892 } 893 swsqe->idx = qhp->wq.sq.pidx; 894 swsqe->complete = 0; 895 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 896 qhp->sq_sig_all; 897 swsqe->flushed = 0; 898 swsqe->wr_id = wr->wr_id; 899 if (c4iw_wr_log) { 900 swsqe->sge_ts = cxgb4_read_sge_timestamp( 901 qhp->rhp->rdev.lldi.ports[0]); 902 getnstimeofday(&swsqe->host_ts); 903 } 904 905 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 906 907 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", 908 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 909 swsqe->opcode, swsqe->read_len); 910 wr = wr->next; 911 num_wrs--; 912 t4_sq_produce(&qhp->wq, len16); 913 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 914 } 915 if (!qhp->rhp->rdev.status_page->db_off) { 916 t4_ring_sq_db(&qhp->wq, idx, wqe); 917 spin_unlock_irqrestore(&qhp->lock, flag); 918 } else { 919 spin_unlock_irqrestore(&qhp->lock, flag); 920 ring_kernel_sq_db(qhp, idx); 921 } 922 return err; 923 } 924 925 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 926 struct ib_recv_wr **bad_wr) 927 { 928 int err = 0; 929 struct c4iw_qp *qhp; 930 union t4_recv_wr *wqe = NULL; 931 u32 num_wrs; 932 u8 len16 = 0; 933 unsigned long flag; 934 u16 idx = 0; 935 936 qhp = to_c4iw_qp(ibqp); 937 spin_lock_irqsave(&qhp->lock, flag); 938 if (t4_wq_in_error(&qhp->wq)) { 939 spin_unlock_irqrestore(&qhp->lock, flag); 940 *bad_wr = wr; 941 return -EINVAL; 942 } 943 num_wrs = t4_rq_avail(&qhp->wq); 944 if (num_wrs == 0) { 945 spin_unlock_irqrestore(&qhp->lock, flag); 946 *bad_wr = wr; 947 return -ENOMEM; 948 } 949 while (wr) { 950 if (wr->num_sge > T4_MAX_RECV_SGE) { 951 err = -EINVAL; 952 *bad_wr = wr; 953 break; 954 } 955 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 956 qhp->wq.rq.wq_pidx * 957 T4_EQ_ENTRY_SIZE); 958 if (num_wrs) 959 err = build_rdma_recv(qhp, wqe, wr, &len16); 960 else 961 err = -ENOMEM; 962 if (err) { 963 *bad_wr = wr; 964 break; 965 } 966 967 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 968 if (c4iw_wr_log) { 969 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts = 970 cxgb4_read_sge_timestamp( 971 qhp->rhp->rdev.lldi.ports[0]); 972 getnstimeofday( 973 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts); 974 } 975 976 wqe->recv.opcode = FW_RI_RECV_WR; 977 wqe->recv.r1 = 0; 978 wqe->recv.wrid = qhp->wq.rq.pidx; 979 wqe->recv.r2[0] = 0; 980 wqe->recv.r2[1] = 0; 981 wqe->recv.r2[2] = 0; 982 wqe->recv.len16 = len16; 983 PDBG("%s cookie 0x%llx pidx %u\n", __func__, 984 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 985 t4_rq_produce(&qhp->wq, len16); 986 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 987 wr = wr->next; 988 num_wrs--; 989 } 990 if (!qhp->rhp->rdev.status_page->db_off) { 991 t4_ring_rq_db(&qhp->wq, idx, wqe); 992 spin_unlock_irqrestore(&qhp->lock, flag); 993 } else { 994 spin_unlock_irqrestore(&qhp->lock, flag); 995 ring_kernel_rq_db(qhp, idx); 996 } 997 return err; 998 } 999 1000 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 1001 u8 *ecode) 1002 { 1003 int status; 1004 int tagged; 1005 int opcode; 1006 int rqtype; 1007 int send_inv; 1008 1009 if (!err_cqe) { 1010 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1011 *ecode = 0; 1012 return; 1013 } 1014 1015 status = CQE_STATUS(err_cqe); 1016 opcode = CQE_OPCODE(err_cqe); 1017 rqtype = RQ_TYPE(err_cqe); 1018 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 1019 (opcode == FW_RI_SEND_WITH_SE_INV); 1020 tagged = (opcode == FW_RI_RDMA_WRITE) || 1021 (rqtype && (opcode == FW_RI_READ_RESP)); 1022 1023 switch (status) { 1024 case T4_ERR_STAG: 1025 if (send_inv) { 1026 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1027 *ecode = RDMAP_CANT_INV_STAG; 1028 } else { 1029 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1030 *ecode = RDMAP_INV_STAG; 1031 } 1032 break; 1033 case T4_ERR_PDID: 1034 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1035 if ((opcode == FW_RI_SEND_WITH_INV) || 1036 (opcode == FW_RI_SEND_WITH_SE_INV)) 1037 *ecode = RDMAP_CANT_INV_STAG; 1038 else 1039 *ecode = RDMAP_STAG_NOT_ASSOC; 1040 break; 1041 case T4_ERR_QPID: 1042 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1043 *ecode = RDMAP_STAG_NOT_ASSOC; 1044 break; 1045 case T4_ERR_ACCESS: 1046 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1047 *ecode = RDMAP_ACC_VIOL; 1048 break; 1049 case T4_ERR_WRAP: 1050 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1051 *ecode = RDMAP_TO_WRAP; 1052 break; 1053 case T4_ERR_BOUND: 1054 if (tagged) { 1055 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1056 *ecode = DDPT_BASE_BOUNDS; 1057 } else { 1058 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1059 *ecode = RDMAP_BASE_BOUNDS; 1060 } 1061 break; 1062 case T4_ERR_INVALIDATE_SHARED_MR: 1063 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 1064 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1065 *ecode = RDMAP_CANT_INV_STAG; 1066 break; 1067 case T4_ERR_ECC: 1068 case T4_ERR_ECC_PSTAG: 1069 case T4_ERR_INTERNAL_ERR: 1070 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 1071 *ecode = 0; 1072 break; 1073 case T4_ERR_OUT_OF_RQE: 1074 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1075 *ecode = DDPU_INV_MSN_NOBUF; 1076 break; 1077 case T4_ERR_PBL_ADDR_BOUND: 1078 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1079 *ecode = DDPT_BASE_BOUNDS; 1080 break; 1081 case T4_ERR_CRC: 1082 *layer_type = LAYER_MPA|DDP_LLP; 1083 *ecode = MPA_CRC_ERR; 1084 break; 1085 case T4_ERR_MARKER: 1086 *layer_type = LAYER_MPA|DDP_LLP; 1087 *ecode = MPA_MARKER_ERR; 1088 break; 1089 case T4_ERR_PDU_LEN_ERR: 1090 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1091 *ecode = DDPU_MSG_TOOBIG; 1092 break; 1093 case T4_ERR_DDP_VERSION: 1094 if (tagged) { 1095 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1096 *ecode = DDPT_INV_VERS; 1097 } else { 1098 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1099 *ecode = DDPU_INV_VERS; 1100 } 1101 break; 1102 case T4_ERR_RDMA_VERSION: 1103 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1104 *ecode = RDMAP_INV_VERS; 1105 break; 1106 case T4_ERR_OPCODE: 1107 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1108 *ecode = RDMAP_INV_OPCODE; 1109 break; 1110 case T4_ERR_DDP_QUEUE_NUM: 1111 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1112 *ecode = DDPU_INV_QN; 1113 break; 1114 case T4_ERR_MSN: 1115 case T4_ERR_MSN_GAP: 1116 case T4_ERR_MSN_RANGE: 1117 case T4_ERR_IRD_OVERFLOW: 1118 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1119 *ecode = DDPU_INV_MSN_RANGE; 1120 break; 1121 case T4_ERR_TBIT: 1122 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 1123 *ecode = 0; 1124 break; 1125 case T4_ERR_MO: 1126 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1127 *ecode = DDPU_INV_MO; 1128 break; 1129 default: 1130 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1131 *ecode = 0; 1132 break; 1133 } 1134 } 1135 1136 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 1137 gfp_t gfp) 1138 { 1139 struct fw_ri_wr *wqe; 1140 struct sk_buff *skb; 1141 struct terminate_message *term; 1142 1143 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1144 qhp->ep->hwtid); 1145 1146 skb = skb_dequeue(&qhp->ep->com.ep_skb_list); 1147 if (WARN_ON(!skb)) 1148 return; 1149 1150 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1151 1152 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1153 memset(wqe, 0, sizeof *wqe); 1154 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR)); 1155 wqe->flowid_len16 = cpu_to_be32( 1156 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1157 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1158 1159 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 1160 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 1161 term = (struct terminate_message *)wqe->u.terminate.termmsg; 1162 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 1163 term->layer_etype = qhp->attr.layer_etype; 1164 term->ecode = qhp->attr.ecode; 1165 } else 1166 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 1167 c4iw_ofld_send(&qhp->rhp->rdev, skb); 1168 } 1169 1170 /* 1171 * Assumes qhp lock is held. 1172 */ 1173 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1174 struct c4iw_cq *schp) 1175 { 1176 int count; 1177 int rq_flushed, sq_flushed; 1178 unsigned long flag; 1179 1180 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 1181 1182 /* locking hierarchy: cq lock first, then qp lock. */ 1183 spin_lock_irqsave(&rchp->lock, flag); 1184 spin_lock(&qhp->lock); 1185 1186 if (qhp->wq.flushed) { 1187 spin_unlock(&qhp->lock); 1188 spin_unlock_irqrestore(&rchp->lock, flag); 1189 return; 1190 } 1191 qhp->wq.flushed = 1; 1192 1193 c4iw_flush_hw_cq(rchp); 1194 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1195 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1196 spin_unlock(&qhp->lock); 1197 spin_unlock_irqrestore(&rchp->lock, flag); 1198 1199 /* locking hierarchy: cq lock first, then qp lock. */ 1200 spin_lock_irqsave(&schp->lock, flag); 1201 spin_lock(&qhp->lock); 1202 if (schp != rchp) 1203 c4iw_flush_hw_cq(schp); 1204 sq_flushed = c4iw_flush_sq(qhp); 1205 spin_unlock(&qhp->lock); 1206 spin_unlock_irqrestore(&schp->lock, flag); 1207 1208 if (schp == rchp) { 1209 if (t4_clear_cq_armed(&rchp->cq) && 1210 (rq_flushed || sq_flushed)) { 1211 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1212 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1213 rchp->ibcq.cq_context); 1214 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1215 } 1216 } else { 1217 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { 1218 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1219 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1220 rchp->ibcq.cq_context); 1221 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1222 } 1223 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { 1224 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1225 (*schp->ibcq.comp_handler)(&schp->ibcq, 1226 schp->ibcq.cq_context); 1227 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1228 } 1229 } 1230 } 1231 1232 static void flush_qp(struct c4iw_qp *qhp) 1233 { 1234 struct c4iw_cq *rchp, *schp; 1235 unsigned long flag; 1236 1237 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1238 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1239 1240 t4_set_wq_in_error(&qhp->wq); 1241 if (qhp->ibqp.uobject) { 1242 t4_set_cq_in_error(&rchp->cq); 1243 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1244 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1245 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1246 if (schp != rchp) { 1247 t4_set_cq_in_error(&schp->cq); 1248 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1249 (*schp->ibcq.comp_handler)(&schp->ibcq, 1250 schp->ibcq.cq_context); 1251 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1252 } 1253 return; 1254 } 1255 __flush_qp(qhp, rchp, schp); 1256 } 1257 1258 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1259 struct c4iw_ep *ep) 1260 { 1261 struct fw_ri_wr *wqe; 1262 int ret; 1263 struct sk_buff *skb; 1264 1265 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1266 ep->hwtid); 1267 1268 skb = skb_dequeue(&ep->com.ep_skb_list); 1269 if (WARN_ON(!skb)) 1270 return -ENOMEM; 1271 1272 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); 1273 1274 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1275 memset(wqe, 0, sizeof *wqe); 1276 wqe->op_compl = cpu_to_be32( 1277 FW_WR_OP_V(FW_RI_INIT_WR) | 1278 FW_WR_COMPL_F); 1279 wqe->flowid_len16 = cpu_to_be32( 1280 FW_WR_FLOWID_V(ep->hwtid) | 1281 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1282 wqe->cookie = (uintptr_t)&ep->com.wr_wait; 1283 1284 wqe->u.fini.type = FW_RI_TYPE_FINI; 1285 ret = c4iw_ofld_send(&rhp->rdev, skb); 1286 if (ret) 1287 goto out; 1288 1289 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid, 1290 qhp->wq.sq.qid, __func__); 1291 out: 1292 PDBG("%s ret %d\n", __func__, ret); 1293 return ret; 1294 } 1295 1296 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1297 { 1298 PDBG("%s p2p_type = %d\n", __func__, p2p_type); 1299 memset(&init->u, 0, sizeof init->u); 1300 switch (p2p_type) { 1301 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1302 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1303 init->u.write.stag_sink = cpu_to_be32(1); 1304 init->u.write.to_sink = cpu_to_be64(1); 1305 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1306 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1307 sizeof(struct fw_ri_immd), 1308 16); 1309 break; 1310 case FW_RI_INIT_P2PTYPE_READ_REQ: 1311 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1312 init->u.read.stag_src = cpu_to_be32(1); 1313 init->u.read.to_src_lo = cpu_to_be32(1); 1314 init->u.read.stag_sink = cpu_to_be32(1); 1315 init->u.read.to_sink_lo = cpu_to_be32(1); 1316 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1317 break; 1318 } 1319 } 1320 1321 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1322 { 1323 struct fw_ri_wr *wqe; 1324 int ret; 1325 struct sk_buff *skb; 1326 1327 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp, 1328 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord); 1329 1330 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1331 if (!skb) { 1332 ret = -ENOMEM; 1333 goto out; 1334 } 1335 ret = alloc_ird(rhp, qhp->attr.max_ird); 1336 if (ret) { 1337 qhp->attr.max_ird = 0; 1338 kfree_skb(skb); 1339 goto out; 1340 } 1341 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1342 1343 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1344 memset(wqe, 0, sizeof *wqe); 1345 wqe->op_compl = cpu_to_be32( 1346 FW_WR_OP_V(FW_RI_INIT_WR) | 1347 FW_WR_COMPL_F); 1348 wqe->flowid_len16 = cpu_to_be32( 1349 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1350 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1351 1352 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait; 1353 1354 wqe->u.init.type = FW_RI_TYPE_INIT; 1355 wqe->u.init.mpareqbit_p2ptype = 1356 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) | 1357 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type); 1358 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1359 if (qhp->attr.mpa_attr.recv_marker_enabled) 1360 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1361 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1362 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1363 if (qhp->attr.mpa_attr.crc_enabled) 1364 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1365 1366 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1367 FW_RI_QP_RDMA_WRITE_ENABLE | 1368 FW_RI_QP_BIND_ENABLE; 1369 if (!qhp->ibqp.uobject) 1370 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1371 FW_RI_QP_STAG0_ENABLE; 1372 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1373 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1374 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1375 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1376 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1377 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1378 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1379 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1380 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1381 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq); 1382 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq); 1383 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1384 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1385 rhp->rdev.lldi.vr->rq.start); 1386 if (qhp->attr.mpa_attr.initiator) 1387 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1388 1389 ret = c4iw_ofld_send(&rhp->rdev, skb); 1390 if (ret) 1391 goto err1; 1392 1393 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait, 1394 qhp->ep->hwtid, qhp->wq.sq.qid, __func__); 1395 if (!ret) 1396 goto out; 1397 err1: 1398 free_ird(rhp, qhp->attr.max_ird); 1399 out: 1400 PDBG("%s ret %d\n", __func__, ret); 1401 return ret; 1402 } 1403 1404 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1405 enum c4iw_qp_attr_mask mask, 1406 struct c4iw_qp_attributes *attrs, 1407 int internal) 1408 { 1409 int ret = 0; 1410 struct c4iw_qp_attributes newattr = qhp->attr; 1411 int disconnect = 0; 1412 int terminate = 0; 1413 int abort = 0; 1414 int free = 0; 1415 struct c4iw_ep *ep = NULL; 1416 1417 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__, 1418 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1419 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1420 1421 mutex_lock(&qhp->mutex); 1422 1423 /* Process attr changes if in IDLE */ 1424 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1425 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1426 ret = -EIO; 1427 goto out; 1428 } 1429 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1430 newattr.enable_rdma_read = attrs->enable_rdma_read; 1431 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1432 newattr.enable_rdma_write = attrs->enable_rdma_write; 1433 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1434 newattr.enable_bind = attrs->enable_bind; 1435 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1436 if (attrs->max_ord > c4iw_max_read_depth) { 1437 ret = -EINVAL; 1438 goto out; 1439 } 1440 newattr.max_ord = attrs->max_ord; 1441 } 1442 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1443 if (attrs->max_ird > cur_max_read_depth(rhp)) { 1444 ret = -EINVAL; 1445 goto out; 1446 } 1447 newattr.max_ird = attrs->max_ird; 1448 } 1449 qhp->attr = newattr; 1450 } 1451 1452 if (mask & C4IW_QP_ATTR_SQ_DB) { 1453 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc); 1454 goto out; 1455 } 1456 if (mask & C4IW_QP_ATTR_RQ_DB) { 1457 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc); 1458 goto out; 1459 } 1460 1461 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1462 goto out; 1463 if (qhp->attr.state == attrs->next_state) 1464 goto out; 1465 1466 switch (qhp->attr.state) { 1467 case C4IW_QP_STATE_IDLE: 1468 switch (attrs->next_state) { 1469 case C4IW_QP_STATE_RTS: 1470 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1471 ret = -EINVAL; 1472 goto out; 1473 } 1474 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1475 ret = -EINVAL; 1476 goto out; 1477 } 1478 qhp->attr.mpa_attr = attrs->mpa_attr; 1479 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1480 qhp->ep = qhp->attr.llp_stream_handle; 1481 set_state(qhp, C4IW_QP_STATE_RTS); 1482 1483 /* 1484 * Ref the endpoint here and deref when we 1485 * disassociate the endpoint from the QP. This 1486 * happens in CLOSING->IDLE transition or *->ERROR 1487 * transition. 1488 */ 1489 c4iw_get_ep(&qhp->ep->com); 1490 ret = rdma_init(rhp, qhp); 1491 if (ret) 1492 goto err; 1493 break; 1494 case C4IW_QP_STATE_ERROR: 1495 set_state(qhp, C4IW_QP_STATE_ERROR); 1496 flush_qp(qhp); 1497 break; 1498 default: 1499 ret = -EINVAL; 1500 goto out; 1501 } 1502 break; 1503 case C4IW_QP_STATE_RTS: 1504 switch (attrs->next_state) { 1505 case C4IW_QP_STATE_CLOSING: 1506 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1507 t4_set_wq_in_error(&qhp->wq); 1508 set_state(qhp, C4IW_QP_STATE_CLOSING); 1509 ep = qhp->ep; 1510 if (!internal) { 1511 abort = 0; 1512 disconnect = 1; 1513 c4iw_get_ep(&qhp->ep->com); 1514 } 1515 ret = rdma_fini(rhp, qhp, ep); 1516 if (ret) 1517 goto err; 1518 break; 1519 case C4IW_QP_STATE_TERMINATE: 1520 t4_set_wq_in_error(&qhp->wq); 1521 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1522 qhp->attr.layer_etype = attrs->layer_etype; 1523 qhp->attr.ecode = attrs->ecode; 1524 ep = qhp->ep; 1525 if (!internal) { 1526 c4iw_get_ep(&qhp->ep->com); 1527 terminate = 1; 1528 disconnect = 1; 1529 } else { 1530 terminate = qhp->attr.send_term; 1531 ret = rdma_fini(rhp, qhp, ep); 1532 if (ret) 1533 goto err; 1534 } 1535 break; 1536 case C4IW_QP_STATE_ERROR: 1537 t4_set_wq_in_error(&qhp->wq); 1538 set_state(qhp, C4IW_QP_STATE_ERROR); 1539 if (!internal) { 1540 abort = 1; 1541 disconnect = 1; 1542 ep = qhp->ep; 1543 c4iw_get_ep(&qhp->ep->com); 1544 } 1545 goto err; 1546 break; 1547 default: 1548 ret = -EINVAL; 1549 goto out; 1550 } 1551 break; 1552 case C4IW_QP_STATE_CLOSING: 1553 if (!internal) { 1554 ret = -EINVAL; 1555 goto out; 1556 } 1557 switch (attrs->next_state) { 1558 case C4IW_QP_STATE_IDLE: 1559 flush_qp(qhp); 1560 set_state(qhp, C4IW_QP_STATE_IDLE); 1561 qhp->attr.llp_stream_handle = NULL; 1562 c4iw_put_ep(&qhp->ep->com); 1563 qhp->ep = NULL; 1564 wake_up(&qhp->wait); 1565 break; 1566 case C4IW_QP_STATE_ERROR: 1567 goto err; 1568 default: 1569 ret = -EINVAL; 1570 goto err; 1571 } 1572 break; 1573 case C4IW_QP_STATE_ERROR: 1574 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1575 ret = -EINVAL; 1576 goto out; 1577 } 1578 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1579 ret = -EINVAL; 1580 goto out; 1581 } 1582 set_state(qhp, C4IW_QP_STATE_IDLE); 1583 break; 1584 case C4IW_QP_STATE_TERMINATE: 1585 if (!internal) { 1586 ret = -EINVAL; 1587 goto out; 1588 } 1589 goto err; 1590 break; 1591 default: 1592 printk(KERN_ERR "%s in a bad state %d\n", 1593 __func__, qhp->attr.state); 1594 ret = -EINVAL; 1595 goto err; 1596 break; 1597 } 1598 goto out; 1599 err: 1600 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep, 1601 qhp->wq.sq.qid); 1602 1603 /* disassociate the LLP connection */ 1604 qhp->attr.llp_stream_handle = NULL; 1605 if (!ep) 1606 ep = qhp->ep; 1607 qhp->ep = NULL; 1608 set_state(qhp, C4IW_QP_STATE_ERROR); 1609 free = 1; 1610 abort = 1; 1611 BUG_ON(!ep); 1612 flush_qp(qhp); 1613 wake_up(&qhp->wait); 1614 out: 1615 mutex_unlock(&qhp->mutex); 1616 1617 if (terminate) 1618 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1619 1620 /* 1621 * If disconnect is 1, then we need to initiate a disconnect 1622 * on the EP. This can be a normal close (RTS->CLOSING) or 1623 * an abnormal close (RTS/CLOSING->ERROR). 1624 */ 1625 if (disconnect) { 1626 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1627 GFP_KERNEL); 1628 c4iw_put_ep(&ep->com); 1629 } 1630 1631 /* 1632 * If free is 1, then we've disassociated the EP from the QP 1633 * and we need to dereference the EP. 1634 */ 1635 if (free) 1636 c4iw_put_ep(&ep->com); 1637 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1638 return ret; 1639 } 1640 1641 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1642 { 1643 struct c4iw_dev *rhp; 1644 struct c4iw_qp *qhp; 1645 struct c4iw_qp_attributes attrs; 1646 struct c4iw_ucontext *ucontext; 1647 1648 qhp = to_c4iw_qp(ib_qp); 1649 rhp = qhp->rhp; 1650 1651 attrs.next_state = C4IW_QP_STATE_ERROR; 1652 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1653 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1654 else 1655 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1656 wait_event(qhp->wait, !qhp->ep); 1657 1658 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1659 1660 spin_lock_irq(&rhp->lock); 1661 if (!list_empty(&qhp->db_fc_entry)) 1662 list_del_init(&qhp->db_fc_entry); 1663 spin_unlock_irq(&rhp->lock); 1664 free_ird(rhp, qhp->attr.max_ird); 1665 1666 ucontext = ib_qp->uobject ? 1667 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1668 destroy_qp(&rhp->rdev, &qhp->wq, 1669 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1670 1671 c4iw_qp_rem_ref(ib_qp); 1672 1673 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid); 1674 return 0; 1675 } 1676 1677 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1678 struct ib_udata *udata) 1679 { 1680 struct c4iw_dev *rhp; 1681 struct c4iw_qp *qhp; 1682 struct c4iw_pd *php; 1683 struct c4iw_cq *schp; 1684 struct c4iw_cq *rchp; 1685 struct c4iw_create_qp_resp uresp; 1686 unsigned int sqsize, rqsize; 1687 struct c4iw_ucontext *ucontext; 1688 int ret; 1689 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm; 1690 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL; 1691 1692 PDBG("%s ib_pd %p\n", __func__, pd); 1693 1694 if (attrs->qp_type != IB_QPT_RC) 1695 return ERR_PTR(-EINVAL); 1696 1697 php = to_c4iw_pd(pd); 1698 rhp = php->rhp; 1699 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1700 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1701 if (!schp || !rchp) 1702 return ERR_PTR(-EINVAL); 1703 1704 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1705 return ERR_PTR(-EINVAL); 1706 1707 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size) 1708 return ERR_PTR(-E2BIG); 1709 rqsize = attrs->cap.max_recv_wr + 1; 1710 if (rqsize < 8) 1711 rqsize = 8; 1712 1713 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size) 1714 return ERR_PTR(-E2BIG); 1715 sqsize = attrs->cap.max_send_wr + 1; 1716 if (sqsize < 8) 1717 sqsize = 8; 1718 1719 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1720 1721 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1722 if (!qhp) 1723 return ERR_PTR(-ENOMEM); 1724 qhp->wq.sq.size = sqsize; 1725 qhp->wq.sq.memsize = 1726 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1727 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64); 1728 qhp->wq.sq.flush_cidx = -1; 1729 qhp->wq.rq.size = rqsize; 1730 qhp->wq.rq.memsize = 1731 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1732 sizeof(*qhp->wq.rq.queue); 1733 1734 if (ucontext) { 1735 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1736 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1737 } 1738 1739 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1740 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1741 if (ret) 1742 goto err1; 1743 1744 attrs->cap.max_recv_wr = rqsize - 1; 1745 attrs->cap.max_send_wr = sqsize - 1; 1746 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1747 1748 qhp->rhp = rhp; 1749 qhp->attr.pd = php->pdid; 1750 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1751 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1752 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1753 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1754 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1755 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1756 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1757 qhp->attr.state = C4IW_QP_STATE_IDLE; 1758 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1759 qhp->attr.enable_rdma_read = 1; 1760 qhp->attr.enable_rdma_write = 1; 1761 qhp->attr.enable_bind = 1; 1762 qhp->attr.max_ord = 0; 1763 qhp->attr.max_ird = 0; 1764 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1765 spin_lock_init(&qhp->lock); 1766 init_completion(&qhp->sq_drained); 1767 init_completion(&qhp->rq_drained); 1768 mutex_init(&qhp->mutex); 1769 init_waitqueue_head(&qhp->wait); 1770 kref_init(&qhp->kref); 1771 1772 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1773 if (ret) 1774 goto err2; 1775 1776 if (udata) { 1777 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1778 if (!sq_key_mm) { 1779 ret = -ENOMEM; 1780 goto err3; 1781 } 1782 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1783 if (!rq_key_mm) { 1784 ret = -ENOMEM; 1785 goto err4; 1786 } 1787 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1788 if (!sq_db_key_mm) { 1789 ret = -ENOMEM; 1790 goto err5; 1791 } 1792 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1793 if (!rq_db_key_mm) { 1794 ret = -ENOMEM; 1795 goto err6; 1796 } 1797 if (t4_sq_onchip(&qhp->wq.sq)) { 1798 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm), 1799 GFP_KERNEL); 1800 if (!ma_sync_key_mm) { 1801 ret = -ENOMEM; 1802 goto err7; 1803 } 1804 uresp.flags = C4IW_QPF_ONCHIP; 1805 } else 1806 uresp.flags = 0; 1807 uresp.qid_mask = rhp->rdev.qpmask; 1808 uresp.sqid = qhp->wq.sq.qid; 1809 uresp.sq_size = qhp->wq.sq.size; 1810 uresp.sq_memsize = qhp->wq.sq.memsize; 1811 uresp.rqid = qhp->wq.rq.qid; 1812 uresp.rq_size = qhp->wq.rq.size; 1813 uresp.rq_memsize = qhp->wq.rq.memsize; 1814 spin_lock(&ucontext->mmap_lock); 1815 if (ma_sync_key_mm) { 1816 uresp.ma_sync_key = ucontext->key; 1817 ucontext->key += PAGE_SIZE; 1818 } else { 1819 uresp.ma_sync_key = 0; 1820 } 1821 uresp.sq_key = ucontext->key; 1822 ucontext->key += PAGE_SIZE; 1823 uresp.rq_key = ucontext->key; 1824 ucontext->key += PAGE_SIZE; 1825 uresp.sq_db_gts_key = ucontext->key; 1826 ucontext->key += PAGE_SIZE; 1827 uresp.rq_db_gts_key = ucontext->key; 1828 ucontext->key += PAGE_SIZE; 1829 spin_unlock(&ucontext->mmap_lock); 1830 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1831 if (ret) 1832 goto err8; 1833 sq_key_mm->key = uresp.sq_key; 1834 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1835 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1836 insert_mmap(ucontext, sq_key_mm); 1837 rq_key_mm->key = uresp.rq_key; 1838 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue); 1839 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1840 insert_mmap(ucontext, rq_key_mm); 1841 sq_db_key_mm->key = uresp.sq_db_gts_key; 1842 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa; 1843 sq_db_key_mm->len = PAGE_SIZE; 1844 insert_mmap(ucontext, sq_db_key_mm); 1845 rq_db_key_mm->key = uresp.rq_db_gts_key; 1846 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa; 1847 rq_db_key_mm->len = PAGE_SIZE; 1848 insert_mmap(ucontext, rq_db_key_mm); 1849 if (ma_sync_key_mm) { 1850 ma_sync_key_mm->key = uresp.ma_sync_key; 1851 ma_sync_key_mm->addr = 1852 (pci_resource_start(rhp->rdev.lldi.pdev, 0) + 1853 PCIE_MA_SYNC_A) & PAGE_MASK; 1854 ma_sync_key_mm->len = PAGE_SIZE; 1855 insert_mmap(ucontext, ma_sync_key_mm); 1856 } 1857 } 1858 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1859 init_timer(&(qhp->timer)); 1860 INIT_LIST_HEAD(&qhp->db_fc_entry); 1861 PDBG("%s sq id %u size %u memsize %zu num_entries %u " 1862 "rq id %u size %u memsize %zu num_entries %u\n", __func__, 1863 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize, 1864 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size, 1865 qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1866 return &qhp->ibqp; 1867 err8: 1868 kfree(ma_sync_key_mm); 1869 err7: 1870 kfree(rq_db_key_mm); 1871 err6: 1872 kfree(sq_db_key_mm); 1873 err5: 1874 kfree(rq_key_mm); 1875 err4: 1876 kfree(sq_key_mm); 1877 err3: 1878 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1879 err2: 1880 destroy_qp(&rhp->rdev, &qhp->wq, 1881 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1882 err1: 1883 kfree(qhp); 1884 return ERR_PTR(ret); 1885 } 1886 1887 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1888 int attr_mask, struct ib_udata *udata) 1889 { 1890 struct c4iw_dev *rhp; 1891 struct c4iw_qp *qhp; 1892 enum c4iw_qp_attr_mask mask = 0; 1893 struct c4iw_qp_attributes attrs; 1894 1895 PDBG("%s ib_qp %p\n", __func__, ibqp); 1896 1897 /* iwarp does not support the RTR state */ 1898 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1899 attr_mask &= ~IB_QP_STATE; 1900 1901 /* Make sure we still have something left to do */ 1902 if (!attr_mask) 1903 return 0; 1904 1905 memset(&attrs, 0, sizeof attrs); 1906 qhp = to_c4iw_qp(ibqp); 1907 rhp = qhp->rhp; 1908 1909 attrs.next_state = c4iw_convert_state(attr->qp_state); 1910 attrs.enable_rdma_read = (attr->qp_access_flags & 1911 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1912 attrs.enable_rdma_write = (attr->qp_access_flags & 1913 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1914 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1915 1916 1917 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1918 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1919 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1920 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1921 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1922 1923 /* 1924 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 1925 * ringing the queue db when we're in DB_FULL mode. 1926 * Only allow this on T4 devices. 1927 */ 1928 attrs.sq_db_inc = attr->sq_psn; 1929 attrs.rq_db_inc = attr->rq_psn; 1930 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 1931 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 1932 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) && 1933 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB))) 1934 return -EINVAL; 1935 1936 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1937 } 1938 1939 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1940 { 1941 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn); 1942 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1943 } 1944 1945 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1946 int attr_mask, struct ib_qp_init_attr *init_attr) 1947 { 1948 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1949 1950 memset(attr, 0, sizeof *attr); 1951 memset(init_attr, 0, sizeof *init_attr); 1952 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1953 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1954 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1955 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1956 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1957 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1958 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1959 return 0; 1960 } 1961 1962 static void move_qp_to_err(struct c4iw_qp *qp) 1963 { 1964 struct c4iw_qp_attributes attrs = { .next_state = C4IW_QP_STATE_ERROR }; 1965 1966 (void)c4iw_modify_qp(qp->rhp, qp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1967 } 1968 1969 void c4iw_drain_sq(struct ib_qp *ibqp) 1970 { 1971 struct c4iw_qp *qp = to_c4iw_qp(ibqp); 1972 unsigned long flag; 1973 bool need_to_wait; 1974 1975 move_qp_to_err(qp); 1976 spin_lock_irqsave(&qp->lock, flag); 1977 need_to_wait = !t4_sq_empty(&qp->wq); 1978 spin_unlock_irqrestore(&qp->lock, flag); 1979 1980 if (need_to_wait) 1981 wait_for_completion(&qp->sq_drained); 1982 } 1983 1984 void c4iw_drain_rq(struct ib_qp *ibqp) 1985 { 1986 struct c4iw_qp *qp = to_c4iw_qp(ibqp); 1987 unsigned long flag; 1988 bool need_to_wait; 1989 1990 move_qp_to_err(qp); 1991 spin_lock_irqsave(&qp->lock, flag); 1992 need_to_wait = !t4_rq_empty(&qp->wq); 1993 spin_unlock_irqrestore(&qp->lock, flag); 1994 1995 if (need_to_wait) 1996 wait_for_completion(&qp->rq_drained); 1997 } 1998