1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 35 #include "iw_cxgb4.h" 36 37 static int db_delay_usecs = 1; 38 module_param(db_delay_usecs, int, 0644); 39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain"); 40 41 static int ocqp_support = 1; 42 module_param(ocqp_support, int, 0644); 43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); 44 45 int db_fc_threshold = 1000; 46 module_param(db_fc_threshold, int, 0644); 47 MODULE_PARM_DESC(db_fc_threshold, 48 "QP count/threshold that triggers" 49 " automatic db flow control mode (default = 1000)"); 50 51 int db_coalescing_threshold; 52 module_param(db_coalescing_threshold, int, 0644); 53 MODULE_PARM_DESC(db_coalescing_threshold, 54 "QP count/threshold that triggers" 55 " disabling db coalescing (default = 0)"); 56 57 static int max_fr_immd = T4_MAX_FR_IMMD; 58 module_param(max_fr_immd, int, 0644); 59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate"); 60 61 static int alloc_ird(struct c4iw_dev *dev, u32 ird) 62 { 63 int ret = 0; 64 65 spin_lock_irq(&dev->lock); 66 if (ird <= dev->avail_ird) 67 dev->avail_ird -= ird; 68 else 69 ret = -ENOMEM; 70 spin_unlock_irq(&dev->lock); 71 72 if (ret) 73 dev_warn(&dev->rdev.lldi.pdev->dev, 74 "device IRD resources exhausted\n"); 75 76 return ret; 77 } 78 79 static void free_ird(struct c4iw_dev *dev, int ird) 80 { 81 spin_lock_irq(&dev->lock); 82 dev->avail_ird += ird; 83 spin_unlock_irq(&dev->lock); 84 } 85 86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 87 { 88 unsigned long flag; 89 spin_lock_irqsave(&qhp->lock, flag); 90 qhp->attr.state = state; 91 spin_unlock_irqrestore(&qhp->lock, flag); 92 } 93 94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 95 { 96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize); 97 } 98 99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 100 { 101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue, 102 pci_unmap_addr(sq, mapping)); 103 } 104 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 106 { 107 if (t4_sq_onchip(sq)) 108 dealloc_oc_sq(rdev, sq); 109 else 110 dealloc_host_sq(rdev, sq); 111 } 112 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 114 { 115 if (!ocqp_support || !ocqp_supported(&rdev->lldi)) 116 return -ENOSYS; 117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); 118 if (!sq->dma_addr) 119 return -ENOMEM; 120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr - 121 rdev->lldi.vr->ocq.start; 122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr - 123 rdev->lldi.vr->ocq.start); 124 sq->flags |= T4_SQ_ONCHIP; 125 return 0; 126 } 127 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 129 { 130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize, 131 &(sq->dma_addr), GFP_KERNEL); 132 if (!sq->queue) 133 return -ENOMEM; 134 sq->phys_addr = virt_to_phys(sq->queue); 135 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 136 return 0; 137 } 138 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user) 140 { 141 int ret = -ENOSYS; 142 if (user) 143 ret = alloc_oc_sq(rdev, sq); 144 if (ret) 145 ret = alloc_host_sq(rdev, sq); 146 return ret; 147 } 148 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 150 struct c4iw_dev_ucontext *uctx) 151 { 152 /* 153 * uP clears EQ contexts when the connection exits rdma mode, 154 * so no need to post a RESET WR for these EQs. 155 */ 156 dma_free_coherent(&(rdev->lldi.pdev->dev), 157 wq->rq.memsize, wq->rq.queue, 158 dma_unmap_addr(&wq->rq, mapping)); 159 dealloc_sq(rdev, &wq->sq); 160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 161 kfree(wq->rq.sw_rq); 162 kfree(wq->sq.sw_sq); 163 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 164 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 165 return 0; 166 } 167 168 /* 169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL, 170 * then this is a user mapping so compute the page-aligned physical address 171 * for mapping. 172 */ 173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 174 enum cxgb4_bar2_qtype qtype, 175 unsigned int *pbar2_qid, u64 *pbar2_pa) 176 { 177 u64 bar2_qoffset; 178 int ret; 179 180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype, 181 pbar2_pa ? 1 : 0, 182 &bar2_qoffset, pbar2_qid); 183 if (ret) 184 return NULL; 185 186 if (pbar2_pa) 187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK; 188 189 if (is_t4(rdev->lldi.adapter_type)) 190 return NULL; 191 192 return rdev->bar2_kva + bar2_qoffset; 193 } 194 195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 196 struct t4_cq *rcq, struct t4_cq *scq, 197 struct c4iw_dev_ucontext *uctx, 198 struct c4iw_wr_wait *wr_waitp) 199 { 200 int user = (uctx != &rdev->uctx); 201 struct fw_ri_res_wr *res_wr; 202 struct fw_ri_res *res; 203 int wr_len; 204 struct sk_buff *skb; 205 int ret = 0; 206 int eqsize; 207 208 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 209 if (!wq->sq.qid) 210 return -ENOMEM; 211 212 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 213 if (!wq->rq.qid) { 214 ret = -ENOMEM; 215 goto free_sq_qid; 216 } 217 218 if (!user) { 219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 220 GFP_KERNEL); 221 if (!wq->sq.sw_sq) { 222 ret = -ENOMEM; 223 goto free_rq_qid; 224 } 225 226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 227 GFP_KERNEL); 228 if (!wq->rq.sw_rq) { 229 ret = -ENOMEM; 230 goto free_sw_sq; 231 } 232 } 233 234 /* 235 * RQT must be a power of 2 and at least 16 deep. 236 */ 237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16)); 238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 239 if (!wq->rq.rqt_hwaddr) { 240 ret = -ENOMEM; 241 goto free_sw_rq; 242 } 243 244 ret = alloc_sq(rdev, &wq->sq, user); 245 if (ret) 246 goto free_hwaddr; 247 memset(wq->sq.queue, 0, wq->sq.memsize); 248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 249 250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), 251 wq->rq.memsize, &(wq->rq.dma_addr), 252 GFP_KERNEL); 253 if (!wq->rq.queue) { 254 ret = -ENOMEM; 255 goto free_sq; 256 } 257 pr_debug("sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", 258 wq->sq.queue, 259 (unsigned long long)virt_to_phys(wq->sq.queue), 260 wq->rq.queue, 261 (unsigned long long)virt_to_phys(wq->rq.queue)); 262 memset(wq->rq.queue, 0, wq->rq.memsize); 263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 264 265 wq->db = rdev->lldi.db_reg; 266 267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, 268 &wq->sq.bar2_qid, 269 user ? &wq->sq.bar2_pa : NULL); 270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, 271 &wq->rq.bar2_qid, 272 user ? &wq->rq.bar2_pa : NULL); 273 274 /* 275 * User mode must have bar2 access. 276 */ 277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) { 278 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n", 279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid); 280 goto free_dma; 281 } 282 283 wq->rdev = rdev; 284 wq->rq.msn = 1; 285 286 /* build fw_ri_res_wr */ 287 wr_len = sizeof *res_wr + 2 * sizeof *res; 288 289 skb = alloc_skb(wr_len, GFP_KERNEL); 290 if (!skb) { 291 ret = -ENOMEM; 292 goto free_dma; 293 } 294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 295 296 res_wr = __skb_put_zero(skb, wr_len); 297 res_wr->op_nres = cpu_to_be32( 298 FW_WR_OP_V(FW_RI_RES_WR) | 299 FW_RI_RES_WR_NRES_V(2) | 300 FW_WR_COMPL_F); 301 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 302 res_wr->cookie = (uintptr_t)wr_waitp; 303 res = res_wr->res; 304 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 305 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 306 307 /* 308 * eqsize is the number of 64B entries plus the status page size. 309 */ 310 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 311 rdev->hw_queue.t4_eq_status_entries; 312 313 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 314 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 315 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 316 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 317 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) | 318 FW_RI_RES_WR_IQID_V(scq->cqid)); 319 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 320 FW_RI_RES_WR_DCAEN_V(0) | 321 FW_RI_RES_WR_DCACPU_V(0) | 322 FW_RI_RES_WR_FBMIN_V(2) | 323 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) : 324 FW_RI_RES_WR_FBMAX_V(3)) | 325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 326 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 327 FW_RI_RES_WR_EQSIZE_V(eqsize)); 328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 330 res++; 331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 332 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 333 334 /* 335 * eqsize is the number of 64B entries plus the status page size. 336 */ 337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 338 rdev->hw_queue.t4_eq_status_entries; 339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 343 FW_RI_RES_WR_IQID_V(rcq->cqid)); 344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 345 FW_RI_RES_WR_DCAEN_V(0) | 346 FW_RI_RES_WR_DCACPU_V(0) | 347 FW_RI_RES_WR_FBMIN_V(2) | 348 FW_RI_RES_WR_FBMAX_V(3) | 349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 350 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 351 FW_RI_RES_WR_EQSIZE_V(eqsize)); 352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 354 355 c4iw_init_wr_wait(wr_waitp); 356 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->sq.qid, __func__); 357 if (ret) 358 goto free_dma; 359 360 pr_debug("sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n", 361 wq->sq.qid, wq->rq.qid, wq->db, 362 wq->sq.bar2_va, wq->rq.bar2_va); 363 364 return 0; 365 free_dma: 366 dma_free_coherent(&(rdev->lldi.pdev->dev), 367 wq->rq.memsize, wq->rq.queue, 368 dma_unmap_addr(&wq->rq, mapping)); 369 free_sq: 370 dealloc_sq(rdev, &wq->sq); 371 free_hwaddr: 372 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 373 free_sw_rq: 374 kfree(wq->rq.sw_rq); 375 free_sw_sq: 376 kfree(wq->sq.sw_sq); 377 free_rq_qid: 378 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 379 free_sq_qid: 380 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 381 return ret; 382 } 383 384 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 385 struct ib_send_wr *wr, int max, u32 *plenp) 386 { 387 u8 *dstp, *srcp; 388 u32 plen = 0; 389 int i; 390 int rem, len; 391 392 dstp = (u8 *)immdp->data; 393 for (i = 0; i < wr->num_sge; i++) { 394 if ((plen + wr->sg_list[i].length) > max) 395 return -EMSGSIZE; 396 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 397 plen += wr->sg_list[i].length; 398 rem = wr->sg_list[i].length; 399 while (rem) { 400 if (dstp == (u8 *)&sq->queue[sq->size]) 401 dstp = (u8 *)sq->queue; 402 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 403 len = rem; 404 else 405 len = (u8 *)&sq->queue[sq->size] - dstp; 406 memcpy(dstp, srcp, len); 407 dstp += len; 408 srcp += len; 409 rem -= len; 410 } 411 } 412 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 413 if (len) 414 memset(dstp, 0, len); 415 immdp->op = FW_RI_DATA_IMMD; 416 immdp->r1 = 0; 417 immdp->r2 = 0; 418 immdp->immdlen = cpu_to_be32(plen); 419 *plenp = plen; 420 return 0; 421 } 422 423 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 424 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 425 int num_sge, u32 *plenp) 426 427 { 428 int i; 429 u32 plen = 0; 430 __be64 *flitp = (__be64 *)isglp->sge; 431 432 for (i = 0; i < num_sge; i++) { 433 if ((plen + sg_list[i].length) < plen) 434 return -EMSGSIZE; 435 plen += sg_list[i].length; 436 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 437 sg_list[i].length); 438 if (++flitp == queue_end) 439 flitp = queue_start; 440 *flitp = cpu_to_be64(sg_list[i].addr); 441 if (++flitp == queue_end) 442 flitp = queue_start; 443 } 444 *flitp = (__force __be64)0; 445 isglp->op = FW_RI_DATA_ISGL; 446 isglp->r1 = 0; 447 isglp->nsge = cpu_to_be16(num_sge); 448 isglp->r2 = 0; 449 if (plenp) 450 *plenp = plen; 451 return 0; 452 } 453 454 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 455 struct ib_send_wr *wr, u8 *len16) 456 { 457 u32 plen; 458 int size; 459 int ret; 460 461 if (wr->num_sge > T4_MAX_SEND_SGE) 462 return -EINVAL; 463 switch (wr->opcode) { 464 case IB_WR_SEND: 465 if (wr->send_flags & IB_SEND_SOLICITED) 466 wqe->send.sendop_pkd = cpu_to_be32( 467 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE)); 468 else 469 wqe->send.sendop_pkd = cpu_to_be32( 470 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND)); 471 wqe->send.stag_inv = 0; 472 break; 473 case IB_WR_SEND_WITH_INV: 474 if (wr->send_flags & IB_SEND_SOLICITED) 475 wqe->send.sendop_pkd = cpu_to_be32( 476 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV)); 477 else 478 wqe->send.sendop_pkd = cpu_to_be32( 479 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV)); 480 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 wqe->send.r3 = 0; 487 wqe->send.r4 = 0; 488 489 plen = 0; 490 if (wr->num_sge) { 491 if (wr->send_flags & IB_SEND_INLINE) { 492 ret = build_immd(sq, wqe->send.u.immd_src, wr, 493 T4_MAX_SEND_INLINE, &plen); 494 if (ret) 495 return ret; 496 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 497 plen; 498 } else { 499 ret = build_isgl((__be64 *)sq->queue, 500 (__be64 *)&sq->queue[sq->size], 501 wqe->send.u.isgl_src, 502 wr->sg_list, wr->num_sge, &plen); 503 if (ret) 504 return ret; 505 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 506 wr->num_sge * sizeof(struct fw_ri_sge); 507 } 508 } else { 509 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 510 wqe->send.u.immd_src[0].r1 = 0; 511 wqe->send.u.immd_src[0].r2 = 0; 512 wqe->send.u.immd_src[0].immdlen = 0; 513 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 514 plen = 0; 515 } 516 *len16 = DIV_ROUND_UP(size, 16); 517 wqe->send.plen = cpu_to_be32(plen); 518 return 0; 519 } 520 521 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 522 struct ib_send_wr *wr, u8 *len16) 523 { 524 u32 plen; 525 int size; 526 int ret; 527 528 if (wr->num_sge > T4_MAX_SEND_SGE) 529 return -EINVAL; 530 wqe->write.r2 = 0; 531 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey); 532 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr); 533 if (wr->num_sge) { 534 if (wr->send_flags & IB_SEND_INLINE) { 535 ret = build_immd(sq, wqe->write.u.immd_src, wr, 536 T4_MAX_WRITE_INLINE, &plen); 537 if (ret) 538 return ret; 539 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 540 plen; 541 } else { 542 ret = build_isgl((__be64 *)sq->queue, 543 (__be64 *)&sq->queue[sq->size], 544 wqe->write.u.isgl_src, 545 wr->sg_list, wr->num_sge, &plen); 546 if (ret) 547 return ret; 548 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 549 wr->num_sge * sizeof(struct fw_ri_sge); 550 } 551 } else { 552 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 553 wqe->write.u.immd_src[0].r1 = 0; 554 wqe->write.u.immd_src[0].r2 = 0; 555 wqe->write.u.immd_src[0].immdlen = 0; 556 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 557 plen = 0; 558 } 559 *len16 = DIV_ROUND_UP(size, 16); 560 wqe->write.plen = cpu_to_be32(plen); 561 return 0; 562 } 563 564 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 565 { 566 if (wr->num_sge > 1) 567 return -EINVAL; 568 if (wr->num_sge && wr->sg_list[0].length) { 569 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey); 570 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr 571 >> 32)); 572 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr); 573 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 574 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 575 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 576 >> 32)); 577 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 578 } else { 579 wqe->read.stag_src = cpu_to_be32(2); 580 wqe->read.to_src_hi = 0; 581 wqe->read.to_src_lo = 0; 582 wqe->read.stag_sink = cpu_to_be32(2); 583 wqe->read.plen = 0; 584 wqe->read.to_sink_hi = 0; 585 wqe->read.to_sink_lo = 0; 586 } 587 wqe->read.r2 = 0; 588 wqe->read.r5 = 0; 589 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 590 return 0; 591 } 592 593 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 594 struct ib_recv_wr *wr, u8 *len16) 595 { 596 int ret; 597 598 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 599 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 600 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 601 if (ret) 602 return ret; 603 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 604 wr->num_sge * sizeof(struct fw_ri_sge), 16); 605 return 0; 606 } 607 608 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr, 609 struct ib_reg_wr *wr, struct c4iw_mr *mhp, 610 u8 *len16) 611 { 612 __be64 *p = (__be64 *)fr->pbl; 613 614 fr->r2 = cpu_to_be32(0); 615 fr->stag = cpu_to_be32(mhp->ibmr.rkey); 616 617 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 618 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) | 619 FW_RI_TPTE_STAGSTATE_V(1) | 620 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) | 621 FW_RI_TPTE_PDID_V(mhp->attr.pdid)); 622 fr->tpte.locread_to_qpid = cpu_to_be32( 623 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) | 624 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) | 625 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12)); 626 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V( 627 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3)); 628 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0); 629 fr->tpte.len_hi = cpu_to_be32(0); 630 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length); 631 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 632 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 633 634 p[0] = cpu_to_be64((u64)mhp->mpl[0]); 635 p[1] = cpu_to_be64((u64)mhp->mpl[1]); 636 637 *len16 = DIV_ROUND_UP(sizeof(*fr), 16); 638 } 639 640 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, 641 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16, 642 bool dsgl_supported) 643 { 644 struct fw_ri_immd *imdp; 645 __be64 *p; 646 int i; 647 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32); 648 int rem; 649 650 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl)) 651 return -EINVAL; 652 653 wqe->fr.qpbinde_to_dcacpu = 0; 654 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12; 655 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 656 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access); 657 wqe->fr.len_hi = 0; 658 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length); 659 wqe->fr.stag = cpu_to_be32(wr->key); 660 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 661 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 662 0xffffffff); 663 664 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) { 665 struct fw_ri_dsgl *sglp; 666 667 for (i = 0; i < mhp->mpl_len; i++) 668 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]); 669 670 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 671 sglp->op = FW_RI_DATA_DSGL; 672 sglp->r1 = 0; 673 sglp->nsge = cpu_to_be16(1); 674 sglp->addr0 = cpu_to_be64(mhp->mpl_addr); 675 sglp->len0 = cpu_to_be32(pbllen); 676 677 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); 678 } else { 679 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 680 imdp->op = FW_RI_DATA_IMMD; 681 imdp->r1 = 0; 682 imdp->r2 = 0; 683 imdp->immdlen = cpu_to_be32(pbllen); 684 p = (__be64 *)(imdp + 1); 685 rem = pbllen; 686 for (i = 0; i < mhp->mpl_len; i++) { 687 *p = cpu_to_be64((u64)mhp->mpl[i]); 688 rem -= sizeof(*p); 689 if (++p == (__be64 *)&sq->queue[sq->size]) 690 p = (__be64 *)sq->queue; 691 } 692 while (rem) { 693 *p = 0; 694 rem -= sizeof(*p); 695 if (++p == (__be64 *)&sq->queue[sq->size]) 696 p = (__be64 *)sq->queue; 697 } 698 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) 699 + pbllen, 16); 700 } 701 return 0; 702 } 703 704 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 705 { 706 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 707 wqe->inv.r2 = 0; 708 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 709 return 0; 710 } 711 712 static void free_qp_work(struct work_struct *work) 713 { 714 struct c4iw_ucontext *ucontext; 715 struct c4iw_qp *qhp; 716 struct c4iw_dev *rhp; 717 718 qhp = container_of(work, struct c4iw_qp, free_work); 719 ucontext = qhp->ucontext; 720 rhp = qhp->rhp; 721 722 pr_debug("qhp %p ucontext %p\n", qhp, ucontext); 723 destroy_qp(&rhp->rdev, &qhp->wq, 724 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 725 726 if (ucontext) 727 c4iw_put_ucontext(ucontext); 728 c4iw_put_wr_wait(qhp->wr_waitp); 729 kfree(qhp); 730 } 731 732 static void queue_qp_free(struct kref *kref) 733 { 734 struct c4iw_qp *qhp; 735 736 qhp = container_of(kref, struct c4iw_qp, kref); 737 pr_debug("qhp %p\n", qhp); 738 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work); 739 } 740 741 void c4iw_qp_add_ref(struct ib_qp *qp) 742 { 743 pr_debug("ib_qp %p\n", qp); 744 kref_get(&to_c4iw_qp(qp)->kref); 745 } 746 747 void c4iw_qp_rem_ref(struct ib_qp *qp) 748 { 749 pr_debug("ib_qp %p\n", qp); 750 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free); 751 } 752 753 static void add_to_fc_list(struct list_head *head, struct list_head *entry) 754 { 755 if (list_empty(entry)) 756 list_add_tail(entry, head); 757 } 758 759 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc) 760 { 761 unsigned long flags; 762 763 spin_lock_irqsave(&qhp->rhp->lock, flags); 764 spin_lock(&qhp->lock); 765 if (qhp->rhp->db_state == NORMAL) 766 t4_ring_sq_db(&qhp->wq, inc, NULL); 767 else { 768 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 769 qhp->wq.sq.wq_pidx_inc += inc; 770 } 771 spin_unlock(&qhp->lock); 772 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 773 return 0; 774 } 775 776 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc) 777 { 778 unsigned long flags; 779 780 spin_lock_irqsave(&qhp->rhp->lock, flags); 781 spin_lock(&qhp->lock); 782 if (qhp->rhp->db_state == NORMAL) 783 t4_ring_rq_db(&qhp->wq, inc, NULL); 784 else { 785 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 786 qhp->wq.rq.wq_pidx_inc += inc; 787 } 788 spin_unlock(&qhp->lock); 789 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 790 return 0; 791 } 792 793 static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr) 794 { 795 struct t4_cqe cqe = {}; 796 struct c4iw_cq *schp; 797 unsigned long flag; 798 struct t4_cq *cq; 799 800 schp = to_c4iw_cq(qhp->ibqp.send_cq); 801 cq = &schp->cq; 802 803 cqe.u.drain_cookie = wr->wr_id; 804 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) | 805 CQE_OPCODE_V(C4IW_DRAIN_OPCODE) | 806 CQE_TYPE_V(1) | 807 CQE_SWCQE_V(1) | 808 CQE_QPID_V(qhp->wq.sq.qid)); 809 810 spin_lock_irqsave(&schp->lock, flag); 811 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen)); 812 cq->sw_queue[cq->sw_pidx] = cqe; 813 t4_swcq_produce(cq); 814 spin_unlock_irqrestore(&schp->lock, flag); 815 816 if (t4_clear_cq_armed(&schp->cq)) { 817 spin_lock_irqsave(&schp->comp_handler_lock, flag); 818 (*schp->ibcq.comp_handler)(&schp->ibcq, 819 schp->ibcq.cq_context); 820 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 821 } 822 } 823 824 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr) 825 { 826 struct t4_cqe cqe = {}; 827 struct c4iw_cq *rchp; 828 unsigned long flag; 829 struct t4_cq *cq; 830 831 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 832 cq = &rchp->cq; 833 834 cqe.u.drain_cookie = wr->wr_id; 835 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) | 836 CQE_OPCODE_V(C4IW_DRAIN_OPCODE) | 837 CQE_TYPE_V(0) | 838 CQE_SWCQE_V(1) | 839 CQE_QPID_V(qhp->wq.sq.qid)); 840 841 spin_lock_irqsave(&rchp->lock, flag); 842 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen)); 843 cq->sw_queue[cq->sw_pidx] = cqe; 844 t4_swcq_produce(cq); 845 spin_unlock_irqrestore(&rchp->lock, flag); 846 847 if (t4_clear_cq_armed(&rchp->cq)) { 848 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 849 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 850 rchp->ibcq.cq_context); 851 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 852 } 853 } 854 855 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 856 struct ib_send_wr **bad_wr) 857 { 858 int err = 0; 859 u8 len16 = 0; 860 enum fw_wr_opcodes fw_opcode = 0; 861 enum fw_ri_wr_flags fw_flags; 862 struct c4iw_qp *qhp; 863 union t4_wr *wqe = NULL; 864 u32 num_wrs; 865 struct t4_swsqe *swsqe; 866 unsigned long flag; 867 u16 idx = 0; 868 869 qhp = to_c4iw_qp(ibqp); 870 spin_lock_irqsave(&qhp->lock, flag); 871 if (t4_wq_in_error(&qhp->wq)) { 872 spin_unlock_irqrestore(&qhp->lock, flag); 873 complete_sq_drain_wr(qhp, wr); 874 return err; 875 } 876 num_wrs = t4_sq_avail(&qhp->wq); 877 if (num_wrs == 0) { 878 spin_unlock_irqrestore(&qhp->lock, flag); 879 *bad_wr = wr; 880 return -ENOMEM; 881 } 882 while (wr) { 883 if (num_wrs == 0) { 884 err = -ENOMEM; 885 *bad_wr = wr; 886 break; 887 } 888 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 889 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 890 891 fw_flags = 0; 892 if (wr->send_flags & IB_SEND_SOLICITED) 893 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 894 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 895 fw_flags |= FW_RI_COMPLETION_FLAG; 896 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 897 switch (wr->opcode) { 898 case IB_WR_SEND_WITH_INV: 899 case IB_WR_SEND: 900 if (wr->send_flags & IB_SEND_FENCE) 901 fw_flags |= FW_RI_READ_FENCE_FLAG; 902 fw_opcode = FW_RI_SEND_WR; 903 if (wr->opcode == IB_WR_SEND) 904 swsqe->opcode = FW_RI_SEND; 905 else 906 swsqe->opcode = FW_RI_SEND_WITH_INV; 907 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 908 break; 909 case IB_WR_RDMA_WRITE: 910 fw_opcode = FW_RI_RDMA_WRITE_WR; 911 swsqe->opcode = FW_RI_RDMA_WRITE; 912 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 913 break; 914 case IB_WR_RDMA_READ: 915 case IB_WR_RDMA_READ_WITH_INV: 916 fw_opcode = FW_RI_RDMA_READ_WR; 917 swsqe->opcode = FW_RI_READ_REQ; 918 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) { 919 c4iw_invalidate_mr(qhp->rhp, 920 wr->sg_list[0].lkey); 921 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 922 } else { 923 fw_flags = 0; 924 } 925 err = build_rdma_read(wqe, wr, &len16); 926 if (err) 927 break; 928 swsqe->read_len = wr->sg_list[0].length; 929 if (!qhp->wq.sq.oldest_read) 930 qhp->wq.sq.oldest_read = swsqe; 931 break; 932 case IB_WR_REG_MR: { 933 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr); 934 935 swsqe->opcode = FW_RI_FAST_REGISTER; 936 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support && 937 !mhp->attr.state && mhp->mpl_len <= 2) { 938 fw_opcode = FW_RI_FR_NSMR_TPTE_WR; 939 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr), 940 mhp, &len16); 941 } else { 942 fw_opcode = FW_RI_FR_NSMR_WR; 943 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), 944 mhp, &len16, 945 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl); 946 if (err) 947 break; 948 } 949 mhp->attr.state = 1; 950 break; 951 } 952 case IB_WR_LOCAL_INV: 953 if (wr->send_flags & IB_SEND_FENCE) 954 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 955 fw_opcode = FW_RI_INV_LSTAG_WR; 956 swsqe->opcode = FW_RI_LOCAL_INV; 957 err = build_inv_stag(wqe, wr, &len16); 958 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); 959 break; 960 default: 961 pr_warn("%s post of type=%d TBD!\n", __func__, 962 wr->opcode); 963 err = -EINVAL; 964 } 965 if (err) { 966 *bad_wr = wr; 967 break; 968 } 969 swsqe->idx = qhp->wq.sq.pidx; 970 swsqe->complete = 0; 971 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 972 qhp->sq_sig_all; 973 swsqe->flushed = 0; 974 swsqe->wr_id = wr->wr_id; 975 if (c4iw_wr_log) { 976 swsqe->sge_ts = cxgb4_read_sge_timestamp( 977 qhp->rhp->rdev.lldi.ports[0]); 978 getnstimeofday(&swsqe->host_ts); 979 } 980 981 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 982 983 pr_debug("cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", 984 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 985 swsqe->opcode, swsqe->read_len); 986 wr = wr->next; 987 num_wrs--; 988 t4_sq_produce(&qhp->wq, len16); 989 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 990 } 991 if (!qhp->rhp->rdev.status_page->db_off) { 992 t4_ring_sq_db(&qhp->wq, idx, wqe); 993 spin_unlock_irqrestore(&qhp->lock, flag); 994 } else { 995 spin_unlock_irqrestore(&qhp->lock, flag); 996 ring_kernel_sq_db(qhp, idx); 997 } 998 return err; 999 } 1000 1001 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 1002 struct ib_recv_wr **bad_wr) 1003 { 1004 int err = 0; 1005 struct c4iw_qp *qhp; 1006 union t4_recv_wr *wqe = NULL; 1007 u32 num_wrs; 1008 u8 len16 = 0; 1009 unsigned long flag; 1010 u16 idx = 0; 1011 1012 qhp = to_c4iw_qp(ibqp); 1013 spin_lock_irqsave(&qhp->lock, flag); 1014 if (t4_wq_in_error(&qhp->wq)) { 1015 spin_unlock_irqrestore(&qhp->lock, flag); 1016 complete_rq_drain_wr(qhp, wr); 1017 return err; 1018 } 1019 num_wrs = t4_rq_avail(&qhp->wq); 1020 if (num_wrs == 0) { 1021 spin_unlock_irqrestore(&qhp->lock, flag); 1022 *bad_wr = wr; 1023 return -ENOMEM; 1024 } 1025 while (wr) { 1026 if (wr->num_sge > T4_MAX_RECV_SGE) { 1027 err = -EINVAL; 1028 *bad_wr = wr; 1029 break; 1030 } 1031 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 1032 qhp->wq.rq.wq_pidx * 1033 T4_EQ_ENTRY_SIZE); 1034 if (num_wrs) 1035 err = build_rdma_recv(qhp, wqe, wr, &len16); 1036 else 1037 err = -ENOMEM; 1038 if (err) { 1039 *bad_wr = wr; 1040 break; 1041 } 1042 1043 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 1044 if (c4iw_wr_log) { 1045 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts = 1046 cxgb4_read_sge_timestamp( 1047 qhp->rhp->rdev.lldi.ports[0]); 1048 getnstimeofday( 1049 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts); 1050 } 1051 1052 wqe->recv.opcode = FW_RI_RECV_WR; 1053 wqe->recv.r1 = 0; 1054 wqe->recv.wrid = qhp->wq.rq.pidx; 1055 wqe->recv.r2[0] = 0; 1056 wqe->recv.r2[1] = 0; 1057 wqe->recv.r2[2] = 0; 1058 wqe->recv.len16 = len16; 1059 pr_debug("cookie 0x%llx pidx %u\n", 1060 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx); 1061 t4_rq_produce(&qhp->wq, len16); 1062 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 1063 wr = wr->next; 1064 num_wrs--; 1065 } 1066 if (!qhp->rhp->rdev.status_page->db_off) { 1067 t4_ring_rq_db(&qhp->wq, idx, wqe); 1068 spin_unlock_irqrestore(&qhp->lock, flag); 1069 } else { 1070 spin_unlock_irqrestore(&qhp->lock, flag); 1071 ring_kernel_rq_db(qhp, idx); 1072 } 1073 return err; 1074 } 1075 1076 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 1077 u8 *ecode) 1078 { 1079 int status; 1080 int tagged; 1081 int opcode; 1082 int rqtype; 1083 int send_inv; 1084 1085 if (!err_cqe) { 1086 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1087 *ecode = 0; 1088 return; 1089 } 1090 1091 status = CQE_STATUS(err_cqe); 1092 opcode = CQE_OPCODE(err_cqe); 1093 rqtype = RQ_TYPE(err_cqe); 1094 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 1095 (opcode == FW_RI_SEND_WITH_SE_INV); 1096 tagged = (opcode == FW_RI_RDMA_WRITE) || 1097 (rqtype && (opcode == FW_RI_READ_RESP)); 1098 1099 switch (status) { 1100 case T4_ERR_STAG: 1101 if (send_inv) { 1102 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1103 *ecode = RDMAP_CANT_INV_STAG; 1104 } else { 1105 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1106 *ecode = RDMAP_INV_STAG; 1107 } 1108 break; 1109 case T4_ERR_PDID: 1110 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1111 if ((opcode == FW_RI_SEND_WITH_INV) || 1112 (opcode == FW_RI_SEND_WITH_SE_INV)) 1113 *ecode = RDMAP_CANT_INV_STAG; 1114 else 1115 *ecode = RDMAP_STAG_NOT_ASSOC; 1116 break; 1117 case T4_ERR_QPID: 1118 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1119 *ecode = RDMAP_STAG_NOT_ASSOC; 1120 break; 1121 case T4_ERR_ACCESS: 1122 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1123 *ecode = RDMAP_ACC_VIOL; 1124 break; 1125 case T4_ERR_WRAP: 1126 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1127 *ecode = RDMAP_TO_WRAP; 1128 break; 1129 case T4_ERR_BOUND: 1130 if (tagged) { 1131 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1132 *ecode = DDPT_BASE_BOUNDS; 1133 } else { 1134 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1135 *ecode = RDMAP_BASE_BOUNDS; 1136 } 1137 break; 1138 case T4_ERR_INVALIDATE_SHARED_MR: 1139 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 1140 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1141 *ecode = RDMAP_CANT_INV_STAG; 1142 break; 1143 case T4_ERR_ECC: 1144 case T4_ERR_ECC_PSTAG: 1145 case T4_ERR_INTERNAL_ERR: 1146 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 1147 *ecode = 0; 1148 break; 1149 case T4_ERR_OUT_OF_RQE: 1150 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1151 *ecode = DDPU_INV_MSN_NOBUF; 1152 break; 1153 case T4_ERR_PBL_ADDR_BOUND: 1154 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1155 *ecode = DDPT_BASE_BOUNDS; 1156 break; 1157 case T4_ERR_CRC: 1158 *layer_type = LAYER_MPA|DDP_LLP; 1159 *ecode = MPA_CRC_ERR; 1160 break; 1161 case T4_ERR_MARKER: 1162 *layer_type = LAYER_MPA|DDP_LLP; 1163 *ecode = MPA_MARKER_ERR; 1164 break; 1165 case T4_ERR_PDU_LEN_ERR: 1166 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1167 *ecode = DDPU_MSG_TOOBIG; 1168 break; 1169 case T4_ERR_DDP_VERSION: 1170 if (tagged) { 1171 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1172 *ecode = DDPT_INV_VERS; 1173 } else { 1174 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1175 *ecode = DDPU_INV_VERS; 1176 } 1177 break; 1178 case T4_ERR_RDMA_VERSION: 1179 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1180 *ecode = RDMAP_INV_VERS; 1181 break; 1182 case T4_ERR_OPCODE: 1183 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1184 *ecode = RDMAP_INV_OPCODE; 1185 break; 1186 case T4_ERR_DDP_QUEUE_NUM: 1187 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1188 *ecode = DDPU_INV_QN; 1189 break; 1190 case T4_ERR_MSN: 1191 case T4_ERR_MSN_GAP: 1192 case T4_ERR_MSN_RANGE: 1193 case T4_ERR_IRD_OVERFLOW: 1194 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1195 *ecode = DDPU_INV_MSN_RANGE; 1196 break; 1197 case T4_ERR_TBIT: 1198 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 1199 *ecode = 0; 1200 break; 1201 case T4_ERR_MO: 1202 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1203 *ecode = DDPU_INV_MO; 1204 break; 1205 default: 1206 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1207 *ecode = 0; 1208 break; 1209 } 1210 } 1211 1212 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 1213 gfp_t gfp) 1214 { 1215 struct fw_ri_wr *wqe; 1216 struct sk_buff *skb; 1217 struct terminate_message *term; 1218 1219 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, 1220 qhp->ep->hwtid); 1221 1222 skb = skb_dequeue(&qhp->ep->com.ep_skb_list); 1223 if (WARN_ON(!skb)) 1224 return; 1225 1226 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1227 1228 wqe = __skb_put(skb, sizeof(*wqe)); 1229 memset(wqe, 0, sizeof *wqe); 1230 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR)); 1231 wqe->flowid_len16 = cpu_to_be32( 1232 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1233 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1234 1235 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 1236 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 1237 term = (struct terminate_message *)wqe->u.terminate.termmsg; 1238 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 1239 term->layer_etype = qhp->attr.layer_etype; 1240 term->ecode = qhp->attr.ecode; 1241 } else 1242 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 1243 c4iw_ofld_send(&qhp->rhp->rdev, skb); 1244 } 1245 1246 /* 1247 * Assumes qhp lock is held. 1248 */ 1249 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1250 struct c4iw_cq *schp) 1251 { 1252 int count; 1253 int rq_flushed, sq_flushed; 1254 unsigned long flag; 1255 1256 pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp); 1257 1258 /* locking hierarchy: cqs lock first, then qp lock. */ 1259 spin_lock_irqsave(&rchp->lock, flag); 1260 if (schp != rchp) 1261 spin_lock(&schp->lock); 1262 spin_lock(&qhp->lock); 1263 1264 if (qhp->wq.flushed) { 1265 spin_unlock(&qhp->lock); 1266 if (schp != rchp) 1267 spin_unlock(&schp->lock); 1268 spin_unlock_irqrestore(&rchp->lock, flag); 1269 return; 1270 } 1271 qhp->wq.flushed = 1; 1272 t4_set_wq_in_error(&qhp->wq); 1273 1274 c4iw_flush_hw_cq(rchp); 1275 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1276 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1277 1278 if (schp != rchp) 1279 c4iw_flush_hw_cq(schp); 1280 sq_flushed = c4iw_flush_sq(qhp); 1281 1282 spin_unlock(&qhp->lock); 1283 if (schp != rchp) 1284 spin_unlock(&schp->lock); 1285 spin_unlock_irqrestore(&rchp->lock, flag); 1286 1287 if (schp == rchp) { 1288 if (t4_clear_cq_armed(&rchp->cq) && 1289 (rq_flushed || sq_flushed)) { 1290 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1291 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1292 rchp->ibcq.cq_context); 1293 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1294 } 1295 } else { 1296 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { 1297 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1298 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1299 rchp->ibcq.cq_context); 1300 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1301 } 1302 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { 1303 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1304 (*schp->ibcq.comp_handler)(&schp->ibcq, 1305 schp->ibcq.cq_context); 1306 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1307 } 1308 } 1309 } 1310 1311 static void flush_qp(struct c4iw_qp *qhp) 1312 { 1313 struct c4iw_cq *rchp, *schp; 1314 unsigned long flag; 1315 1316 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1317 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1318 1319 if (qhp->ibqp.uobject) { 1320 t4_set_wq_in_error(&qhp->wq); 1321 t4_set_cq_in_error(&rchp->cq); 1322 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1323 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1324 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1325 if (schp != rchp) { 1326 t4_set_cq_in_error(&schp->cq); 1327 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1328 (*schp->ibcq.comp_handler)(&schp->ibcq, 1329 schp->ibcq.cq_context); 1330 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1331 } 1332 return; 1333 } 1334 __flush_qp(qhp, rchp, schp); 1335 } 1336 1337 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1338 struct c4iw_ep *ep) 1339 { 1340 struct fw_ri_wr *wqe; 1341 int ret; 1342 struct sk_buff *skb; 1343 1344 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, ep->hwtid); 1345 1346 skb = skb_dequeue(&ep->com.ep_skb_list); 1347 if (WARN_ON(!skb)) 1348 return -ENOMEM; 1349 1350 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); 1351 1352 wqe = __skb_put(skb, sizeof(*wqe)); 1353 memset(wqe, 0, sizeof *wqe); 1354 wqe->op_compl = cpu_to_be32( 1355 FW_WR_OP_V(FW_RI_INIT_WR) | 1356 FW_WR_COMPL_F); 1357 wqe->flowid_len16 = cpu_to_be32( 1358 FW_WR_FLOWID_V(ep->hwtid) | 1359 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1360 wqe->cookie = (uintptr_t)ep->com.wr_waitp; 1361 1362 wqe->u.fini.type = FW_RI_TYPE_FINI; 1363 1364 ret = c4iw_ref_send_wait(&rhp->rdev, skb, ep->com.wr_waitp, 1365 qhp->ep->hwtid, qhp->wq.sq.qid, __func__); 1366 1367 pr_debug("ret %d\n", ret); 1368 return ret; 1369 } 1370 1371 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1372 { 1373 pr_debug("p2p_type = %d\n", p2p_type); 1374 memset(&init->u, 0, sizeof init->u); 1375 switch (p2p_type) { 1376 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1377 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1378 init->u.write.stag_sink = cpu_to_be32(1); 1379 init->u.write.to_sink = cpu_to_be64(1); 1380 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1381 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1382 sizeof(struct fw_ri_immd), 1383 16); 1384 break; 1385 case FW_RI_INIT_P2PTYPE_READ_REQ: 1386 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1387 init->u.read.stag_src = cpu_to_be32(1); 1388 init->u.read.to_src_lo = cpu_to_be32(1); 1389 init->u.read.stag_sink = cpu_to_be32(1); 1390 init->u.read.to_sink_lo = cpu_to_be32(1); 1391 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1392 break; 1393 } 1394 } 1395 1396 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1397 { 1398 struct fw_ri_wr *wqe; 1399 int ret; 1400 struct sk_buff *skb; 1401 1402 pr_debug("qhp %p qid 0x%x tid %u ird %u ord %u\n", qhp, 1403 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord); 1404 1405 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1406 if (!skb) { 1407 ret = -ENOMEM; 1408 goto out; 1409 } 1410 ret = alloc_ird(rhp, qhp->attr.max_ird); 1411 if (ret) { 1412 qhp->attr.max_ird = 0; 1413 kfree_skb(skb); 1414 goto out; 1415 } 1416 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1417 1418 wqe = __skb_put(skb, sizeof(*wqe)); 1419 memset(wqe, 0, sizeof *wqe); 1420 wqe->op_compl = cpu_to_be32( 1421 FW_WR_OP_V(FW_RI_INIT_WR) | 1422 FW_WR_COMPL_F); 1423 wqe->flowid_len16 = cpu_to_be32( 1424 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1425 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1426 1427 wqe->cookie = (uintptr_t)qhp->ep->com.wr_waitp; 1428 1429 wqe->u.init.type = FW_RI_TYPE_INIT; 1430 wqe->u.init.mpareqbit_p2ptype = 1431 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) | 1432 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type); 1433 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1434 if (qhp->attr.mpa_attr.recv_marker_enabled) 1435 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1436 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1437 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1438 if (qhp->attr.mpa_attr.crc_enabled) 1439 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1440 1441 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1442 FW_RI_QP_RDMA_WRITE_ENABLE | 1443 FW_RI_QP_BIND_ENABLE; 1444 if (!qhp->ibqp.uobject) 1445 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1446 FW_RI_QP_STAG0_ENABLE; 1447 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1448 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1449 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1450 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1451 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1452 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1453 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1454 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1455 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1456 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq); 1457 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq); 1458 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1459 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1460 rhp->rdev.lldi.vr->rq.start); 1461 if (qhp->attr.mpa_attr.initiator) 1462 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1463 1464 ret = c4iw_ref_send_wait(&rhp->rdev, skb, qhp->ep->com.wr_waitp, 1465 qhp->ep->hwtid, qhp->wq.sq.qid, __func__); 1466 if (!ret) 1467 goto out; 1468 1469 free_ird(rhp, qhp->attr.max_ird); 1470 out: 1471 pr_debug("ret %d\n", ret); 1472 return ret; 1473 } 1474 1475 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1476 enum c4iw_qp_attr_mask mask, 1477 struct c4iw_qp_attributes *attrs, 1478 int internal) 1479 { 1480 int ret = 0; 1481 struct c4iw_qp_attributes newattr = qhp->attr; 1482 int disconnect = 0; 1483 int terminate = 0; 1484 int abort = 0; 1485 int free = 0; 1486 struct c4iw_ep *ep = NULL; 1487 1488 pr_debug("qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", 1489 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1490 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1491 1492 mutex_lock(&qhp->mutex); 1493 1494 /* Process attr changes if in IDLE */ 1495 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1496 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1497 ret = -EIO; 1498 goto out; 1499 } 1500 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1501 newattr.enable_rdma_read = attrs->enable_rdma_read; 1502 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1503 newattr.enable_rdma_write = attrs->enable_rdma_write; 1504 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1505 newattr.enable_bind = attrs->enable_bind; 1506 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1507 if (attrs->max_ord > c4iw_max_read_depth) { 1508 ret = -EINVAL; 1509 goto out; 1510 } 1511 newattr.max_ord = attrs->max_ord; 1512 } 1513 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1514 if (attrs->max_ird > cur_max_read_depth(rhp)) { 1515 ret = -EINVAL; 1516 goto out; 1517 } 1518 newattr.max_ird = attrs->max_ird; 1519 } 1520 qhp->attr = newattr; 1521 } 1522 1523 if (mask & C4IW_QP_ATTR_SQ_DB) { 1524 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc); 1525 goto out; 1526 } 1527 if (mask & C4IW_QP_ATTR_RQ_DB) { 1528 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc); 1529 goto out; 1530 } 1531 1532 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1533 goto out; 1534 if (qhp->attr.state == attrs->next_state) 1535 goto out; 1536 1537 switch (qhp->attr.state) { 1538 case C4IW_QP_STATE_IDLE: 1539 switch (attrs->next_state) { 1540 case C4IW_QP_STATE_RTS: 1541 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1542 ret = -EINVAL; 1543 goto out; 1544 } 1545 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1546 ret = -EINVAL; 1547 goto out; 1548 } 1549 qhp->attr.mpa_attr = attrs->mpa_attr; 1550 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1551 qhp->ep = qhp->attr.llp_stream_handle; 1552 set_state(qhp, C4IW_QP_STATE_RTS); 1553 1554 /* 1555 * Ref the endpoint here and deref when we 1556 * disassociate the endpoint from the QP. This 1557 * happens in CLOSING->IDLE transition or *->ERROR 1558 * transition. 1559 */ 1560 c4iw_get_ep(&qhp->ep->com); 1561 ret = rdma_init(rhp, qhp); 1562 if (ret) 1563 goto err; 1564 break; 1565 case C4IW_QP_STATE_ERROR: 1566 set_state(qhp, C4IW_QP_STATE_ERROR); 1567 flush_qp(qhp); 1568 break; 1569 default: 1570 ret = -EINVAL; 1571 goto out; 1572 } 1573 break; 1574 case C4IW_QP_STATE_RTS: 1575 switch (attrs->next_state) { 1576 case C4IW_QP_STATE_CLOSING: 1577 t4_set_wq_in_error(&qhp->wq); 1578 set_state(qhp, C4IW_QP_STATE_CLOSING); 1579 ep = qhp->ep; 1580 if (!internal) { 1581 abort = 0; 1582 disconnect = 1; 1583 c4iw_get_ep(&qhp->ep->com); 1584 } 1585 ret = rdma_fini(rhp, qhp, ep); 1586 if (ret) 1587 goto err; 1588 break; 1589 case C4IW_QP_STATE_TERMINATE: 1590 t4_set_wq_in_error(&qhp->wq); 1591 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1592 qhp->attr.layer_etype = attrs->layer_etype; 1593 qhp->attr.ecode = attrs->ecode; 1594 ep = qhp->ep; 1595 if (!internal) { 1596 c4iw_get_ep(&qhp->ep->com); 1597 terminate = 1; 1598 disconnect = 1; 1599 } else { 1600 terminate = qhp->attr.send_term; 1601 ret = rdma_fini(rhp, qhp, ep); 1602 if (ret) 1603 goto err; 1604 } 1605 break; 1606 case C4IW_QP_STATE_ERROR: 1607 t4_set_wq_in_error(&qhp->wq); 1608 set_state(qhp, C4IW_QP_STATE_ERROR); 1609 if (!internal) { 1610 abort = 1; 1611 disconnect = 1; 1612 ep = qhp->ep; 1613 c4iw_get_ep(&qhp->ep->com); 1614 } 1615 goto err; 1616 break; 1617 default: 1618 ret = -EINVAL; 1619 goto out; 1620 } 1621 break; 1622 case C4IW_QP_STATE_CLOSING: 1623 1624 /* 1625 * Allow kernel users to move to ERROR for qp draining. 1626 */ 1627 if (!internal && (qhp->ibqp.uobject || attrs->next_state != 1628 C4IW_QP_STATE_ERROR)) { 1629 ret = -EINVAL; 1630 goto out; 1631 } 1632 switch (attrs->next_state) { 1633 case C4IW_QP_STATE_IDLE: 1634 flush_qp(qhp); 1635 set_state(qhp, C4IW_QP_STATE_IDLE); 1636 qhp->attr.llp_stream_handle = NULL; 1637 c4iw_put_ep(&qhp->ep->com); 1638 qhp->ep = NULL; 1639 wake_up(&qhp->wait); 1640 break; 1641 case C4IW_QP_STATE_ERROR: 1642 goto err; 1643 default: 1644 ret = -EINVAL; 1645 goto err; 1646 } 1647 break; 1648 case C4IW_QP_STATE_ERROR: 1649 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1650 ret = -EINVAL; 1651 goto out; 1652 } 1653 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1654 ret = -EINVAL; 1655 goto out; 1656 } 1657 set_state(qhp, C4IW_QP_STATE_IDLE); 1658 break; 1659 case C4IW_QP_STATE_TERMINATE: 1660 if (!internal) { 1661 ret = -EINVAL; 1662 goto out; 1663 } 1664 goto err; 1665 break; 1666 default: 1667 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state); 1668 ret = -EINVAL; 1669 goto err; 1670 break; 1671 } 1672 goto out; 1673 err: 1674 pr_debug("disassociating ep %p qpid 0x%x\n", qhp->ep, 1675 qhp->wq.sq.qid); 1676 1677 /* disassociate the LLP connection */ 1678 qhp->attr.llp_stream_handle = NULL; 1679 if (!ep) 1680 ep = qhp->ep; 1681 qhp->ep = NULL; 1682 set_state(qhp, C4IW_QP_STATE_ERROR); 1683 free = 1; 1684 abort = 1; 1685 flush_qp(qhp); 1686 wake_up(&qhp->wait); 1687 out: 1688 mutex_unlock(&qhp->mutex); 1689 1690 if (terminate) 1691 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1692 1693 /* 1694 * If disconnect is 1, then we need to initiate a disconnect 1695 * on the EP. This can be a normal close (RTS->CLOSING) or 1696 * an abnormal close (RTS/CLOSING->ERROR). 1697 */ 1698 if (disconnect) { 1699 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1700 GFP_KERNEL); 1701 c4iw_put_ep(&ep->com); 1702 } 1703 1704 /* 1705 * If free is 1, then we've disassociated the EP from the QP 1706 * and we need to dereference the EP. 1707 */ 1708 if (free) 1709 c4iw_put_ep(&ep->com); 1710 pr_debug("exit state %d\n", qhp->attr.state); 1711 return ret; 1712 } 1713 1714 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1715 { 1716 struct c4iw_dev *rhp; 1717 struct c4iw_qp *qhp; 1718 struct c4iw_qp_attributes attrs; 1719 1720 qhp = to_c4iw_qp(ib_qp); 1721 rhp = qhp->rhp; 1722 1723 attrs.next_state = C4IW_QP_STATE_ERROR; 1724 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1725 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1726 else 1727 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1728 wait_event(qhp->wait, !qhp->ep); 1729 1730 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1731 1732 spin_lock_irq(&rhp->lock); 1733 if (!list_empty(&qhp->db_fc_entry)) 1734 list_del_init(&qhp->db_fc_entry); 1735 spin_unlock_irq(&rhp->lock); 1736 free_ird(rhp, qhp->attr.max_ird); 1737 1738 c4iw_qp_rem_ref(ib_qp); 1739 1740 pr_debug("ib_qp %p qpid 0x%0x\n", ib_qp, qhp->wq.sq.qid); 1741 return 0; 1742 } 1743 1744 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1745 struct ib_udata *udata) 1746 { 1747 struct c4iw_dev *rhp; 1748 struct c4iw_qp *qhp; 1749 struct c4iw_pd *php; 1750 struct c4iw_cq *schp; 1751 struct c4iw_cq *rchp; 1752 struct c4iw_create_qp_resp uresp; 1753 unsigned int sqsize, rqsize; 1754 struct c4iw_ucontext *ucontext; 1755 int ret; 1756 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm; 1757 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL; 1758 1759 pr_debug("ib_pd %p\n", pd); 1760 1761 if (attrs->qp_type != IB_QPT_RC) 1762 return ERR_PTR(-EINVAL); 1763 1764 php = to_c4iw_pd(pd); 1765 rhp = php->rhp; 1766 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1767 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1768 if (!schp || !rchp) 1769 return ERR_PTR(-EINVAL); 1770 1771 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1772 return ERR_PTR(-EINVAL); 1773 1774 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size) 1775 return ERR_PTR(-E2BIG); 1776 rqsize = attrs->cap.max_recv_wr + 1; 1777 if (rqsize < 8) 1778 rqsize = 8; 1779 1780 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size) 1781 return ERR_PTR(-E2BIG); 1782 sqsize = attrs->cap.max_send_wr + 1; 1783 if (sqsize < 8) 1784 sqsize = 8; 1785 1786 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1787 1788 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1789 if (!qhp) 1790 return ERR_PTR(-ENOMEM); 1791 1792 qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL); 1793 if (!qhp->wr_waitp) { 1794 ret = -ENOMEM; 1795 goto err_free_qhp; 1796 } 1797 1798 qhp->wq.sq.size = sqsize; 1799 qhp->wq.sq.memsize = 1800 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1801 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64); 1802 qhp->wq.sq.flush_cidx = -1; 1803 qhp->wq.rq.size = rqsize; 1804 qhp->wq.rq.memsize = 1805 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1806 sizeof(*qhp->wq.rq.queue); 1807 1808 if (ucontext) { 1809 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1810 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1811 } 1812 1813 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1814 ucontext ? &ucontext->uctx : &rhp->rdev.uctx, 1815 qhp->wr_waitp); 1816 if (ret) 1817 goto err_free_wr_wait; 1818 1819 attrs->cap.max_recv_wr = rqsize - 1; 1820 attrs->cap.max_send_wr = sqsize - 1; 1821 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1822 1823 qhp->rhp = rhp; 1824 qhp->attr.pd = php->pdid; 1825 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1826 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1827 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1828 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1829 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1830 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1831 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1832 qhp->attr.state = C4IW_QP_STATE_IDLE; 1833 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1834 qhp->attr.enable_rdma_read = 1; 1835 qhp->attr.enable_rdma_write = 1; 1836 qhp->attr.enable_bind = 1; 1837 qhp->attr.max_ord = 0; 1838 qhp->attr.max_ird = 0; 1839 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1840 spin_lock_init(&qhp->lock); 1841 mutex_init(&qhp->mutex); 1842 init_waitqueue_head(&qhp->wait); 1843 kref_init(&qhp->kref); 1844 INIT_WORK(&qhp->free_work, free_qp_work); 1845 1846 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1847 if (ret) 1848 goto err_destroy_qp; 1849 1850 if (udata && ucontext) { 1851 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1852 if (!sq_key_mm) { 1853 ret = -ENOMEM; 1854 goto err_remove_handle; 1855 } 1856 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1857 if (!rq_key_mm) { 1858 ret = -ENOMEM; 1859 goto err_free_sq_key; 1860 } 1861 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1862 if (!sq_db_key_mm) { 1863 ret = -ENOMEM; 1864 goto err_free_rq_key; 1865 } 1866 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1867 if (!rq_db_key_mm) { 1868 ret = -ENOMEM; 1869 goto err_free_sq_db_key; 1870 } 1871 if (t4_sq_onchip(&qhp->wq.sq)) { 1872 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm), 1873 GFP_KERNEL); 1874 if (!ma_sync_key_mm) { 1875 ret = -ENOMEM; 1876 goto err_free_rq_db_key; 1877 } 1878 uresp.flags = C4IW_QPF_ONCHIP; 1879 } else 1880 uresp.flags = 0; 1881 uresp.qid_mask = rhp->rdev.qpmask; 1882 uresp.sqid = qhp->wq.sq.qid; 1883 uresp.sq_size = qhp->wq.sq.size; 1884 uresp.sq_memsize = qhp->wq.sq.memsize; 1885 uresp.rqid = qhp->wq.rq.qid; 1886 uresp.rq_size = qhp->wq.rq.size; 1887 uresp.rq_memsize = qhp->wq.rq.memsize; 1888 spin_lock(&ucontext->mmap_lock); 1889 if (ma_sync_key_mm) { 1890 uresp.ma_sync_key = ucontext->key; 1891 ucontext->key += PAGE_SIZE; 1892 } else { 1893 uresp.ma_sync_key = 0; 1894 } 1895 uresp.sq_key = ucontext->key; 1896 ucontext->key += PAGE_SIZE; 1897 uresp.rq_key = ucontext->key; 1898 ucontext->key += PAGE_SIZE; 1899 uresp.sq_db_gts_key = ucontext->key; 1900 ucontext->key += PAGE_SIZE; 1901 uresp.rq_db_gts_key = ucontext->key; 1902 ucontext->key += PAGE_SIZE; 1903 spin_unlock(&ucontext->mmap_lock); 1904 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1905 if (ret) 1906 goto err_free_ma_sync_key; 1907 sq_key_mm->key = uresp.sq_key; 1908 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1909 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1910 insert_mmap(ucontext, sq_key_mm); 1911 rq_key_mm->key = uresp.rq_key; 1912 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue); 1913 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1914 insert_mmap(ucontext, rq_key_mm); 1915 sq_db_key_mm->key = uresp.sq_db_gts_key; 1916 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa; 1917 sq_db_key_mm->len = PAGE_SIZE; 1918 insert_mmap(ucontext, sq_db_key_mm); 1919 rq_db_key_mm->key = uresp.rq_db_gts_key; 1920 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa; 1921 rq_db_key_mm->len = PAGE_SIZE; 1922 insert_mmap(ucontext, rq_db_key_mm); 1923 if (ma_sync_key_mm) { 1924 ma_sync_key_mm->key = uresp.ma_sync_key; 1925 ma_sync_key_mm->addr = 1926 (pci_resource_start(rhp->rdev.lldi.pdev, 0) + 1927 PCIE_MA_SYNC_A) & PAGE_MASK; 1928 ma_sync_key_mm->len = PAGE_SIZE; 1929 insert_mmap(ucontext, ma_sync_key_mm); 1930 } 1931 1932 c4iw_get_ucontext(ucontext); 1933 qhp->ucontext = ucontext; 1934 } 1935 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1936 INIT_LIST_HEAD(&qhp->db_fc_entry); 1937 pr_debug("sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n", 1938 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize, 1939 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size, 1940 qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1941 return &qhp->ibqp; 1942 err_free_ma_sync_key: 1943 kfree(ma_sync_key_mm); 1944 err_free_rq_db_key: 1945 kfree(rq_db_key_mm); 1946 err_free_sq_db_key: 1947 kfree(sq_db_key_mm); 1948 err_free_rq_key: 1949 kfree(rq_key_mm); 1950 err_free_sq_key: 1951 kfree(sq_key_mm); 1952 err_remove_handle: 1953 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1954 err_destroy_qp: 1955 destroy_qp(&rhp->rdev, &qhp->wq, 1956 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1957 err_free_wr_wait: 1958 c4iw_put_wr_wait(qhp->wr_waitp); 1959 err_free_qhp: 1960 kfree(qhp); 1961 return ERR_PTR(ret); 1962 } 1963 1964 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1965 int attr_mask, struct ib_udata *udata) 1966 { 1967 struct c4iw_dev *rhp; 1968 struct c4iw_qp *qhp; 1969 enum c4iw_qp_attr_mask mask = 0; 1970 struct c4iw_qp_attributes attrs; 1971 1972 pr_debug("ib_qp %p\n", ibqp); 1973 1974 /* iwarp does not support the RTR state */ 1975 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1976 attr_mask &= ~IB_QP_STATE; 1977 1978 /* Make sure we still have something left to do */ 1979 if (!attr_mask) 1980 return 0; 1981 1982 memset(&attrs, 0, sizeof attrs); 1983 qhp = to_c4iw_qp(ibqp); 1984 rhp = qhp->rhp; 1985 1986 attrs.next_state = c4iw_convert_state(attr->qp_state); 1987 attrs.enable_rdma_read = (attr->qp_access_flags & 1988 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1989 attrs.enable_rdma_write = (attr->qp_access_flags & 1990 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1991 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1992 1993 1994 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1995 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1996 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1997 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1998 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1999 2000 /* 2001 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 2002 * ringing the queue db when we're in DB_FULL mode. 2003 * Only allow this on T4 devices. 2004 */ 2005 attrs.sq_db_inc = attr->sq_psn; 2006 attrs.rq_db_inc = attr->rq_psn; 2007 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 2008 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 2009 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) && 2010 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB))) 2011 return -EINVAL; 2012 2013 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 2014 } 2015 2016 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 2017 { 2018 pr_debug("ib_dev %p qpn 0x%x\n", dev, qpn); 2019 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 2020 } 2021 2022 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2023 int attr_mask, struct ib_qp_init_attr *init_attr) 2024 { 2025 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 2026 2027 memset(attr, 0, sizeof *attr); 2028 memset(init_attr, 0, sizeof *init_attr); 2029 attr->qp_state = to_ib_qp_state(qhp->attr.state); 2030 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 2031 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 2032 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 2033 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 2034 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 2035 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 2036 return 0; 2037 } 2038