1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include "iw_cxgb4.h" 33 34 static int ocqp_support; 35 module_param(ocqp_support, int, 0644); 36 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=0)"); 37 38 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 39 { 40 unsigned long flag; 41 spin_lock_irqsave(&qhp->lock, flag); 42 qhp->attr.state = state; 43 spin_unlock_irqrestore(&qhp->lock, flag); 44 } 45 46 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 47 { 48 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize); 49 } 50 51 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 52 { 53 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue, 54 pci_unmap_addr(sq, mapping)); 55 } 56 57 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 58 { 59 if (t4_sq_onchip(sq)) 60 dealloc_oc_sq(rdev, sq); 61 else 62 dealloc_host_sq(rdev, sq); 63 } 64 65 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 66 { 67 if (!ocqp_support || !t4_ocqp_supported()) 68 return -ENOSYS; 69 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); 70 if (!sq->dma_addr) 71 return -ENOMEM; 72 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr - 73 rdev->lldi.vr->ocq.start; 74 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr - 75 rdev->lldi.vr->ocq.start); 76 sq->flags |= T4_SQ_ONCHIP; 77 return 0; 78 } 79 80 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 81 { 82 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize, 83 &(sq->dma_addr), GFP_KERNEL); 84 if (!sq->queue) 85 return -ENOMEM; 86 sq->phys_addr = virt_to_phys(sq->queue); 87 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 88 return 0; 89 } 90 91 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 92 struct c4iw_dev_ucontext *uctx) 93 { 94 /* 95 * uP clears EQ contexts when the connection exits rdma mode, 96 * so no need to post a RESET WR for these EQs. 97 */ 98 dma_free_coherent(&(rdev->lldi.pdev->dev), 99 wq->rq.memsize, wq->rq.queue, 100 dma_unmap_addr(&wq->rq, mapping)); 101 dealloc_sq(rdev, &wq->sq); 102 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 103 kfree(wq->rq.sw_rq); 104 kfree(wq->sq.sw_sq); 105 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 106 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 107 return 0; 108 } 109 110 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 111 struct t4_cq *rcq, struct t4_cq *scq, 112 struct c4iw_dev_ucontext *uctx) 113 { 114 int user = (uctx != &rdev->uctx); 115 struct fw_ri_res_wr *res_wr; 116 struct fw_ri_res *res; 117 int wr_len; 118 struct c4iw_wr_wait wr_wait; 119 struct sk_buff *skb; 120 int ret; 121 int eqsize; 122 123 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 124 if (!wq->sq.qid) 125 return -ENOMEM; 126 127 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 128 if (!wq->rq.qid) 129 goto err1; 130 131 if (!user) { 132 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 133 GFP_KERNEL); 134 if (!wq->sq.sw_sq) 135 goto err2; 136 137 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 138 GFP_KERNEL); 139 if (!wq->rq.sw_rq) 140 goto err3; 141 } 142 143 /* 144 * RQT must be a power of 2. 145 */ 146 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); 147 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 148 if (!wq->rq.rqt_hwaddr) 149 goto err4; 150 151 if (user) { 152 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq)) 153 goto err5; 154 } else 155 if (alloc_host_sq(rdev, &wq->sq)) 156 goto err5; 157 memset(wq->sq.queue, 0, wq->sq.memsize); 158 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 159 160 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), 161 wq->rq.memsize, &(wq->rq.dma_addr), 162 GFP_KERNEL); 163 if (!wq->rq.queue) 164 goto err6; 165 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", 166 __func__, wq->sq.queue, 167 (unsigned long long)virt_to_phys(wq->sq.queue), 168 wq->rq.queue, 169 (unsigned long long)virt_to_phys(wq->rq.queue)); 170 memset(wq->rq.queue, 0, wq->rq.memsize); 171 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 172 173 wq->db = rdev->lldi.db_reg; 174 wq->gts = rdev->lldi.gts_reg; 175 if (user) { 176 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) + 177 (wq->sq.qid << rdev->qpshift); 178 wq->sq.udb &= PAGE_MASK; 179 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) + 180 (wq->rq.qid << rdev->qpshift); 181 wq->rq.udb &= PAGE_MASK; 182 } 183 wq->rdev = rdev; 184 wq->rq.msn = 1; 185 186 /* build fw_ri_res_wr */ 187 wr_len = sizeof *res_wr + 2 * sizeof *res; 188 189 skb = alloc_skb(wr_len, GFP_KERNEL); 190 if (!skb) { 191 ret = -ENOMEM; 192 goto err7; 193 } 194 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 195 196 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); 197 memset(res_wr, 0, wr_len); 198 res_wr->op_nres = cpu_to_be32( 199 FW_WR_OP(FW_RI_RES_WR) | 200 V_FW_RI_RES_WR_NRES(2) | 201 FW_WR_COMPL(1)); 202 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 203 res_wr->cookie = (unsigned long) &wr_wait; 204 res = res_wr->res; 205 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 206 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 207 208 /* 209 * eqsize is the number of 64B entries plus the status page size. 210 */ 211 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES; 212 213 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 214 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 215 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 216 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 217 t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0 | 218 V_FW_RI_RES_WR_IQID(scq->cqid)); 219 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 220 V_FW_RI_RES_WR_DCAEN(0) | 221 V_FW_RI_RES_WR_DCACPU(0) | 222 V_FW_RI_RES_WR_FBMIN(2) | 223 V_FW_RI_RES_WR_FBMAX(3) | 224 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 225 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 226 V_FW_RI_RES_WR_EQSIZE(eqsize)); 227 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 228 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 229 res++; 230 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 231 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 232 233 /* 234 * eqsize is the number of 64B entries plus the status page size. 235 */ 236 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES; 237 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 238 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 239 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 240 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 241 V_FW_RI_RES_WR_IQID(rcq->cqid)); 242 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 243 V_FW_RI_RES_WR_DCAEN(0) | 244 V_FW_RI_RES_WR_DCACPU(0) | 245 V_FW_RI_RES_WR_FBMIN(2) | 246 V_FW_RI_RES_WR_FBMAX(3) | 247 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 248 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 249 V_FW_RI_RES_WR_EQSIZE(eqsize)); 250 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 251 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 252 253 c4iw_init_wr_wait(&wr_wait); 254 255 ret = c4iw_ofld_send(rdev, skb); 256 if (ret) 257 goto err7; 258 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 259 if (ret) 260 goto err7; 261 262 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n", 263 __func__, wq->sq.qid, wq->rq.qid, wq->db, 264 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb); 265 266 return 0; 267 err7: 268 dma_free_coherent(&(rdev->lldi.pdev->dev), 269 wq->rq.memsize, wq->rq.queue, 270 dma_unmap_addr(&wq->rq, mapping)); 271 err6: 272 dealloc_sq(rdev, &wq->sq); 273 err5: 274 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 275 err4: 276 kfree(wq->rq.sw_rq); 277 err3: 278 kfree(wq->sq.sw_sq); 279 err2: 280 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 281 err1: 282 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 283 return -ENOMEM; 284 } 285 286 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 287 struct ib_send_wr *wr, int max, u32 *plenp) 288 { 289 u8 *dstp, *srcp; 290 u32 plen = 0; 291 int i; 292 int rem, len; 293 294 dstp = (u8 *)immdp->data; 295 for (i = 0; i < wr->num_sge; i++) { 296 if ((plen + wr->sg_list[i].length) > max) 297 return -EMSGSIZE; 298 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 299 plen += wr->sg_list[i].length; 300 rem = wr->sg_list[i].length; 301 while (rem) { 302 if (dstp == (u8 *)&sq->queue[sq->size]) 303 dstp = (u8 *)sq->queue; 304 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 305 len = rem; 306 else 307 len = (u8 *)&sq->queue[sq->size] - dstp; 308 memcpy(dstp, srcp, len); 309 dstp += len; 310 srcp += len; 311 rem -= len; 312 } 313 } 314 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 315 if (len) 316 memset(dstp, 0, len); 317 immdp->op = FW_RI_DATA_IMMD; 318 immdp->r1 = 0; 319 immdp->r2 = 0; 320 immdp->immdlen = cpu_to_be32(plen); 321 *plenp = plen; 322 return 0; 323 } 324 325 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 326 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 327 int num_sge, u32 *plenp) 328 329 { 330 int i; 331 u32 plen = 0; 332 __be64 *flitp = (__be64 *)isglp->sge; 333 334 for (i = 0; i < num_sge; i++) { 335 if ((plen + sg_list[i].length) < plen) 336 return -EMSGSIZE; 337 plen += sg_list[i].length; 338 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 339 sg_list[i].length); 340 if (++flitp == queue_end) 341 flitp = queue_start; 342 *flitp = cpu_to_be64(sg_list[i].addr); 343 if (++flitp == queue_end) 344 flitp = queue_start; 345 } 346 *flitp = (__force __be64)0; 347 isglp->op = FW_RI_DATA_ISGL; 348 isglp->r1 = 0; 349 isglp->nsge = cpu_to_be16(num_sge); 350 isglp->r2 = 0; 351 if (plenp) 352 *plenp = plen; 353 return 0; 354 } 355 356 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 357 struct ib_send_wr *wr, u8 *len16) 358 { 359 u32 plen; 360 int size; 361 int ret; 362 363 if (wr->num_sge > T4_MAX_SEND_SGE) 364 return -EINVAL; 365 switch (wr->opcode) { 366 case IB_WR_SEND: 367 if (wr->send_flags & IB_SEND_SOLICITED) 368 wqe->send.sendop_pkd = cpu_to_be32( 369 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 370 else 371 wqe->send.sendop_pkd = cpu_to_be32( 372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 373 wqe->send.stag_inv = 0; 374 break; 375 case IB_WR_SEND_WITH_INV: 376 if (wr->send_flags & IB_SEND_SOLICITED) 377 wqe->send.sendop_pkd = cpu_to_be32( 378 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 379 else 380 wqe->send.sendop_pkd = cpu_to_be32( 381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 382 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 383 break; 384 385 default: 386 return -EINVAL; 387 } 388 389 plen = 0; 390 if (wr->num_sge) { 391 if (wr->send_flags & IB_SEND_INLINE) { 392 ret = build_immd(sq, wqe->send.u.immd_src, wr, 393 T4_MAX_SEND_INLINE, &plen); 394 if (ret) 395 return ret; 396 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 397 plen; 398 } else { 399 ret = build_isgl((__be64 *)sq->queue, 400 (__be64 *)&sq->queue[sq->size], 401 wqe->send.u.isgl_src, 402 wr->sg_list, wr->num_sge, &plen); 403 if (ret) 404 return ret; 405 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 406 wr->num_sge * sizeof(struct fw_ri_sge); 407 } 408 } else { 409 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 410 wqe->send.u.immd_src[0].r1 = 0; 411 wqe->send.u.immd_src[0].r2 = 0; 412 wqe->send.u.immd_src[0].immdlen = 0; 413 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 414 plen = 0; 415 } 416 *len16 = DIV_ROUND_UP(size, 16); 417 wqe->send.plen = cpu_to_be32(plen); 418 return 0; 419 } 420 421 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 422 struct ib_send_wr *wr, u8 *len16) 423 { 424 u32 plen; 425 int size; 426 int ret; 427 428 if (wr->num_sge > T4_MAX_SEND_SGE) 429 return -EINVAL; 430 wqe->write.r2 = 0; 431 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); 432 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); 433 if (wr->num_sge) { 434 if (wr->send_flags & IB_SEND_INLINE) { 435 ret = build_immd(sq, wqe->write.u.immd_src, wr, 436 T4_MAX_WRITE_INLINE, &plen); 437 if (ret) 438 return ret; 439 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 440 plen; 441 } else { 442 ret = build_isgl((__be64 *)sq->queue, 443 (__be64 *)&sq->queue[sq->size], 444 wqe->write.u.isgl_src, 445 wr->sg_list, wr->num_sge, &plen); 446 if (ret) 447 return ret; 448 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 449 wr->num_sge * sizeof(struct fw_ri_sge); 450 } 451 } else { 452 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 453 wqe->write.u.immd_src[0].r1 = 0; 454 wqe->write.u.immd_src[0].r2 = 0; 455 wqe->write.u.immd_src[0].immdlen = 0; 456 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 457 plen = 0; 458 } 459 *len16 = DIV_ROUND_UP(size, 16); 460 wqe->write.plen = cpu_to_be32(plen); 461 return 0; 462 } 463 464 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 465 { 466 if (wr->num_sge > 1) 467 return -EINVAL; 468 if (wr->num_sge) { 469 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); 470 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr 471 >> 32)); 472 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); 473 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 474 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 475 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 476 >> 32)); 477 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 478 } else { 479 wqe->read.stag_src = cpu_to_be32(2); 480 wqe->read.to_src_hi = 0; 481 wqe->read.to_src_lo = 0; 482 wqe->read.stag_sink = cpu_to_be32(2); 483 wqe->read.plen = 0; 484 wqe->read.to_sink_hi = 0; 485 wqe->read.to_sink_lo = 0; 486 } 487 wqe->read.r2 = 0; 488 wqe->read.r5 = 0; 489 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 490 return 0; 491 } 492 493 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 494 struct ib_recv_wr *wr, u8 *len16) 495 { 496 int ret; 497 498 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 499 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 500 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 501 if (ret) 502 return ret; 503 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 504 wr->num_sge * sizeof(struct fw_ri_sge), 16); 505 return 0; 506 } 507 508 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, 509 struct ib_send_wr *wr, u8 *len16) 510 { 511 512 struct fw_ri_immd *imdp; 513 __be64 *p; 514 int i; 515 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 516 int rem; 517 518 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 519 return -EINVAL; 520 521 wqe->fr.qpbinde_to_dcacpu = 0; 522 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; 523 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 524 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); 525 wqe->fr.len_hi = 0; 526 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); 527 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); 528 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 529 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 530 0xffffffff); 531 WARN_ON(pbllen > T4_MAX_FR_IMMD); 532 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 533 imdp->op = FW_RI_DATA_IMMD; 534 imdp->r1 = 0; 535 imdp->r2 = 0; 536 imdp->immdlen = cpu_to_be32(pbllen); 537 p = (__be64 *)(imdp + 1); 538 rem = pbllen; 539 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { 540 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); 541 rem -= sizeof *p; 542 if (++p == (__be64 *)&sq->queue[sq->size]) 543 p = (__be64 *)sq->queue; 544 } 545 BUG_ON(rem < 0); 546 while (rem) { 547 *p = 0; 548 rem -= sizeof *p; 549 if (++p == (__be64 *)&sq->queue[sq->size]) 550 p = (__be64 *)sq->queue; 551 } 552 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); 553 return 0; 554 } 555 556 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, 557 u8 *len16) 558 { 559 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 560 wqe->inv.r2 = 0; 561 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 562 return 0; 563 } 564 565 void c4iw_qp_add_ref(struct ib_qp *qp) 566 { 567 PDBG("%s ib_qp %p\n", __func__, qp); 568 atomic_inc(&(to_c4iw_qp(qp)->refcnt)); 569 } 570 571 void c4iw_qp_rem_ref(struct ib_qp *qp) 572 { 573 PDBG("%s ib_qp %p\n", __func__, qp); 574 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) 575 wake_up(&(to_c4iw_qp(qp)->wait)); 576 } 577 578 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 579 struct ib_send_wr **bad_wr) 580 { 581 int err = 0; 582 u8 len16 = 0; 583 enum fw_wr_opcodes fw_opcode = 0; 584 enum fw_ri_wr_flags fw_flags; 585 struct c4iw_qp *qhp; 586 union t4_wr *wqe; 587 u32 num_wrs; 588 struct t4_swsqe *swsqe; 589 unsigned long flag; 590 u16 idx = 0; 591 592 qhp = to_c4iw_qp(ibqp); 593 spin_lock_irqsave(&qhp->lock, flag); 594 if (t4_wq_in_error(&qhp->wq)) { 595 spin_unlock_irqrestore(&qhp->lock, flag); 596 return -EINVAL; 597 } 598 num_wrs = t4_sq_avail(&qhp->wq); 599 if (num_wrs == 0) { 600 spin_unlock_irqrestore(&qhp->lock, flag); 601 return -ENOMEM; 602 } 603 while (wr) { 604 if (num_wrs == 0) { 605 err = -ENOMEM; 606 *bad_wr = wr; 607 break; 608 } 609 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 610 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 611 612 fw_flags = 0; 613 if (wr->send_flags & IB_SEND_SOLICITED) 614 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 615 if (wr->send_flags & IB_SEND_SIGNALED) 616 fw_flags |= FW_RI_COMPLETION_FLAG; 617 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 618 switch (wr->opcode) { 619 case IB_WR_SEND_WITH_INV: 620 case IB_WR_SEND: 621 if (wr->send_flags & IB_SEND_FENCE) 622 fw_flags |= FW_RI_READ_FENCE_FLAG; 623 fw_opcode = FW_RI_SEND_WR; 624 if (wr->opcode == IB_WR_SEND) 625 swsqe->opcode = FW_RI_SEND; 626 else 627 swsqe->opcode = FW_RI_SEND_WITH_INV; 628 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 629 break; 630 case IB_WR_RDMA_WRITE: 631 fw_opcode = FW_RI_RDMA_WRITE_WR; 632 swsqe->opcode = FW_RI_RDMA_WRITE; 633 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 634 break; 635 case IB_WR_RDMA_READ: 636 case IB_WR_RDMA_READ_WITH_INV: 637 fw_opcode = FW_RI_RDMA_READ_WR; 638 swsqe->opcode = FW_RI_READ_REQ; 639 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 640 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 641 else 642 fw_flags = 0; 643 err = build_rdma_read(wqe, wr, &len16); 644 if (err) 645 break; 646 swsqe->read_len = wr->sg_list[0].length; 647 if (!qhp->wq.sq.oldest_read) 648 qhp->wq.sq.oldest_read = swsqe; 649 break; 650 case IB_WR_FAST_REG_MR: 651 fw_opcode = FW_RI_FR_NSMR_WR; 652 swsqe->opcode = FW_RI_FAST_REGISTER; 653 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); 654 break; 655 case IB_WR_LOCAL_INV: 656 if (wr->send_flags & IB_SEND_FENCE) 657 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 658 fw_opcode = FW_RI_INV_LSTAG_WR; 659 swsqe->opcode = FW_RI_LOCAL_INV; 660 err = build_inv_stag(wqe, wr, &len16); 661 break; 662 default: 663 PDBG("%s post of type=%d TBD!\n", __func__, 664 wr->opcode); 665 err = -EINVAL; 666 } 667 if (err) { 668 *bad_wr = wr; 669 break; 670 } 671 swsqe->idx = qhp->wq.sq.pidx; 672 swsqe->complete = 0; 673 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED); 674 swsqe->wr_id = wr->wr_id; 675 676 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 677 678 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", 679 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 680 swsqe->opcode, swsqe->read_len); 681 wr = wr->next; 682 num_wrs--; 683 t4_sq_produce(&qhp->wq, len16); 684 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 685 } 686 if (t4_wq_db_enabled(&qhp->wq)) 687 t4_ring_sq_db(&qhp->wq, idx); 688 spin_unlock_irqrestore(&qhp->lock, flag); 689 return err; 690 } 691 692 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 693 struct ib_recv_wr **bad_wr) 694 { 695 int err = 0; 696 struct c4iw_qp *qhp; 697 union t4_recv_wr *wqe; 698 u32 num_wrs; 699 u8 len16 = 0; 700 unsigned long flag; 701 u16 idx = 0; 702 703 qhp = to_c4iw_qp(ibqp); 704 spin_lock_irqsave(&qhp->lock, flag); 705 if (t4_wq_in_error(&qhp->wq)) { 706 spin_unlock_irqrestore(&qhp->lock, flag); 707 return -EINVAL; 708 } 709 num_wrs = t4_rq_avail(&qhp->wq); 710 if (num_wrs == 0) { 711 spin_unlock_irqrestore(&qhp->lock, flag); 712 return -ENOMEM; 713 } 714 while (wr) { 715 if (wr->num_sge > T4_MAX_RECV_SGE) { 716 err = -EINVAL; 717 *bad_wr = wr; 718 break; 719 } 720 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 721 qhp->wq.rq.wq_pidx * 722 T4_EQ_ENTRY_SIZE); 723 if (num_wrs) 724 err = build_rdma_recv(qhp, wqe, wr, &len16); 725 else 726 err = -ENOMEM; 727 if (err) { 728 *bad_wr = wr; 729 break; 730 } 731 732 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 733 734 wqe->recv.opcode = FW_RI_RECV_WR; 735 wqe->recv.r1 = 0; 736 wqe->recv.wrid = qhp->wq.rq.pidx; 737 wqe->recv.r2[0] = 0; 738 wqe->recv.r2[1] = 0; 739 wqe->recv.r2[2] = 0; 740 wqe->recv.len16 = len16; 741 PDBG("%s cookie 0x%llx pidx %u\n", __func__, 742 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 743 t4_rq_produce(&qhp->wq, len16); 744 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 745 wr = wr->next; 746 num_wrs--; 747 } 748 if (t4_wq_db_enabled(&qhp->wq)) 749 t4_ring_rq_db(&qhp->wq, idx); 750 spin_unlock_irqrestore(&qhp->lock, flag); 751 return err; 752 } 753 754 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) 755 { 756 return -ENOSYS; 757 } 758 759 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 760 u8 *ecode) 761 { 762 int status; 763 int tagged; 764 int opcode; 765 int rqtype; 766 int send_inv; 767 768 if (!err_cqe) { 769 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 770 *ecode = 0; 771 return; 772 } 773 774 status = CQE_STATUS(err_cqe); 775 opcode = CQE_OPCODE(err_cqe); 776 rqtype = RQ_TYPE(err_cqe); 777 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 778 (opcode == FW_RI_SEND_WITH_SE_INV); 779 tagged = (opcode == FW_RI_RDMA_WRITE) || 780 (rqtype && (opcode == FW_RI_READ_RESP)); 781 782 switch (status) { 783 case T4_ERR_STAG: 784 if (send_inv) { 785 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 786 *ecode = RDMAP_CANT_INV_STAG; 787 } else { 788 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 789 *ecode = RDMAP_INV_STAG; 790 } 791 break; 792 case T4_ERR_PDID: 793 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 794 if ((opcode == FW_RI_SEND_WITH_INV) || 795 (opcode == FW_RI_SEND_WITH_SE_INV)) 796 *ecode = RDMAP_CANT_INV_STAG; 797 else 798 *ecode = RDMAP_STAG_NOT_ASSOC; 799 break; 800 case T4_ERR_QPID: 801 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 802 *ecode = RDMAP_STAG_NOT_ASSOC; 803 break; 804 case T4_ERR_ACCESS: 805 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 806 *ecode = RDMAP_ACC_VIOL; 807 break; 808 case T4_ERR_WRAP: 809 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 810 *ecode = RDMAP_TO_WRAP; 811 break; 812 case T4_ERR_BOUND: 813 if (tagged) { 814 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 815 *ecode = DDPT_BASE_BOUNDS; 816 } else { 817 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 818 *ecode = RDMAP_BASE_BOUNDS; 819 } 820 break; 821 case T4_ERR_INVALIDATE_SHARED_MR: 822 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 823 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 824 *ecode = RDMAP_CANT_INV_STAG; 825 break; 826 case T4_ERR_ECC: 827 case T4_ERR_ECC_PSTAG: 828 case T4_ERR_INTERNAL_ERR: 829 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 830 *ecode = 0; 831 break; 832 case T4_ERR_OUT_OF_RQE: 833 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 834 *ecode = DDPU_INV_MSN_NOBUF; 835 break; 836 case T4_ERR_PBL_ADDR_BOUND: 837 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 838 *ecode = DDPT_BASE_BOUNDS; 839 break; 840 case T4_ERR_CRC: 841 *layer_type = LAYER_MPA|DDP_LLP; 842 *ecode = MPA_CRC_ERR; 843 break; 844 case T4_ERR_MARKER: 845 *layer_type = LAYER_MPA|DDP_LLP; 846 *ecode = MPA_MARKER_ERR; 847 break; 848 case T4_ERR_PDU_LEN_ERR: 849 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 850 *ecode = DDPU_MSG_TOOBIG; 851 break; 852 case T4_ERR_DDP_VERSION: 853 if (tagged) { 854 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 855 *ecode = DDPT_INV_VERS; 856 } else { 857 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 858 *ecode = DDPU_INV_VERS; 859 } 860 break; 861 case T4_ERR_RDMA_VERSION: 862 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 863 *ecode = RDMAP_INV_VERS; 864 break; 865 case T4_ERR_OPCODE: 866 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 867 *ecode = RDMAP_INV_OPCODE; 868 break; 869 case T4_ERR_DDP_QUEUE_NUM: 870 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 871 *ecode = DDPU_INV_QN; 872 break; 873 case T4_ERR_MSN: 874 case T4_ERR_MSN_GAP: 875 case T4_ERR_MSN_RANGE: 876 case T4_ERR_IRD_OVERFLOW: 877 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 878 *ecode = DDPU_INV_MSN_RANGE; 879 break; 880 case T4_ERR_TBIT: 881 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 882 *ecode = 0; 883 break; 884 case T4_ERR_MO: 885 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 886 *ecode = DDPU_INV_MO; 887 break; 888 default: 889 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 890 *ecode = 0; 891 break; 892 } 893 } 894 895 int c4iw_post_zb_read(struct c4iw_qp *qhp) 896 { 897 union t4_wr *wqe; 898 struct sk_buff *skb; 899 u8 len16; 900 901 PDBG("%s enter\n", __func__); 902 skb = alloc_skb(40, GFP_KERNEL); 903 if (!skb) { 904 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__); 905 return -ENOMEM; 906 } 907 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 908 909 wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read); 910 memset(wqe, 0, sizeof wqe->read); 911 wqe->read.r2 = cpu_to_be64(0); 912 wqe->read.stag_sink = cpu_to_be32(1); 913 wqe->read.to_sink_hi = cpu_to_be32(0); 914 wqe->read.to_sink_lo = cpu_to_be32(1); 915 wqe->read.stag_src = cpu_to_be32(1); 916 wqe->read.plen = cpu_to_be32(0); 917 wqe->read.to_src_hi = cpu_to_be32(0); 918 wqe->read.to_src_lo = cpu_to_be32(1); 919 len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 920 init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16); 921 922 return c4iw_ofld_send(&qhp->rhp->rdev, skb); 923 } 924 925 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 926 gfp_t gfp) 927 { 928 struct fw_ri_wr *wqe; 929 struct sk_buff *skb; 930 struct terminate_message *term; 931 932 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 933 qhp->ep->hwtid); 934 935 skb = alloc_skb(sizeof *wqe, gfp); 936 if (!skb) 937 return; 938 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 939 940 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 941 memset(wqe, 0, sizeof *wqe); 942 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR)); 943 wqe->flowid_len16 = cpu_to_be32( 944 FW_WR_FLOWID(qhp->ep->hwtid) | 945 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 946 947 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 948 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 949 term = (struct terminate_message *)wqe->u.terminate.termmsg; 950 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 951 c4iw_ofld_send(&qhp->rhp->rdev, skb); 952 } 953 954 /* 955 * Assumes qhp lock is held. 956 */ 957 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 958 struct c4iw_cq *schp) 959 { 960 int count; 961 int flushed; 962 unsigned long flag; 963 964 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 965 966 /* locking hierarchy: cq lock first, then qp lock. */ 967 spin_lock_irqsave(&rchp->lock, flag); 968 spin_lock(&qhp->lock); 969 c4iw_flush_hw_cq(&rchp->cq); 970 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 971 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 972 spin_unlock(&qhp->lock); 973 spin_unlock_irqrestore(&rchp->lock, flag); 974 if (flushed) 975 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 976 977 /* locking hierarchy: cq lock first, then qp lock. */ 978 spin_lock_irqsave(&schp->lock, flag); 979 spin_lock(&qhp->lock); 980 c4iw_flush_hw_cq(&schp->cq); 981 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 982 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 983 spin_unlock(&qhp->lock); 984 spin_unlock_irqrestore(&schp->lock, flag); 985 if (flushed) 986 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 987 } 988 989 static void flush_qp(struct c4iw_qp *qhp) 990 { 991 struct c4iw_cq *rchp, *schp; 992 993 rchp = get_chp(qhp->rhp, qhp->attr.rcq); 994 schp = get_chp(qhp->rhp, qhp->attr.scq); 995 996 if (qhp->ibqp.uobject) { 997 t4_set_wq_in_error(&qhp->wq); 998 t4_set_cq_in_error(&rchp->cq); 999 if (schp != rchp) 1000 t4_set_cq_in_error(&schp->cq); 1001 return; 1002 } 1003 __flush_qp(qhp, rchp, schp); 1004 } 1005 1006 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1007 struct c4iw_ep *ep) 1008 { 1009 struct fw_ri_wr *wqe; 1010 int ret; 1011 struct sk_buff *skb; 1012 1013 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1014 ep->hwtid); 1015 1016 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1017 if (!skb) 1018 return -ENOMEM; 1019 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); 1020 1021 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1022 memset(wqe, 0, sizeof *wqe); 1023 wqe->op_compl = cpu_to_be32( 1024 FW_WR_OP(FW_RI_INIT_WR) | 1025 FW_WR_COMPL(1)); 1026 wqe->flowid_len16 = cpu_to_be32( 1027 FW_WR_FLOWID(ep->hwtid) | 1028 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1029 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1030 1031 wqe->u.fini.type = FW_RI_TYPE_FINI; 1032 c4iw_init_wr_wait(&ep->com.wr_wait); 1033 ret = c4iw_ofld_send(&rhp->rdev, skb); 1034 if (ret) 1035 goto out; 1036 1037 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid, 1038 qhp->wq.sq.qid, __func__); 1039 out: 1040 PDBG("%s ret %d\n", __func__, ret); 1041 return ret; 1042 } 1043 1044 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1045 { 1046 memset(&init->u, 0, sizeof init->u); 1047 switch (p2p_type) { 1048 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1049 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1050 init->u.write.stag_sink = cpu_to_be32(1); 1051 init->u.write.to_sink = cpu_to_be64(1); 1052 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1053 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1054 sizeof(struct fw_ri_immd), 1055 16); 1056 break; 1057 case FW_RI_INIT_P2PTYPE_READ_REQ: 1058 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1059 init->u.read.stag_src = cpu_to_be32(1); 1060 init->u.read.to_src_lo = cpu_to_be32(1); 1061 init->u.read.stag_sink = cpu_to_be32(1); 1062 init->u.read.to_sink_lo = cpu_to_be32(1); 1063 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1064 break; 1065 } 1066 } 1067 1068 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1069 { 1070 struct fw_ri_wr *wqe; 1071 int ret; 1072 struct sk_buff *skb; 1073 1074 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1075 qhp->ep->hwtid); 1076 1077 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1078 if (!skb) 1079 return -ENOMEM; 1080 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1081 1082 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1083 memset(wqe, 0, sizeof *wqe); 1084 wqe->op_compl = cpu_to_be32( 1085 FW_WR_OP(FW_RI_INIT_WR) | 1086 FW_WR_COMPL(1)); 1087 wqe->flowid_len16 = cpu_to_be32( 1088 FW_WR_FLOWID(qhp->ep->hwtid) | 1089 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1090 1091 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait; 1092 1093 wqe->u.init.type = FW_RI_TYPE_INIT; 1094 wqe->u.init.mpareqbit_p2ptype = 1095 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1096 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1097 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1098 if (qhp->attr.mpa_attr.recv_marker_enabled) 1099 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1100 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1101 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1102 if (qhp->attr.mpa_attr.crc_enabled) 1103 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1104 1105 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1106 FW_RI_QP_RDMA_WRITE_ENABLE | 1107 FW_RI_QP_BIND_ENABLE; 1108 if (!qhp->ibqp.uobject) 1109 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1110 FW_RI_QP_STAG0_ENABLE; 1111 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1112 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1113 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1114 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1115 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1116 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1117 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1118 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1119 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1120 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq); 1121 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq); 1122 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1123 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1124 rhp->rdev.lldi.vr->rq.start); 1125 if (qhp->attr.mpa_attr.initiator) 1126 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1127 1128 c4iw_init_wr_wait(&qhp->ep->com.wr_wait); 1129 ret = c4iw_ofld_send(&rhp->rdev, skb); 1130 if (ret) 1131 goto out; 1132 1133 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait, 1134 qhp->ep->hwtid, qhp->wq.sq.qid, __func__); 1135 out: 1136 PDBG("%s ret %d\n", __func__, ret); 1137 return ret; 1138 } 1139 1140 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1141 enum c4iw_qp_attr_mask mask, 1142 struct c4iw_qp_attributes *attrs, 1143 int internal) 1144 { 1145 int ret = 0; 1146 struct c4iw_qp_attributes newattr = qhp->attr; 1147 int disconnect = 0; 1148 int terminate = 0; 1149 int abort = 0; 1150 int free = 0; 1151 struct c4iw_ep *ep = NULL; 1152 1153 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__, 1154 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1155 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1156 1157 mutex_lock(&qhp->mutex); 1158 1159 /* Process attr changes if in IDLE */ 1160 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1161 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1162 ret = -EIO; 1163 goto out; 1164 } 1165 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1166 newattr.enable_rdma_read = attrs->enable_rdma_read; 1167 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1168 newattr.enable_rdma_write = attrs->enable_rdma_write; 1169 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1170 newattr.enable_bind = attrs->enable_bind; 1171 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1172 if (attrs->max_ord > c4iw_max_read_depth) { 1173 ret = -EINVAL; 1174 goto out; 1175 } 1176 newattr.max_ord = attrs->max_ord; 1177 } 1178 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1179 if (attrs->max_ird > c4iw_max_read_depth) { 1180 ret = -EINVAL; 1181 goto out; 1182 } 1183 newattr.max_ird = attrs->max_ird; 1184 } 1185 qhp->attr = newattr; 1186 } 1187 1188 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1189 goto out; 1190 if (qhp->attr.state == attrs->next_state) 1191 goto out; 1192 1193 switch (qhp->attr.state) { 1194 case C4IW_QP_STATE_IDLE: 1195 switch (attrs->next_state) { 1196 case C4IW_QP_STATE_RTS: 1197 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1198 ret = -EINVAL; 1199 goto out; 1200 } 1201 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1202 ret = -EINVAL; 1203 goto out; 1204 } 1205 qhp->attr.mpa_attr = attrs->mpa_attr; 1206 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1207 qhp->ep = qhp->attr.llp_stream_handle; 1208 set_state(qhp, C4IW_QP_STATE_RTS); 1209 1210 /* 1211 * Ref the endpoint here and deref when we 1212 * disassociate the endpoint from the QP. This 1213 * happens in CLOSING->IDLE transition or *->ERROR 1214 * transition. 1215 */ 1216 c4iw_get_ep(&qhp->ep->com); 1217 ret = rdma_init(rhp, qhp); 1218 if (ret) 1219 goto err; 1220 break; 1221 case C4IW_QP_STATE_ERROR: 1222 set_state(qhp, C4IW_QP_STATE_ERROR); 1223 flush_qp(qhp); 1224 break; 1225 default: 1226 ret = -EINVAL; 1227 goto out; 1228 } 1229 break; 1230 case C4IW_QP_STATE_RTS: 1231 switch (attrs->next_state) { 1232 case C4IW_QP_STATE_CLOSING: 1233 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1234 set_state(qhp, C4IW_QP_STATE_CLOSING); 1235 ep = qhp->ep; 1236 if (!internal) { 1237 abort = 0; 1238 disconnect = 1; 1239 c4iw_get_ep(&qhp->ep->com); 1240 } 1241 ret = rdma_fini(rhp, qhp, ep); 1242 if (ret) { 1243 if (internal) 1244 c4iw_get_ep(&qhp->ep->com); 1245 disconnect = abort = 1; 1246 goto err; 1247 } 1248 break; 1249 case C4IW_QP_STATE_TERMINATE: 1250 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1251 if (qhp->ibqp.uobject) 1252 t4_set_wq_in_error(&qhp->wq); 1253 ep = qhp->ep; 1254 if (!internal) 1255 terminate = 1; 1256 disconnect = 1; 1257 c4iw_get_ep(&qhp->ep->com); 1258 break; 1259 case C4IW_QP_STATE_ERROR: 1260 set_state(qhp, C4IW_QP_STATE_ERROR); 1261 if (!internal) { 1262 abort = 1; 1263 disconnect = 1; 1264 ep = qhp->ep; 1265 c4iw_get_ep(&qhp->ep->com); 1266 } 1267 goto err; 1268 break; 1269 default: 1270 ret = -EINVAL; 1271 goto out; 1272 } 1273 break; 1274 case C4IW_QP_STATE_CLOSING: 1275 if (!internal) { 1276 ret = -EINVAL; 1277 goto out; 1278 } 1279 switch (attrs->next_state) { 1280 case C4IW_QP_STATE_IDLE: 1281 flush_qp(qhp); 1282 set_state(qhp, C4IW_QP_STATE_IDLE); 1283 qhp->attr.llp_stream_handle = NULL; 1284 c4iw_put_ep(&qhp->ep->com); 1285 qhp->ep = NULL; 1286 wake_up(&qhp->wait); 1287 break; 1288 case C4IW_QP_STATE_ERROR: 1289 goto err; 1290 default: 1291 ret = -EINVAL; 1292 goto err; 1293 } 1294 break; 1295 case C4IW_QP_STATE_ERROR: 1296 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1297 ret = -EINVAL; 1298 goto out; 1299 } 1300 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1301 ret = -EINVAL; 1302 goto out; 1303 } 1304 set_state(qhp, C4IW_QP_STATE_IDLE); 1305 break; 1306 case C4IW_QP_STATE_TERMINATE: 1307 if (!internal) { 1308 ret = -EINVAL; 1309 goto out; 1310 } 1311 goto err; 1312 break; 1313 default: 1314 printk(KERN_ERR "%s in a bad state %d\n", 1315 __func__, qhp->attr.state); 1316 ret = -EINVAL; 1317 goto err; 1318 break; 1319 } 1320 goto out; 1321 err: 1322 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep, 1323 qhp->wq.sq.qid); 1324 1325 /* disassociate the LLP connection */ 1326 qhp->attr.llp_stream_handle = NULL; 1327 if (!ep) 1328 ep = qhp->ep; 1329 qhp->ep = NULL; 1330 set_state(qhp, C4IW_QP_STATE_ERROR); 1331 free = 1; 1332 wake_up(&qhp->wait); 1333 BUG_ON(!ep); 1334 flush_qp(qhp); 1335 out: 1336 mutex_unlock(&qhp->mutex); 1337 1338 if (terminate) 1339 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1340 1341 /* 1342 * If disconnect is 1, then we need to initiate a disconnect 1343 * on the EP. This can be a normal close (RTS->CLOSING) or 1344 * an abnormal close (RTS/CLOSING->ERROR). 1345 */ 1346 if (disconnect) { 1347 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1348 GFP_KERNEL); 1349 c4iw_put_ep(&ep->com); 1350 } 1351 1352 /* 1353 * If free is 1, then we've disassociated the EP from the QP 1354 * and we need to dereference the EP. 1355 */ 1356 if (free) 1357 c4iw_put_ep(&ep->com); 1358 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1359 return ret; 1360 } 1361 1362 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1363 { 1364 struct c4iw_dev *rhp; 1365 struct c4iw_qp *qhp; 1366 struct c4iw_qp_attributes attrs; 1367 struct c4iw_ucontext *ucontext; 1368 1369 qhp = to_c4iw_qp(ib_qp); 1370 rhp = qhp->rhp; 1371 1372 attrs.next_state = C4IW_QP_STATE_ERROR; 1373 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1374 wait_event(qhp->wait, !qhp->ep); 1375 1376 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1377 atomic_dec(&qhp->refcnt); 1378 wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); 1379 1380 ucontext = ib_qp->uobject ? 1381 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1382 destroy_qp(&rhp->rdev, &qhp->wq, 1383 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1384 1385 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid); 1386 kfree(qhp); 1387 return 0; 1388 } 1389 1390 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1391 struct ib_udata *udata) 1392 { 1393 struct c4iw_dev *rhp; 1394 struct c4iw_qp *qhp; 1395 struct c4iw_pd *php; 1396 struct c4iw_cq *schp; 1397 struct c4iw_cq *rchp; 1398 struct c4iw_create_qp_resp uresp; 1399 int sqsize, rqsize; 1400 struct c4iw_ucontext *ucontext; 1401 int ret; 1402 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL; 1403 1404 PDBG("%s ib_pd %p\n", __func__, pd); 1405 1406 if (attrs->qp_type != IB_QPT_RC) 1407 return ERR_PTR(-EINVAL); 1408 1409 php = to_c4iw_pd(pd); 1410 rhp = php->rhp; 1411 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1412 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1413 if (!schp || !rchp) 1414 return ERR_PTR(-EINVAL); 1415 1416 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1417 return ERR_PTR(-EINVAL); 1418 1419 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); 1420 if (rqsize > T4_MAX_RQ_SIZE) 1421 return ERR_PTR(-E2BIG); 1422 1423 sqsize = roundup(attrs->cap.max_send_wr + 1, 16); 1424 if (sqsize > T4_MAX_SQ_SIZE) 1425 return ERR_PTR(-E2BIG); 1426 1427 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1428 1429 1430 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1431 if (!qhp) 1432 return ERR_PTR(-ENOMEM); 1433 qhp->wq.sq.size = sqsize; 1434 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; 1435 qhp->wq.rq.size = rqsize; 1436 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; 1437 1438 if (ucontext) { 1439 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1440 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1441 } 1442 1443 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n", 1444 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1445 1446 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1447 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1448 if (ret) 1449 goto err1; 1450 1451 attrs->cap.max_recv_wr = rqsize - 1; 1452 attrs->cap.max_send_wr = sqsize - 1; 1453 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1454 1455 qhp->rhp = rhp; 1456 qhp->attr.pd = php->pdid; 1457 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1458 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1459 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1460 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1461 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1462 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1463 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1464 qhp->attr.state = C4IW_QP_STATE_IDLE; 1465 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1466 qhp->attr.enable_rdma_read = 1; 1467 qhp->attr.enable_rdma_write = 1; 1468 qhp->attr.enable_bind = 1; 1469 qhp->attr.max_ord = 1; 1470 qhp->attr.max_ird = 1; 1471 spin_lock_init(&qhp->lock); 1472 mutex_init(&qhp->mutex); 1473 init_waitqueue_head(&qhp->wait); 1474 atomic_set(&qhp->refcnt, 1); 1475 1476 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1477 if (ret) 1478 goto err2; 1479 1480 if (udata) { 1481 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); 1482 if (!mm1) { 1483 ret = -ENOMEM; 1484 goto err3; 1485 } 1486 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 1487 if (!mm2) { 1488 ret = -ENOMEM; 1489 goto err4; 1490 } 1491 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); 1492 if (!mm3) { 1493 ret = -ENOMEM; 1494 goto err5; 1495 } 1496 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); 1497 if (!mm4) { 1498 ret = -ENOMEM; 1499 goto err6; 1500 } 1501 if (t4_sq_onchip(&qhp->wq.sq)) { 1502 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL); 1503 if (!mm5) { 1504 ret = -ENOMEM; 1505 goto err7; 1506 } 1507 uresp.flags = C4IW_QPF_ONCHIP; 1508 } else 1509 uresp.flags = 0; 1510 uresp.qid_mask = rhp->rdev.qpmask; 1511 uresp.sqid = qhp->wq.sq.qid; 1512 uresp.sq_size = qhp->wq.sq.size; 1513 uresp.sq_memsize = qhp->wq.sq.memsize; 1514 uresp.rqid = qhp->wq.rq.qid; 1515 uresp.rq_size = qhp->wq.rq.size; 1516 uresp.rq_memsize = qhp->wq.rq.memsize; 1517 spin_lock(&ucontext->mmap_lock); 1518 if (mm5) { 1519 uresp.ma_sync_key = ucontext->key; 1520 ucontext->key += PAGE_SIZE; 1521 } 1522 uresp.sq_key = ucontext->key; 1523 ucontext->key += PAGE_SIZE; 1524 uresp.rq_key = ucontext->key; 1525 ucontext->key += PAGE_SIZE; 1526 uresp.sq_db_gts_key = ucontext->key; 1527 ucontext->key += PAGE_SIZE; 1528 uresp.rq_db_gts_key = ucontext->key; 1529 ucontext->key += PAGE_SIZE; 1530 spin_unlock(&ucontext->mmap_lock); 1531 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1532 if (ret) 1533 goto err8; 1534 mm1->key = uresp.sq_key; 1535 mm1->addr = qhp->wq.sq.phys_addr; 1536 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1537 insert_mmap(ucontext, mm1); 1538 mm2->key = uresp.rq_key; 1539 mm2->addr = virt_to_phys(qhp->wq.rq.queue); 1540 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1541 insert_mmap(ucontext, mm2); 1542 mm3->key = uresp.sq_db_gts_key; 1543 mm3->addr = qhp->wq.sq.udb; 1544 mm3->len = PAGE_SIZE; 1545 insert_mmap(ucontext, mm3); 1546 mm4->key = uresp.rq_db_gts_key; 1547 mm4->addr = qhp->wq.rq.udb; 1548 mm4->len = PAGE_SIZE; 1549 insert_mmap(ucontext, mm4); 1550 if (mm5) { 1551 mm5->key = uresp.ma_sync_key; 1552 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0) 1553 + A_PCIE_MA_SYNC) & PAGE_MASK; 1554 mm5->len = PAGE_SIZE; 1555 insert_mmap(ucontext, mm5); 1556 } 1557 } 1558 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1559 init_timer(&(qhp->timer)); 1560 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n", 1561 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1562 qhp->wq.sq.qid); 1563 return &qhp->ibqp; 1564 err8: 1565 kfree(mm5); 1566 err7: 1567 kfree(mm4); 1568 err6: 1569 kfree(mm3); 1570 err5: 1571 kfree(mm2); 1572 err4: 1573 kfree(mm1); 1574 err3: 1575 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1576 err2: 1577 destroy_qp(&rhp->rdev, &qhp->wq, 1578 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1579 err1: 1580 kfree(qhp); 1581 return ERR_PTR(ret); 1582 } 1583 1584 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1585 int attr_mask, struct ib_udata *udata) 1586 { 1587 struct c4iw_dev *rhp; 1588 struct c4iw_qp *qhp; 1589 enum c4iw_qp_attr_mask mask = 0; 1590 struct c4iw_qp_attributes attrs; 1591 1592 PDBG("%s ib_qp %p\n", __func__, ibqp); 1593 1594 /* iwarp does not support the RTR state */ 1595 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1596 attr_mask &= ~IB_QP_STATE; 1597 1598 /* Make sure we still have something left to do */ 1599 if (!attr_mask) 1600 return 0; 1601 1602 memset(&attrs, 0, sizeof attrs); 1603 qhp = to_c4iw_qp(ibqp); 1604 rhp = qhp->rhp; 1605 1606 attrs.next_state = c4iw_convert_state(attr->qp_state); 1607 attrs.enable_rdma_read = (attr->qp_access_flags & 1608 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1609 attrs.enable_rdma_write = (attr->qp_access_flags & 1610 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1611 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1612 1613 1614 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1615 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1616 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1617 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1618 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1619 1620 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1621 } 1622 1623 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1624 { 1625 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn); 1626 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1627 } 1628