1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 35 #include "iw_cxgb4.h" 36 37 static int db_delay_usecs = 1; 38 module_param(db_delay_usecs, int, 0644); 39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain"); 40 41 static int ocqp_support = 1; 42 module_param(ocqp_support, int, 0644); 43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); 44 45 int db_fc_threshold = 1000; 46 module_param(db_fc_threshold, int, 0644); 47 MODULE_PARM_DESC(db_fc_threshold, 48 "QP count/threshold that triggers" 49 " automatic db flow control mode (default = 1000)"); 50 51 int db_coalescing_threshold; 52 module_param(db_coalescing_threshold, int, 0644); 53 MODULE_PARM_DESC(db_coalescing_threshold, 54 "QP count/threshold that triggers" 55 " disabling db coalescing (default = 0)"); 56 57 static int max_fr_immd = T4_MAX_FR_IMMD; 58 module_param(max_fr_immd, int, 0644); 59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate"); 60 61 static int alloc_ird(struct c4iw_dev *dev, u32 ird) 62 { 63 int ret = 0; 64 65 spin_lock_irq(&dev->lock); 66 if (ird <= dev->avail_ird) 67 dev->avail_ird -= ird; 68 else 69 ret = -ENOMEM; 70 spin_unlock_irq(&dev->lock); 71 72 if (ret) 73 dev_warn(&dev->rdev.lldi.pdev->dev, 74 "device IRD resources exhausted\n"); 75 76 return ret; 77 } 78 79 static void free_ird(struct c4iw_dev *dev, int ird) 80 { 81 spin_lock_irq(&dev->lock); 82 dev->avail_ird += ird; 83 spin_unlock_irq(&dev->lock); 84 } 85 86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 87 { 88 unsigned long flag; 89 spin_lock_irqsave(&qhp->lock, flag); 90 qhp->attr.state = state; 91 spin_unlock_irqrestore(&qhp->lock, flag); 92 } 93 94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 95 { 96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize); 97 } 98 99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 100 { 101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue, 102 pci_unmap_addr(sq, mapping)); 103 } 104 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 106 { 107 if (t4_sq_onchip(sq)) 108 dealloc_oc_sq(rdev, sq); 109 else 110 dealloc_host_sq(rdev, sq); 111 } 112 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 114 { 115 if (!ocqp_support || !ocqp_supported(&rdev->lldi)) 116 return -ENOSYS; 117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); 118 if (!sq->dma_addr) 119 return -ENOMEM; 120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr - 121 rdev->lldi.vr->ocq.start; 122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr - 123 rdev->lldi.vr->ocq.start); 124 sq->flags |= T4_SQ_ONCHIP; 125 return 0; 126 } 127 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 129 { 130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize, 131 &(sq->dma_addr), GFP_KERNEL); 132 if (!sq->queue) 133 return -ENOMEM; 134 sq->phys_addr = virt_to_phys(sq->queue); 135 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 136 return 0; 137 } 138 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user) 140 { 141 int ret = -ENOSYS; 142 if (user) 143 ret = alloc_oc_sq(rdev, sq); 144 if (ret) 145 ret = alloc_host_sq(rdev, sq); 146 return ret; 147 } 148 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 150 struct c4iw_dev_ucontext *uctx) 151 { 152 /* 153 * uP clears EQ contexts when the connection exits rdma mode, 154 * so no need to post a RESET WR for these EQs. 155 */ 156 dma_free_coherent(&(rdev->lldi.pdev->dev), 157 wq->rq.memsize, wq->rq.queue, 158 dma_unmap_addr(&wq->rq, mapping)); 159 dealloc_sq(rdev, &wq->sq); 160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 161 kfree(wq->rq.sw_rq); 162 kfree(wq->sq.sw_sq); 163 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 164 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 165 return 0; 166 } 167 168 /* 169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL, 170 * then this is a user mapping so compute the page-aligned physical address 171 * for mapping. 172 */ 173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 174 enum cxgb4_bar2_qtype qtype, 175 unsigned int *pbar2_qid, u64 *pbar2_pa) 176 { 177 u64 bar2_qoffset; 178 int ret; 179 180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype, 181 pbar2_pa ? 1 : 0, 182 &bar2_qoffset, pbar2_qid); 183 if (ret) 184 return NULL; 185 186 if (pbar2_pa) 187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK; 188 189 if (is_t4(rdev->lldi.adapter_type)) 190 return NULL; 191 192 return rdev->bar2_kva + bar2_qoffset; 193 } 194 195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 196 struct t4_cq *rcq, struct t4_cq *scq, 197 struct c4iw_dev_ucontext *uctx) 198 { 199 int user = (uctx != &rdev->uctx); 200 struct fw_ri_res_wr *res_wr; 201 struct fw_ri_res *res; 202 int wr_len; 203 struct c4iw_wr_wait wr_wait; 204 struct sk_buff *skb; 205 int ret = 0; 206 int eqsize; 207 208 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 209 if (!wq->sq.qid) 210 return -ENOMEM; 211 212 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 213 if (!wq->rq.qid) { 214 ret = -ENOMEM; 215 goto free_sq_qid; 216 } 217 218 if (!user) { 219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 220 GFP_KERNEL); 221 if (!wq->sq.sw_sq) { 222 ret = -ENOMEM; 223 goto free_rq_qid; 224 } 225 226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 227 GFP_KERNEL); 228 if (!wq->rq.sw_rq) { 229 ret = -ENOMEM; 230 goto free_sw_sq; 231 } 232 } 233 234 /* 235 * RQT must be a power of 2 and at least 16 deep. 236 */ 237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16)); 238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 239 if (!wq->rq.rqt_hwaddr) { 240 ret = -ENOMEM; 241 goto free_sw_rq; 242 } 243 244 ret = alloc_sq(rdev, &wq->sq, user); 245 if (ret) 246 goto free_hwaddr; 247 memset(wq->sq.queue, 0, wq->sq.memsize); 248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 249 250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), 251 wq->rq.memsize, &(wq->rq.dma_addr), 252 GFP_KERNEL); 253 if (!wq->rq.queue) { 254 ret = -ENOMEM; 255 goto free_sq; 256 } 257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", 258 __func__, wq->sq.queue, 259 (unsigned long long)virt_to_phys(wq->sq.queue), 260 wq->rq.queue, 261 (unsigned long long)virt_to_phys(wq->rq.queue)); 262 memset(wq->rq.queue, 0, wq->rq.memsize); 263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 264 265 wq->db = rdev->lldi.db_reg; 266 267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, 268 &wq->sq.bar2_qid, 269 user ? &wq->sq.bar2_pa : NULL); 270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, 271 &wq->rq.bar2_qid, 272 user ? &wq->rq.bar2_pa : NULL); 273 274 /* 275 * User mode must have bar2 access. 276 */ 277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) { 278 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n", 279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid); 280 goto free_dma; 281 } 282 283 wq->rdev = rdev; 284 wq->rq.msn = 1; 285 286 /* build fw_ri_res_wr */ 287 wr_len = sizeof *res_wr + 2 * sizeof *res; 288 289 skb = alloc_skb(wr_len, GFP_KERNEL); 290 if (!skb) { 291 ret = -ENOMEM; 292 goto free_dma; 293 } 294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 295 296 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); 297 memset(res_wr, 0, wr_len); 298 res_wr->op_nres = cpu_to_be32( 299 FW_WR_OP_V(FW_RI_RES_WR) | 300 FW_RI_RES_WR_NRES_V(2) | 301 FW_WR_COMPL_F); 302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 303 res_wr->cookie = (uintptr_t)&wr_wait; 304 res = res_wr->res; 305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 306 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 307 308 /* 309 * eqsize is the number of 64B entries plus the status page size. 310 */ 311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 312 rdev->hw_queue.t4_eq_status_entries; 313 314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) | 319 FW_RI_RES_WR_IQID_V(scq->cqid)); 320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 321 FW_RI_RES_WR_DCAEN_V(0) | 322 FW_RI_RES_WR_DCACPU_V(0) | 323 FW_RI_RES_WR_FBMIN_V(2) | 324 FW_RI_RES_WR_FBMAX_V(2) | 325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 326 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 327 FW_RI_RES_WR_EQSIZE_V(eqsize)); 328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 330 res++; 331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 332 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 333 334 /* 335 * eqsize is the number of 64B entries plus the status page size. 336 */ 337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 338 rdev->hw_queue.t4_eq_status_entries; 339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 343 FW_RI_RES_WR_IQID_V(rcq->cqid)); 344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 345 FW_RI_RES_WR_DCAEN_V(0) | 346 FW_RI_RES_WR_DCACPU_V(0) | 347 FW_RI_RES_WR_FBMIN_V(2) | 348 FW_RI_RES_WR_FBMAX_V(2) | 349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 350 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 351 FW_RI_RES_WR_EQSIZE_V(eqsize)); 352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 354 355 c4iw_init_wr_wait(&wr_wait); 356 357 ret = c4iw_ofld_send(rdev, skb); 358 if (ret) 359 goto free_dma; 360 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 361 if (ret) 362 goto free_dma; 363 364 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n", 365 __func__, wq->sq.qid, wq->rq.qid, wq->db, 366 wq->sq.bar2_va, wq->rq.bar2_va); 367 368 return 0; 369 free_dma: 370 dma_free_coherent(&(rdev->lldi.pdev->dev), 371 wq->rq.memsize, wq->rq.queue, 372 dma_unmap_addr(&wq->rq, mapping)); 373 free_sq: 374 dealloc_sq(rdev, &wq->sq); 375 free_hwaddr: 376 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 377 free_sw_rq: 378 kfree(wq->rq.sw_rq); 379 free_sw_sq: 380 kfree(wq->sq.sw_sq); 381 free_rq_qid: 382 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 383 free_sq_qid: 384 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 385 return ret; 386 } 387 388 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 389 struct ib_send_wr *wr, int max, u32 *plenp) 390 { 391 u8 *dstp, *srcp; 392 u32 plen = 0; 393 int i; 394 int rem, len; 395 396 dstp = (u8 *)immdp->data; 397 for (i = 0; i < wr->num_sge; i++) { 398 if ((plen + wr->sg_list[i].length) > max) 399 return -EMSGSIZE; 400 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 401 plen += wr->sg_list[i].length; 402 rem = wr->sg_list[i].length; 403 while (rem) { 404 if (dstp == (u8 *)&sq->queue[sq->size]) 405 dstp = (u8 *)sq->queue; 406 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 407 len = rem; 408 else 409 len = (u8 *)&sq->queue[sq->size] - dstp; 410 memcpy(dstp, srcp, len); 411 dstp += len; 412 srcp += len; 413 rem -= len; 414 } 415 } 416 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 417 if (len) 418 memset(dstp, 0, len); 419 immdp->op = FW_RI_DATA_IMMD; 420 immdp->r1 = 0; 421 immdp->r2 = 0; 422 immdp->immdlen = cpu_to_be32(plen); 423 *plenp = plen; 424 return 0; 425 } 426 427 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 428 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 429 int num_sge, u32 *plenp) 430 431 { 432 int i; 433 u32 plen = 0; 434 __be64 *flitp = (__be64 *)isglp->sge; 435 436 for (i = 0; i < num_sge; i++) { 437 if ((plen + sg_list[i].length) < plen) 438 return -EMSGSIZE; 439 plen += sg_list[i].length; 440 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 441 sg_list[i].length); 442 if (++flitp == queue_end) 443 flitp = queue_start; 444 *flitp = cpu_to_be64(sg_list[i].addr); 445 if (++flitp == queue_end) 446 flitp = queue_start; 447 } 448 *flitp = (__force __be64)0; 449 isglp->op = FW_RI_DATA_ISGL; 450 isglp->r1 = 0; 451 isglp->nsge = cpu_to_be16(num_sge); 452 isglp->r2 = 0; 453 if (plenp) 454 *plenp = plen; 455 return 0; 456 } 457 458 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 459 struct ib_send_wr *wr, u8 *len16) 460 { 461 u32 plen; 462 int size; 463 int ret; 464 465 if (wr->num_sge > T4_MAX_SEND_SGE) 466 return -EINVAL; 467 switch (wr->opcode) { 468 case IB_WR_SEND: 469 if (wr->send_flags & IB_SEND_SOLICITED) 470 wqe->send.sendop_pkd = cpu_to_be32( 471 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE)); 472 else 473 wqe->send.sendop_pkd = cpu_to_be32( 474 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND)); 475 wqe->send.stag_inv = 0; 476 break; 477 case IB_WR_SEND_WITH_INV: 478 if (wr->send_flags & IB_SEND_SOLICITED) 479 wqe->send.sendop_pkd = cpu_to_be32( 480 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV)); 481 else 482 wqe->send.sendop_pkd = cpu_to_be32( 483 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV)); 484 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 485 break; 486 487 default: 488 return -EINVAL; 489 } 490 wqe->send.r3 = 0; 491 wqe->send.r4 = 0; 492 493 plen = 0; 494 if (wr->num_sge) { 495 if (wr->send_flags & IB_SEND_INLINE) { 496 ret = build_immd(sq, wqe->send.u.immd_src, wr, 497 T4_MAX_SEND_INLINE, &plen); 498 if (ret) 499 return ret; 500 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 501 plen; 502 } else { 503 ret = build_isgl((__be64 *)sq->queue, 504 (__be64 *)&sq->queue[sq->size], 505 wqe->send.u.isgl_src, 506 wr->sg_list, wr->num_sge, &plen); 507 if (ret) 508 return ret; 509 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 510 wr->num_sge * sizeof(struct fw_ri_sge); 511 } 512 } else { 513 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 514 wqe->send.u.immd_src[0].r1 = 0; 515 wqe->send.u.immd_src[0].r2 = 0; 516 wqe->send.u.immd_src[0].immdlen = 0; 517 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 518 plen = 0; 519 } 520 *len16 = DIV_ROUND_UP(size, 16); 521 wqe->send.plen = cpu_to_be32(plen); 522 return 0; 523 } 524 525 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 526 struct ib_send_wr *wr, u8 *len16) 527 { 528 u32 plen; 529 int size; 530 int ret; 531 532 if (wr->num_sge > T4_MAX_SEND_SGE) 533 return -EINVAL; 534 wqe->write.r2 = 0; 535 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey); 536 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr); 537 if (wr->num_sge) { 538 if (wr->send_flags & IB_SEND_INLINE) { 539 ret = build_immd(sq, wqe->write.u.immd_src, wr, 540 T4_MAX_WRITE_INLINE, &plen); 541 if (ret) 542 return ret; 543 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 544 plen; 545 } else { 546 ret = build_isgl((__be64 *)sq->queue, 547 (__be64 *)&sq->queue[sq->size], 548 wqe->write.u.isgl_src, 549 wr->sg_list, wr->num_sge, &plen); 550 if (ret) 551 return ret; 552 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 553 wr->num_sge * sizeof(struct fw_ri_sge); 554 } 555 } else { 556 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 557 wqe->write.u.immd_src[0].r1 = 0; 558 wqe->write.u.immd_src[0].r2 = 0; 559 wqe->write.u.immd_src[0].immdlen = 0; 560 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 561 plen = 0; 562 } 563 *len16 = DIV_ROUND_UP(size, 16); 564 wqe->write.plen = cpu_to_be32(plen); 565 return 0; 566 } 567 568 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 569 { 570 if (wr->num_sge > 1) 571 return -EINVAL; 572 if (wr->num_sge) { 573 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey); 574 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr 575 >> 32)); 576 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr); 577 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 578 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 579 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 580 >> 32)); 581 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 582 } else { 583 wqe->read.stag_src = cpu_to_be32(2); 584 wqe->read.to_src_hi = 0; 585 wqe->read.to_src_lo = 0; 586 wqe->read.stag_sink = cpu_to_be32(2); 587 wqe->read.plen = 0; 588 wqe->read.to_sink_hi = 0; 589 wqe->read.to_sink_lo = 0; 590 } 591 wqe->read.r2 = 0; 592 wqe->read.r5 = 0; 593 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 594 return 0; 595 } 596 597 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 598 struct ib_recv_wr *wr, u8 *len16) 599 { 600 int ret; 601 602 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 603 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 604 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 605 if (ret) 606 return ret; 607 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 608 wr->num_sge * sizeof(struct fw_ri_sge), 16); 609 return 0; 610 } 611 612 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr, 613 struct ib_reg_wr *wr, struct c4iw_mr *mhp, 614 u8 *len16) 615 { 616 __be64 *p = (__be64 *)fr->pbl; 617 618 fr->r2 = cpu_to_be32(0); 619 fr->stag = cpu_to_be32(mhp->ibmr.rkey); 620 621 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 622 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) | 623 FW_RI_TPTE_STAGSTATE_V(1) | 624 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) | 625 FW_RI_TPTE_PDID_V(mhp->attr.pdid)); 626 fr->tpte.locread_to_qpid = cpu_to_be32( 627 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) | 628 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) | 629 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12)); 630 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V( 631 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3)); 632 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0); 633 fr->tpte.len_hi = cpu_to_be32(0); 634 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length); 635 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 636 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 637 638 p[0] = cpu_to_be64((u64)mhp->mpl[0]); 639 p[1] = cpu_to_be64((u64)mhp->mpl[1]); 640 641 *len16 = DIV_ROUND_UP(sizeof(*fr), 16); 642 } 643 644 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, 645 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16, 646 bool dsgl_supported) 647 { 648 struct fw_ri_immd *imdp; 649 __be64 *p; 650 int i; 651 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32); 652 int rem; 653 654 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl)) 655 return -EINVAL; 656 657 wqe->fr.qpbinde_to_dcacpu = 0; 658 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12; 659 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 660 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access); 661 wqe->fr.len_hi = 0; 662 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length); 663 wqe->fr.stag = cpu_to_be32(wr->key); 664 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 665 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 666 0xffffffff); 667 668 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) { 669 struct fw_ri_dsgl *sglp; 670 671 for (i = 0; i < mhp->mpl_len; i++) 672 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]); 673 674 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 675 sglp->op = FW_RI_DATA_DSGL; 676 sglp->r1 = 0; 677 sglp->nsge = cpu_to_be16(1); 678 sglp->addr0 = cpu_to_be64(mhp->mpl_addr); 679 sglp->len0 = cpu_to_be32(pbllen); 680 681 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); 682 } else { 683 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 684 imdp->op = FW_RI_DATA_IMMD; 685 imdp->r1 = 0; 686 imdp->r2 = 0; 687 imdp->immdlen = cpu_to_be32(pbllen); 688 p = (__be64 *)(imdp + 1); 689 rem = pbllen; 690 for (i = 0; i < mhp->mpl_len; i++) { 691 *p = cpu_to_be64((u64)mhp->mpl[i]); 692 rem -= sizeof(*p); 693 if (++p == (__be64 *)&sq->queue[sq->size]) 694 p = (__be64 *)sq->queue; 695 } 696 BUG_ON(rem < 0); 697 while (rem) { 698 *p = 0; 699 rem -= sizeof(*p); 700 if (++p == (__be64 *)&sq->queue[sq->size]) 701 p = (__be64 *)sq->queue; 702 } 703 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) 704 + pbllen, 16); 705 } 706 return 0; 707 } 708 709 static int build_inv_stag(struct c4iw_dev *dev, union t4_wr *wqe, 710 struct ib_send_wr *wr, u8 *len16) 711 { 712 struct c4iw_mr *mhp = get_mhp(dev, wr->ex.invalidate_rkey >> 8); 713 714 mhp->attr.state = 0; 715 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 716 wqe->inv.r2 = 0; 717 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 718 return 0; 719 } 720 721 static void _free_qp(struct kref *kref) 722 { 723 struct c4iw_qp *qhp; 724 725 qhp = container_of(kref, struct c4iw_qp, kref); 726 PDBG("%s qhp %p\n", __func__, qhp); 727 kfree(qhp); 728 } 729 730 void c4iw_qp_add_ref(struct ib_qp *qp) 731 { 732 PDBG("%s ib_qp %p\n", __func__, qp); 733 kref_get(&to_c4iw_qp(qp)->kref); 734 } 735 736 void c4iw_qp_rem_ref(struct ib_qp *qp) 737 { 738 PDBG("%s ib_qp %p\n", __func__, qp); 739 kref_put(&to_c4iw_qp(qp)->kref, _free_qp); 740 } 741 742 static void add_to_fc_list(struct list_head *head, struct list_head *entry) 743 { 744 if (list_empty(entry)) 745 list_add_tail(entry, head); 746 } 747 748 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc) 749 { 750 unsigned long flags; 751 752 spin_lock_irqsave(&qhp->rhp->lock, flags); 753 spin_lock(&qhp->lock); 754 if (qhp->rhp->db_state == NORMAL) 755 t4_ring_sq_db(&qhp->wq, inc, NULL); 756 else { 757 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 758 qhp->wq.sq.wq_pidx_inc += inc; 759 } 760 spin_unlock(&qhp->lock); 761 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 762 return 0; 763 } 764 765 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc) 766 { 767 unsigned long flags; 768 769 spin_lock_irqsave(&qhp->rhp->lock, flags); 770 spin_lock(&qhp->lock); 771 if (qhp->rhp->db_state == NORMAL) 772 t4_ring_rq_db(&qhp->wq, inc, NULL); 773 else { 774 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 775 qhp->wq.rq.wq_pidx_inc += inc; 776 } 777 spin_unlock(&qhp->lock); 778 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 779 return 0; 780 } 781 782 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 783 struct ib_send_wr **bad_wr) 784 { 785 int err = 0; 786 u8 len16 = 0; 787 enum fw_wr_opcodes fw_opcode = 0; 788 enum fw_ri_wr_flags fw_flags; 789 struct c4iw_qp *qhp; 790 union t4_wr *wqe = NULL; 791 u32 num_wrs; 792 struct t4_swsqe *swsqe; 793 unsigned long flag; 794 u16 idx = 0; 795 796 qhp = to_c4iw_qp(ibqp); 797 spin_lock_irqsave(&qhp->lock, flag); 798 if (t4_wq_in_error(&qhp->wq)) { 799 spin_unlock_irqrestore(&qhp->lock, flag); 800 return -EINVAL; 801 } 802 num_wrs = t4_sq_avail(&qhp->wq); 803 if (num_wrs == 0) { 804 spin_unlock_irqrestore(&qhp->lock, flag); 805 return -ENOMEM; 806 } 807 while (wr) { 808 if (num_wrs == 0) { 809 err = -ENOMEM; 810 *bad_wr = wr; 811 break; 812 } 813 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 814 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 815 816 fw_flags = 0; 817 if (wr->send_flags & IB_SEND_SOLICITED) 818 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 819 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 820 fw_flags |= FW_RI_COMPLETION_FLAG; 821 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 822 switch (wr->opcode) { 823 case IB_WR_SEND_WITH_INV: 824 case IB_WR_SEND: 825 if (wr->send_flags & IB_SEND_FENCE) 826 fw_flags |= FW_RI_READ_FENCE_FLAG; 827 fw_opcode = FW_RI_SEND_WR; 828 if (wr->opcode == IB_WR_SEND) 829 swsqe->opcode = FW_RI_SEND; 830 else 831 swsqe->opcode = FW_RI_SEND_WITH_INV; 832 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 833 break; 834 case IB_WR_RDMA_WRITE: 835 fw_opcode = FW_RI_RDMA_WRITE_WR; 836 swsqe->opcode = FW_RI_RDMA_WRITE; 837 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 838 break; 839 case IB_WR_RDMA_READ: 840 case IB_WR_RDMA_READ_WITH_INV: 841 fw_opcode = FW_RI_RDMA_READ_WR; 842 swsqe->opcode = FW_RI_READ_REQ; 843 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 844 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 845 else 846 fw_flags = 0; 847 err = build_rdma_read(wqe, wr, &len16); 848 if (err) 849 break; 850 swsqe->read_len = wr->sg_list[0].length; 851 if (!qhp->wq.sq.oldest_read) 852 qhp->wq.sq.oldest_read = swsqe; 853 break; 854 case IB_WR_REG_MR: { 855 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr); 856 857 swsqe->opcode = FW_RI_FAST_REGISTER; 858 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support && 859 !mhp->attr.state && mhp->mpl_len <= 2) { 860 fw_opcode = FW_RI_FR_NSMR_TPTE_WR; 861 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr), 862 mhp, &len16); 863 } else { 864 fw_opcode = FW_RI_FR_NSMR_WR; 865 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), 866 mhp, &len16, 867 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl); 868 if (err) 869 break; 870 } 871 mhp->attr.state = 1; 872 break; 873 } 874 case IB_WR_LOCAL_INV: 875 if (wr->send_flags & IB_SEND_FENCE) 876 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 877 fw_opcode = FW_RI_INV_LSTAG_WR; 878 swsqe->opcode = FW_RI_LOCAL_INV; 879 err = build_inv_stag(qhp->rhp, wqe, wr, &len16); 880 break; 881 default: 882 PDBG("%s post of type=%d TBD!\n", __func__, 883 wr->opcode); 884 err = -EINVAL; 885 } 886 if (err) { 887 *bad_wr = wr; 888 break; 889 } 890 swsqe->idx = qhp->wq.sq.pidx; 891 swsqe->complete = 0; 892 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 893 qhp->sq_sig_all; 894 swsqe->flushed = 0; 895 swsqe->wr_id = wr->wr_id; 896 if (c4iw_wr_log) { 897 swsqe->sge_ts = cxgb4_read_sge_timestamp( 898 qhp->rhp->rdev.lldi.ports[0]); 899 getnstimeofday(&swsqe->host_ts); 900 } 901 902 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 903 904 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", 905 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 906 swsqe->opcode, swsqe->read_len); 907 wr = wr->next; 908 num_wrs--; 909 t4_sq_produce(&qhp->wq, len16); 910 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 911 } 912 if (!qhp->rhp->rdev.status_page->db_off) { 913 t4_ring_sq_db(&qhp->wq, idx, wqe); 914 spin_unlock_irqrestore(&qhp->lock, flag); 915 } else { 916 spin_unlock_irqrestore(&qhp->lock, flag); 917 ring_kernel_sq_db(qhp, idx); 918 } 919 return err; 920 } 921 922 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 923 struct ib_recv_wr **bad_wr) 924 { 925 int err = 0; 926 struct c4iw_qp *qhp; 927 union t4_recv_wr *wqe = NULL; 928 u32 num_wrs; 929 u8 len16 = 0; 930 unsigned long flag; 931 u16 idx = 0; 932 933 qhp = to_c4iw_qp(ibqp); 934 spin_lock_irqsave(&qhp->lock, flag); 935 if (t4_wq_in_error(&qhp->wq)) { 936 spin_unlock_irqrestore(&qhp->lock, flag); 937 return -EINVAL; 938 } 939 num_wrs = t4_rq_avail(&qhp->wq); 940 if (num_wrs == 0) { 941 spin_unlock_irqrestore(&qhp->lock, flag); 942 return -ENOMEM; 943 } 944 while (wr) { 945 if (wr->num_sge > T4_MAX_RECV_SGE) { 946 err = -EINVAL; 947 *bad_wr = wr; 948 break; 949 } 950 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 951 qhp->wq.rq.wq_pidx * 952 T4_EQ_ENTRY_SIZE); 953 if (num_wrs) 954 err = build_rdma_recv(qhp, wqe, wr, &len16); 955 else 956 err = -ENOMEM; 957 if (err) { 958 *bad_wr = wr; 959 break; 960 } 961 962 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 963 if (c4iw_wr_log) { 964 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts = 965 cxgb4_read_sge_timestamp( 966 qhp->rhp->rdev.lldi.ports[0]); 967 getnstimeofday( 968 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts); 969 } 970 971 wqe->recv.opcode = FW_RI_RECV_WR; 972 wqe->recv.r1 = 0; 973 wqe->recv.wrid = qhp->wq.rq.pidx; 974 wqe->recv.r2[0] = 0; 975 wqe->recv.r2[1] = 0; 976 wqe->recv.r2[2] = 0; 977 wqe->recv.len16 = len16; 978 PDBG("%s cookie 0x%llx pidx %u\n", __func__, 979 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 980 t4_rq_produce(&qhp->wq, len16); 981 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 982 wr = wr->next; 983 num_wrs--; 984 } 985 if (!qhp->rhp->rdev.status_page->db_off) { 986 t4_ring_rq_db(&qhp->wq, idx, wqe); 987 spin_unlock_irqrestore(&qhp->lock, flag); 988 } else { 989 spin_unlock_irqrestore(&qhp->lock, flag); 990 ring_kernel_rq_db(qhp, idx); 991 } 992 return err; 993 } 994 995 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 996 u8 *ecode) 997 { 998 int status; 999 int tagged; 1000 int opcode; 1001 int rqtype; 1002 int send_inv; 1003 1004 if (!err_cqe) { 1005 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1006 *ecode = 0; 1007 return; 1008 } 1009 1010 status = CQE_STATUS(err_cqe); 1011 opcode = CQE_OPCODE(err_cqe); 1012 rqtype = RQ_TYPE(err_cqe); 1013 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 1014 (opcode == FW_RI_SEND_WITH_SE_INV); 1015 tagged = (opcode == FW_RI_RDMA_WRITE) || 1016 (rqtype && (opcode == FW_RI_READ_RESP)); 1017 1018 switch (status) { 1019 case T4_ERR_STAG: 1020 if (send_inv) { 1021 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1022 *ecode = RDMAP_CANT_INV_STAG; 1023 } else { 1024 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1025 *ecode = RDMAP_INV_STAG; 1026 } 1027 break; 1028 case T4_ERR_PDID: 1029 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1030 if ((opcode == FW_RI_SEND_WITH_INV) || 1031 (opcode == FW_RI_SEND_WITH_SE_INV)) 1032 *ecode = RDMAP_CANT_INV_STAG; 1033 else 1034 *ecode = RDMAP_STAG_NOT_ASSOC; 1035 break; 1036 case T4_ERR_QPID: 1037 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1038 *ecode = RDMAP_STAG_NOT_ASSOC; 1039 break; 1040 case T4_ERR_ACCESS: 1041 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1042 *ecode = RDMAP_ACC_VIOL; 1043 break; 1044 case T4_ERR_WRAP: 1045 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1046 *ecode = RDMAP_TO_WRAP; 1047 break; 1048 case T4_ERR_BOUND: 1049 if (tagged) { 1050 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1051 *ecode = DDPT_BASE_BOUNDS; 1052 } else { 1053 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1054 *ecode = RDMAP_BASE_BOUNDS; 1055 } 1056 break; 1057 case T4_ERR_INVALIDATE_SHARED_MR: 1058 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 1059 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1060 *ecode = RDMAP_CANT_INV_STAG; 1061 break; 1062 case T4_ERR_ECC: 1063 case T4_ERR_ECC_PSTAG: 1064 case T4_ERR_INTERNAL_ERR: 1065 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 1066 *ecode = 0; 1067 break; 1068 case T4_ERR_OUT_OF_RQE: 1069 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1070 *ecode = DDPU_INV_MSN_NOBUF; 1071 break; 1072 case T4_ERR_PBL_ADDR_BOUND: 1073 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1074 *ecode = DDPT_BASE_BOUNDS; 1075 break; 1076 case T4_ERR_CRC: 1077 *layer_type = LAYER_MPA|DDP_LLP; 1078 *ecode = MPA_CRC_ERR; 1079 break; 1080 case T4_ERR_MARKER: 1081 *layer_type = LAYER_MPA|DDP_LLP; 1082 *ecode = MPA_MARKER_ERR; 1083 break; 1084 case T4_ERR_PDU_LEN_ERR: 1085 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1086 *ecode = DDPU_MSG_TOOBIG; 1087 break; 1088 case T4_ERR_DDP_VERSION: 1089 if (tagged) { 1090 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1091 *ecode = DDPT_INV_VERS; 1092 } else { 1093 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1094 *ecode = DDPU_INV_VERS; 1095 } 1096 break; 1097 case T4_ERR_RDMA_VERSION: 1098 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1099 *ecode = RDMAP_INV_VERS; 1100 break; 1101 case T4_ERR_OPCODE: 1102 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1103 *ecode = RDMAP_INV_OPCODE; 1104 break; 1105 case T4_ERR_DDP_QUEUE_NUM: 1106 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1107 *ecode = DDPU_INV_QN; 1108 break; 1109 case T4_ERR_MSN: 1110 case T4_ERR_MSN_GAP: 1111 case T4_ERR_MSN_RANGE: 1112 case T4_ERR_IRD_OVERFLOW: 1113 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1114 *ecode = DDPU_INV_MSN_RANGE; 1115 break; 1116 case T4_ERR_TBIT: 1117 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 1118 *ecode = 0; 1119 break; 1120 case T4_ERR_MO: 1121 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1122 *ecode = DDPU_INV_MO; 1123 break; 1124 default: 1125 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1126 *ecode = 0; 1127 break; 1128 } 1129 } 1130 1131 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 1132 gfp_t gfp) 1133 { 1134 struct fw_ri_wr *wqe; 1135 struct sk_buff *skb; 1136 struct terminate_message *term; 1137 1138 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1139 qhp->ep->hwtid); 1140 1141 skb = skb_dequeue(&qhp->ep->com.ep_skb_list); 1142 if (WARN_ON(!skb)) 1143 return; 1144 1145 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1146 1147 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1148 memset(wqe, 0, sizeof *wqe); 1149 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR)); 1150 wqe->flowid_len16 = cpu_to_be32( 1151 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1152 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1153 1154 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 1155 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 1156 term = (struct terminate_message *)wqe->u.terminate.termmsg; 1157 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 1158 term->layer_etype = qhp->attr.layer_etype; 1159 term->ecode = qhp->attr.ecode; 1160 } else 1161 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 1162 c4iw_ofld_send(&qhp->rhp->rdev, skb); 1163 } 1164 1165 /* 1166 * Assumes qhp lock is held. 1167 */ 1168 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1169 struct c4iw_cq *schp) 1170 { 1171 int count; 1172 int rq_flushed, sq_flushed; 1173 unsigned long flag; 1174 1175 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 1176 1177 /* locking hierarchy: cq lock first, then qp lock. */ 1178 spin_lock_irqsave(&rchp->lock, flag); 1179 spin_lock(&qhp->lock); 1180 1181 if (qhp->wq.flushed) { 1182 spin_unlock(&qhp->lock); 1183 spin_unlock_irqrestore(&rchp->lock, flag); 1184 return; 1185 } 1186 qhp->wq.flushed = 1; 1187 1188 c4iw_flush_hw_cq(rchp); 1189 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1190 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1191 spin_unlock(&qhp->lock); 1192 spin_unlock_irqrestore(&rchp->lock, flag); 1193 1194 /* locking hierarchy: cq lock first, then qp lock. */ 1195 spin_lock_irqsave(&schp->lock, flag); 1196 spin_lock(&qhp->lock); 1197 if (schp != rchp) 1198 c4iw_flush_hw_cq(schp); 1199 sq_flushed = c4iw_flush_sq(qhp); 1200 spin_unlock(&qhp->lock); 1201 spin_unlock_irqrestore(&schp->lock, flag); 1202 1203 if (schp == rchp) { 1204 if (t4_clear_cq_armed(&rchp->cq) && 1205 (rq_flushed || sq_flushed)) { 1206 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1207 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1208 rchp->ibcq.cq_context); 1209 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1210 } 1211 } else { 1212 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { 1213 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1214 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1215 rchp->ibcq.cq_context); 1216 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1217 } 1218 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { 1219 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1220 (*schp->ibcq.comp_handler)(&schp->ibcq, 1221 schp->ibcq.cq_context); 1222 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1223 } 1224 } 1225 } 1226 1227 static void flush_qp(struct c4iw_qp *qhp) 1228 { 1229 struct c4iw_cq *rchp, *schp; 1230 unsigned long flag; 1231 1232 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1233 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1234 1235 t4_set_wq_in_error(&qhp->wq); 1236 if (qhp->ibqp.uobject) { 1237 t4_set_cq_in_error(&rchp->cq); 1238 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1239 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1240 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1241 if (schp != rchp) { 1242 t4_set_cq_in_error(&schp->cq); 1243 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1244 (*schp->ibcq.comp_handler)(&schp->ibcq, 1245 schp->ibcq.cq_context); 1246 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1247 } 1248 return; 1249 } 1250 __flush_qp(qhp, rchp, schp); 1251 } 1252 1253 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1254 struct c4iw_ep *ep) 1255 { 1256 struct fw_ri_wr *wqe; 1257 int ret; 1258 struct sk_buff *skb; 1259 1260 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1261 ep->hwtid); 1262 1263 skb = skb_dequeue(&ep->com.ep_skb_list); 1264 if (WARN_ON(!skb)) 1265 return -ENOMEM; 1266 1267 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); 1268 1269 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1270 memset(wqe, 0, sizeof *wqe); 1271 wqe->op_compl = cpu_to_be32( 1272 FW_WR_OP_V(FW_RI_INIT_WR) | 1273 FW_WR_COMPL_F); 1274 wqe->flowid_len16 = cpu_to_be32( 1275 FW_WR_FLOWID_V(ep->hwtid) | 1276 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1277 wqe->cookie = (uintptr_t)&ep->com.wr_wait; 1278 1279 wqe->u.fini.type = FW_RI_TYPE_FINI; 1280 ret = c4iw_ofld_send(&rhp->rdev, skb); 1281 if (ret) 1282 goto out; 1283 1284 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid, 1285 qhp->wq.sq.qid, __func__); 1286 out: 1287 PDBG("%s ret %d\n", __func__, ret); 1288 return ret; 1289 } 1290 1291 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1292 { 1293 PDBG("%s p2p_type = %d\n", __func__, p2p_type); 1294 memset(&init->u, 0, sizeof init->u); 1295 switch (p2p_type) { 1296 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1297 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1298 init->u.write.stag_sink = cpu_to_be32(1); 1299 init->u.write.to_sink = cpu_to_be64(1); 1300 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1301 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1302 sizeof(struct fw_ri_immd), 1303 16); 1304 break; 1305 case FW_RI_INIT_P2PTYPE_READ_REQ: 1306 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1307 init->u.read.stag_src = cpu_to_be32(1); 1308 init->u.read.to_src_lo = cpu_to_be32(1); 1309 init->u.read.stag_sink = cpu_to_be32(1); 1310 init->u.read.to_sink_lo = cpu_to_be32(1); 1311 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1312 break; 1313 } 1314 } 1315 1316 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1317 { 1318 struct fw_ri_wr *wqe; 1319 int ret; 1320 struct sk_buff *skb; 1321 1322 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp, 1323 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord); 1324 1325 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1326 if (!skb) { 1327 ret = -ENOMEM; 1328 goto out; 1329 } 1330 ret = alloc_ird(rhp, qhp->attr.max_ird); 1331 if (ret) { 1332 qhp->attr.max_ird = 0; 1333 kfree_skb(skb); 1334 goto out; 1335 } 1336 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1337 1338 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1339 memset(wqe, 0, sizeof *wqe); 1340 wqe->op_compl = cpu_to_be32( 1341 FW_WR_OP_V(FW_RI_INIT_WR) | 1342 FW_WR_COMPL_F); 1343 wqe->flowid_len16 = cpu_to_be32( 1344 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1345 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1346 1347 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait; 1348 1349 wqe->u.init.type = FW_RI_TYPE_INIT; 1350 wqe->u.init.mpareqbit_p2ptype = 1351 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) | 1352 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type); 1353 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1354 if (qhp->attr.mpa_attr.recv_marker_enabled) 1355 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1356 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1357 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1358 if (qhp->attr.mpa_attr.crc_enabled) 1359 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1360 1361 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1362 FW_RI_QP_RDMA_WRITE_ENABLE | 1363 FW_RI_QP_BIND_ENABLE; 1364 if (!qhp->ibqp.uobject) 1365 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1366 FW_RI_QP_STAG0_ENABLE; 1367 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1368 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1369 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1370 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1371 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1372 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1373 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1374 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1375 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1376 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq); 1377 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq); 1378 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1379 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1380 rhp->rdev.lldi.vr->rq.start); 1381 if (qhp->attr.mpa_attr.initiator) 1382 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1383 1384 ret = c4iw_ofld_send(&rhp->rdev, skb); 1385 if (ret) 1386 goto err1; 1387 1388 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait, 1389 qhp->ep->hwtid, qhp->wq.sq.qid, __func__); 1390 if (!ret) 1391 goto out; 1392 err1: 1393 free_ird(rhp, qhp->attr.max_ird); 1394 out: 1395 PDBG("%s ret %d\n", __func__, ret); 1396 return ret; 1397 } 1398 1399 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1400 enum c4iw_qp_attr_mask mask, 1401 struct c4iw_qp_attributes *attrs, 1402 int internal) 1403 { 1404 int ret = 0; 1405 struct c4iw_qp_attributes newattr = qhp->attr; 1406 int disconnect = 0; 1407 int terminate = 0; 1408 int abort = 0; 1409 int free = 0; 1410 struct c4iw_ep *ep = NULL; 1411 1412 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__, 1413 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1414 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1415 1416 mutex_lock(&qhp->mutex); 1417 1418 /* Process attr changes if in IDLE */ 1419 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1420 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1421 ret = -EIO; 1422 goto out; 1423 } 1424 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1425 newattr.enable_rdma_read = attrs->enable_rdma_read; 1426 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1427 newattr.enable_rdma_write = attrs->enable_rdma_write; 1428 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1429 newattr.enable_bind = attrs->enable_bind; 1430 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1431 if (attrs->max_ord > c4iw_max_read_depth) { 1432 ret = -EINVAL; 1433 goto out; 1434 } 1435 newattr.max_ord = attrs->max_ord; 1436 } 1437 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1438 if (attrs->max_ird > cur_max_read_depth(rhp)) { 1439 ret = -EINVAL; 1440 goto out; 1441 } 1442 newattr.max_ird = attrs->max_ird; 1443 } 1444 qhp->attr = newattr; 1445 } 1446 1447 if (mask & C4IW_QP_ATTR_SQ_DB) { 1448 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc); 1449 goto out; 1450 } 1451 if (mask & C4IW_QP_ATTR_RQ_DB) { 1452 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc); 1453 goto out; 1454 } 1455 1456 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1457 goto out; 1458 if (qhp->attr.state == attrs->next_state) 1459 goto out; 1460 1461 switch (qhp->attr.state) { 1462 case C4IW_QP_STATE_IDLE: 1463 switch (attrs->next_state) { 1464 case C4IW_QP_STATE_RTS: 1465 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1466 ret = -EINVAL; 1467 goto out; 1468 } 1469 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1470 ret = -EINVAL; 1471 goto out; 1472 } 1473 qhp->attr.mpa_attr = attrs->mpa_attr; 1474 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1475 qhp->ep = qhp->attr.llp_stream_handle; 1476 set_state(qhp, C4IW_QP_STATE_RTS); 1477 1478 /* 1479 * Ref the endpoint here and deref when we 1480 * disassociate the endpoint from the QP. This 1481 * happens in CLOSING->IDLE transition or *->ERROR 1482 * transition. 1483 */ 1484 c4iw_get_ep(&qhp->ep->com); 1485 ret = rdma_init(rhp, qhp); 1486 if (ret) 1487 goto err; 1488 break; 1489 case C4IW_QP_STATE_ERROR: 1490 set_state(qhp, C4IW_QP_STATE_ERROR); 1491 flush_qp(qhp); 1492 break; 1493 default: 1494 ret = -EINVAL; 1495 goto out; 1496 } 1497 break; 1498 case C4IW_QP_STATE_RTS: 1499 switch (attrs->next_state) { 1500 case C4IW_QP_STATE_CLOSING: 1501 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1502 t4_set_wq_in_error(&qhp->wq); 1503 set_state(qhp, C4IW_QP_STATE_CLOSING); 1504 ep = qhp->ep; 1505 if (!internal) { 1506 abort = 0; 1507 disconnect = 1; 1508 c4iw_get_ep(&qhp->ep->com); 1509 } 1510 ret = rdma_fini(rhp, qhp, ep); 1511 if (ret) 1512 goto err; 1513 break; 1514 case C4IW_QP_STATE_TERMINATE: 1515 t4_set_wq_in_error(&qhp->wq); 1516 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1517 qhp->attr.layer_etype = attrs->layer_etype; 1518 qhp->attr.ecode = attrs->ecode; 1519 ep = qhp->ep; 1520 if (!internal) { 1521 c4iw_get_ep(&qhp->ep->com); 1522 terminate = 1; 1523 disconnect = 1; 1524 } else { 1525 terminate = qhp->attr.send_term; 1526 ret = rdma_fini(rhp, qhp, ep); 1527 if (ret) 1528 goto err; 1529 } 1530 break; 1531 case C4IW_QP_STATE_ERROR: 1532 t4_set_wq_in_error(&qhp->wq); 1533 set_state(qhp, C4IW_QP_STATE_ERROR); 1534 if (!internal) { 1535 abort = 1; 1536 disconnect = 1; 1537 ep = qhp->ep; 1538 c4iw_get_ep(&qhp->ep->com); 1539 } 1540 goto err; 1541 break; 1542 default: 1543 ret = -EINVAL; 1544 goto out; 1545 } 1546 break; 1547 case C4IW_QP_STATE_CLOSING: 1548 if (!internal) { 1549 ret = -EINVAL; 1550 goto out; 1551 } 1552 switch (attrs->next_state) { 1553 case C4IW_QP_STATE_IDLE: 1554 flush_qp(qhp); 1555 set_state(qhp, C4IW_QP_STATE_IDLE); 1556 qhp->attr.llp_stream_handle = NULL; 1557 c4iw_put_ep(&qhp->ep->com); 1558 qhp->ep = NULL; 1559 wake_up(&qhp->wait); 1560 break; 1561 case C4IW_QP_STATE_ERROR: 1562 goto err; 1563 default: 1564 ret = -EINVAL; 1565 goto err; 1566 } 1567 break; 1568 case C4IW_QP_STATE_ERROR: 1569 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1570 ret = -EINVAL; 1571 goto out; 1572 } 1573 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1574 ret = -EINVAL; 1575 goto out; 1576 } 1577 set_state(qhp, C4IW_QP_STATE_IDLE); 1578 break; 1579 case C4IW_QP_STATE_TERMINATE: 1580 if (!internal) { 1581 ret = -EINVAL; 1582 goto out; 1583 } 1584 goto err; 1585 break; 1586 default: 1587 printk(KERN_ERR "%s in a bad state %d\n", 1588 __func__, qhp->attr.state); 1589 ret = -EINVAL; 1590 goto err; 1591 break; 1592 } 1593 goto out; 1594 err: 1595 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep, 1596 qhp->wq.sq.qid); 1597 1598 /* disassociate the LLP connection */ 1599 qhp->attr.llp_stream_handle = NULL; 1600 if (!ep) 1601 ep = qhp->ep; 1602 qhp->ep = NULL; 1603 set_state(qhp, C4IW_QP_STATE_ERROR); 1604 free = 1; 1605 abort = 1; 1606 BUG_ON(!ep); 1607 flush_qp(qhp); 1608 wake_up(&qhp->wait); 1609 out: 1610 mutex_unlock(&qhp->mutex); 1611 1612 if (terminate) 1613 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1614 1615 /* 1616 * If disconnect is 1, then we need to initiate a disconnect 1617 * on the EP. This can be a normal close (RTS->CLOSING) or 1618 * an abnormal close (RTS/CLOSING->ERROR). 1619 */ 1620 if (disconnect) { 1621 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1622 GFP_KERNEL); 1623 c4iw_put_ep(&ep->com); 1624 } 1625 1626 /* 1627 * If free is 1, then we've disassociated the EP from the QP 1628 * and we need to dereference the EP. 1629 */ 1630 if (free) 1631 c4iw_put_ep(&ep->com); 1632 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1633 return ret; 1634 } 1635 1636 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1637 { 1638 struct c4iw_dev *rhp; 1639 struct c4iw_qp *qhp; 1640 struct c4iw_qp_attributes attrs; 1641 struct c4iw_ucontext *ucontext; 1642 1643 qhp = to_c4iw_qp(ib_qp); 1644 rhp = qhp->rhp; 1645 1646 attrs.next_state = C4IW_QP_STATE_ERROR; 1647 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1648 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1649 else 1650 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1651 wait_event(qhp->wait, !qhp->ep); 1652 1653 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1654 1655 spin_lock_irq(&rhp->lock); 1656 if (!list_empty(&qhp->db_fc_entry)) 1657 list_del_init(&qhp->db_fc_entry); 1658 spin_unlock_irq(&rhp->lock); 1659 free_ird(rhp, qhp->attr.max_ird); 1660 1661 ucontext = ib_qp->uobject ? 1662 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1663 destroy_qp(&rhp->rdev, &qhp->wq, 1664 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1665 1666 c4iw_qp_rem_ref(ib_qp); 1667 1668 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid); 1669 return 0; 1670 } 1671 1672 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1673 struct ib_udata *udata) 1674 { 1675 struct c4iw_dev *rhp; 1676 struct c4iw_qp *qhp; 1677 struct c4iw_pd *php; 1678 struct c4iw_cq *schp; 1679 struct c4iw_cq *rchp; 1680 struct c4iw_create_qp_resp uresp; 1681 unsigned int sqsize, rqsize; 1682 struct c4iw_ucontext *ucontext; 1683 int ret; 1684 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm; 1685 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL; 1686 1687 PDBG("%s ib_pd %p\n", __func__, pd); 1688 1689 if (attrs->qp_type != IB_QPT_RC) 1690 return ERR_PTR(-EINVAL); 1691 1692 php = to_c4iw_pd(pd); 1693 rhp = php->rhp; 1694 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1695 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1696 if (!schp || !rchp) 1697 return ERR_PTR(-EINVAL); 1698 1699 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1700 return ERR_PTR(-EINVAL); 1701 1702 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size) 1703 return ERR_PTR(-E2BIG); 1704 rqsize = attrs->cap.max_recv_wr + 1; 1705 if (rqsize < 8) 1706 rqsize = 8; 1707 1708 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size) 1709 return ERR_PTR(-E2BIG); 1710 sqsize = attrs->cap.max_send_wr + 1; 1711 if (sqsize < 8) 1712 sqsize = 8; 1713 1714 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1715 1716 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1717 if (!qhp) 1718 return ERR_PTR(-ENOMEM); 1719 qhp->wq.sq.size = sqsize; 1720 qhp->wq.sq.memsize = 1721 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1722 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64); 1723 qhp->wq.sq.flush_cidx = -1; 1724 qhp->wq.rq.size = rqsize; 1725 qhp->wq.rq.memsize = 1726 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1727 sizeof(*qhp->wq.rq.queue); 1728 1729 if (ucontext) { 1730 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1731 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1732 } 1733 1734 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1735 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1736 if (ret) 1737 goto err1; 1738 1739 attrs->cap.max_recv_wr = rqsize - 1; 1740 attrs->cap.max_send_wr = sqsize - 1; 1741 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1742 1743 qhp->rhp = rhp; 1744 qhp->attr.pd = php->pdid; 1745 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1746 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1747 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1748 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1749 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1750 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1751 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1752 qhp->attr.state = C4IW_QP_STATE_IDLE; 1753 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1754 qhp->attr.enable_rdma_read = 1; 1755 qhp->attr.enable_rdma_write = 1; 1756 qhp->attr.enable_bind = 1; 1757 qhp->attr.max_ord = 0; 1758 qhp->attr.max_ird = 0; 1759 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1760 spin_lock_init(&qhp->lock); 1761 init_completion(&qhp->sq_drained); 1762 init_completion(&qhp->rq_drained); 1763 mutex_init(&qhp->mutex); 1764 init_waitqueue_head(&qhp->wait); 1765 kref_init(&qhp->kref); 1766 1767 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1768 if (ret) 1769 goto err2; 1770 1771 if (udata) { 1772 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1773 if (!sq_key_mm) { 1774 ret = -ENOMEM; 1775 goto err3; 1776 } 1777 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1778 if (!rq_key_mm) { 1779 ret = -ENOMEM; 1780 goto err4; 1781 } 1782 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1783 if (!sq_db_key_mm) { 1784 ret = -ENOMEM; 1785 goto err5; 1786 } 1787 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1788 if (!rq_db_key_mm) { 1789 ret = -ENOMEM; 1790 goto err6; 1791 } 1792 if (t4_sq_onchip(&qhp->wq.sq)) { 1793 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm), 1794 GFP_KERNEL); 1795 if (!ma_sync_key_mm) { 1796 ret = -ENOMEM; 1797 goto err7; 1798 } 1799 uresp.flags = C4IW_QPF_ONCHIP; 1800 } else 1801 uresp.flags = 0; 1802 uresp.qid_mask = rhp->rdev.qpmask; 1803 uresp.sqid = qhp->wq.sq.qid; 1804 uresp.sq_size = qhp->wq.sq.size; 1805 uresp.sq_memsize = qhp->wq.sq.memsize; 1806 uresp.rqid = qhp->wq.rq.qid; 1807 uresp.rq_size = qhp->wq.rq.size; 1808 uresp.rq_memsize = qhp->wq.rq.memsize; 1809 spin_lock(&ucontext->mmap_lock); 1810 if (ma_sync_key_mm) { 1811 uresp.ma_sync_key = ucontext->key; 1812 ucontext->key += PAGE_SIZE; 1813 } else { 1814 uresp.ma_sync_key = 0; 1815 } 1816 uresp.sq_key = ucontext->key; 1817 ucontext->key += PAGE_SIZE; 1818 uresp.rq_key = ucontext->key; 1819 ucontext->key += PAGE_SIZE; 1820 uresp.sq_db_gts_key = ucontext->key; 1821 ucontext->key += PAGE_SIZE; 1822 uresp.rq_db_gts_key = ucontext->key; 1823 ucontext->key += PAGE_SIZE; 1824 spin_unlock(&ucontext->mmap_lock); 1825 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1826 if (ret) 1827 goto err8; 1828 sq_key_mm->key = uresp.sq_key; 1829 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1830 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1831 insert_mmap(ucontext, sq_key_mm); 1832 rq_key_mm->key = uresp.rq_key; 1833 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue); 1834 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1835 insert_mmap(ucontext, rq_key_mm); 1836 sq_db_key_mm->key = uresp.sq_db_gts_key; 1837 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa; 1838 sq_db_key_mm->len = PAGE_SIZE; 1839 insert_mmap(ucontext, sq_db_key_mm); 1840 rq_db_key_mm->key = uresp.rq_db_gts_key; 1841 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa; 1842 rq_db_key_mm->len = PAGE_SIZE; 1843 insert_mmap(ucontext, rq_db_key_mm); 1844 if (ma_sync_key_mm) { 1845 ma_sync_key_mm->key = uresp.ma_sync_key; 1846 ma_sync_key_mm->addr = 1847 (pci_resource_start(rhp->rdev.lldi.pdev, 0) + 1848 PCIE_MA_SYNC_A) & PAGE_MASK; 1849 ma_sync_key_mm->len = PAGE_SIZE; 1850 insert_mmap(ucontext, ma_sync_key_mm); 1851 } 1852 } 1853 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1854 init_timer(&(qhp->timer)); 1855 INIT_LIST_HEAD(&qhp->db_fc_entry); 1856 PDBG("%s sq id %u size %u memsize %zu num_entries %u " 1857 "rq id %u size %u memsize %zu num_entries %u\n", __func__, 1858 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize, 1859 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size, 1860 qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1861 return &qhp->ibqp; 1862 err8: 1863 kfree(ma_sync_key_mm); 1864 err7: 1865 kfree(rq_db_key_mm); 1866 err6: 1867 kfree(sq_db_key_mm); 1868 err5: 1869 kfree(rq_key_mm); 1870 err4: 1871 kfree(sq_key_mm); 1872 err3: 1873 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1874 err2: 1875 destroy_qp(&rhp->rdev, &qhp->wq, 1876 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1877 err1: 1878 kfree(qhp); 1879 return ERR_PTR(ret); 1880 } 1881 1882 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1883 int attr_mask, struct ib_udata *udata) 1884 { 1885 struct c4iw_dev *rhp; 1886 struct c4iw_qp *qhp; 1887 enum c4iw_qp_attr_mask mask = 0; 1888 struct c4iw_qp_attributes attrs; 1889 1890 PDBG("%s ib_qp %p\n", __func__, ibqp); 1891 1892 /* iwarp does not support the RTR state */ 1893 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1894 attr_mask &= ~IB_QP_STATE; 1895 1896 /* Make sure we still have something left to do */ 1897 if (!attr_mask) 1898 return 0; 1899 1900 memset(&attrs, 0, sizeof attrs); 1901 qhp = to_c4iw_qp(ibqp); 1902 rhp = qhp->rhp; 1903 1904 attrs.next_state = c4iw_convert_state(attr->qp_state); 1905 attrs.enable_rdma_read = (attr->qp_access_flags & 1906 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1907 attrs.enable_rdma_write = (attr->qp_access_flags & 1908 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1909 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1910 1911 1912 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1913 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1914 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1915 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1916 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1917 1918 /* 1919 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 1920 * ringing the queue db when we're in DB_FULL mode. 1921 * Only allow this on T4 devices. 1922 */ 1923 attrs.sq_db_inc = attr->sq_psn; 1924 attrs.rq_db_inc = attr->rq_psn; 1925 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 1926 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 1927 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) && 1928 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB))) 1929 return -EINVAL; 1930 1931 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1932 } 1933 1934 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1935 { 1936 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn); 1937 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1938 } 1939 1940 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1941 int attr_mask, struct ib_qp_init_attr *init_attr) 1942 { 1943 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1944 1945 memset(attr, 0, sizeof *attr); 1946 memset(init_attr, 0, sizeof *init_attr); 1947 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1948 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1949 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1950 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1951 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1952 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1953 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1954 return 0; 1955 } 1956 1957 static void move_qp_to_err(struct c4iw_qp *qp) 1958 { 1959 struct c4iw_qp_attributes attrs = { .next_state = C4IW_QP_STATE_ERROR }; 1960 1961 (void)c4iw_modify_qp(qp->rhp, qp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1962 } 1963 1964 void c4iw_drain_sq(struct ib_qp *ibqp) 1965 { 1966 struct c4iw_qp *qp = to_c4iw_qp(ibqp); 1967 unsigned long flag; 1968 bool need_to_wait; 1969 1970 move_qp_to_err(qp); 1971 spin_lock_irqsave(&qp->lock, flag); 1972 need_to_wait = !t4_sq_empty(&qp->wq); 1973 spin_unlock_irqrestore(&qp->lock, flag); 1974 1975 if (need_to_wait) 1976 wait_for_completion(&qp->sq_drained); 1977 } 1978 1979 void c4iw_drain_rq(struct ib_qp *ibqp) 1980 { 1981 struct c4iw_qp *qp = to_c4iw_qp(ibqp); 1982 unsigned long flag; 1983 bool need_to_wait; 1984 1985 move_qp_to_err(qp); 1986 spin_lock_irqsave(&qp->lock, flag); 1987 need_to_wait = !t4_rq_empty(&qp->wq); 1988 spin_unlock_irqrestore(&qp->lock, flag); 1989 1990 if (need_to_wait) 1991 wait_for_completion(&qp->rq_drained); 1992 } 1993