1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <linux/moduleparam.h> 35 #include <rdma/ib_umem.h> 36 #include <linux/atomic.h> 37 38 #include "iw_cxgb4.h" 39 40 int use_dsgl = 0; 41 module_param(use_dsgl, int, 0644); 42 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=0)"); 43 44 #define T4_ULPTX_MIN_IO 32 45 #define C4IW_MAX_INLINE_SIZE 96 46 #define T4_ULPTX_MAX_DMA 1024 47 #define C4IW_INLINE_THRESHOLD 128 48 49 static int inline_threshold = C4IW_INLINE_THRESHOLD; 50 module_param(inline_threshold, int, 0644); 51 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)"); 52 53 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length) 54 { 55 return (is_t4(dev->rdev.lldi.adapter_type) || 56 is_t5(dev->rdev.lldi.adapter_type)) && 57 length >= 8*1024*1024*1024ULL; 58 } 59 60 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, 61 u32 len, dma_addr_t data, int wait) 62 { 63 struct sk_buff *skb; 64 struct ulp_mem_io *req; 65 struct ulptx_sgl *sgl; 66 u8 wr_len; 67 int ret = 0; 68 struct c4iw_wr_wait wr_wait; 69 70 addr &= 0x7FFFFFF; 71 72 if (wait) 73 c4iw_init_wr_wait(&wr_wait); 74 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16); 75 76 skb = alloc_skb(wr_len, GFP_KERNEL); 77 if (!skb) 78 return -ENOMEM; 79 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 80 81 req = (struct ulp_mem_io *)__skb_put(skb, wr_len); 82 memset(req, 0, wr_len); 83 INIT_ULPTX_WR(req, wr_len, 0, 0); 84 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 85 (wait ? FW_WR_COMPL_F : 0)); 86 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L; 87 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 88 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE)); 89 req->cmd |= cpu_to_be32(T5_ULP_MEMIO_ORDER_V(1)); 90 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5)); 91 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16)); 92 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr)); 93 94 sgl = (struct ulptx_sgl *)(req + 1); 95 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 96 ULPTX_NSGE_V(1)); 97 sgl->len0 = cpu_to_be32(len); 98 sgl->addr0 = cpu_to_be64(data); 99 100 ret = c4iw_ofld_send(rdev, skb); 101 if (ret) 102 return ret; 103 if (wait) 104 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 105 return ret; 106 } 107 108 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, 109 void *data) 110 { 111 struct sk_buff *skb; 112 struct ulp_mem_io *req; 113 struct ulptx_idata *sc; 114 u8 wr_len, *to_dp, *from_dp; 115 int copy_len, num_wqe, i, ret = 0; 116 struct c4iw_wr_wait wr_wait; 117 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE)); 118 119 if (is_t4(rdev->lldi.adapter_type)) 120 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F); 121 else 122 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F); 123 124 addr &= 0x7FFFFFF; 125 PDBG("%s addr 0x%x len %u\n", __func__, addr, len); 126 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 127 c4iw_init_wr_wait(&wr_wait); 128 for (i = 0; i < num_wqe; i++) { 129 130 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE : 131 len; 132 wr_len = roundup(sizeof *req + sizeof *sc + 133 roundup(copy_len, T4_ULPTX_MIN_IO), 16); 134 135 skb = alloc_skb(wr_len, GFP_KERNEL); 136 if (!skb) 137 return -ENOMEM; 138 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 139 140 req = (struct ulp_mem_io *)__skb_put(skb, wr_len); 141 memset(req, 0, wr_len); 142 INIT_ULPTX_WR(req, wr_len, 0, 0); 143 144 if (i == (num_wqe-1)) { 145 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 146 FW_WR_COMPL_F); 147 req->wr.wr_lo = (__force __be64)&wr_wait; 148 } else 149 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR)); 150 req->wr.wr_mid = cpu_to_be32( 151 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 152 153 req->cmd = cmd; 154 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V( 155 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); 156 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 157 16)); 158 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3)); 159 160 sc = (struct ulptx_idata *)(req + 1); 161 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM)); 162 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO)); 163 164 to_dp = (u8 *)(sc + 1); 165 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE; 166 if (data) 167 memcpy(to_dp, from_dp, copy_len); 168 else 169 memset(to_dp, 0, copy_len); 170 if (copy_len % T4_ULPTX_MIN_IO) 171 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 172 (copy_len % T4_ULPTX_MIN_IO)); 173 ret = c4iw_ofld_send(rdev, skb); 174 if (ret) 175 return ret; 176 len -= C4IW_MAX_INLINE_SIZE; 177 } 178 179 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 180 return ret; 181 } 182 183 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data) 184 { 185 u32 remain = len; 186 u32 dmalen; 187 int ret = 0; 188 dma_addr_t daddr; 189 dma_addr_t save; 190 191 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE); 192 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr)) 193 return -1; 194 save = daddr; 195 196 while (remain > inline_threshold) { 197 if (remain < T4_ULPTX_MAX_DMA) { 198 if (remain & ~T4_ULPTX_MIN_IO) 199 dmalen = remain & ~(T4_ULPTX_MIN_IO-1); 200 else 201 dmalen = remain; 202 } else 203 dmalen = T4_ULPTX_MAX_DMA; 204 remain -= dmalen; 205 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr, 206 !remain); 207 if (ret) 208 goto out; 209 addr += dmalen >> 5; 210 data += dmalen; 211 daddr += dmalen; 212 } 213 if (remain) 214 ret = _c4iw_write_mem_inline(rdev, addr, remain, data); 215 out: 216 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE); 217 return ret; 218 } 219 220 /* 221 * write len bytes of data into addr (32B aligned address) 222 * If data is NULL, clear len byte of memory to zero. 223 */ 224 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, 225 void *data) 226 { 227 if (is_t5(rdev->lldi.adapter_type) && use_dsgl) { 228 if (len > inline_threshold) { 229 if (_c4iw_write_mem_dma(rdev, addr, len, data)) { 230 printk_ratelimited(KERN_WARNING 231 "%s: dma map" 232 " failure (non fatal)\n", 233 pci_name(rdev->lldi.pdev)); 234 return _c4iw_write_mem_inline(rdev, addr, len, 235 data); 236 } else 237 return 0; 238 } else 239 return _c4iw_write_mem_inline(rdev, addr, len, data); 240 } else 241 return _c4iw_write_mem_inline(rdev, addr, len, data); 242 } 243 244 /* 245 * Build and write a TPT entry. 246 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, 247 * pbl_size and pbl_addr 248 * OUT: stag index 249 */ 250 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, 251 u32 *stag, u8 stag_state, u32 pdid, 252 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 253 int bind_enabled, u32 zbva, u64 to, 254 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr) 255 { 256 int err; 257 struct fw_ri_tpte tpt; 258 u32 stag_idx; 259 static atomic_t key; 260 261 if (c4iw_fatal_error(rdev)) 262 return -EIO; 263 264 stag_state = stag_state > 0; 265 stag_idx = (*stag) >> 8; 266 267 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) { 268 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table); 269 if (!stag_idx) { 270 mutex_lock(&rdev->stats.lock); 271 rdev->stats.stag.fail++; 272 mutex_unlock(&rdev->stats.lock); 273 return -ENOMEM; 274 } 275 mutex_lock(&rdev->stats.lock); 276 rdev->stats.stag.cur += 32; 277 if (rdev->stats.stag.cur > rdev->stats.stag.max) 278 rdev->stats.stag.max = rdev->stats.stag.cur; 279 mutex_unlock(&rdev->stats.lock); 280 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 281 } 282 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n", 283 __func__, stag_state, type, pdid, stag_idx); 284 285 /* write TPT entry */ 286 if (reset_tpt_entry) 287 memset(&tpt, 0, sizeof(tpt)); 288 else { 289 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 290 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) | 291 FW_RI_TPTE_STAGSTATE_V(stag_state) | 292 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid)); 293 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) | 294 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) | 295 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO : 296 FW_RI_VA_BASED_TO))| 297 FW_RI_TPTE_PS_V(page_size)); 298 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32( 299 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3)); 300 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL)); 301 tpt.va_hi = cpu_to_be32((u32)(to >> 32)); 302 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL)); 303 tpt.dca_mwbcnt_pstag = cpu_to_be32(0); 304 tpt.len_hi = cpu_to_be32((u32)(len >> 32)); 305 } 306 err = write_adapter_mem(rdev, stag_idx + 307 (rdev->lldi.vr->stag.start >> 5), 308 sizeof(tpt), &tpt); 309 310 if (reset_tpt_entry) { 311 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 312 mutex_lock(&rdev->stats.lock); 313 rdev->stats.stag.cur -= 32; 314 mutex_unlock(&rdev->stats.lock); 315 } 316 return err; 317 } 318 319 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 320 u32 pbl_addr, u32 pbl_size) 321 { 322 int err; 323 324 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n", 325 __func__, pbl_addr, rdev->lldi.vr->pbl.start, 326 pbl_size); 327 328 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl); 329 return err; 330 } 331 332 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 333 u32 pbl_addr) 334 { 335 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 336 pbl_size, pbl_addr); 337 } 338 339 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid) 340 { 341 *stag = T4_STAG_UNSET; 342 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 343 0UL, 0, 0, 0, 0); 344 } 345 346 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag) 347 { 348 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 349 0); 350 } 351 352 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 353 u32 pbl_size, u32 pbl_addr) 354 { 355 *stag = T4_STAG_UNSET; 356 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 357 0UL, 0, 0, pbl_size, pbl_addr); 358 } 359 360 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 361 { 362 u32 mmid; 363 364 mhp->attr.state = 1; 365 mhp->attr.stag = stag; 366 mmid = stag >> 8; 367 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 368 PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp); 369 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid); 370 } 371 372 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 373 struct c4iw_mr *mhp, int shift) 374 { 375 u32 stag = T4_STAG_UNSET; 376 int ret; 377 378 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 379 FW_RI_STAG_NSMR, mhp->attr.len ? 380 mhp->attr.perms : 0, 381 mhp->attr.mw_bind_enable, mhp->attr.zbva, 382 mhp->attr.va_fbo, mhp->attr.len ? 383 mhp->attr.len : -1, shift - 12, 384 mhp->attr.pbl_size, mhp->attr.pbl_addr); 385 if (ret) 386 return ret; 387 388 ret = finish_mem_reg(mhp, stag); 389 if (ret) 390 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 391 mhp->attr.pbl_addr); 392 return ret; 393 } 394 395 static int reregister_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 396 struct c4iw_mr *mhp, int shift, int npages) 397 { 398 u32 stag; 399 int ret; 400 401 if (npages > mhp->attr.pbl_size) 402 return -ENOMEM; 403 404 stag = mhp->attr.stag; 405 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 406 FW_RI_STAG_NSMR, mhp->attr.perms, 407 mhp->attr.mw_bind_enable, mhp->attr.zbva, 408 mhp->attr.va_fbo, mhp->attr.len, shift - 12, 409 mhp->attr.pbl_size, mhp->attr.pbl_addr); 410 if (ret) 411 return ret; 412 413 ret = finish_mem_reg(mhp, stag); 414 if (ret) 415 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 416 mhp->attr.pbl_addr); 417 418 return ret; 419 } 420 421 static int alloc_pbl(struct c4iw_mr *mhp, int npages) 422 { 423 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, 424 npages << 3); 425 426 if (!mhp->attr.pbl_addr) 427 return -ENOMEM; 428 429 mhp->attr.pbl_size = npages; 430 431 return 0; 432 } 433 434 static int build_phys_page_list(struct ib_phys_buf *buffer_list, 435 int num_phys_buf, u64 *iova_start, 436 u64 *total_size, int *npages, 437 int *shift, __be64 **page_list) 438 { 439 u64 mask; 440 int i, j, n; 441 442 mask = 0; 443 *total_size = 0; 444 for (i = 0; i < num_phys_buf; ++i) { 445 if (i != 0 && buffer_list[i].addr & ~PAGE_MASK) 446 return -EINVAL; 447 if (i != 0 && i != num_phys_buf - 1 && 448 (buffer_list[i].size & ~PAGE_MASK)) 449 return -EINVAL; 450 *total_size += buffer_list[i].size; 451 if (i > 0) 452 mask |= buffer_list[i].addr; 453 else 454 mask |= buffer_list[i].addr & PAGE_MASK; 455 if (i != num_phys_buf - 1) 456 mask |= buffer_list[i].addr + buffer_list[i].size; 457 else 458 mask |= (buffer_list[i].addr + buffer_list[i].size + 459 PAGE_SIZE - 1) & PAGE_MASK; 460 } 461 462 if (*total_size > 0xFFFFFFFFULL) 463 return -ENOMEM; 464 465 /* Find largest page shift we can use to cover buffers */ 466 for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift)) 467 if ((1ULL << *shift) & mask) 468 break; 469 470 buffer_list[0].size += buffer_list[0].addr & ((1ULL << *shift) - 1); 471 buffer_list[0].addr &= ~0ull << *shift; 472 473 *npages = 0; 474 for (i = 0; i < num_phys_buf; ++i) 475 *npages += (buffer_list[i].size + 476 (1ULL << *shift) - 1) >> *shift; 477 478 if (!*npages) 479 return -EINVAL; 480 481 *page_list = kmalloc(sizeof(u64) * *npages, GFP_KERNEL); 482 if (!*page_list) 483 return -ENOMEM; 484 485 n = 0; 486 for (i = 0; i < num_phys_buf; ++i) 487 for (j = 0; 488 j < (buffer_list[i].size + (1ULL << *shift) - 1) >> *shift; 489 ++j) 490 (*page_list)[n++] = cpu_to_be64(buffer_list[i].addr + 491 ((u64) j << *shift)); 492 493 PDBG("%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d\n", 494 __func__, (unsigned long long)*iova_start, 495 (unsigned long long)mask, *shift, (unsigned long long)*total_size, 496 *npages); 497 498 return 0; 499 500 } 501 502 int c4iw_reregister_phys_mem(struct ib_mr *mr, int mr_rereg_mask, 503 struct ib_pd *pd, struct ib_phys_buf *buffer_list, 504 int num_phys_buf, int acc, u64 *iova_start) 505 { 506 507 struct c4iw_mr mh, *mhp; 508 struct c4iw_pd *php; 509 struct c4iw_dev *rhp; 510 __be64 *page_list = NULL; 511 int shift = 0; 512 u64 total_size; 513 int npages; 514 int ret; 515 516 PDBG("%s ib_mr %p ib_pd %p\n", __func__, mr, pd); 517 518 /* There can be no memory windows */ 519 if (atomic_read(&mr->usecnt)) 520 return -EINVAL; 521 522 mhp = to_c4iw_mr(mr); 523 rhp = mhp->rhp; 524 php = to_c4iw_pd(mr->pd); 525 526 /* make sure we are on the same adapter */ 527 if (rhp != php->rhp) 528 return -EINVAL; 529 530 memcpy(&mh, mhp, sizeof *mhp); 531 532 if (mr_rereg_mask & IB_MR_REREG_PD) 533 php = to_c4iw_pd(pd); 534 if (mr_rereg_mask & IB_MR_REREG_ACCESS) { 535 mh.attr.perms = c4iw_ib_to_tpt_access(acc); 536 mh.attr.mw_bind_enable = (acc & IB_ACCESS_MW_BIND) == 537 IB_ACCESS_MW_BIND; 538 } 539 if (mr_rereg_mask & IB_MR_REREG_TRANS) { 540 ret = build_phys_page_list(buffer_list, num_phys_buf, 541 iova_start, 542 &total_size, &npages, 543 &shift, &page_list); 544 if (ret) 545 return ret; 546 } 547 548 if (mr_exceeds_hw_limits(rhp, total_size)) { 549 kfree(page_list); 550 return -EINVAL; 551 } 552 553 ret = reregister_mem(rhp, php, &mh, shift, npages); 554 kfree(page_list); 555 if (ret) 556 return ret; 557 if (mr_rereg_mask & IB_MR_REREG_PD) 558 mhp->attr.pdid = php->pdid; 559 if (mr_rereg_mask & IB_MR_REREG_ACCESS) 560 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 561 if (mr_rereg_mask & IB_MR_REREG_TRANS) { 562 mhp->attr.zbva = 0; 563 mhp->attr.va_fbo = *iova_start; 564 mhp->attr.page_size = shift - 12; 565 mhp->attr.len = (u32) total_size; 566 mhp->attr.pbl_size = npages; 567 } 568 569 return 0; 570 } 571 572 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 573 struct ib_phys_buf *buffer_list, 574 int num_phys_buf, int acc, u64 *iova_start) 575 { 576 __be64 *page_list; 577 int shift; 578 u64 total_size; 579 int npages; 580 struct c4iw_dev *rhp; 581 struct c4iw_pd *php; 582 struct c4iw_mr *mhp; 583 int ret; 584 585 PDBG("%s ib_pd %p\n", __func__, pd); 586 php = to_c4iw_pd(pd); 587 rhp = php->rhp; 588 589 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 590 if (!mhp) 591 return ERR_PTR(-ENOMEM); 592 593 mhp->rhp = rhp; 594 595 /* First check that we have enough alignment */ 596 if ((*iova_start & ~PAGE_MASK) != (buffer_list[0].addr & ~PAGE_MASK)) { 597 ret = -EINVAL; 598 goto err; 599 } 600 601 if (num_phys_buf > 1 && 602 ((buffer_list[0].addr + buffer_list[0].size) & ~PAGE_MASK)) { 603 ret = -EINVAL; 604 goto err; 605 } 606 607 ret = build_phys_page_list(buffer_list, num_phys_buf, iova_start, 608 &total_size, &npages, &shift, 609 &page_list); 610 if (ret) 611 goto err; 612 613 if (mr_exceeds_hw_limits(rhp, total_size)) { 614 kfree(page_list); 615 ret = -EINVAL; 616 goto err; 617 } 618 619 ret = alloc_pbl(mhp, npages); 620 if (ret) { 621 kfree(page_list); 622 goto err; 623 } 624 625 ret = write_pbl(&mhp->rhp->rdev, page_list, mhp->attr.pbl_addr, 626 npages); 627 kfree(page_list); 628 if (ret) 629 goto err_pbl; 630 631 mhp->attr.pdid = php->pdid; 632 mhp->attr.zbva = 0; 633 634 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 635 mhp->attr.va_fbo = *iova_start; 636 mhp->attr.page_size = shift - 12; 637 638 mhp->attr.len = (u32) total_size; 639 mhp->attr.pbl_size = npages; 640 ret = register_mem(rhp, php, mhp, shift); 641 if (ret) 642 goto err_pbl; 643 644 return &mhp->ibmr; 645 646 err_pbl: 647 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 648 mhp->attr.pbl_size << 3); 649 650 err: 651 kfree(mhp); 652 return ERR_PTR(ret); 653 654 } 655 656 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 657 { 658 struct c4iw_dev *rhp; 659 struct c4iw_pd *php; 660 struct c4iw_mr *mhp; 661 int ret; 662 u32 stag = T4_STAG_UNSET; 663 664 PDBG("%s ib_pd %p\n", __func__, pd); 665 php = to_c4iw_pd(pd); 666 rhp = php->rhp; 667 668 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 669 if (!mhp) 670 return ERR_PTR(-ENOMEM); 671 672 mhp->rhp = rhp; 673 mhp->attr.pdid = php->pdid; 674 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 675 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND; 676 mhp->attr.zbva = 0; 677 mhp->attr.va_fbo = 0; 678 mhp->attr.page_size = 0; 679 mhp->attr.len = ~0ULL; 680 mhp->attr.pbl_size = 0; 681 682 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 683 FW_RI_STAG_NSMR, mhp->attr.perms, 684 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0); 685 if (ret) 686 goto err1; 687 688 ret = finish_mem_reg(mhp, stag); 689 if (ret) 690 goto err2; 691 return &mhp->ibmr; 692 err2: 693 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 694 mhp->attr.pbl_addr); 695 err1: 696 kfree(mhp); 697 return ERR_PTR(ret); 698 } 699 700 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 701 u64 virt, int acc, struct ib_udata *udata) 702 { 703 __be64 *pages; 704 int shift, n, len; 705 int i, k, entry; 706 int err = 0; 707 struct scatterlist *sg; 708 struct c4iw_dev *rhp; 709 struct c4iw_pd *php; 710 struct c4iw_mr *mhp; 711 712 PDBG("%s ib_pd %p\n", __func__, pd); 713 714 if (length == ~0ULL) 715 return ERR_PTR(-EINVAL); 716 717 if ((length + start) < start) 718 return ERR_PTR(-EINVAL); 719 720 php = to_c4iw_pd(pd); 721 rhp = php->rhp; 722 723 if (mr_exceeds_hw_limits(rhp, length)) 724 return ERR_PTR(-EINVAL); 725 726 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 727 if (!mhp) 728 return ERR_PTR(-ENOMEM); 729 730 mhp->rhp = rhp; 731 732 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0); 733 if (IS_ERR(mhp->umem)) { 734 err = PTR_ERR(mhp->umem); 735 kfree(mhp); 736 return ERR_PTR(err); 737 } 738 739 shift = ffs(mhp->umem->page_size) - 1; 740 741 n = mhp->umem->nmap; 742 err = alloc_pbl(mhp, n); 743 if (err) 744 goto err; 745 746 pages = (__be64 *) __get_free_page(GFP_KERNEL); 747 if (!pages) { 748 err = -ENOMEM; 749 goto err_pbl; 750 } 751 752 i = n = 0; 753 754 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) { 755 len = sg_dma_len(sg) >> shift; 756 for (k = 0; k < len; ++k) { 757 pages[i++] = cpu_to_be64(sg_dma_address(sg) + 758 mhp->umem->page_size * k); 759 if (i == PAGE_SIZE / sizeof *pages) { 760 err = write_pbl(&mhp->rhp->rdev, 761 pages, 762 mhp->attr.pbl_addr + (n << 3), i); 763 if (err) 764 goto pbl_done; 765 n += i; 766 i = 0; 767 } 768 } 769 } 770 771 if (i) 772 err = write_pbl(&mhp->rhp->rdev, pages, 773 mhp->attr.pbl_addr + (n << 3), i); 774 775 pbl_done: 776 free_page((unsigned long) pages); 777 if (err) 778 goto err_pbl; 779 780 mhp->attr.pdid = php->pdid; 781 mhp->attr.zbva = 0; 782 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 783 mhp->attr.va_fbo = virt; 784 mhp->attr.page_size = shift - 12; 785 mhp->attr.len = length; 786 787 err = register_mem(rhp, php, mhp, shift); 788 if (err) 789 goto err_pbl; 790 791 return &mhp->ibmr; 792 793 err_pbl: 794 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 795 mhp->attr.pbl_size << 3); 796 797 err: 798 ib_umem_release(mhp->umem); 799 kfree(mhp); 800 return ERR_PTR(err); 801 } 802 803 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type) 804 { 805 struct c4iw_dev *rhp; 806 struct c4iw_pd *php; 807 struct c4iw_mw *mhp; 808 u32 mmid; 809 u32 stag = 0; 810 int ret; 811 812 if (type != IB_MW_TYPE_1) 813 return ERR_PTR(-EINVAL); 814 815 php = to_c4iw_pd(pd); 816 rhp = php->rhp; 817 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 818 if (!mhp) 819 return ERR_PTR(-ENOMEM); 820 ret = allocate_window(&rhp->rdev, &stag, php->pdid); 821 if (ret) { 822 kfree(mhp); 823 return ERR_PTR(ret); 824 } 825 mhp->rhp = rhp; 826 mhp->attr.pdid = php->pdid; 827 mhp->attr.type = FW_RI_STAG_MW; 828 mhp->attr.stag = stag; 829 mmid = (stag) >> 8; 830 mhp->ibmw.rkey = stag; 831 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 832 deallocate_window(&rhp->rdev, mhp->attr.stag); 833 kfree(mhp); 834 return ERR_PTR(-ENOMEM); 835 } 836 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 837 return &(mhp->ibmw); 838 } 839 840 int c4iw_dealloc_mw(struct ib_mw *mw) 841 { 842 struct c4iw_dev *rhp; 843 struct c4iw_mw *mhp; 844 u32 mmid; 845 846 mhp = to_c4iw_mw(mw); 847 rhp = mhp->rhp; 848 mmid = (mw->rkey) >> 8; 849 remove_handle(rhp, &rhp->mmidr, mmid); 850 deallocate_window(&rhp->rdev, mhp->attr.stag); 851 kfree(mhp); 852 PDBG("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp); 853 return 0; 854 } 855 856 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth) 857 { 858 struct c4iw_dev *rhp; 859 struct c4iw_pd *php; 860 struct c4iw_mr *mhp; 861 u32 mmid; 862 u32 stag = 0; 863 int ret = 0; 864 865 php = to_c4iw_pd(pd); 866 rhp = php->rhp; 867 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 868 if (!mhp) { 869 ret = -ENOMEM; 870 goto err; 871 } 872 873 mhp->rhp = rhp; 874 ret = alloc_pbl(mhp, pbl_depth); 875 if (ret) 876 goto err1; 877 mhp->attr.pbl_size = pbl_depth; 878 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 879 mhp->attr.pbl_size, mhp->attr.pbl_addr); 880 if (ret) 881 goto err2; 882 mhp->attr.pdid = php->pdid; 883 mhp->attr.type = FW_RI_STAG_NSMR; 884 mhp->attr.stag = stag; 885 mhp->attr.state = 1; 886 mmid = (stag) >> 8; 887 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 888 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 889 ret = -ENOMEM; 890 goto err3; 891 } 892 893 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 894 return &(mhp->ibmr); 895 err3: 896 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 897 mhp->attr.pbl_addr); 898 err2: 899 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 900 mhp->attr.pbl_size << 3); 901 err1: 902 kfree(mhp); 903 err: 904 return ERR_PTR(ret); 905 } 906 907 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(struct ib_device *device, 908 int page_list_len) 909 { 910 struct c4iw_fr_page_list *c4pl; 911 struct c4iw_dev *dev = to_c4iw_dev(device); 912 dma_addr_t dma_addr; 913 int pll_len = roundup(page_list_len * sizeof(u64), 32); 914 915 c4pl = kmalloc(sizeof(*c4pl), GFP_KERNEL); 916 if (!c4pl) 917 return ERR_PTR(-ENOMEM); 918 919 c4pl->ibpl.page_list = dma_alloc_coherent(&dev->rdev.lldi.pdev->dev, 920 pll_len, &dma_addr, 921 GFP_KERNEL); 922 if (!c4pl->ibpl.page_list) { 923 kfree(c4pl); 924 return ERR_PTR(-ENOMEM); 925 } 926 dma_unmap_addr_set(c4pl, mapping, dma_addr); 927 c4pl->dma_addr = dma_addr; 928 c4pl->dev = dev; 929 c4pl->pll_len = pll_len; 930 931 PDBG("%s c4pl %p pll_len %u page_list %p dma_addr %pad\n", 932 __func__, c4pl, c4pl->pll_len, c4pl->ibpl.page_list, 933 &c4pl->dma_addr); 934 935 return &c4pl->ibpl; 936 } 937 938 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *ibpl) 939 { 940 struct c4iw_fr_page_list *c4pl = to_c4iw_fr_page_list(ibpl); 941 942 PDBG("%s c4pl %p pll_len %u page_list %p dma_addr %pad\n", 943 __func__, c4pl, c4pl->pll_len, c4pl->ibpl.page_list, 944 &c4pl->dma_addr); 945 946 dma_free_coherent(&c4pl->dev->rdev.lldi.pdev->dev, 947 c4pl->pll_len, 948 c4pl->ibpl.page_list, dma_unmap_addr(c4pl, mapping)); 949 kfree(c4pl); 950 } 951 952 int c4iw_dereg_mr(struct ib_mr *ib_mr) 953 { 954 struct c4iw_dev *rhp; 955 struct c4iw_mr *mhp; 956 u32 mmid; 957 958 PDBG("%s ib_mr %p\n", __func__, ib_mr); 959 /* There can be no memory windows */ 960 if (atomic_read(&ib_mr->usecnt)) 961 return -EINVAL; 962 963 mhp = to_c4iw_mr(ib_mr); 964 rhp = mhp->rhp; 965 mmid = mhp->attr.stag >> 8; 966 remove_handle(rhp, &rhp->mmidr, mmid); 967 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 968 mhp->attr.pbl_addr); 969 if (mhp->attr.pbl_size) 970 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 971 mhp->attr.pbl_size << 3); 972 if (mhp->kva) 973 kfree((void *) (unsigned long) mhp->kva); 974 if (mhp->umem) 975 ib_umem_release(mhp->umem); 976 PDBG("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp); 977 kfree(mhp); 978 return 0; 979 } 980