1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <linux/moduleparam.h> 35 #include <rdma/ib_umem.h> 36 #include <linux/atomic.h> 37 #include <rdma/ib_user_verbs.h> 38 39 #include "iw_cxgb4.h" 40 41 int use_dsgl = 1; 42 module_param(use_dsgl, int, 0644); 43 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1) (DEPRECATED)"); 44 45 #define T4_ULPTX_MIN_IO 32 46 #define C4IW_MAX_INLINE_SIZE 96 47 #define T4_ULPTX_MAX_DMA 1024 48 #define C4IW_INLINE_THRESHOLD 128 49 50 static int inline_threshold = C4IW_INLINE_THRESHOLD; 51 module_param(inline_threshold, int, 0644); 52 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)"); 53 54 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length) 55 { 56 return (is_t4(dev->rdev.lldi.adapter_type) || 57 is_t5(dev->rdev.lldi.adapter_type)) && 58 length >= 8*1024*1024*1024ULL; 59 } 60 61 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, 62 u32 len, dma_addr_t data, 63 int wait, struct sk_buff *skb) 64 { 65 struct ulp_mem_io *req; 66 struct ulptx_sgl *sgl; 67 u8 wr_len; 68 int ret = 0; 69 struct c4iw_wr_wait wr_wait; 70 71 addr &= 0x7FFFFFF; 72 73 if (wait) 74 c4iw_init_wr_wait(&wr_wait); 75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16); 76 77 if (!skb) { 78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); 79 if (!skb) 80 return -ENOMEM; 81 } 82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 83 84 req = (struct ulp_mem_io *)__skb_put(skb, wr_len); 85 memset(req, 0, wr_len); 86 INIT_ULPTX_WR(req, wr_len, 0, 0); 87 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 88 (wait ? FW_WR_COMPL_F : 0)); 89 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L; 90 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 91 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) | 92 T5_ULP_MEMIO_ORDER_V(1) | 93 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0])); 94 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5)); 95 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16)); 96 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr)); 97 98 sgl = (struct ulptx_sgl *)(req + 1); 99 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 100 ULPTX_NSGE_V(1)); 101 sgl->len0 = cpu_to_be32(len); 102 sgl->addr0 = cpu_to_be64(data); 103 104 ret = c4iw_ofld_send(rdev, skb); 105 if (ret) 106 return ret; 107 if (wait) 108 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 109 return ret; 110 } 111 112 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, 113 void *data, struct sk_buff *skb) 114 { 115 struct ulp_mem_io *req; 116 struct ulptx_idata *sc; 117 u8 wr_len, *to_dp, *from_dp; 118 int copy_len, num_wqe, i, ret = 0; 119 struct c4iw_wr_wait wr_wait; 120 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE)); 121 122 if (is_t4(rdev->lldi.adapter_type)) 123 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F); 124 else 125 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F); 126 127 addr &= 0x7FFFFFF; 128 pr_debug("%s addr 0x%x len %u\n", __func__, addr, len); 129 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 130 c4iw_init_wr_wait(&wr_wait); 131 for (i = 0; i < num_wqe; i++) { 132 133 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE : 134 len; 135 wr_len = roundup(sizeof *req + sizeof *sc + 136 roundup(copy_len, T4_ULPTX_MIN_IO), 16); 137 138 if (!skb) { 139 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); 140 if (!skb) 141 return -ENOMEM; 142 } 143 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 144 145 req = (struct ulp_mem_io *)__skb_put(skb, wr_len); 146 memset(req, 0, wr_len); 147 INIT_ULPTX_WR(req, wr_len, 0, 0); 148 149 if (i == (num_wqe-1)) { 150 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 151 FW_WR_COMPL_F); 152 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait; 153 } else 154 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR)); 155 req->wr.wr_mid = cpu_to_be32( 156 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 157 158 req->cmd = cmd; 159 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V( 160 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); 161 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 162 16)); 163 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3)); 164 165 sc = (struct ulptx_idata *)(req + 1); 166 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM)); 167 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO)); 168 169 to_dp = (u8 *)(sc + 1); 170 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE; 171 if (data) 172 memcpy(to_dp, from_dp, copy_len); 173 else 174 memset(to_dp, 0, copy_len); 175 if (copy_len % T4_ULPTX_MIN_IO) 176 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 177 (copy_len % T4_ULPTX_MIN_IO)); 178 ret = c4iw_ofld_send(rdev, skb); 179 skb = NULL; 180 if (ret) 181 return ret; 182 len -= C4IW_MAX_INLINE_SIZE; 183 } 184 185 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 186 return ret; 187 } 188 189 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, 190 void *data, struct sk_buff *skb) 191 { 192 u32 remain = len; 193 u32 dmalen; 194 int ret = 0; 195 dma_addr_t daddr; 196 dma_addr_t save; 197 198 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE); 199 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr)) 200 return -1; 201 save = daddr; 202 203 while (remain > inline_threshold) { 204 if (remain < T4_ULPTX_MAX_DMA) { 205 if (remain & ~T4_ULPTX_MIN_IO) 206 dmalen = remain & ~(T4_ULPTX_MIN_IO-1); 207 else 208 dmalen = remain; 209 } else 210 dmalen = T4_ULPTX_MAX_DMA; 211 remain -= dmalen; 212 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr, 213 !remain, skb); 214 if (ret) 215 goto out; 216 addr += dmalen >> 5; 217 data += dmalen; 218 daddr += dmalen; 219 } 220 if (remain) 221 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb); 222 out: 223 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE); 224 return ret; 225 } 226 227 /* 228 * write len bytes of data into addr (32B aligned address) 229 * If data is NULL, clear len byte of memory to zero. 230 */ 231 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, 232 void *data, struct sk_buff *skb) 233 { 234 if (rdev->lldi.ulptx_memwrite_dsgl && use_dsgl) { 235 if (len > inline_threshold) { 236 if (_c4iw_write_mem_dma(rdev, addr, len, data, skb)) { 237 pr_warn_ratelimited("%s: dma map failure (non fatal)\n", 238 pci_name(rdev->lldi.pdev)); 239 return _c4iw_write_mem_inline(rdev, addr, len, 240 data, skb); 241 } else { 242 return 0; 243 } 244 } else 245 return _c4iw_write_mem_inline(rdev, addr, 246 len, data, skb); 247 } else 248 return _c4iw_write_mem_inline(rdev, addr, len, data, skb); 249 } 250 251 /* 252 * Build and write a TPT entry. 253 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, 254 * pbl_size and pbl_addr 255 * OUT: stag index 256 */ 257 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, 258 u32 *stag, u8 stag_state, u32 pdid, 259 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 260 int bind_enabled, u32 zbva, u64 to, 261 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr, 262 struct sk_buff *skb) 263 { 264 int err; 265 struct fw_ri_tpte tpt; 266 u32 stag_idx; 267 static atomic_t key; 268 269 if (c4iw_fatal_error(rdev)) 270 return -EIO; 271 272 stag_state = stag_state > 0; 273 stag_idx = (*stag) >> 8; 274 275 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) { 276 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table); 277 if (!stag_idx) { 278 mutex_lock(&rdev->stats.lock); 279 rdev->stats.stag.fail++; 280 mutex_unlock(&rdev->stats.lock); 281 return -ENOMEM; 282 } 283 mutex_lock(&rdev->stats.lock); 284 rdev->stats.stag.cur += 32; 285 if (rdev->stats.stag.cur > rdev->stats.stag.max) 286 rdev->stats.stag.max = rdev->stats.stag.cur; 287 mutex_unlock(&rdev->stats.lock); 288 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 289 } 290 pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n", 291 __func__, stag_state, type, pdid, stag_idx); 292 293 /* write TPT entry */ 294 if (reset_tpt_entry) 295 memset(&tpt, 0, sizeof(tpt)); 296 else { 297 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 298 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) | 299 FW_RI_TPTE_STAGSTATE_V(stag_state) | 300 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid)); 301 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) | 302 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) | 303 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO : 304 FW_RI_VA_BASED_TO))| 305 FW_RI_TPTE_PS_V(page_size)); 306 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32( 307 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3)); 308 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL)); 309 tpt.va_hi = cpu_to_be32((u32)(to >> 32)); 310 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL)); 311 tpt.dca_mwbcnt_pstag = cpu_to_be32(0); 312 tpt.len_hi = cpu_to_be32((u32)(len >> 32)); 313 } 314 err = write_adapter_mem(rdev, stag_idx + 315 (rdev->lldi.vr->stag.start >> 5), 316 sizeof(tpt), &tpt, skb); 317 318 if (reset_tpt_entry) { 319 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 320 mutex_lock(&rdev->stats.lock); 321 rdev->stats.stag.cur -= 32; 322 mutex_unlock(&rdev->stats.lock); 323 } 324 return err; 325 } 326 327 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 328 u32 pbl_addr, u32 pbl_size) 329 { 330 int err; 331 332 pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n", 333 __func__, pbl_addr, rdev->lldi.vr->pbl.start, 334 pbl_size); 335 336 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL); 337 return err; 338 } 339 340 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 341 u32 pbl_addr, struct sk_buff *skb) 342 { 343 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 344 pbl_size, pbl_addr, skb); 345 } 346 347 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid) 348 { 349 *stag = T4_STAG_UNSET; 350 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 351 0UL, 0, 0, 0, 0, NULL); 352 } 353 354 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag, 355 struct sk_buff *skb) 356 { 357 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 358 0, skb); 359 } 360 361 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 362 u32 pbl_size, u32 pbl_addr) 363 { 364 *stag = T4_STAG_UNSET; 365 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 366 0UL, 0, 0, pbl_size, pbl_addr, NULL); 367 } 368 369 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 370 { 371 u32 mmid; 372 373 mhp->attr.state = 1; 374 mhp->attr.stag = stag; 375 mmid = stag >> 8; 376 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 377 pr_debug("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp); 378 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid); 379 } 380 381 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 382 struct c4iw_mr *mhp, int shift) 383 { 384 u32 stag = T4_STAG_UNSET; 385 int ret; 386 387 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 388 FW_RI_STAG_NSMR, mhp->attr.len ? 389 mhp->attr.perms : 0, 390 mhp->attr.mw_bind_enable, mhp->attr.zbva, 391 mhp->attr.va_fbo, mhp->attr.len ? 392 mhp->attr.len : -1, shift - 12, 393 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL); 394 if (ret) 395 return ret; 396 397 ret = finish_mem_reg(mhp, stag); 398 if (ret) { 399 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 400 mhp->attr.pbl_addr, mhp->dereg_skb); 401 mhp->dereg_skb = NULL; 402 } 403 return ret; 404 } 405 406 static int alloc_pbl(struct c4iw_mr *mhp, int npages) 407 { 408 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, 409 npages << 3); 410 411 if (!mhp->attr.pbl_addr) 412 return -ENOMEM; 413 414 mhp->attr.pbl_size = npages; 415 416 return 0; 417 } 418 419 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 420 { 421 struct c4iw_dev *rhp; 422 struct c4iw_pd *php; 423 struct c4iw_mr *mhp; 424 int ret; 425 u32 stag = T4_STAG_UNSET; 426 427 pr_debug("%s ib_pd %p\n", __func__, pd); 428 php = to_c4iw_pd(pd); 429 rhp = php->rhp; 430 431 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 432 if (!mhp) 433 return ERR_PTR(-ENOMEM); 434 435 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 436 if (!mhp->dereg_skb) { 437 ret = -ENOMEM; 438 goto err0; 439 } 440 441 mhp->rhp = rhp; 442 mhp->attr.pdid = php->pdid; 443 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 444 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND; 445 mhp->attr.zbva = 0; 446 mhp->attr.va_fbo = 0; 447 mhp->attr.page_size = 0; 448 mhp->attr.len = ~0ULL; 449 mhp->attr.pbl_size = 0; 450 451 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 452 FW_RI_STAG_NSMR, mhp->attr.perms, 453 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0, 454 NULL); 455 if (ret) 456 goto err1; 457 458 ret = finish_mem_reg(mhp, stag); 459 if (ret) 460 goto err2; 461 return &mhp->ibmr; 462 err2: 463 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 464 mhp->attr.pbl_addr, mhp->dereg_skb); 465 err1: 466 kfree_skb(mhp->dereg_skb); 467 err0: 468 kfree(mhp); 469 return ERR_PTR(ret); 470 } 471 472 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 473 u64 virt, int acc, struct ib_udata *udata) 474 { 475 __be64 *pages; 476 int shift, n, len; 477 int i, k, entry; 478 int err = 0; 479 struct scatterlist *sg; 480 struct c4iw_dev *rhp; 481 struct c4iw_pd *php; 482 struct c4iw_mr *mhp; 483 484 pr_debug("%s ib_pd %p\n", __func__, pd); 485 486 if (length == ~0ULL) 487 return ERR_PTR(-EINVAL); 488 489 if ((length + start) < start) 490 return ERR_PTR(-EINVAL); 491 492 php = to_c4iw_pd(pd); 493 rhp = php->rhp; 494 495 if (mr_exceeds_hw_limits(rhp, length)) 496 return ERR_PTR(-EINVAL); 497 498 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 499 if (!mhp) 500 return ERR_PTR(-ENOMEM); 501 502 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 503 if (!mhp->dereg_skb) { 504 kfree(mhp); 505 return ERR_PTR(-ENOMEM); 506 } 507 508 mhp->rhp = rhp; 509 510 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0); 511 if (IS_ERR(mhp->umem)) { 512 err = PTR_ERR(mhp->umem); 513 kfree_skb(mhp->dereg_skb); 514 kfree(mhp); 515 return ERR_PTR(err); 516 } 517 518 shift = mhp->umem->page_shift; 519 520 n = mhp->umem->nmap; 521 err = alloc_pbl(mhp, n); 522 if (err) 523 goto err; 524 525 pages = (__be64 *) __get_free_page(GFP_KERNEL); 526 if (!pages) { 527 err = -ENOMEM; 528 goto err_pbl; 529 } 530 531 i = n = 0; 532 533 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) { 534 len = sg_dma_len(sg) >> shift; 535 for (k = 0; k < len; ++k) { 536 pages[i++] = cpu_to_be64(sg_dma_address(sg) + 537 (k << shift)); 538 if (i == PAGE_SIZE / sizeof *pages) { 539 err = write_pbl(&mhp->rhp->rdev, 540 pages, 541 mhp->attr.pbl_addr + (n << 3), i); 542 if (err) 543 goto pbl_done; 544 n += i; 545 i = 0; 546 } 547 } 548 } 549 550 if (i) 551 err = write_pbl(&mhp->rhp->rdev, pages, 552 mhp->attr.pbl_addr + (n << 3), i); 553 554 pbl_done: 555 free_page((unsigned long) pages); 556 if (err) 557 goto err_pbl; 558 559 mhp->attr.pdid = php->pdid; 560 mhp->attr.zbva = 0; 561 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 562 mhp->attr.va_fbo = virt; 563 mhp->attr.page_size = shift - 12; 564 mhp->attr.len = length; 565 566 err = register_mem(rhp, php, mhp, shift); 567 if (err) 568 goto err_pbl; 569 570 return &mhp->ibmr; 571 572 err_pbl: 573 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 574 mhp->attr.pbl_size << 3); 575 576 err: 577 ib_umem_release(mhp->umem); 578 kfree_skb(mhp->dereg_skb); 579 kfree(mhp); 580 return ERR_PTR(err); 581 } 582 583 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 584 struct ib_udata *udata) 585 { 586 struct c4iw_dev *rhp; 587 struct c4iw_pd *php; 588 struct c4iw_mw *mhp; 589 u32 mmid; 590 u32 stag = 0; 591 int ret; 592 593 if (type != IB_MW_TYPE_1) 594 return ERR_PTR(-EINVAL); 595 596 php = to_c4iw_pd(pd); 597 rhp = php->rhp; 598 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 599 if (!mhp) 600 return ERR_PTR(-ENOMEM); 601 602 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 603 if (!mhp->dereg_skb) { 604 ret = -ENOMEM; 605 goto free_mhp; 606 } 607 608 ret = allocate_window(&rhp->rdev, &stag, php->pdid); 609 if (ret) 610 goto free_skb; 611 mhp->rhp = rhp; 612 mhp->attr.pdid = php->pdid; 613 mhp->attr.type = FW_RI_STAG_MW; 614 mhp->attr.stag = stag; 615 mmid = (stag) >> 8; 616 mhp->ibmw.rkey = stag; 617 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 618 ret = -ENOMEM; 619 goto dealloc_win; 620 } 621 pr_debug("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 622 return &(mhp->ibmw); 623 624 dealloc_win: 625 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb); 626 free_skb: 627 kfree_skb(mhp->dereg_skb); 628 free_mhp: 629 kfree(mhp); 630 return ERR_PTR(ret); 631 } 632 633 int c4iw_dealloc_mw(struct ib_mw *mw) 634 { 635 struct c4iw_dev *rhp; 636 struct c4iw_mw *mhp; 637 u32 mmid; 638 639 mhp = to_c4iw_mw(mw); 640 rhp = mhp->rhp; 641 mmid = (mw->rkey) >> 8; 642 remove_handle(rhp, &rhp->mmidr, mmid); 643 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb); 644 kfree_skb(mhp->dereg_skb); 645 kfree(mhp); 646 pr_debug("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp); 647 return 0; 648 } 649 650 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, 651 enum ib_mr_type mr_type, 652 u32 max_num_sg) 653 { 654 struct c4iw_dev *rhp; 655 struct c4iw_pd *php; 656 struct c4iw_mr *mhp; 657 u32 mmid; 658 u32 stag = 0; 659 int ret = 0; 660 int length = roundup(max_num_sg * sizeof(u64), 32); 661 662 php = to_c4iw_pd(pd); 663 rhp = php->rhp; 664 665 if (mr_type != IB_MR_TYPE_MEM_REG || 666 max_num_sg > t4_max_fr_depth(&rhp->rdev.lldi.ulptx_memwrite_dsgl && 667 use_dsgl)) 668 return ERR_PTR(-EINVAL); 669 670 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 671 if (!mhp) { 672 ret = -ENOMEM; 673 goto err; 674 } 675 676 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev, 677 length, &mhp->mpl_addr, GFP_KERNEL); 678 if (!mhp->mpl) { 679 ret = -ENOMEM; 680 goto err_mpl; 681 } 682 mhp->max_mpl_len = length; 683 684 mhp->rhp = rhp; 685 ret = alloc_pbl(mhp, max_num_sg); 686 if (ret) 687 goto err1; 688 mhp->attr.pbl_size = max_num_sg; 689 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 690 mhp->attr.pbl_size, mhp->attr.pbl_addr); 691 if (ret) 692 goto err2; 693 mhp->attr.pdid = php->pdid; 694 mhp->attr.type = FW_RI_STAG_NSMR; 695 mhp->attr.stag = stag; 696 mhp->attr.state = 0; 697 mmid = (stag) >> 8; 698 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 699 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 700 ret = -ENOMEM; 701 goto err3; 702 } 703 704 pr_debug("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 705 return &(mhp->ibmr); 706 err3: 707 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 708 mhp->attr.pbl_addr, mhp->dereg_skb); 709 err2: 710 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 711 mhp->attr.pbl_size << 3); 712 err1: 713 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 714 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 715 err_mpl: 716 kfree(mhp); 717 err: 718 return ERR_PTR(ret); 719 } 720 721 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr) 722 { 723 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 724 725 if (unlikely(mhp->mpl_len == mhp->max_mpl_len)) 726 return -ENOMEM; 727 728 mhp->mpl[mhp->mpl_len++] = addr; 729 730 return 0; 731 } 732 733 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 734 unsigned int *sg_offset) 735 { 736 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 737 738 mhp->mpl_len = 0; 739 740 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page); 741 } 742 743 int c4iw_dereg_mr(struct ib_mr *ib_mr) 744 { 745 struct c4iw_dev *rhp; 746 struct c4iw_mr *mhp; 747 u32 mmid; 748 749 pr_debug("%s ib_mr %p\n", __func__, ib_mr); 750 751 mhp = to_c4iw_mr(ib_mr); 752 rhp = mhp->rhp; 753 mmid = mhp->attr.stag >> 8; 754 remove_handle(rhp, &rhp->mmidr, mmid); 755 if (mhp->mpl) 756 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 757 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 758 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 759 mhp->attr.pbl_addr, mhp->dereg_skb); 760 if (mhp->attr.pbl_size) 761 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 762 mhp->attr.pbl_size << 3); 763 if (mhp->kva) 764 kfree((void *) (unsigned long) mhp->kva); 765 if (mhp->umem) 766 ib_umem_release(mhp->umem); 767 pr_debug("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp); 768 kfree(mhp); 769 return 0; 770 } 771 772 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey) 773 { 774 struct c4iw_mr *mhp; 775 unsigned long flags; 776 777 spin_lock_irqsave(&rhp->lock, flags); 778 mhp = get_mhp(rhp, rkey >> 8); 779 if (mhp) 780 mhp->attr.state = 0; 781 spin_unlock_irqrestore(&rhp->lock, flags); 782 } 783