1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <linux/moduleparam.h> 35 #include <rdma/ib_umem.h> 36 #include <linux/atomic.h> 37 #include <rdma/ib_user_verbs.h> 38 39 #include "iw_cxgb4.h" 40 41 int use_dsgl = 1; 42 module_param(use_dsgl, int, 0644); 43 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1) (DEPRECATED)"); 44 45 #define T4_ULPTX_MIN_IO 32 46 #define C4IW_MAX_INLINE_SIZE 96 47 #define T4_ULPTX_MAX_DMA 1024 48 #define C4IW_INLINE_THRESHOLD 128 49 50 static int inline_threshold = C4IW_INLINE_THRESHOLD; 51 module_param(inline_threshold, int, 0644); 52 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)"); 53 54 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length) 55 { 56 return (is_t4(dev->rdev.lldi.adapter_type) || 57 is_t5(dev->rdev.lldi.adapter_type)) && 58 length >= 8*1024*1024*1024ULL; 59 } 60 61 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, 62 u32 len, dma_addr_t data, 63 int wait, struct sk_buff *skb) 64 { 65 struct ulp_mem_io *req; 66 struct ulptx_sgl *sgl; 67 u8 wr_len; 68 int ret = 0; 69 struct c4iw_wr_wait wr_wait; 70 71 addr &= 0x7FFFFFF; 72 73 if (wait) 74 c4iw_init_wr_wait(&wr_wait); 75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16); 76 77 if (!skb) { 78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); 79 if (!skb) 80 return -ENOMEM; 81 } 82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 83 84 req = __skb_put_zero(skb, wr_len); 85 INIT_ULPTX_WR(req, wr_len, 0, 0); 86 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 87 (wait ? FW_WR_COMPL_F : 0)); 88 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L; 89 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 90 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) | 91 T5_ULP_MEMIO_ORDER_V(1) | 92 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0])); 93 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5)); 94 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16)); 95 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr)); 96 97 sgl = (struct ulptx_sgl *)(req + 1); 98 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 99 ULPTX_NSGE_V(1)); 100 sgl->len0 = cpu_to_be32(len); 101 sgl->addr0 = cpu_to_be64(data); 102 103 ret = c4iw_ofld_send(rdev, skb); 104 if (ret) 105 return ret; 106 if (wait) 107 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 108 return ret; 109 } 110 111 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, 112 void *data, struct sk_buff *skb) 113 { 114 struct ulp_mem_io *req; 115 struct ulptx_idata *sc; 116 u8 wr_len, *to_dp, *from_dp; 117 int copy_len, num_wqe, i, ret = 0; 118 struct c4iw_wr_wait wr_wait; 119 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE)); 120 121 if (is_t4(rdev->lldi.adapter_type)) 122 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F); 123 else 124 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F); 125 126 addr &= 0x7FFFFFF; 127 pr_debug("%s addr 0x%x len %u\n", __func__, addr, len); 128 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 129 c4iw_init_wr_wait(&wr_wait); 130 for (i = 0; i < num_wqe; i++) { 131 132 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE : 133 len; 134 wr_len = roundup(sizeof *req + sizeof *sc + 135 roundup(copy_len, T4_ULPTX_MIN_IO), 16); 136 137 if (!skb) { 138 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); 139 if (!skb) 140 return -ENOMEM; 141 } 142 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 143 144 req = __skb_put_zero(skb, wr_len); 145 INIT_ULPTX_WR(req, wr_len, 0, 0); 146 147 if (i == (num_wqe-1)) { 148 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 149 FW_WR_COMPL_F); 150 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait; 151 } else 152 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR)); 153 req->wr.wr_mid = cpu_to_be32( 154 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 155 156 req->cmd = cmd; 157 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V( 158 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); 159 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 160 16)); 161 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3)); 162 163 sc = (struct ulptx_idata *)(req + 1); 164 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM)); 165 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO)); 166 167 to_dp = (u8 *)(sc + 1); 168 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE; 169 if (data) 170 memcpy(to_dp, from_dp, copy_len); 171 else 172 memset(to_dp, 0, copy_len); 173 if (copy_len % T4_ULPTX_MIN_IO) 174 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 175 (copy_len % T4_ULPTX_MIN_IO)); 176 ret = c4iw_ofld_send(rdev, skb); 177 skb = NULL; 178 if (ret) 179 return ret; 180 len -= C4IW_MAX_INLINE_SIZE; 181 } 182 183 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 184 return ret; 185 } 186 187 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, 188 void *data, struct sk_buff *skb) 189 { 190 u32 remain = len; 191 u32 dmalen; 192 int ret = 0; 193 dma_addr_t daddr; 194 dma_addr_t save; 195 196 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE); 197 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr)) 198 return -1; 199 save = daddr; 200 201 while (remain > inline_threshold) { 202 if (remain < T4_ULPTX_MAX_DMA) { 203 if (remain & ~T4_ULPTX_MIN_IO) 204 dmalen = remain & ~(T4_ULPTX_MIN_IO-1); 205 else 206 dmalen = remain; 207 } else 208 dmalen = T4_ULPTX_MAX_DMA; 209 remain -= dmalen; 210 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr, 211 !remain, skb); 212 if (ret) 213 goto out; 214 addr += dmalen >> 5; 215 data += dmalen; 216 daddr += dmalen; 217 } 218 if (remain) 219 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb); 220 out: 221 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE); 222 return ret; 223 } 224 225 /* 226 * write len bytes of data into addr (32B aligned address) 227 * If data is NULL, clear len byte of memory to zero. 228 */ 229 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, 230 void *data, struct sk_buff *skb) 231 { 232 if (rdev->lldi.ulptx_memwrite_dsgl && use_dsgl) { 233 if (len > inline_threshold) { 234 if (_c4iw_write_mem_dma(rdev, addr, len, data, skb)) { 235 pr_warn_ratelimited("%s: dma map failure (non fatal)\n", 236 pci_name(rdev->lldi.pdev)); 237 return _c4iw_write_mem_inline(rdev, addr, len, 238 data, skb); 239 } else { 240 return 0; 241 } 242 } else 243 return _c4iw_write_mem_inline(rdev, addr, 244 len, data, skb); 245 } else 246 return _c4iw_write_mem_inline(rdev, addr, len, data, skb); 247 } 248 249 /* 250 * Build and write a TPT entry. 251 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, 252 * pbl_size and pbl_addr 253 * OUT: stag index 254 */ 255 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, 256 u32 *stag, u8 stag_state, u32 pdid, 257 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 258 int bind_enabled, u32 zbva, u64 to, 259 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr, 260 struct sk_buff *skb) 261 { 262 int err; 263 struct fw_ri_tpte tpt; 264 u32 stag_idx; 265 static atomic_t key; 266 267 if (c4iw_fatal_error(rdev)) 268 return -EIO; 269 270 stag_state = stag_state > 0; 271 stag_idx = (*stag) >> 8; 272 273 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) { 274 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table); 275 if (!stag_idx) { 276 mutex_lock(&rdev->stats.lock); 277 rdev->stats.stag.fail++; 278 mutex_unlock(&rdev->stats.lock); 279 return -ENOMEM; 280 } 281 mutex_lock(&rdev->stats.lock); 282 rdev->stats.stag.cur += 32; 283 if (rdev->stats.stag.cur > rdev->stats.stag.max) 284 rdev->stats.stag.max = rdev->stats.stag.cur; 285 mutex_unlock(&rdev->stats.lock); 286 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 287 } 288 pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n", 289 __func__, stag_state, type, pdid, stag_idx); 290 291 /* write TPT entry */ 292 if (reset_tpt_entry) 293 memset(&tpt, 0, sizeof(tpt)); 294 else { 295 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 296 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) | 297 FW_RI_TPTE_STAGSTATE_V(stag_state) | 298 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid)); 299 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) | 300 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) | 301 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO : 302 FW_RI_VA_BASED_TO))| 303 FW_RI_TPTE_PS_V(page_size)); 304 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32( 305 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3)); 306 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL)); 307 tpt.va_hi = cpu_to_be32((u32)(to >> 32)); 308 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL)); 309 tpt.dca_mwbcnt_pstag = cpu_to_be32(0); 310 tpt.len_hi = cpu_to_be32((u32)(len >> 32)); 311 } 312 err = write_adapter_mem(rdev, stag_idx + 313 (rdev->lldi.vr->stag.start >> 5), 314 sizeof(tpt), &tpt, skb); 315 316 if (reset_tpt_entry) { 317 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 318 mutex_lock(&rdev->stats.lock); 319 rdev->stats.stag.cur -= 32; 320 mutex_unlock(&rdev->stats.lock); 321 } 322 return err; 323 } 324 325 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 326 u32 pbl_addr, u32 pbl_size) 327 { 328 int err; 329 330 pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n", 331 __func__, pbl_addr, rdev->lldi.vr->pbl.start, 332 pbl_size); 333 334 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL); 335 return err; 336 } 337 338 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 339 u32 pbl_addr, struct sk_buff *skb) 340 { 341 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 342 pbl_size, pbl_addr, skb); 343 } 344 345 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid) 346 { 347 *stag = T4_STAG_UNSET; 348 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 349 0UL, 0, 0, 0, 0, NULL); 350 } 351 352 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag, 353 struct sk_buff *skb) 354 { 355 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 356 0, skb); 357 } 358 359 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 360 u32 pbl_size, u32 pbl_addr) 361 { 362 *stag = T4_STAG_UNSET; 363 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 364 0UL, 0, 0, pbl_size, pbl_addr, NULL); 365 } 366 367 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 368 { 369 u32 mmid; 370 371 mhp->attr.state = 1; 372 mhp->attr.stag = stag; 373 mmid = stag >> 8; 374 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 375 pr_debug("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp); 376 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid); 377 } 378 379 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 380 struct c4iw_mr *mhp, int shift) 381 { 382 u32 stag = T4_STAG_UNSET; 383 int ret; 384 385 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 386 FW_RI_STAG_NSMR, mhp->attr.len ? 387 mhp->attr.perms : 0, 388 mhp->attr.mw_bind_enable, mhp->attr.zbva, 389 mhp->attr.va_fbo, mhp->attr.len ? 390 mhp->attr.len : -1, shift - 12, 391 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL); 392 if (ret) 393 return ret; 394 395 ret = finish_mem_reg(mhp, stag); 396 if (ret) { 397 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 398 mhp->attr.pbl_addr, mhp->dereg_skb); 399 mhp->dereg_skb = NULL; 400 } 401 return ret; 402 } 403 404 static int alloc_pbl(struct c4iw_mr *mhp, int npages) 405 { 406 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, 407 npages << 3); 408 409 if (!mhp->attr.pbl_addr) 410 return -ENOMEM; 411 412 mhp->attr.pbl_size = npages; 413 414 return 0; 415 } 416 417 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 418 { 419 struct c4iw_dev *rhp; 420 struct c4iw_pd *php; 421 struct c4iw_mr *mhp; 422 int ret; 423 u32 stag = T4_STAG_UNSET; 424 425 pr_debug("%s ib_pd %p\n", __func__, pd); 426 php = to_c4iw_pd(pd); 427 rhp = php->rhp; 428 429 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 430 if (!mhp) 431 return ERR_PTR(-ENOMEM); 432 433 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 434 if (!mhp->dereg_skb) { 435 ret = -ENOMEM; 436 goto err0; 437 } 438 439 mhp->rhp = rhp; 440 mhp->attr.pdid = php->pdid; 441 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 442 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND; 443 mhp->attr.zbva = 0; 444 mhp->attr.va_fbo = 0; 445 mhp->attr.page_size = 0; 446 mhp->attr.len = ~0ULL; 447 mhp->attr.pbl_size = 0; 448 449 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 450 FW_RI_STAG_NSMR, mhp->attr.perms, 451 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0, 452 NULL); 453 if (ret) 454 goto err1; 455 456 ret = finish_mem_reg(mhp, stag); 457 if (ret) 458 goto err2; 459 return &mhp->ibmr; 460 err2: 461 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 462 mhp->attr.pbl_addr, mhp->dereg_skb); 463 err1: 464 kfree_skb(mhp->dereg_skb); 465 err0: 466 kfree(mhp); 467 return ERR_PTR(ret); 468 } 469 470 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 471 u64 virt, int acc, struct ib_udata *udata) 472 { 473 __be64 *pages; 474 int shift, n, len; 475 int i, k, entry; 476 int err = 0; 477 struct scatterlist *sg; 478 struct c4iw_dev *rhp; 479 struct c4iw_pd *php; 480 struct c4iw_mr *mhp; 481 482 pr_debug("%s ib_pd %p\n", __func__, pd); 483 484 if (length == ~0ULL) 485 return ERR_PTR(-EINVAL); 486 487 if ((length + start) < start) 488 return ERR_PTR(-EINVAL); 489 490 php = to_c4iw_pd(pd); 491 rhp = php->rhp; 492 493 if (mr_exceeds_hw_limits(rhp, length)) 494 return ERR_PTR(-EINVAL); 495 496 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 497 if (!mhp) 498 return ERR_PTR(-ENOMEM); 499 500 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 501 if (!mhp->dereg_skb) { 502 kfree(mhp); 503 return ERR_PTR(-ENOMEM); 504 } 505 506 mhp->rhp = rhp; 507 508 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0); 509 if (IS_ERR(mhp->umem)) { 510 err = PTR_ERR(mhp->umem); 511 kfree_skb(mhp->dereg_skb); 512 kfree(mhp); 513 return ERR_PTR(err); 514 } 515 516 shift = mhp->umem->page_shift; 517 518 n = mhp->umem->nmap; 519 err = alloc_pbl(mhp, n); 520 if (err) 521 goto err; 522 523 pages = (__be64 *) __get_free_page(GFP_KERNEL); 524 if (!pages) { 525 err = -ENOMEM; 526 goto err_pbl; 527 } 528 529 i = n = 0; 530 531 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) { 532 len = sg_dma_len(sg) >> shift; 533 for (k = 0; k < len; ++k) { 534 pages[i++] = cpu_to_be64(sg_dma_address(sg) + 535 (k << shift)); 536 if (i == PAGE_SIZE / sizeof *pages) { 537 err = write_pbl(&mhp->rhp->rdev, 538 pages, 539 mhp->attr.pbl_addr + (n << 3), i); 540 if (err) 541 goto pbl_done; 542 n += i; 543 i = 0; 544 } 545 } 546 } 547 548 if (i) 549 err = write_pbl(&mhp->rhp->rdev, pages, 550 mhp->attr.pbl_addr + (n << 3), i); 551 552 pbl_done: 553 free_page((unsigned long) pages); 554 if (err) 555 goto err_pbl; 556 557 mhp->attr.pdid = php->pdid; 558 mhp->attr.zbva = 0; 559 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 560 mhp->attr.va_fbo = virt; 561 mhp->attr.page_size = shift - 12; 562 mhp->attr.len = length; 563 564 err = register_mem(rhp, php, mhp, shift); 565 if (err) 566 goto err_pbl; 567 568 return &mhp->ibmr; 569 570 err_pbl: 571 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 572 mhp->attr.pbl_size << 3); 573 574 err: 575 ib_umem_release(mhp->umem); 576 kfree_skb(mhp->dereg_skb); 577 kfree(mhp); 578 return ERR_PTR(err); 579 } 580 581 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 582 struct ib_udata *udata) 583 { 584 struct c4iw_dev *rhp; 585 struct c4iw_pd *php; 586 struct c4iw_mw *mhp; 587 u32 mmid; 588 u32 stag = 0; 589 int ret; 590 591 if (type != IB_MW_TYPE_1) 592 return ERR_PTR(-EINVAL); 593 594 php = to_c4iw_pd(pd); 595 rhp = php->rhp; 596 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 597 if (!mhp) 598 return ERR_PTR(-ENOMEM); 599 600 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 601 if (!mhp->dereg_skb) { 602 ret = -ENOMEM; 603 goto free_mhp; 604 } 605 606 ret = allocate_window(&rhp->rdev, &stag, php->pdid); 607 if (ret) 608 goto free_skb; 609 mhp->rhp = rhp; 610 mhp->attr.pdid = php->pdid; 611 mhp->attr.type = FW_RI_STAG_MW; 612 mhp->attr.stag = stag; 613 mmid = (stag) >> 8; 614 mhp->ibmw.rkey = stag; 615 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 616 ret = -ENOMEM; 617 goto dealloc_win; 618 } 619 pr_debug("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 620 return &(mhp->ibmw); 621 622 dealloc_win: 623 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb); 624 free_skb: 625 kfree_skb(mhp->dereg_skb); 626 free_mhp: 627 kfree(mhp); 628 return ERR_PTR(ret); 629 } 630 631 int c4iw_dealloc_mw(struct ib_mw *mw) 632 { 633 struct c4iw_dev *rhp; 634 struct c4iw_mw *mhp; 635 u32 mmid; 636 637 mhp = to_c4iw_mw(mw); 638 rhp = mhp->rhp; 639 mmid = (mw->rkey) >> 8; 640 remove_handle(rhp, &rhp->mmidr, mmid); 641 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb); 642 kfree_skb(mhp->dereg_skb); 643 kfree(mhp); 644 pr_debug("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp); 645 return 0; 646 } 647 648 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, 649 enum ib_mr_type mr_type, 650 u32 max_num_sg) 651 { 652 struct c4iw_dev *rhp; 653 struct c4iw_pd *php; 654 struct c4iw_mr *mhp; 655 u32 mmid; 656 u32 stag = 0; 657 int ret = 0; 658 int length = roundup(max_num_sg * sizeof(u64), 32); 659 660 php = to_c4iw_pd(pd); 661 rhp = php->rhp; 662 663 if (mr_type != IB_MR_TYPE_MEM_REG || 664 max_num_sg > t4_max_fr_depth(rhp->rdev.lldi.ulptx_memwrite_dsgl && 665 use_dsgl)) 666 return ERR_PTR(-EINVAL); 667 668 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 669 if (!mhp) { 670 ret = -ENOMEM; 671 goto err; 672 } 673 674 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev, 675 length, &mhp->mpl_addr, GFP_KERNEL); 676 if (!mhp->mpl) { 677 ret = -ENOMEM; 678 goto err_mpl; 679 } 680 mhp->max_mpl_len = length; 681 682 mhp->rhp = rhp; 683 ret = alloc_pbl(mhp, max_num_sg); 684 if (ret) 685 goto err1; 686 mhp->attr.pbl_size = max_num_sg; 687 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 688 mhp->attr.pbl_size, mhp->attr.pbl_addr); 689 if (ret) 690 goto err2; 691 mhp->attr.pdid = php->pdid; 692 mhp->attr.type = FW_RI_STAG_NSMR; 693 mhp->attr.stag = stag; 694 mhp->attr.state = 0; 695 mmid = (stag) >> 8; 696 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 697 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 698 ret = -ENOMEM; 699 goto err3; 700 } 701 702 pr_debug("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 703 return &(mhp->ibmr); 704 err3: 705 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 706 mhp->attr.pbl_addr, mhp->dereg_skb); 707 err2: 708 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 709 mhp->attr.pbl_size << 3); 710 err1: 711 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 712 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 713 err_mpl: 714 kfree(mhp); 715 err: 716 return ERR_PTR(ret); 717 } 718 719 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr) 720 { 721 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 722 723 if (unlikely(mhp->mpl_len == mhp->max_mpl_len)) 724 return -ENOMEM; 725 726 mhp->mpl[mhp->mpl_len++] = addr; 727 728 return 0; 729 } 730 731 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 732 unsigned int *sg_offset) 733 { 734 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 735 736 mhp->mpl_len = 0; 737 738 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page); 739 } 740 741 int c4iw_dereg_mr(struct ib_mr *ib_mr) 742 { 743 struct c4iw_dev *rhp; 744 struct c4iw_mr *mhp; 745 u32 mmid; 746 747 pr_debug("%s ib_mr %p\n", __func__, ib_mr); 748 749 mhp = to_c4iw_mr(ib_mr); 750 rhp = mhp->rhp; 751 mmid = mhp->attr.stag >> 8; 752 remove_handle(rhp, &rhp->mmidr, mmid); 753 if (mhp->mpl) 754 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 755 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 756 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 757 mhp->attr.pbl_addr, mhp->dereg_skb); 758 if (mhp->attr.pbl_size) 759 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 760 mhp->attr.pbl_size << 3); 761 if (mhp->kva) 762 kfree((void *) (unsigned long) mhp->kva); 763 if (mhp->umem) 764 ib_umem_release(mhp->umem); 765 pr_debug("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp); 766 kfree(mhp); 767 return 0; 768 } 769 770 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey) 771 { 772 struct c4iw_mr *mhp; 773 unsigned long flags; 774 775 spin_lock_irqsave(&rhp->lock, flags); 776 mhp = get_mhp(rhp, rkey >> 8); 777 if (mhp) 778 mhp->attr.state = 0; 779 spin_unlock_irqrestore(&rhp->lock, flags); 780 } 781